Display devices and electronic equipment

Abstract

The present invention provides a novel display device. The display device has a first layer, a second layer, and a third layer. Each of the first layer, the second layer, and the third layer is provided in a different layer. The first layer has a driving circuit and a functional circuit. The second layer has a pixel circuit. The third layer has a display element. The pixel circuit has a function for controlling the light emission of the display element. The driving circuit has a function for controlling the pixel circuit. The functional circuit has a function for controlling the driving circuit. The first layer has a first transistor that has a semiconductor layer having silicon in a channel forming region. The second layer has a second transistor that has a semiconductor layer having a metal oxide in a channel forming region.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a display device. Another aspect of the present invention relates to a method for manufacturing a display device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention disclosed herein include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving them, or methods for manufacturing them. [Background technology]

[0003] In recent years, there has been a growing demand for higher resolution display devices. Examples of devices requiring high-resolution displays include those for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR), and these are currently undergoing extensive development. Display devices used in these applications require both high resolution and miniaturization.

[0004] Examples of display devices include liquid crystal displays, organic EL (Electro-Luminescence) elements, light-emitting devices equipped with light-emitting elements such as LEDs, and electronic paper that displays information using electrophoretic methods.

[0005] For example, the basic structure of an organic EL element is one in which a layer containing a light-emitting organic compound is sandwiched between a pair of electrodes. By applying a voltage to this element, light emission can be obtained from the light-emitting organic compound. A display device to which such an organic EL element is applied does not require a backlight, which was necessary in liquid crystal display devices and the like, and thus can realize a thin, lightweight, high-contrast, and low-power consumption display device. For example, an example of a display device using an organic EL element is described in Patent Document 1. When high display quality is required, as in the display device of Patent Document 1, a display device with a high pixel count and high definition may be required.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] Devices for virtual reality and augmented reality require a display device with high display quality as shown in Patent Document 1. In this case, since the display is configured in a wearable housing such as glasses-type or goggle-type, miniaturization and weight reduction of the display device are important factors. In a wearable housing, for example, it is necessary to reduce the size of the display device to approximately 2 inches or less, 1 inch or less, etc.

[0008] In addition, a display device requires a drive circuit such as a gate driver or a source driver for driving pixels, or a functional circuit such as an application processor for generating a control signal or the like for performing display. In the case of a configuration in which a drive circuit and a functional circuit are provided separately in addition to a pixel circuit including a plurality of pixels, the wiring length for electrically connecting each circuit increases, and there is a risk that it becomes difficult to miniaturize and lighten the display device. Further, in the case of integrating and providing a drive circuit and a functional circuit in addition to a pixel circuit including a plurality of pixels, the circuit area increases due to the addition of the drive circuit and the functional circuit to the pixel circuit, and there is a risk that it becomes difficult to miniaturize and lighten the display device.

[0009] One aspect of the present invention aims to provide a display device that is miniaturized. Or, one aspect of the present invention aims to provide a display device that is lightened. Or, one aspect of the present invention aims to provide a display device with excellent display quality. Or, one aspect of the present invention aims to provide a novel display device.

[0010] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems can be extracted from the descriptions in the specification, drawings, claims, etc.

Means for Solving the Problems

[0011] One aspect of the present invention has a first layer, a second layer, and a third layer. The first layer, the second layer, and the third layer are provided in different layers respectively. The first layer has a drive circuit and a functional circuit. The second layer has a pixel circuit. The third layer has a display element. The pixel circuit has a function of controlling the light emission of the display element. The drive circuit has a function of controlling the pixel circuit. The functional circuit has a function of controlling the drive circuit. It is a display device.

[0012] One aspect of the present invention is a display device having a first layer, a second layer, and a third layer, the first layer, the second layer, and the third layer being provided on different layers, the first layer having a drive circuit and a function circuit, the second layer having a pixel circuit, the third layer having a display element, the first layer having a first transistor having a semiconductor layer with silicon in the channel formation region, the second layer having a second transistor having a semiconductor layer with a metal oxide in the channel formation region, the pixel circuit having a function to control the light emission of the display element, the drive circuit having a function to control the pixel circuit, and the function circuit having a function to control the drive circuit.

[0013] In one embodiment of the present invention, a display device having a metal oxide of In, element M (where M is Al, Ga, Y, or Sn), and Zn is preferred.

[0014] In one embodiment of the present invention, a display device is preferred in which the display element has an organic EL element, and the organic EL element is a display element processed by photolithography.

[0015] In one embodiment of the present invention, a display device having a drive circuit comprising a gate driver circuit and a source driver circuit is preferred.

[0016] In one embodiment of the present invention, a display device is preferred in which the pixel circuit is divided into a plurality of regions, one of which has a source driver circuit and a gate driver circuit, the source driver circuit has a plurality of source lines electrically connected, and the gate driver circuit has a plurality of gate lines electrically connected.

[0017] One aspect of the present invention is an electronic device comprising the display device described above, a fixing device, a pair of lenses, and a battery.

[0018] Further embodiments of the present invention are described in the following descriptions of embodiments and in the drawings. [Effects of the Invention]

[0019] One aspect of the present invention can provide a miniaturized display device. Alternatively, one aspect of the present invention can provide a lightweight display device. Alternatively, one aspect of the present invention can provide a display device with excellent display quality. Alternatively, one aspect of the present invention can provide a novel display device.

[0020] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawing]

[0021] Figures 1A and 1B illustrate an example of the configuration of a display device. Figures 2A and 2B illustrate examples of display device configurations. Figures 3A and 3B illustrate an example of a display device configuration. Figures 4A and 4B illustrate examples of the configuration of a display device. Figures 5A and 5B illustrate examples of display device configurations. Figures 6A to 6D illustrate examples of the configuration of a display device. Figures 7A to 7D illustrate examples of the configuration of a display device. Figure 8 illustrates an example of a display device configuration. Figures 9A and 9B illustrate an example of the configuration of a display device. Figure 10 illustrates an example of a display device configuration. Figure 11 illustrates an example of a display device configuration. Figures 12A to 12C illustrate examples of the configuration of a display device. Figure 13A is a diagram illustrating the classification of crystal structures. Figure 13B is a diagram illustrating the XRD spectrum of the CAAC-IGZO film. Figure 13C is a diagram illustrating the micro-electron diffraction pattern of the CAAC-IGZO film. Figures 14A to 14D illustrate examples of the configuration of a display element. Figures 15A to 15D illustrate examples of the configuration of a display element. Figures 16A and 16B illustrate examples of the configuration of a display element. Figures 17A and 17B are layout diagrams of a display device fabricated on a 12-inch wafer. Figures 18A to 18D illustrate examples of electronic device configurations. Figures 19A and 19B illustrate examples of electronic device configurations. [Modes for carrying out the invention]

[0022] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different forms, and that their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention shall not be construed as being limited to the contents of the following embodiments.

[0023] Furthermore, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings.

[0024] Furthermore, unless otherwise specified in this specification, off-current refers to the drain current when the transistor is in the off state (also called the non-conducting state or cutoff state). Unless otherwise specified, the off state in an n-channel transistor is defined as the voltage V between the gate and source. gs The threshold voltage V th Lower than (in p-channel transistors, V th This refers to a state that is higher than [a certain value].

[0025] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the active layer of a transistor, that metal oxide may be referred to as an oxide semiconductor. In other words, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0026] In this specification, devices fabricated using a metal mask or an FMM (Fine Metal Mask, a high-resolution metal mask) may be referred to as MM (Metal Mask) structured devices. Furthermore, in this specification, devices fabricated without using a metal mask or an FMM may be referred to as MML (Metal Maskless) structured devices.

[0027] (Embodiment 1) In the following section, an example of the configuration of a display device according to one aspect of the present invention will be described with reference to the drawings.

[0028] Figure 1A is a schematic perspective view of the display device 10.

[0029] The display device 10 has a substrate 11 and a substrate 12. The display device 10 has a display unit 13 which is composed of elements provided between the substrate 11 and the substrate 12. The display unit 13 is the area in the display device 10 that displays images. The display unit 13 is the area where pixels are provided, which are composed of pixel circuits and display elements connected to the pixel circuits.

[0030] In this specification, the term "element" may sometimes be replaced with "device." For example, display elements, light-emitting elements, and liquid crystal elements may be replaced with, for example, display devices, light-emitting devices, and liquid crystal devices.

[0031] The display device 10 receives various signals and power potentials from the outside via the terminal section 14, and can display information on the display section 13. Multiple layers are provided between the substrate 11 and the substrate 12, and each layer is provided with transistors for circuit operation or display elements that emit light. The multiple layers are provided with pixel circuits that have the function of controlling the light emission of the display elements, drive circuits that have the function of controlling the pixel circuits, functional circuits that have the function of controlling the drive circuits, and so on.

[0032] Figure 1B shows a schematic perspective view illustrating the configuration of each layer provided between substrate 11 and substrate 12.

[0033] A layer 20 is provided on the substrate 11. The layer 20 is provided with a drive circuit 30 and a functional circuit 40. The layer 20 has a transistor 21 (also called a Si transistor) having silicon in the channel formation region 22. The substrate 11 is, for example, a silicon substrate. A silicon substrate is preferred because it has higher thermal conductivity compared to a glass substrate.

[0034] The transistor 21 can be, for example, a transistor having single-crystal silicon in its channel formation region. In particular, using a transistor having single-crystal silicon in its channel formation region as the transistor provided in layer 20 allows for a large on-current of the transistor. Therefore, it is preferable because it allows the circuit of layer 20 to be driven at high speed. Furthermore, since Si transistors can be formed with microfabrication such as a channel length of 3 nm to 10 nm, they can be used in a display device 10 equipped with an accelerator such as a CPU or GPU, an application processor, etc.

[0035] The drive circuit 30 includes, for example, a gate driver circuit, a source driver circuit, etc. It may also include an arithmetic circuit, a memory circuit, or a power supply circuit, etc. Since the gate driver circuit, source driver circuit, and other circuits can be arranged on top of the display unit 13, the width of the non-display area (also called a frame) on the outer periphery of the display unit 13 of the display device 10 can be made extremely narrow compared to the case where these circuits and the display unit 13 are arranged side by side, thereby realizing a compact display device 10.

[0036] The functional circuit 40 has, for example, the functions of an application processor for controlling each circuit in the display device 10 and for generating signals for controlling each circuit. The functional circuit 40 may also have circuits for correcting image data, such as CPUs and GPUs. The functional circuit 40 may also have LVDS (Low Voltage Differential Signaling) circuits, MIPI (Mobile Industry Processor Interface) circuits, and / or D / A (Digital to Analog) conversion circuits, etc., which function as interfaces for receiving image data etc. from outside the display device 10. The functional circuit 40 may also have circuits for compressing and decompressing image data, and / or power supply circuits, etc.

[0037] A layer 50 is provided on layer 20. Layer 50 is provided with a plurality of pixel circuits 51. Layer 50 has a channel formation region 54 containing a transistor 52 (also called an OS transistor) having a metal oxide (also called an oxide semiconductor). Layer 50 can be configured by stacking it on layer 20. It is also possible to form layer 50 on a separate substrate and then bond it together.

[0038] As the OS transistor 52, it is preferable to use a transistor having an oxide containing at least one of indium, element M (where element M is aluminum, gallium, yttrium, or tin), and zinc in the channel formation region. Such an OS transistor has the characteristic of having a very low off-current. Therefore, it is preferable to use an OS transistor, especially as a transistor provided in a pixel circuit, because it can retain the analog data written to the pixel circuit for a long period of time.

[0039] A layer 60 is provided on layer 50. A substrate 12 is provided on layer 60. Preferably, the substrate 12 is a light-transmitting substrate or a layer made of a light-transmitting material. A plurality of display elements 61 are provided on layer 60. Layer 60 can be configured to be stacked on layer 50. As the display elements 61, for example, organic electroluminescent elements (also called organic EL elements) can be used. However, the display elements 61 are not limited to this, and for example, inorganic EL elements made of inorganic materials may be used. Note that "organic EL elements" and "inorganic EL elements" are sometimes collectively referred to as "EL elements". The display elements 61 may have inorganic compounds such as quantum dots. For example, quantum dots can be used as the light-emitting layer to function as a light-emitting material.

[0040] Figure 2A is a schematic block diagram of the display device 10 described in Figures 1A and 1B. As shown in Figure 2A, the display device 10 according to one embodiment of the present invention can have a stacked configuration of display elements 61, pixel circuits 51, drive circuits 30, and function circuits 40, so that the aperture ratio (effective display area ratio) of the pixels can be made extremely high. For example, the aperture ratio of the pixels can be 40% or more and less than 100%, preferably 50% or more and 95%, and more preferably 60% or more and 95%. In addition, it is possible to arrange the pixel circuits 51 at an extremely high density, so that the resolution of the pixels can be made extremely high. For example, in the display section of the display device 10 (the area where the pixel circuits 51 and display elements 61 are stacked and provided), it is possible to arrange pixels with a resolution of 20000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and a resolution of 20000 ppi or less, or 30000 ppi or less.

[0041] Because such a display device 10 has extremely high resolution, it can be suitably used in VR devices such as head-mounted displays, or AR devices such as glasses. For example, even in a configuration where the display unit of the display device 10 is viewed through lenses, the display device 10 has an extremely high-resolution display unit, so even when the display unit is magnified with lenses, pixels are not visible, allowing for a highly immersive display. Furthermore, the display device 10 is not limited to this, and can be suitably used in electronic devices with relatively small display units. For example, it can be suitably used in the display unit of wearable electronic devices such as smartwatches.

[0042] In the display device 10, if a material having single-crystal silicon is used as the transistor 21 in the layer 20, the size of the display section 13 can be 0.1 inches or more and 5 inches or less diagonally, preferably 0.5 inches or more and 3 inches or less diagonally, and more preferably 1 inch or more and 2 inches or less. In one embodiment of the present invention, the width of the frame can be made extremely narrow, so for example, if the size of the substrate 11 on which the layer 20 is provided is 1 inch diagonally, it is preferable because it is possible to extract about four times the amount of light compared to a size of 0.5 inches diagonally.

[0043] A specific example of the configuration of the drive circuit 30 and the function circuit 40 will be explained with reference to Figure 2B. The display device 10 shown in Figure 2B is a block diagram illustrating the pixel circuit 51, the multiple wires connecting the drive circuit 30 and the function circuit 40, and buses, etc.

[0044] In the display device 10 shown in Figure 2B, layer 50 has multiple pixel circuits 51 arranged in a matrix.

[0045] Furthermore, in the display device 10 shown in Figure 2B, layer 20 contains a drive circuit 30 and a function circuit 40. The drive circuit 30 includes, for example, a source driver circuit 31, a digital-to-analog conversion circuit 32, a gate driver circuit 33, and a level shifter 34. The function circuit 40 includes, for example, a memory device 41, a GPU (AI accelerator) 42, an EL correction circuit 43, a timing controller 44, a CPU 45, a sensor controller 46, and a power supply circuit 47. The function circuit 40 has the functions of an application processor.

[0046] Furthermore, in the display device 10 shown in Figure 2B, the circuits included in the drive circuit 30 and the circuits included in the function circuit 40 are electrically connected to a bus wiring BSL, for example.

[0047] The source driver circuit 31, for example, has the function of transmitting image data to the pixel circuit 51. Therefore, the source driver circuit 31 is electrically connected to the pixel circuit 51 via wiring SL.

[0048] The digital-to-analog conversion circuit 32, for example, has the function of converting image data that has been digitally processed by a GPU, correction circuit, etc. (described later) into analog data. The image data converted to analog data is transmitted to the pixel circuit 51 via the source driver circuit 31. The digital-to-analog conversion circuit 32 may be included in the source driver circuit 31, or the image data may be transmitted in the order of source driver circuit 31, digital-to-analog conversion circuit 32, and then pixel circuit 51.

[0049] The gate driver circuit 33, for example, has the function of selecting the pixel circuit to which the image data will be transmitted in the pixel circuit 51. Therefore, the gate driver circuit 33 is electrically connected to the pixel circuit 51 via wiring GL.

[0050] The level shifter 34 has the function of converting signals input to the source driver circuit 31, the digital-to-analog conversion circuit 32, the gate driver circuit 33, etc., to an appropriate level.

[0051] The storage device 41, for example, has the function of storing image data to be displayed on the pixel circuit 51. The storage device 41 can be configured to store image data as either digital or analog data.

[0052] Furthermore, when storing image data in the storage device 41, it is preferable that the storage device 41 be a non-volatile memory. In this case, for example, a NAND type memory can be used as the storage device 41.

[0053] Furthermore, when storing temporary data generated by the GPU 42, EL correction circuit 43, CPU 45, etc., in the storage device 41, it is preferable to use volatile memory as the storage device 41. In this case, for example, SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory) can be used as the storage device 41.

[0054] For example, the GPU42 has the function of processing image data read from the storage device 41 for output to the pixel circuit 51. In particular, because the GPU42 is configured to perform parallel pipeline processing, it can process image data to be output to the pixel circuit 51 at high speed. The GPU42 can also function as a decoder for restoring encoded images.

[0055] Furthermore, the functional circuit 40 may include multiple circuits that can improve the display quality of the display device 10. For example, such circuits may include correction circuits (color adjustment, brightness adjustment) that detect color unevenness in the displayed image and correct the color unevenness to produce an optimal image. Also, if an organic EL light-emitting device is used as the display element, the functional circuit 40 may include an EL correction circuit. As an example, the functional circuit 40 includes an EL correction circuit 43.

[0056] Furthermore, artificial intelligence may be used for the image correction described above. For example, the current flowing through the pixel circuit (or the voltage applied to the pixel circuit) may be monitored and acquired, the displayed image may be acquired using an image sensor, and the current (or voltage) and the image may be treated as input data for an artificial intelligence calculation (e.g., an artificial neural network), and the output result may be used to determine whether or not the image has been corrected.

[0057] Furthermore, artificial intelligence calculations can be applied not only to image correction but also to image data upconversion (downconversion). As an example, GPU42 in Figure 2B illustrates a block for performing various correction calculations (color uniformity correction 42a, upconversion 42b, etc.).

[0058] The timing controller 44 has, for example, a function to vary the frame rate at which images are displayed. For instance, when displaying a still image on the display device 10, the timing controller 44 can be used to lower the frame rate and drive the display. Conversely, when displaying a video on the display device 10, the timing controller 44 can be used to increase the frame rate and drive the display.

[0059] The CPU 45 has functions to perform general-purpose processing, such as executing an operating system, controlling data, and executing various calculations or programs. The CPU 45 also has the role of issuing commands, for example, to write or read image data from the storage device 41, correct image data, and operate sensors, which will be described later. In addition, the CPU 45 may also have the function of transmitting control signals to at least one of the circuits included in the functional circuit 40.

[0060] The sensor controller 46, for example, has the function of controlling the sensor. In Figure 2B, the wiring SNCL is shown as the wiring for electrically connecting to the sensor.

[0061] The sensor in question may be, for example, a touch sensor that can be provided on the display unit. Alternatively, the sensor may be, for example, an illuminance sensor.

[0062] The power supply circuit 47 has the function of generating voltage to supply to circuits such as the pixel circuit 51, the drive circuit 30, and the function circuit 40, as an example. The power supply circuit 47 may also have the function of selecting which circuits to supply voltage to. For example, the power supply circuit 47 can reduce the overall power consumption of the display device 10 by stopping the voltage supply to the CPU 45, GPU 42, etc., during the period when a still image is being displayed.

[0063] As described above, one aspect of the present invention allows for a display device configuration in which a display element, a pixel circuit, a drive circuit, and a function circuit are stacked. The peripheral circuits, the drive circuit and the function circuit, can be arranged in overlapping positions with the pixel circuit, and the width of the bezel can be made extremely narrow, resulting in a miniaturized display device. Furthermore, by stacking the circuits in one aspect of the present invention, the wiring connecting each circuit can be shortened, resulting in a lightweight display device. In addition, one aspect of the present invention allows for a display unit with increased pixel resolution, resulting in a display device with superior display quality.

[0064] Figures 3A and 3B show an example configuration of the pixel circuit 51 and the display element 61 connected to the pixel circuit 51. Figure 3A is a diagram showing the connections of each element, and Figure 3B is a diagram schematically showing the hierarchical relationship between the layer 20 containing the drive circuit, the layer 50 containing the multiple transistors of the pixel circuit, and the layer 60 containing the light-emitting element.

[0065] The pixel circuit 51 shown as an example in Figures 3A and 3B comprises transistors 52A, 52B, 52C, and a capacitor 53. Transistors 52A, 52B, and 52C can be composed of OS transistors. Each OS transistor of transistors 52A, 52B, and 52C preferably has a back gate electrode, in which case the back gate electrode can be configured to receive the same signal as the gate electrode, or to receive a different signal from the gate electrode.

[0066] Transistor 52B comprises a gate electrode electrically connected to transistor 52A, a first terminal electrically connected to the display element 61, and a second terminal electrically connected to wiring ANO. Wiring ANO is a wire that provides a potential for supplying current to the display element 61.

[0067] Transistor 52A has a first terminal electrically connected to the gate electrode of transistor 52B, a second terminal electrically connected to wiring SL which functions as a source line, and a function to control the conduction or non-conduction state based on the potential of wiring GL1 which functions as a gate line.

[0068] Transistor 52C has a first terminal electrically connected to wiring V0, a ​​second terminal electrically connected to display element 61, and a function to control the conduction or non-conduction state based on the potential of wiring GL2 which functions as a gate line. Wiring V0 is a wiring for supplying a reference potential and a wiring for outputting the current flowing through the pixel circuit 51 to the drive circuit 30 or the function circuit 40.

[0069] Capacitor 53 comprises a conductive film electrically connected to the gate electrode of transistor 52B and a conductive film electrically connected to the second terminal of transistor 52C.

[0070] The display element 61 includes a first electrode electrically connected to the first terminal of the transistor 52B and a second electrode electrically connected to the wiring VCOM. The wiring VCOM is a wire that provides a potential for supplying current to the display element 61.

[0071] This allows the intensity of light emitted by the display element 61 to be controlled according to the image signal applied to the gate electrode of transistor 52B. Furthermore, variations in the gate-source potential of transistor 52B can be suppressed by the reference potential of the wiring V0 provided via transistor 52C.

[0072] Furthermore, a current value that can be used to set pixel parameters can be output from wiring V0. More specifically, wiring V0 can function as a monitor line to output the current flowing through transistor 52B or the current flowing through display element 61 to the outside. The current output to wiring V0 is converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter or the like and output to a function circuit 40 or the like.

[0073] In one aspect of the present invention, the light-emitting element described refers to a self-emissive display element such as an organic light-emitting diode (OLED). The light-emitting element electrically connected to the pixel circuit can be a self-emissive light-emitting element such as an LED (light-emitting diode), micro-LED, QLED (quantum-dot light-emitting diode), or semiconductor laser.

[0074] In the configuration shown as an example in Figure 3B, the wiring electrically connecting the pixel circuit 51 and the drive circuit 30 can be shortened, thereby reducing the wiring resistance. As a result, data can be written at high speed, and the display device 10 can be driven at high speed. This allows for a sufficient frame duration even with a large number of pixel circuits 51 in the display device 10, thus increasing the pixel density of the display device 10. Furthermore, increasing the pixel density of the display device 10 improves the resolution of the image displayed by the display device 10. For example, the pixel density of the display device 10 can be set to 1000 ppi or more, or 5000 ppi or more, or 7000 ppi or more. Therefore, the display device 10 can be used as a display device for AR or VR, and can be suitably applied to electronic devices such as HMDs where the distance between the display unit and the user is close.

[0075] Figure 4A shows an example of a drive circuit 30 that is arranged to overlap with the pixel circuit 51. The drive circuit 30 is shown to consist of a source driver circuit 31 and a gate driver circuit 33. Multiple pixel circuits 51 (not shown) are divided into multiple regions 59. Each region 59 is provided in the region that overlaps with the source driver circuit 31 and the gate driver circuit 33. The source driver circuit 31 and the gate driver circuit 33 can be divided into any region of the layer 20 and arranged corresponding to the region 59.

[0076] Figure 4B shows an enlarged view of region 59. In Figure 4B, multiple wirings SL and multiple wirings GL are shown with dashed lines.

[0077] In Figure 4B, multiple vertically extending wirings SL are each electrically connected to a source driver circuit 31. Similarly, multiple horizontally extending wirings GL are each electrically connected to a gate driver circuit 33. Wirings SL and GL are each electrically connected to multiple pixel circuits 51.

[0078] In this way, by providing multiple source driver circuits 31 and gate driver circuits 33 directly below the pixel circuit 51, the lengths of wiring SL and wiring GL can be made extremely short. As a result, the load on wiring SL and wiring GL is reduced, so the time and power required for charging and discharging can be made extremely small, enabling high-speed driving. In addition, since the image can be rewritten for each region 59, it is possible to rewrite the data only for the parts of the image that have changed, and retain the data for images that have not changed, thereby reducing power consumption.

[0079] Furthermore, since the pixel circuit 51 is composed of OS transistors with extremely low off-current, the data written to the pixels can be retained for a long period of time. Therefore, the display frame frequency can be set arbitrarily (made variable). Also, since the display device 10 can be driven for each region 59, the frame frequency can also be set for each region 59 in some cases.

[0080] In one embodiment of the present invention, a display device can stack a pixel circuit and a functional circuit, allowing for the detection of defective pixels using the functional circuit located below the pixel circuit. By using this information about defective pixels, display defects caused by defective pixels can be corrected, enabling normal display.

[0081] Some of the correction methods illustrated below may be performed by circuits located outside the display device. Furthermore, some of the correction methods may be performed by the functional circuit 40 of the display device 10.

[0082] The following shows examples of more specific correction methods. Figure 5A is a flowchart illustrating the correction method described below.

[0083] First, the correction operation is started in step S1.

[0084] Next, in step S2, the pixel current is read. For example, each pixel can be driven to output current to the monitor line electrically connected to the pixel.

[0085] Current readout operations can be performed simultaneously in multiple regions 59. Because the screen is divided, current readout operations for all pixels can be performed in an extremely short time.

[0086] Next, in step S3, the read current is converted into a voltage. At this point, if the signal will be handled in a later process, it can be converted into digital data in step S3. For example, analog data can be converted into digital data using an analog-to-digital converter (ADC).

[0087] Next, in step S4, pixel parameters for each pixel are obtained based on the acquired data. Examples of pixel parameters include the threshold voltage or field-effect mobility of the drive transistor, the threshold voltage of the light-emitting element, and the current value at a predetermined voltage.

[0088] Next, in step S5, a determination is made for each pixel based on its pixel parameters to determine whether it is abnormal or not. For example, if the value of a pixel parameter exceeds (or falls below) a predetermined threshold, that pixel is determined to be an abnormal pixel.

[0089] Abnormal pixels include dark spots, which are significantly lower in brightness relative to the input data potential, and bright spots, which are significantly higher in brightness.

[0090] In step S5, the address of the abnormal pixel and the type of defect can be identified and obtained.

[0091] Next, in step S6, a correction process is performed.

[0092] An example of the correction process will be explained using Figure 5B. Figure 5B schematically shows a pixel consisting of a set of 3x3 pixel circuits 51 and display elements 61. Here, the central pixel is assumed to be pixel 151, which is a dark spot defect. Figure 5B schematically shows a state in which pixel 151 is turned off and the surrounding pixels 150 are lit at a predetermined brightness.

[0093] A dark spot defect is a defect in which, even if a correction is applied to increase the data potential input to the pixel, the pixel's brightness is unlikely to reach normal levels. Therefore, as shown in Figure 5B, a correction is applied to increase the brightness of the pixels 150 surrounding the dark spot defect pixel 151. This allows for the display of a normal image even when a dark spot defect occurs.

[0094] In the case of bright pixel defects, the brightness of the surrounding pixels can be reduced to make the bright pixel defects less noticeable.

[0095] In particular, with high-resolution display devices (e.g., 1000 ppi or higher), it is difficult to distinguish and see each individual pixel, so using a correction method that compensates for abnormal pixels with surrounding pixels is especially effective.

[0096] On the other hand, it is preferable to correct abnormal pixels such as dark spots and bright spots by not inputting data potentials.

[0097] In this way, correction parameters can be set for each pixel. By applying the correction parameters to the input image data, corrected image data can be generated to display an optimal image on the display device 10.

[0098] Furthermore, because variations exist in pixel parameters not only in abnormal pixels and the pixels surrounding them, but also in pixels that were not identified as abnormal, when an image is displayed, inconsistencies caused by these variations may be visible. Therefore, for pixels that were not identified as abnormal, correction parameters can be set to cancel (level out) the variations in pixel parameters. For example, a reference value can be set based on the median or average value of the pixel parameters for some or all pixels, and a correction value can be set as the correction parameter for a given pixel to cancel out the difference from the reference value for the pixel parameters of that pixel.

[0099] Furthermore, for pixels surrounding an abnormal pixel, it is preferable to set correction data that takes into account both a correction amount to compensate for the abnormal pixel and a correction amount to cancel out variations in pixel parameters.

[0100] Next, in step S7, the correction operation is terminated.

[0101] From this point forward, the image can be displayed based on the correction parameters obtained through the above correction operation and the input image data.

[0102] Furthermore, a neural network may be used as one of the correction operations. For example, the neural network can determine correction parameters based on inference results obtained through machine learning. For instance, when determining correction parameters using a neural network, high-precision correction can be achieved to minimize the visibility of abnormal pixels without the need for a detailed correction algorithm.

[0103] The above is an explanation of the correction method.

[0104] Figures 3A and 3B show a pixel circuit 51 having a total of three transistors as an example, but the present invention is not limited to this. Below, examples of pixel circuit configurations and driving methods applicable to the pixel circuit 51 will be described.

[0105] The pixel circuit 51A shown in Figure 6A includes transistors 52A and 52B, and capacitor 53. Figure 6A also shows a display element 61 connected to the pixel circuit 51A. Wirings SL, GL, ANO, and VCOM are electrically connected to the pixel circuit 51A.

[0106] Transistor 52A's gate is electrically connected to wiring GL, one of its source and drain is electrically connected to wiring SL, the other of which is electrically connected to the gate of transistor 52B and one of the electrodes of capacitor 53. Transistor 52B's source and drain are electrically connected to wiring ANO, the other of which is electrically connected to the anode of display element 61. Capacitor 53's other electrode is electrically connected to the anode of display element 61. Display element 61's cathode is electrically connected to wiring VCOM.

[0107] The pixel circuit 51B shown in Figure 6B is configured by adding a transistor 52C to the pixel circuit 51A. Furthermore, wiring V0 is electrically connected to the pixel circuit 51B.

[0108] The pixel circuit 51C shown in Figure 6C is an example in which transistors 52A and 52B of the pixel circuit 51A are replaced with transistors in which a pair of gates are electrically connected. Similarly, the pixel circuit 51D shown in Figure 6D is an example in which the same transistor is replaced with the same transistor in the pixel circuit 51B. This increases the current that the transistors can supply. While transistors with a pair of gates electrically connected are used here, this is not the only option. Alternatively, transistors with a pair of gates that are electrically connected to different wirings may be used. For example, reliability can be improved by using a transistor in which one of the gates is electrically connected to the source.

[0109] The pixel circuit 51E shown in Figure 7A is configured by adding a transistor 52D to the above 51B. Furthermore, the pixel circuit 51E is electrically connected to three wires that function as gate lines (wires GL1, GL2, and GL3).

[0110] Transistor 52D has its gate electrically connected to wiring GL3, and one of its source and drain is electrically connected to the gate of transistor 52B, while the other is electrically connected to wiring V0. Also, the gate of transistor 52A is electrically connected to wiring GL1, and the gate of transistor 52C is electrically connected to wiring GL2.

[0111] By simultaneously making transistors 52C and 52D conduct, the source and gate of transistor 52B become at the same potential, making transistor 52B non-conducting. This allows the current flowing to the display element 61 to be forcibly interrupted. Such a pixel circuit is suitable for display methods that alternate between display periods and off periods.

[0112] The pixel circuit 51F shown in Figure 7B is an example in which a capacitor 53A is added to the above pixel circuit 51E. Capacitor 53A functions as a retaining capacitor.

[0113] The pixel circuits 51G shown in Figure 7C and 51H shown in Figure 7D are examples of applying a transistor having a pair of gates to the above-mentioned pixel circuit 51E or pixel circuit 51F, respectively. Transistors 52A, 52C, and 52D are transistors in which a pair of gates are electrically connected, while transistor 52B is a transistor in which one of its gates is electrically connected to the source.

[0114] Next, an example of a driving method for a display device to which the pixel circuit 51E is applied will be described. Note that the same driving method can also be applied to the pixel circuits 51F, 51G, and 51H.

[0115] Figure 8 shows a timing chart for the driving method of a display device to which the pixel circuit 51E is applied. Here, the potential changes of the gate lines of the k-th row, wiring GL1[k], wiring GL2[k], and wiring GL3[k], and the gate lines of the k+1-th row, wiring GL1[k+1], wiring GL2[k+1], and wiring GL3[k+1] are shown. Figure 8 also shows the timing of the signal applied to wiring SL, which functions as a source line.

[0116] This example shows a driving method that divides one horizontal period into an on-time period and an off-time period. Also, the horizontal period in row k and the horizontal period in row k+1 are shifted by the gate line selection period.

[0117] During the k-th row's illumination period, a high-level potential is first applied to wires GL1[k] and GL2[k], and a source signal is applied to wire SL. This causes transistors 52A and 52C to conduct, and the potential corresponding to the source signal is written from wire SL to the gate of transistor 52B. Subsequently, a low-level potential is applied to wires GL1[k] and GL2[k], causing transistors 52A and 52C to become non-conductive, and the gate potential of transistor 52B is maintained.

[0118] Next, the process transitions to the illumination period of row k+1, and data is written using the same procedure as described above.

[0119] Next, we will explain the blackout period. During the blackout period for row k, a high-level potential is applied to wiring GL2[k] and wiring GL3[k]. This causes transistors 52C and 52D to conduct, and the same potential is supplied to the source and gate of transistor 52B, so almost no current flows through transistor 52B. As a result, the display element 61 turns off. All subpixels located in row k turn off. The subpixels in row k remain off until the next illumination period.

[0120] Next, the process transitions to the blackout period for row k+1, and as described above, all subpixels in row k+1 become black.

[0121] Thus, a driving method that includes periods of the light being off during a horizontal display period, rather than being continuously lit during the horizontal display period, can also be called duty cycle driving. By using duty cycle driving, the afterimage phenomenon when displaying videos can be reduced, thereby enabling the realization of display devices with high video display performance. In particular, in VR devices, reducing afterimages can alleviate so-called VR sickness.

[0122] In duty cycle operation, the ratio of the lighting period to the horizontal period can be called the duty cycle. For example, a duty cycle of 50% means that the lighting period and the off period are of equal length. The duty cycle can be freely set and can be adjusted as appropriate within a range of, for example, higher than 0% and less than or equal to 100%.

[0123] Furthermore, a configuration different from the pixel circuit described above will be explained with reference to Figures 9A and 9B.

[0124] Figure 9A shows the elements of a pixel circuit and a block diagram of a pixel having an light-emitting element. The pixel shown in Figure 9A has a switching transistor (Switching Tr), a driving transistor (Driving Tr), a light-emitting element (LED), and memory (Memory).

[0125] The memory is supplied with data_W. In addition to the display data Data, the supply of data_W to the pixels increases the current flowing to the light-emitting elements, allowing the display device to display high brightness.

[0126] Figure 9B shows a specific circuit diagram of the pixel circuit.

[0127] The pixel circuit 52I shown in Figure 9B includes transistors 52_w, 52A, 52B, 52C, capacitors 53_s, and 53_w. Figure 9B also illustrates the display element 61 connected to the pixel circuit 52I.

[0128] One of the sources or drains of transistor 52_w is electrically connected to one electrode of capacitor 53_w. The other electrode of capacitor 53_w is electrically connected to one of the sources or drains of transistor 52A. One of the sources or drains of transistor 52A is electrically connected to the gate of transistor 52B. The gate of transistor 52B is electrically connected to one electrode of capacitor 53_s. The other electrode of capacitor 53_s is electrically connected to one of the sources or drains of transistor 52B. One of the sources or drains of transistor 52B is electrically connected to one of the sources or drains of transistor 52C. One of the sources or drains of transistor 52C is electrically connected to one electrode of display element 61. Each transistor shown in Figure 9B has a back gate electrically connected to the gate, but the connection of the back gate is not limited to this. Also, a back gate may not be provided for the transistor.

[0129] Here, node NM is the node to which the other electrode of capacitor 53_w, one of the source or drain of transistor 52A, the gate of transistor 52B, and one electrode of capacitor 53_s are connected. Also, node NA is the node to which the other electrode of capacitor 53_s, one of the source or drain of transistor 52B, one of the source or drain of transistor 52C, and one electrode of display element 61 are connected.

[0130] The gate of transistor 52_w is electrically connected to wiring GL1. The gate of transistor 52C is electrically connected to wiring GL1. The gate of transistor 52A is electrically connected to wiring GL2. The other end of the source or drain of transistor 52_w is electrically connected to wiring SL1. The other end of the source or drain of transistor 52C is electrically connected to wiring V0. The other end of the source or drain of transistor 52A is electrically connected to wiring SL2.

[0131] The source or drain of transistor 52B is electrically connected to wiring ANO. The other electrode of display element 61 is electrically connected to wiring VCOM.

[0132] Wirings GL1 and GL2 can function as signal lines for controlling the operation of the transistor. Wiring SL1 can function as a signal line for supplying image signals to pixels. Wiring SL2 can function as a signal line for writing data to the memory circuit MEM. Wiring SL2 can function as a signal line for supplying correction signals to pixels. Wiring V0 can function as a monitor line for acquiring the electrical characteristics of transistor 52B. Furthermore, by supplying a specific potential from wiring V0 to the other electrode of capacitor 53_s via transistor 52C, the writing of the image signal can also be stabilized.

[0133] Transistors 52A and 52B, and capacitor 53_w constitute the memory circuit MEM. Node NM is a memory node, and by making transistor 52_w conduct, the signal supplied to wiring SL2 can be written to node NM. By using an OS transistor with an extremely low off-current for transistor 52A, the potential of node NM can be maintained for a long time.

[0134] In a pixel, the signal written to node NM is capacitively coupled with the image signal supplied from wiring SL1 and can be output to node NA. The transistor 52_w may have a pixel selection function.

[0135] In other words, by storing the desired correction signal in node NM, the correction signal can be added to the supplied image signal. In this case, by combining this with the configuration described in Figures 4A and 4B, in which the source driver circuit 31 and gate driver circuit 33 are divided into arbitrary regions of layer 20 and operated in accordance with the divided regions of the display unit, it becomes possible to operate the system by adding the correction signal only to the region where the image data is updated. Therefore, a configuration with low power consumption can be achieved. Note that the correction signal may be attenuated by elements in the transmission path, so it is preferable to generate it taking such attenuation into consideration.

[0136] By using image signals and correction signals to make the light-emitting element emit light, the current flowing through the light-emitting device can be increased, enabling the expression of high brightness. Since a voltage higher than the output voltage of the source driver circuit can be applied as the gate voltage of the drive transistor, the power consumption of the source driver circuit can be reduced. Because high-brightness light can be used as the light source, the sensitivity of the sensor can be increased.

[0137] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be appropriately combined with other configuration examples or drawings, etc., at least in part.

[0138] (Embodiment 2) In this embodiment, an example of the cross-sectional configuration of a display device 10, which is one aspect of the present invention, will be described.

[0139] Figure 10 is a cross-sectional view showing an example of the configuration of the display device 10. The display device 10 has a substrate 11 and a substrate 12, and the substrate 11 and the substrate 12 are bonded together by a sealing material 712.

[0140] A single-crystal semiconductor substrate, such as a single-crystal silicon substrate, can be used as the substrate 11. Alternatively, a semiconductor substrate other than a single-crystal semiconductor substrate may be used as the substrate 11.

[0141] Transistors 441 and 601 are provided on the substrate 11. Transistors 441 and 601 can be the same as the transistor 21 provided on layer 20 as shown in Embodiment 1.

[0142] The transistor 441 consists of a conductor 443 that functions as a gate electrode, an insulator 445 that functions as a gate insulator, and a part of the substrate 11, and has a semiconductor region 447 including a channel formation region, a low-resistance region 449a that functions as either a source region or a drain region, and a low-resistance region 449b that functions as either a source region or a drain region. The transistor 441 may be either a p-channel or an n-channel type.

[0143] Transistor 441 is electrically isolated from other transistors by the element isolation layer 403. Figure 10 shows the case where transistor 441 and transistor 601 are electrically isolated by the element isolation layer 403. The element isolation layer 403 can be formed using the LOCOS (Local Oxidation of Silicon) method or the STI (Shallow Trench Isolation) method, etc.

[0144] In Figure 10, the transistor 441 has a convex semiconductor region 447. Furthermore, the sides and top surface of the semiconductor region 447 are covered by a conductor 443 via an insulator 445. Note that Figure 10 does not show how the conductor 443 covers the sides of the semiconductor region 447. Additionally, materials that adjust the work function can be used for the conductor 443.

[0145] A transistor with a convex semiconductor region, such as transistor 441, can be called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulator in contact with the upper part of the convex portion, functioning as a mask for forming the convex portion. Furthermore, while Figure 10 shows a configuration where a portion of the substrate 11 is processed to form the convex portion, a semiconductor with a convex shape may also be formed by processing an SOI substrate.

[0146] Note that the configuration of transistor 441 shown in Figure 10 is just one example, and is not limited to this configuration. An appropriate configuration may be used depending on the circuit configuration or the way the circuit operates. For example, transistor 441 may be a planar transistor.

[0147] Transistor 601 can have the same configuration as transistor 441.

[0148] On the substrate 11, in addition to the element isolation layer 403, transistors 441 and 601, insulators 405, 407, 409, and 411 are provided. Conductors 451 are embedded in insulators 405, 407, 409, and 411. Here, the height of the upper surface of the conductor 451 and the height of the upper surface of the insulator 411 can be made to be approximately the same.

[0149] Insulators 421 and 214 are provided on the conductor 451 and on the insulator 411, respectively. The conductor 453 is embedded in the insulator 421 and in the insulator 214. Here, the height of the upper surface of the conductor 453 and the height of the upper surface of the insulator 214 can be made to be approximately the same.

[0150] An insulator 216 is provided on the conductor 453 and on the insulator 214. The conductor 455 is embedded in the insulator 216. Here, the height of the upper surface of the conductor 455 and the height of the upper surface of the insulator 216 can be made to be approximately the same.

[0151] Insulators 222, 224, 254, 280, 274, and 281 are provided on the conductor 455 and on the insulator 216. The conductor 305 is embedded in insulators 222, 224, 254, 280, 274, and 281. Here, the height of the upper surface of the conductor 305 and the height of the upper surface of the insulator 281 can be made to be approximately the same.

[0152] An insulator 361 is provided on the conductor 305 and on the insulator 281. Conductors 317 and 337 are embedded in the insulator 361. Here, the height of the upper surface of the conductor 337 and the height of the upper surface of the insulator 361 can be made to be approximately the same.

[0153] An insulator 363 is provided on the conductor 337 and on the insulator 361. Conductors 347, 353, 355, and 357 are embedded in the insulator 363. Here, the height of the upper surfaces of conductors 353, 355, and 357 can be made to be approximately the same as the height of the upper surface of the insulator 363.

[0154] Connecting electrodes 760 are provided on the conductor 353, conductor 355, conductor 357, and insulator 363. An anisotropic conductor 780 is provided so as to be electrically connected to the connecting electrodes 760, and an FPC (Flexible Printed Circuit) 716 is provided so as to be electrically connected to the anisotropic conductor 780. Various signals and the like are supplied to the display device 10 from outside the display device 10 via the FPC 716.

[0155] As shown in Figure 10, the low-resistance region 449b, which functions as either the source region or the drain region of transistor 441, is electrically connected to the FPC 716 via conductors 451, 453, 455, 305, 317, 337, 347, 353, 355, 357, connecting electrode 760, and anisotropic conductor 780. Here, Figure 10 shows three conductors, conductors 353, 355, and 357, which have the function of electrically connecting the connecting electrode 760 and the conductor 347, but the present invention is not limited to these. There may be one, two, or four or more conductors that have the function of electrically connecting the connecting electrode 760 and the conductor 347. By providing multiple conductors that have the function of electrically connecting the connecting electrode 760 and the conductor 347, the contact resistance can be reduced.

[0156] A transistor 750 is provided on the insulator 214. Transistor 750 can be the transistor 52 provided on layer 50 as shown in Embodiment 1. For example, it can be the transistor provided on the pixel circuit 51. An OS transistor can preferably be used for transistor 750. OS transistors have the characteristic of having an extremely small off-current. Therefore, the retention time of image data, etc. can be extended, and the frequency of refresh operations can be reduced. Therefore, the power consumption of the display device 10 can be reduced.

[0157] Conductors 301a and 301b are embedded in insulators 254, 280, 274, and 281, respectively. Conductor 301a is electrically connected to either the source or drain of transistor 750, and conductor 301b is electrically connected to the other source or drain of transistor 750. Here, the height of the upper surfaces of conductors 301a and 301b can be made to be approximately the same as the height of the upper surface of insulator 281.

[0158] Conductors 311, 313, 331, capacitor 790, 333, and 335 are embedded in the insulator 361. Conductors 311 and 313 are electrically connected to the transistor 750 and function as wiring. Conductors 333 and 335 are electrically connected to the capacitor 790. Here, the height of the upper surfaces of conductors 331, 333, and 335 can be made to be approximately the same as the height of the upper surface of the insulator 361.

[0159] Conductors 341, 343, and 351 are embedded in the insulator 363. Here, the height of the upper surface of conductor 351 and the height of the upper surface of insulator 363 can be made to be approximately the same.

[0160] Insulators 405, 407, 409, 411, 421, 214, 280, 274, 281, 361, and 363 may function as interlayer films and as planarizing films that cover the uneven surface beneath them. For example, the upper surface of insulator 363 may be planarized by a planarizing treatment such as chemical mechanical polishing (CMP) to improve its flatness.

[0161] As shown in Figure 10, the capacitor 790 has a lower electrode 321 and an upper electrode 325. An insulator 323 is provided between the lower electrode 321 and the upper electrode 325. In other words, the capacitor 790 has a laminated structure in which an insulator 323, which functions as a dielectric, is sandwiched between a pair of electrodes. Although Figure 10 shows an example in which the capacitor 790 is provided on an insulator 281, the capacitor 790 may be provided on an insulator different from the insulator 281.

[0162] Figure 10 shows an example in which conductors 301a, 301b, and 305 are formed in the same layer. It also shows an example in which conductors 311, 313, 317, and the lower electrode 321 are formed in the same layer. Furthermore, it shows an example in which conductors 331, 333, 335, and 337 are formed in the same layer. It also shows an example in which conductors 341, 343, and 347 are formed in the same layer. In addition, it shows an example in which conductors 351, 353, 355, and 357 are formed in the same layer. By forming multiple conductors in the same layer, the manufacturing process of the display device 10 can be simplified, thereby reducing the manufacturing cost of the display device 10. Note that these may be formed in different layers and may be made of different types of materials.

[0163] The display device 10 shown in Figure 10 has a display element 61. The display element 61 has a conductor 772, an EL layer 786, and a conductor 788. The EL layer 786 has an organic compound or an inorganic compound such as a quantum dot.

[0164] Materials that can be used in organic compounds include fluorescent materials or phosphorescent materials. Materials that can be used in quantum dots include colloidal quantum dot materials, alloy-type quantum dot materials, core-shell type quantum dot materials, and core-type quantum dot materials.

[0165] The conductor 772 is electrically connected to the source or drain of the transistor 750 via conductors 351, 341, 331, 313, and 301b. The conductor 772 is formed on the insulator 363 and functions as a pixel electrode.

[0166] The conductor 772 can be made of a material that is transparent to visible light or a material that is reflective to visible light. As a transparent material, for example, an oxide material containing indium, zinc, tin, etc., may be used. As a reflective material, for example, a material containing aluminum, silver, etc., may be used.

[0167] Although not shown in Figure 10, the display device 10 may be equipped with optical components (optical substrates) such as polarizing members, phase difference members, and anti-reflective members.

[0168] On the substrate 12 side, a light-shielding layer 738 and an insulator 734 in contact with them are provided. The light-shielding layer 738 has the function of blocking light emitted from adjacent areas. Alternatively, the light-shielding layer 738 has the function of preventing ambient light from reaching the transistor 750, etc.

[0169] In the display device 10 shown in Figure 10, an insulator 730 is provided on an insulator 363. Here, the insulator 730 can be configured to cover a portion of the conductor 772. Furthermore, the display element 61 has a light-transmitting conductor 788 and can be a top-emission type light-emitting element.

[0170] The light-shielding layer 738 is provided so as to have an area that overlaps with the insulator 730. The light-shielding layer 738 is covered with the insulator 734. The space between the display element 61 and the insulator 734 is filled with a sealing layer 732.

[0171] Furthermore, the structure 778 is provided between the insulator 730 and the EL layer 786. Also, the structure 778 is provided between the insulator 730 and the insulator 734.

[0172] A modified version of the display device 10 shown in Figure 10 is shown in Figure 11. The display device 10 shown in Figure 11 differs from the display device 10 shown in Figure 10 in that it has a colored layer 736. The colored layer 736 is provided so as to have an area that overlaps with the display element 61. By providing the colored layer 736, the color purity of the light extracted from the display element 61 can be increased. As a result, the display device 10 can display high-resolution images. Furthermore, since, for example, all of the display elements 61 of the display device 10 can be light-emitting elements that emit white light, it is not necessary to form the EL layer 786 by painting, and the display device 10 can be made high-resolution.

[0173] The element 61 can have a microcavity structure. Thereby, light of a predetermined color (e.g., RGB) can be extracted without providing a coloring layer, and the display device 10 can perform color display. By adopting a configuration without a coloring layer, absorption of light by the coloring layer can be suppressed. Thereby, the display device 10 can display a high-brightness image and can also reduce the power consumption of the display device 10. Note that even when the EL layer 786 is formed in an island shape for each pixel or in a stripe shape for each pixel column, that is, formed by painting, a configuration without a coloring layer can be adopted. The brightness of the display device 10 is, for example, 500 cd / m 2 or more, preferably 1000 cd / m 2 or more and 10000 cd / m 2 or less, more preferably 2000 cd / m 2 or more and 5000 cd / m 2 or less can be adopted.

[0174] <Configuration Example of OS Transistor> FIGS. 12A, 12B, and 12C are top views and cross-sectional views of the transistor 750 and the periphery of the transistor 750 that can be used in a display device according to an aspect of the present invention. The transistor 750 can be applied to a display device according to an aspect of the present invention.

[0175] FIG. 12A is a top view of the transistor 750. FIGS. 12B and 12C are cross-sectional views of the transistor 750. Here, FIG. 12B is a cross-sectional view of a portion indicated by a one-dot chain line A1-A2 in FIG. 12A and is also a cross-sectional view in the channel length direction of the transistor 750. FIG. 12C is a cross-sectional view of a portion indicated by a one-dot chain line A3-A4 in FIG. 12A and is also a cross-sectional view in the channel width direction of the transistor 750. In the top view of FIG. 12A, some elements are omitted for clarity of the drawing.

[0176] As shown in Figure 12, the transistor 750 includes a metal oxide 230a disposed on a substrate (not shown), a metal oxide 230b disposed on the metal oxide 230a, conductors 242a and 242b disposed on the metal oxide 230b at a distance from each other, an insulator 280 disposed on the conductors 242a and 242b with an opening formed between the conductors 242a and 242b, a conductor 260 disposed in the opening, an insulator 250 disposed between the metal oxide 230b, conductors 242a, conductors 242b, and insulator 280 and conductor 260, and a metal oxide 230c disposed between the metal oxide 230b, conductors 242a, conductors 242b, and insulator 280 and insulator 250. Here, as shown in Figures 12B and 12C, it is preferable that the upper surface of the conductor 260 substantially coincides with the upper surfaces of the insulators 250, 254, metal oxide 230c, and 280. In the following, metal oxides 230a, 230b, and 230c may be collectively referred to as metal oxide 230. Also, conductors 242a and 242b may be collectively referred to as conductor 242.

[0177] In the transistor 750 shown in Figure 12, the sides of the conductors 242a and 242b facing the conductor 260 have a generally vertical shape. However, the transistor 750 shown in Figure 12 is not limited to this, and the angle between the side and bottom surfaces of the conductors 242a and 242b may be 10° to 80°, preferably 30° to 60°. Furthermore, the opposing sides of the conductors 242a and 242b may have multiple surfaces.

[0178] As shown in Figure 12, it is preferable that an insulator 254 is placed between the insulator 224, metal oxide 230a, metal oxide 230b, conductor 242a, conductor 242b, and metal oxide 230c and the insulator 280. Here, it is preferable that the insulator 254 is in contact with the side surface of the metal oxide 230c, the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, the side surfaces of the metal oxide 230a and metal oxide 230b, and the top surface of the insulator 224, as shown in Figures 12B and 12C.

[0179] In the transistor 750, a configuration is shown in which three layers of metal oxide 230a, metal oxide 230b, and metal oxide 230c are stacked in the region where the channel is formed (hereinafter also referred to as the channel formation region) and in its vicinity. However, the present invention is not limited to this. For example, a two-layer structure of metal oxide 230b and metal oxide 230c, or a stacked structure of four or more layers, may be provided. Also, in the transistor 750, the conductor 260 is shown as a two-layer stacked structure. However, the present invention is not limited to this. For example, the conductor 260 may be a single-layer structure or a stacked structure of three or more layers. Furthermore, each of the metal oxide 230a, metal oxide 230b, and metal oxide 230c may have a stacked structure of two or more layers.

[0180] For example, if the metal oxide 230c has a layered structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, it is preferable that the first metal oxide has the same composition as metal oxide 230b and the second metal oxide has the same composition as metal oxide 230a.

[0181] Here, the conductor 260 functions as the gate electrode of the transistor, and the conductors 242a and 242b function as the source electrode or drain electrode, respectively. As described above, the conductor 260 is formed to be embedded in the opening of the insulator 280 and in the region sandwiched between the conductors 242a and 242b. Here, the arrangement of the conductors 260, 242a, and 242b is selected in a self-aligned manner with respect to the opening of the insulator 280. In other words, in the transistor 750, the gate electrode can be positioned in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductor 260 can be formed without providing a positional margin, the occupied area of ​​the transistor 750 can be reduced. This makes it possible to make the display device high-resolution. It also makes it possible to make the display device narrow-bezel.

[0182] As shown in Figure 12, it is preferable that the conductor 260 has a conductor 260a provided inside the insulator 250 and a conductor 260b provided so as to be embedded inside the conductor 260a.

[0183] The transistor 750 preferably includes an insulator 214 disposed on a substrate (not shown), an insulator 216 disposed on top of the insulator 214, a conductor 205 disposed so as to be embedded in the insulator 216, an insulator 222 disposed on top of the insulator 216 and the conductor 205, and an insulator 224 disposed on top of the insulator 222. It is preferable that a metal oxide 230a is disposed on top of the insulator 224.

[0184] It is preferable that insulators 274 and 281, which function as interlayer films, are placed on top of the transistor 750. Here, it is preferable that insulator 274 is placed in contact with the upper surfaces of the conductor 260, insulator 250, insulator 254, metal oxide 230c, and insulator 280.

[0185] It is preferable that insulators 222, 254, and 274 have a function to suppress the diffusion of at least one of the hydrogen (e.g., hydrogen atoms, hydrogen molecules, etc.). For example, it is preferable that insulators 222, 254, and 274 have lower hydrogen permeability than insulators 224, 250, and 280. It is also preferable that insulators 222 and 254 have a function to suppress the diffusion of at least one of the oxygen (e.g., oxygen atoms, oxygen molecules, etc.). For example, it is preferable that insulators 222 and 254 have lower oxygen permeability than insulators 224, 250, and 280.

[0186] Here, insulator 224, metal oxide 230, and insulator 250 are separated from insulators 280 and 281 by insulators 254 and 274. Therefore, it is possible to suppress the mixing of impurities such as hydrogen, or excess oxygen, contained in insulators 280 and 281, into insulators 224, metal oxide 230a, metal oxide 230b, and insulator 250.

[0187] It is preferable that a conductor 240 (conductor 240a and conductor 240b) is provided that is electrically connected to the transistor 750 and functions as a plug. In addition, an insulator 241 (insulator 241a and insulator 241b) is provided in contact with the side surface of the conductor 240 that functions as a plug. That is, the insulator 241 is provided in contact with the inner wall of the opening of the insulator 254, insulator 280, insulator 274, and insulator 281. Alternatively, a first conductor of the conductor 240 may be provided in contact with the side surface of the insulator 241, and a second conductor of the conductor 240 may be provided further inside. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 281 can be made to be approximately the same. Although the transistor 750 shows a configuration in which the first conductor and the second conductor of the conductor 240 are stacked, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or as a laminated structure of three or more layers. When the structure has a laminated structure, ordinal numbers may be assigned to distinguish them according to the order of formation.

[0188] In transistor 750, it is preferable to use a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) for the metal oxide 230 (metal oxide 230a, metal oxide 230b, and metal oxide 230c) that includes the channel formation region. For example, it is preferable to use a metal oxide with a band gap of 2 eV or more, preferably 2.5 eV or more, as the metal oxide that forms the channel formation region of metal oxide 230.

[0189] The above metal oxide preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable that it contains indium (In) and zinc (Zn). In addition, it is preferable that it contains element M. As element M, one or more of the following can be used: aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), or cobalt (Co). In particular, it is preferable that element M is one or more of aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn). Furthermore, it is even more preferable that element M contains either Ga or Sn, or both.

[0190] Furthermore, as shown in Figure 12B, the thickness of the metal oxide 230b in the region that does not overlap with the conductor 242 may be thinner than the thickness of the metal oxide 230b in the region that overlaps with the conductor 242. This is formed by removing a portion of the upper surface of the metal oxide 230b when forming the conductors 242a and 242b. When a conductive film that will become the conductor 242 is deposited on the upper surface of the metal oxide 230b, a region with low resistance may be formed near the interface with the conductive film. In this way, by removing the region with low resistance located between the conductors 242a and 242b on the upper surface of the metal oxide 230b, it is possible to prevent the formation of a channel in that region.

[0191] According to one aspect of the present invention, a display device with a small size transistor and high resolution can be provided. Alternatively, a display device with a large on-current transistor and high brightness can be provided. Alternatively, a display device with a fast-operating transistor and fast operation can be provided. Alternatively, a display device with a stable electrical characteristic transistor and high reliability can be provided. Alternatively, a display device with a small off-current transistor and low power consumption can be provided.

[0192] A detailed configuration of a transistor 750 that can be used in a display device according to one aspect of the present invention will be described.

[0193] The conductor 205 is arranged so as to have an overlapping region with the metal oxide 230 and the conductor 260. Furthermore, it is preferable that the conductor 205 is embedded in the insulator 216.

[0194] The conductor 205 comprises conductor 205a, conductor 205b, and conductor 205c. Conductor 205a is provided in contact with the bottom surface and side wall of an opening provided in the insulator 216. Conductor 205b is provided so as to be embedded in a recess formed in conductor 205a. Here, the upper surface of conductor 205b is lower than the upper surface of conductor 205a and the upper surface of the insulator 216. Conductor 205c is provided in contact with the upper surface of conductor 205b and the side surface of conductor 205a. Here, the height of the upper surface of conductor 205c is approximately equal to the height of the upper surface of conductor 205a and the upper surface of the insulator 216. In other words, conductor 205b is enclosed by conductors 205a and 205c.

[0195] It is preferable to use conductive materials for conductors 205a and 205c that have the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use conductive materials that have the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0196] By using a conductive material having a function of reducing the diffusion of hydrogen for the conductors 205a and 205c, it is possible to suppress impurities such as hydrogen contained in the conductor 205b from diffusing into the metal oxide 230 through the insulator 224 or the like. Further, by using a conductive material having a function of suppressing the diffusion of oxygen for the conductors 205a and 205c, it is possible to suppress the conductor 205b from being oxidized and the conductivity from decreasing. As the conductive material having a function of suppressing the diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used. Therefore, as the conductor 205a, the above conductive material may be used as a single layer or a laminate. For example, the conductor 205a may use titanium nitride.

[0197] Also, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductor 205b. For example, the conductor 205b may use tungsten.

[0198] Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. Also, the conductor 205 may function as a second gate (also referred to as a bottom gate) electrode. In that case, by changing the potential applied to the conductor 205 independently without linking it to the potential applied to the conductor 260, the V th of the transistor 750 can be controlled. In particular, by applying a negative potential to the conductor 205, the V th of the transistor 750 can be made larger than 0V and the off-current can be made smaller. Therefore, applying a negative potential to the conductor 205 can make the drain current smaller when the potential applied to the conductor 260 is 0V than when no potential is applied.

[0199] The conductor 205 should be larger than the channel-forming region in the metal oxide 230. In particular, as shown in Figure 12C, it is preferable that the conductor 205 extends to the region outside the end that intersects with the channel width direction of the metal oxide 230. That is, it is preferable that the conductor 205 and the conductor 260 are superimposed on the outside of the side surface in the channel width direction of the metal oxide 230, with an insulator in between.

[0200] With the above configuration, the channel-forming region of the metal oxide 230 can be electrically surrounded by the electric field of the conductor 260, which functions as the first gate electrode, and the electric field of the conductor 205, which functions as the second gate electrode.

[0201] As shown in Figure 12C, the conductor 205 is extended to function as wiring. However, the configuration is not limited to this, and a conductor that functions as wiring may be provided beneath the conductor 205.

[0202] The insulator 214 preferably functions as a barrier insulating film that suppresses the ingress of impurities such as water or hydrogen into the transistor 750 from the substrate side. Therefore, it is preferable to use an insulating material for the insulator 214 that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (i.e., the above impurities are less permeable). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules) (i.e., the above oxygen is less permeable).

[0203] For example, it is preferable to use aluminum oxide or silicon nitride as the insulator 214. This suppresses the diffusion of impurities such as water or hydrogen from the substrate side to the transistor 750 side beyond the insulator 214. Alternatively, it suppresses the diffusion of oxygen contained in the insulator 224, etc., toward the substrate side beyond the insulator 214.

[0204] The insulators 216, 280, and 281, which function as interlayer films, preferably have a lower dielectric constant than insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wiring can be reduced. For example, silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or porous silicon oxide may be used as insulators 216, 280, and 281.

[0205] Insulators 222 and 224 function as gate insulators.

[0206] Here, it is preferable that the insulator 224 in contact with the metal oxide 230 desorbs oxygen upon heating. In this specification, the oxygen that is desorbed upon heating is sometimes referred to as excess oxygen. For example, the insulator 224 may be silicon oxide or silicon oxide nitride, etc., as appropriate. By providing an oxygen-containing insulator in contact with the metal oxide 230, the oxygen deficiency in the metal oxide 230 can be reduced, and the reliability of the transistor 750 can be improved.

[0207] Specifically, it is preferable to use an oxide material in which some oxygen is desorbed upon heating as the insulator 224. An oxide that desorbs oxygen upon heating is one in which the amount of oxygen desorbed, converted to oxygen atoms, is 1.0 × 10¹⁶ as determined by TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 Preferably 1.0 × 10 19 atoms / cm 3 More preferably 2.0 × 10 19 atoms / cm 3 The above, or 3.0 × 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C, or 100°C to 400°C.

[0208] As shown in Figure 12C, the thickness of the insulator 224 in the region that does not overlap with the insulator 254 and does not overlap with the metal oxide 230b may be thinner than the thickness of the other regions. In the insulator 224, it is preferable that the thickness of the region that does not overlap with the insulator 254 and does not overlap with the metal oxide 230b is such that the above-mentioned oxygen can diffuse sufficiently.

[0209] The insulator 222, like the insulator 214, preferably functions as a barrier insulating film that suppresses the ingress of impurities such as water or hydrogen into the transistor 750 from the substrate side. For example, it is preferable that the insulator 222 has lower hydrogen permeability than the insulator 224. By surrounding the insulator 224, the metal oxide 230, and the insulator 250 with the insulator 222, the insulator 254, and the insulator 274, it is possible to suppress the ingress of impurities such as water or hydrogen into the transistor 750 from the outside.

[0210] Furthermore, it is preferable that the insulator 222 has a function to suppress the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule) (i.e., it is difficult for the above-mentioned oxygen to permeate it). For example, it is preferable that the insulator 222 has lower oxygen permeability than the insulator 224. It is preferable that the insulator 222 has a function to suppress the diffusion of oxygen or impurities, thereby reducing the diffusion of oxygen contained in the metal oxide 230 to the substrate side. In addition, it is possible to suppress the reaction of the conductor 205 with the oxygen contained in the insulator 224 or the metal oxide 230.

[0211] The insulator 222 may be an insulator containing an oxide of either or both aluminum and hafnium, which are insulating materials. Preferably, the insulator containing an oxide of either or both aluminum and hafnium is an aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the metal oxide 230 or the incorporation of impurities such as hydrogen from the periphery of the transistor 750 into the metal oxide 230.

[0212] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be subjected to nitriding treatment. Silicon oxide, silicon oxide nitride, or silicon nitride may be laminated onto the above insulators.

[0213] The insulator 222 may be a single-layer or multi-layer insulator containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0214] Furthermore, the insulators 222 and 224 may have a laminated structure of two or more layers. In that case, the laminated structure is not limited to being made of the same material, but may be made of different materials. For example, an insulator similar to the insulator 224 may be provided below the insulator 222.

[0215] The metal oxide 230 comprises a metal oxide 230a, a metal oxide 230b on the metal oxide 230a, and a metal oxide 230c on the metal oxide 230b. By having the metal oxide 230a below the metal oxide 230b, the diffusion of impurities from structures formed below the metal oxide 230a to the metal oxide 230b can be suppressed. Furthermore, by having the metal oxide 230c on the metal oxide 230b, the diffusion of impurities from structures formed above the metal oxide 230c to the metal oxide 230b can be suppressed.

[0216] Furthermore, it is preferable that the metal oxide 230 has a layered structure of multiple oxide layers with different atomic ratios of each metal atom. For example, if the metal oxide 230 contains at least indium (In) and element M, it is preferable that the ratio of the number of atoms of element M contained in metal oxide 230a to the total number of atoms of all elements constituting metal oxide 230a is higher than the ratio of the number of atoms of element M contained in metal oxide 230b to the total number of atoms of all elements constituting metal oxide 230b. It is also preferable that the atomic ratio of element M contained in metal oxide 230a to In is higher than the atomic ratio of element M contained in metal oxide 230b to In. Here, metal oxide 230c can be any metal oxide that can be used in metal oxide 230a or metal oxide 230b.

[0217] It is preferable that the energy at the lower end of the conduction band of metal oxide 230a and metal oxide 230c is higher than the energy at the lower end of the conduction band of metal oxide 230b. In other words, it is preferable that the electron affinity of metal oxide 230a and metal oxide 230c is smaller than the electron affinity of metal oxide 230b. In this case, it is preferable that metal oxide 230c is a metal oxide that can be used for metal oxide 230a. Specifically, it is preferable that the ratio of the number of atoms of element M contained in metal oxide 230c to the total number of atoms of all elements constituting metal oxide 230c is higher than the ratio of the number of atoms of element M contained in metal oxide 230b to the total number of atoms of all elements constituting metal oxide 230b. It is also preferable that the atomic ratio of element M contained in metal oxide 230c to In is higher than the atomic ratio of element M contained in metal oxide 230b to In.

[0218] Here, at the junctions of metal oxide 230a, metal oxide 230b, and metal oxide 230c, the energy level at the lower end of the conduction band changes smoothly. In other words, the energy level at the lower end of the conduction band at the junctions of metal oxide 230a, metal oxide 230b, and metal oxide 230c can be said to change continuously or be continuously joined. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between metal oxide 230a and metal oxide 230b, and at the interface between metal oxide 230b and metal oxide 230c.

[0219] Specifically, a mixed layer with a low defect level density can be formed by having metal oxide 230a and metal oxide 230b, and metal oxide 230b and metal oxide 230c, all having a common element other than oxygen (which serves as the main component). For example, if metal oxide 230b is In-Ga-Zn oxide, then In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc., may be used as metal oxide 230a and metal oxide 230c. Furthermore, metal oxide 230c may be in a layered structure. For example, a layered structure of In-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide, or a layered structure of In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide can be used. In other words, a layered structure of In-Ga-Zn oxide and an oxide that does not contain In may be used as metal oxide 230c.

[0220] Specifically, for metal oxide 230a, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4 or 1:1:0.5 may be used. For metal oxide 230b, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:3 or 3:1:2 may be used. For metal oxide 230c, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4, In:Ga:Zn = 4:2:3, Ga:Zn = 2:1, or Ga:Zn = 2:5 may be used. Furthermore, specific examples of layered structures for metal oxide 230c include a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], and a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide.

[0221] In this case, the main carrier pathway is metal oxide 230b. By configuring metal oxide 230a and metal oxide 230c as described above, the defect level density at the interface between metal oxide 230a and metal oxide 230b, and at the interface between metal oxide 230b and metal oxide 230c, can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 750 can obtain high on-current and high frequency characteristics. Furthermore, if metal oxide 230c is in a stacked structure, in addition to the effect of reducing the defect level density at the interface between metal oxide 230b and metal oxide 230c as described above, it is expected that the diffusion of constituent elements of metal oxide 230c to the insulator 250 side will be suppressed. More specifically, by making metal oxide 230c in a stacked structure and positioning an oxide that does not contain In on top of the stacked structure, it is possible to suppress In that could diffuse to the insulator 250 side. Since insulator 250 functions as a gate insulator, if In diffuses, it will result in poor transistor characteristics. Therefore, by using a layered structure for the metal oxide 230c, it becomes possible to provide a highly reliable display device.

[0222] A conductor 242 (conductor 242a and conductor 242b) that functions as a source electrode and a drain electrode is provided on the metal oxide 230b. It is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum as the conductor 242, or an alloy containing the above metal elements, or an alloy combining the above metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0223] By providing the conductor 242 in contact with the metal oxide 230, the oxygen concentration in the vicinity of the conductor 242 in the metal oxide 230 may be reduced. In addition, a metal compound layer containing the metal in the conductor 242 and the components of the metal oxide 230 may be formed in the vicinity of the conductor 242 in the metal oxide 230. In such a case, the carrier density increases in the region of the metal oxide 230 near the conductor 242, and this region becomes a low-resistance region.

[0224] Here, the region between the conductor 242a and the conductor 242b is formed by superimposing it on the opening of the insulator 280. This allows the conductor 260 to be positioned self-aligned between the conductor 242a and the conductor 242b.

[0225] The insulator 250 functions as a gate insulator. It is preferable that the insulator 250 be placed in contact with the upper surface of the metal oxide 230c. The insulator 250 can be silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies. In particular, silicon oxide and silicon oxide nitride are preferred because they are stable with respect to heat.

[0226] Similar to the insulator 224, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 250 is reduced. The film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0227] A metal oxide may be provided between the insulator 250 and the conductor 260. It is preferable that the metal oxide suppresses oxygen diffusion from the insulator 250 to the conductor 260. This suppresses the oxidation of the conductor 260 by oxygen from the insulator 250.

[0228] The metal oxide may function as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, it is preferable to use a metal oxide that is a high-k material with a high dielectric constant. By making the gate insulator a laminated structure of insulator 250 and the metal oxide, a laminated structure that is stable against heat and has a high dielectric constant can be made. Therefore, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it becomes possible to thin the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator.

[0229] Specifically, metal oxides containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used. In particular, it is preferable to use insulators containing oxides of aluminum, hafnium, or both, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0230] Although the conductor 260 is shown as a two-layer structure in Figure 12, it may also be a single-layer structure or a laminated structure of three or more layers.

[0231] It is preferable to use a conductor 260a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0232] The conductor 260a has the function of suppressing oxygen diffusion, thereby preventing the conductor 260b from oxidizing due to oxygen contained in the insulator 250 and reducing its conductivity. It is preferable to use a conductive material that has the function of suppressing oxygen diffusion, such as tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0233] The conductor 260b is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. The conductor 260b may also have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0234] As shown in Figures 12A and 12C, in the region of the metal oxide 230b that does not overlap with the conductor 242, in other words, in the channel-forming region of the metal oxide 230, the side surface of the metal oxide 230 is covered by the conductor 260. This makes it easier to apply the electric field of the conductor 260, which functions as the first gate electrode, to the side surface of the metal oxide 230. Therefore, the on-current of the transistor 750 can be increased and the frequency characteristics can be improved.

[0235] The insulator 254, like the insulator 214, preferably functions as a barrier insulating film that suppresses the ingress of impurities such as water or hydrogen into the transistor 750 from the insulator 280 side. For example, it is preferable that the insulator 254 has lower hydrogen permeability than the insulator 224. Furthermore, as shown in Figures 12B and 12C, it is preferable that the insulator 254 is in contact with the side surface of the metal oxide 230c, the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, the side surfaces of the metal oxide 230a and metal oxide 230b, and the top surface of the insulator 224. With this configuration, it is possible to suppress the ingress of hydrogen contained in the insulator 280 into the metal oxide 230 from the top or side surfaces of the conductor 242a, conductor 242b, metal oxide 230a, metal oxide 230b, and the insulator 224.

[0236] Furthermore, it is preferable that the insulator 254 has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule) (i.e., it is difficult for the above-mentioned oxygen to permeate through it). For example, it is preferable that the insulator 254 has lower oxygen permeability than the insulator 280 or the insulator 224.

[0237] The insulator 254 is preferably deposited using a sputtering method. By depositing the insulator 254 using a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the vicinity of the region of the insulator 224 that is in contact with the insulator 254. This allows oxygen to be supplied from this region to the metal oxide 230 via the insulator 224. Here, the insulator 254 has a function to suppress upward diffusion of oxygen, thereby preventing oxygen from diffusing from the metal oxide 230 to the insulator 280. In addition, the insulator 222 has a function to suppress downward diffusion of oxygen, thereby preventing oxygen from diffusing from the metal oxide 230 to the substrate side. In this way, oxygen is supplied to the channel formation region of the metal oxide 230. This reduces oxygen deficiency in the metal oxide 230 and suppresses normally-on formation of the transistor.

[0238] As the insulator 254, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed as a film. It is preferable to use aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) as the insulator containing an oxide of one or both of aluminum and hafnium.

[0239] The insulator 224, insulator 250, and metal oxide 230 are covered by the hydrogen barrier insulator 254, so the insulator 280 is separated from the insulator 224, metal oxide 230, and insulator 250 by the insulator 254. This prevents impurities such as hydrogen from entering the transistor 750 from the outside, thus providing the transistor 750 with good electrical characteristics and reliability.

[0240] The insulator 280 is provided on the insulator 224, the metal oxide 230, and the conductor 242 via the insulator 254. For example, the insulator 280 is preferably silicon oxide, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0241] It is preferable that the concentration of impurities such as water or hydrogen in the insulator 280 is reduced. Furthermore, the upper surface of the insulator 280 may be flattened.

[0242] The insulator 274 preferably functions as a barrier insulating film that suppresses the incorporation of impurities such as water or hydrogen into the insulator 280 from above, similar to the insulator 214. For example, the insulator 274 can be an insulator that can be used for the insulator 214, insulator 254, etc.

[0243] It is preferable to provide an insulator 281, which functions as an interlayer film, on top of the insulator 274. It is preferable that the insulator 281, like the insulator 224, has a reduced concentration of impurities such as water or hydrogen in the film.

[0244] Conductors 240a and 240b are placed in the openings formed in insulators 281, 274, 280, and 254. Conductors 240a and 240b are provided facing each other with conductor 260 in between. The height of the upper surfaces of conductors 240a and 240b may be on the same plane as the upper surface of insulator 281.

[0245] Furthermore, an insulator 241a is provided in contact with the inner wall of the opening of insulators 281, 274, 280, and 254, and a first conductive portion of conductor 240a is formed in contact with its side surface. Conductor 242a is located in at least a portion of the bottom of the opening, and conductor 240a is in contact with conductor 242a. Similarly, an insulator 241b is provided in contact with the inner wall of the opening of insulators 281, 274, 280, and 254, and a first conductive portion of conductor 240b is formed in contact with its side surface. Conductor 242b is located in at least a portion of the bottom of the opening, and conductor 240b is in contact with conductor 242b.

[0246] It is preferable that the conductors 240a and 240b are made of conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, the conductors 240a and 240b may be arranged in a laminated structure.

[0247] When the conductor 240 has a laminated structure, it is preferable to use a conductor that has the function of suppressing the diffusion of impurities such as water or hydrogen, as described above, for the conductors that come into contact with the metal oxide 230a, metal oxide 230b, conductor 242, insulator 254, insulator 280, insulator 274, and insulator 281. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. Furthermore, the conductive material that has the function of suppressing the diffusion of impurities such as water or hydrogen may be used in a single layer or a laminate. By using this conductive material, it is possible to suppress the absorption of oxygen added to the insulator 280 by the conductors 240a and 240b. In addition, it is possible to suppress the mixing of impurities such as water or hydrogen from the layer above the insulator 281 into the metal oxide 230 through the conductors 240a and 240b.

[0248] For insulators 241a and 241b, any insulator that can be used for insulator 254, for example, may be used. Since insulators 241a and 241b are provided in contact with insulator 254, it is possible to suppress the mixing of impurities such as water or hydrogen from insulator 280, etc., into the metal oxide 230 through conductors 240a and 240b. Furthermore, it is possible to suppress the absorption of oxygen contained in insulator 280 into conductors 240a and 240b.

[0249] Although not shown in the figures, conductors that function as wiring may be placed in contact with the upper surfaces of conductor 240a and conductor 240b. It is preferable that the conductors functioning as wiring are made of a conductive material mainly composed of tungsten, copper, or aluminum. Furthermore, the conductors may have a laminated structure; for example, they may be laminates of titanium or titanium nitride with the conductive material. The conductors may also be formed to be embedded in openings provided in the insulator.

[0250] <Materials that make up a transistor> This section describes the constituent materials that can be used in transistors.

[0251] [substrate] As a substrate for forming a transistor, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include silicon, germanium, and other semiconductor substrates, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides or metal oxides. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates on which elements are provided may be used. Elements provided on a substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0252] [Insulator] Insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0253] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0254] Examples of insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxide nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxide nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0255] Examples of insulators with low dielectric constant include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with voids, or resins.

[0256] Transistors using oxide semiconductors can have their electrical characteristics stabilized by surrounding them with an insulator (insulator 214, insulator 222, insulator 254, and insulator 274, etc.) that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, metal nitrides such as aluminum nitride, titanium aluminum nitride, titanium nitride, silicon oxide nitride, or silicon nitride can be used.

[0257] The insulator that functions as a gate insulator is preferably an insulator having a region containing oxygen that is desorbed by heating. For example, by having a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating is in contact with the metal oxide 230, the oxygen deficiency of the metal oxide 230 can be compensated for.

[0258] [conductor] It is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0259] Multiple conductors formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining a material containing the aforementioned metal element with a conductive material containing oxygen. Alternatively, a laminated structure may be formed by combining a material containing the aforementioned metal element with a conductive material containing nitrogen. Furthermore, a laminated structure may be formed by combining a material containing the aforementioned metal element with a conductive material containing oxygen and a conductive material containing nitrogen.

[0260] Furthermore, when using a metal oxide for the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor functioning as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to place the conductive material containing oxygen on the channel formation region side. By placing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0261] In particular, it is preferable to use a conductive material containing metal elements and oxygen contained in the metal oxide in which the channel is formed as the conductor that functions as the gate electrode. Alternatively, conductive materials containing the aforementioned metal elements and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-added indium tin oxide may be used. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen that is mixed in from an external insulator or the like.

[0262] <Classification of crystal structures in oxide semiconductors> The classification of crystal structures in oxide semiconductors will be explained using Figure 13A. Figure 13A is a diagram illustrating the classification of crystal structures in oxide semiconductors, specifically IGZO (a metal oxide containing In, Ga, and Zn).

[0263] As shown in FIG. 13A, oxide semiconductors are roughly classified into "Amorphous", "Crystalline", and "Crystal". Further, "Amorphous" includes completely amorphous. Also, "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite). Note that single crystal, poly crystal, and completely amorphous are excluded from the classification of "Crystalline". Also, "Crystal" includes single crystal and poly crystal.

[0264] Note that the structure within the thick frame shown in FIG. 13A is an intermediate state between "Amorphous" and "Crystal", and belongs to a new boundary region (New crystalline phase). That is, this structure can be rephrased as a structure that is completely different from the energetically unstable "Amorphous" or "Crystal".

[0265] Note that the crystal structure of a film or a substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Here, FIG. 13B shows the XRD spectrum obtained by grazing-incidence XRD (GIXD) measurement of a CAAC-IGZO film classified as "Crystalline". Note that the GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in FIG. 13B will be simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in FIG. 13B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in FIG. 13B is 500 nm.

[0266] In Fig. 13B, the horizontal axis is 2θ [deg.] and the vertical axis is intensity [a.u.]. As shown in Fig. 13B, in the XRD spectrum of the CAAC-IGZO film, peaks indicating clear crystallinity are detected. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected near 2θ = 31°. As shown in Fig. 13B, the peak near 2θ = 31° is asymmetric about the axis of the angle at which the peak intensity was detected.

[0267] The crystal structure of the film or substrate can be evaluated by the diffraction pattern (also referred to as the nano-beam electron diffraction pattern) observed by the nano-beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Fig. 13C. Fig. 13C is the diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Fig. 13C is near In:Ga:Zn = 4:2:3 [atomic ratio]. Also, in the nano-beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0268] As shown in Fig. 13C, in the diffraction pattern of the CAAC-IGZO film, a plurality of spots indicating c-axis orientation are observed.

[0269] 〔Structure of Oxide Semiconductor〕 Note that when focusing on the crystal structure, the oxide semiconductor may be classified differently from Fig. 13A. For example, the oxide semiconductor can be divided into a single crystal oxide semiconductor and other non-single crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Also, non-single crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), amorphous oxide semiconductors, and the like.

[0270] Here, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0271] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0272] Each of the above-mentioned crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of that crystalline region will be less than 10 nm. When a crystalline region is composed of many minute crystals, the size of that crystalline region may be around several tens of nanometers.

[0273] In In-M-Zn oxide (where element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer). Indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. The In layer may also contain element M. The In layer may also contain Zn. This layered structure can be observed, for example, as a lattice image in high-resolution TEM images.

[0274] When structural analysis of a CAAC-OS film is performed using, for example, an XRD instrument, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the peak indicating c-axis orientation (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0275] For example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0276] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to the sparse arrangement of oxygen atoms in the ab-plane direction, or because the bond distance between atoms changes due to the substitution of metal atoms.

[0277] A crystal structure in which clear grain boundaries are observed is called a polycrystal. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they suppress the generation of grain boundaries more effectively than In oxide.

[0278] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0279] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0280] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0281] [Oxide semiconductor configuration] Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition.

[0282] [CAC-OS] CAC-OS is a material composition in which, for example, the elements constituting the metal oxide are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing the metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0283] Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (hereinafter also referred to as a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0284] Here, the atomic number ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0285] Specifically, the above-mentioned first region is a region mainly composed of indium oxide, indium zinc oxide, etc. Also, the above-mentioned second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the above-mentioned first region can be rephrased as a region mainly composed of In. Also, the above-mentioned second region can be rephrased as a region mainly composed of Ga.

[0286] Note that there may be cases where no clear boundary can be observed between the above-mentioned first region and the above-mentioned second region.

[0287] For example, in the CAC-OS of In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0288] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I) can be achieved. on ), high field-effect mobility (μ), and good switching operation can be achieved.

[0289] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0290] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0291] By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors.

[0292] It is preferable to use an oxide semiconductor with a low carrier concentration for the transistor. For example, the carrier concentration of an oxide semiconductor is 1 × 10⁻⁶. 17 cm -3 The following is preferably 1 × 10 15 cm -3 More preferably 1 × 10 13 cm -3 More preferably 1 × 10 11 cm -3 More preferably 1 × 10 10 cm -3 It is less than 1 × 10 -9 cm-3 This concludes the explanation. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film should be lowered to reduce the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors with low carrier concentrations are sometimes referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors.

[0293] High-purity intrinsic or substantially high-purity intrinsic oxide semiconductor films have a low defect level density, which may result in a low trap level density.

[0294] Charges trapped in the trap levels of oxide semiconductors can take a long time to disappear and sometimes behave like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high density of trap levels may exhibit unstable electrical properties.

[0295] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0296] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0297] In oxide semiconductors, the presence of silicon or carbon, which are Group 14 elements, leads to the formation of defect levels in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (concentration obtained by SIMS) are 2 × 10⁻¹⁰. 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0298] When alkali metals or alkaline earth metals are present in oxide semiconductors, they can form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, the concentration of alkali metals or alkaline earth metals in the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0299] In oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in oxide semiconductors obtained by SIMS should be set to 5 × 10⁻¹⁰. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 Do the following:

[0300] Hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. When hydrogen fills these vacancies, electrons, which act as carriers, can be generated. Furthermore, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to reduce the hydrogen content in oxide semiconductors as much as possible. Specifically, in oxide semiconductors, the hydrogen concentration obtained by SIMS should be 1 × 10⁻⁶.20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0301] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0302] <Example configuration of display element 61> The EL layer 786 of the display element 61 can be composed of multiple layers, such as layer 4420, light-emitting layer 4411, and layer 4430, as shown in Figure 14A. Layer 4420 may include, for example, a layer containing a material with high electron injection properties (electron injection layer) and a layer containing a material with high electron transport properties (electron transport layer). Light-emitting layer 4411 may contain, for example, a light-emitting compound. Layer 4430 may include, for example, a layer containing a material with high hole injection properties (hole injection layer) and a layer containing a material with high hole transport properties (hole transport layer).

[0303] A configuration having a layer 4420, an emissive layer 4411, and a layer 4430 provided between a pair of electrodes can function as a single emissive unit, and in this specification, the configuration shown in Figure 14A is referred to as a single structure.

[0304] Furthermore, Figure 14B shows a modified example of the EL layer 786 of the display element 61 shown in Figure 14A. Specifically, the display element 61 shown in Figure 14B includes a layer 4430-1 on a conductor 772, a layer 4430-2 on layer 4430-1, a light-emitting layer 4411 on layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on layer 4420-1, and a conductor 788 on layer 4420-2. For example, when the conductor 772 is the anode and the conductor 788 is the cathode, layer 4430-1 functions as a hole injection layer, layer 4430-2 functions as a hole transport layer, layer 4420-1 functions as an electron transport layer, and layer 4420-2 functions as an electron injection layer. Alternatively, when conductor 772 is used as the cathode and conductor 788 as the anode, layer 4430-1 functions as an electron injection layer, layer 4430-2 functions as an electron transport layer, layer 4420-1 functions as a hole transport layer, and layer 4420-2 functions as a hole injection layer. This layer structure allows for efficient injection of carriers into the light-emitting layer 4411 and improves the efficiency of carrier recombination within the light-emitting layer 4411.

[0305] Furthermore, as shown in Figure 14C, a configuration in which multiple light-emitting layers (light-emitting layers 4411, 4412, and 4413) are provided between layer 4420 and layer 4430 is also a variation of the single structure.

[0306] Furthermore, as shown in Figure 14D, a configuration in which multiple light-emitting units (EL layers 786a, 786b) are connected in series via an intermediate layer (charge generation layer) 4440 is referred to as a tandem structure in this specification. In this specification, the configuration shown in Figure 14D is referred to as a tandem structure, but it is not limited to this, and for example, a tandem structure may also be called a stacked structure. By using a tandem structure, a light-emitting element capable of high-brightness emission can be made.

[0307] Furthermore, in Figures 14C and 14D, as shown in Figure 14B, layer 4420 and layer 4430 may be a laminated structure consisting of two or more layers.

[0308] The light-emitting color of the display element 61 can be red, green, blue, cyan, magenta, yellow, or white, depending on the material constituting the EL layer 786. Furthermore, the color purity can be further enhanced by adding a microcavity structure to the display element 61.

[0309] A light-emitting element that emits white light preferably has a configuration that includes two or more types of light-emitting materials in the light-emitting layer. To obtain white light emission, light-emitting materials should be selected such that the light emitted by each of the two or more materials is complementary in color.

[0310] The light-emitting layer preferably contains two or more light-emitting materials that emit light such as R (red), G (green), B (blue), Y (yellow), and O (orange). Alternatively, it is preferable that the layer contains two or more light-emitting materials, and the light emitted by each light-emitting material contains spectral components of two or more colors from R, G, and B.

[0311] <Method for forming the display element 61> The following describes the method for forming the display element 61.

[0312] Figure 15A shows schematic top views of display elements 61_R, 61_G, and 61_B that can be applied to the display element 61. Display element 61_R is a light-emitting element that emits red light, display element 61_G is a light-emitting element that emits green light, and display element 61_B is a light-emitting element that emits blue light. In Figure 15A, the symbols R, G, and B are added within the light-emitting area of ​​each light-emitting element to simplify the distinction between them. The configuration shown in Figure 15A may also be called an SBS (Side By Side) structure. Furthermore, although the configuration shown in Figure 15A is exemplified as having three colors, red (R), green (G), and blue (B), it is not limited to this. For example, a configuration with four or more colors may also be used.

[0313] The display elements 61_R, 61_G, and 61_B are each arranged in a matrix. Figure 15A shows a so-called stripe arrangement, in which light-emitting elements of the same color are arranged in one direction. Note that the arrangement method of the light-emitting elements is not limited to this; other arrangement methods such as delta arrangement and zigzag arrangement may be applied, and pentile arrangement can also be used.

[0314] As the display elements 61_R, 61_G, and 61_B, it is preferable to use organic EL devices such as OLED (Organic Light Emitting Diode) or QLED (Quantum-dot Light Emitting Diode). Examples of light-emitting materials for EL elements include fluorescent materials, phosphorescent materials, inorganic compounds (such as quantum dot materials), and thermally activated delayed fluorescence (TADF) materials.

[0315] Figure 15B is a schematic cross-sectional view corresponding to the dashed line A1-A2 in Figure 15A.

[0316] Figure 15B shows cross-sections of the display elements 61_R, 61_G, and 61_B. Each of the display elements 61_R, 61_G, and 61_B is provided on the substrate 751 and has a conductor 772 that functions as a pixel electrode and a conductor 788 that functions as a common electrode.

[0317] Display element 61_R has an EL layer 786R between conductor 772 and conductor 788. The EL layer 786R has a light-emitting organic compound that emits light having a peak in at least the red wavelength range. The EL layer 786G of display element 61_G has a light-emitting organic compound that emits light having a peak in at least the green wavelength range. The EL layer 786B of display element 61_B has a light-emitting organic compound that emits light having a peak in at least the blue wavelength range.

[0318] Each of the EL layers 786R, 786G, and 786B may have, in addition to a layer containing a light-emitting organic compound (light-emitting layer), one or more of the following: an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.

[0319] A conductor 772 is provided for each light-emitting element. A conductor 788 is provided as a continuous layer common to each light-emitting element. A conductive film that is transparent to visible light is used for either the conductor 772 or the conductor 788 which functions as a common electrode, and a conductive film that is reflective is used for the other. By making the conductor 772 transparent and the conductor 788 reflective, a bottom-emission type display device can be made. Conversely, by making the conductor 772 reflective and the conductor 788 transparent, a top-emission type display device can be made. Furthermore, by making both the conductor 772 and the conductor 788 transparent, a dual-emission type display device can be made.

[0320] An insulating layer 755 is provided covering the end of the conductor 772. Preferably, the end of the insulating layer 755 is tapered.

[0321] Each of the EL layers 786R, 786G, and 786B has a region in contact with the upper surface of the conductor 772 and a region in contact with the surface of the insulating layer 755. The edges of the EL layers 786R, 786G, and 786B are located on the insulating layer 755.

[0322] As shown in Figure 15B, a gap is provided between the two EL layers between light-emitting elements of different colors. It is preferable that the EL layers 786R, 786G, and 786B are arranged so that they do not touch each other. This effectively prevents current from flowing through two adjacent EL layers, which can cause unintended light emission (also known as crosstalk). Therefore, contrast can be enhanced, and a display device with high display quality can be realized.

[0323] EL layer 786R, EL layer 786G, and EL layer 786B can be fabricated separately using methods such as vacuum deposition with a shadow mask like a metal mask. Alternatively, they may be fabricated separately using photolithography. By using photolithography, it is possible to realize a display device with high resolution that is difficult to achieve when using a metal mask.

[0324] Furthermore, a protective layer 756 is provided on the conductive material 788, covering the display elements 61_R, 61_G, and 61_B. The protective layer 756 has the function of preventing impurities such as water from diffusing to each light-emitting element from above.

[0325] The protective layer 756 can be, for example, a single-layer structure or a multilayer structure including at least an inorganic insulating film. Examples of inorganic insulating films include oxide films or nitride films such as silicon oxide films, silicon oxide nitride films, silicon nitride films, silicon nitride films, aluminum oxide films, aluminum oxide nitride films, and hafnium oxide films. Alternatively, semiconductor materials such as indium gallium oxide and indium gallium zinc oxide may be used as the protective layer 756. The protective layer 756 may be formed using ALD, CVD, and sputtering methods. Although the example shows a configuration including an inorganic insulating film as the protective layer 756, it is not limited to this. For example, the protective layer 756 may be a multilayer structure of an inorganic insulating film and an organic insulating film.

[0326] Figure 15C shows a different example from the one described above.

[0327] Figure 15C shows a display element 61_W that emits white light. The display element 61_W has an EL layer 786W that emits white light between a conductor 772 and a conductor 788.

[0328] The EL layer 786W can be configured, for example, by stacking two or more light-emitting layers selected so that their respective emission colors are complementary. Alternatively, a stacked EL layer, a so-called tandem structure EL layer, can be used, in which a charge generation layer is sandwiched between the light-emitting layers. By using a tandem structure, a light-emitting element capable of high-brightness emission can be created.

[0329] Figure 15C shows three display elements 61_W arranged side by side. A colored layer 757R is provided on the top of the left display element 61_W. The colored layer 757R functions as a bandpass filter that transmits red light. Similarly, a colored layer 757G that transmits green light is provided on the top of the center display element 61_W, and a colored layer 757B that transmits blue light is provided on the top of the right display element 61_W. As a result, the display device can display a color image.

[0330] Here, the EL layer 786W and the conductor 788 are separated between two adjacent display elements 61_W. This effectively prevents current from flowing through the EL layer 786W between two adjacent display elements 61_W, thus preventing unintended light emission. In particular, when a stacked EL element is used as the EL layer 786W, in which a charge generation layer is provided between two light-emitting layers, the effect of crosstalk becomes more pronounced as the resolution increases, i.e., the distance between adjacent pixels decreases, resulting in a decrease in contrast. Therefore, this configuration makes it possible to realize a display device that combines high resolution and high contrast.

[0331] It is preferable to separate the EL layer 786W and the conductor 788 by photolithography. This allows for a narrower spacing between light-emitting elements, enabling the realization of a display device with a higher aperture ratio compared to cases where a shadow mask such as a metal mask is used.

[0332] In the case of a bottom-emission type light-emitting element, a colored layer can be provided between the conductor 772 and the substrate 751.

[0333] Figure 15D shows a different example from the above. Specifically, Figure 15D shows a configuration in which the insulating layer 755 is not provided between the display elements 61_R, 61_G, and 61_B. This configuration allows for a display device with a high aperture ratio. In addition, the protective layer 756 covers the sides of the display elements 61_R, 61_G, and 61_B. This configuration suppresses impurities (typically water, etc.) that could enter from the sides of the display elements 61_R, 61_G, and 61_B. Furthermore, in the configuration shown in Figure 15D, the top surface shapes of the conductor 772, the EL layer 786R, and the conductor 788 are roughly the same. Such a structure can be formed all at once using a resist mask or the like after the conductor 772, the EL layer 786R, and the conductor 788 have been formed. This process, which involves processing the EL layer 786R and the conductor 753 using the conductor 788 as a mask, can also be called self-aligned patterning. Although the display element 61_R has been described here, the same configuration can be used for the display elements 61_G and 61_B.

[0334] Furthermore, in Figure 15D, a protective layer 758 is provided on top of the protective layer 756. For example, by forming the protective layer 756 using an apparatus capable of forming a highly covering film (typically an ALD apparatus, etc.) and forming the protective layer 758 using an apparatus capable of forming a film with lower covering properties than the protective layer 756 (typically a sputtering apparatus, etc.), a gap 759 can be provided between the protective layer 756 and the protective layer 758. In other words, the gap 759 is located between the display element 61_R and the display element 61_G, and between the display element 61_G and the display element 61_B.

[0335] The void 759 contains one or more of the following: air, nitrogen, oxygen, carbon dioxide, and Group 18 elements (typically helium, neon, argon, xenon, krypton, etc.). Furthermore, the void 759 may contain gases used during the deposition of the protective layer 758. For example, when the protective layer 758 is deposited by sputtering, the void 759 may contain one or more of the aforementioned Group 18 elements. If the void 759 contains gas, the gas can be identified by gas chromatography or other methods. Alternatively, when the protective layer 758 is deposited by sputtering, the protective layer 758 may also contain gases used during sputtering. In this case, elements such as argon may be detected when the protective layer 758 is analyzed by energy-dispersive X-ray spectroscopy (EDX analysis).

[0336] Furthermore, if the refractive index of the air gap 759 is lower than that of the protective layer 756, the light emitted from the display element 61_R, display element 61_G, or display element 61_B will be reflected at the interface between the protective layer 756 and the air gap 759. This suppresses the incidence of light emitted from the display element 61_R, display element 61_G, or display element 61_B on adjacent pixels. This suppresses the mixing of light of different colors, thereby improving the image quality of the display device.

[0337] In the configuration shown in Figure 15D, the region between display element 61_R and display element 61_G, or the region between display element 61_G and display element 61_B (hereinafter simply referred to as the distance between light-emitting elements) can be narrowed. Specifically, the distance between light-emitting elements can be 1 μm or less, preferably 500 nm or less, and more preferably 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm. In other words, the distance between the side surface of display element 61_R and the side surface of display element 61_G, or the distance between the side surface of display element 61_G and the side surface of display element 61_B, has a region of 1 μm or less, preferably a region of 0.5 μm (500 nm) or less, and more preferably a region of 100 nm or less.

[0338] Furthermore, for example, if the gap 759 contains air, the configuration shown in Figure 15D can be called an air isolation structure. By having an air isolation structure, it is possible to isolate the light-emitting elements while suppressing color mixing or crosstalk of light from each light-emitting element.

[0339] Figure 16A shows a different example from the one described above. Specifically, the configuration shown in Figure 16A differs from the configuration shown in Figure 15D in the configuration of the substrate 751. When the display elements 61_R, 61_G, and 61_B are processed, a portion of the top surface of the substrate 751 is shaved off, creating a recess. A protective layer 756 is formed in this recess. In other words, in a cross-sectional view, the lower surface of the protective layer 756 is located below the lower surface of the conductor 772 in a certain region. Having this region effectively suppresses impurities (typically water, etc.) that could enter the display elements 61_R, 61_G, and 61_B from below. The recess can be formed when impurities (also called residues) that may adhere to the sides of each light-emitting element during processing of the display elements 61_R, 61_G, and 61_B are removed by wet etching or the like. After removing the above-mentioned residue, a highly reliable display device can be created by covering the sides of each light-emitting element with a protective layer 756.

[0340] Figure 16B shows a different example from the above. Specifically, the configuration shown in Figure 16B includes an insulating layer 776 and a microlens array 777 in addition to the configuration shown in Figure 16A. The insulating layer 776 functions as an adhesive layer. When the refractive index of the insulating layer 776 is lower than that of the microlens array 777, the microlens array 777 can concentrate the light emitted from the display elements 61_R, 61_G, and 61_B. This can improve the light extraction efficiency of the display device. This is particularly suitable when the user views the display surface from the front of the display surface of the display device, as a bright image can be seen. Various types of curing adhesives can be used as the insulating layer 776, such as UV-curing adhesives, reaction-curing adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. Materials with low moisture permeability, such as epoxy resins, are particularly preferred. Two-component mixed resins may also be used. Adhesive sheets may also be used.

[0341] <Number of slots for display device 10> The number of display devices that can be fabricated on a single substrate was estimated when a 12-inch Si wafer was used as substrate 11. Table 1 shows the specifications used for the estimation. The distance between areas defined by the pixel size (2.64 × 7.92 μm) is estimated to be 0.55 μm when the pixel arrangement is an RGB stripe.

[0342] [Table 1]

[0343] Figure 17A shows a layout diagram of a display device 10A that can be fabricated on a substrate 100A, which is a 12-inch Si wafer. 72 display devices 10A can be fabricated on a single 12-inch Si wafer substrate.

[0344] In addition, Figure 17A shows a layout diagram of a display device 10 that can be fabricated on a rectangular 5-inch Si wafer substrate 100B. Two display devices 10 can be fabricated on the 5-inch Si wafer substrate 100B.

[0345] Figure 17B illustrates the layout of the display device 10 fabricated on a 5-inch Si wafer substrate 100B. As shown in Figure 17B, the area 102 corresponding to the screen size has an aspect ratio of 4:3 and measures 1.5 inches. The area 102 is also provided with terminal sections 106A and 106B at the top and bottom for connection to the FPC. In Figure 17B, arrows 103 and 104 represent the width (margin) for sealing each element of the display device 10, with arrow 105 representing 6.6 mm and arrow 105 representing the width of terminal sections 106A and 106B.

[0346] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0347] (Embodiment 3) This embodiment describes electronic equipment to which a display device according to one aspect of the present invention can be applied.

[0348] A display device according to one aspect of the present invention can be suitably used in portable electronic devices, wearable electronic devices, and e-book terminals. It can also be suitably used in VR (Virtual Reality) devices, AR (Augmented Reality) devices, and the like.

[0349] Figure 18A shows the external appearance of the head-mounted display 8200.

[0350] The head-mounted display 8200 includes a mounting section 8201, lenses 8202, a main unit 8203, a display unit 8204, a cable 8205, etc. The mounting section 8201 also has a built-in battery 8206.

[0351] Cable 8205 supplies power from battery 8206 to main unit 8203. Main unit 8203 is equipped with a wireless receiver and can display images corresponding to received image data on display unit 8204. In addition, a camera provided on main unit 8203 captures the movement of the user's eyeballs or eyelids, and by calculating the coordinates of the user's gaze based on that information, the user's gaze can be used as an input means.

[0352] The attachment part 8201 may have multiple electrodes positioned to come into contact with the user. The main unit 8203 may have a function to recognize the user's gaze by detecting the current flowing through the electrodes in accordance with the user's eye movements. It may also have a function to monitor the user's pulse by detecting the current flowing through the electrodes. Furthermore, the attachment part 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function to display the user's biometric information on the display unit 8204. It may also detect the user's head movements and change the image displayed on the display unit 8204 in accordance with those movements.

[0353] A display device according to one embodiment of the present invention can be applied to the display unit 8204. This reduces the power consumption of the head-mounted display 8200, allowing it to be used continuously for a long period of time. Furthermore, by reducing the power consumption of the head-mounted display 8200, the battery 8206 can be made smaller and lighter, thus making the head-mounted display 8200 smaller and lighter. This reduces the burden on the user of the head-mounted display 8200, making it less likely for the user to experience fatigue.

[0354] Figures 18B, 18C, and 18D show the external appearance of the head-mounted display 8300. The head-mounted display 8300 comprises a housing 8301, a display unit 8302, a band-shaped fixing device 8304, and a pair of lenses 8305. The housing 8301 also has a built-in battery 8306, which can supply power to the display unit 8302 and other components.

[0355] The user can view the display on the display unit 8302 through the lens 8305. It is preferable to position the display unit 8302 in a curved shape. By positioning the display unit 8302 in a curved shape, the user can experience a high degree of realism. In this embodiment, a configuration with one display unit 8302 has been illustrated, but the system is not limited to this, and for example, a configuration with two display units 8302 may be used. In this case, if one display unit is positioned for each eye of the user, it becomes possible to perform 3D display using parallax, etc.

[0356] Furthermore, the display device described above can be applied to the display unit 8302. This reduces the power consumption of the head-mounted display 8300, allowing it to be used continuously for extended periods. In addition, by reducing the power consumption of the head-mounted display 8300, the battery 8306 can be made smaller and lighter, thus making the head-mounted display 8300 smaller and lighter. This reduces the burden on the user of the head-mounted display 8300, making it less likely for the user to experience fatigue.

[0357] Next, Figures 19A and 19B show the electronic equipment shown in Figures 18A to 18D, as well as an example of a different electronic equipment.

[0358] The electronic device shown in Figures 19A and 19B includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), connection terminals 9006, sensors 9007 (including functions for measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation), and a battery 9009, etc.

[0359] The electronic devices shown in Figures 19A and 19B have a variety of functions. For example, they may have functions to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to control processing by various software (programs), a wireless communication function, a function to connect to various computer networks using wireless communication, a function to transmit or receive various data using wireless communication, a function to read programs or data recorded on a recording medium and display them on a display unit, etc. However, the functions that the electronic devices shown in Figures 19A and 19B may have are not limited to these, and they may have a variety of functions. In addition, although not shown in Figures 19A and 19B, the electronic devices may have a configuration with multiple display units. Furthermore, the electronic devices may be equipped with a camera, etc., and have functions to capture still images, capture videos, save captured images to a recording medium (external or built into the camera), display captured images on a display unit, etc.

[0360] The details of the electronic equipment shown in Figures 19A and 19B will be explained below.

[0361] Figure 19A is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 has one or more functions selected from, for example, a telephone, a notebook, or an information viewing device. Specifically, it can be used as a smartphone. The portable information terminal 9101 can also display text or images on multiple surfaces. For example, three operation buttons 9050 (also called operation icons or simply icons) can be displayed on one surface of the display unit 9001. Information 9051, shown by a dashed rectangle, can also be displayed on other surfaces of the display unit 9001. Examples of information 9051 include notifications of incoming emails, SNS (Social Networking Service) messages, or phone calls, the subject of emails or SNS messages, the sender's name of emails or SNS messages, the date and time, the battery level, or the antenna signal strength. Alternatively, operation buttons 9050 or the like may be displayed in place of the information 9051.

[0362] The above-described display device can be applied to the personal digital assistant (PAD) 9101. This reduces the power consumption of the PAD 9101, allowing it to be used continuously for extended periods. Furthermore, by reducing the power consumption of the PAD 9101, the battery 9009 can be made smaller and lighter, thus making the PAD 9101 smaller and lighter. This improves the portability of the PAD 9101.

[0363] Figure 19B is a perspective view showing a wristwatch-type personal information terminal 9200. The personal information terminal 9200 can run various applications such as mobile phone calls, email, document viewing and creation, music playback, internet communication, and computer games. The display unit 9001 has a curved display surface, allowing it to display information along the curved surface. Figure 19B shows an example where the time 9251, operation buttons 9252 (also called operation icons or simply icons), and content 9253 are displayed on the display unit 9001. The content 9253 can be, for example, a video.

[0364] Furthermore, the personal information terminal 9200 is capable of performing standardized short-range wireless communication. For example, it can communicate with a wireless communication-enabled headset to make hands-free calls. The personal information terminal 9200 also has a connection terminal 9006, which allows it to directly exchange data with other information terminals via a connector. It can also be charged via the connection terminal 9006. However, charging may be performed by wireless power supply without using the connection terminal 9006.

[0365] The above-described display device can be applied to the personal digital assistant (PAD) 9200. This reduces the power consumption of the PAD, allowing it to be used continuously for extended periods. Furthermore, by reducing the power consumption of the PAD, the battery 9009 can be made smaller and lighter, thus making the PAD 9200 smaller and lighter. This improves the portability of the PAD 9200.

[0366] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0367] <Notes regarding the description in this specification, etc.> The above embodiments and a description of each component in those embodiments are provided below.

[0368] The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Furthermore, if multiple configuration examples are shown within a single embodiment, these configuration examples can be appropriately combined.

[0369] Furthermore, the content described in one embodiment (even if only a part of it) can be applied to, combined with, or substituted for other content described in the same embodiment (even if only a part of it), and / or content described in one or more other embodiments (even if only a part of it).

[0370] The content described in the embodiments refers to the content described using various figures or the content described using text in the specification in each embodiment.

[0371] Furthermore, a diagram (even a part of it) described in one embodiment can be combined with another part of that diagram, another diagram (even a part of it) described in that embodiment, and / or a diagram (even a part of it) described in one or more other embodiments to form even more diagrams.

[0372] Furthermore, in this specification, block diagrams classify components by function and show them as independent blocks. However, in actual circuits, it is difficult to separate components by function, and there may be cases where multiple functions are involved in a single circuit, or where a single function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, and can be appropriately rephrased depending on the situation.

[0373] Furthermore, in the drawings, the size, layer thickness, or area are shown at arbitrary sizes for the sake of explanation. Therefore, they are not necessarily limited to that scale. Also, the drawings are schematic for clarity and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0374] In this specification and other documents, when describing the connections of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the transistor's structure or operating conditions. The terms source and drain of a transistor can be appropriately rephrased as source (drain) terminal or source (drain) electrode, depending on the context.

[0375] Furthermore, in this specification, the terms "electrode" or "wiring" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" or "wiring" also include cases where multiple "electrodes" and "wiring" are formed as a single unit.

[0376] Furthermore, in this specification, voltage and potential may be used interchangeably as appropriate. Voltage is the potential difference from a reference potential; for example, if the reference potential is the ground voltage (earth voltage), then voltage can be replaced with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and depending on the reference potential, it may change the potential applied to wiring, etc.

[0377] In this specification, terms such as "film" and "layer" may be interchanged depending on the context or situation. For example, the term "conductive layer" may be changed to "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer."

[0378] In this specification, a switch refers to a device that has the function of controlling whether or not to allow current to flow by being in a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to a device that has the function of selecting and switching the path through which current flows.

[0379] In this specification, channel length refers, for example, to the distance between the source and drain in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate overlap in a top view of a transistor, or in the region where the channel is formed.

[0380] In this specification, channel width refers, for example, to the length of the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or the region in which the channel is formed, where the source and drain face each other.

[0381] In this specification, "A and B are connected" includes not only those that are directly connected, but also those that are electrically connected. Here, "electrically connected" means that when there is an object between A and B that has some kind of electrical effect, it enables the exchange of electrical signals between A and B.

[0382] In this specification, a structure in which different light-emitting layers are created or painted for each color of light-emitting device (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. Also, in this specification, a light-emitting device capable of emitting white light may be referred to as a white light-emitting device. A white light-emitting device can be combined with a colored layer (for example, a color filter) to become a full-color display light-emitting device.

[0383] Furthermore, light-emitting devices can be broadly classified into single-structure and tandem-structure devices. A single-structure device has one light-emitting unit between a pair of electrodes, and it is preferable that this light-emitting unit includes one or more light-emitting layers. To obtain white light emission, one should select light-emitting layers such that the light emitted from each of the two or more layers is complementary in color. For example, by making the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer complementary, a configuration that emits white light as a whole can be obtained. The same applies to light-emitting devices having three or more light-emitting layers.

[0384] A tandem device preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission, the device should be configured such that the light from the light-emitting layers of the multiple light-emitting units is combined to produce white light emission. The configuration for obtaining white light emission is the same as that for a single-structure device. In a tandem device, it is preferable to provide an intermediate layer, such as a charge-generating layer, between the multiple light-emitting units.

[0385] Furthermore, when comparing the aforementioned white light-emitting devices (single or tandem structure) with SBS structure light-emitting devices, SBS structure light-emitting devices can consume less power than white light-emitting devices. If you want to keep power consumption low, it is preferable to use SBS structure light-emitting devices. On the other hand, white light-emitting devices are preferable because their manufacturing process is simpler than that of SBS structure light-emitting devices, which can lead to lower manufacturing costs or higher manufacturing yields. [Explanation of Symbols]

[0386] 10: Display device, 11: Substrate, 12: Substrate, 13: Display unit, 14: Terminal unit, 20: Layer, 21: Transistor, 22: Channel formation region, 30: Driving circuit, 40: Functional circuit, 50: Layer, 51: Pixel circuit, 52: Transistor, 54: Channel formation region, 60: Layer, 61: Display element

Claims

1. It has a first layer, a second layer, and a third layer, The first layer, the second layer, and the third layer are each provided in different layers. The first layer comprises a drive circuit and a function circuit, The second layer described above has a pixel circuit, The third layer comprises a first display element, a second display element, a first protective layer, and a second protective layer. The pixel circuit has a function of controlling the light emission of the first display element or the second display element. The drive circuit has a function of controlling the pixel circuit, The aforementioned functional circuit has the function of controlling the drive circuit, The first display element comprises a first conductor provided on an insulator, a first EL layer on the first conductor, and a second conductor on the first EL layer. The second display element comprises a third conductor provided on the insulator, a second EL layer on the third conductor, and a fourth conductor on the second EL layer. The first protective layer has a first portion in contact with the side surface of the first conductor, a second portion in contact with the side surface of the first EL layer, a third portion in contact with the side surface of the second conductor, a fourth portion in contact with the upper surface of the second conductor, a fifth portion in contact with the upper surface of the insulator between the first display element and the second display element, a sixth portion in contact with the side surface of the third conductor, a seventh portion in contact with the side surface of the second EL layer, an eighth portion in contact with the side surface of the fourth conductor, and a ninth portion in contact with the upper surface of the fourth conductor. The second protective layer has a region in contact with the upper surface of the fourth portion of the first protective layer and a region in contact with the upper surface of the ninth portion of the first protective layer. A display device having a gap between the first protective layer and the second protective layer.

2. It has a first layer, a second layer, and a third layer, The first layer, the second layer, and the third layer are each provided in different layers. The first layer comprises a drive circuit and a function circuit, The second layer described above has a pixel circuit, The third layer comprises a first display element, a second display element, a first protective layer, and a second protective layer. The first layer has a first transistor having a semiconductor layer with silicon in the channel formation region, The second layer has a second transistor having a semiconductor layer with a metal oxide in the channel formation region. In a cross-sectional view, the semiconductor layer having the metal oxide has a region that overlaps with the semiconductor layer having silicon. The pixel circuit has a function of controlling the light emission of the first display element or the second display element. The drive circuit has a function of controlling the pixel circuit, The aforementioned functional circuit has the function of controlling the drive circuit, The first display element comprises a first conductor provided on an insulator, a first EL layer on the first conductor, and a second conductor on the first EL layer. The second display element comprises a third conductor provided on the insulator, a second EL layer on the third conductor, and a fourth conductor on the second EL layer. The first protective layer has a first portion in contact with the side surface of the first conductor, a second portion in contact with the side surface of the first EL layer, a third portion in contact with the side surface of the second conductor, a fourth portion in contact with the upper surface of the second conductor, a fifth portion in contact with the upper surface of the insulator between the first display element and the second display element, a sixth portion in contact with the side surface of the third conductor, a seventh portion in contact with the side surface of the second EL layer, an eighth portion in contact with the side surface of the fourth conductor, and a ninth portion in contact with the upper surface of the fourth conductor. The second protective layer has a region in contact with the upper surface of the fourth portion of the first protective layer and a region in contact with the upper surface of the ninth portion of the first protective layer. A display device having a gap between the first protective layer and the second protective layer.

3. In claim 2, The metal oxide is a display device comprising In, element M (where M is Al, Ga, Y, or Sn), and Zn.

4. In any one of claims 1 to 3, A display device in which the void has one or more selected from air, nitrogen, oxygen, carbon dioxide, helium, neon, argon, xenon, krypton, etc.

5. In claim 4, The aforementioned pixel circuit is provided divided into multiple regions, One of the aforementioned multiple regions includes a source driver circuit and a gate driver circuit. The aforementioned source driver circuit has multiple source lines electrically connected, The gate driver circuit is a display device in which multiple gate lines are electrically connected.

6. A display device according to any one of claims 1 to 5, An electronic device including a mounting fixture, a pair of lenses, and a battery.

Images