Signal acquisition circuit and wearable device

Abstract

To provide a signal collection circuit that reduce influence of parasitic capacitance on signal collection and a wearable device.SOLUTION: A signal collection circuit 200 includes a difference amplifier 230, a first electrode 210, a second electrode 220, a first negative capacitance circuit C10, and a second negative capacitance circuit C20. The first electrode is connected to a first input end of a difference amplifier via a first lead wire L1, and the second electrode is connected to a second input end of the difference amplifier via a second lead wire L2. The first negative capacitance circuit is electrically connected to the first lead wire and a ground line, the second negative capacitance circuit is electrically connected to the second lead wire and the ground line, and both circuits have a negative capacitance effect. The signal collection circuit may further include a third negative capacitance circuit C30. The third negative capacitance circuit is electrically connected between the first lead wire and the second lead wire and being connected in parallel to inter-lead parasitic capacitance C3.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] This application relates to the field of circuit design, particularly to signal acquisition circuits and wearable devices.

Background Art

[0002] In conventional bioelectric (such as electrocardiogram, electromyogram, etc.) signal acquisition circuits, since the common-mode commercial frequency signal is converted into differential-mode commercial frequency noise and input to the amplifier, the signal-to-noise ratio decreases, and as a result, the circuit often saturates and fails. Thus, a large input impedance is required to reduce commercial frequency interference. However, in an actual circuit, parasitic capacitance often reduces the input impedance of the circuit and further deteriorates commercial frequency interference. That is, due to the existence of parasitic capacitance, the effect of bioelectric signal acquisition is limited.

[0003] Therefore, it is desired to provide a signal acquisition circuit and a wearable device that can reduce the influence of parasitic capacitance on signal acquisition.

Summary of the Invention

Means for Solving the Problems

[0004] The signal acquisition circuit according to an embodiment of this application includes a differential amplifier, a first electrode and a second electrode, and a first negative capacitance circuit and a second negative capacitance circuit. The first electrode is connected to the first input end of the differential amplifier via a first lead wire, the second electrode is connected to the second input end of the differential amplifier via a second lead wire, the first negative capacitance circuit is electrically connected to the first lead wire and the ground wire, the second negative capacitance circuit is electrically connected to the second lead wire and the ground wire, and both the first negative capacitance circuit and the second negative capacitance circuit have a negative capacitance effect.

[0005] In some embodiments, the relative error between the absolute value of the equivalent capacitance of the first negative capacitance circuit and the parasitic capacitance of the first lead wire to ground is less than 50%, and the relative error between the absolute value of the equivalent capacitance of the second negative capacitance circuit and the parasitic capacitance of the second lead wire to ground is less than 50%.

[0006] In some embodiments, a first equivalent input capacitance exists at the first input terminal of the differential amplifier, a second equivalent input capacitance exists at the second input terminal of the differential amplifier, the relative error between the absolute value of the equivalent capacitance of the first negative capacitance circuit and the sum of the parasitic capacitance of the first lead wire to ground and the first equivalent input capacitance is less than 50%, and the relative error between the absolute value of the equivalent capacitance of the second negative capacitance circuit and the sum of the parasitic capacitance of the second lead wire to ground and the second equivalent input capacitance is less than 50%.

[0007] In some embodiments, the circuit further includes a third negative capacitance circuit, which is electrically connected to the first lead wire and the second lead wire and has a negative capacitance effect.

[0008] In some embodiments, the relative error between the absolute value of the equivalent capacitance of the third negative capacitance circuit and the parasitic capacitance between the first lead wire and the second lead wire is less than 50%.

[0009] In some embodiments, the first negative capacitance circuit includes a first operational amplifier, a first resistor, a second resistor, and a first capacitor; the second negative capacitance circuit includes a second operational amplifier, a third resistor, a fourth resistor, and a second capacitor; the first operational amplifier has an inverting input terminal grounded through the first resistor and connected to the output terminal of the first operational amplifier via the second resistor, and a non-inverting input terminal connected to the output terminal of the first operational amplifier via the first capacitor; the second operational amplifier has an inverting input terminal grounded through the third resistor and connected to the output terminal of the second operational amplifier via the fourth resistor, and a non-inverting input terminal connected to the output terminal of the second operational amplifier via the second capacitor.

[0010] In some embodiments, the non-inverting input terminal of the first operational amplifier is connected to the first lead wire, and the non-inverting input terminal of the second operational amplifier is connected to the second lead wire.

[0011] In some embodiments, the circuit further includes a feedback control circuit that adjusts the equivalent capacitance values ​​of the first negative capacitance circuit and the second negative capacitance circuit.

[0012] In some embodiments, the input impedance of the differential amplifier is greater than 100 megaohms.

[0013] In some embodiments, the differential amplifier is double-ended and powered with positive and negative voltages.

[0014] In some embodiments, the differential amplifier is powered by a single voltage.

[0015] A signal acquisition circuit according to one embodiment of the present invention includes a differential amplifier, a first electrode and a second electrode, and a fourth negative capacitance circuit, wherein the first electrode is connected to the first input terminal of the fourth negative capacitance circuit via the first lead wire, the second electrode is connected to the second input terminal of the fourth negative capacitance circuit via the second lead wire, the first output terminal of the fourth negative capacitance circuit is connected to the first input terminal of the differential amplifier, and the second output terminal of the fourth negative capacitance circuit is connected to the second input terminal of the differential amplifier, and the fourth negative capacitance circuit has a negative capacitance effect.

[0016] In some embodiments, the fourth negative capacitance circuit includes a double-ended differential amplifier, a first negative feedback capacitor, and a second negative feedback capacitor, wherein the first negative feedback capacitor is connected between the first input terminal and the first output terminal of the double-ended differential amplifier, and the second negative feedback capacitor is connected between the second input terminal and the second output terminal of the double-ended differential amplifier.

[0017] In some embodiments, the double-ended differential amplifier is an amplifier with a fixed gain.

[0018] In some embodiments, the fourth negative capacitance circuit includes a first unit and a second unit. The first unit includes a first amplifier and a third negative feedback capacitor. The second unit includes a second amplifier and a fourth negative feedback capacitor. The third negative feedback capacitor is connected between the input terminal and the output terminal of the first amplifier. The fourth negative feedback capacitor is connected between the input terminal and the output terminal of the second amplifier.

[0019] In some embodiments, the relative error between the absolute value of the equivalent capacitance value of the first unit of the fourth negative capacitance circuit and the parasitic capacitance value to the ground of the first lead wire is less than 50%. The relative error between the absolute value of the equivalent capacitance value of the second unit of the fourth negative capacitance circuit and the parasitic capacitance value to the ground of the second lead wire is less than 50%.

[0020] In some embodiments, the first amplifier and the second amplifier are amplifiers with equal and fixed gains.

[0021] In some embodiments, the circuit further includes a feedback control circuit for adjusting the equivalent capacitance value of the fourth negative capacitance circuit.

[0022] In some embodiments, the input impedance of the differential amplifier is greater than 100 megaohms.

[0023] In some embodiments, the differential amplifier is powered by positive and negative voltages in a double-ended manner.

[0024] In some embodiments, the differential amplifier is powered by a single voltage.

[0025] A wearable device according to an embodiment of the present application includes the above signal acquisition circuit.

[0026] The signal acquisition circuit according to an embodiment of the present application has a first negative capacitance circuit and a second negative capacitance circuit connected to the lead wire at the acquisition end. Since the first negative capacitance circuit and the second negative capacitance circuit have a negative capacitance effect, they cancel out the parasitic capacitance to the ground of the lead wire, reduce the influence on signal acquisition caused by the parasitic capacitance, and can further improve the performance of the signal acquisition circuit and the effect of signal acquisition.

[0027] The present application will be further described by way of exemplary embodiments, and these exemplary embodiments will be described in more detail with reference to the drawings. These embodiments are not limiting, and in these embodiments, the same reference numerals represent the same structures.

Brief Description of the Drawings

[0028] [Figure 1] It is a schematic diagram of the commercial frequency interference principle according to some embodiments of the present application. [Figure 2A] It is a schematic diagram of the power supply method of a differential amplifier according to some embodiments of the present application. [Figure 2B] It is a schematic diagram of the power supply method of a differential amplifier according to some embodiments of the present application. [Figure 3] It is a schematic diagram of the signal acquisition circuit according to some embodiments of the present application. [Figure 4] It is a schematic configuration diagram of the negative capacitance circuit in the signal acquisition circuit according to some embodiments of the present application. [Figure 5] It is a schematic diagram of the signal acquisition circuit according to some embodiments of the present application. [Figure 6A] It is a schematic configuration diagram of the fourth negative capacitance circuit in the signal acquisition circuit according to some embodiments of the present application. [Figure 6B] It is another schematic configuration diagram of the fourth negative capacitance circuit in the signal acquisition circuit according to some embodiments of the present application. [Figure 7A] It is a schematic diagram of the effect circuit before removing the commercial frequency interference according to some embodiments of the present application. [Figure 7B] It is a schematic diagram of the effect circuit after removing the commercial frequency interference according to some embodiments of the present application. [Modes for carrying out the invention]

[0029] To more clearly illustrate the technical means of the embodiments of this application, the drawings necessary for describing the embodiments are briefly described below. Clearly, the drawings described below are only a part of the examples or embodiments of this application, and those skilled in the art can apply this application to other similar scenarios based on these drawings without requiring any creative effort. Unless otherwise stated or otherwise evident from the language context, the same reference numerals in the figures indicate the same structure or operation.

[0030] It should be understood that the terms “system,” “apparatus,” “unit,” and / or “module” as used herein are means of distinguishing various assemblies, elements, components, parts, or assemblies of different levels. However, other terms may be used in place of the above terms if they can achieve the same purpose.

[0031] As used in this application and claims, unless the context explicitly indicates otherwise, terms such as “one,” “one,” “one kind,” and / or “the” do not specifically mean singular and may include plural forms. Generally, the terms “includes” and “contains” merely indicate the inclusion of clearly identified steps and elements, which are not an exclusive list, and the method or apparatus may include other steps or elements.

[0032] The signal acquisition circuit described in the embodiments of the present application can be applied to various signal monitoring devices that require signal acquisition, particularly physiological signal monitoring devices, such as smart wearable devices. In some embodiments, the wearable device (e.g., clothing, wristbands, straps, etc.) may be attached to various parts of the human body (e.g., lower legs, upper legs, waist, back, chest, shoulders, neck, etc.) to collect physiological signals from various parts of the body when the user is in different states, and to subsequently process the collected signals. In some embodiments, the physiological signals may be detectable signals that embody the user's physical state, and may include various signals such as respiratory signals, electrocardiogram (ECG), electromyography (EMG), electroencephalograph (EEG), blood pressure signals, and temperature signals. In some embodiments, the wearable device that acquires physiological signals may be applied to emerging cross-industries such as medical, game entertainment, and health education. For example, by combining it with technologies such as virtual reality (VR) and EMG collection, it can promote the development of immersive entertainment and education. By combining it with technologies such as mechanical and electronic devices and exoskeleton equipment, it can achieve the goal of reducing medical costs and promoting the development of medical care and health.

[0033] Figure 1 is a schematic diagram of the commercial frequency interference principle according to some embodiments of the present application.

[0034] In some embodiments, the signal acquisition circuit 100 shown in Figure 1 includes one or more sensor units that come into contact with the user's body (e.g., a first electrode 110 and a second electrode 120), a differential amplifier 130, and one or more lead wires connecting the sensor units and the differential amplifier 130 (e.g., a first lead wire L1 and a second lead wire L2).

[0035] In some embodiments, the sensor unit may acquire one or more physiological signals from the user. The sensor unit may include, but is not limited to, one or more of the following: electromyography sensors, posture sensors, electrocardiogram sensors, respiration sensors, temperature sensors, humidity sensors, inertia sensors, blood oxygen saturation sensors, Hall sensors, electrocutaneous reaction sensors, rotation sensors, etc. In some embodiments, the physiological signals may include one or more of the following: electromyography signals, posture signals, electrocardiogram signals, respiratory rate, temperature signals, humidity signals, etc. The sensor unit may be positioned at different locations on the wearable device depending on the type of motion signal to be acquired.

[0036] In some embodiments, different signal acquisition circuits may be positioned at different locations on the user's body to acquire the same or different types of physiological signals from the user. For example, signal acquisition circuits positioned on different sides of the user's upper thigh can both acquire electromyographic signals from the upper thigh. Alternatively, a signal acquisition circuit positioned in the user's forearm can acquire electromyographic signals from the forearm, and a signal acquisition circuit positioned in the user's heart area can acquire the user's electrocardiogram (ECG) signal.

[0037] In some embodiments, the sensor unit may include one or more electrode elements that come into contact with the user's body, and the electrode elements can collect electromyographic signals from the user's body surface. The electrode elements may be dry electrodes or wet electrodes. Dry electrodes are metal structure electrodes woven from metal pieces or metal wires, and the contact strength with the human body can be increased by applying a conductive colloid between the human skin and the electrode element to form a wet electrode. Since the human body is not an absolute conductor, there is contact impedance between both dry and wet electrodes and the human body, and since the impedance differs in different physiological states, different electrode types can be selected in each case.

[0038] In some embodiments, the electrode element includes a first electrode 110 and a second electrode 120. The first electrode 110 is connected to the first input terminal A of the differential amplifier 130 via a first lead wire L1, and the second electrode 120 is connected to the second input terminal B of the differential amplifier 130 via a second lead wire L2. The first lead wire L1 and the second lead wire L2 transmit the physiological signals collected by the electrode element to the differential amplifier for appropriate processing (e.g., noise reduction, amplification, etc.).

[0039] In some embodiments, the differential amplifier 130 may perform differential amplification processing on the physiological signal acquired by the electrode element. In some embodiments, the physiological signal processed by the differential amplifier 130, i.e., Vout output from the output terminal, may be transmitted to other elements in the wearable device for subsequent processing. For example, the processed physiological signal can be converted from an analog signal to a digital signal by an analog-to-digital converter (ADC), and further processing, such as signal analysis, can be performed by a processor.

[0040] In some embodiments, the differential amplifier 130 may include two power supply methods: single-ended and double-ended. As shown in Figure 2A, the differential amplifier 130 has a first power supply terminal (111) connected to a positive power supply +Vcc, a second power supply terminal (112) connected to a negative power supply -Vcc, and one end (113) that receives the bias voltage is grounded. As shown in Figure 2B, the differential amplifier 130 has a first power supply terminal (114) connected to a positive power supply +Vcc, a second power supply terminal (116) grounded, and one end (117) that receives the bias voltage receives a bias voltage with a voltage value of +Vcc / 2.

[0041] In some embodiments, if the contact impedance between the first electrode 110 and the second electrode 120 and the user's body does not match, that is, if the impedances of the two input terminals of the differential amplifier 130 do not match (impedance becomes unbalanced), the common-mode commercial frequency signal on the surface of the human body is converted into differential-mode commercial frequency noise and input to the amplifier, further reducing the signal-to-noise ratio, which in turn causes the circuit to saturate and fail.

[0042] The environment in which the human body is placed contains various 50 / 60Hz commercial frequency power lines (50Hz lines in China, 60Hz lines outside of China). These commercial frequency power lines emit electromagnetic waves, which combine with the human body and cause potential changes in the body. The amplitude of these waves is generally at the millivolt level, but can range from a few mV to several hundred mV, and is related to the position of the human body and the commercial frequency power line. To facilitate understanding, if we equate environmental interference with a capacitor coupling model C0 and represent the impedance between the human body and the ground as Z0, the model of commercial frequency interference can be equivalent to the left half of Figure 1, that is, the commercial frequency power line is connected in series with the equivalent capacitor C0, the human body, and the ground impedance and is grounded. When the human body moves, the distance from the commercial frequency power line changes, and the value of the equivalent capacitor C0 changes accordingly.

[0043] In some embodiments, the commercial frequency current coupled to the human body is Icm, and the common-mode commercial frequency potential Vcm on the surface of the human body can be expressed as follows:

[0044] Vcm = Icm * Z0 (1) The impedance to ground at the first input terminal A is Zin1, and the impedance to ground at the second input terminal B is Zin2. Generally,

number

[0045] Zcm = Zin / 2(2) In some embodiments, if the contact impedance between the first electrode 110 and the second electrode 120 and the user's body does not match, it causes the potentials of the first input terminal A and the second input terminal B of the differential amplifier 130 to be unequal, and the differential amplifier 130 further amplifies the potential difference between the two points A and B, thereby causing circuit saturation or failure. When a common-mode commercial frequency potential Vcm is present in the human body, the potential difference V between the first input terminal A and the second input terminal B of the differential amplifier 130 AB This can be expressed by the following equation (3).

[0046]

number

[0047] In the equation, Z1 is the contact impedance value of the first electrode 110, and Z2 is the contact impedance value of the second electrode 120. As can be seen from the above equation, the intensity of the differential-mode commercial frequency signal between the first input terminal A and the second input terminal B of the differential amplifier 130 is inversely proportional to the common-mode input impedance of the differential amplifier 130, and the lower the common-mode input impedance, the greater the commercial frequency interference.

[0048] In some embodiments, to reduce the impact of commercial frequency interference on signal acquisition, the potential difference between the two input terminals of a differential amplifier may be reduced by reducing the contact impedance of the electrode element, or the common-mode commercial frequency potential may be reduced by adding a ground electrode to the human body, further reducing the potential difference between the two input terminals of the differential amplifier. For example, one end of the electrode may be in contact with the human body and the other end may be connected to the GND of the circuit. However, since contact impedance always exists in the electrode element, it is not possible to completely eliminate the common-mode commercial frequency potential.

[0049] In some embodiments, a method of increasing the (common-mode) input impedance of the differential amplifier may be used to reduce the impact of commercial frequency interference on signal acquisition. For example, a differential amplifier having a high (common-mode) input impedance (for example, both the first input terminal A and the second input terminal B have high impedance to ground) can be used as the input front-end of the signal acquisition circuit. In some embodiments, the (common-mode) input impedance of the differential amplifier 130 is greater than 100 MΩ, preferably greater than 1 GΩ.

[0050] However, when the signal acquisition circuit 100 is applied to a wearable device, the presence of parasitic capacitance in the actual circuit causes a decrease in the input impedance of the differential amplifier. In actual applications, parasitic capacitance exists not only between the leads but also between the leads and ground. In particular, in scenarios where physiological signals are acquired, the effect of these parasitic capacitances is especially pronounced because some physiological signals (e.g., electromyography signals, electrocardiogram signals, etc.) are weak. In some embodiments, these parasitic capacitances are connected in parallel to various equivalent impedances in the signal acquisition circuit, significantly reducing the overall input impedance of the circuit, further exacerbating commercial frequency interference, and cannot be resolved by a differential amplifier using a higher input impedance. As can be seen, the presence of these parasitic capacitances limits the performance and acquisition effect of the signal acquisition circuit.

[0051] Figure 3 is a schematic diagram of a signal acquisition circuit 200 according to some embodiments of the present application.

[0052] In some embodiments, the signal acquisition circuit 200 shown in Figure 3 may include a first electrode 210, a second electrode 220, a differential amplifier 230, a first lead wire L1, a second lead wire L2, a first negative capacitance circuit C10, and a second negative capacitance circuit C20.

[0053] In some embodiments, the first electrode 210 is connected to the first input terminal A of the differential amplifier 230 via the first lead wire L1, and the second electrode 220 is connected to the second input terminal B of the differential amplifier 230 via the second lead wire L2. A detailed explanation of the first electrode 210, the second electrode 220, the differential amplifier 230, the first lead wire L1, and the second lead wire L2 can be found in the explanation in Figure 1, and is therefore omitted here.

[0054] In some embodiments, a first parasitic capacitance C1 exists between the first lead wire L1 and the ground wire, a second parasitic capacitance C2 exists between the second lead wire L2 and the ground wire, and an inter-lead parasitic capacitance C3 exists between the first lead wire L1 and the second lead wire L2. As shown in Figure 3, the first parasitic capacitance C1 can be considered to be equivalently connected between the first lead wire L1 and the ground wire and connected in parallel to the ground impedance Zin1 of the first input terminal A of the differential amplifier 230, the second parasitic capacitance C2 can be considered to be equivalently connected between the second lead wire L2 and the ground wire and connected in parallel to the ground impedance Zin2 of the second input terminal B of the differential amplifier 230, and the inter-lead parasitic capacitance C3 can be considered to be equivalently connected between the first lead wire L1 and the second lead wire L2. Since the first parasitic capacitance C1 and the second parasitic capacitance C2 are connected in parallel to the differential amplifier's ground impedance Zin1 and ground impedance Zin2, respectively, the overall input impedance of the circuit is significantly reduced, worsening the impact of commercial frequency interference on signal acquisition.

[0055] In some embodiments, changes in parasitic capacitance values ​​cannot be measured in real time, but because they are related to circuit design, parasitic capacitance values ​​can be measured after circuit design. That is, the first parasitic capacitance to ground C1, the second parasitic capacitance to ground C2, and the parasitic capacitance between lead wires C3 can be measured after the circuit design of the signal acquisition circuit. In the actual application process, parasitic capacitance values ​​between the human body cannot be measured accurately, but they can be measured when the human body is not moving to determine a baseline value for parasitic capacitance. When the human body moves, the parasitic capacitance values ​​between the human body change, and a rough range of variation can be determined based on the baseline value for parasitic capacitance.

[0056] In some embodiments, a first negative capacitance circuit C10 and a second negative capacitance circuit C20 are installed in the signal acquisition circuit 200 to reduce the effect of parasitic capacitance and increase the input impedance of the differential amplifier. The first negative capacitance circuit C10 is electrically connected to the first lead wire L1 and the ground wire, and the second negative capacitance circuit C20 is electrically connected to the second lead wire L2 and the ground wire. Since the first negative capacitance circuit C10 and the second negative capacitance circuit C20 have a negative capacitance effect, they cancel out the parasitic capacitance of the lead wires to ground, thereby reducing the effect of parasitic capacitance on the circuit input impedance and signal acquisition, and further improving the performance of the signal acquisition circuit and the effectiveness of signal acquisition. The negative capacitance effect referred to here can be understood as the trend of change in the charge amount in the first negative capacitance circuit C10 and the second negative capacitance circuit C20 being inverse to the trend of change in the voltage applied to them; that is, as the voltage decreases, the charge amount in the first negative capacitance circuit C10 and the second negative capacitance circuit C20 increases accordingly.

[0057] In some embodiments, the method of electrically connecting the first negative capacitance circuit C10 and / or the second negative capacitance circuit C20 to the ground line may include connecting the first negative capacitance circuit C10 and / or the second negative capacitance circuit C20 to a common ground terminal on one or more printed circuit boards (PCBs).

[0058] In some embodiments, the first negative capacitance circuit C10 can be considered to be connected in parallel to the first parasitic capacitance to ground C1, and the second negative capacitance circuit C20 can be considered to be connected in parallel to the second parasitic capacitance to ground C2. The first negative capacitance circuit C10 and the second negative capacitance circuit C20 cancel out the parasitic capacitances at the two input terminals of the differential amplifier, thereby reducing the capacitance value at the input terminals of the differential amplifier and achieving an improvement in input impedance. In some embodiments, the equivalent capacitance values ​​of the first negative capacitance circuit C10 and the second negative capacitance circuit C20 can be expressed as follows. C10 = -C1(4) C20 = -C2(5) The total capacitance to ground of both the first lead wire L1 and the second lead wire L2 is 0. In this case, the parasitic capacitance to ground at the input terminal of the differential amplifier is completely canceled out, significantly improving the input impedance of the entire signal acquisition circuit and further enhancing its resistance to commercial frequency interference.

[0059] In some embodiments, the absolute value of the negative capacitance circuit is not exactly equal to the parasitic capacitance because, in the actual operating environment, the parasitic capacitance may change slightly with the movement of the lead wires. In some embodiments, in order to effectively cancel out the parasitic capacitance to ground at the input terminal of the differential amplifier, the relative error between the absolute value of the equivalent capacitance of the first negative capacitance circuit C10 and the parasitic capacitance value C1 of the first lead wire L1 is less than 50%, and the relative error between the absolute value of the equivalent capacitance of the second negative capacitance circuit C20 and the parasitic capacitance value C2 of the second lead wire L2 is less than 50%. In some embodiments, in order to ensure that the input terminal of the differential amplifier has a larger input impedance, the relative error between the absolute value of the equivalent capacitance of the first negative capacitance circuit C10 and the parasitic capacitance value C1 of the first lead wire L1 to ground is less than 30%, and the relative error between the absolute value of the equivalent capacitance of the second negative capacitance circuit C20 and the parasitic capacitance value C2 of the second lead wire L2 to ground is less than 30%.

[0060] In actual application, the smaller the relative error between the absolute value of the equivalent capacitance of the first negative capacitance circuit C10 and the parasitic capacitance value C1 of the first lead wire L1 to ground, the greater the parasitic capacitance value C1 of the first lead wire L1 that is canceled out by the first negative capacitance circuit C10. This increases the input impedance of the entire signal acquisition circuit and ultimately enhances the effectiveness of signal acquisition. The same applies to the second negative capacitance circuit C20, which will not be explained here.

[0061] In some embodiments, the relative error between the absolute value of the equivalent capacitance of the first negative capacitance circuit C10 and the parasitic capacitance of the first lead wire L1 to ground is the ratio of the difference between the absolute value of the equivalent capacitance of the first negative capacitance circuit C10 and the parasitic capacitance of the first lead wire L1 to ground, to the parasitic capacitance of the first lead wire L1.

[0062] In some embodiments, the equivalent input impedance Zin1 of the first input terminal A of the differential amplifier 230 may be equivalent to the parallel-connected capacitors Rin1 and Cin1, and the equivalent input impedance Zin2 of the second input terminal B of the differential amplifier 230 may be equivalent to the parallel-connected capacitors Rin2 and Cin2. In some embodiments, in order to further improve the input impedance performance of the signal acquisition circuit 200, the first negative capacitance circuit C10 and the second negative capacitance circuit C20 can be adjusted to further cancel out the effect of the equivalent input capacitance of the differential amplifier 230. In some embodiments, the equivalent capacitance values ​​of the first negative capacitance circuit C10 and the second negative capacitance circuit C20 can be adjusted as follows.

[0063] C10 = -(C1 + Cin1)(6)

[0064] C20 = -(C2 + Cin2)(7)

[0065] In some embodiments, in order to effectively cancel out the equivalent input capacitance at the input terminal of the differential amplifier, the relative error between the absolute value of the equivalent capacitance of the first negative capacitance circuit C10 and the sum of the parasitic capacitance value C1 of the first lead wire L1 to ground and the equivalent input capacitance value Cin1 of the first input terminal A of the differential amplifier 230 is less than 50%, and the relative error between the absolute value of the equivalent capacitance of the second negative capacitance circuit C20 and the sum of the parasitic capacitance value C2 of the second lead wire L2 to ground and the equivalent input capacitance value Cin2 of the second input terminal B of the differential amplifier 230 is less than 50%. In some embodiments, in order to ensure that the input terminal of the differential amplifier has a larger input impedance, the relative error between the absolute value of the equivalent capacitance of the first negative capacitance circuit C10 and the sum of the parasitic capacitance value C1 of the first lead wire L1 to ground and the equivalent input capacitance value Cin1 of the first input terminal A of the differential amplifier 230 is less than 30%, and the relative error between the absolute value of the equivalent capacitance of the second negative capacitance circuit C20 and the sum of the parasitic capacitance value C2 of the second lead wire L2 to ground and the equivalent input capacitance value Cin2 of the second input terminal B of the differential amplifier 230 is less than 30%.

[0066] In actual application, the smaller the relative error between the absolute value of the equivalent capacitance of the first negative capacitance circuit C10 and the sum of the parasitic capacitance of the first lead wire L1 to ground and the first equivalent input capacitance Cin1 of the differential amplifier, the greater the parasitic capacitance of the first lead wire L1 to ground and the first equivalent input capacitance Cin1 of the differential amplifier that are canceled out by the first negative capacitance circuit C10. This increases the input impedance of the entire signal acquisition circuit and ultimately enhances the effectiveness of signal acquisition. The same applies to the second negative capacitance circuit C20, which will not be explained here.

[0067] As a result, the first negative capacitance circuit C10 and the second negative capacitance circuit C20 cancel out the parasitic capacitance to ground of the first lead wire L1 and the first equivalent input capacitance Cin1 of the differential amplifier, and the parasitic capacitance to ground of the second lead wire L2 and the second equivalent input capacitance Cin2 of the differential amplifier, respectively, further increasing the input impedance of the entire signal acquisition circuit.

[0068] In some embodiments, the signal acquisition circuit 200 may further include a third negative capacitance circuit C30. The third negative capacitance circuit C30 is electrically connected between the first lead wire L1 and the second lead wire L2 and is connected in parallel to the inter-lead parasitic capacitance C3. In some embodiments, the signal acquisition circuit 200 may not include the third negative capacitance circuit C30 because the influence of the inter-lead parasitic capacitance C3 on the circuit performance is low. In some embodiments, the signal acquisition circuit 200 may include the third negative capacitance circuit C30 if the requirements for the signal acquisition circuit 200 are high. In some embodiments, the value of the third negative capacitance circuit C30 can be expressed as follows.

[0069] C30 = -C3(8)

[0070] In some embodiments, the relative error between the absolute value of the equivalent capacitance of the third negative capacitance circuit C30 and the value of the parasitic capacitance C3 between the leads is less than 50%. In some embodiments, the relative error between the absolute value of the equivalent capacitance of the third negative capacitance circuit C30 and the value of the parasitic capacitance C3 between the leads is less than 30%. In actual application, it should be understood that the smaller the relative error between the absolute value of the equivalent capacitance of the third negative capacitance circuit C30 and the value of the parasitic capacitance C3 between the leads, the more the parasitic capacitance C3 between the leads is canceled out by the third negative capacitance circuit C30, the larger the input impedance of the entire signal acquisition circuit becomes, and the greater the final signal acquisition effect.

[0071] In some embodiments, the signal acquisition circuit may further include a feedback control circuit that adjusts the equivalent capacitance values ​​of the first negative capacitance circuit C10 and the second negative capacitance circuit C20, for example, by changing the resistance values ​​of the negative capacitance circuits.

[0072] For specific structures of the first negative capacitance circuit C10, the second negative capacitance circuit C20, and the third negative capacitance circuit C30, please refer to the relevant information in Figures 4A and 4B.

[0073] Figure 4 is a schematic diagram of the negative capacitance circuit in a signal acquisition circuit 200 according to some embodiments of the present application.

[0074] In some embodiments, the first negative capacitance circuit C10 may have the structure shown in Figure 4, and as shown in Figure 4, the first negative capacitance circuit C10 may include a first operational amplifier 410, a first resistor R1, a second resistor R2, and a first capacitor C401. In some embodiments, the inverting input terminal of the first operational amplifier 410 is grounded via the first resistor R1 and connected to the output terminal of the first operational amplifier 410 via the second resistor R2, and the non-inverting input terminal is connected to the output terminal of the first operational amplifier 410 via the first capacitor C401. In some embodiments, point m in Figure 4 and point a in Figure 3 are both points at the same potential, and points a and m may be electrically connected using lead wires.

[0075] In some embodiments, the second negative capacitance circuit C20 may have the structure shown in Figure 4, in which case point m in Figure 4 and point b in Figure 3 are both equipotential points, and points m and b may be electrically connected using lead wires.

[0076] Note that the negative capacitance circuit shown in Figure 4 is an equivalent circuit that exhibits a negative capacitance effect. Specifically, for the negative capacitance circuit shown in Figure 4, the equivalent impedance of the negative capacitance circuit is the impedance between point m and GND. The impedance between point m and GND is z a Then, z a The impedance can be expressed by the following equation (9).

[0077]

number

[0078] That is, the impedance between point m and GND may be equivalent to include one negative capacitance, or it may be generated by one negative capacitance. The negative capacitance between point m and GND is C a Therefore, C aThe equivalent capacity value can be expressed by the following equation (10).

[0079]

number

[0080] C a Please understand that this represents the equivalent capacitance of the negative capacitance circuit shown in Figure 4.

[0081] In some embodiments, resistors R1 and R2 may be resistors with adjustable resistance values ​​(e.g., sliding resistors, resistor boxes, and potentiometers) or resistors with fixed resistance values. In some embodiments, the resistance values ​​of resistors R1 and R2 may be equal or unequal. In some embodiments, by adjusting the resistance values ​​of resistors R1 and R2, the equivalent capacitance C can be adjusted. a Please understand that you may adjust the size.

[0082] In some embodiments, the first capacitor C401 may be a paper capacitor, a metallized paper capacitor, a ceramic capacitor, a film capacitor, an oil paper capacitor, an aluminum electrolytic capacitor, a semi-variable capacitor, a variable capacitor, etc. In some embodiments, by adjusting the capacitance value of the first capacitor C401, the equivalent capacitance C a You can adjust the size.

[0083] In some embodiments, the first operational amplifier 410 may be powered by two power supplies, for example, with voltage +Vcc (411) as the positive power supply and voltage -Vcc (412) as the negative power supply, and the amplified signal generated by the first operational amplifier 410 is output at 413. In some embodiments, the first operational amplifier 410 may be powered by a single power supply, and this will not be explained here.

[0084] In some embodiments, the first negative capacitance circuit C10 and the second negative capacitance circuit C20 may have structures other than those shown in Figure 4.

[0085] In some embodiments, the signal acquisition circuit 200 may further include a third negative capacitance circuit C30, which is electrically connected to the first lead wire L1 and the second lead wire L2 and has a negative capacitance effect.

[0086] In some embodiments, the third negative capacitance circuit C30 may have the structure shown in Figure 4, in which case point m in Figure 4 and point c in Figure 3 are both at the same potential, and point GND in Figure 4 and point d in Figure 3 are both at the same potential. Point c in Figure 3 and point m in Figure 4 may be electrically connected using lead wires, and point d in Figure 3 and point GND in Figure 4 may be electrically connected.

[0087] In some embodiments, the third negative capacitance circuit C30 may have a structure other than that shown in Figure 4, as long as it can cancel out the parasitic capacitance C3 between the lead wires.

[0088] The above description of the signal acquisition circuit 100, the signal acquisition circuit 200, and their structures is for illustrative purposes only and is not limited to the embodiments cited in this application.

[0089] Figure 5 is a schematic diagram of a signal acquisition circuit 300 according to some embodiments of the present application.

[0090] The signal acquisition circuit 300 shown in Figure 5 may include a first electrode 210, a second electrode 220, a differential amplifier 230, a first lead wire L1, a second lead wire L2, and a fourth negative capacitance circuit C40. For a detailed explanation of the first electrode 210, the second electrode 220, the differential amplifier 230, the first lead wire L1, and the second lead wire L2, please refer to the explanations in Figures 1 to 4 above; a detailed explanation is omitted here.

[0091] As described in the above embodiment, a first parasitic capacitance C1 exists between the first lead wire L1 and the ground wire, and a second parasitic capacitance C2 exists between the second lead wire L2 and the ground wire. Since the first parasitic capacitance C1 and the second parasitic capacitance C2 are connected in parallel to the ground impedances Zin1 and Zin2 of the differential amplifier, respectively, the input impedance of the entire circuit is significantly reduced, worsening the impact of commercial frequency interference on signal acquisition.

[0092] Therefore, in some embodiments, a fourth negative capacitance circuit C40 is installed in the signal acquisition circuit 300 to reduce the effect of parasitic capacitance and increase the input impedance of the differential amplifier 230. In some embodiments, the first electrode 210 is connected to the first input terminal P of the fourth negative capacitance circuit C40 via the first lead wire L1, the second electrode 220 is connected to the second input terminal Q of the fourth negative capacitance circuit C40 via the second lead wire L2, the first output terminal M of the fourth negative capacitance circuit C40 is connected to the first input terminal A of the differential amplifier 230, and the second output terminal N of the fourth negative capacitance circuit C40 is connected to the second input terminal B of the differential amplifier 230. Because the fourth negative capacitance circuit C40 has a negative capacitance effect, it can cancel out the parasitic capacitance to ground of the lead wires, thereby reducing the effect of parasitic capacitance on the input impedance of the circuit and signal acquisition, and further improving the performance of the signal acquisition circuit and the effectiveness of signal acquisition.

[0093] In some embodiments, the negative capacitance circuit C40 can be realized by using an amplifier with a fixed gain and a feedback capacitor, thereby achieving the effect of simultaneously canceling out the first parasitic capacitance to ground C1 and the second parasitic capacitance to ground C2. For specific implementation methods of the negative capacitance circuit C40, please refer to the related explanations in Figures 6A and 6B.

[0094] In some embodiments, the signal acquisition circuit 300 may further include a third negative capacitance circuit C30. The third negative capacitance circuit C30 is electrically connected between the first lead wire L1 and the second lead wire L2 and is connected in parallel to the inter-lead parasitic capacitance C3. In some embodiments, the signal acquisition circuit 200 does not need to have the third negative capacitance circuit C30 because the influence of the inter-lead parasitic capacitance C3 on the circuit performance is low. In some embodiments, if the requirements of the signal acquisition circuit 200 are high, the signal acquisition circuit 200 may have the third negative capacitance circuit C30. For specific implementation methods of the third negative capacitance circuit C30, please refer to the related explanations in Figures 3 and 4, and the explanation is omitted here.

[0095] In some embodiments, the signal acquisition circuit may further include a feedback control circuit that adjusts the equivalent capacitance value of the fourth negative capacitance circuit C40, for example, by changing the resistance or capacitance value of the negative capacitance circuit.

[0096] Figure 6A is a schematic diagram of the fourth negative capacitance circuit C40 in a signal acquisition circuit 300 according to some embodiments of the present application.

[0097] In some embodiments, the fourth negative capacitance circuit C40 may include a first unit C402 and a second unit C404, where the first unit C402 includes a first amplifier G2 and a third negative feedback capacitor C46, ​​and the second unit C404 includes a second amplifier G3 and a fourth negative feedback capacitor C48. In some embodiments, both the first amplifier G2 and the second amplifier G3 are amplifiers with fixed gain.

[0098] In some embodiments, the input terminal of the first amplifier G2 is the first input terminal P of the fourth negative capacitance circuit C40, the input terminal of the second amplifier G3 is the second input terminal Q of the fourth negative capacitance circuit C40, similarly, the output terminal of the first amplifier G2 is the first output terminal M of the fourth negative capacitance circuit C40, and the output terminal of the second amplifier G3 is the second output terminal N of the fourth negative capacitance circuit C40.

[0099] In some embodiments, the input terminal P of the first amplifier G2 and the output terminal M of the first amplifier G2 are connected in series via a third negative feedback capacitor C46, ​​and the input terminal Q of the second amplifier G3 and the output terminal N of the second amplifier G3 are connected in series via a fourth negative feedback capacitor C48.

[0100] In some embodiments, when the gain of the first amplifier G2 is constant at g1, the gain of the second amplifier G3 is also constant at g1, and the equivalent capacitance value of the first unit C402 of the fourth negative capacitance circuit C40 can be expressed as follows.

[0101] C402 = -C46(g1-1)(11)

[0102] The equivalent capacitance value of the second unit C404 of the fourth negative capacitance circuit C40 can be expressed as follows:

[0103] C404 = -C48(g1-1)(12)

[0104] In some embodiments, the first amplifier G2 and the second amplifier G3 are amplifiers with equal and fixed gains; for example, if the gain of the first amplifier G2 is constant at g1, then the gain of the second amplifier G3 is also constant at g1. In some embodiments, the gain range of the first amplifier G2 and the second amplifier G3 may be 0 to 100 dB, preferably 0 to 10 dB.

[0105] In some embodiments, the values ​​of the third negative feedback capacitor C46 and the fourth negative feedback capacitor C48 are equal. Thus, the first unit C402 and the second unit C404 of the fourth negative capacitance circuit C40 form a highly symmetrical structure so that a large common-mode rejection ratio can be obtained for the signal acquisition circuit 300 as a whole. In some embodiments, if the gains of the first amplifier G2 and the second amplifier G3 are not equal, the common-mode rejection ratio of the circuit decreases, and the effect of reducing commercial frequency interference cannot be achieved.

[0106] In some embodiments, the first amplifier G2 and the second amplifier G3 may each be configured as a multi-stage cascade of amplifiers with fixed gain.

[0107] In some embodiments, the first unit C402 of the fourth negative capacitance circuit C40 may cancel out the first parasitic capacitance to ground C1, and the second unit C404 of the fourth negative capacitance circuit C40 may cancel out the second parasitic capacitance to ground C2. This allows the fourth negative capacitance circuit C40 to cancel out both the first parasitic capacitance to ground C1 and the second parasitic capacitance to ground C2 simultaneously. In some embodiments, the equivalent capacitance values ​​of the first unit C402 and the second unit C404 can be expressed as follows.

[0108] C402 = -C1(13)

[0109] C404 = -C2(14)

[0110] Thus, the total capacitance to ground of the first lead wire L1 and the total capacitance to ground of the second lead wire L2 are both 0. In this case, the parasitic capacitance to ground at the input terminal of the differential amplifier 230 is completely canceled out, which significantly improves the input impedance of the entire signal acquisition circuit 300 and further improves its resistance to commercial frequency interference.

[0111] In some embodiments, considering that parasitic capacitance may change slightly with the movement of the lead wires in the actual operating environment, the relative error between the absolute value of the equivalent capacitance of the first unit C402 of the fourth negative capacitance circuit C40 and the parasitic capacitance value C1 of the first lead wire L1 is less than 50%, and the relative error between the absolute value of the equivalent capacitance of the second unit C404 of the fourth negative capacitance circuit C40 and the parasitic capacitance value C2 of the second lead wire L2 is less than 50%. In some embodiments, the relative error between the absolute value of the equivalent capacitance of the first unit C402 of the fourth negative capacitance circuit C40 and the parasitic capacitance value C1 of the first lead wire L1 is less than 30%, and the relative error between the absolute value of the equivalent capacitance of the second unit C404 of the fourth negative capacitance circuit C40 and the parasitic capacitance value C2 of the second lead wire L2 is less than 30%.

[0112] Figure 6B is another schematic diagram of the fourth negative capacitance circuit C40 in the signal acquisition circuit 300 according to some embodiments of the present application.

[0113] In some embodiments, the fourth negative capacitance circuit C40 may include a double-ended differential amplifier G1, a first negative feedback capacitor C42, and a second negative feedback capacitor C44.

[0114] In some embodiments, the first input terminal of the double-ended differential amplifier G1 is the first input terminal P of the fourth negative capacitance circuit C40, the second input terminal of the double-ended differential amplifier G1 is the second input terminal Q of the fourth negative capacitance circuit C40, similarly, the first output terminal of the double-ended differential amplifier G1 is the first output terminal M of the fourth negative capacitance circuit C40, and the second output terminal of the double-ended differential amplifier G1 is the second output terminal N of the fourth negative capacitance circuit C40. The first input terminal P and the first output terminal M of the double-ended differential amplifier G1 are connected in series via a first negative feedback capacitor C42, and the second input terminal Q and the second output terminal N of the double-ended differential amplifier G1 are connected in series via a second negative feedback capacitor C44.

[0115] In some embodiments, the double-ended differential amplifier G1 is an amplifier with a fixed gain. In some embodiments, the gain g0 of the double-ended differential amplifier G1 may be in the range of 0 to 100 dB, and preferably the range of g0 is 0 to 10 dB.

[0116] In some embodiments, the fourth negative capacitance circuit C40 may simultaneously cancel out the first parasitic capacitance to ground C1 and the second parasitic capacitance to ground C2. In some embodiments, the double-ended differential amplifier G1 may be composed of a combination of multiple amplifiers with fixed gains, for example, the double-ended differential amplifier G1 is composed of two amplifiers G11 and G12 with gain g0, where amplifiers G11 and G12 are identical amplifiers with fixed gains, and their structures may be exactly the same. In some embodiments, the input terminal of amplifier G11 is point P and the output terminal is point M, and the first negative feedback capacitor C42 is connected in series between points P and M, and the circuit structure consisting of amplifier G11 and the first negative feedback capacitor C42 may cancel out the first parasitic capacitance to ground C1. In some embodiments, the amplifier G12 has an input terminal at point Q and an output terminal at point N, and the second negative feedback capacitor C44 is connected in series between points Q and N, and the circuit structure consisting of the amplifier G12 and the second negative feedback capacitor C44 may cancel out the first parasitic capacitance to ground C1. In some embodiments, the equivalent capacitance value C11 of the circuit structure consisting of the amplifier G11 and the first negative feedback capacitor C42 and the equivalent capacitance value C12 of the circuit structure consisting of the amplifier G12 and the second negative feedback capacitor C44 can be expressed as follows.

[0117] C11 = -C42(g0-1)(15)

[0118] C12 = -C45(g0-1)(16)

[0119] In this case, the circuit structure consisting of amplifier G11 and the first negative feedback capacitor C42 may cancel out the first parasitic capacitance to ground C1, and the circuit structure consisting of amplifier G12 and the second negative feedback capacitor C44 may cancel out the second parasitic capacitance to ground C2. In this case, the parasitic capacitance to ground at the input terminal of the differential amplifier is canceled out, which significantly improves the input impedance of the entire signal acquisition circuit and further improves its resistance to commercial frequency interference.

[0120] In some embodiments, in order to effectively cancel out the parasitic capacitance to ground at the input terminal of the differential amplifier, the relative error between the absolute value of the equivalent capacitance C11 of the circuit structure consisting of amplifier G11 and the first negative feedback capacitor C42 and the parasitic capacitance C1 of the first lead wire L1 is less than 50%, and the relative error between the absolute value of the equivalent capacitance C12 of the circuit structure consisting of amplifier G12 and the second negative feedback capacitor C44 and the parasitic capacitance C2 of the second lead wire L2 is less than 50%. In some embodiments, in order to ensure that the input terminal of the differential amplifier has a larger input impedance, the relative error between the absolute value of the equivalent capacitance C11 of the circuit structure consisting of amplifier G11 and the first negative feedback capacitor C42 and the parasitic capacitance C1 of the first lead wire L1 to ground is less than 30%, and the relative error between the absolute value of the equivalent capacitance C12 of the circuit structure consisting of amplifier G12 and the second negative feedback capacitor C44 and the parasitic capacitance C2 of the second lead wire L2 to ground is less than 30%.

[0121] In actual application, the smaller the relative error between the absolute value of the equivalent capacitance C11 of the circuit structure consisting of amplifier G11 and the first negative feedback capacitor C42 and the parasitic capacitance C1 of the first lead wire L1 to ground, and the smaller the relative error between the equivalent capacitance C12 of the circuit structure consisting of amplifier G12 and the second negative feedback capacitor C44 and the parasitic capacitance C2 of the second lead wire L2 to ground, the greater the parasitic capacitance C1 of the first lead wire L1 and the parasitic capacitance C2 of the second lead wire L2 that are canceled out by the fourth negative capacitance circuit C40. This increases the input impedance of the entire signal acquisition circuit and ultimately enhances the effectiveness of signal acquisition.

[0122] In some embodiments, the structure of the fourth negative capacitance circuit C40 may be any other structure other than those shown in Figures 6A and 6B, as long as the equivalent capacitance value of C40 can cancel out the first parasitic capacitance value C1 of the first lead wire L1 and the parasitic capacitance value C2 of the second lead wire L2, and is not limited thereto.

[0123] Figure 7A is a schematic diagram of the effect circuit before commercial frequency interference is removed according to some embodiments of the present application. Figure 7B is a schematic diagram of the effect circuit after commercial frequency interference is removed according to some embodiments of the present application.

[0124] In some embodiments, as shown in Figure 7A, an analog signal acquisition circuit 400 is provided, which includes a common-mode commercial frequency source 501, a differential amplifier 530, a resistor R5 with a resistance of 10 MΩ, a resistor R6 with a resistance of 100 KΩ, and capacitors C5 and C6, each with a capacitance of 6 pF, wherein resistor R5 is connected to the first input terminal (A1) of the differential amplifier 530 via a first lead wire L11, resistor R6 is connected to the second input terminal (B1) of the differential amplifier 530 via a second lead wire L22, capacitor C5 has one end connected to the first input terminal (A1) of the differential amplifier 530 and also to the first lead wire L11, and the other end is grounded, and capacitor C6 has one end connected to the second input terminal (B1) of the differential amplifier 530 and also to the second lead wire L22, and the other end is grounded.

[0125] The common-mode commercial frequency source 501 is an AC power supply with a voltage peak of 300mV and a frequency of 50Hz, and it simulates the common-mode commercial frequency signal generated by the human body. There may be a difference in the resistance values ​​of R5 and R6, and it simulates the impedance mismatch that occurs between the two electrodes when an actual wearable device collects human body signals. Capacitors C5 and C6 simulate the parasitic capacitance that occurs between each of the two leads relative to ground when an actual wearable device collects human body signals.

[0126] In some embodiments, the differential amplifier 530 uses a double-ended power supply configuration, with the first power supply terminal (511) connected to a positive power supply +Vcc, the second power supply terminal (512) connected to a negative power supply -Vcc, and one end (513) that receives the bias voltage being grounded. In some embodiments, the positive power supply +Vcc provides a voltage of 3.3V, and the negative power supply -Vcc provides a voltage of -3.3V.

[0127] In some embodiments, the signal acquisition circuit 400 further includes a first probe T1 installed on the signal input side and connected to the first input terminal (A1) of the differential amplifier 530, and a second probe T2 installed on the signal output side and connected to the output terminal (514) of the differential amplifier 530. The first probe T1 and the second probe T2 measure the voltage peak value, effective value, frequency, etc., before and after the voltage signal is input to the differential amplifier 530, respectively. The data obtained after the test is shown in Table 1 below.

[0128] [Table 1]

[0129] Figure 7B is a schematic diagram of the effect circuit after commercial frequency interference has been removed according to some embodiments of the present application. Figure 7B is obtained by adding negative capacitance circuits C510 and C520 to Figure 7A. The structures of both negative capacitance circuits C510 and C520 are the same as those in Figure 4, with point x of negative capacitance circuit C510 electrically connected to point X on the first lead wire L11, and point y of negative capacitance circuit C520 electrically connected to point Y on the second lead wire L22.

[0130] In some embodiments, the operational amplifier 502 of the negative capacitance circuit C510 has a first feed terminal (521) connected to a positive power supply +Vcc and a second feed terminal (522) connected to a negative power supply -Vcc, and the output terminal (523) of the operational amplifier 502 outputs an amplified voltage. In some embodiments, the positive power supply +Vcc provides a voltage of 3.3V, the negative power supply -Vcc provides a voltage of -3.3V, the magnitude of the capacitor C501 is 6pF, and the magnitudes of resistors R51 and R52 are both 10kΩ.

[0131] According to equation (10) above, the magnitude of the capacitance value of the negative capacitance circuit C510 can be calculated to be -6pF.

[0132] Since the negative capacitance circuit C520 uses the same configuration and elements as the negative capacitance circuit C510, the capacitance value of the negative capacitance circuit C520 is also -6pF.

[0133] After adding the two negative capacitance circuits, tests were performed again using the first probe T1 and the second probe T2 to verify that the commercial frequency interference of the entire signal acquisition circuit 400 had been significantly reduced. The obtained data is shown in Table 2 below.

[0134] [Table 2]

[0135] As can be seen by comparing the data in Table 1 and Table 2, before adding negative capacitance circuits C510 and C520, the voltage peak values ​​measured with the first probe T1 and the second probe T2 were both 11.4mV. After adding negative capacitance circuits C510 and C520, the voltage peak value measured with the first probe T1 was 1.17mV, and the voltage peak value measured with the second probe T2 was 1.10mV. As can be seen from this, after adding negative capacitance circuits C510 and C520, the commercial frequency interference of the entire circuit decreased by more than 10 times.

[0136] These results demonstrate that by adding a negative capacitance circuit to the input terminal of a differential amplifier, the input impedance can be significantly increased, and interference caused by the conversion of the commercial frequency common mode to the differential mode due to impedance mismatch of the electrodes can be reduced, thereby greatly reducing the risk of circuit saturation.

[0137] In some embodiments, the signal acquisition circuits 200 and 300 described above may be applied to wearable devices. The wearable device (e.g., clothing, wristbands, straps, etc.) may be attached to various parts of the human body (e.g., lower legs, upper legs, waist, back, chest, shoulders, neck, etc.) and can collect physiological signals from various parts of the body when the user is in different states, and subsequently process the collected signals.

[0138] The above-described signal acquisition circuit can be used in situations where it is necessary to detect signals that embody the user's physical state. For example, the physiological signals can include various signals such as respiratory signals, electrocardiogram signals, electromyogram signals, electroencephalogram signals, blood pressure signals, and temperature signals. In some embodiments, wearable devices that acquire physiological signals may be applied to emerging cross-industries such as medical care, gaming entertainment, and health education. For example, when combined with technologies such as virtual reality and EMG acquisition, it can promote the development of immersive entertainment and education. When combined with technologies such as mechanical electronics and exoskeleton devices, it can achieve the objective of reducing medical costs and promoting the development of medical health. This application does not limit the specific application scenarios of the signal acquisition circuit and wearable device.

[0139] The beneficial effects of the embodiments of the present invention include, but are not limited to, canceling parasitic capacitance in the signal acquisition circuit by installing a negative capacitance circuit, further effectively increasing the input impedance of the entire signal acquisition circuit, and ultimately significantly reducing the interference of parasitic capacitance with the entire signal acquisition circuit, thereby improving the effectiveness of signal acquisition by the signal acquisition circuit.

[0140] The achievable beneficial effects may differ depending on the embodiment. In different embodiments, the achievable beneficial effects may be one or a combination of any of the above, or any other achievable beneficial effects.

[0141] Having explained the basic concepts above, it will be clear to those skilled in the art that the above detailed disclosures are merely examples and do not limit the present application. Although not explicitly stated herein, those skilled in the art can make various changes, improvements, and modifications to the present application. These changes, improvements, and modifications are intended to be suggested by the present application and are therefore within the spirit and scope of the exemplary embodiments of the present application.

[0142] Furthermore, certain terms are used in this Application to describe embodiments thereof. For example, “one embodiment,” “one embodiment,” and / or “several embodiments” mean certain features, structures, or properties relating to at least one embodiment of this Application. Therefore, it should be emphasized and understood that two or more references to “one embodiment,” “one embodiment,” or “one alternative embodiment” in various parts of this Specification do not necessarily all refer to the same embodiment. Also, certain features, structures, or properties in one or more embodiments of this Application may be appropriately combined.

[0143] Furthermore, as will be understood by those skilled in the art, each aspect of this Application may be illustrated and described in several patentable classes or contexts, including any novel and useful combination of processes, machines, products or materials, or any novel and useful improvement thereto. Thus, each aspect of this Application may be executed entirely by hardware, entirely by software (including firmware, resident software, microcode, etc.), or by a combination of hardware and software. Any of the above hardware or software may be referred to as “data blocks,” “modules,” “engines,” “units,” “assemblies,” or “systems.” Furthermore, each aspect of this Application may take the form of a computer program product embodied in one or more computer-readable media, including computer-readable program code.

[0144] A computer storage medium may include propagated data signals that are propagated over a baseband or as part of a carrier wave for carrying computer program code. These propagated signals may take various forms, such as electromagnetic signals, optical signals, or appropriate combinations thereof. The computer storage medium may be any computer-readable medium other than a computer-readable storage medium, which, when connected to an instruction execution system, device, or apparatus, can enable communication, propagation, or transmission of the program being used. Program code on the computer storage medium can be propagated via any appropriate medium, including wireless, cable, fiber optic cable, RF, or similar media, or any combination of the above media.

[0145] Furthermore, unless explicitly stated in the claims, the enumerated order, use of alphanumeric characters, or use of other names of the processing elements or sequences described herein does not limit the order of the procedures and methods of this application. While the above disclosure illustrates various examples that are currently considered useful embodiments of the invention, such details are for illustrative purposes only, and it should be understood that the attached claims are not limited to the disclosed embodiments, but rather are intended to cover all modifications and equivalent combinations that fall within the spirit and scope of the embodiments of this application. For example, the system assembly described above may be implemented by hardware devices, but may also be implemented by software-only solutions, such as installing the described system on an existing server or mobile device.

[0146] Similarly, in the foregoing description of embodiments of the present application, it should be understood that, for the purpose of simplifying the application and aiding in the understanding of embodiments of one or more inventions, various features may be grouped together in a single embodiment, drawing, or description. However, such disclosure methods should not be interpreted as reflecting an intention that the claimed subject matter requires more features than are enumerated in each claim. In fact, the features of an embodiment may be fewer than all the features of a single embodiment disclosed above.

[0147] In some embodiments, numbers are used to describe the number of components and attributes, and it should be understood that these numbers describing such embodiments are modified in some cases by the modifiers “approximately,” “about,” or “roughly.” Unless otherwise specified, “approximately,” “about,” or “roughly” indicates that the above numbers are allowed to vary by ±20%. Therefore, in some embodiments, the numerical parameters used in the specification and claims are all approximations that may vary depending on the characteristics required for the individual embodiment. In some embodiments, the numerical parameters should be rounded using standard rounding techniques, taking into account the specified number of significant figures. In some embodiments of this application, the numerical ranges and parameters used to determine the range are approximations, but in specific embodiments, such numbers are set as accurately as possible.

[0148] All patents, patent applications, published patent gazettes, and other materials such as articles, books, specifications, publications, and documents referenced herein are incorporated in their entirety by reference, with the exception of any prosecution history documents that are inconsistent with or contradict the content of this Application, and any documents that may have a limited effect on the broadest scope of the claims of this Application (currently or later relating to this Application). In the event of any inconsistency or contradiction between the descriptions, definitions, and / or use of terms in the appendices to this Application and the content of this Application, the descriptions, definitions, and / or use of terms in this Application shall prevail.

[0149] Finally, it should be understood that the embodiments described herein are merely illustrative of the principles of the embodiments herein. Other modifications may also be within the scope of this application. Therefore, alternative configurations of the embodiments herein may be considered consistent with the teachings herein, for example, without limitation. Thus, the embodiments herein are not limited to those explicitly introduced and described herein. [Explanation of Symbols]

[0150] 100 Signal Acquisition Circuit 110 First electrode 120 Second electrode 130 Differential Amplifier L1 First lead wire L2 Second lead wire 200 Signal Acquisition Circuit 210 First electrode 220 Second electrode 230 Differential Amplifier C10 First negative capacitance circuit C20 Second negative capacitance circuit C30 Third negative capacitance circuit 410 First operational amplifier R1 is the first resistor. R2 Second resistor C401 First capacitor 300 Signal Acquisition Circuit C40 Fourth negative capacitance circuit C402 Unit 1 C404 Second Unit G2 First Amplifier G3 Second Amplifier C46 Third negative feedback capacitor C48 Fourth negative feedback capacitor G1 Dual-Ended Differential Amplifier C42 First negative feedback capacitor C44 Second negative feedback capacitor 400 Signal Acquisition Circuit 501 Common-mode power frequency sources 530 Differential Amplifier R5, R6 resistance C5, C6 Capacitors L11 First lead wire L22 Second lead wire

Claims

1. A differential amplifier and A first electrode and a second electrode, The fourth negative capacitance circuit, Includes, The first electrode is connected to the first input terminal of the fourth negative capacitance circuit via a first lead wire. The second electrode is connected to the second input terminal of the fourth negative capacitance circuit via a second lead wire. The first output terminal of the fourth negative capacitance circuit is connected to the first input terminal of the differential amplifier. The second output terminal of the fourth negative capacitance circuit is connected to the second input terminal of the differential amplifier. The fourth negative capacitance circuit has a negative capacitance effect to cancel the parasitic capacitance to ground of the first lead wire and the parasitic capacitance to ground of the second lead wire. The fourth negative capacitance circuit includes a first unit and a second unit, The relative error between the absolute value of the equivalent capacitance of the first unit of the fourth negative capacitance circuit and the parasitic capacitance value to ground of the first lead wire is less than 50%. The relative error between the absolute value of the equivalent capacitance of the second unit of the fourth negative capacitance circuit and the parasitic capacitance of the second lead wire to ground is less than 50%. A signal acquisition circuit characterized by the following features.

2. The fourth negative capacitance circuit includes a double-ended differential amplifier, a first negative feedback capacitor, and a second negative feedback capacitor. The signal acquisition circuit according to claim 1, characterized in that the first negative feedback capacitor is connected between the first input terminal and the first output terminal of the double-ended differential amplifier, and the second negative feedback capacitor is connected between the second input terminal and the second output terminal of the double-ended differential amplifier.

3. The signal acquisition circuit according to claim 2, characterized in that the double-ended differential amplifier is an amplifier with a fixed gain.

4. The first unit includes a first amplifier and a third negative feedback capacitor, and the second unit includes a second amplifier and a fourth negative feedback capacitor, The signal acquisition circuit according to claim 1, characterized in that the third negative feedback capacitor is connected between the input terminal and the output terminal of the first amplifier, and the fourth negative feedback capacitor is connected between the input terminal and the output terminal of the second amplifier.

5. The signal acquisition circuit according to claim 1, further comprising a feedback control circuit for adjusting the equivalent capacitance value of the fourth negative capacitance circuit.

6. A wearable device characterized by including a signal acquisition circuit according to any one of claims 1 to 5.

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