Memory devices and memory systems

Abstract

To provide a memory device and a memory system, which can enhance read performances.SOLUTION: A memory device according to an embodiment includes a controller, a nonvolatile memory, and a cache memory. The controller is configured to: record multiple first addresses sequentially accessed to read data stored in the nonvolatile memory; acquire an address list including a second address within the recorded multiple first addresses and a third address within the multiple first addresses which is estimated to be accessed after the second address is accessed; read data from the nonvolatile memory based on the third address included in the address list when the second address included in the address list is accessed; and store the read data in the cache memory.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory device and a memory system.

Background Art

[0002] In recent years, memory devices including nonvolatile memories (e.g., NAND-type flash memories) are known, and it has been considered to use such a memory device as part of a main memory (main storage device) conventionally composed of DRAM (Dynamic Random Access Memory) or the like.

[0003] However, while the above-described memory device has an advantage of being lower in cost than DRAM, it has a longer data read latency than the DRAM. Therefore, it is required to improve the read performance of the memory device.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Therefore, the problem to be solved by the present invention is to provide a memory device and a memory system capable of improving read performance.

Means for Solving the Problems

[0006] The memory device according to the embodiment comprises a controller, a non-volatile memory, and a cache memory. The controller records a plurality of first addresses that are sequentially accessed to read data stored in the non-volatile memory, obtains an address list that includes a second address from the plurality of recorded first addresses and a third address from the plurality of first addresses that is presumed to be accessed after the second address has been accessed, and when a second address included in the address list is accessed, reads data from the non-volatile memory based on the third address included in the address list and stores the read data in the cache memory. The non-volatile memory includes multiple pages, which are units of data read operations. If two or more data items to be read based on a third address included in the address list are located on one of the multiple pages, the controller reads the two or more data items from that page in a single read operation and stores them in the cache memory. [Brief explanation of the drawing]

[0007] [Figure 1] A block diagram showing an example of the configuration of a memory device according to the first embodiment. [Figure 2] A diagram illustrating an example of access log processing in the first embodiment. [Figure 3] A diagram illustrating the overview of the operation of the access history analysis unit in the first embodiment. [Figure 4] A diagram showing an example of an access pattern in the first embodiment. [Figure 5] A diagram showing an example of an address list created from the access pattern in the first embodiment. [Figure 6] A diagram illustrating an example of data placement processing in the first embodiment. [Figure 7] A diagram showing an example of access playback data in the first embodiment. [Figure 8] A diagram illustrating an example of access regeneration processing in the first embodiment. [Figure 9] A diagram illustrating an example of the priority assigned to the logical addresses constituting the access pattern in the second embodiment. [Figure 10]A diagram illustrating an example of data placement processing in the second embodiment. [Figure 11] A flowchart showing an example of the processing procedure for access regeneration in the second embodiment. [Figure 12] This figure shows an example of how the access pattern changes due to conditional branching in the second embodiment. [Figure 13] A block diagram showing an example of the configuration of a memory device according to the third embodiment. [Figure 14] A diagram showing an example of access playback data in the third embodiment. [Figure 15] A flowchart showing an example of the processing procedure for access regeneration in the third embodiment. [Figure 16] A block diagram showing an example of the configuration of a memory device according to the fourth embodiment. [Modes for carrying out the invention]

[0008] The embodiments will be described below with reference to the drawings. (First Embodiment) First, the first embodiment will be described. Figure 1 is a block diagram showing an example of the configuration of a memory device according to this embodiment.

[0009] The memory device 10 according to this embodiment is configured to be connectable to a processor such as a CPU 20, and the memory device 10 and the CPU 20 constitute a memory system 30.

[0010] In this embodiment, the memory system 30 is used to realize serverless computing, which enables the execution of various programs (application programs) on the server without, for example, building or maintaining a server. In serverless computing, for example, it is possible to execute a pre-registered program in response to an event (trigger), such as a file upload or message reception, at a predetermined time (i.e., at a set time).

[0011] By the way, in the above-described serverless computing, a program may be executed in a short time. In such a case, it is preferable to speed up the startup part of the program.

[0012] In this case, in order to eliminate the overhead of the startup part, when maintaining the memory state in the started state, a large-capacity memory is required.

[0013] In the memory system 30, for example, DRAM (not shown) is used as the main memory, but increasing the capacity of the DRAM is costly.

[0014] Therefore, in the present embodiment, the memory device 10 that constitutes the memory system 30 used as a server for realizing the above-described serverless computing is made to operate as the main memory connected to the CPU 20. Note that the memory device 10 has a non-volatile memory and has intermediate performance between DRAM and a storage device (for example, SSD or the like). Specifically, the storage capacity of the memory device 10 is larger than that of the main memory (DRAM), and the access speed to the memory device 10 is higher than that of the storage device. In the present embodiment, by using such a memory device 10, a substantial increase in the capacity of the main memory is realized.

[0015] However, the memory device 10 has a longer data read latency than DRAM, and the performance (application performance) of the program executed in the server as described above deteriorates.

[0016] In the present embodiment, a memory device 10 (and a memory system 30) that suppresses such a decrease in application performance (that is, improves the read performance) is provided. Note that the memory device 10 according to the present embodiment operates as a part of the main memory as described above, and thus is treated as a volatile memory device while being a non-volatile storage device.

[0017] The memory device 10 is connected to the CPU 20, for example, via a memory bus. The memory bus connecting the memory device 10 and the CPU 20 is, for example, a Compute Express Link. TM (CXL TM CXL compliant with the standard TM This includes buses, but buses conforming to other standards are also acceptable.

[0018] In this embodiment, the CPU 20 is, for example, a multi-core processor, and accesses the memory device 10 via a memory bus. Specifically, the CPU 20 sends a store command, which is a write access request for writing data, to the memory device 10. The CPU 20 also sends a load command, which is a read access request for reading data, to the memory device 10.

[0019] When the CPU 20 accesses the memory device 10, the physical memory address converted from the virtual memory address used by the program (application program) is used. That is, in the write access request (store command) and read access request (load command) described above, the physical memory address converted from the virtual memory address is specified, and when the CPU 20 accesses the memory device 10, this physical memory address is sent from the CPU 20 to the memory device 10. In the following explanation, the physical memory address specified by the CPU 20 when the CPU 20 accesses the memory device 10 (the physical memory address sent from the CPU 20 to the memory device 10) will be referred to as a logical address for convenience.

[0020] Furthermore, read / write access to the memory device 10 via the memory bus is performed with a predetermined data granularity. The data granularity is, for example, 64 bytes (64B), but may also be 128 bytes (128B) or 256 bytes (256B), etc. If the data granularity is, for example, 64 bytes, the CPU 20 can access the 64 bytes of data by sending a logical address from the CPU 20 to the memory device 10.

[0021] The memory device 10 includes a NAND flash memory 11, a cache memory 12, and a controller 13.

[0022] The NAND flash memory 11 is a non-volatile memory. Specifically, the NAND flash memory 11 is, for example, a three-dimensional flash memory. The NAND flash memory 11 has multiple blocks. Each of the multiple blocks is a unit of data erasure operation. Each of the multiple blocks contains multiple physical pages. Each of the multiple physical pages contains multiple memory cells connected to the same word line. Each of the multiple physical pages is a unit of data program operation and data read operation. The size of each of the multiple physical pages is larger than the data access unit. When reading data placed in a page, the NAND flash memory 11 can output only a portion of the data read from one physical page (data equivalent to the size of one physical page).

[0023] As described above, when a logical address is sent from the CPU 20 to the memory device 10 (i.e., when the CPU 20 accesses the logical address), the logical address is translated into an address indicating the physical location within the NAND flash memory 11 (hereinafter referred to as the physical address) based on the address translation table. That is, when writing data to or reading data from the NAND flash memory 11 shown in Figure 1, the physical address is used. The controller that performs such address translation (the controller that controls the NAND flash memory 11) is assumed to be included in the NAND flash memory 11 shown in Figure 1. The address translation table described above may be stored in the NAND flash memory 11 or it may be held in DRAM (not shown).

[0024] The cache memory 12 is a volatile memory that operates as a cache memory for the NAND flash memory 11, and operates to cache the data read from the NAND flash memory 11. The cache memory 12 is implemented, for example, by DRAM or SRAM (Static Random Access Memory) provided in the memory device 10. Although not shown in Figure 1, the controller that controls the cache memory 12 is assumed to be included in the cache memory 12 shown in Figure 1.

[0025] Here, we will briefly explain the operation of the NAND flash memory 11 and cache memory 12 described above.

[0026] For example, when the CPU 20 reads data from the memory device 10, the logical address accessed by the CPU 20 is sent from the CPU 20 to the memory device 10. If the data to be read based on the logical address sent from the CPU 20 (hereinafter referred to as the data to be read) is stored in the cache memory 12, the memory device 10 reads the data to be read from the cache memory 12 and returns the data to the CPU 20.

[0027] On the other hand, if the data to be read is not stored in the cache memory 12, the memory device 10 reads the data to be read from the NAND flash memory 11 and returns the data to the CPU 20.

[0028] Since the cache memory 12 (for example, DRAM) can read data faster than the NAND flash memory 11, the read performance of the memory device 10 can be improved when the data to be read is stored in the cache memory 12. On the other hand, if the data to be read is not stored in the cache memory 12, the read performance of the memory device 10 cannot be improved.

[0029] Here, for example, if the data to be read is read from the NAND flash memory 11 as described above, the data to be read is stored in the cache memory 12. Therefore, if the logical address for reading the data to be read is sent again from the CPU 20 while the data to be read is stored in the cache memory 12, the data to be read can be read from the cache memory 12 at high speed.

[0030] However, the capacity of the cache memory 12 is finite, and data stored in the cache memory 12 may be erased from the cache memory 12 over time. When the memory system 30 according to this embodiment is used as a server to realize serverless computing as described above, it is thought that the same program will be executed repeatedly on the server, but since the program is executed, for example, in response to the occurrence of an event, the timing of the program's execution is unknown. For this reason, even if data is stored in the cache memory 12 when the program is executed once, it is possible that the data has already been erased from the cache memory 12 when the program is executed again.

[0031] Therefore, in this embodiment, the controller 13 takes advantage of the property that when the same program is executed, the same data is often read (the same data is accessed) as during the previous execution, and operates to prefetch data based on the access pattern (data reading pattern) from the CPU 20 to the memory device 10. In this embodiment, "prefetching data" means reading the data stored in the NAND flash memory 11 in advance and storing the read data in the cache memory 12.

[0032] The controller 13 includes an access recording unit 131, a placement unit 132, and an access playback unit 133.

[0033] The access recording unit 131 records the CPU 20's access to the memory device 10. Specifically, the access recording unit 131 stores a sequence of logical addresses (i.e., multiple logical addresses sequentially accessed by the CPU 20 to read data stored in the NAND flash memory 11) transmitted from the CPU 20 to the memory device 10 (hereinafter referred to as the address sequence). The address sequence (recorded sequence) recorded by the access recording unit 131 is then transmitted to, for example, the access history analysis unit 40 located outside the memory device 10.

[0034] The access history analysis unit 40 analyzes the address sequence (history of logical addresses accessed sequentially by the CPU 20) transmitted from the access recording unit 131. This allows the access history analysis unit 40 to identify the logical address that triggers the prefetch (hereinafter referred to as the trigger address) and the logical address that is estimated to be accessed after the trigger address (i.e., accessed at a time close to the trigger address) (hereinafter referred to as the replay target logical address) from the address sequence. The list containing the trigger address and the replay target logical address identified by the access history analysis unit 40 (hereinafter referred to as the address list) is transmitted to the placement unit 132.

[0035] The access history analysis unit 40 is assumed to be implemented by, for example, the CPU 20, but it may also be implemented by a processor (or controller) other than the CPU 20.

[0036] The placement unit 132 reads data (hereinafter referred to as "data to be regenerated") from the NAND flash memory 11 based on the logical address to be regenerated included in the address list transmitted from the access history analysis unit 40, and places (writes) the data to be regenerated into the same page (hereinafter referred to as "page to be regenerated") among the multiple pages contained in the NAND flash memory 11.

[0037] The placement unit 132 outputs access playback data to the access playback unit 133, which includes the trigger address included in the address list output from the access history analysis unit 40 and the physical address (hereinafter referred to as the playback target physical address) which includes the page number (the page number assigned to the page) for identifying the page to be played back.

[0038] The access regeneration unit 133 monitors the logical address (the logical address accessed by the CPU 20 to read data stored in the NAND flash memory 11) that is sent from the CPU 20 to the memory device 10 by referring to the access regeneration data output from the placement unit 132. When the CPU 20 accesses the trigger address included in the access regeneration data, the access regeneration unit 133 instructs the NAND flash memory 11 to prefetch. In this case, the data to be regenerated, which is placed in the page to be regenerated based on the physical address to be regenerated (the page number included therein) included in the access regeneration data, is read from the NAND flash memory 11, and the data to be regenerated is stored in the cache memory 12.

[0039] The operation of the memory device 10 according to this embodiment will be described below. Here, we will mainly describe the processing performed by the access recording unit 131 (hereinafter referred to as the access recording process), the processing performed by the placement unit 132 (hereinafter referred to as the data placement process), and the processing performed by the access playback unit 133 (hereinafter referred to as the access playback process).

[0040] First, the access recording process will be explained with reference to Figure 2. Note that in Figure 2, the placement unit 132 and the access playback unit 133 included in the controller 13 are omitted.

[0041] As described above, in this embodiment, the access recording unit 131 records a sequence of multiple logical addresses (address sequence) that are sequentially accessed by the CPU 20. However, the period for recording the address sequence (the timing for starting and ending the recording of the address sequence) is instructed, for example, from outside the memory device 10 (for example, the CPU 20).

[0042] Specifically, if the instruction to start recording the address sequence (hereinafter simply referred to as the recording start timing) is set to record_start, then this record_start is sent to the access recording unit 131 at the timing when the execution of a predetermined program starts on the memory system 30 (the server in serverless computing) (step S1). The record_start sent in step S1 is stored in a register, for example, provided in the controller 13. As a result, the access recording unit 131 starts recording the address sequence.

[0043] Next, when the CPU 20 reads data from the memory device 10 (NAND flash memory 11) during program execution, the logical address accessed by the CPU 20 is sent from the CPU 20 to the memory device 10 (step S2).

[0044] In this case, the access recording unit 131 obtains the logical address sent from the CPU 20 in step S2 (step S3). The logical address obtained in step S3 is temporarily recorded in the access recording unit 131.

[0045] Here, the recording start timing is indicated by record_start as described above, but the timing to end the recording of that address sequence (hereinafter simply referred to as the recording end timing) is indicated by record_end.

[0046] Assuming that the record_start message described above is sent to the access recording unit 131 when the execution of a predetermined program begins, the record_end message is sent to the access recording unit 131 when the execution of that program ends (step S4). The record_end message sent in step S4 is stored in a register, for example, provided in the controller 13. As a result, the access recording unit 131 terminates the recording of the address sequence.

[0047] In this embodiment, the processes in steps S2 and S3 described above are repeatedly executed between the recording start timing (the timing when record_start is stored in the register) and the recording end timing (the timing when record_end is stored in the register). As a result, the access recording unit 131 can record the address sequence (a sequence of multiple logical addresses) described above.

[0048] The address sequence recorded by the access recording unit 131 is transmitted from the access recording unit 131 to the access history analysis unit 40 (step S5). Here, it is assumed that multiple logical addresses recorded between the recording start timing and the recording end timing are transmitted together from the access recording unit 131 to the access history analysis unit 40. However, these logical addresses may also be transmitted individually from the access recording unit 131 to the access history analysis unit 40 each time they are transmitted from the CPU 20.

[0049] Here, we have explained that the recording of address sequences begins when record_start is stored in the register and ends when record_end is stored in the register (i.e., there are explicit instructions regarding the start and end of recording). However, for example, the recording of address sequences may begin when a specific logical address is sent from the CPU 20 to the memory device 10 (when the CPU 20 accesses the specific logical address) and end when another specific logical address is sent from the CPU 20 to the memory device 10 (when the CPU 20 accesses the specific logical address). In this case, the specific logical address shall be assumed to be set separately in the memory device 10 in advance. Furthermore, the timing of the end of address sequence recording may also be when a predetermined number of logical addresses have been recorded (acquired).

[0050] Furthermore, although Figure 2 mainly describes the processing performed by the access recording unit 131, the data to be read (data to be read) based on the logical address sent from the CPU 20 to the memory device 10 during the access recording process is returned to the CPU 20 from, for example, the NAND flash memory 11.

[0051] By the way, when the access recording process described above is executed and an address sequence (i.e., access history) is transmitted from the access recording unit 131 to the access history analysis unit 40, the access history analysis unit 40 analyzes the said address sequence.

[0052] The operation (processing) of the access history analysis unit 40 will be briefly explained below with reference to Figure 3.

[0053] First, in this embodiment, the CPU 20 provided in the memory system 30 is, for example, a multi-core processor and is configured to execute multiple programs (application programs) in parallel.

[0054] In this case, even if the access recording unit 131 records an address sequence based on record_start and record_end as described above, the recorded address sequence may contain a mixture of logical addresses accessed by the CPU 20 (i.e., sent from the CPU 20) to execute program A and logical addresses accessed by the CPU 20 to execute program B, which is different from program A.

[0055] Therefore, the access history analysis unit 40 extracts a sequence of logical addresses (hereinafter referred to as the access pattern) accessed by the CPU 20 when executing a predetermined program (for example, program A) from the address sequence transmitted from the access recording unit 131.

[0056] Here, we assume that the address sequence 100 transmitted from the access recording unit 131 to the access history analysis unit 40 is "A0, B0, A1, A2, B1, A3, B2, ..." as shown in Figure 3. The "A0", "A1", and "A2" etc. that make up the address sequence 100 shown in Figure 3 represent the logical addresses accessed by the CPU 20 to execute program A, and the "B0", "B1", and "B2" etc. that make up the address sequence 100 represent the logical addresses accessed by the CPU 20 to execute program B. In other words, the address sequence 100 is the address sequence when programs A and B are executed in parallel on the CPU 20.

[0057] In this case, the access history analysis unit 40 is assumed to have in advance a range of virtual memory addresses and physical memory addresses (logical addresses) that may be used when executing program A, for example (hereinafter referred to as the address range).

[0058] The access history analysis unit 40 compares the address sequence 100 (the multiple logical addresses that make up it) transmitted from the access recording unit 131 with the address range (the logical addresses included in it) that may be used when executing program A. In doing so, it can extract an access pattern from the address sequence that is related only to program A (i.e., the sequence of logical addresses accessed by the CPU 20 when executing program A). As a result, an access pattern 200 (A0, A1, A2, A3, A4, ...) is extracted from the address sequence 100.

[0059] In this explanation, the access pattern 200 is extracted based on the address range that may be used when program A is executed. However, if the address range that may be used when program A is executed can be separated by a simple conditional comparison, the access pattern 200 may be extracted by a simpler process based on that range. Specifically, for example, if the range of logical addresses that may be used when program A is executed and the range of logical addresses that may be used when program B is executed can be easily determined by a comparison of the magnitudes of predetermined logical addresses (i.e., the address spaces are clearly separated), the access pattern may be extracted based on the result of that comparison.

[0060] Furthermore, although it has been explained here that access patterns are extracted from address sequences transmitted from the access recording unit 131 to the access history analysis unit 40, if, for example, the address spaces described above are clearly separated, making it easy to determine logical addresses that may be used when a particular program is executed, the access recording unit 131 may record only the logical addresses (sequences of logical addresses) that may be used when that particular program is executed by performing a comparison and determination process on the logical addresses input to the access recording unit 131, thereby reducing the recording capacity of the access recording unit 131 and the processing load of the access history analysis unit 40.

[0061] The access history analysis unit 40 creates an address list (the address list of program A) based on the access pattern 200 described above. The address list may be created based solely on the access pattern 200, or it may be created by further considering past access patterns managed by the access history analysis unit 40 (i.e., based on multiple access patterns extracted from address sequences recorded multiple times).

[0062] The address list created by the access history analysis unit 40 will be described below with reference to Figures 4 and 5.

[0063] Figure 4 shows an example of access pattern 200 (a sequence of logical addresses accessed by the CPU 20 when executing program A). In the example shown in Figure 4, it is shown that logical addresses A0 to A15 were accessed sequentially by the CPU 20 when executing program A.

[0064] Here, as described above, the address list created by the access history analysis unit 40 includes the trigger address and the logical address to be replayed, in association with each other.

[0065] In the case of the access pattern 200 shown in Figure 4, the access history analysis unit 40 determines, for example, the logical address A0 located at the beginning of the sequence (arrangement) of multiple logical addresses constituting the access pattern 200 as the first trigger address. The access history analysis unit 40 also determines, for example, logical addresses A8 to A11 among the multiple logical addresses constituting the access pattern 200 as the first logical addresses to be replayed, corresponding to the trigger address A0.

[0066] Here, we have explained that logical address A0, which is located at the beginning of the access pattern 200, is determined as the first trigger address, and logical addresses A8 to A11, which are located between trigger address A0 and a predetermined number of other logical addresses (in this case, seven) in the access pattern 200, are determined as the first replayable logical addresses. However, the first trigger address and the first replayable logical addresses can be determined in accordance with rules predetermined by the access history analysis unit 40.

[0067] However, as will be described later, the data read based on the first replayable logical address (replayable data) is stored in the cache memory 12 when the trigger address is accessed by the CPU 20. Therefore, if logical addresses are accessed sequentially as in the access pattern 200 when program A is executed, if the number of logical addresses placed between the first trigger address and the first replayable logical address corresponding to the first trigger address is small, the first replayable logical address may be accessed by the CPU 20 before the replayable data is stored in the cache memory 12. On the other hand, if the number of logical addresses placed between the first trigger address and the first replayable logical address corresponding to the first trigger address is large, the replayable data may have already been erased from the cache memory 12 when the first replayable logical address is accessed by the CPU 20 after the first trigger address has been accessed. In other words, in this embodiment, depending on the timing of when the first replayable logical address is accessed by the CPU 20 after the first trigger address has been accessed, the cache memory 12 may not be able to be used effectively. For this reason, in this embodiment, the first trigger address and the first replayable logical address described above are determined in such a way that the cache memory 12 can be used appropriately.

[0068] Furthermore, although only one trigger address A0 (and the replay target logical addresses A8 to A11 corresponding to that trigger address A0) has been described here, there may be multiple trigger addresses determined from the access pattern 200. Specifically, the access history analysis unit 40 may further determine logical address A4 from among the multiple logical addresses constituting the access pattern 200 as a second trigger address, and further determine logical addresses A12 to A15 as second replay target logical addresses corresponding to that trigger address A4.

[0069] Figure 5 shows an example of an address list created from the access pattern 200 described above. In the example shown in Figure 5, the address list includes the trigger address "A0" and the replayable logical addresses "A8, A9, A10, A11" in association. The address list also includes the trigger address "A4" and the replayable logical addresses "A12, A13, A14, A15" in association.

[0070] In this embodiment, it is assumed that the address list contains multiple regenerative logical addresses corresponding to one trigger address, but the number of regenerative logical addresses corresponding to one trigger address may be just one.

[0071] Furthermore, a specific logical address to be regenerated may correspond to multiple trigger addresses. Specifically, the logical addresses to be regenerated may be associated with trigger address "A0" as "A8, A9, A10, A11, A12, A13, A14, A15", and the logical addresses to be regenerated may be associated with trigger address "A4" as "A12, A13, A14, A15, A16, A17, A18, A19". In this case, the logical addresses to be regenerated "A12, A13, A14, A15" are logical addresses to be regenerated that correspond to both trigger addresses "A0" and "A4". When program A is actually executed, if trigger address "A0" is accessed, the replayable logical addresses "A8, A9, A10, A11, A12, A13, A14, A15" will be replayed, and if trigger address "A4" is accessed, the replayable logical addresses "A12, A13, A14, A15, A16, A17, A18, A19" will be replayed. However, the replayable logical addresses "A12, A13, A14, A15" may be duplicates. In this case, since the logical addresses to be regenerated "A8, A9, A10, A11, A12, A13, A14, A15" have already been regenerated by accessing the trigger address "A0", when the trigger address "A4" is accessed, only the logical addresses to be regenerated "A16, A17, A18, A19" may be regenerated, and the duplicate logical addresses to be regenerated "A12, A13, A14, A15" may not be processed.

[0072] Here, it has been explained that an access pattern 200 is extracted from the address sequence 100 described above, and an address list (the address list of program A) is created from this access pattern 200. However, it is also acceptable for the sequence of logical addresses accessed by the CPU 20 when program B is executed to be extracted as an access pattern from the address sequence 100, and for an address list (the address list of program B) to be created from this access pattern.

[0073] As described above, the address list created by the access history analysis unit 40 is sent to the placement unit 132 included in the controller 13.

[0074] Next, the data placement process will be explained with reference to Figure 6. Note that the access recording unit 131 included in the controller 13 is omitted in Figure 6.

[0075] First, the placement unit 132 obtains the address list sent from the access history analysis unit 40 as described above (step S11).

[0076] Next, the placement unit 132 obtains multiple logical addresses to be regenerated from the address list acquired in step S11.

[0077] Here, the logical address to be retrieved corresponds to the logical address that is presumed to be accessed after the trigger address included in the address list, associated with the logical address to be retrieved, is accessed by the CPU 20 (i.e., the logical address accessed at a time close to the trigger address), and the data to be retrieved read based on the logical address to be retrieved is the data that will be prefetched when the trigger address is accessed by the CPU 20, as will be described later.

[0078] However, the data to be retrieved, which is read based on each of the multiple logical addresses to be retrieved, is often stored (written) in a distributed manner across multiple pages (physical pages) contained in, for example, the NAND flash memory 11. Reading such data to be retrieved from each of these multiple pages during prefetching can lead to performance degradation of the memory device 10.

[0079] Therefore, the placement unit 132, for example, via a controller that controls the NAND flash memory 11, acquires the data to be recovered from the NAND flash memory 11 based on each of the multiple logical addresses to be recovered obtained from the address list (step S12).

[0080] In step S12, the controller controlling the NAND flash memory 11 can read the data to be regenerated from the NAND flash memory 11 based on the physical address by referring to the address translation table described above and converting each of the multiple logical addresses to be regenerated into a physical address.

[0081] When the process in step S12 is executed, the placement unit 132, via a controller that controls the NAND flash memory 11, places the data to be replayed acquired in step S12 into the same page (replayable page) contained in the NAND flash memory 11 (step S13). The process in step S13 corresponds to, for example, packing the data to be replayed, which is distributed across multiple pages, into a single page.

[0082] When the process in step S13 is executed, the address translation table is updated to store (manage) the correspondence between the logical address to be regenerated and the address indicating the physical location within the NAND type address where the data to be regenerated is located (stored) (physical address). This process of updating the address translation table is performed, for example, by the management unit that manages the address translation table, but if the placement unit 132 is configured to be able to access the address translation table, the placement unit 132 may update the address translation table.

[0083] Next, the placement unit 132 generates access playback data that includes a trigger address included in the address list and a playback target physical address that includes a page number for identifying the playback target page on which the playback target data is placed. In this embodiment, for convenience, the playback target physical address is described as including at least a page number, but the playback target physical address may also include information such as a block number and information indicating the position within the page identified by the page number (in-page offset).

[0084] The access playback data generated by the arrangement unit 132 in this manner is output to the access playback unit 133 (step S14).

[0085] The processing in steps S12 to S14 described above is performed for each trigger address (and logical address to be replayed) included in the address list obtained in step S11. That is, for example, if the address list shown in Figure 5 is obtained in step S11, then in step S14, the access replay data shown in Figure 7 is output from the placement unit 132 to the access replay unit 133.

[0086] Figure 7 shows multiple access regeneration data, including access regeneration data 132a and 132b. Specifically, access regeneration data 132a includes the trigger address "A0" and the regeneration target physical address "P2" in association. According to this access regeneration data 132a, the regeneration target data read from the NAND flash memory 11 based on the regeneration target logical addresses A8 to A11 included in the address list associated with the trigger address A0 is placed in the regeneration target page identified by the page number included in the regeneration target physical address P2.

[0087] Furthermore, the access retrieval data 132b includes the trigger address "A4" and the retrieval target physical address "P3" in association. According to this access retrieval data 132b, the retrieval target data read from the NAND flash memory 11 based on the retrieval target logical addresses A12 to A15 included in the address list associated with the trigger address A4 is placed within the retrieval target page identified by the page number included in the retrieval target physical address P3.

[0088] In this explanation, we have assumed that the data for access and playback contains only one page number. However, if the data to be played back is spread across multiple pages, the number of page numbers included in the physical address to be played back may be multiple. In this case, the physical address to be played back may be a sequence of multiple page numbers, or it may be a pair of the first page number and the page number.

[0089] Furthermore, if the data to be reproduced is located at the beginning of the page to be reproduced, the data can be read using only the page number included in the physical address of the data to be reproduced. However, if the data to be reproduced is located anywhere other than the beginning of the page, the data can be read based on the page number and the in-page offset included in the physical address of the data to be reproduced. In addition, the data to be reproduced may be read using length information indicating the length of the data to be reproduced. This makes it possible to read the amount of data to be reproduced corresponding to the length information from the in-page offset position of a specific page number. The length information may be stored on the NAND flash memory 11 side. This allows for a configuration in which, when a trigger address is accessed, data is read from the in-page offset position of a specific page number, and the amount of data to be reproduced corresponding to the length information from the read data is read and processed.

[0090] Next, the access playback process will be explained with reference to Figure 8. Note that in Figure 8, the access recording unit 131 and the placement unit 132 included in the controller 13, and the access history analysis unit 40 are omitted.

[0091] First, when the CPU 20 reads data from the memory device 10 (NAND flash memory 11), the logical address accessed by the CPU 20 is sent from the CPU 20 to the memory device 10 (step S21).

[0092] In this case, the access regeneration unit 133 refers to the access regeneration data mentioned above in order to prefetch the data to be regenerated (i.e., store it in the cache memory 12) and monitors the logical address sent from the CPU 20 to the memory device 10 (step S22). Specifically, in step S22, a process is executed to determine whether or not the trigger address included in the access regeneration data has been accessed by the CPU 20, based on the logical address sent from the CPU 20 in step S21.

[0093] If the CPU 20 determines that a trigger address included in the access regeneration data has been accessed, the access regeneration unit 133 obtains the regeneration target physical address included in the access regeneration data in association with that trigger address. Here, it has been explained that the regeneration target physical address is obtained simply when it is determined that a trigger address has been accessed, but other processes may be performed. Specifically, even if it is determined that a trigger address has been accessed, if prefetching based on the regeneration target physical address associated with that trigger address has already been performed, the regeneration target physical address may not be obtained.

[0094] The access regeneration unit 133 instructs the NAND flash memory 11 and the cache memory 12 to prefetch based on the acquired physical address to be regenerated (step S23).

[0095] When the process in step S23 is executed, the controller controlling the NAND flash memory 11 reads the data to be regenerated from the NAND flash memory 11 based on the physical address to be regenerated instructed by the access regeneration unit 133, and stores the data to be regenerated in a buffer (not shown). The data to be regenerated stored in the buffer in this way is read by the controller controlling the cache memory 12 and stored in the cache memory 12.

[0096] According to the access regeneration process described above, when a trigger address is accessed by the CPU 20, the data accessed (read) based on the regeneration target logical address that is presumed to be accessed after the trigger address can be regenerated (reproduced) on the cache memory 12.

[0097] Here, we have described a scenario where prefetching is instructed when the trigger address is accessed by the CPU 20. However, it is also possible to configure the system so that the timing of the prefetching is notified from the CPU 20 to the memory device 10 using, for example, a sideband signal.

[0098] Furthermore, the start of a specific program (for example, program A) may be notified to the memory device 10 using the sideband signal described above. This means that, for example, even when many programs are executed in parallel in the CPU 20, it is only necessary to monitor the trigger addresses that may be used when executing a specific program whose start has been notified by the sideband signal, which may reduce the processing load on the access regeneration unit 133.

[0099] Furthermore, the data read from the CPU 20 to the memory device 10 based on the logical address (trigger address) during the access and playback process is returned to the CPU 20 from, for example, the NAND flash memory 11.

[0100] Next, we will specifically explain the access playback process using the access playback data shown in Figure 7 above.

[0101] First, the access regeneration unit 133 monitors the logical address sent from the CPU 20 to the memory device 10, as described above.

[0102] Let's assume that the CPU 20 has sent logical address A0 to the memory device 10. In this case, since the access regeneration data 132a shown in Figure 7 contains trigger address A0, the access regeneration unit 133 determines that the trigger address has been accessed by the CPU 20.

[0103] Next, the access regeneration unit 133 obtains the physical address P2 to be regenerated, which is included in the access regeneration data 132a and is associated with the trigger address (logical address A0).

[0104] The access retrieval unit 133 instructs prefetching based on the acquired retrieval target physical address P2. In this case, for example, retrieval target data corresponding to the data to be read based on the four logical addresses from the beginning of the retrieval target page identified by the page number contained in the retrieval target physical address P2 (here, 64 bytes × 4 of data read based on retrieval target logical addresses A8 to A11) is read.

[0105] Here, we assume that the data to be played back is located at the beginning of the page to be played back, which is identified by the page number contained in the physical address P2. However, if the data to be played back is not located at the beginning of the page, the data to be played back can be read based on the page number and in-page offset contained in the physical address.

[0106] As described above, the data to be retrieved read from the NAND flash memory 11 is stored in a buffer and then in the cache memory 12. It is assumed that the fact that the data to be retrieved stored in the cache memory 12 is read based on the logical addresses A8 to A11 (i.e., a list showing the correspondence between the data to be retrieved and the logical addresses to be retrieved) is managed within the memory device 10 (for example, the NAND flash memory 11).

[0107] For example, according to the access pattern 200 shown in Figure 4, it is highly likely that logical addresses A1 to A15 will be accessed sequentially by the CPU 20 after logical address A0. If the CPU 20 then accesses logical addresses A8 to A11 after the access regeneration process described above has been executed (i.e., trigger address A0 has been accessed by the CPU 20), the data read based on those logical addresses A8 to A11 will be returned from the cache memory 12 to the CPU 20.

[0108] Although the operation will be the same for subsequent steps and therefore a detailed explanation will be omitted, when the logical address A4 is sent from the CPU 20 to the memory device 10, the data to be regenerated (in this case, 64 bytes x 4 data read based on the logical addresses A12 to A15) corresponding to the data read from the first four logical addresses of the regenerated page identified by the page number contained in the physical address P3 to be regenerated is read, and the data to be regenerated is stored in the cache memory 12. Accordingly, if the CPU 20 accesses the trigger address A4 and then accesses the logical addresses A12 to A15, the data read based on those logical addresses A12 to A15 is returned from the cache memory 12 to the CPU 20.

[0109] As described above, in this embodiment, the controller 13 provided in the memory device 10 records a plurality of logical addresses (first addresses) that are accessed sequentially in order to read data stored in the NAND flash memory 11 (non-volatile memory), obtains an address list that includes a trigger address (second address) from the plurality of recorded logical addresses and a recovery target logical address (third address) from the plurality of logical addresses that is presumed to be accessed after the trigger address has been accessed, and when a trigger address included in the address list is accessed, reads the recovery target data from the NAND flash memory 11 based on the recovery target logical address included in the address list and stores the read recovery target data in the cache memory 12.

[0110] In other words, in this embodiment, for example, when the memory system 30 is used as a server in serverless computing, a pre-registered program is repeatedly executed (i.e., the same access to the memory device 10 is repeatedly performed), and data is prefetched based on the CPU 20's access pattern to the memory device 10 (the sequence of logical addresses accessed by the CPU 20).

[0111] In this embodiment, with this configuration, when a logical address to be retrieved is accessed after a trigger address, the data to be read based on that logical address is already stored in the cache memory 12 (i.e., the data can be read from the cache memory 12, which is faster than the NAND flash memory 11). As a result, latency caused by reading data from the memory device 10 (NAND flash memory 11) can be hidden, and the read performance of the memory device 10 can be improved.

[0112] Furthermore, in this embodiment, the NAND flash memory 11 includes multiple pages, which are units of data reading operations, the address list includes multiple logical addresses to be rewound, and the controller 13 places the data to be read based on each of the multiple logical addresses to be rewound (rewound data) within the same page before the trigger address included in the address list is accessed.

[0113] For example, if the address list shown in Figure 5 is obtained from the access history analysis unit 40, when logical address (trigger address) A0 is accessed, the data to be regenerated, which is read based on logical addresses (regenerated logical addresses) A8 to A11, is read from the NAND flash memory 11 and stored in the cache memory 12.

[0114] In this case, if the data to be retrieved based on logical addresses A8 to A11 is stored (written) on different pages, it is necessary to retrieve the data from each of those different pages, which is inefficient.

[0115] In contrast, in this embodiment, as described above, by arranging (packing) the data to be rewound, which is read based on multiple logical addresses to be rewound, into a single page, it is possible to avoid inefficient access (data reading operation) to the NAND flash memory 11 during prefetching and reduce the required IOPS (Input / Output Per Second) for said prefetching.

[0116] In this embodiment, it is assumed that the controller included in the NAND flash memory 11 converts logical addresses to physical addresses, but such address conversion may also be performed by, for example, a controller that controls the cache memory 12.

[0117] Furthermore, while this embodiment assumes operation using logical addresses for prefetching, in the case where address translation is performed by the controller controlling the cache memory 12 as described above, cache data management may be performed on a physical address basis instead of a logical address basis. In that case, prefetching from the NAND flash memory 11 can be performed using only physical addresses, without using logical addresses. Such a configuration has the advantage that it does not require managing a list showing the correspondence between data to be retrieved (prefetched) and logical addresses.

[0118] In this embodiment, multiple data to be replayed are described as being placed within a single page. However, if the data to be replayed can be prefetched before the logical address of the data to be replayed is accessed, the read performance of the memory device 10 can be improved. Therefore, it is also possible to adopt a configuration that omits the process of placing multiple data to be replayed within a single page. Furthermore, even in a configuration that omits the process of placing multiple data to be replayed within a single page, if two or more of the data to be replayed are located within the same page, the read performance can be further improved by reading the data from that page (i.e., reading multiple data to be replayed in a single page read operation).

[0119] Furthermore, as described above, if the data to be replayed, which is read based on each of the multiple logical addresses to be replayed, is located within the same page, access replay data is generated that includes a trigger address and a physical address to be replayed (a fourth address) which includes a page number to identify the page. When the trigger address included in the access replay data is accessed, the data to be replayed is read from the NAND flash memory 11 based on the physical address to be replayed included in the access replay data. With this configuration, multiple data to be replayed located within the same page (replayable page) can be appropriately read from the NAND flash memory 11 and stored in the cache memory 12 (i.e., prefetched).

[0120] Incidentally, according to the address list shown in Figure 5 and the access retrieval data shown in Figure 7, data read based on logical addresses from logical address A8 onwards can be read at high speed from the cache memory 12 by prefetching. However, data read based on logical addresses A0 to A7 is not stored in the cache memory 12 and cannot be read at high speed. For this reason, for example, in the data placement process described above, a process may be further executed to pre-store the data to be read based on logical addresses A0 to A7 in the cache memory 12. This makes it possible to quickly return the data read based on logical addresses A0 to A7 from the cache memory 12 to the CPU 20 even when the CPU 20 accesses those logical addresses. Here, it has been explained that the data read based on logical addresses A0 to A7 is stored in the cache memory 12, but it is sufficient that the data be stored in a storage area that can read data at a higher speed than the NAND flash memory 11 (for example, DRAM used as main memory in the memory system 30 or other memory within the memory device 10). In other words, in this embodiment, the starting portion of an access pattern that cannot be prefetched (the data read based on the corresponding logical address) may be pinned to a high-speed recording area.

[0121] Furthermore, in this embodiment, the address sequence is recorded during the first execution of a specific program (for example, program A), and prefetched during subsequent executions of the same program. However, during the first execution of the program, all data must be read from the NAND flash memory 11, resulting in long latency. For this reason, data read based on logical addresses (sequences of addresses) accessed during the execution of a specific program for which access replay data has not yet been generated may be allocated to use DRAM or the like, which is used as main memory, instead of the NAND flash memory 11. With such a configuration, data can be read at high speed even during the first execution of a specific program. However, even when using DRAM as described above, the CPU 20 accesses the DRAM via the memory device 10. In other words, even when data is read from DRAM, the operation of the CPU 20 is the same as when accessing the memory device 10. That is, whether it is NAND flash memory 11 or DRAM, it is accessed using addresses with the same logic. The physical address that corresponds to that logical address and is translated internally within the memory device 10 differs in whether it points to the NAND flash memory 11 or the DRAM (main memory).

[0122] Furthermore, since the system is configured to prefetch data during the second execution of a particular program, once the first execution of that particular program is complete, the data stored in the cache memory 12 or the DRAM used as main memory in the memory system 30 may be deleted. However, if the data stored in the NAND flash memory 11 is not copied to the DRAM, but exists only in the DRAM, then it is necessary to move the data from the DRAM to the NAND flash memory 11.

[0123] Furthermore, in this embodiment, the same program is executed repeatedly, and as described above, the generated access regeneration data can be used repeatedly each time the program is executed. However, the access regeneration data may also be periodically modified (updated) based on the address sequence recorded each time the program is executed.

[0124] Furthermore, the modification of the access regeneration data may be performed, for example, when the cache hit rate of the prefetched data is low (i.e., triggered by a low cache hit rate), or when the trigger address included in the access regeneration data is not accessed by the CPU 20 (i.e., triggered by a failure to track the trigger address).

[0125] Furthermore, the modification of the access playback data may be performed based on the prefetch timing. Specifically, for example, the timing of storing (refilling) the playback target data in the cache memory 12 and erasing (evicting) it from the cache memory 12 may be recorded (dumped). If the playback target data stored in the cache memory 12 is erased from the cache memory 12 before it is accessed (i.e., the prefetch timing is too early), the access playback data is modified to delay the prefetch timing. On the other hand, if the playback target data is stored in the cache memory 12 after it has been accessed (i.e., the prefetch timing is too late), the access playback data is modified to advance the prefetch timing. In other words, in this embodiment, the access playback data may be modified based on the measurement result of whether or not the prefetching is performed appropriately (i.e., whether or not the playback target data stored in the cache memory 12 is being used appropriately). The prefetch timing is adjusted, for example, by the number of logical addresses placed between the trigger address and the playback target logical address in the access pattern.

[0126] (Second Embodiment) Next, a second embodiment will be described. In this embodiment, detailed explanations of parts similar to those in the first embodiment described above will be omitted, and only parts that differ from the first embodiment will be described. Furthermore, since the configuration of the memory device according to this embodiment is the same as that of the first embodiment described above, Figure 1 will be used to explain it as appropriate.

[0127] In the first embodiment described above, it is assumed that all logical addresses A0 to A15 constituting the access pattern shown in Figure 4 have the same priority. However, this embodiment differs from the first embodiment in that different priorities are assigned to these logical addresses A0 to A15.

[0128] Here, with reference to Figure 9, an example of the priority assigned to the logical addresses constituting the access pattern in this embodiment will be described.

[0129] Here, we assume that the above address sequence is recorded three times, and that an access pattern (for example, a sequence of logical addresses accessed by CPU 20 when program A is executed) is extracted from each of these three recorded address sequences (hereinafter referred to as the 1st to 3rd address sequences). In this case, the access pattern extracted from the 1st address sequence is the logical address pattern A0, A1, A2, A3, A4, A5, A6; the access pattern extracted from the 2nd address sequence is the logical address pattern A2, A5, A6, A3, A4; and the access pattern extracted from the 3rd address sequence is the logical address pattern A2, A3, A5, A4, A6, A7.

[0130] In this embodiment, among such multiple access patterns, logical addresses that appear frequently (have a high frequency of occurrence) are assigned a high priority, and logical addresses that appear infrequently (have a low frequency of occurrence) are assigned a low priority.

[0131] In the example shown in Figure 9, logical addresses A2, A3, A4, A5, and A6, which appear in all access patterns, are assigned high priority, while the other logical addresses A0, A1, and A7 are assigned low priority.

[0132] Note that the priority levels described here are just examples. In this embodiment, a high priority should be assigned to logical addresses used to reliably read data that should be prefetched, and a lower priority should be assigned to logical addresses used to read data that should be prefetched if there is sufficient capacity.

[0133] In this case, the access history analysis unit 40 creates an address list including the trigger address and the replay target logical addresses to which priority has been assigned, and transmits the address list to the placement unit 132.

[0134] The operation of the memory device 10 according to this embodiment will be described below. Note that the access recording process is the same as in the first embodiment described above, so a detailed explanation of it will be omitted here. The data placement process and access playback process will be described here.

[0135] First, the data placement process will be explained with reference to Figure 10. Note that the access recording unit 131 included in the controller 13 is omitted in Figure 10.

[0136] The configuration unit 132 obtains the address list transmitted from the access history analysis unit 40 (step S31). It is assumed that each of the logical addresses to be regenerated included in the address list obtained in step S31 is assigned the priority described above.

[0137] Next, the placement unit 132 obtains multiple logical addresses to be regenerated from the address list acquired in step S31.

[0138] The placement unit 132, for example, via a controller that controls the NAND flash memory 11, acquires data (data to be recovered) from the NAND flash memory 11 based on each of the multiple logical addresses to be recovered obtained from the address list (step S32). The process in step S32 corresponds to the process in step S12 shown in Figure 6 above.

[0139] When the process in step S32 is executed, the placement unit 132, via a controller that controls the NAND flash memory 11, places the data to be regenerated acquired in step S32 into the same page (regenerated page) contained in the NAND flash memory 11 (step S33).

[0140] The process in step S33 is similar to the process in step S13 shown in Figure 6 above, in that it packs the data to be reproduced, which is distributed across multiple pages, into a single page. However, in step S33, for example, the data to be reproduced read based on the logical address with higher priority among the multiple logical addresses to be reproduced included in the address list associated with the trigger address is packed into a single page, while the data to be reproduced read based on the logical address with lower priority is packed into a different page. If the amount of data to be reproduced read based on the logical address with higher priority and the data to be reproduced read based on the logical address with lower priority can fit on the same page, they may be packed within that same page.

[0141] Next, the placement unit 132 generates access playback data that includes a trigger address included in the address list and a playback target physical address that includes a page number to identify the playback target page on which the playback target data is located. The access playback data generated by the placement unit 132 in this way is output to the access playback unit 133 (step S34).

[0142] Here, we will specifically explain the processes in steps S33 and S34 described above. Here, we assume that in step S31, the address list shown in Figure 5 is obtained, and that among the regenerative logical addresses "A8, A9, A10, A11" included in the address list and associated with the trigger address "A0", regenerative logical addresses A8 and A9 are assigned a high priority, and regenerative logical addresses A10 and A11 are assigned a low priority.

[0143] According to this, if the data to be regenerated read from the NAND flash memory 11 based on the regenerated logical addresses A8 and A9, which are assigned high priority in step S33, is placed on a single regenerated page, then in step S34, access regeneration data including the trigger address A0 and the regenerated physical address including the page number for identifying the regenerated page (i.e., access regeneration data generated from the regenerated logical address with high priority) is output to the access regeneration unit 133.

[0144] Furthermore, assuming that the data to be regenerated read from the NAND flash memory 11 based on the regenerated logical addresses A10 and A11, which are assigned low priority in step S33, is placed on a single regenerated page, then in step S34, access regeneration data including the trigger address A0 and the regenerated physical address including the page number for identifying the regenerated page (i.e., access regeneration data generated from the regenerated logical address with low priority) is output to the access regeneration unit 133.

[0145] Although this explanation focuses on trigger address A0 (and the replayable logical addresses A8-A11 included in the address list associated with trigger address A0), the same process is performed for other trigger addresses, including trigger address A4.

[0146] For convenience, in the following explanation, access recovery data generated from a logical address to be recovered with a higher priority, as described above, will be referred to as the first access recovery data, and access recovery data generated from a logical address to be recovered with a lower priority, will be referred to as the second access recovery data.

[0147] Next, the access regeneration process in this embodiment will be described with reference to the flowchart in Figure 11. The access regeneration process in this embodiment is generally the same as that of the first embodiment described above. However, in this access regeneration process, as described in the first embodiment described above, if it is determined that a trigger address included in the access regeneration data has been accessed by the CPU 20, the first access regeneration data including the trigger address is stored in a queue corresponding to a higher priority (hereinafter referred to as the first queue) 133a, and the second access regeneration data including the trigger address is stored in a queue corresponding to a lower priority (hereinafter referred to as the second queue) 133b. Although not described in the first embodiment, the access regeneration unit 133 may also use a queue for storing access regeneration data in the first embodiment.

[0148] In this case, the access playback unit 133 determines whether or not the first access playback data is stored in the first queue 133a described above (step S41).

[0149] If it is determined that the first access playback data is stored in the first queue 133a (YES in step S41), the access playback unit 133 retrieves the first access playback data from the first queue 133a and instructs prefetching using the first access playback data (step S42). The process in step S42 corresponds to the process in step S23 shown in Figure 8 above, so a detailed explanation is omitted here.

[0150] On the other hand, if it is determined that the first access playback data is not stored in the first queue 133a (NO in step S41), the access playback unit 133 refers to the second queue 133b and determines whether the second access playback data located at the beginning of the second queue 133b is old or not (step S43).

[0151] Furthermore, the second access playback data stored in the second queue 133b is assigned the date and time on which the second access playback data was stored in the second queue 133b, and the processing in step S43 described above is determined based on the time elapsed from the date and time assigned to the second access playback data located at the beginning of the second queue 133b to the current date and time.

[0152] If the second access playback data located at the beginning of the second queue 133b is determined to be old (YES in step S43), the access playback unit 133 discards the second access playback data (step S44).

[0153] On the other hand, if it is determined that the second access regeneration data located at the beginning of the second queue 133b is not old (NO in step S43), the access regeneration unit 133 determines whether the number of reads (Outstanding requests) to the NAND flash memory 11 is below a threshold (step S45). Note that the current number of reads to the NAND flash memory 11 is counted within the memory device 10, and the access regeneration unit 133 is able to grasp the number of reads to the NAND flash memory 11.

[0154] If it is determined that the number of reads to the NAND flash memory 11 is less than a threshold (YES in step S45), the access regeneration unit 133 retrieves the second access regeneration data (access regeneration data including the trigger address accessed by the CPU 20) located at the beginning of the second queue 133b and instructs prefetching using the second access regeneration data (step S46). The process in step S46 corresponds to the process in step S23 shown in Figure 8 above, so a detailed explanation is omitted here.

[0155] On the other hand, if it is determined that the number of reads to the NAND flash memory 11 is not below a threshold (NO in step S45), the process shown in Figure 11 is terminated.

[0156] The process shown in Figure 11 above is repeatedly executed when access playback data is stored in the first queue 133a and the second queue 133b.

[0157] In the example shown in Figure 11, prefetching is instructed using second access retrieval data when the number of reads to the NAND flash memory 11 is below a threshold. However, the conditions for instructing prefetching using the second access retrieval data may be other than the number of reads to the NAND flash memory 11 being below a threshold. Furthermore, in this embodiment, any configuration that prioritizes referencing the first access retrieval data over the second access retrieval data for prefetching is acceptable.

[0158] Furthermore, although this explanation assumes that the first and second access playback data are stored in the first queue 133a and the second queue 133b, the first and second access playback data may be managed in a different data structure.

[0159] As described above, in this embodiment, the data to be replayed, which is read based on a higher priority logical address to be replayed (the fifth address), is placed in one page to be replayed, and first access replay data is generated, which includes a trigger address and a physical address to be replayed that includes a page number for identifying the page to be replayed. The data to be replayed, which is read based on a lower priority logical address to be replayed (the sixth address), is placed in another page to be replayed, and second access replay data is generated, which includes a trigger address and a physical address to be replayed that includes a page number for identifying the page to be replayed. Furthermore, in this embodiment, in order to store the data to be replayed in the cache memory 12 (i.e., prefetch), the first access replay data is referenced with higher priority than the second access replay data (i.e., prefetching using the first access replay data is prioritized over prefetching using the second access replay data).

[0160] Here, assuming that the first embodiment described above is configured to prefetch all data read based on high-priority and low-priority logical addresses to be replayed, then even data read based on infrequently occurring (i.e., low-priority) logical addresses to be replayed will be stored in the cache memory 12, increasing the processing load related to the prefetch and the amount of data stored in the cache memory 12.

[0161] On the other hand, if the first embodiment described above is configured to prefetch only data read based on a high-priority retrievable logical address, then when a retrievable logical address with a low occurrence count (i.e., low priority) is accessed by the CPU 20, it becomes necessary to read data from the NAND flash memory 11 based on that retrievable logical address, and the cache memory 12 does not contribute to concealing latency.

[0162] In contrast, in this embodiment, as described above, data read based on a high-priority logical address to be retrieved is preferentially prefetched, while data read based on a low-priority logical address to be retrieved is prefetched according to the status of the memory device 10, such as the number of reads to the NAND flash memory 11. Therefore, it is considered that the read performance of the memory device 10 can be efficiently improved (latency is hidden) by taking this priority into consideration.

[0163] In this embodiment, the priority of the logical address to be retrieved is described as being determined based on the number of occurrences (frequency of occurrence) in the address sequence (access pattern extracted therefrom) that has been recorded multiple times. However, this priority may be determined based on other considerations.

[0164] By the way, depending on the program executed in the memory system 30, the access pattern may change, for example, due to conditional branching.

[0165] Here, Figure 12 shows an example where the access pattern changes due to the conditional branching described above. Specifically, the example shown in Figure 12 shows access pattern 201 extracted from the address sequence recorded during the first execution of the program and access pattern 202 extracted from the address sequence recorded during the second execution of the program. Note that access patterns 201 and 202 assume that, for example, after data is read based on logical addresses A0 to A7, the data may be read based on logical addresses A8 to A15 or based on logical addresses A8' to A15' due to conditional branching.

[0166] Here, we assume that access pattern 201 is extracted from the address sequence recorded during the first execution of the program, access pattern 202 is extracted from the address sequence recorded during the second execution of the program, and access pattern 201 is extracted again from the address sequence recorded during the third execution of the program, and that the priority of each logical address (recoverable logical address) is determined based on the number of occurrences in such access patterns. In this case, the pattern in which recoverable logical addresses A8 to A15 are accessed is more frequent during conditional branching, and the pattern in which recoverable logical addresses A8' to A15' are accessed is less frequent. Therefore, recoverable logical addresses A8 to A15 will be assigned a high priority, and recoverable logical addresses A8' to A15' will be assigned a low priority.

[0167] In this case, when trigger addresses "A0" and "A4" are accessed, the logical addresses A8 to A15 to be retrieved will be prefetched with higher priority, and the logical addresses A8' to A15' to be retrieved will be prefetched with lower priority.

[0168] Here, for example, if the trigger address A8' is accessed, the replayable logical addresses A16'~A19' are prefetched. However, even if the program is executed multiple times, the overall frequency of the pattern in which the replayable logical addresses A16'~A19' are accessed is low. Nevertheless, it is assumed that after the trigger address A8' is accessed, the replayable logical addresses A16'~A19' will definitely be accessed. In such cases, if the trigger address A8' is accessed, the replayable logical addresses A16'~A19' may be prefetched with a higher priority.

[0169] In other words, in this embodiment, the priority may be determined by considering the conditional branching described above.

[0170] (Third embodiment) Next, a third embodiment will be described. In this embodiment, a detailed explanation of the parts that are the same as those of the first embodiment described above will be omitted, and only the parts that differ from the first embodiment will be described.

[0171] Figure 13 is a block diagram showing an example of the configuration of the memory device 10 according to this embodiment. In Figure 13, the same reference numerals are used for parts that are the same as those in Figure 1, and their detailed explanations are omitted. Here, we will describe the parts that differ from those in Figure 1.

[0172] As shown in Figure 13, the memory device 10 according to this embodiment differs from the first embodiment described above in that the controller 13 further includes an access and playback data storage unit 134.

[0173] The access playback data storage unit 134 stores the access playback data generated by the placement unit 132. The access playback data storage unit 134 is implemented by, for example, memory provided in a memory device 10 other than the NAND flash memory 11 and cache memory 12.

[0174] In this embodiment, the access playback unit 133 obtains access playback data from the access playback data storage unit 134 to be referenced in order to store the playback target data in the cache memory 12 (i.e., prefetch it).

[0175] The following describes the general operation of the memory device 10 in this embodiment. Figure 14 shows an example of access recovery data generated by the placement unit 132. Figure 14 assumes that the placement unit 132 generates multiple access recovery data, including access recovery data 132a to 132f. Access recovery data 132a to 132f are access recovery data generated for each trigger address A0, A4, A8, A12, A16, and A20 included in the address list output from the access history analysis unit 40 (i.e., multiple access recovery data corresponding to each of the multiple trigger addresses). Note that the access recovery data 132a to 132f shown in Figure 14 are the same as the access recovery data 132a and 132b described in Figure 7 above, so a detailed explanation is omitted here.

[0176] Here, in order to prefetch the data to be replayed, it is necessary to monitor the logical addresses sent from the CPU 20 to the memory device 10 by referring to the access replay data. For example, when the access replay unit 133 refers to the access replay data 132a to 132f shown in Figure 14 above, the access replay unit 133 must execute a process (hereinafter referred to as the address matching process) to determine whether the logical address sent from the CPU 20 to the memory device 10 is a trigger address included in each of the access replay data 132a to 132f each time a logical address is sent (hereinafter referred to as the address matching process).

[0177] Here, we have explained the access regeneration data 132a to 132f, but in reality, it is necessary to refer to more access regeneration data, which increases the scale of the hardware (circuitry) required to execute the address matching determination process described above at high speed.

[0178] Therefore, in this embodiment, the hardware size (hardware resources) described above is reduced by limiting the number of access playback data that are referenced in order to prefetch the playback target data from among the multiple access playback data generated by the arrangement unit 132.

[0179] The operation of the memory device 10 according to this embodiment will be described below. Note that the access recording process is the same as in the first embodiment described above, so a detailed explanation will be omitted here. Also, the data placement process is the same as in the first embodiment described above, except that the output destination of the access playback data generated by the placement unit 132 is the access playback data storage unit 134 instead of the access playback unit 133, so a detailed explanation will be omitted here.

[0180] The access playback process in this embodiment is generally the same as that of the first embodiment described above, but differs in that the access playback data described above is obtained from the access playback data storage unit 134.

[0181] The details of the access playback process will be explained with reference to the flowchart in Figure 15. Here, it is assumed that multiple access playback data, such as the access playback data 132a to 132f shown in Figure 14 above, are stored in the access playback data storage unit 134.

[0182] First, the access playback unit 133 acquires a predetermined number of access playback data from the access playback data storage unit 134 (step S51).

[0183] As mentioned above, the multiple access playback data stored in the access playback data storage unit 134 are generated for each trigger address included in the address list. In step S51, a predetermined number of access playback data are acquired in order of the earliest appearance (i.e., arrangement) of the trigger address in the access pattern extracted from the aforementioned address sequence.

[0184] Specifically, assuming that the trigger addresses in the access pattern appear in the order A0, A4, A8, A12, A16, A20, and the number of access playback data obtained from the access playback data storage unit 134 is 4, the access playback unit 133 obtains access playback data 132a to 132d from the multiple access playback data 132a to 132f shown in Figure 14.

[0185] When the process in step S51 is executed, the access regeneration unit 133 sets the trigger addresses A0, A4, A8, and A12, which are included in each of the access regeneration data 132a to 132d acquired in step S51, as the trigger addresses to be monitored.

[0186] Next, the access regeneration unit 133 determines whether the logical address sent from the CPU 20 to the memory device 10 is the trigger address to be monitored as described above (step S52).

[0187] If it is determined that the target trigger address is not one to be monitored (NO in step S52), the system waits until the next logical address is sent from the CPU 20, and the process in step S52 is repeated.

[0188] On the other hand, if it is determined that the trigger address is one to be monitored (YES in step S52), the access regeneration unit 133 instructs prefetching using the access regeneration data that includes the trigger address (step S53). Note that the processing in step S53 corresponds to the processing in step S23 shown in Figure 8 above, so a detailed explanation is omitted here.

[0189] When the process in step S53 is executed, the access playback unit 133 updates the prefetch position (details will be described later) and obtains the next access playback data from the access playback data storage unit 134 (step S54).

[0190] Next, the access regeneration unit 133 resets (updates) the trigger address to be monitored based on the access regeneration data acquired in step S54 (step S55).

[0191] Specifically, as described above, in step S51, access regeneration data 132a to 132d are acquired, and in step S53, if prefetching is instructed using access regeneration data 132a, in step S54, the prefetch position is updated to trigger address A0, and access regeneration data 132e is acquired from the access regeneration data storage unit 134 as access regeneration data containing the next trigger address to be monitored. In this case, in step S55, trigger addresses A4, A8, A12, and A16 included in access regeneration data 132b to 132e are reset as trigger addresses to be monitored. Note that trigger address A0 included in access regeneration data 132a, which was used to instruct prefetching in step S53, is excluded from the trigger addresses to be monitored.

[0192] Note that in Figure 15, for convenience, it is shown that the access regeneration process ends when the process in step S55 is executed, but after the process in step S55 is executed, the processes from step S52 onwards are repeated.

[0193] Specifically, in step S53, which is repeated in this manner, if, for example, prefetching is instructed using access regeneration data 132b (i.e., trigger address A4 is sent from CPU 20), then in step S54, the prefetch position is updated to trigger address A4, and access regeneration data 132f is further acquired from access regeneration data storage unit 134. In this case, in step S55, trigger addresses A8, A12, A16, and A20 contained in access regeneration data 132c to 132f are reset as trigger addresses to be monitored. Note that trigger address A4 contained in access regeneration data 132b, which was used to instruct prefetching in step S53, is excluded from the trigger addresses to be monitored.

[0194] In other words, in this embodiment, the access regeneration data referenced is replaced so that the number of trigger addresses to be monitored is always below a certain number (for example, four).

[0195] As described above, in this embodiment, multiple access replay data are generated corresponding to each of the multiple trigger addresses included in the address list, and these multiple access replay data are stored in the access replay data storage unit 134. In this embodiment, in order to store the data to be replayed in the cache memory 12 (i.e., prefetch), a predetermined number of access replay data are referenced from the multiple access replay data stored in the access replay data storage unit 134 (i.e., the trigger addresses included in the predetermined number of access replay data are monitored).

[0196] In this embodiment, this configuration eliminates the need to monitor all trigger addresses contained in each of the multiple access replay data generated by the placement unit 132 (i.e., to refer to all of the multiple access replay data), thus reducing the hardware size required to implement prefetching in this embodiment. In other words, this embodiment achieves both improved read performance and reduced hardware size.

[0197] Although a detailed explanation will be omitted here, the configuration relating to priority described in the second embodiment described above may be further applied to the configuration described in this embodiment.

[0198] (Fourth Embodiment) Next, a fourth embodiment will be described. In this embodiment, detailed explanations of parts similar to those in the first and third embodiments described above will be omitted, and only parts that differ from the first and third embodiments will be described.

[0199] Figure 16 is a block diagram showing an example of the configuration of the memory device 10 according to this embodiment. In Figure 16, the same reference numerals are used for parts that are the same as those in Figures 1 and 13 described above, and their detailed explanations are omitted. Here, we will describe the parts that differ from those in Figures 1 and 13.

[0200] As shown in Figure 16, the memory device 10 according to this embodiment differs from the first and third embodiments described above in that the access regeneration unit 133 included in the controller 13 includes a detection unit 133c and a monitoring unit 133d.

[0201] The detection unit 133c detects the start of execution of a specific program based on the trigger address accessed by the CPU 20.

[0202] The monitoring unit 133d refers to the access playback data generated for the program whose execution has been detected by the detection unit 133c in order to store the playback target data in the cache memory 12 (i.e., prefetch it).

[0203] The operation of the memory device 10 according to this embodiment will be described below. Note that the access recording process is the same as in the first embodiment described above, so a detailed explanation of it will be omitted here.

[0204] First, the data placement process in this embodiment will be briefly explained. In the first and third embodiments described above, the case in which an address list is created from a sequence of logical addresses (access pattern) accessed by the CPU 20 when a single program (for example, program A) is executed was mainly explained. However, in this embodiment, the access history analysis unit 40 creates an address list for each of the multiple programs executed in the memory system 30 (that is, it creates an address list for each program). That is, Figure 5 described above shows the address list created for program A, but address lists are similarly created for other programs such as programs B and C in addition to program A. The multiple address lists created for each program by the access history analysis unit 40 in this way are transmitted to the placement unit 132.

[0205] The configuration unit 132 generates access replay data based on multiple address lists transmitted from the access history analysis unit 40. In the first and third embodiments described above, multiple access replay data corresponding to each of the multiple trigger addresses included in one address list were generated from that address list. However, in this embodiment, multiple access replay data are generated for each of the multiple address lists (i.e., for each address list).

[0206] In this embodiment, as described above, multiple access playback data generated for each address list by the arrangement unit 132 are stored in the access playback data storage unit 134.

[0207] Next, the access regeneration process in this embodiment will be described. Here, a large number of programs are executed in the memory system 30, and assuming that the number of such programs is 1024, the access regeneration data storage unit 134 stores multiple access regeneration data generated from each of the address lists of the 1024 programs. In this case, as described in the third embodiment above, if the access regeneration unit 133 refers to four access regeneration data for one program executed in the memory system 30 (that is, it monitors the trigger addresses included in the four access regeneration data), then the access regeneration unit 133 needs to execute 1024 × 4 address matching determination processes (processes that determine whether the logical address and the trigger address match) each time a logical address is transmitted from the CPU 20 to the memory device 10 (the logical address is accessed by the CPU 20), which increases the hardware size.

[0208] In contrast, in this embodiment, the detection unit 133c included in the access regeneration unit 133 refers to one access regeneration data for each program from among the multiple access regeneration data stored in the access regeneration data storage unit 134. The one access regeneration data referred to for each program by the detection unit 133c is the access regeneration data that contains the trigger address that appears first in the access pattern of the program, from among the multiple access regeneration data generated from the address list of the program. The number of access regeneration data referred to for each program by the detection unit 133c does not have to be one; a small number is sufficient.

[0209] Here, we assume that the trigger address included in the access regeneration data generated from the address list of a specific program (hereinafter referred to as the target program) among the access regeneration data referenced for each program as described above matches the logical address sent from the CPU 20 to the memory device 10. In this case, the detection unit 133c detects the start of execution of the target program.

[0210] Next, the monitoring unit 133d obtains from the access playback data storage unit 134 multiple access playback data (multiple access playback data corresponding to each of the multiple trigger addresses included in the address list) generated from the address list of the target program whose execution start has been detected by the detection unit 133c. In addition, the monitoring unit 133d may obtain a predetermined number (for example, four) of the multiple access playback data generated from the address list of the target program, similar to the third embodiment described above.

[0211] The monitoring unit 133d can then perform the same processing as the access regeneration process described in the third embodiment above.

[0212] As described above, in this embodiment, an address list is obtained for each program executed in the memory system 30, and for each address list, multiple access replay data (i.e., access replay data for each program) corresponding to each of the multiple trigger addresses included in the address list are generated. Furthermore, in this embodiment, when a trigger address is accessed by the CPU 20, the start of execution of the target program (a specific program) is detected based on that trigger address, and in order to store the data to be replayed in the cache memory 12 (i.e., prefetch), multiple access replay data corresponding to each of the multiple trigger addresses included in the address list of the target program whose execution start was detected are referenced (i.e., the trigger addresses included in the multiple access replay data are monitored). In other words, in this embodiment, the access replay data referenced to store the data to be replayed in the cache memory 12 is replaced based on the detection result of the start of execution of a specific program.

[0213] Here, if an address list is created for each program as described above, the configuration of the third embodiment described above requires hardware capable of executing 1024 x 4 address matching checks each time a logical address is accessed by the CPU 20. However, according to this embodiment, the detection unit 133c executes 1024 x 1 address matching check, and the monitoring unit 133d only needs to execute the same number of address matching checks as the number of access playback data (for example, 4) obtained from the access playback data storage unit 134 based on the target program, thus reducing the hardware size. In other words, this embodiment improves read performance and further reduces the hardware size compared to the third embodiment described above.

[0214] Although a detailed explanation will be omitted here, the configuration relating to priority described in the second embodiment described above may be further applied to the configuration described in this embodiment.

[0215] According to at least one embodiment described above, it is possible to provide a memory device and a memory system capable of improving read performance.

[0216] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0217] 10...Memory device, 11...NAND flash memory (non-volatile memory), 12...Cache memory, 13...Controller, 20...CPU, 30...Memory system, 40...Access history analysis unit, 131...Access recording unit, 132...Placement unit, 133...Access playback unit, 133a...First queue, 133b...Second queue, 133c...Detection unit, 133d...Monitoring unit, 134...Access playback data storage unit.

Claims

1. Controller and Non-volatile memory and Cache memory and It is equipped with, The aforementioned controller, A plurality of first addresses that are accessed sequentially in order to read the data stored in the non-volatile memory are recorded. Obtain an address list that includes the second address from the plurality of recorded first addresses and the third address from the plurality of first addresses that is presumed to be accessed after the second address has been accessed. When a second address included in the address list is accessed, data is read from the non-volatile memory based on a third address included in the address list. The data read out is stored in the cache memory, The aforementioned non-volatile memory includes multiple pages, which are units of data read operations. If two or more data items among the data to be read based on the third address included in the address list are located on one of the multiple pages, the controller reads the two or more data items from the page in a single read operation and stores them in the cache memory. Memory device.

2. A controller and Non-volatile memory and Cache memory and It is equipped with, The aforementioned controller, A plurality of first addresses that are accessed sequentially in order to read the data stored in the non-volatile memory are recorded. Obtain an address list that includes the second address from the plurality of recorded first addresses and the third address from the plurality of first addresses that is presumed to be accessed after the second address has been accessed. When a second address included in the address list is accessed, data is read from the non-volatile memory based on a third address included in the address list. The data read out is stored in the cache memory, The aforementioned non-volatile memory includes multiple pages, which are units of data read operations. The aforementioned address list includes multiple third addresses, The controller places the data to be read based on each of the plurality of third addresses into the same page in the non-volatile memory before the second address included in the address list is accessed. Memory device.

3. The aforementioned controller, If the data read based on each of the plurality of third addresses is located within the same page contained in the non-volatile memory, access and playback data is generated including the second address and a fourth address including a page number for identifying the page. When the second address included in the access regeneration data is accessed, data is read from the non-volatile memory based on the fourth address included in the access regeneration data. The memory device according to claim 2.

4. The aforementioned plurality of third addresses include a fifth address with higher priority and a sixth address with lower priority. The aforementioned controller, The data read based on the fifth address is placed in the first page contained in the non-volatile memory, and first access replay data is generated including the second address and a fourth address including a page number for identifying the first page. The data read based on the sixth address is placed in a second page different from the first page contained in the non-volatile memory, and second access playback data is generated, which includes the second address and a fourth address including a page number for identifying the second page. In order to store the aforementioned data in the cache memory, the first access playback data is referenced with priority over the second access playback data. The memory device according to claim 3.

5. The controller records the plurality of first addresses multiple times, The fifth and sixth addresses are determined based on the number of occurrences in the multiple first addresses that have been recorded multiple times. The memory device according to claim 4.

6. The controller obtains an address list that includes a plurality of second addresses and a plurality of third addresses that are presumed to be accessed after each of the plurality of second addresses has been accessed. Multiple access regeneration data are generated corresponding to each of the multiple second addresses included in the aforementioned address list. When the second address is accessed, the access regeneration data referenced to store the data in the cache memory is replaced with access regeneration data corresponding to another second address. The memory device according to claim 3.

7. Connected to a processor configured to run multiple programs, The aforementioned controller, The access playback data for each program is generated, When the second address is accessed, the start of execution of a specific program is detected based on the second address. Based on the detection results, the access replay data referenced to store the data in the cache memory is replaced. The memory device according to claim 3.

8. A controller and Non-volatile memory and Cache memory and It is equipped with, The aforementioned controller, A plurality of first addresses that are accessed sequentially in order to read the data stored in the non-volatile memory are recorded. Obtain an address list that includes the second address from the plurality of recorded first addresses and the third address from the plurality of first addresses that is presumed to be accessed after the second address has been accessed. When a second address included in the address list is accessed, data is read from the non-volatile memory based on a third address included in the address list. The data read out is stored in the cache memory, Of the data read based on the second and third addresses included in the address list, data that is not stored in the cache memory when the second address is accessed is pre-placed in a storage area capable of reading data at a faster speed than the non-volatile memory. Memory device.

9. Memory devices and, A processor connected to the aforementioned memory device and It is equipped with, The memory device comprises a controller, non-volatile memory, and cache memory. The aforementioned controller, A plurality of first addresses that are accessed sequentially in order to read the data stored in the non-volatile memory are recorded. Obtain an address list that includes the second address from the plurality of recorded first addresses and the third address from the plurality of first addresses that is presumed to be accessed after the second address has been accessed. When a second address included in the address list is accessed, data is read from the non-volatile memory based on a third address included in the address list. The data read out is stored in the cache memory, The processor creates the address list based on the recorded plurality of first addresses, The aforementioned non-volatile memory includes multiple pages, which are units of data read operations. If two or more data items among the data to be read based on the third address included in the address list are located on one of the multiple pages, the controller reads the two or more data items from the page in a single read operation and stores them in the cache memory. Memory system.

10. A memory device and A processor connected to the aforementioned memory device and It is equipped with, The memory device comprises a controller, non-volatile memory, and cache memory. The aforementioned controller, A plurality of first addresses that are accessed sequentially in order to read the data stored in the non-volatile memory are recorded. Obtain an address list that includes the second address from the plurality of recorded first addresses and the third address from the plurality of first addresses that is presumed to be accessed after the second address has been accessed. When a second address included in the address list is accessed, data is read from the non-volatile memory based on a third address included in the address list. The data read out is stored in the cache memory, The processor creates the address list based on the recorded plurality of first addresses, The aforementioned non-volatile memory includes multiple pages, which are units of data read operations. The aforementioned address list includes multiple third addresses, The controller places the data to be read based on each of the plurality of third addresses into the same page in the non-volatile memory before the second address included in the address list is accessed. Memory system.

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