System and method for post-detection synthesis of multiple downlink signals representing communication signals

Abstract

Provided herein are embodiments of systems and methods for combining downlink signals representing communication signals. An exemplary method includes receiving samples of the downlink signals from multiple antenna feeds, generating a first symbol for the first signal and a second symbol for the second signal based on performing a timing recovery operation on the first signal and the second signal, respectively, generating offset information based on performing a correlator operation on the first symbol and the second symbol, and combining the first signal and the second signal based on performing a weighted combiner operation. At least one of the first timing recovery operation, the second timing recovery operation, the correlator operation, and the combining are performed in multiple processing blocks in one or more processors, and the first processing block and the second processing block operate in parallel.

Description

Technical Field

[0001] This disclosure relates to signal processing. More specifically, this disclosure relates to implementing distributed computing using a general-purpose processor to achieve high-speed processing.

Background Art

[0002] Description of Related Art In some examples, satellite communication signals may require large terrestrial stations and other facilities to transmit and / or receive data locally and process it. This may include a large antenna array for receiving data from the associated satellite and processing the received data for use, an associated radio frequency terminal (RFT), and critical electronic devices (such as modems, signal processors, etc.).

Summary of the Invention

[0003] This disclosure provides an improved communication system. The following summary is not intended to define all aspects of the present invention, and other features and advantages of this disclosure will become apparent from the following detailed description, which includes the drawings. This disclosure is intended to be associated as an integrated document, and it should be understood that all combinations of the features described herein are envisioned, even if the combinations of features are not found together in the same sentence or paragraph or section of this disclosure. Further, this disclosure includes, as additional aspects, all embodiments of the present invention that are narrower in scope in some respect than the variations specifically mentioned herein.

[0004] As disclosed herein, digital signal processing (DSP) can be performed in many different ways using a general-purpose processor or a central processing unit (CPU). Examples of techniques executed on a general-purpose processor to achieve high-speed processing capable of performing the disclosed functions include parallel processing with multiple CPUs and multiple cores of each CPU, and adopting single instruction multiple data (SIMD) technology, and Performing a feedforward operation to interrupt the feedback loop, Pre-calculating metadata (or state information) to distribute heavy processing across several CPUs, Combining multiple functions into a single function in a way that improves CPU performance or reduces memory bandwidth usage, This includes, but is not limited to, the following:

[0005] One way to improve the throughput of a general-purpose CPU is to utilize as many cores as possible present on the CPU. While careful attention must be paid to ensuring that data is properly shared among several cores within the CPU, this allows for increased processing throughput by adding more CPU cores. It is also possible to use several CPUs on the same system, with each CPU containing multiple cores. All embodiments of this disclosure take advantage of the benefits of using multiple cores within a CPU, and some embodiments also take advantage of having multiple CPUs per system and / or per group of systems within a server environment.

[0006] Another way to achieve high processing speeds is to utilize the Single Instruction Multiple Data (SIMD) capabilities of general-purpose CPUs. This allows a single CPU core to perform up to 16 floating-point operations in a single instruction, similar to AVX512 SIMD operations. One example of employing SIMD is using a finite impulse response (FIR) filter function that computes 16 floating-point results simultaneously. Another example is multiplying complex numbers. AVX512 allows computing eight pairs of quadrature signals (IQ data) simultaneously instead of one pair. Complex multiplication is used in virtually all processing algorithms described in this disclosure.

[0007] Some processing systems implement various forms of feedback, often including phase-locked loops (PLLs) or delay-locked loops (DLLs). However, as with PLLs and DLLs, feedback can generally be problematic because the very nature of feedback itself can cause bottlenecks. Feedback loops force all incoming data to be processed in a single (e.g., linear) process that cannot be easily or otherwise divided. In addition to feedback, there are other obstacles to overcome using PLLs and DLLs, including the frequency with which error terms are calculated. Feedback loops can be replaced with feedforward loops. In a feedforward loop, the error state is processed on a data block, and then the calculated error term is fedforward to another block to which this error term is applied. With appropriate redundancy, the calculation of errors and the application of the term can be divided among several CPU cores to further improve throughput. An example of this is a diversity combiner where timing and phase corrections are calculated in one block, timing adjustments are applied in another block, and phase corrections are applied in yet another block. This method can be parallelized across several CPU cores as a set to further improve throughput.

[0008] In addition to a feedforward approach to processing data, it can also be beneficial to perform metadata pre-computation in a single block and then distribute the data processing across several CPU cores. This method is similar to the feedforward method already described, but in this case, it does not interrupt loops (such as feedback loops), but simply leverages more CPU cores to increase the amount of data that can be processed. Thus, the block performing the pre-computation does not perform CPU-intensive processing, but rather computes the necessary steps such as the iterations within the for loop and the starting exponent and the slope point between the interpolated phase values. One such example is Doppler compensation performed in a diversity combiner. The necessary phase adjustment is created in the first block, but the CPU-intensive calculations for performing the phase adjustment are handed off to subsequent downstream blocks. If the second part of the processing is the CPU-intensive part, this allows for the use of any number of CPU cores, resulting in increased processing speed that would not otherwise be achievable within a single block.

[0009] Another technique that can be employed in general-purpose CPUs to achieve high throughput is the way the function set is used and the type of memory used. In some cases, memory bandwidth can be a performance limiting factor. In this case, the goal is to limit the amount of data that needs to be transferred to and from random access memory (RAM) (not faster memory like the CPU cache). To do this, functions need to be folded so that they are all executed together rather than individually, with the aim of minimizing access to the slower RAM compared to accessing the faster CPU cache. Another way to reduce memory bandwidth is to utilize properly spaced memory types, for example, by using int8 instead of float or double whenever possible.

[0010] In one embodiment, a method for combining a plurality of downlink signals representing a communication signal is provided herein. The method includes receiving samples of a plurality of downlink signals from a plurality of antenna feeds; generating a first symbol for a first signal based on a first timing recovery operation on a first sample of a first signal of the plurality of downlink signals; generating a second symbol for a second signal based on a second timing recovery operation on a second sample of a second signal of the plurality of downlink signals; generating time and phase offset information based on a correlator operation on the first and second symbols; and combining a first and second signal based on (i) the first and second symbols, (ii) aligning the timing and phase of the first symbol with the second symbol based on the time and phase offset information, and (iii) performing a weighted combiner operation that applies scaling to the first and second data packets, respectively, based on the corresponding signal quality. At least one of the first timing recovery operation, the second timing recovery operation, the correlator operation, and the combining is performed in a plurality of processing blocks in one or more processors, the first and second processing blocks operating in parallel.

[0011] In another embodiment, a system is provided for synthesizing multiple downlink signals representing communication signals. This system includes multiple antennas configured to receive multiple downlink signals, and one or more processors communically coupled to the multiple antennas, each having multiple processing blocks. The one or more processors are operable to perform the method described above.

[0012] In another embodiment, an apparatus is provided for combining a plurality of downlink signals representing a communication signal. The apparatus includes means for receiving samples of a plurality of downlink signals from a plurality of antenna feeds; means for generating a first symbol for the first signal based on performing a first timing recovery operation on a first sample of the first signal of the plurality of downlink signals; means for generating a second symbol for the second signal based on performing a second timing recovery operation on a second sample of the second signal of the plurality of downlink signals; means for generating time and phase offset information based on performing correlator operations on the first and second symbols; and means for combining the first and second signals based on (i) the first and second symbols, (ii) aligning the timing and phase of the first symbol with the second symbol based on the time and phase offset information, and (iii) performing a weighted combiner operation that applies scaling to the first and second data packets, respectively, based on the corresponding signal quality. At least one of the means for generating the first symbol, the means for generating the second symbol, the means for generating the time and phase offset information, and the means for combining is performed in a plurality of processing blocks in one or more processors, the first processing block and the second processing block operating in parallel.

[0013] Details of the present invention, both in terms of their structure and operation, can be partially derived by examining the accompanying drawings, in which similar reference numerals refer to similar parts. [Brief explanation of the drawing]

[0014] [Figure 1] This is a graphical representation of an example of a communication system according to embodiments disclosed herein. [Figure 2] This is a functional block diagram of wired or wireless communication devices for use as one or more components of the system shown in Figure 1. [Figure 3]This is a graphical representation of an example of feedforward or pre-calculated signal processing according to embodiments disclosed herein. [Figure 4] This is a graphical representation of another example of feedforward or pre-calculated signal processing shown in Figure 3, according to embodiments disclosed herein. [Figure 5] This is a functional block diagram of an example of a digital signal diversity combiner according to embodiments disclosed herein. [Figure 6] This is a functional block diagram of another example of a digital signal diversity combiner according to embodiments disclosed herein. [Figure 7] This is a functional block diagram of an example of a timing and carrier recovery method according to embodiments disclosed herein. [Figure 8] This is a functional block diagram of another example of a timing and carrier recovery method according to embodiments disclosed herein. [Figure 9] This is a functional block diagram of an example of a channel simulator according to embodiments disclosed herein. [Figure 10] This is a functional block diagram of an example of a signal modulator according to embodiments disclosed herein. [Modes for carrying out the invention]

[0015] Embodiments of an improved communication system that uses a general-purpose processor to achieve high-speed processing are disclosed. The embodiments disclosed herein provide an improved communication system that can efficiently achieve high-speed signal processing using a general-purpose processor. After reading this description, it will be apparent to those skilled in the art how the invention can be implemented in various alternative embodiments and alternative applications. However, while various embodiments of the invention are described herein, it is understood that these embodiments are presented by way of example and illustration only, and not by way of limitation. Thus, this detailed description of the various embodiments should not be construed as limiting the scope or breadth of the invention, as set forth in the appended claims.

[0016] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in relation to that embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0017] Although a communication system is used as a main example throughout the description, the application of the disclosed method is not limited thereto. For example, any wireless or wireline communication system that requires the use of digital signal processing, modems, etc. can implement the systems, methods, and computer-readable media described herein.

[0018] This disclosure provides systems and methods for performing digital signal processing using a general-purpose central processing unit (CPU) in either a standard server environment or a virtual cloud environment. In some examples, the systems can employ Single Instruction Multiple Data (SIMD) techniques to achieve high throughput, including instruction sets such as SSE, SSE2, SSE3, SSE4.1, SSE4.2, AVX, AVX2, and AVX512. This disclosure describes how data processing is managed across multiple processing cores of a processor (such as a CPU) to achieve the required throughput without using dedicated signal processing hardware such as field-programmable gate arrays (FPGAs) or high-performance computing (HPC) hardware such as graphics processing units (GPUs). Since this processing can be performed on general-purpose server CPUs, including but not limited to ARM processors such as Cortex-A76, NEON, and AWS Graviton and Graviton2, in addition to x86 architectures from Intel and AMD microprocessors, these functions can be deployed within a general-purpose cloud processing environment using a virtualized processing architecture without requiring dedicated hardware. Processing on a general-purpose CPU is made possible by a digital IF appliance that samples the analog signal and supplies the digitized sample to the CPU via an Ethernet connection. The digital IF appliance can also accept the digitized sample and convert it back to an analog signal, as described in U.S. Patent No. 9,577,936, entitled “Packetized Radio Frequency Transport System,” issued on February 21, 2017, the details of which are incorporated by reference.

[0019] FIG. 1 is a graphical representation of an embodiment of a communication system. The communication system (system) 100 can have a platform 110 and a satellite 111 that communicate with a plurality of ground stations. The platform 110 can be an aircraft (e.g., an airplane, helicopter, or unmanned aerial vehicle (UAV), missile, boat, etc.). The plurality of ground stations 120, 130, 140 can be associated with a ground radio frequency (RF) antenna 122 or one or more satellite antennas 132, 142. The ground station 120 can have an antenna 122 coupled to a digitizer 124. The digitizer 124 can have one or more analog-to-digital (A2D) converters for converting an analog signal received by the antenna 122 into a digital bit stream for transmission over a network. The digitizer 124 can also include a corresponding digital-to-analog (D2A) converter for operation on the uplink to the platform 110 and the satellite 111.

[0020] Similarly, the ground station 130 can have an antenna 132 and a digitizer 134, and the ground station 140 can have an antenna 142 and a digitizer 144.

[0021] The ground stations 120, 130, 140 can each receive, in the receive chain, a downlink signal 160 (labeled 160a, 160b, 160c) from the platform 110 and a downlink signal 170 (labeled 170a, 170b, 170c) from the satellite 111. The ground stations 120, 130, 140 can also each transmit an uplink signal via the antennas 122, 132, 142 in the transmit chain. The digitizers 124, 134, 144 can digitize the received downlink signals 160, 170 as a digital bit stream 154 for transmission. The digital bit stream 154 can then be transmitted to a cloud processing system via the network 152.

[0022] In some examples, ground stations 120, 130, and 140 can process all data (e.g., included in the downlink signal) locally, but this can be very expensive in terms of time, resources, and efficiency. Therefore, in some embodiments, the downlink signal can be digitized and transmitted as a digital bitstream 152 to a remote signal processing server (SPS) 150. In some implementations, the SPS 150 can be located in a physical location, such as a data center located in an off-site facility accessible via a wide area network (WAN). Such a WAN can be, for example, the internet. The SPS 150 can demodulate the downlink signal from the digital bitstream 152 and output data or information bits from the downlink signal. In some other implementations, the SPS 150 can use cloud computing or cloud processing to perform the signal processing and other methods described herein. The SPS 150 may also be called a cloud server.

[0023] Next, the SPS150 can provide the processed data to the user or transmit it to another site. The data and information may be mission-dependent. Furthermore, the information contained in the data may be the primary purpose of the satellite, including weather data, image data, and satellite communications (SATCOM) payload data. As stated above, SATCOM is used as the primary example herein, but any communications or signal processing system using a DSP can implement the methods described herein.

[0024] To achieve high processing speeds in software, phase-locked loop (PLL) or delay-locked loop (DLL) approaches can be problematic due to feedback within the loop. A feedback loop forces all incoming data (e.g., downlink signals 160 and / or 170) to be processed in a single (e.g., linear) process that cannot be easily divided or otherwise separated. In addition to feedback, there are other obstacles to overcome when using PLLs / DLLs, including the frequency with which error terms are calculated.

[0025] Figure 2 is a functional block diagram of wired or wireless communication devices for use as one or more components of the system in Figure 1. The processing device (device) 200 may be implemented, for example, as SPS150 in Figure 1. Device 200 may be implemented as necessary to perform one or more of the signal processing methods or steps disclosed herein.

[0026] Device 200 may include a processor 202 that controls the operation of device 200. The processor 202 is sometimes called a CPU. The processor 202 can, for example, direct and / or perform functions originating from SPS150. Certain embodiments of device 200 including the processor 202 can be implemented as various cloud-based elements, such as cloud-based processing. Thus, the processor 202 can represent cloud processing distributed across several different processors over a network (e.g., the Internet). Alternatively, a specific component can be implemented in hardware. The processor 202 can be implemented by any combination of one or more of the following: a general-purpose microprocessor, a microcontroller, a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic device (PLD), a controller, a state machine, gate logic, a discrete hardware component, a dedicated hardware finite state machine, or any other suitable entity capable of performing computation or other operations on information.

[0027] The processor 202 may have one or more cores 204 (illustrated as cores 204a through 204n) capable of performing computations. In implementations using cloud processing, the cores 204 may represent multiple iterations of distributed cloud processing. In some embodiments, the processor 202 may be a complex integrated circuit that uses hardware to perform all computations for the receiver. As used herein, each core 204 may be a single processing element of the processor 202. The processor 202 may implement multiple cores 204 to perform the parallel processing required for the methods disclosed herein. In some embodiments, the processor 202 may be distributed across multiple CPUs, as in cloud computing.

[0028] Device 200 may further include memory 206 operably coupled to processor 202. Memory 206 may be cloud-based storage or local hardware storage. Memory 206 may include both read-only memory (ROM) and random access memory (RAM) and can provide instructions and data to processor 202. Part of memory 206 may also include non-volatile random access memory (NVRAM). Processor 202 typically performs logical and arithmetic operations based on program instructions stored in memory 206. Instructions in memory 206 may be executable to implement the methods described herein. Memory 206 may further include removable media or multiple distributed databases.

[0029] Memory 206 may also include machine-readable media for storing software. Software is broadly interpreted to mean any type of instruction, whether called software, firmware, middleware, microcode, hardware description language, etc. Instructions may include code (e.g., in source code format, binary code format, executable code format, or any other suitable code format). When the instructions are executed by processor 202 or one or more cores 204, they cause device 200 (e.g., SPS150) to perform various functions described herein.

[0030] Device 200 may also include a transmitter 210 and a receiver 212 that enable the transmission and reception of data between the communication device 200 and a remote location. Such communication can take place, for example, between a ground station 120 and an SPS 150 via a network 152. Such communication can be conducted wirelessly or via a wired connection. The transmitter 210 and receiver 212 may be combined with a transceiver 214. The transceiver 214 can be communicatively coupled to the network 152. In some examples, the transceiver 214 may include or be part of a network interface card (NIC).

[0031] Device 200 may further include a user interface 222. The user interface 222 may include a keypad, microphone, speaker, and / or display. The user interface 222 may include any elements or components that transmit information to the user of device 200 and / or receive input from the user.

[0032] The various components of device 200 described herein may be coupled together by a bus system 226. The bus system 226 may include not only a data bus, but also, for example, a power bus, a control signal bus, and a status signal bus in addition to the data bus. In some embodiments, the bus system 226 may be communicatively coupled to a network 152. The network 152 may, for example, provide a communication link between device 200 (e.g., processor 202) and a ground station 120. Those skilled in the art will understand that the components of device 200 may be coupled together, or accept or provide input to each other, using some other mechanism such as a local area network or a wide area network for distributed processing.

[0033] Figure 3 is a graphical representation of a schematic block diagram of one embodiment of the feedforward or pre-computed signal processing 300. Method 300 can be carried out, for example, by a processor 202, as a generalized process incorporating multiple functions. The processor 202 can execute multiple functions in series or parallel arrangement, as shown, to execute one or more desired processes. Each function may refer to a block or collection of instructions or software that is executable by the processor 202 and stored in memory 206.

[0034] The first function 302 can be executed by the processor 202. In some embodiments, the second function 304 can be executed in series following the first function 302. Thus, the processor 202 can execute the first function 302 and the second function 304 by dividing blocks of data having different functions for processing across multiple cores 204.

[0035] Processor 202 can execute the distributed processing of the third function 306 (illustrated as 306a, 306b, ..., 306n) in parallel, following the second function 304. To show that various numbers of functions 306a-306n can operate in parallel, three paths are drawn with three dots vertically between them, such as 4, 5, 6, etc., but it is not limited to these, and any number of paths can be included. Parallel processing of the third function 306 may include, for example, dividing blocks of data associated with the same function across several cores 204 of processor 202 (e.g., processing blocks). For example, a “block of data” could mean a group of samples that need to be processed.

[0036] The term “parallel” is used herein to describe processing occurring simultaneously in blocks 306a–306n. Since the packets being processed may have varying lengths from one block 306a–306n to another, the processing of packets may have the same rate or speed from one block 306a–306n to the next. As shown below, some of blocks 306a–306n may progress faster or slower than others. Therefore, the term “parallel” should not be limited to simultaneous or concurrent processing within blocks 306a–306n.

[0037] Next, the processor 202 can execute the fourth function 308 and the fifth function 309 in series. Similar to the first function 302 and the second function 304, the series performance of the fourth function 308 and the fifth function 309 may involve dividing blocks of data associated with different functions for processing across multiple cores 204. In general, each of the first function 302, the second function 304, the third function 306, the fourth function 308, and the fifth function 309 can be executed in different processing blocks. As used herein, a processing block can refer to a specific task to be performed on a block of data. A processing block can be associated, for example, with one or more cores 204.

[0038] Therefore, method 300 can divide blocks of data having the same function for processing across multiple cores 204, for example. Similarly, method 300 can divide blocks of data having different functions for processing across multiple cores 204.

[0039] In some other implementations of Method 300, the same processing block (e.g., core 204) can perform data processing in Single Instruction Multiple Data (SIMD), regardless of whether it has the same or different functionality.

[0040] In other implementations, embodiments of Method 300 can support the processing of data blocks with minimal state information by using redundant data. As used herein, state information may include variables required during feedback (e.g., feedback processing), data frame boundaries, etc. For example, in the case of a feedback loop, state information may include variables computed within the loop during feedback when processing a continuous data stream. State information may also include the position of frame boundaries in the data stream. Other examples include things like FIR filters, where state information includes values ​​stored in buffers (e.g., possibly many delay elements) necessary to maintain a continuous data flow.

[0041] By ignoring state information and overlapping portions of adjacent data blocks, processes can utilize parallel processing with a variable level of overlap between data blocks.

[0042] Figure 4 is a graphical depiction of one embodiment of the feedforward or pre-calculated signal processing method of Figure 3. Method 400 can use the principles of Method 300 for serial-parallel and / or parallel-serial processing of multiple functions grouped as a process 315. In one example, the first function 302 (Figure 3) may be a data acquisition function 305 in which the processor 202 receives data for processing. The second function 304 (Figure 3) may be a data partitioning function 310 in which the processor 202 can parse data in overlapping data blocks. The overlapping data blocks can then be processed in parallel in various parallel iterations of the multiple functions as processing blocks 315a to 315n. For example, the first data block may be processed by a group of functions in processing block 315a, and another data block may be processed by a group of functions in another processing block 315b to 315n, which is executed in parallel with processing block 315a. Multiple processing blocks 315a to 315n can be executed in parallel and are not limited to two processing blocks such as those. Duplication in data blocks can provide a level of redundancy that is less (or no) dependent on state information. The less state information required, the easier it is to process data blocks in parallel, as opposed to a continuous stream. To demonstrate that various numbers of processing blocks 315a-315n can operate in parallel, three paths are drawn with three dots vertically between them, such as 4, 5, 6, etc., but it is shown that any number of paths can be included, but not limited to these.

[0043] The term "parallel" is used herein to describe processing that occurs simultaneously in processing blocks 315a–315n. Since the packets being processed may have different lengths from one processing block 315a–315n to another, the processing of packets may have the same rate or speed from one processing block 315a–315n to the next. As shown below, some of the blocks 315a–315n may proceed faster or slower than others. Therefore, the term parallel should not be limited to simultaneous or concurrent processing within processing blocks 315a–315n.

[0044] Method 400 is similar to the fourth function 308 (Figure 3) and may further include a data synthesis function 320 for synthesizing processed data, and a data output function 325 similar to the fifth function 309 (Figure 3).

[0045] In a further example, the tunable series-parallel or parallel-series arrangement of the various functions of Method 300 provides several ways to implement feedforward processing to replace feedback loops. This is advantageous because it can improve throughput and avoid bottlenecks caused by delays during feedback processing.

[0046] An additional advantage of serial-parallel or parallel-serial processing provided by methods 300 and 400 is that by placing one or more desired algorithms within a processing block (e.g., one of the five processing blocks of method 300), the processor 202 can distribute the processing load (e.g., across multiple cores 204) without concern for the speed of a given algorithm within a processing block (e.g., a core 204). Thus, each core 204 shares exactly the same processing load, eliminating bottleneck problems caused by individual algorithms.

[0047] A further advantage of embodiments of Method 300 may include customizing the order of dedicated algorithms (e.g., processing blocks) to reduce the computational load within the processor 202. As described below, the overall multi-stage processing of a given process may not depend on the order of multiple subprocesses. Thus, in some examples, ordering the fourth function 308 may have particular advantages if it is executed before the third function 306.

[0048] Method 300 can further implement different variable types, such as int8, int16, and float, to optimize memory bandwidth. This allows for acceleration of specific algorithms (such as type-based algorithms). Furthermore, this improves flexibility and maximizes memory bandwidth.

[0049] Figures 5 and 6 are functional block diagrams of embodiments of a digital signal diversity combiner. Diversity combining methods 500 and / or 600 may include feedforward block processing as described above in relation to Figures 3 and 4. Methods 500 and / or methods 600 may include multiple blocks. In some examples, each block represents a functional block and can perform a function in a similar manner to functional blocks 306a, 306b, ... 306n (Figure 3), etc. In other examples, two or more of the multiple blocks in Figures 5 and / or 6 may be combined and grouped together as a single “process” 315 that performs a function in a similar manner to processing blocks 315a, 315b, ... 315n (Figure 4), etc.

[0050] Figure 9 is a functional block diagram of one embodiment of a channel simulator. The channel simulation method 900 may include the feedforward block processing described above in relation to Figures 3 and 4. The method 900 includes multiple blocks. In some examples, each block represents a functional block and can perform a function in a similar manner to functional blocks 306a, 306b, ... 306n (Figure 3), etc. In other examples, two or more of the multiple blocks in Figure 9 can be grouped together as a single "process" 315 that performs a function in a similar manner to processing blocks 315a, 315b, ... 315n (Figure 4), etc.

[0051] Figure 10 is a functional block diagram of an embodiment of a signal modulator for waveform generation. The signal modulation method 1000 includes feedforward block processing as described above in relation to Figures 3 and 4. Method 1000 includes multiple blocks. In some examples, each block represents a functional block and can perform a function in a similar manner to functional blocks 306a, 306b, 306n (Figure 3), etc. In other examples, two or more of the multiple blocks in Figure 10 can be grouped together as a single "process" 315 that performs a function in a similar manner to processing blocks 315a, 315b, ... 315n (Figure 4), etc.

[0052] In block 305, the SPS150 can acquire or otherwise receive the digital bitstream 152 (for example, via network 152). Data acquisition in block 305 can receive digital bitstream data from a network connection (for example, Ethernet).

[0053] In block 310, data can be split into parallel data streams by a data splitter. In some embodiments, the processor 202 can perform the data splitting function required in block 310. In some other embodiments, a separate data splitting component (e.g., a data splitter) can be included in device 200 (Figure 2). Splitting data into multiple parallel streams enables parallel processing of downlink signals such as downlink signals 160, 170, etc. Thus, method 300 can utilize feedforward or pre-computation processing to split incoming digitized signal data into smaller parts before processing by multiple cores 204. The digital bitstream 152 can be split to form packets that overlap in in-phase / orthogonal (I / Q) pairs. In some embodiments, “overlapping packets” can include data packets in which consecutive packets overlap with adjacent data packets. In some embodiments, all data packets may be the same length, but may overlap. Overlapping in data packets can be at the beginning or end of the data packet. Furthermore, a data packet may overlap with both preceding and succeeding data packets. Data packets can have different lengths (for example, the amount of data may vary). Therefore, the first packet sent to processing block 315a may overlap with certain data in the second packet sent to processing block 315b, or the data may be repeated in other ways.

[0054] The amount of overlap between packets, or the overlap size, can be programmed and configured as needed. In some examples, the overlap can be set to 1 percent (1%) of the packet size. This overlap size can be increased or decreased as needed. For example, one specific parameter that can affect the overlap size is the uncertainty of the symbol rate in the digital bitstream 152. For most signals, the worst-case uncertainty is less than 1%, so 1% overlap covers most cases. In some other embodiments, the overlap can be as high as 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, or even 10%, or anywhere in between, as needed. It is also possible to have overlap of less than 1%. If the data rate uncertainty is less than 0.1%, the overlap may be 0.1% or less.

[0055] Processor 202 can implement Single Instruction Multiple Data (SIMD) processing on the digital bitstream 152. In some examples, SIMD may include Advanced Vector Extensions (AVX-512) using 512 bits, enabling 16 floating-point operations on a single CPU core with a single CPU instruction. For example, AVX-512 can process enormous amounts of data on a CPU (e.g., CPU 202). For example, processor 202 (and device 200) can receive a data stream with a 500 MHz bandwidth. The 500 MHz bandwidth is significant in several respects, as it is a generally accepted practical limit for a 10 Gigabit Ethernet link. Sampling data including a parity bit at 500 MHz using 8-bit samples for I / Q pairs can saturate a 10 Gigabit Ethernet link. The 500 MHz example is not limiting to this disclosure. Larger data pipes than a 10 Gigabit Ethernet link are possible. Furthermore, the processing can be divided into n parallel blocks (for example, block 315) to accommodate any amount of data.

[0056] Process 315 is shown by a dashed line and represents the processing steps of method 300. Process 315 is shown to be executed in multiple parallel steps or processing blocks 315a, 315b, ... 315n.

[0057] As used herein, process 315 can refer to, for example, a collection of processing functions performed by processor 202. The digital bitstream 152 can be divided and transmitted into multiple parallel processing blocks 315a, 315b, ... 315n, distributing the processing load across several cores 204. Each individual processing block 315a, 315b, ... 315n can represent an individual iteration of cloud processing. Thus, each processing block 315a-315n can be associated with a (cloud-based) core 204a-204n. The required number of processing blocks 315a-315n varies based on the amount of data being processed. In some embodiments, the number of processing blocks 315a-315n can be limited by the number of available logical cores, either via the network 152 or, in the case of local hardware processing, within processor 202. In some other embodiments, memory bandwidth constraints may cause bottlenecks during signal processing. Memory bandwidth can refer to the rate at which data can be read from or stored in semiconductor memory (e.g., memory 206) by a processor (e.g., processor 202).

[0058] In some embodiments, the number of processing blocks 315a-315n can vary. Generally, the fewer processing blocks 315a-315n present, the more appropriate it is to limit the number of cores required for the entire process. This makes it even possible to adapt the system to smaller virtual private cloud (VPC) machines for less expensive operation. A VPC could include, for example, an SPS150 with several CPUs. In some embodiments, eight processing blocks 315a-315n can be used for a 10 Gigabit Ethernet link. Such embodiments may not include forward error correction processing blocks. In some other embodiments, the only practical limit on the number of required processing blocks 315a-315n is the bitrate and bandwidth of the communication link (e.g., the size of the pipe). Thus, any number (n) of processing blocks 315a-315n is possible. However, in some embodiments, there may be a practical limit on the number (n) of processing blocks 315a-315n based on the number of threads that can be executed on the CPU, or the number of cores 204 in the processor 202. However, if a limit is reached within a single CPU, multiple CPUs (e.g., processor 202) within an SPS150 (e.g., VPC) can together have an unlimited number of cloud-based CPUs or cores 204 to perform processing. Furthermore, processor 202 can create new processing blocks 315a-315n as needed. Processing cores 204 can be distributed across multiple distributed processors (e.g., processor 202) as needed for throughput and efficiency.

[0059] Processing blocks 315a to 315n are arranged in a manner that does not depend on which processing block 315a, 315b, ... 315n is executed the slowest (or fastest). Method 300 can share the processing load across processing blocks 315a to 315n, thereby mitigating any processing delays caused by bottleneck issues in individual processing blocks 315a to 315n. For example, individual subprocesses in processing blocks 315a to 315n (see explanation in Figure 4 below) may or may not be executed at the same rate (e.g., some may be faster than others). Thus, for example, a larger process in Method 400 (Figure 4) can account for variations in performance or processing time. Processing block 315 can be created as many times as necessary to process incoming data.

[0060] In some embodiments, each processing block 315a-315n may represent a collection of signal processing algorithms executed by the processor 202. As used herein, an algorithm may refer to a minimal collection of function or method steps that perform a desired function. Several exemplary algorithms are described herein.

[0061] An exemplary advantage of method 300 is the ability to create more processing blocks 315a-315n as needed. Generally, processing blocks 315a-315n can be implemented in software and therefore can be created or removed as needed to suit a given data rate or processing load. Each processing block 315a-315n can be rearranged to suit the needs of different received waveforms (e.g., downlink signals 160 and / or 170) and associated digital bitstreams 154.

[0062] In block 320, processed signal data from multiple processing blocks 315 can be recombined to form the original data encoded and modulated over the downlink signals 160, 170. In some embodiments, the processor 202 can perform the function of a data recombiner. In other embodiments, the device 200 may have additional components to perform such functions. Each data packet or processed data block may have a timestamp. A data recombiner (e.g., the processor 202) can order the data blocks based on the timestamp and compare the phases between the ordered blocks. The recombiner can further adjust the phases of adjacent blocks to reorder the data stream. In some embodiments, the phase of a subsequent data block can be adjusted to match the phase of a preceding data block.

[0063] Every processing block shown in process 315 has at least four options for execution: 1) Each sub-element within processing block 315 (e.g., each block 315a to 315n) acquires its own core (e.g., cores 204a to 204n), and execution of multiple blocks. 2) Processing block 315 has only one dedicated core for the entire block, executing multiple blocks. 3) Execution of a single block in which each sub-element within the processing block acquires its own core, and 4) Execution of a single block, where the processing block has only one dedicated core for the entire block.

[0064] The more cores that can be used, the higher the rate that can be achieved.

[0065] In block 325, device 200 can output data to an appropriate receiver. In some examples, such receivers may be one or more mission operations centers. This data may be mission-dependent (e.g., satellite objective) and may include, in particular, weather data, image data, and SATCOM payload data.

[0066] In general-purpose CPUs, there are at least three main factors that can limit high-rate performance: 1) data ingestion, 2) CPU capacity, and 3) memory bandwidth utilization. Data ingestion refers to how quickly data can be supplied to the CPU. CPU capacity is determined by the CPU's clock speed and the number of cores within the CPU. Memory bandwidth refers to how quickly data can be transferred between the CPU and external DDR RAM (not the CPU cache). Memory bandwidth may be determined by the number of memory lanes and the clock speed of the DDR RAM. In certain cases, the limiting factor for achieving high-rate processing is CPU capacity, but in other cases, it is memory bandwidth. Care must be taken to determine which of the above cases is affecting performance and whether memory bandwidth is limiting, and the embodiments described below are non-limiting examples of methods for reducing memory bandwidth utilization within the proposed patent approach.

[0067] Function calls within a given processing block can be arranged in a way that optimizes CPU computation or memory bandwidth usage. For example, referring to the function calls shown in Figure 5 (exemplified as a block), in a given example, various function calls (e.g., timing recovery block, carrier recovery block, correlator block, time adjustment block, phase rotation block, power and Es / No estimator block, amplitude adjustment block, and weighted combiner block) can be grouped in a way that minimizes memory bandwidth. Since these function calls can be called independently, each function is simplified by completing each function on the dataset before starting another function. In another example, multiple or all function calls can be combined into a single block, so that after each function is executed, data is not transferred to RAM, and the memory bandwidth of the combined function is much smaller before it is called independently. When functions are called independently, the first function call (e.g., timing recovery) may be executed across the entire dataset before the second function call (e.g., correlator) occurs. In the case of combination, only a portion of the data is processed during the first function call before the second function call is executed. In this way, memory bandwidth is reduced. This method can be applied not only to the function shown in Figure 5, but to any grouping of functions. For example, this method may be applied to the method shown in Figure 6, or to any other grouping of function calls performed within the blocks disclosed herein (e.g., the various function call blocks shown in Figures 7-10).

[0068] Another way to improve memory bandwidth utilization, similar to the approach described above, is to fold several function call blocks into a single block. For example, as will be explained in more detail below with reference to Figure 5, multiple functions may be required to perform timing and carrier recovery. Normally, each function requires its own block for ease of operation and CPU optimization, but all functions can be combined into a single processing block to reduce memory bandwidth utilization. This trade-off reduces memory bandwidth utilization relative to the performance of the CPU hit.

[0069] A diversity combiner after digital signal detection that employs parallel processing across multiple cores to run on a general-purpose CPU and achieve high-throughput operation in a cloud environment: As described above, Figures 5 and 6 are functional block diagrams of exemplary implementations of methods 500 and 600. In various examples, each of methods 500 and 600 may be an example of a diversity combiner method. To show that various numbers of signals can be processed in parallel, two paths are drawn with three dots vertically between them, indicating that any number of paths, such as four, eight, etc., can be used. Diversity combining may be optimized to transfer the combined information to multiple input signals A through N by combining multiple antenna feeds so that all signals are aligned in time and phase and weighted based on signal quality. Signal quality may be determined using one or more of the following, for example, but not limited to, signal-to-noise ratio, energy-to-noise power spectral density ratio per symbol (Es / No), power estimate, and received signal strength indicator (RSSI). The multiple antenna feeds may be from one or more remote locations, such as platform 110 or satellite 111. While a satellite is used as an example in this specification, other wireless transmission systems such as a radio antenna (e.g., antenna 122) or other types of transmitters may be implemented. Therefore, the use of a satellite is not limited to this disclosure.

[0070] In the case of a satellite as shown in Figure 1, platform 110 and satellite 111 are visible from the same ground station (e.g., ground station 122), but diversity synthesis can be used during an antenna handover event even if, for example, satellite 111 is below the horizon (e.g., in the east) and platform 110 is above the horizon (e.g., in the west). Several calculations need to be performed in order to properly synthesize the downlink signals. The disclosed system can digitize the signals and convert them into digital samples, which are then transported to a signal processing element. The system can further calculate and compensate for the Doppler effect. The system can also determine the time difference of each signal and the estimated signal-to-noise ratio, as well as the residual phase and frequency delta (e.g., difference) between the downlink signals. Following these operations, the signals are combined and synthesized.

[0071] Numerous approaches can be used to synthesize signals. For example, signals can be synthesized using pre-detection (Pre-D) diversity combiners and / or post-detection (Post-D) diversity combiners. A Pre-D diversity combiner may be configured to synthesize signals before performing a match filter (e.g., also called a detector). An exemplary implementation of a Pre-D diversity combiner is described in PCT / US2020 / 65351, the disclosure of which is incorporated herein by reference in its entirety. A Post-D diversity combiner may be configured to synthesize signals after the completion of the match filter function. Thus, a Post-D diversity combiner may present a simplified method for performing diversity synthesis that is superior to the Pre-D method, since the signals and data packets are discrete digital samples. Therefore, the function and complexity may be reduced compared to a Pre-D diversity combiner. For example, Post-D may be simpler because it is performed after the match filter and the synthesis takes place in symbol space. In other words, time adjustment can be performed in only one symbol step, and subsample adjustment is unnecessary; this does not apply to Pre-D.

[0072] Implementations of a Post-D diversity combiner may include Post-D End (hereinafter referred to as Post-DE, an exemplary example of which is shown in Figure 5) and Post-D Mid (hereinafter referred to as Post-DM, an exemplary example of which is shown in Figure 6). As used herein, Post-DE may refer to a combiner in which the signals are combined after the match filter has been executed and after full demodulation, including carrier and timing recovery, has been performed. In other words, the combination in the Post-DE method takes place after both timing recovery and carrier recovery are locked. As used herein, the term "locked" refers to error-free demodulation of the signal in which proper timing and / or carrier alignment is achieved through timing recovery and / or carrier recovery, respectively. As used herein, Post-DM may refer to a combiner in which the input signals are combined after a partial execution of the full demodulation process, for example, after the timing recovery of the demodulation processing chain and the match filter, but before the carrier recovery of the demodulation processing chain. Thus, the Post-DM method makes it possible to combine after timing recovery is locked but before carrier recovery. An example of the non-limiting advantages of Post-DM is that the combined signal can achieve a higher Es / No and / or signal-to-noise ratio (SNR) before carrier recovery is performed. Since carrier recovery can fail at higher Es / No than timing recovery, the Post-DM method may improve the overall Es / No sensitivity of the system. However, the Post-DM method may involve increased costs of complexity during implementation. On the other hand, the Post-DE method may be simpler to set up and run, but it may require locking carrier recovery before synthesis, which is usually a limiting factor for receiver sensitivity. This limits the low Es / No and / or SNR at which diversity combiners can operate, and may limit the usefulness of power forward error correction (FEC), as used in some waveform standards such as DVB-S2.

[0073] The Post-DM and Post-DE methods disclosed herein represent two possible high-level examples of Post-D diversity combiner methods. It will be understood that the embodiments disclosed herein are not limited to these two methods; other methods are also possible.

[0074] Figure 5 shows an exemplary Post-DE diversity combiner as Method 500. As shown in Figure 5, Method 500 optimizes the transfer of information combined from multiple signals by receiving input samples from multiple antenna feeds (e.g., receiving and sampling downlink signals 160 and / or 170 at the antennas and feeding them to Method 500), combining and synthesizing the inputs, and outputting a synthesized signal in which the signals are aligned in time and phase and weighted based on signal quality. Method 500 can be implemented by a processor (e.g., processor 202 in Figure 2), which may be implemented as SPS150 in Figure 1.

[0075] Method 500 includes multiple functional blocks, for example, multiple timing recovery blocks 510a to 510n (collectively referred to as timing recovery block(multiple) 510 or block(multiple) 510), multiple carrier recovery blocks 520a to 520n (collectively referred to as carrier recovery block(multiple) 520 or block(multiple) 520), one or more correlator blocks(multiple) 530, and multiple time adjustment blocks 540a to 540n (collectively referred to as time adjustment block(multiple) 540 or block(multiple) 54 It includes a plurality of phase rotation blocks 550a to 550n (collectively referred to as phase rotation block(s) 550 or block(s) 550), a plurality of amplitude adjustment blocks 560a to 560n (collectively referred to as amplitude adjustment block(s) 560 or block(s) 560), a plurality of power and Es / No estimator blocks 565a to 540n (collectively referred to as power and Es / No estimator block(s) 565 or block(s) 565), and one or more combiner blocks(s) 570. In the illustrated example, several blocks 510a-510n, 520a-520n, 540a-540n, 550a-550n, 560a-560n, and 565a-565n are shown to perform functions on multiple samples of downlink signals received through multiple antenna feeds, with each block performing functions on the corresponding signal. Any number of signals is possible, but the examples herein will be illustrated with reference to two signals (e.g., sample A and sample N).

[0076] In the exemplary example of Figure 5, a given timing recovery block 510 and the corresponding carrier recovery block 520 may be part of a full demodulation process, including match filters for their respective input signals. For example, blocks 510a and 520a may be part of a full demodulation process for signal A, and blocks 510n and 520n may be part of a full demodulation process for signal N. Each block 510 and block 520 may be configured to demodulate their respective input signals and may be referred to herein as a demodulator processing chain. Thus, the Post-DE method shown in Figure 5 is configured to combine the input signals at the end of the demodulator chain (e.g., following the execution of the demodulator chain). Thus, the combiner logic is post-demodulation but before forward error correction.

[0077] As described above, each of the multiple blocks of Method 500 can represent a function and may be implemented as one or more of the functions 306a, 306b, ... 306n (Figure 3). For example, as shown in the exemplary implementation in Figure 5, the correlator block 530 may be implemented as function 306 in Figure 3, and can divide such data from carrier recovery blocks 520a-520n into data blocks for processing by parallel functions 306a-306n. Similarly, as shown in Figure 5, the combiner block 570 may be implemented as function 306 and may be executed as multiple functions 306a-306n for processing multiple data blocks in parallel. While specific examples of blocks are shown to be implemented as function 306, these examples are not intended to be limiting, and any block of Method 500 may be implemented as function 306.

[0078] In another example, the multiple blocks shown in Figure 5, either individually or in combination, can be grouped together as a single “process” 515 that performs a function similar to process 315 in Figure 4. That is, the multiple blocks in Figure 5 may be grouped together as process 515 and may be executed in multiple parallel iterations as processing blocks 315a, 315b, ... 315n (Figure 4). For example, different parts of method 500 may be grouped together as process 515 and may be executed in serial-parallel and / or parallel-serial processing as described above in relation to Figure 4. In the exemplary example shown in Figure 5, the timing recovery block 510n and carrier recovery block 520n for executing a match filter along the processing path of signal N are grouped together as process 515. In this case, referring to Figure 4, the input sample can be captured in block 305 and divided into duplicate sample blocks in block 310, where each of the duplicate data blocks can be processed as processing blocks 315a to 315n in multiple parallel iterations of timing recovery block 510n and carrier recovery block 520n. The processed duplicate data blocks are then output to data synthesis 320 for synthesis of the processed data, and subsequently output by block 325 for processing by subsequent blocks of method 500. The data synthesis block 320 in Figure 4 should not be confused with the combiner block 570. Block 320 synthesizes the parallel processing blocks 315a to 315n, while the combiner block 570 performs diversity synthesis, as described later. Similarly, as illustrated in Figure 5, the time adjustment block 540n, the phase rotation block 550n, and the power and Es / No estimator block 565, as well as the amplitude adjustment block 560n, are grouped together as a processing block 315.

[0079] While specific examples of blocks are shown grouped together as process 515, these examples are not intended to be limiting, and any grouping of one or more blocks of method 500 may be grouped together as process 515 and executed in parallel as described in relation to Figure 4. For example, one or more of the time adjustment block 540n, the phase rotation block 550n, and the amplitude adjustment block 560n may be executed as process block 315.

[0080] Furthermore, although Figure 5 shows only the path portion corresponding to the input from signal N grouped together, it can be understood that various blocks of signal A path can also be grouped together as process 515 and executed in parallel. For example, blocks 510a and 520b can be grouped as the first process 515, and blocks 540a to 565n can be grouped together as the second process 515. As mentioned above, other groupings are also possible.

[0081] In various examples, the multiple blocks in Figure 5 may be implemented using SIMD processing techniques, as described throughout this disclosure. SIMD techniques can be shown to improve throughput and minimize memory bandwidth requirements. Increasing the functionality of each processing block executed using SIMD techniques may be useful in further minimizing memory bandwidth requirements.

[0082] In blocks 510 and 520, the processor 202 (e.g., one or more cores 204) can perform timing and carrier recovery for each input sample from each antenna feed to the downlink. An example of a timing and carrier recovery method is illustrated in Figures 7 and 8.

[0083] Figure 7 is a flowchart of an example of a timing and carrier recovery method implemented by the signal processing methods of Figure 3 and / or Figure 4. Figure 7 shows a method 700 comprising multiple blocks, one or more of which may be implemented as a process 315 to process the grouping of blocks in each of the processing blocks 315a to 315n of Figure 4. Each block of method 700 may be implemented as a function 306, so that a single block can be executed across functions 306a to 306n of Figure 3. The execution of blocks according to Figure 3 may be performed separately or in combination with the execution of processes according to Figure 4.

[0084] Method 700 can be used for standard waveform processing, in contrast to the offset waveforms described below. For example, standard waveform processing can be used for waveforms that map bits to symbols and modulate those symbols to a carrier wave. Examples of standard waveforms include quadrature amplitude modulation (QAM) waveforms as well as binary phase-shift keying (BPSK), quaternary phase-shift keying (QPSK), 8PSK, 16APSK, 32APSK, and 64APSK. Method 700 may be the exemplary timing recovery processing block 510 and the exemplary carrier recovery block 520 in Figure 5.

[0085] In block 705, the processor 202 (e.g., one or more cores 204) can perform a timing recovery error calculation on the received data packet (e.g., samples of digitized bitstream 154 or digitized downlink signal 160 and / or 170). The timing recovery error calculation can provide the phase information necessary to properly align a matched filter to the incoming data stream (e.g., digitized bitstream 134). The matched filter is used to match the transmitted waveform in the time domain and its performance is optimized by being aligned with the timing error to capture all the energy in the received signal. The result of the timing recovery error calculation may include three parameters: 1) start phase (degrees), 2) frequency adjustment (Hertz (Hz)), and 3) Doppler rate adjustment (Hz / second). The units described above are illustrative and not limiting to the present disclosure. Other equivalent units are also possible.

[0086] In block 710, processor 202 (e.g., one of cores 204) performs timing recovery on the packet to align the internally generated match filters with the received samples generated by each of the modulator's match filters. The alignment is based on calculations in block 705. The output of block 710 is the synchronized (e.g., time-corrected) symbols in the data packet received in block 705.

[0087] Examples of timing recovery error calculation blocks 705 and 710 are described in U.S. Patent No. 10,790,920, the disclosure of which is incorporated herein by reference as if it were fully described. For example, as is known in the art, an estimated Gardner timing error detector can be applied to incoming data to create timing information. In another embodiment, the incoming sample stream can be delayed by one sample. The undelayed data can then be multiplied by the conjugate of the delayed data (conjugate multiplication). Both approaches have advantages and disadvantages, so the choice of implementation is a trade-off. The timing spikes generated by the Gardner timing error detector can be mixed with timing estimates or symbol rate estimates. The mixed signal may be decimated to reduce the sampling rate. Phase unwrapping calculations may be performed on the decimated samples. Curve fitting calculations can also be performed to determine phase, frequency, and Doppler rate offset information that can be applied to update the timing estimates.

[0088] In block 715, a processor 202 (for example, one of the cores 204) can perform carrier recovery error calculations on the packet to determine phase and frequency information.

[0089] In block 720, a processor 202 (e.g., one of the cores 204) can perform carrier recovery on packets based on calculations in block 715. Carrier recovery compensates for unknown frequency, Doppler rate, and phase offset in downlink signals (e.g., downlink signals 160 and / or 170) from a spacecraft (e.g., satellite 110). The two most common sources of uncertainty are the Doppler effect from the spacecraft's motion and the Doppler effect from an imperfect oscillator within the spacecraft. The processor 202 can apply phase, frequency, and Doppler rate corrections from block 715 to form synchronization symbols corresponding to the modulated data in the downlink signals (e.g., downlink signals 160 and / or 170) at the output of block 720.

[0090] Examples of carrier recovery error calculation blocks 715 and 720 are also described in U.S. Patent No. 10,790,920, the disclosure of which is incorporated herein by reference as if it were fully described. For example, an incoming signal can be boosted to a certain power based on the modulation type. A mixed signal can be decimated to reduce the sampling rate. A phase unwrap calculation can be performed on the decimated sample. A curve fitting calculation can be performed to determine phase, frequency, and Doppler rate offset information that can be applied to update the carrier recovery algorithm. Curve fitting can also be used to update (and improve) the carrier frequency estimate.

[0091] In some implementations, blocks 705 and 710 may be grouped together as a single processing block, for example, as a timing recovery processing block 510, as shown in Figure 5. Similarly, in some implementations, blocks 715 and 720 may be grouped together as a single processing block, for example, as a carrier recovery processing block 520, as shown in Figure 5. In some implementations, one or more additional processing blocks may be executed between blocks 710 and 705, for example, as shown in Figure 6.

[0092] Furthermore, the timing recovery error calculation 705 and the timing recovery block 710 may be grouped together as process 315 in Figure 4. If timing recovery is performed across multiple processing blocks 315a to 315n, the signals may be combined via block 320 before execution of the grouped blocks (e.g., process 315) and output as a single-thread operation per signal by block 325 in Figure 4. Blocks 305, 310, 320, and 325 are not shown in Figure 7, but it will be understood that such blocks may exist so that the process can take in input data (305), divide it (310), perform grouping functions as processing blocks 315a to 315n, and then combine the resulting processed data for downstream processing (320) and output it (325). As shown in Figure 7, here the output signals are in symbol space and downstream functions can be performed on the resulting output symbols. The more processing blocks that are executed, the higher the processing rate that can be achieved and the higher the throughput.

[0093] In block 710, after conversion from sample space to symbol space, the signal symbols can be corrected by blocks 715 and 720. Blocks 715 and 720 can be grouped together as process 315 in Figure 4. Thus, the symbols output from block 710 may be fed back into the carrier recovery process 315, which may be executed across processing blocks 315a to 315n, and block 710 may be implemented as a separate process and / or function from block 715, for example, as described above.

[0094] As another example, each of blocks 705-720 may be grouped as a single processing block 315, as described above in relation to Figure 5, for example, or may be executed across processing blocks 315a-315n in Figure 4. Furthermore, each of blocks 705-720 may be implemented as a function 306, or may be executed across cores 204 as functions 306a-306n.

[0095] Figure 8 is a flowchart of one embodiment of another method for timing and carrier recovery implemented by the signal processing method in Figures 3 / 4 (processes occurring in each block 315a-315n). Figure 8 shows another method 800 which may be similar to method 700 (Figure 7) in which some functional blocks are combined and rearranged. Similar to method 700, method 800 can be used for offset waveform processing. For example, offset waveform processing can be used for waveforms that have an offset or stagger between the in-phase (I) channel and the quadrature (Q) channel, such as offset quaternary phase shift keying (OQPSK), minimum shift keying (MSK), Gaussian minimum shift keying (GMSK), and shaped offset quaternary phase shift (SOQPSK).

[0096] In block 805, the processor 202 (e.g., one or more cores 204) can perform timing and carrier recovery error calculations on the packet. The timing and carrier recovery error calculations are similar to those performed in blocks 705 and 715 (Figure 7). However, in method 800, carrier recovery is performed before the timing recovery of the symbol. The input to method 800 is a sample, and the output is a corrected synchronization symbol.

[0097] In block 810, a processor 202 (e.g., one or more cores 204) can perform carrier recovery operations based on calculations from block 805. An example of timing and carrier recovery error calculation block 810 is also described in U.S. Patent No. 10,790,920, the disclosure of which is incorporated herein by reference as if it were fully described. For example, if a digitized bitstream can be squared, spikes can occur in the frequency domain. Each spike can be mixed with a mixed signal created from a composite estimate of the carrier frequency and symbol rate. The two mixed signals may then be decimated to reduce the sampling rate. Phase unwrapping calculations and curve fitting calculations may be performed on both mixed signals. The results are then passed to carrier recovery and timing recovery algorithms to update the information.

[0098] Referring back to Figure 5, each of the input signals output from blocks 520a to 520n is supplied to block 530 with corrected symbols. In block 530, the processor 202 (e.g., one or more cores 204) can calculate the time and phase relationships between the input signals (two input signals in this example). For example, block 530 can perform a correlator function using the Fast Fourier Transform (FFT) on the corrected symbols, and both time and phase information indicating the respective offsets or staggers between the input signals from the same operation can be output. Performing a coarse correlation using the FFT allows for finer correlation on smaller datasets to ensure that the time and phase alignment remains unchanged.

[0099] Coarse correlation sometimes refers to performing timing and phase differences between two signals across many symbols to determine the time uncertainty between the two signals. For a single satellite and two antennas, this time is usually short (e.g., less than a microsecond) and can vary based on cable length and timing differences in analog equipment. For rates less than 1 million symbols per second (Msps), coarse timing estimation may only need to cover + / - 1 symbol. If the symbol rate is 100 Msps, coarse timing estimation may need to cover + / - 100 symbols. For example, in an antenna handover scenario with two satellites and two antennas, the timing difference between the two signals can be 100 milliseconds or more. At 1 Msps, coarse timing estimation may need to cover at least + / - 100k symbols. Also at 100 Msps, coarse timing estimation may need to cover 10 million symbols. While fine correlation may be required to perform the analysis on at least one symbol, it may be performed over 3 to 15 symbols to ensure that the timing alignment obtained is not lost due to coarse correlation. For each acquisition mode, if the timing is known, the phase difference between two signals can be determined by comparing either the phase of the FFT result, as in the case of coarse correlation, or the phase of a properly time-aligned correlator, as in the case of fine correlation.

[0100] In block 540, timing information from block 520 is supplied to block 540 and the processor 202 (e.g., one or more cores 204) to adjust the timing of the input signals based on the timing information. Since the signals have already been properly demodulated and passed through a matched filter, and are here merely symbols, time alignment is straightforward, requiring only the application of delays of an integer number of symbols instead of a fraction of samples, as in pre-D synthesis. Block 540 can apply delays based on the timing offsets between the input signals calculated in block 530 for proper alignment between the input signals. That is, for example, a delay corresponding to the timing offset between input signal A and input signal N is applied to align the symbols of each signal in the time domain. For example, block 520 can calculate the time relationships for aligning the symbol streams from blocks 520a to 520n so that each symbol from one signal chain matches the symbols of other symbol chains with respect to symbol order. For example, if the system includes a single satellite (e.g., satellite 111 or platform 110) and two antennas (e.g., antennas 122, 132, and / or 142), each symbol from the satellite transmitter can be labeled with a number corresponding to all the symbols being transmitted. The correlator 530 determines that the first symbol is symbol 1, the 100th symbol is symbol 100, and so on. The time adjustment block 540 then ensures that symbol 1 from signal A is aligned with symbol 1 from signal N.

[0101] The phase offset information calculated in block 530 is supplied to block 540, where the processor 202 (e.g., one or more cores 204) rotates the phase of at least one input signal to align the phases of the signals. Block 550 can eliminate the Doppler effect by rotating one of the signals based on the phase offset information from block 530 to properly align it with the other signals(s). This operation can be achieved using complex multiplication, as is known in the art. In some cases, if the phase shift is + / - 90 degrees or 180 degrees, a combination of in-phase (I) and quadrature (Q) channels can be performed, including swapping and / or inversion. As an exemplary example, the phase of the first signal A needs to be properly adjusted to match the phase of signal N. For example, in the case of QPSK, there are four possible phases for each symbol. Since the demodulator does not guarantee how these four possible phases will align after demodulation, one of the signal phases needs to be adjusted to match the other phases. Block 530 calculates this adjustment amount. For example, suppose the phase of signal A of symbol 1 is 45 degrees and the phase of signal N of symbol 1 is 135 degrees. Block 530 determines that signal N needs to be adjusted by -90 degrees in order for symbol 1 of signal N (and all other symbols) to align with symbol 1 of signal N, and passes this information to block 550, which rotates the phase of the signals accordingly.

[0102] In block 565, the processor 202 (e.g., one or more cores 204) estimates the signal power and Es / No for each input signal. In block 565, Es / No can be measured using one of several approaches. One exemplary example for measuring Es / No is to calculate (C / N) × (B / fs), where C / N is either the carrier-to-noise ratio or the signal-to-noise ratio, B is the channel bandwidth in Hertz, and fs is the symbol rate or number of symbols per second. However, it will be understood that any approach for measuring Es / No is equally applicable to the embodiments disclosed herein. In another example, block 565 can estimate signal quality, such as the signal-to-noise ratio, power estimate, and received signal strength indicator (RSSI). These estimates can be supplied to block 570 to appropriately weight each input signal for synthesis.

[0103] Power and Es / No estimates from block 565 may be supplied to block 560 along with amplitude information indicating the difference in signal amplitude from block 530. Alternatively, since these blocks may include an automatic gain control (AGC) loop, the amplitude information may be applied directly by the demodulation process (e.g., blocks 510 and 520). In either case, in block 560, the processor 202 (e.g., one or more cores 204) adjusts the amplitude of each signal, for example, by multiplying the amplitude of the input signal based on the power and Es / No estimates provided from block 565. In subsequent synthesis, signals A-N are weighted by the difference in Es / No between them. For example, if both signals have the same Es / No, a 50 / 50 weighting may be applied, scaled by 0.5 (or weighted by 50%) before each signal is synthesized. If the Es / No difference between the signals is 3dB, a 66 / 34 weighting may be applied, where the higher Es / No signal is scaled by 0.66 (or weighted by 66%) and the lower Es / No signal is scaled by 0.34 (or weighted by 34%) before being combined.

[0104] As described above, once the signals are aligned in time and phase and their amplitudes are adjusted, in block 570, the processors 202 (e.g., one or more processors 204) can apply scaling based on the Es / No estimates and power estimates calculated in block 565. For example, a signal with a better signal-to-noise ratio compared to another signal may be assigned a higher weight and scaled accordingly. Similarly, higher Es / No estimates and / or power estimates may be assigned a larger weight and scaled accordingly. Multiple signals (e.g., two signals in this example) can be efficiently scaled and combined by employing SIMD techniques. Block 570 can then sum the signals after all adjustments have been made.

[0105] Blocks 540, 550, and 560 are executed in a specific order as an example, but it will be understood that the embodiments herein are not limited to the example order. Blocks 540, 550, and 560 may be executed in any order as desired and / or in parallel.

[0106] Figure 6 shows an exemplary Post-DM diversity combiner as Method 600. As shown in Figure 6, Method 600 receives input samples from multiple antenna feeds, combines and synthesizes them, and outputs a synthesized signal, in substantially the same manner as the method in Figure 5.

[0107] Method 600 includes the same blocks as Method 5, which are configured to perform substantially the same functions, but are performed in the order shown in Figure 6. For example, Method 600 includes a timing recovery block 510, a carrier recovery block 520, one or more correlator blocks 530, a time adjustment block 540a, a phase rotation block 550, an amplitude adjustment block 560, and one or more combiner blocks 570. Similar to Method 500, Method 600 includes several blocks 510a-510n, blocks 540a-540n, blocks 550a-550n, blocks 565a-565n, and blocks 560a-560n, each block being for performing a function on a sample of multiple signals received through multiple input antenna feeds. Any number of signals are possible, but the examples herein are described with reference to two signals.

[0108] The difference between Method 600 and Method 500 is that Method 600 synthesizes the input signals after timing recovery is performed in Block 510, but before carrier recovery is performed in Block 520 of the demodulator processing chain. Therefore, synthesis is performed during demodulation. For example, as shown in Figure 6, the carrier recovery block 520 is performed on the synthesized signal output from the combiner block 570.

[0109] As described above in relation to Figure 5, the multiple blocks of method 600 each represent a function 306 and may be executed in parallel as one or more functions 306a, 306b, ..., 306n (Figure 3). That is, for example, the correlator block 530 in Figure 6, the weighted combiner block 570 in Figure 6, etc., may be executed in parallel as one or more functions 306a to 306n. Similarly, the multiple blocks shown in Figure 6 can be grouped together as a single "process" (e.g., process 515 and / or 315) that performs a function in a similar manner to the processing blocks 315a, 315b, ..., 315n (Figure 4). That is, for example, for a given signal processing chain, the timing recovery block 510 may be grouped as process 515 (e.g., timing recovery error calculation block 705 and timing recovery block 710), and blocks 540 to 565 may be grouped together as another process 515. Similarly, blocks 570 and 520 in Figure 6 may be grouped together as yet another process 515. Various other combinations are possible. Furthermore, multiple blocks in Figure 6 may be implemented using SIMD processing techniques, as described throughout this disclosure.

[0110] Figures 5 and 6 show two possible high-level examples of Post-D diversity combiner methods, but it will be understood that the embodiments herein are not limited to these two methods, and other methods are also possible. That is, embodiments herein provide a method for executing any function of a diversity combiner as function 306 which is executed in parallel as function 306a to 306n (Figure 3), and / or a method for grouping one or more functions of a diversity combiner as process 315 which is executed in parallel as processing blocks 315a to 315n.

[0111] A channel simulator that employs parallel processing across multiple cores to run on a general-purpose CPU, achieving high-throughput operation in a cloud environment: As described above, Figure 9 is a functional block diagram of an exemplary implementation of Method 900. In various examples, Method 900 may be an example of a channel simulation method. A channel simulator is used to simulate one or more different distortions and / or effects of a transmitter and / or receiver moving in a radio environment. For example, referring to Figure 1, an embodiment of the channel simulator may be used to simulate a transmitter on satellite 111 and / or platform 110 (e.g., an airplane, helicopter, or unmanned aerial vehicle (UAV)) moving relative to a receiver (e.g., one or more of antennas 122, 132, and 142) in that environment. In another example, an embodiment of the channel simulator may be used to simulate a receiver on satellite 111 and / or platform 110 (e.g., an airplane, helicopter, or unmanned aerial vehicle (UAV)) moving relative to a transmitter (e.g., one or more of antennas 122, 132, and 142) in that environment. In yet another example, an embodiment of the channel simulator may be used to simulate a transmitter on satellite 111 and / or platform 110 (e.g., an airplane, helicopter, or unmanned aerial vehicle (UAV)) moving relative to a receiver on satellite 111 and / or platform 110 (e.g., an airplane, helicopter, or unmanned aerial vehicle (UAV)) in that environment.

[0112] The channel simulator method simulates at least one, and possibly all, of the possible environmental effects described above, either due to an imperfect transmitter, environmental effects, or a moving vehicle. Possible transmitter faults that can be simulated include, but are not limited to, phase noise, nonlinear distortion (AM-PM), in-phase / quadrature (I / Q) imbalance, imperfect match filters, and timing jitter. Possible environmental effects include, but are not limited to, rain fade, scintillation, and multipath. Possible motion effects include, but are not limited to, signal center frequency adjustment, time delay adjustment, and power adjustment. The channel simulator can also add additive white Gaussian noise (AWGN), or any other type of noise that the channel may impart to the signal.

[0113] Figure 9 shows an exemplary channel simulator as Method 900. To simulate all necessary channel effects, Method 900 may include one or more functional blocks 910-960 for several operations performed on the signal. For example, in the exemplary example of Figure 9, Method 900 includes one or more of the following: signal distortion block 910, phase noise block 920, center frequency adjustment block 930, timing adjustment block 940, gain adjustment block 950, and additive noise block 960. The functional blocks included in Method 900 may depend on the distortion or effect that is to be simulated. Method 900 may include one, one or more, or all of the blocks 910-960, and in some embodiments, additional blocks may be added to simulate other distortions and / or effects.

[0114] As described above, each of the multiple blocks of method 900 can represent a function and may be implemented as one or more of the functions 306a, 306b, ... 306n (Figure 3). In another example, two or more of the multiple blocks can be grouped together as a single "process" 915 that performs the function in a similar manner to process 315 in Figure 4. That is, the multiple blocks in Figure 9 may be grouped together as process 915 and may be executed in multiple parallel iterations as processing blocks 315a, 315b, ... 315n (Figure 4), etc. For example, as shown in Figure 9, all function blocks 910-960 are grouped into a single process 915, and the grouped functions are replicated into multiple processing blocks 315a-315n. The number of processing blocks 315a-315n can be replicated as many times as desired to achieve the required processing rate and throughput. Although blocks 305, 310, 320, and 325 are not shown in Figure 9, it will be understood that such blocks may exist to take in input data (305), divide it (310), execute process 915 as processing blocks 315a to 315n, and synthesize the resulting processed data (320) and output it for downstream processing (325).

[0115] Figure 9 shows all functional blocks grouped into process 915, but the embodiments herein are not limited thereto. Functional blocks 910-960 can be grouped in many different ways. For example, fewer functional blocks than all of 910-960 (e.g., two or more) can be grouped as a process (e.g., process 915). As an exemplary example, functional blocks 910 and 920 may be grouped together as a first process 915 and distributed and processed over one or more first processing blocks 315a-315n, and functional blocks 930-960 may be grouped together as a second process 915 and distributed and processed over one or more second processing blocks 315a-315n. Furthermore, although blocks 305, 310, 320, and 325 are not shown in Figure 9, it should be understood that such blocks may exist before each process 915 so that they can take in input data (305), divide it (310), execute the grouping function of process 915 (as processing blocks 315a to 315n), and synthesize the resulting processed data (320) and output it for downstream processing (325).

[0116] In various examples, the multiple blocks in Figure 9 may be implemented using SIMD processing techniques, as described throughout this disclosure. SIMD techniques can be shown to improve throughput and minimize memory bandwidth requirements. Increasing the functionality of each processing block executed using SIMD techniques may further minimize memory bandwidth requirements.

[0117] In block 910, the processor 202 (e.g., one or more cores 204) can simulate signal distortion in the input signal. Block 910 can simulate one or more of the following distortions in the input signal: nonlinear distortion (AM-PM), common-mode / quadrature (I / Q) imbalance distortion, scintillation distortion, and multipath distortion, thus simulating signals subjected to such distortions. For example, a complex finite impulse response (FIR) filter can be used to simulate the above distortions, excluding AM-PM distortion. An example of an FIR filter can be implemented using SIMD techniques to improve throughput. The FIR filter coefficients can be set to achieve the simulation of the desired distortion. In the case of AM-PM distortion, nonlinear calculations, such as lookup tables, may be performed on the complex nonlinear calculation.

[0118] In block 920, processor 202 (e.g., one or more cores 204) can simulate phase noise on an input signal. Block 920 can provide a simulation of phase noise to the input signal in order to simulate phase noise. For example, colored noise may be added to the carrier mixed with the input signal. One way to create colored noise is to shape white noise using an FIR filter (which may be the same FIR filter as in block 910 or a different FIR filter) to achieve the desired noise shape. The noise can be created in 10 steps, after creating a bandwidth of 0.1 to 1 Hz, which is then interpolated and added to another stage of noise extending from 1 Hz to 10 Hz. This process can be repeated as many times as needed to cover the required phase noise bandwidth. In each step, SIMD techniques can be used to achieve noise generation, filtering, and interpolation. This colored noise is then used to adjust the phase of either the carrier signal or a complex vector starting from (1,0). This phase-adjusted signal or vector is then multiplied with the input signal, and the phase noise is added to the input signal.

[0119] In block 930, the processor 202 (e.g., one or more cores 204) can perform carrier tuning by adjusting the phase of the input signal over time. Block 930 may be performed in a similar manner to block 920, but in block 930, the phase of the mixed carriers changes over time to achieve the desired carrier frequency and phase tuning. Block 930 may be used to simulate the motion of a moving platform (e.g., platform 110 and / or satellite 111 in Figure 1), or more generally, the change in carrier frequency from the motion of either the transmitter or receiver, known as the Doppler effect.

[0120] In block 940, the processor 202 (e.g., one or more cores 204) can perform timing adjustments to simulate the effect of a moving platform (e.g., platform 110 and / or satellite 111). For example, such motion may lengthen or lengthen the input signal over time. Block 940 can apply a polyphase filter using adjustable delay taps. Block 940 may be similar to the timing-adjusted block 540 in Figures 5 and 6, but instead of the result of analyzing the input signal, the timing information of block 940 is driven by user input to simulate the desired effect.

[0121] In block 950, the processor 202 (e.g., one or more cores 204) can perform gain adjustments to simulate rainfall fade or other effects that may affect signal power. Block 950 can be performed by multiplying the amplitude of the input signal.

[0122] In block 960, the processor 202 (e.g., one or more cores 204) can add noise to the input signal. For example, block 960 can simulate additive Gaussian white noise (or any type of noise (e.g., a colored distribution like Rayleigh or other types of distributions)) and add that noise to the input signal. There are many ways to generate Gaussian white noise, and the Box-Muller method is one known in the art.

[0123] Blocks 910–960 are shown in a specific order, but it will be understood that the embodiments herein are not limited to the order shown. Blocks 910–960 may be executed in any order as desired and / or in parallel with the input signals.

[0124] A signal modulator that employs parallel processing across multiple cores to run on a general-purpose CPU, achieving high-throughput operation in a cloud environment: As described above, Figure 10 is a functional block diagram of an exemplary implementation of Method 1000. In various examples, Method 1000 may be an example of a signal modulation method. A modulator can be used to generate a waveform and transmit information from one point to another. For example, a downlink signal (e.g., downlink signals 160 and / or 170 in Figure 1) may be modulated according to Method 1000. For example, the information may be divided into digital information or into analog signals, such as those used in AM and FM radio. Although the generation of a digital signal is used as an example herein, the same approach can also be used to generate an analog signal.

[0125] Figure 10 shows an exemplary signal modularizer as Method 1000. Method 1000 is a phase-shift keying (PSK) modulator method that supports modulation types such as B / Q / SQ / 8 / 16A / 32APSK / , quadrature amplitude modulation (QAM), or any similar digital modulation waveform. While Figure 10 shows one exemplary modulation method, the same approach to signal processing (e.g., as described in Figures 3 and 4) can be applied to other modulation methods.

[0126] Method 1000 includes a plurality of functional blocks, as shown in Figure 10. For example, in the exemplary example in Figure 10, Method 1000 includes one or more of the following: frame builder block 1010, forward error correction (FEC) block 1020, pulse shaper block 1030, center frequency adjustment block 1040, and sweeper block 1050.

[0127] While specific blocks and configurations are shown in Figure 10, different blocks may be required for specific modulation schemes. Therefore, Figure 10 illustrates a high-level modulation method and is not a catch-all configuration. One or more additional functional blocks can be added to Method 1000 as needed to implement different modulation schemes. Unless a specific modulation scheme is included in the configuration of Figure 10, those skilled in the art will understand that the concepts disclosed throughout this disclosure in relation to various embodiments are equally applicable to all modulation schemes, not just the modulation method of Figure 10.

[0128] As described above, each of the multiple blocks of method 1000 can represent a function and may be implemented as one or more of the functions 306a, 306b, ... 306n (Figure 3). In another example, two or more of the multiple blocks can be grouped together as a single "process" 1015 that performs the function in a similar manner to process 315 in Figure 4. That is, the multiple blocks in Figure 10 can be grouped together as process 1015 and may be executed in multiple parallel iterations as processing blocks 315a, 315b, ... 315n (Figure 4), etc. For example, as shown in Figure 10, function blocks 1010 and 1020 can be grouped together as a first process 1015, then replicated by multiple first processing blocks 315a to 315n, function blocks 1030 to 1050 can be grouped together as a second process 315, then replicated by multiple second processing blocks 315a to 315n. Figure 10 shows a specific functional block grouped into a separate process 1015, but the embodiments herein are not limited thereto. Functional blocks 1010-1050 can be grouped in many different ways. For example, all functional blocks 1010-1050 can be grouped together.

[0129] Method 10 also exemplary includes a data acquisition block 1005 and a data partitioning block 1010 before each process 1015. Each data acquisition block 1005 may be substantially similar to a data acquisition block 305 (Figure 4), and each data partitioning block 1010 may be substantially similar to a data partitioning block 310 (Figure 4). Thus, input data can be acquired (1005), the data can be received and processed by the processor 202 and partitioned (1010), and the data can be parsed by the processor 202 into overlapping data blocks, for example, as described in relation to Figure 4. Furthermore, after each process 1015, Method 10 also exemplary includes a data synthesis block 1020 and a data output block 1025. Each data synthesis block 1020 may be substantially similar to a data synthesis block 320 (Figure 4), and each data output block 1025 may be substantially similar to a data output block 325 (Figure 4). Therefore, process 1015 outputs and synthesizes duplicate data blocks (1020), as described in relation to Figure 4, for example, and outputs the resulting data (1025).

[0130] In various examples, the multiple blocks in Figure 10 may be implemented using SIMD processing techniques, as described throughout this disclosure. SIMD techniques can be shown to improve throughput and minimize memory bandwidth requirements. Increasing the functionality of each processing block executed using SIMD techniques may further minimize memory bandwidth requirements.

[0131] In block 1010, the processor 202 (e.g., one or more cores 204) can convert incoming data of an input signal into a predetermined format based on a desired modulation scheme (e.g., the modulation scheme of receivers such as antennas 122, 132, and / or 134). For example, a particular modulation scheme requires a particular format, and block 1010 converts the data of the input signal into that format. The modulator method 1000 can support many different waveform standards, including, but not limited to, DVB-S2, DVB-S2x, as well as less standardized cases using Reed-Solomon coding, turbo coding, convolutional coding, etc. For brevity, the waveform standards are grouped into two cases: streaming data and frame data. The streaming data case is when the incoming data is uncoded or is a continuous, uninterrupted stream, such as convolutional coding. Frame data is for incoming data that requires frame data or data blocks, such as DVB-S2 or Reed-Solomon. Block 1010 can construct frames (e.g., in the case of frame data) or data streams (e.g., in the case of streaming data) by converting incoming data into a format that corresponds to the modulation scheme.

[0132] In block 1020, the processor 202 (e.g., one or more cores 204) generates coding corresponding to the modulation schemes of method 1010, including but not limited to BCH and LDPC coding for DVB-S2, LDPC coding for CCSDS, Reed-Solomon, turbo coding, polar coding, and convolutional coding. Block 1020 may be one of the more complex blocks of modulation method 1000 and therefore can benefit from all of the signal processing methods (e.g., Figures 3 and / or 4) and SIMD techniques disclosed throughout this disclosure.

[0133] In block 1030, the processor 202 (e.g., one or more cores 204) converts symbolic data into samples, for example, by applying a pulse shaping filter. Block 1030 can create any pulse shape, for example, a root-raised cosine (RRC). The pulse shaper may be a combination of a multiphase filter and a numerically controlled oscillator (NCO). Block 1030 can also be a complex block and therefore can benefit from all of the signal processing methods (e.g., Figures 3 and / or 4) and SIMD techniques disclosed throughout this disclosure.

[0134] In block 1040, the processor 202 (e.g., one or more cores 204) can change the center frequency of the carrier of the sample data from block 1030 using complex multiplication. In block 1040, the processor 202 (e.g., one or more cores 204) can change the phase and frequency over time based on a predetermined profile corresponding to the modulation scheme. In some implementations, block 1050 is executed while the center frequency is being adjusted by block 1040.

[0135] Other aspects The attached claims and their equivalents are intended to encompass forms or modifications that fall within the scope of this disclosure. The various components shown in the figures may, for example, be implemented as software and / or firmware on a processor or dedicated hardware, but are not limited thereto. Furthermore, features and attributes of the particular exemplary embodiments disclosed above may be combined in various ways to form additional embodiments, all of which are within the scope of this disclosure.

[0136] The above-described method and process flow diagrams are provided merely as illustrative examples and are not intended to require or imply that the operations of the various embodiments must be performed in the order presented. As those skilled in the art will understand, the order of operations in the above-described embodiments can be performed in any order. Words such as “then,” “next,” and “the following” are not intended to restrict the order of operations, and these words are used merely to guide the reader through the description of the method. Furthermore, any reference to an element of a claim using the singular form and articles such as “a,” “an,” or “the” should not be construed as limiting the element to the singular form.

[0137] The operation of various exemplary logic blocks, modules, and algorithms described in connection with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly demonstrate this hardware and software compatibility, the diverse exemplary components, blocks, modules, and operations are generally described above in terms of their functionality. Whether such functionality is implemented as hardware or as software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art will be able to implement the described functionality in various ways for each specific application, but such determination of embodiments should not be construed as resulting in a departure from the scope of the concept of the present invention.

[0138] The diverse exemplary logic, logic blocks, and modules described in relation to the various embodiments disclosed herein can be implemented or run by a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof intended to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of receiving devices, such as a DSP and a microprocessor, multiple microprocessors, one or more microprocessors working in conjunction with a DSP core, or any other combination thereof. Alternatively, some operations or methods may be performed by circuits dedicated to a given function.

[0139] In one or more exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions or codes on a non-temporary computer-readable storage medium or a non-temporary processor-readable storage medium. The operation of any method or algorithm disclosed herein may be embodied in processor-executable instructions that may reside on a non-temporary computer-readable storage medium or a processor-readable storage medium. A non-temporary computer-readable storage medium or a processor-readable storage medium may be any storage medium accessible by a computer or processor. Such non-temporary computer-readable storage mediums or processor-readable storage media may include, but are not limited to, random-access memory (RAM), read-only memory (ROM), electrically erasable and programmable read-only memory (EEPROM), flash memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium accessible by a computer that can be used to store desired program code in the form of instructions or data structures. The terms "Disk" and "disc" as used herein include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs. These discs typically reproduce data magnetically, while discs reproduce data optically by a laser. The above combinations also fall within the scope of non-temporary computer-readable media and processor-readable media. Furthermore, the operation of a method or algorithm may reside in non-temporary processor-readable storage media and / or computer-readable storage media, which may be incorporated into a computer program product as one or any combination or set of code and / or instructions.

[0140] It is understood that the specific order or hierarchy of blocks in the disclosed process / flowchart is illustrative of an exemplary approach. It is understood that the specific order or hierarchy of blocks in the process / flowchart can be rearranged based on design preferences. Also, some blocks may be combined or omitted. The claims of the attached method present various block elements in a sample order and are not intended to be limited to the specific order or hierarchy presented.

[0141] The preceding description is provided to enable those skilled in the art to carry out the various embodiments described herein. Various modifications of these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments.

[0142] Accordingly, the claims are not intended to be limited to the embodiments shown herein, but rather to be the full scope corresponding to the language of the claims, and references to singular elements are not intended to mean "one" unless explicitly stated so, but rather to mean "one or more".

[0143] The term “exemplary” is used herein to mean “serving as an example, illustration, or representation.” No aspect described herein as “exemplary” should be construed as necessarily preferable or more advantageous than any other aspect. Unless otherwise specified, the term “several” refers to one or more.

Claims

1. A method for synthesizing multiple downlink signals representing communication signals, wherein the method is Receiving samples of the multiple downlink signals from multiple antenna feeds, A first symbol for the first signal is generated based on performing a first timing recovery operation on the first sample of the first signal among the plurality of downlink signals, A second symbol for the second signal is generated based on performing a second timing recovery operation on the second sample of the second signal among the plurality of downlink signals, Based on performing correlator operations on the first and second symbols, time and phase offset information is generated, The first signal is divided into multiple first data packets, The second signal is divided into multiple second data packets, (i) combining the first and second signals based on the first and second symbols, (ii) aligning the timing and phase of the first symbol with the second symbol based on the time and phase offset information, and (iii) performing a weighted combiner operation that applies scaling to each of the first and second data packets based on the corresponding signal quality, Includes, A method wherein at least one of the first timing recovery operation, the second timing recovery operation, the correlator operation, and the synthesis is performed in a plurality of processing blocks within one or more processors, and the first processing block and the second processing block among the plurality of processing blocks operate in parallel.

2. The method according to claim 1, wherein the plurality of processing blocks include a plurality of central processing unit (CPU) cores.

3. The method according to claim 1 or 2, wherein the one or more processors include a plurality of processors, one or more first processing blocks among the plurality of processing blocks are included in the first processor among the plurality of processors, and one or more second processing blocks among the plurality of processing blocks are included in the second processor among the plurality of processors.

4. The method according to claim 1 or 2, wherein the one or more processors include a single processor having one or more first processing blocks from the plurality of processing blocks and one or more second processing blocks from the plurality of processing blocks.

5. The method according to any one of claims 1 to 4, wherein the first timing recovery operation is performed in the plurality of processing blocks, the plurality of processing blocks include at least a first processing block and a second processing block, the first processing block performs the first timing recovery operation in the first part of the first sample, the second processing block performs the first timing recovery operation in the second part of the first sample, and the first processing block and the second processing block operate in parallel.

6. The aforementioned multiple processing blocks are, A first processing block that performs at least one of the first timing recovery operation, the second timing recovery operation, the correlator operation, and the synthesis, A second processing block that performs at least one of the first timing recovery operation, the second timing recovery operation, the correlator operation, and the synthesis, Includes, The method according to any one of claims 1 to 5, wherein the first processing block and the second processing block operate in parallel.

7. Based on performing a first carrier recovery operation on the first symbol, a corrected first symbol is generated, Based on performing a second carrier recovery operation on the aforementioned second symbol, a corrected second symbol is generated, The method according to any one of claims 1 to 6, further comprising:

8. The plurality of processing blocks execute the first timing recovery operation and the first carrier recovery operation, and the plurality of processing blocks The first portion of the first sample includes a first processing block that performs the first timing recovery operation and the first carrier recovery operation, The second part of the first sample includes a second processing block that performs the first timing recovery operation and the first carrier recovery operation, The method according to claim 7, comprising at least the following:

9. The method according to claim 7, wherein the plurality of processing blocks include one or more first processing blocks that perform the first timing recovery operation and the first carrier recovery operation, and one or more second processing blocks that perform the second timing recovery operation and the second carrier recovery operation.

10. The method according to claim 7, wherein the plurality of processing blocks include one or more first processing blocks that perform the first timing recovery operation and the first carrier recovery operation, and one or more second processing blocks that perform the second timing recovery operation and the second carrier recovery operation.

11. The first timing recovery operation and the first carrier recovery operation are part of the first match filtering, The second timing recovery operation and the second carrier recovery operation are part of the second match filtering. The method according to claim 7.

12. The method according to any one of claims 1 to 6, further comprising generating corrected symbols based on performing a carrier recovery operation on the combined first and second signals.

13. The first timing recovery operation, the second timing recovery operation, and the carrier recovery operation are all part of the match filtering process. The method according to claim 12.

14. The method according to any one of claims 1 to 13, wherein the one or more processors are one or more general-purpose central processing units (CPUs).

15. The method according to any one of claims 1 to 14, wherein the one or more processors employ single instruction multiple data (SIMD) technology to achieve high throughput.

16. A system for synthesizing multiple downlink signals representing communication signals, wherein the system is Multiple antennas configured to receive the aforementioned multiple downlink signals, One or more processors communicably coupled to the plurality of antennas, wherein the one or more processors have a plurality of processing blocks and are operable to perform the method according to any one of claims 1 to 15, A system that includes this.

17. A device for synthesizing multiple downlink signals representing communication signals, wherein the device is Means for receiving samples of the multiple downlink signals from multiple antenna feeds, Means for generating a first symbol for the first signal, based on performing a first timing recovery operation on the first sample of the first signal of the plurality of downlink signals, Means for generating a second symbol for the second signal, based on performing a second timing recovery operation on the second sample of the second signal of the plurality of downlink signals, Means for generating time and phase offset information based on performing correlator operations on the first symbol and the second symbol, Means for dividing the first signal into multiple first data packets, Means for dividing the second signal into multiple second data packets, Means for combining the first signal and the second signal, based on (i) the first symbol and the second symbol, (ii) aligning the timing and phase of the first symbol with the second symbol based on the time and phase offset information, and (iii) performing a weighted combiner operation that applies scaling to each of the first data packets and the second data packets based on the corresponding signal quality, Includes, An apparatus in which at least one of the means for generating the first symbol, the means for generating the second symbol, the means for generating the time and phase offset information, and the means for synthesis is performed in a plurality of processing blocks within one or more processors, and the first processing block and the second processing block among the plurality of processing blocks operate in parallel.

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