Comparator circuit and power supply

The comparator circuit design equalizes input terminal voltages using PMOS or NMOS transistors as differential pairs to prevent NBTI or PBTI degradation, maintaining stable transistor characteristics in standby modes.

JP7876004B2Active Publication Date: 2026-06-18NISSHINBO MICRO DEVICES INC
6 Cites 0 Cited by

Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
NISSHINBO MICRO DEVICES INC
Filing Date
2023-01-31
Publication Date
2026-06-18

AI Technical Summary

⚠Technical Problem

Conventional comparator circuits using PMOS or NMOS transistors as differential pairs are susceptible to NBTI or PBTI degradation due to input potential differences, particularly in standby modes, which cannot be effectively suppressed.

⚗Method used

A comparator circuit design that uses PMOS or NMOS transistors as differential pairs, incorporating a control circuit to equalize input terminal voltages during standby states, thereby preventing NBTI or PBTI degradation.

🎯Benefits of technology

The proposed design effectively suppresses NBTI or PBTI in comparator circuits by maintaining equal input voltages, ensuring stable transistor characteristics regardless of potential differences.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

A comparator circuit (2) according to the present invention comprises a comparator (5) which detects an abnormal voltage of a secondary battery (1) and uses a PMOS transistor or an NMOS transistor as a differential pair. The comparator circuit (2) comprises a control circuit (3) that provides such control that voltages of two input terminals of the comparator (5) are equal to each other in a standby state in which an operation of the comparator circuit (2) is in a stop state.
Need to check novelty before this filing date? Find Prior Art