Frequency synchronization circuit and oscillator circuit

Abstract

To suppress a power consumption and a phase noise in an oscillation circuit.SOLUTION: A frequency synchronization circuit according to an embodiment comprises: a first switched-capacitor circuit; a current source; and a frequency feedback circuit. The first switched-capacitor circuit generates a first impedance corresponded to a reference period signal of an input reference frequency. The current source generates a reference current in accordance with the first impedance. The frequency feedback circuit contains: a voltage control oscillation circuit; a second switched-capacitor circuit; and a voltage difference detection circuit, and generates an output signal that is synchronized to a frequency to the reference frequency. The voltage control oscillation circuit outputs the output signal of the reference frequency in accordance with a control voltage. The second switched-capacitor circuit is connected in a cascode to the first switched-capacitor circuit, and generates a second impedance in accordance with the output signal. The voltage difference circuit generates the control voltage in accordance with the reference current and the second impedance.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present specification relate to a frequency synchronization circuit and an oscillation circuit.

Background Art

[0002] Conventionally, as an oscillation circuit that obtains a desired output frequency by oscillating a crystal oscillator, a thermostatic chamber type crystal oscillator (Oven Controlled crystal Oscillator: OCXO) and a voltage controlled crystal oscillator (Voltage-Controlled Crystal Oscillator: VCXO) are known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Generally, the output frequency from a crystal oscillator has temperature dependence. However, in an OCXO, there is a problem that power consumption is large because the temperature of the crystal oscillator is maintained using a thermostatic chamber to suppress changes in the output frequency. Also, in a VCXO, while power consumption is smaller than that of an OCXO because it can output a frequency corresponding to the input of a control voltage without using a thermostatic chamber, there is a problem that phase noise is large.

[0005] An object of the present invention has been made in view of the above, and is to suppress power consumption and phase noise in an oscillation circuit.

Means for Solving the Problems

[0006] To solve the above-mentioned problems and achieve the objective, the frequency synchronization circuit according to the embodiment comprises a first switched-capacitor circuit, a current source, and a frequency feedback circuit. The first switched-capacitor circuit is configured to generate a first impedance by charging and discharging a capacitive element in accordance with a reference period signal of an input reference frequency. The current source is electrically connected to the first switched-capacitor circuit and is configured to generate a reference current corresponding to the first impedance using an input first reference voltage. The frequency feedback circuit includes a voltage-controlled oscillator circuit, a second switched-capacitor circuit, and a voltage difference detection circuit and is configured to generate an output signal of the output frequency that is frequency-synchronized to the reference frequency. The voltage-controlled oscillator circuit is configured to output an output signal having an output frequency corresponding to a control voltage. The second switched-capacitor circuit is cascode-connected to the first switched-capacitor circuit and electrically connected to the current source, and is configured to generate a second impedance by charging and discharging a capacitive element in accordance with the output signal, and to generate a voltage corresponding to the second impedance using the reference current. The voltage difference detection circuit is electrically connected to the second switched-capacitor circuit and the voltage-controlled oscillation circuit, and is configured to generate the control voltage according to the difference between the voltage corresponding to the second impedance and the input second reference voltage. [Effects of the Invention]

[0007] According to the present invention, power consumption and phase noise in the oscillation circuit can be suppressed. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows an example of the configuration of an oscillator circuit according to an embodiment. [Figure 2] Figure 2 illustrates the voltage control performed by the control circuit in Figure 1, which is controlled according to the temperature characteristics of the crystal oscillator. [Figure 3]Figure 3 shows an example of the phase noise characteristics of the frequency-locked circuit shown in Figure 1. [Modes for carrying out the invention]

[0009] The following describes in detail embodiments of a frequency synchronization circuit and an oscillator circuit incorporating the frequency synchronization circuit, with reference to the drawings. In the following embodiments, parts with the same reference numerals perform the same operation, and redundant explanations will be omitted as appropriate. In the following embodiments, "connection" means "electrical connection".

[0010] Figure 1 shows an example of the configuration of an oscillator circuit 1 according to an embodiment. As shown in Figure 1, the oscillator circuit 1 according to the embodiment has a reference oscillator circuit 3 and a frequency synchronization circuit 5.

[0011] The reference oscillator circuit 3 includes a crystal oscillator circuit 31 and a crystal oscillator with a built-in temperature sensor. The crystal oscillator with a built-in temperature sensor includes a crystal oscillator 32, a temperature sensor 33, and a substrate 34. In the crystal oscillator with a built-in temperature sensor, the crystal oscillator 32 and the temperature sensor 33 are mounted on the same substrate 34. In other words, the temperature sensor is formed on the same substrate 34 as the crystal oscillator 32. That is, the temperature sensor 33 is configured to measure the temperature of the crystal oscillator 32 or its surroundings via the substrate 34. Any temperature sensor, such as a thermocouple or thermistor, can be used as the temperature sensor 33.

[0012] The reference oscillator circuit 3 is supplied with a fixed-level bias voltage (e.g., power supply voltage VDD) and is configured to oscillate in accordance with the bias voltage to generate a reference frequency FREF signal (periodic signal). Specifically, the crystal oscillator circuit 31 is connected to a crystal resonator 32 and is configured to oscillate the crystal resonator 32 using a fixed-level bias voltage, thereby generating a reference frequency FREF signal through the oscillation of the crystal resonator 32. The reference oscillator circuit 3 only needs to be able to generate a reference frequency FREF signal, and preferably uses the oscillation of a crystal resonator, but other oscillator circuits may also be used. In that case, the voltage values ​​of the reference voltage VREF1 and reference voltage VREF2 should be controlled according to the temperature dependence of the output frequency from the other oscillator circuit.

[0013] In the reference oscillator circuit 3, the output node 31b of the crystal oscillator circuit 31 is connected to the clock node 51c of the control circuit 51 and the input node 52a of the first frequency divider circuit 52, respectively. The reference oscillator circuit 3 is configured to supply a signal of the generated reference frequency FREF to the control circuit 51 and the first frequency divider circuit 52, respectively.

[0014] The frequency synchronization circuit 5 includes a control circuit 51, a first frequency divider circuit 52, a first switched-capacitor circuit 53, a current source 54, a second frequency divider circuit 55, a second switched-capacitor circuit 56, a voltage difference detection circuit 57, and a voltage-controlled oscillator (VCO) 58.

[0015] The control circuit 51 is connected to the reference oscillator circuit 3, the current source 54, and the voltage difference detection circuit 57, respectively. The control circuit 51 has an input node 51a connected to the temperature sensor 33, one of a pair of output nodes 51b connected to the control node 54c of the current source 54, the other of the pair of output nodes 51b connected to the control node 57c of the voltage difference detection circuit 57, and a clock node 51c connected to the output node 31b of the crystal oscillator circuit 31 and the input node 52a of the first frequency divider circuit 52. The control circuit 51 is configured to control the voltage values ​​of the reference voltage VREF1 and reference voltage VREF2 based on the signal from the temperature sensor 33, the reference frequency FREF signal, and the frequency-temperature characteristics of the crystal oscillator 32.

[0016] The first frequency divider circuit 52 is connected between the reference oscillator circuit 3 and the first switched-capacitor circuit 53. One of the pair of output nodes 52b of the first frequency divider circuit 52 is connected to the control terminal of switch 533 of the first switched-capacitor circuit 53, and the other is connected to the control terminal of switch 534. The first frequency divider circuit 52 is configured to divide the reference frequency FREF signal generated by the reference oscillator circuit 3 by 2 and supply the divided signal to each switch 533, 534 so that each switch 533, 534 turns on and off complementaryly. In other words, the first frequency divider circuit 52 is configured to shape the duty cycle of the reference frequency FREF signal oscillated out by the reference oscillator circuit 3 to 50:50 and supply it to the first switched-capacitor circuit 53.

[0017] In the following explanation, a signal with reference frequency FREF will be referred to as the reference period signal, and a divided reference frequency signal, i.e., a signal with frequency FREF / 2, may also be referred to as the divided reference signal.

[0018] The first switched-capacitor circuit 53 is connected between the first frequency divider circuit 52 and the current source 54. The first switched-capacitor circuit 53 is a circuit configured to limit current or voltage like a resistor by combining a switch and a capacitive element. The first switched-capacitor circuit 53 is configured to generate a first impedance corresponding to the frequency divider reference signal by charging and discharging the capacitive element in accordance with the frequency divider reference signal from the first frequency divider circuit 52. In other words, the first switched-capacitor circuit 53 is an example of a frequency-impedance conversion circuit that converts the frequency FREF / 2 of the input frequency divider reference signal to a first impedance. Here, the first switched-capacitor circuit 53 is connected to the output node 31b of the crystal oscillator circuit 31 via the first frequency divider circuit 52. From this, it can be said that the first switched-capacitor circuit 53 is configured to generate a first impedance by charging and discharging the capacitive element in accordance with the reference periodic signal.

[0019] Specifically, the first switched-capacitor circuit 53 has capacitive elements 531, 532 and switches 533, 534, as shown in Figure 1. Switches 533 and 534 are connected in series between the power supply potential VDD and the input node 54a of the current source 54. One end of switch 533, opposite to switch 534, is connected to the power supply potential VDD. The other end of switch 534, opposite to switch 533, is connected to the input node 54a of the current source 54 via the output node 53b of the first switched-capacitor circuit 53. Capacitive element 531 has one end connected to the power supply potential VDD and the other end connected to node 535 between switches 533 and 534. In other words, capacitive element 531 is connected in parallel with switch 533 between the power supply potential VDD and node 535. Capacitive element 532 has one end connected to the power supply potential VDD and the other end connected to output node 53b. In other words, the capacitive element 532 is connected in parallel with switches 533 and 534 between the power supply potential VDD and the output node 53b.

[0020] The current source 54 is connected between the first switch capacitor circuit 53 and the voltage difference detection circuit 57. The input node 54a of the current source 54 is connected to the output node 53b of the first switch capacitor circuit 53, the output node 54b is connected to the input node 57a of the voltage difference detection circuit 57 and the output node 56b of the second switch capacitor circuit 56, and the control node 54c is connected to the output node 51b of the control circuit 51. Specifically, the current source 54 is configured to generate a current corresponding to the first impedance, that is, a current IREF2 corresponding to the reference frequency FREF, using the reference voltage VREF1 input from the control circuit 51. The current source 54 supplies the current IREF2 to the input node 57a of the voltage difference detection circuit 57. Here, the reference voltage VREF1 is an example of the first reference voltage. Also, the current IREF2 is an example of the reference current.

[0021] As an example, as shown in FIG. 1, the current source 54 includes a transistor 541 and a differential amplifier circuit 542. The transistor 541 is connected between the input node 54a and the output node 54b. The transistor 541 is, for example, an NMOS transistor, with its source connected to the output node 54b, its drain connected to the input node 54a, and its gate connected to the output terminal of the differential amplifier circuit 542. The non-inverting input terminal (+) of the differential amplifier circuit 542 is connected to the input node 54a, and the inverting input terminal (-) is connected to the output node 51b of the control circuit 51. The reference voltage VREF1 from the output node 51b of the control circuit 51 is supplied to the inverting input terminal (-) of the differential amplifier circuit 542.

[0022] The second frequency divider circuit 55 is connected between the second switch capacitor circuit 56 and the voltage-controlled oscillator circuit 58. One of the pair of output nodes 55b of the second frequency divider circuit 55 is connected to the control terminal of the switch 563 of the second switch capacitor circuit 56, and the other is connected to the control terminal of the switch 564. The second frequency divider circuit 55 divides the signal of the output frequency FOUT generated by the voltage-controlled oscillator circuit 58 by two, and is configured to supply the divided signal to each of the switches 563 and 564 so that each of the switches 563 and 564 is turned on and off complementarily. That is, the second frequency divider circuit 55 is configured to shape the duty ratio of the signal of the output frequency FOUT oscillated and output by the voltage-controlled oscillator circuit 58 to 50:50 and supply it to the second switch capacitor circuit 56.

[0023] In the following description, the signal of the output frequency FOUT may be described as an output signal, and the divided signal of the output frequency FOUT, that is, the signal of the frequency FOUT / 2 may be described as a divided output signal.

[0024] The second switch capacitor circuit 56 is connected between the second frequency divider circuit 55 and the voltage difference detection circuit 57. Also, the second switch capacitor circuit 56 is cascode-connected to the first switch capacitor circuit. The second switch capacitor circuit 56 is a circuit configured to limit current or voltage like a resistor by combining a switch and a capacitive element. The second switch capacitor circuit 56 is configured to charge and discharge the capacitive element according to the divided output signal from the second frequency divider circuit 56 to generate a second impedance corresponding to the divided output signal. That is, the second switch capacitor circuit 56 is an example of a frequency-impedance conversion circuit that converts the frequency FOUT / 2 of the input divided output signal into a second impedance. Here, the second switch capacitor circuit 56 is connected to the output node 58b of the voltage-controlled oscillator circuit 58 via the second frequency divider circuit 55. From this, it can be expressed that the second switch capacitor circuit 56 is configured to generate a second impedance by charging and discharging the capacitive element according to the output signal.

[0025] Specifically, the second switched-capacitor circuit 56 has capacitive elements 561, 562 and switches 563, 564, as shown in Figure 1. Switches 563, 564 are connected in series between the output node 57b of the voltage difference detection circuit 57 and the power supply potential VSS. One end of switch 563 opposite to switch 564 is connected to the output node 57b of the voltage difference detection circuit 57 via the output node 56b of the second switched-capacitor circuit 56. The other end of switch 564 opposite to switch 563 is connected to the power supply potential VSS. Capacitive element 561 has one end connected to node 565 between switches 563, 564 and the other end connected to the power supply potential VSS. In other words, capacitive element 561 is connected in parallel with switch 564 between node 565 and the power supply potential VSS. Capacitive element 562 has one end connected to the output node 56b and the other end connected to the power supply potential VSS. In other words, the capacitive element 562 is connected in parallel with switches 563 and 564 between the output node 56b and the power supply potential VSS.

[0026] The voltage difference detection circuit 57 is connected between the current source 54 and the second switched-capacitor circuit 56. The voltage difference detection circuit 57 is also connected between the second switched-capacitor circuit 56 and the voltage-controlled oscillator circuit 58. The input node 57a of the voltage difference detection circuit 57 is connected to the output node 57b and the output node 54b of the current source 54; the output node 57b is connected to the output node 56b of the second switched-capacitor circuit 56; the control node 57c is connected to the output node 51b of the control circuit 51; and the output node 57d is connected to the input node 58a of the voltage-controlled oscillator circuit 58. The voltage difference detection circuit 57 receives a reference voltage VREF2 at the control node 57c and generates a voltage VREF_R at the output node 57b using the current source 54 and the second switched-capacitor circuit 56. In other words, the voltage difference detection circuit 57 is configured to generate a control voltage VC according to the difference between the voltage VREF_R corresponding to the second impedance and the reference voltage VREF2. Specifically, the voltage difference detection circuit 57 generates a control voltage VC to control the difference between the reference voltage VREF2 and the voltage VREF_R to be small, and outputs it from the output node 57d. Here, the reference voltage VREF2 is an example of a second reference voltage.

[0027] As an example, the voltage difference detection circuit 57 has a differential amplifier circuit 572, as shown in Figure 1. The differential amplifier circuit 572 has a non-inverting input terminal (+) connected to the control node 57c, an inverting input terminal (-) connected to the input node 57a and the output node 57b, and an output terminal connected to the output node 57d. The differential amplifier circuit 572 generates a control voltage VC corresponding to the difference between the reference voltage VREF2 and the voltage VREF_R.

[0028] The voltage-controlled oscillator circuit 58 is connected between the voltage difference detection circuit 57 and the second frequency divider circuit 55. The input node 58a of the voltage-controlled oscillator circuit 58 is connected to the output node 57d of the voltage difference detection circuit 57, and the output node 58b is connected to the input node 55a of the second frequency divider circuit 55. The voltage-controlled oscillator circuit 58 is configured to output an output signal having an output frequency FOUT corresponding to the control voltage VC from the voltage difference detection circuit 57. Specifically, the voltage-controlled oscillator circuit 58 oscillates in response to the control voltage VC and generates an output signal with a frequency FOUT corresponding to the control voltage VC.

[0029] The output node of the oscillator circuit 1 is connected between the output node 58b of the voltage-controlled oscillator circuit 58 and the input node 55a of the second frequency divider circuit 55.

[0030] Here, an example of the operation of the oscillator circuit 1 according to the embodiment will be described.

[0031] The reference oscillator circuit 3 generates a reference period signal with a reference frequency FREF by oscillating according to the power supply voltage VDD, for example, and supplies it to the first frequency divider circuit 52. The first frequency divider circuit 52 divides the reference period signal from the reference oscillator circuit 3 by 2 and supplies a divided reference signal with a frequency of FREF / 2 to the switches 533 and 534 of the first switched-capacitor circuit 53.

[0032] In the first switched-capacitor circuit 53, switches 533 and 534 are switched on and off complementaryly according to the level of the frequency division reference signal. This causes the capacitive element 531 to be charged and discharged. For example, when switch 533 is ON and switch 534 is OFF, the charge (electrons) of the capacitive element 531 is discharged to the power supply potential VDD, and the capacitive element 531 is discharged. For example, when switch 533 is OFF and switch 534 is ON, the charge (electrons) corresponding to the current IREF1 flowing through the input node 54a of the current source 54 is accumulated in the capacitive element 531, and the capacitive element 531 is charged. At this time, the capacitive element 532 maintains a state in which it has accumulated a charge corresponding to the current IREF1 flowing through the input node 54a of the current source 54, regardless of the level of the frequency division reference signal.

[0033] In other words, the first switched-capacitor circuit 53 periodically charges and discharges the capacitive element 531 using a frequency-divided reference signal having a frequency FREF / 2 based on a reference frequency FREF, thereby generating a first impedance equivalent to the frequency FREF / 2 of the frequency-divided reference signal. At this time, the voltage VREF_S at the output node 53b of the first switched-capacitor circuit 53 changes time-dependently when the capacitive element 531 is being charged, but it converges to a stable point while being averaged by the capacitive element 532 that maintains the accumulation of charge. At the stable point, the voltage VREF_S at the output node 53b (input node 54a) is controlled by the current source 54 to be equal to the reference voltage VREF1. Specifically, in the feedback loop formed by the transistor 541 and the differential amplifier circuit 542, the differential amplifier circuit 542 controls the gate voltage of the transistor 541 so that the voltage VREF_S is equal to the reference voltage VREF1.

[0034] Therefore, at the output node 54b of the current source 54 at the stable point, a current IREF2 corresponding to VREF1 is generated. Furthermore, current IREF2 is equal to current IREF1, depends on the first impedance generated in the first switched-capacitor circuit 53, and corresponds to the frequency division reference signal.

[0035] The second frequency divider circuit 55 divides the output signal FOUT from the voltage-controlled oscillator circuit 58 by 2, and supplies the divided output signal with frequency FOUT / 2 to the switches 563 and 564 of the second switched-capacitor circuit 56.

[0036] In the second switched-capacitor circuit 56, switches 563 and 564 are switched on and off complementaryly according to the level of the divided output signal. This causes the capacitive element 561 to be charged and discharged. For example, when switch 564 is on and switch 563 is off, the charge (electrons) of the capacitive element 561 is discharged to the power supply potential VSS, and the capacitive element 561 is discharged. For example, when switch 564 is off and switch 563 is on, the charge (electrons) corresponding to the current IREF2 generated by the current source 54 according to VREF1 is accumulated in the capacitive element 561, and the capacitive element 561 is charged. At this time, the capacitive element 562 maintains a state in which it has accumulated a charge corresponding to the current IREF2, regardless of the level of the divided output signal.

[0037] In other words, the second switched-capacitor circuit 56 periodically charges and discharges the capacitive element 561 using a frequency-divided output signal having a frequency FOUT / 2 based on the output frequency FOUT, thereby generating a second impedance equivalent to the frequency FOUT / 2 of the frequency-divided output signal. Here, the second switched-capacitor circuit 56 is configured to generate a voltage VREF_R corresponding to the second impedance using a current IREF2. At this time, the voltage VREF_R at the output node 56b of the second switched-capacitor circuit 56 changes time-dependently when the capacitive element 561 is charged, but it converges to a stable point while being averaged by the capacitive element 562 that maintains charge accumulation. The voltage VREF_R at the output node 56b (output node 57b) at the stable point is controlled by the voltage difference detection circuit 57 to be equal to the reference voltage VREF2. Specifically, the differential amplifier circuit 572 generates a control voltage VC so that the voltage VREF_R is equal to the reference voltage VREF2.

[0038] Furthermore, in the frequency synchronization circuit 5, the second frequency divider circuit 55, the second switched-capacitor circuit 56, the voltage difference detection circuit 57, and the voltage-controlled oscillator circuit 58 form a frequency feedback circuit (feedback loop). The frequency feedback circuit is configured to generate an output signal with an output frequency FOUT that is frequency-synchronized to a reference frequency FREF. In other words, using the frequency feedback circuit of voltage difference detection circuit 57 → voltage-controlled oscillator circuit 58 → second frequency divider circuit 55 → second switched-capacitor circuit 56 → voltage difference detection circuit 57, the voltage difference detection circuit 57 feedback-controls the control voltage VC so that the voltage VREF_R becomes equal to the reference voltage VREF2.

[0039] Therefore, at the output node 57b of the voltage difference detection circuit 57 at the stable point, the voltage VREF_R is equal to the reference voltage VREF2 and depends on the second impedance and current IREF2 generated in the second switched-capacitor circuit 56, corresponding to the divided output signal. In this way, the frequency FOUT / 2 of the divided output signal is synchronized with the frequency FREF / 2 of the divided reference signal. In other words, the output frequency FOUT is synchronized with the reference frequency FREF.

[0040] The voltage-controlled oscillator circuit 58 generates an output signal of frequency FOUT by oscillating in accordance with the control voltage VC from the voltage difference detection circuit 57, and supplies it to the second frequency divider circuit 55 and the output node of the oscillator circuit 1. In other words, the output node of the oscillator circuit 1 at the stable point is supplied with an output signal of output frequency FOUT synchronized with the reference frequency FREF.

[0041] Thus, the frequency synchronization circuit 5 according to this embodiment has a frequency feedback circuit formed to match the frequency FREF oscillated by the reference oscillator circuit 3 using reference voltages VREF1 and VREF2.

[0042] Furthermore, it is known that quartz oscillators have frequency-temperature characteristics that depend on their cutting direction. Figure 2 is a diagram illustrating the voltage control of the quartz oscillator 32 according to its frequency-temperature characteristics, which is performed by the control circuit 51 in Figure 1. Figure 2 illustrates the frequency-temperature characteristics of a quartz oscillator with cutting direction A (solid line) and the frequency-temperature characteristics of a quartz oscillator with cutting direction B (dashed line).

[0043] Therefore, the output frequency FOUT of the oscillator circuit 1 according to the embodiment can be expressed as a function of reference voltages VREF1 and VREF2 and reference frequency FREF, using a correction value (Fx) corresponding to the frequency-temperature characteristics of the crystal oscillator 32, as shown in the following relational expression.

[0044]

number

[0045] Here, the correction value (Fx) corresponding to the frequency-temperature characteristics of the crystal oscillator 32 is, for example, a value obtained by inverting the sign of the frequency axis of the frequency-temperature characteristics, as illustrated in Figure 2.

[0046] In the above relationship, it is assumed that the capacitance values ​​of the capacitive element 531 of the first switched-capacitor circuit 53 and the capacitive element 561 of the second switched-capacitor circuit 56 are equal. Also, it is assumed that the capacitance values ​​of the capacitive element 532 of the first switched-capacitor circuit 53 and the capacitive element 562 of the second switched-capacitor circuit 56 are equal.

[0047] The control circuit 51 makes the voltage ratio VREF1 / VREF2, which represents the reference voltage VREF1 with respect to the reference voltage VREF2, inversely proportional to the frequency-temperature characteristics of the crystal oscillator 32. Specifically, the control circuit 51 controls the reference voltages VREF1 and VREF2 such that ΔV is ∂Fx / ∂T, when VREF1 / VREF2 is α / ΔV, thereby canceling the temperature characteristics of the reference frequency FREF. Here, the coefficient α represents the amplification factor (attenuation rate) of the output frequency FOUT with respect to the reference frequency FREF. As an example, the coefficient α is determined according to the cutting orientation of the crystal oscillator 32. The control circuit 51 controls the voltage values ​​of the reference voltages VREF1 and VREF2 using a value obtained by multiplying the voltage ratio VREF1 / VREF2 by a predetermined coefficient α.

[0048] Specifically, the control circuit 51 acquires a signal from the temperature sensor 33, which is located on the same board as the crystal oscillator 32 in the reference oscillation circuit 3, and obtains a correction value (Fx) corresponding to the temperature x of the crystal oscillator 32 using a table or relational expression stored in the internal ROM (Read Only Memory) or other memory. Based on this, the control circuit 51 determines the ratio of VREF1 / VREF2 based on α / ΔV corresponding to the temperature x of the crystal oscillator 32, and outputs reference voltages VREF1 and VREF2 that satisfy this ratio.

[0049] Furthermore, the internal memory of the control circuit 51 may store a table or relational expression showing the correspondence between the signal level from the temperature sensor 33 or the temperature x of the crystal oscillator 32 and the reference voltages VREF1, VREF2 or VREF1 / VREF2. In this case, the control circuit 51 can read out the reference voltages VREF1 and VREF2 corresponding to the signal level from the temperature sensor 33 or the temperature x of the crystal oscillator 32, or read out VREF1 / VREF2 corresponding to the signal level from the temperature sensor 33 or the temperature x of the crystal oscillator 32 and determine the reference voltages VREF1 and VREF2 that satisfy the ratio.

[0050] Conventionally, oscillator circuits that obtain a desired output frequency by causing a crystal oscillator to oscillate include oven-controlled crystal oscillators (OCXOs) and voltage-controlled crystal oscillators (VCXOs).

[0051] Generally, the output frequency from a quartz crystal oscillator is temperature-dependent. However, in an OCXO, the temperature of the quartz crystal oscillator is maintained using a constant-temperature bath to suppress changes in the output frequency. For this reason, OCXOs require a heater, resulting in higher power consumption compared to other oscillator circuits.

[0052] In a VCXO, since it can output a frequency corresponding to the input control voltage, temperature stability can be improved without using a constant temperature bath by precisely controlling the control voltage, and power consumption can be reduced compared to an OCXO. On the other hand, a problem with VCXOs is that the phase noise is larger compared to other crystal oscillator circuits due to the low Q (Quality Factor) of the varicap diode (variable capacitance element).

[0053] In this context, the frequency synchronization circuit 5 in the oscillator circuit 1 according to the embodiment has a frequency feedback circuit. The frequency feedback circuit is configured to compare the frequency with a voltage in a second switched-capacitor circuit 56 and generate an output signal FOUT that is frequency-synchronized to a reference frequency FREF by negative feedback.

[0054] Figure 3 shows an example of the phase noise characteristics of the frequency synchronization circuit 5 in Figure 1. In the graph in Figure 3, the vertical axis and horizontal axis represent the phase noise [dB] and frequency offset [Hz], respectively.

[0055] This configuration allows for the realization of a VCXO without using a varicap diode, thereby improving the Q factor, bringing the phase noise closer to FOUT=FREF, and improving the phase noise represented by the integral value of the characteristic curve in Figure 3. In other words, as illustrated in Figure 3, it is possible to achieve lower phase noise compared to a VCXO using a varicap diode.

[0056] Furthermore, in the oscillator circuit 1 according to this embodiment, the first frequency divider circuit 52 and the second frequency divider circuit 55 are configured to shape the duty cycle of the reference period signal of the reference frequency FREF and the output signal of the output frequency FOUT to 50:50, respectively. With this configuration, even when the reference frequency FREF and output frequency FOUT are high, the charging and discharging of the capacitive elements in the first switched-capacitor circuit 53 and the second switched-capacitor circuit 56 can be performed appropriately.

[0057] Furthermore, in the oscillation circuit 1 according to this embodiment, the control circuit 51 is configured to make the voltage ratio VREF1 / VREF2 inversely proportional to the frequency-temperature characteristics of the crystal oscillator 32. With this configuration, a reference period signal with a highly accurate reference frequency FREF can be generated in the same way as a simple packaged crystal oscillator (SPXO), while the temperature characteristics of the SPXO can be canceled by controlling the reference voltages VREF1 and VREF2. Thus, since the oscillation circuit 1 according to this embodiment has a circuit configuration in which the output frequency OUT is expressed as a function of the reference voltages VREF1 and VREF2, it is possible to achieve temperature stability similar to that of an OCXO without a heater.

[0058] Furthermore, in the oscillation circuit 1 according to the embodiment, the control circuit 51 is configured to control the voltage values ​​of the reference voltages VREF1 and VREF2 using a value obtained by multiplying the voltage ratio VREF1 / VREF2 by a predetermined coefficient α according to the cutting direction of the crystal oscillator 32. With this configuration, the output frequency FOUT can be finely adjusted by controlling the coefficient α with high resolution.

[0059] Furthermore, the coefficient α can be used as an adjustment parameter for the output frequency. Therefore, according to the oscillation circuit 1 of this embodiment, trimming of the crystal oscillator 32 itself can be eliminated.

[0060] According to at least one embodiment described above, power consumption and phase noise in the oscillation circuit can be suppressed.

[0061] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0062] 1. Oscillator circuit 3. Reference Oscillator Circuit 31. Crystal Oscillator Circuit 32 Crystal unit 33 Temperature Sensor 34 circuit boards 5 Frequency Synchronization Circuit 51 Control circuits 52 First frequency divider circuit 53 First switched-capacitor circuit 54 Current source 55 Second frequency divider circuit 56. Second Switched Capacitor Circuit 57 Voltage difference detection circuit 58 Voltage-controlled oscillator circuit

Claims

1. A first switched capacitor circuit configured to generate a first impedance by charging and discharging a capacitive element in accordance with an input reference frequency reference period signal, A current source electrically connected to the first switched-capacitor circuit and configured to generate a reference current corresponding to the first impedance using the input first reference voltage, A voltage-controlled oscillator circuit configured to output an output signal having an output frequency corresponding to the control voltage, A second switched capacitor circuit is cascode-connected to the first switched capacitor circuit, electrically connected to the current source, and configured to generate a second impedance by charging and discharging a capacitive element in accordance with the output signal, and to generate a voltage corresponding to the second impedance using the reference current, A voltage difference detection circuit is electrically connected to the second switched-capacitor circuit and the voltage-controlled oscillator circuit, and is configured to generate the control voltage according to the difference between a voltage corresponding to the second impedance and a second input reference voltage. A frequency feedback circuit configured to generate the output signal having an output frequency that is frequency-synchronized to the reference frequency, and A frequency synchronization circuit equipped with the following features.

2. The frequency synchronization circuit according to claim 1, A crystal oscillator circuit is electrically connected to the first switched-capacitor circuit and configured to generate the reference period signal of the reference frequency by the oscillation operation of a crystal oscillator and to supply the reference period signal to the first switched-capacitor circuit. An oscillator circuit equipped with the following features.

3. A first frequency divider circuit is electrically connected between the crystal oscillator circuit and the first switched-capacitor circuit, and is configured to shape the duty cycle of the reference frequency reference period signal to 50:50 and supply it to the first switched-capacitor circuit. A second frequency divider circuit is electrically connected between the voltage-controlled oscillator circuit and the second switched-capacitor circuit, and is configured to shape the duty cycle of the output signal at the output frequency to 50:50 and supply it to the second switched-capacitor circuit. The oscillation circuit according to claim 2, further comprising:

4. A temperature sensor formed on the same substrate as the aforementioned quartz oscillator, A control circuit is electrically connected to the temperature sensor, the crystal oscillator circuit, the current source, and the voltage difference detection circuit, and is configured to control the voltage values ​​of the first reference voltage and the second reference voltage based on the signal from the temperature sensor, the reference period signal, and the frequency-temperature characteristics of the crystal oscillator. The oscillation circuit according to claim 2 or claim 3, comprising:

5. The oscillation circuit according to claim 4, wherein the control circuit makes the voltage ratio representing the first reference voltage with respect to the second reference voltage inversely proportional to the frequency-temperature characteristics of the crystal oscillator.

6. The oscillation circuit according to claim 5, wherein the control circuit controls the voltage values ​​of the first reference voltage and the second reference voltage using a value obtained by multiplying the voltage ratio by a predetermined coefficient.

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