Infrastructure integrity check

Abstract

The device (200) includes a first component (210) having a data input and a data output. The device further includes an error correcting code (ECC) generation circuit (230) having an input coupled to the data input of the first component (210). The ECC generation circuit (230) has an output. A second component (220) has a data input coupled to the output of the ECC generation circuit (230). The second component (220) has a data output. An ECC error detection circuit (250) has a first data input coupled to the data output of the first component (210) and a second data input coupled to the data output of the second component (230).

Description

Technical Field

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[0001] Some electronic systems benefit from an increased assurance of system behavior. For example, today's automobiles include advanced electronic systems that should incorporate the ability to detect faults and thereby ensure the safe operation of the automobile. Industrial and other applications also benefit from fault detection.

Summary of the Invention

[0002] In at least one example, a device includes a first component having a data input and a data output. The device further includes an error correction code (ECC) generation circuit having an input coupled to the data input of the first component. The ECC generation circuit has an output. A second component has a data input coupled to the output of the ECC generation circuit. The second component has a data output. An ECC error detection circuit has a first data input coupled to the data output of the first component and a second data input coupled to the data output of the second component.

Brief Description of the Drawings

[0003] For a detailed description of various examples, reference is now made to the accompanying drawings.

[0004] [Figure 1] An example of a system-on-chip (SoC) including a crossbar interconnect is illustrated.

[0005] [Figure 2] An exemplary implementation of a crossbar interconnect including a plurality of infrastructure components is illustrated.

[0006] [Figure 3] Examples of functions performed by infrastructure components are illustrated.

[0007] [Figure 4]An example of error injection for testing the performance of error correction codes (ECC) is illustrated.

[0008] [Figure 5] A system including multiple masters and slaves is illustrated.

[0009] [Figure 6] This document provides an example implementation of control bits and data integrity checks in a distributed system. [Modes for carrying out the invention]

[0010] Figure 1 shows an illustrative architecture of a system-on-a-chip (SoC) 100, which includes one or more central processing unit (CPU) cores 110, tightly coupled memories A and B (TCMA and TCMB) 120 and 122, a crossbar 130, a shared memory 128, and input / output (I / O) devices 140 and 142. Each CPU core 110 is coupled to its respective tightly coupled memory. For example, if there are two CPU cores 110, one CPU core is coupled to TCMA 120 and the other CPU core 110 is coupled to TCMB 122. Each CPU core 110 can store and retrieve information from its respective tightly coupled memory. A CPU core 110 is coupled to a crossbar 130, which is coupled to the shared memory 128 and the I / O devices 140 and 142. I / O devices 140, 142 may include network ports (e.g., controller area network, serial peripheral interface, etc.), memory, etc. The SoC 100 may have only one I / O device, or it may have two or more I / O devices. I / O devices 140, 142 are accessible to the CPU core 110 via the crossbar 130. Shared memory may be implemented, for example, as random access memory (RAM). The CPU core 110 can access the common shared memory 128 via the crossbar 130. In one example, the CPU core 110 has a clock frequency of 400 MHz, and the size of the tightly coupled memory (TCMA 110, TCMB 122) is 32 kilobytes (KB). However, the shared memory 128 has a larger size than TCMA 110 or TCMB 120 (e.g., 1 megabyte (MB)).

[0011] The shared memory 128 may be used, for example, to store instructions and data. Instructions are retrieved by the CPU core 110 via the crossbar 130, as indicated by the dashed arrow 145. Data can also be written to or retrieved from the shared memory 128 by the CPU core 110. Since such information (instructions and / or data) traverses the crossbar 130 between the shared memory 128 and the CPU core 110, defects in the crossbar 130 may affect the integrity of the information. That is, an instruction retrieved from the shared memory 128 (which contains multiple bits) may have one or more of its bits changed (inverted), i.e., a "0" becoming a "1" or a "1" becoming a "0". Such defects may adversely affect the operation of a system including the SoC 100 (e.g., an automobile). The example described herein implements defect detection capability within the crossbar 130.

[0012] Figure 2 shows at least some illustrative circuit (e.g., integrated circuit) implementations of the crossbar 130. In the example described above, the crossbar 130 can be used to transfer data between the CPU core 110 and shared memory. However, the crossbar 130 can be used to transfer data between slave devices under the control of a direct memory access (DMA) controller. In general, the crossbar 130 can be used to transfer data between two devices. The circuit 200 in Figure 2 includes an infrastructure component (Main) 210, an infrastructure component 220 (Safe), an error correction code (ECC) generation circuit 230, a control signal comparator circuit 240, and an ECC error detection circuit 250. The signal from the CPU core 110 includes control bits 201 and data bits 202. The control bits 202 encode information about the transaction, such as the address, whether the transaction is read or write, burst size, priority, privilege level, and access type. In the context of a write transaction, data bit 202 contains the data to be written to shared memory 128.

[0013] The control bit 201 and data bit 202 are provided to the infrastructure component (Main) 210. The data bit 202 is also provided to the ECC generation circuit 230. The ECC generation circuit 230 calculates the ECC for the data bit 202 and provides the calculated ECC 231 to the infrastructure component (Safe) 220. The control bit 201 is also provided to the ECC infrastructure component 220.

[0014] In one example, the infrastructure component (Main) 210 performs a conversion on data bits 202. In another example, the infrastructure component (Main) 210 performs a bus width conversion on data bits 202. The data bus providing data bits 202 between the CPU core 110 and the circuit 200 may be, for example, a 128-bit bus, but the width of the data bus up to shared memory 128 is 32 bits. Therefore, the infrastructure component (Main) 210 converts data bits 202 from a 128-bit word to four consecutive 32-bit words. Thus, the width of data bits 212 is 32 bits. An example of the infrastructure component (Main) 210 converting data between a 128-bit width and a 32-bit width is discussed herein, and the infrastructure component (Main) 210 can convert between any bus width. In other examples, the infrastructure component (Main) 210 performs address decoding, arbitration, bus protocol conversion, and / or burst splitting. The infrastructure component (Main) 210 can also modify control bits 201. In an example where the infrastructure component (Main) 210 performs bus width conversion of data bits 202, the infrastructure component (Main) 210 may convert the byte count for each of the four consecutive words to 1 / 4 of the byte count provided in the control bit 201 input to the infrastructure component (Main) 210.

[0015] Data bit 212 flows through the control signal comparator 240 and is supplied to the ECC error detection circuit 250 as data bit 222. In this example, the width of data bit 222 is the same as the width of data bit 212 (e.g., 32 bits). Control bit 211 from the infrastructure component (Main) 210 is also provided to the control signal comparator 240. Control bit 239 from the infrastructure component (Safe) 220 is also provided to the control signal comparator 240. The control signal comparator 240 compares control bit 239 from the infrastructure component (Safe) 220 with control bit 211 from the infrastructure (Main) component 210. In one example, the control signal comparator 240 performs a bitwise comparison between control bit 211 and control bit 239. An error signal 241 indicates whether control bits 211 and 239 match. In one example, the error signal 241 is a single-bit signal (for example, 0 indicates that control bits 211 and 239 match, and 1 indicates a mismatch). If there is a mismatch, the CPU core 110 may be suspended (or notified to an external host), and then perform a suspension service routine to respond to the error. Assuming there is no error, control bit 221 from the control signal comparator 240, which includes control bit 211, is provided as an output from the crossbar 130 (for example, to shared memory 128).

[0016] The infrastructure component (Safe) 220 performs almost the same conversion process as the infrastructure component (Main) 210 and, in some examples, is another instance of the same circuit element that includes the infrastructure component (Main) 210. The infrastructure component (Main) 210 receives data bits 202 as input, and the infrastructure component (Safe) 220 receives ECC bits 231 as input. For data bits 202 containing a 128-bit wide word, the ECC generation circuit 230 calculates 28 bits of ECC and ECC bits 231 in the form of a 128-bit wide word.

[0017] Figure 3 shows the data width conversion performed by the infrastructure component (Main) 210 and the infrastructure component (Safe) 220, as well as the functions performed by the ECC generation circuit 230. A 128-bit word is represented as data bits 202. The data word contains four 32-bit parts 301 to 304. Part 301 contains the lower data bits 0 to 31. Part 302 contains the next set of 32 data bits, i.e., bits 32 to 63. Part 303 contains bits 64 to 95. Part 304 contains bits 96 to 127.

[0018] The infrastructure component (Main) 210 forms four 32-bit words 315-318, which can be clocked out of the infrastructure component (Main) 210 in four separate clock cycles. The 32-bit word 315 includes a portion 301 from the original 128-bit data word. The 32-bit words 316-318 include their respective portions 302-304, as shown in the figure.

[0019] The ECC generation circuit 230 also receives a 128-bit data word (data bits 202), calculates the ECC bits for the associated 128-bit data word, and forms a 128-bit ECC word 231. For a 128-bit data word, the ECC generation circuit 230 calculates 28 bits of ECC, as shown in 237. The 28 bits of ECC are divided into four 7-bit ECC portions. The lower 7 ECC bits are populated in the first 7 bits of the ECC word 231 at bit positions 0-6, as shown in the figure. The next 7 higher-order ECC bits are populated at bit positions 32-38. Similarly, the next two sets of 7 ECC bits are populated at bit positions 64-70 and bit positions 96-102, as shown in the figure. The remaining 100 bits of the ECC word 231 are populated with 0 in this example. Thus, the ECC word 231 generated by the ECC generation circuit 230 contains four distinct segments of ECC bits. Each 32-bit portion of a 128-bit ECC word 231 contains 7 ECC bits.

[0020] Infrastructure component (Safe) 220 receives the 128-bit ECC word 231 and performs the conversion process in the same way as described above for infrastructure component (Main) 210. That is, infrastructure component (Safe) 220 generates four 32-bit words 331 to 334. 32-bit word 331 contains the least significant 32 bits of ECC word 231, with ECC word 231 itself containing seven ECC bits in the first seven bit positions and zeros in the remaining bit positions. Similarly, 32-bit word 332 contains the next set of 32 bits of ECC word 231, with the next seven ECC bits in its seven least significant bit positions. 32-bit words 333 and 334 are formed similarly, each having seven ECC bits in its least significant seven bits, as shown in the figure.

[0021] Each of the 32-bit words 315-318 contains 32 bits of the original 128 bits of data, and each of the 32-bit words 331-334 contains seven ECC bits corresponding to the 32 data bits in each associated word 331-334. That is, the ECC bits in word 331 contain the ECC bits calculated for the 32 bits of data in word 315. Similarly, the ECC bits in words 332-334 contain the ECC bits calculated for the 32 bits of data in words 316-318. The data words 315-318 are represented in Figure 2 as data bits 222. The ECC words 331-334 are represented in Figure 2 as ECC word 248.

[0022] Referring again to FIG. 2, data bits 222 and ECC words 248 are provided to an ECC error detection circuit 250. For each of the 32-bit data words (315 - 318 including data bits 222), the ECC error detection circuit 250 generates seven ECC bits and compares the newly calculated ECC bits with the ECC bits within the corresponding ECC word 248 (words 331 - 334). An error signal 251 (which can interrupt the CPU 110 or be notified to an external host) indicates whether the ECC bits match (for example, an error signal having a value of 0 means the ECC bits match, and an error signal having a value of 1 means at least one ECC bit did not match). If there is no ECC error, the data bits 232 from the ECC error detection circuit 250 include the data bits 222. Therefore, when neither error signal 241 nor error signal 251 indicates an error (i.e., there is no control bit error and no ECC bit error), the control bits 221 and data bits 232 are provided to downstream components such as the shared memory 128.

[0023] FIG. 4 illustrates an implementation in which ECC error detection within the circuit 200 can be tested. In the example of FIG. 4, the logical state of one or more of the data bits is intentionally changed (a "0" is changed to a "1" and vice versa). The circuit of FIG. 4 is substantially the same as the circuit of FIG. 2. The control bits of FIG. 2 are not shown in the example of FIG. 4. The ECC error detection circuit 250 includes an ECC generator circuit 410 coupled to an ECC comparison circuit 420. The data bits 212 from the infrastructure component (Main) 210 are provided to the input of the ECC generator circuit 410.

[0024] One or more of the data bits 212 are provided to the inputs of an exclusive OR (XOR) gate. In the example of FIG. 4, the two least significant bits of the data bits 212 are coupled to respective inputs of the XOR gate. The XOR gate 401 receives the least significant data bit DATA[0] at one of its inputs and the error injection signal 403 at the other input. The output 411 of the XOR gate 401 is coupled to respective inputs of the ECC generator circuit 410. Similarly, the XOR gate 402 receives DATA[1] at one of its inputs, and the error XOR gate 401 receives the least significant data bit DATA[0] at one of its inputs and the error injection signal 403 at the other input. The output 411 of the XOR gate 401 is coupled to respective inputs of the ECC generator circuit 410 and receives the signal 404 at its other input. The output 413 of the XOR gate 402 is coupled to respective inputs of the ECC generator circuit 410.

[0025] The XOR gates 401 and 402 function to invert the polarity of their respective data input bits when it is desired to test the operation of the ECC error detection circuit 250. Otherwise, during normal runtime operation, the polarity of the data bits remains unchanged. When the error injection signal 403 is low (0), the polarity of the signal on the output 411 of the XOR gate 401 is the same as the polarity of DATA[0], and when DATA[0] is equal to 1, the output 411 is 1, and when DATA[0] is equal to 0, the output 411 is 0. When the error injection signal 403 is high (1), the XOR gate 401 sets its output 411 to the opposite polarity of DATA[0], i.e., the XOR gate 401 inverts the logical state of DATA[0] when the error injection signal 403 is forced high. The operation of the XOR gate 402 functions in the same manner to invert the logical level of DATA[1] when the respective error injection signal 404 is asserted high. Otherwise, the XOR gate 402 maintains the logical level of its output 413 the same as the logical level of DATA[1] when the error injection signal 404 is 0.

[0026] In the example in Figure 4, one or two of the data bits 212 can be "inverted". Such an inverted bit state is not reflected in the data bits 202 provided to the infrastructure component (Safe) 220, as the infrastructure component (Safe) 220 itself calculates the ECC of the data bits. Therefore, an error can be injected into the data bits 212, and if it works correctly, the ECC error detection circuit 250 detects the error and asserts the error signal 241 accordingly. The ECC generator circuit 410 calculates the ECC of the data bits, which may include one or more data bits whose logical state has been changed. The ECC comparison circuit 420 receives the ECC word 248 from the infrastructure component (Safe) 220, extracts the ECC from the ECC word 248, and compares them with the newly calculated ECC 417 from the ECC generator circuit 410. If a difference is detected, the error signal 241 is asserted high, for example, to indicate an ECC error state.

[0027] Figure 5 shows an example of a system 300 including multiple masters 302, 306, 310, and 314, multiple slaves 320 and 324, and an interconnect 330. The components shown in Figure 5 can be provided on a semiconductor die. Any appropriate number of masters and slaves can be provided. Information can flow bidirectionally through the interconnect 330 between any masters 302-314 and any slaves 320 and 324. As data and control signals through any given node (master, interconnect, or slave), a complete data and control signal check (as in the example in Figure 2) does not need to be performed at each node. That is, if master 302 is sending communication to slave 324, the logic in Figure 2 does not need to be performed multiple times along the communication path within each of master 302, interconnect 330, and slave 324.

[0028] Alternatively, the master 302 may include an infrastructure component 220 that generates an ECC word 248 and provides control bits 239, but does not compare the control bits, nor generates or compare the ECC bits. Instead, the ECC word 248 and control bits 239 can be transferred from the master 302 to the slave 324 via the interconnect 330. The slave 324 may include logic for comparing the control bits and generating and comparing the ECC bits to detect errors. Thus, the masters 302-314 and the slaves 320 and 324 have logic designated as Safe End (SE) 303 and Safe Parse (SP) 305. The SE 303 includes logic for generating the control bits 239 and the ECC word 248 for one-way communication (e.g., from master to slave) and logic for comparing the control bits and ECC bits for communication in the opposite direction (from slave to master).

[0029] Figure 6 shows an example of circuit 600 that may be implemented as part of masters 302-314 and / or slaves 320-324. Circuit 600 includes circuits 606 and 608. Circuit 606 includes an infrastructure component (Main) 210, an infrastructure component (Safe) 220, and the ECC generator 230 described above. Circuit 608 includes an ECC error detection circuit 250 and the control signal comparator 240 described above. The functionality of these components is largely as described above. In the illustrative implementation of Figure 2, control bits 211 and 239 and data bit 212 are provided to the control signal comparator 240 in the same device. In the illustrative implementation of Figure 6, control bits 611 and data bit 612 from the infrastructure component (Main) 210, and control bits 639 and ECC word 648 from the infrastructure (Safe) component 220 are not provided to circuit 608 in the same device (master, slave). Instead, these signals are supplied to the control signal comparator 240 of the destination device via the interconnect 330. That is, the control bits 655 and 658 and data bits 642 and 668, shown as inputs to circuit 608 in Figure 6, originate from the device via the interconnect 330. Thus, integrity checks of the control bits and data bits (ECC) are performed within the destination device, while the generation of the ECC word and separate control bits used in the integrity check takes place within the device where the communication transaction occurs. For example, if master 302 is attempting to send a transaction to slave 324, master 302 generates control bit 639 and ECC word 648 from its infrastructure component (Safe) 220 and provides control bit 639, ECC word 648, and control bit 611 and data bit 612 via the interconnect 330. Slave 324 receives these bits and performs control and data bit integrity checks within its own control signal comparator 240 and ECC error detection circuit 250. For example, intermediate checks within interconnection 330 do not necessarily need to be performed.

[0030] SP305 specifies an interface that allows control bits, data bits, and ECC words to pass without performing integrity checks. SE303 specifies an interface having circuits 606 and 608, as illustrated in Figure 6. An unsafe (NS) interface 317 specifies an interface that does not implement the integrity techniques described herein and therefore does not include the extra control bits 639 and ECC word 648 that would otherwise be available for the integrity checks described herein.

[0031] The term “coupled” is used throughout this specification. This term may include connections, communications, or signaling paths that enable a functional relationship consistent with the descriptions in this disclosure. For example, if device A generates a signal to control device B in order to perform a certain action, in the first example, device A is coupled to device B, or in the second example, device A is coupled to device B via intermediary component C such that device B is controlled by device A via a control signal generated by device A, provided that intermediary component C does not substantially alter the functional relationship between device A and device B.

[0032] Within the scope of the claims of the present invention, modifications may be made to the exemplary embodiments described, and other embodiments are possible.

Claims

1. It is a device, A first component having a data input and a data output including a first line and a second line, An error correction code (ECC) generation circuit having an input coupled to the data input of the first component and an output, A second component having a data input and a data output coupled to the output of the ECC generation circuit, An ECC error detection circuit having a first data input including a first line and a second line, and a second data input coupled to the data output of the second component, wherein the first line of the first data input is coupled to the first line of the data output of the first component, and the ECC comparison circuit is configured to compare a first code based on data received at the first data input with a second code based on data received at the second data input, A logic gate having a first input connected to a second line of the data output of the first component, and an output connected to a second line of the first data input of the ECC error detection circuit, A device that includes this.

2. The device according to claim 1, A device wherein the ECC error detection circuit further includes an ECC generator configured to calculate the first code, and the ECC comparison circuit further includes an ECC generator configured to extract the second code from data received at the second data input.

3. The device according to claim 2, The device further comprises an ECC comparison circuit configured to assert an error signal in response to a mismatch between the first code and the second code.

4. The device according to claim 1, The device further includes a control signal comparator circuit having a first control input coupled to the control output of the first component and a second control input coupled to the control output of the second component.

5. The device according to claim 4, A device in which the control signal comparator circuit is configured to compare a control bit from the control output of the first component with a corresponding control bit from the control output of the second component.

6. The device according to claim 5, The device further comprises a control signal comparator circuit configured to assert an error signal in response to a mismatch between the control bit from the control output of the first component and the corresponding control bit from the control output of the second component.

7. The device according to claim 1, The ECC generation circuit is configured to generate an ECC word including a first set of ECC bits based on data received on the input of the ECC generation circuit, and to provide the ECC word on the output of the ECC generation circuit. A device wherein the ECC comparison circuit is further configured to extract the second code from the ECC word.

8. The device according to claim 7, The first code is composed of a second set of ECC bits, and the second code is composed of the first set of ECC bits, The device further comprises an ECC error detection circuit which calculates a second set of ECC bits based on data received at the first data input and compares the first set of ECC bits with the second set of ECC bits.

9. The device according to claim 1, The first component is configured to perform bus width conversion between the data input and the data output of the first component. A device in which the second component is configured to perform bus width conversion between the data input and the data output of the second component.

10. The device according to claim 1, A device in which the first component is configured to perform at least one of address decoding, arbitration, bus protocol translation, and burst splitting.

11. The device according to claim 1, A device in which the second component is another instance containing the same circuit elements as the first component.

12. The device according to claim 1, The logic gate further has a second input configured to receive an error injection signal, A device in which, when the error injection signal is asserted to a first state, the bit on the second line of the first data input of the ECC error detection circuit is in the opposite state to the corresponding bit on the second line of the data output of the first component.

13. The device according to claim 12, A device in which the logic gates include an exclusive OR gate.

14. It is a device, A first component having a data input, a control output, and a data output, An error correction code (ECC) generation circuit having an input coupled to the data input of the first component and an output, A second component having a data input coupled to the output of the ECC generation circuit, a control output, and a data output, A control signal comparator circuit having a first control input coupled to the control output of the first component, a second control input coupled to the control output of the second component, a data input coupled to the data output of the first component, and a data output, An ECC error detection circuit having a first data input coupled to the data output of the control signal comparator circuit and a second data input coupled to the data output of the second component, A device that includes this.

15. The device according to claim 14, A device in which the control signal comparator circuit is configured to compare a control bit from the control output of the first component with a corresponding control bit from the control output of the second component.

16. The device according to claim 14, The ECC generation circuit is configured to generate an ECC word including a first set of ECC bits based on data received on the input of the ECC generation circuit, and to provide the ECC word on the output of the ECC generation circuit. A device in which the ECC error detection circuit is configured to calculate a second set of ECC bits based on data on the data output of the first component, and compare the second set of ECC bits with the first set of ECC bits received from the data output of the second component on the second data input.

17. The device according to claim 14, A device in which the first component is configured to perform at least one of the following: bus width translation, address decoding, arbitration, bus protocol translation, and burst splitting.

18. The device according to claim 14, A device in which the second component is another instance containing the same circuit elements as the first component.

19. It is a system-on-a-chip, A first component having a data input, a control output, and a data output, configured to perform at least one of bus width conversion, address decoding, arbitration, bus protocol conversion, and burst splitting, An error correction code (ECC) generation circuit having an input coupled to the data input of the first component and an output, A second component having a data input coupled to the output of the ECC generation circuit, a control output, and a data output, configured to perform at least one of bus width conversion, address decoding, arbitration, bus protocol conversion, and burst splitting, A control signal comparator circuit having a first control input coupled to the control output of the first component, a second control input coupled to the control output of the second component, a data input coupled to the data output of the first component, and a data output, An ECC error detection circuit having a first data input coupled to the data output of the control signal comparator circuit and a second data input coupled to the data output of the second component, A system-on-a-chip that includes this.

20. The SoC according to claim 19, The SoC is configured such that the control signal comparator circuit compares a control bit from the control output of the first component with a corresponding control bit from the control output of the second component.

21. The SoC according to claim 19, The ECC generation circuit is configured to generate an ECC word including a first set of ECC bits based on data received on the input of the ECC generation circuit, and to provide the ECC word on the output of the ECC generation circuit. The SoC is configured such that the ECC error detection circuit calculates a second set of ECC bits based on data on the data output of the control signal comparator circuit and compares the second set of ECC bits with the first set of ECC bits.

22. The SoC according to claim 19, A SoC in which the second component is another instance containing the same circuit elements as the first component.

23. It is a device, A first component having a data input and a data output, configured to convert a data word of a first length received at the data input into a data word of a second length for output at the data output, wherein the first length is greater than the second length and is an integer multiple of the second length, An error correction code (ECC) generation circuit having an input coupled to the data input of the first component and an output, the ECC generation circuit being configured to generate an ECC word including a first set of ECC bits based on a data word of a first length received on the input of the ECC generation circuit, and to provide the ECC word of the first length to the output of the ECC generation circuit, A second component having a data input coupled to the output of the ECC generation circuit and a data output, configured to convert the first length ECC word to the second length ECC word, wherein each of the second length ECC words includes a corresponding subset of the first set of ECC bits; An ECC error detection circuit having a first data input coupled to the data output of the first component and a second data input coupled to the data output of the second component, wherein the circuit is configured to calculate a second set of ECC bits based on a second length data word on the data output of the first component and compare the second set of ECC bits with the first set of ECC bits, A device that includes this.

24. The device according to claim 23, A device in which the second component is another instance containing the same circuit elements as the first component.

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