Interconnection of protection information between components

Abstract

To provide an interconnect with low complexity of design which addresses a defect caused by the fact that handling of EDC (Error Detection and Correction) information and signal width are not defined in AXI(Advanced eXtensible Interface) of AMBA (Advanced Microcontroller Bus Architecture) standard.SOLUTION: The interconnect includes: an input end couplable to a transmission source; and an encoder coupled to the input end. The encoder groups information received from the transmission source via a same channel, sizes the grouped information to a common width, and applies protection to the sized grouped information.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] Aspects described herein generally relate to interconnects, and more particularly, to an interconnect capable of integrating any component.

Background Art

[0002] AMBA (Advanced Microcontroller Bus Architecture) is an open standard that defines the connection and management of components within a System-on-Chip (SoC). AXI (Advanced eXtensible Interface), while being part of the AMBA standard designed to meet a wide range of interface requirements of components, can provide flexibility in the way those components are interconnected.

[0003] There are five independent channels between an AMBA AXI master component and a slave component: a write address channel, a write data channel, a write response channel, a read address channel, and a read data channel. The address channel is used to transmit an address and control information while performing a basic handshake between the master and the slave. The data channel is where the information to be exchanged is placed. The master reads data from the slave and writes data to the slave. The read response information is placed on the read data channel. Since the write response information has a dedicated channel, the master can verify that the write transaction has been completed. All data exchanges are called transactions. A transaction includes not only any response information but also an address, control information, and the transmitted data.

[0004] The AMBA AXI channel signals from the standard are shown in Figures 7A to 7E. Neither the AMBA AXI channel nor the signals provide sufficient security for master-slave communication in functional safety-related applications requiring means of detecting any fault. The AMBA AXI specification released in 2019 employs an error detection and correction (EDC) scheme within the component and a simplified parity scheme for detecting single-bit errors on the AMBA interface between components to provide end-to-end protection. Multi-bit errors can only be detected if they occur in different parity signal groups.

[0005] The AMBA AXI specification recommends that the source generate parity for information on the AMBA AXI channel, the interconnect checks this parity at its input end to generate EDC, the interconnect checks the generated EDC at its output end to generate another parity, and the destination finally checks this. Only integrative sources and destinations should follow this scheme. If the source generates EDC on part of the AMBA AXI channel, the AMBA AXI specification provides no instructions on what to do with this EDC information. Furthermore, because parity checking and EDC generation occur at the interconnect's input end, and parity generation and EDC occur at the interconnect's output end, the interconnect design becomes more complex and system latency increases. The specification also does not specify whether EDC generation at the interconnect's input end should be one EDC per signal, one EDC per channel, or one EDC for multiple channels. [Overview of the project] [Problems that the invention aims to solve]

[0006] Another challenge is that the AMBA AXI standard does not define signal width. This can lead to incompatibility between masters, slaves, and interconnects. For example, masters and slaves should use different signal widths for transaction IDs, so IP providers tend to provide parity information for such signals. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic diagram of the interconnect according to the aspects of this disclosure. [Figure 2] This figure shows an example of an interconnect according to the aspects of this disclosure. [Figure 3] To demonstrate how existing interconnect problems are solved according to the aspects of this disclosure, the diagram shows an example of an interconnect coupled between two masters and two slaves. [Figure 4] This figure shows an example of an interconnect during a write operation according to the embodiments of this disclosure. [Figure 5] This figure shows an example of an interconnect during a read operation according to an aspect of this disclosure. [Figure 6] This figure shows a flowchart illustrating a method for interconnecting information between a sender and a recipient according to the aspects of this disclosure. [Figure 7A] This is a diagram showing the channel signals from the AMBA AXI specification. [Figure 7B] This is a diagram showing the channel signals from the AMBA AXI specification. [Figure 7C] This is a diagram showing the channel signals from the AMBA AXI specification. [Figure 7D] This is a diagram showing the channel signals from the AMBA AXI specification. [Figure 7E] This is a diagram showing the channel signals from the AMBA AXI specification. [Modes for carrying out the invention]

[0008] This disclosure provides an interconnect with reduced design complexity that addresses the shortcomings described above in the background technology section.

[0009] Figure 1 is a schematic diagram of an interconnect 100 according to an embodiment of the present disclosure. It shows an interconnect 100 coupled between a source 10 and a destination 20. For example, the interconnect 100, source 10 and destination 20 may be provided within a system-on-a-chip (SoC) of a microcontroller.

[0010] The interconnect 100 comprises an input terminal 110, an encoder 120, a decoder 130, and an output terminal 140. The input terminal 110 is connectable to a source 10, which has an encoder 12 configured to generate protection information. The output terminal 140 is connectable to a destination 20, which has a decoder 22 configured to decode protection information. The protection information may be, for example, parity or an error detection code (EDC). It should be understood that, as used herein, EDC may be an error correction code (ECC) unless otherwise specified, and conversely, ECC may be EDC. The interconnect 100 is configured to communicate with any source 10 or destination 20 that encodes or decodes signals with parity and / or EDC.

[0011] Source 10 and / or destination 20 may operate in accordance with any AMBA standard, such as the AMBA AXI standard, but this disclosure is not limited thereto. Aspects of this disclosure apply to any source and / or destination that do not support secure communication by default.

[0012] The interconnect 100 is configured to pass any protection information (e.g., parity or EDC) received directly from the source 10 via the sideband channel to the destination 20. The decoder 22 at the destination 20 decodes this protection information, rather than the decoder within the interconnect 100. If the information decoded at the destination 20 indicates a fault, the destination 20 may issue an alarm to take any appropriate action.

[0013] The interconnect encoder 120 generates EDC using AMBA information from source 10. More specifically, encoder 120 first groups the information received from source 10 via the same channel. The channel can be any of the AMBA channels: write address channel, write data channel, write response channel, read address channel, or read data channel. The interconnect encoder 120 then sizes the grouped information to a common width by bit insertion and generates EDC protection based on the grouped and sized information. The common width may depend on the system configuration. The generated EDC is checked by the interconnect decoder 130 at output terminal 140 to ensure detection of any faults that occurred within the interconnect 100 before the AMBA information was passed to destination 20. If a fault is detected, an alarm is issued and / or other appropriate action may be taken. By generating EDC on grouped channel information rather than on a single channel signal, mixing of signals from different sources 10 is substantially avoided. In other words, when the interconnect encoder 120 generates EDC using only a single channel signal (e.g., transaction ID), the risk that destination 20 might receive a transaction ID from one source and an address or other signal from another due to an interconnect failure is reduced. In existing interconnects, the risk of such failures is significantly higher and may not even be detected.

[0014] According to a further aspect, the interconnect 100 can be tested by injecting a signal with an injection error at the input end 110 of the interconnect.

[0015] FIG. 2 is a diagram showing an example of an interconnect 200 according to an aspect of the present disclosure. The interconnect 200 is coupled between a master 22 (source / destination) and a slave 24 (source / destination).

[0016] In the write address channel AW, the master 22 transmits parity information (i.e., awaddr_pty for awaddr and awctrl_pty for awctrl) for both the address and the control signal towards the slave 24. The parity information is directly transferred through the interconnect 200 via a sideband channel and the parity information is decoded at the slave 24.

[0017] In the write data channel W, the master 22 transmits ECC information (i.e., wdata_ecc for wdata) for the data signal, but transmits parity information (i.e., wctrl_pty for wctrl) for the control signal. Both the ECC and the parity are transferred through the interconnect 200 and decoded at the slave 24.

[0018] In the write response channel B, the slave 24 transmits parity information (i.e., bctrl_pty), which is transferred through the interconnect 200 and decoded at the master 22.

[0019] In the read address channel AR, the master 22 transmits parity information (i.e., araddr_pty and arctrl_pty) for both the address and the control signal towards the slave 24. This parity information is transferred through the interconnect 200 and decoded at the slave 24.

[0020] In the read data channel R, slave 24 transmits ECC information for data (i.e., rdata_ecc for rdata) and parity information for control signals (rctrl_pty for rctrl). This ECC and parity information is passed through interconnect 200 and decoded at master 22.

[0021] The encoder of interconnect 200 calculates ECC for each channel (i.e., aw_ecc for write address channel AW, w_ecc for write data channel W, b_ecc for write response channel B, ar_ecc for read address channel AR, r_ecc for read data channel R). The decoder of interconnect 200 performs an ECC check.

[0022] FIG. 3 is a diagram showing an example of an interconnect 300 coupled between two masters 32A and 32B and two slaves 34A and 34B to demonstrate how problems of an existing interconnect are solved according to an aspect of the present disclosure.

[0023] A typical interconnect protocol has a request phase, during which the master requests access from the slave. The slave can identify which master is sending the request because it has an address signal (i.e., Address) that informs the master of the target address for reading / writing, an opcode (i.e., Op-Code) that informs the master how the data can be read / written, and a transaction ID (i.e., TR-ID) used for access protection. In AXI, each of the address, opcode, and transaction ID is signaled with parity (i.e., P), meaning the slave cannot verify that the address, opcode, and transaction ID all come from the same master. In such a situation, errors within the interconnect would go undetected. For example, if a first master requests access from a second slave, and the second slave receives the correct address, but for some reason receives an opcode from the second master, then information mixing exists. Existing interconnects cannot detect this mixed failure.

[0024] Interconnect 300 explains how it overcomes this mixed problem in existing interconnects. Masters and slaves may transfer data with different bit widths. In this example, master 32A transfers with bit width x, and master 32B transfers with bit width y, assuming x is less than y. The interconnect encoder aligns the transactions from the two masters 32A and 32B to a common width y using bit insertion. The width y is a system configuration and therefore a design choice. The circled reference number 4 shows an example where masters 32A and 32B use different widths for the same parity-protected protocol information transaction ID (i.e., TR-ID). The interconnect encoder adjusts its width to a common bit width via bit insertion in order to encode and decode ECC.

[0025] The interconnect encoder generates ECC for information grouped from the same channel (e.g., a write data channel). The interconnect decoder detects any erroneous mixing of channel information when it performs an ECC check on the received address channel information. This ECC check will detect any faults originating from interconnect 300, such as addresses from master 32A and opcodes from master 32B, or interconnect 300 where some information has been unintentionally scrambled. Interconnect 300 ensures that all address information received by slave 34A comes from the same master (32A or 32B), thus detecting faults within the interconnect. Examples in circles 1, 2, and 3 illustrate how the interconnect's ECC decoder may detect erroneous mixing of read data channel information that would not have been detected in an existing interconnect. Again, parity signals from the master and slave are routed directly through interconnect 300. The parity signal does not need to be covered by an ECC encoder / ECC decoder.

[0026] Figure 4 shows an example of interconnect 400 during a write operation, and Figure 5 shows an example of interconnect 500 during a read operation, as described in this disclosure. Signal labels extracted from the AMBA AXI specification are listed in the tables in Figures 7A to 7E. The encoder generates an EDC for each AMBA AXI channel at the input terminals of interconnect 400 / 500, and the decoder checks the EDC at the output terminals of interconnect 400 / 500. Protection information (parity and / or ECC) from the master 42 / 52 or slave 44 / 54 is passed through interconnect 400 / 500 to the other master 42 / 52 and slave 44 / 54 being checked. If a failure is detected at any level of the decoder, an alarm may be issued to the system, or other appropriate action may be taken.

[0027] Figure 6 is a flowchart 600 showing a method for interconnecting information between a sender 10 and a recipient 20 according to an aspect of this disclosure.

[0028] In step 610, information received at the interconnect input terminal 110 from the source 10 via the same channel is grouped together.

[0029] In step 620, the grouped information is resized to a common width.

[0030] In step 630, protection is applied to the grouped and sized information using the encoder 120 coupled to the interconnect input terminal 110.

[0031] Figures 7A to 7E are tables of channel signals from the AMBA AXI specification. Figure 7A is a diagram of Table 700A, which includes the write address channel signals. Figure 7B is a diagram of Table 700B, which includes the write data channel signals. Figure 7C is a diagram of Table 700C, which includes the write response channel signals. Figure 7D is a diagram of Table 700D, which includes the read address channel signals. Figure 7E is a diagram of Table 700E, which includes the read data channel signals.

[0032] The interconnects disclosed herein have lower design complexity and lower latency compared to conventional interconnects. All source, destination, and interconnect communications are seamlessly integrated via the AMBA protocol.

[0033] Furthermore, the technology of this disclosure can be described in the following embodiments.

[0034] Example 1: An interconnect comprising an input terminal connectable to a source, and an encoder connected to the input terminal, configured to group information received from the source via the same channel, to size the grouped information to a common width, and to apply protection to the grouped and sized information.

[0035] Example 2: The interconnect according to Example 1, wherein the interconnect is configured to directly transfer any protection information received at the input terminal to the output terminal of the interconnect via a sideband signal.

[0036] Example 3: The interconnect described in Example 2, wherein the received protection information is a parity bit, an error detection code (EDC), or an error correction code (ECC).

[0037] Example 4: The interconnect according to Example 1, further comprising a decoder coupled to the output terminal of the interconnect and configured to perform inspection of grouped and protected information.

[0038] Example 5: The interconnect according to Example 4, wherein the decoder is configured to output an alarm signal if the inspection of grouped and protected information fails.

[0039] Example 6: The interconnect according to Example 1, wherein the encoder protection configured to be applied to grouped and sized information is an error detection code (EDC) or error correction code (ECC).

[0040] Example 7: The interconnect according to Example 1, wherein the interconnect is configured to communicate with any source or destination configured by the AMBA (Advanced Microcontroller Bus Architecture) AXI (Advanced eXtensible Interface) protocol.

[0041] Example 8: The interconnect according to Example 1, wherein the interconnect is configured to receive injection errors at the input end for testing the interconnect.

[0042] Example 9: The interconnect according to Example 1, wherein the channels are a write address channel, a write data channel, a write response channel, a read address channel, or a read data channel.

[0043] Example 10: The interconnect according to Example 1, wherein the encoder is configured to size the grouped information to a common width by bit insertion.

[0044] Example 11: A microcontroller comprising the interconnect described in Example 1.

[0045] Example 12: A method for interconnecting information between a source and a destination, the method comprising: grouping information received from a source at the input end of an interconnect via the same channel; sizing the grouped information to a common width; and applying protection to the grouped and sized information using an encoder coupled to the input end of an interconnect.

[0046] Example 13: The method according to Example 12, further comprising transferring any protection information received at the input end of the interconnect directly to the output end of the interconnect by a sideband signal.

[0047] Example 14: The method according to Example 13, wherein the received protection information is a parity bit, an error detection code (EDC), or an error correction code (ECC).

[0048] Example 15: The method according to Example 12, further comprising performing inspection of grouped and protected information by a decoder coupled to the output terminal of an interconnect.

[0049] Example 16: The method according to Example 15, further comprising outputting an alarm signal if the inspection by the decoder of grouped and protected information fails.

[0050] Example 17: The method according to Example 12, wherein applying protection to grouped and sized information includes applying an error detection code (EDC) or an error correction code (ECC).

[0051] Example 18: The method according to Example 12, further comprising receiving injection errors at the input end of the interconnect for testing the interconnect.

[0052] Example 19: The method according to Example 12, wherein the channel is a write address channel, a write data channel, a write response channel, a read address channel, or a read data channel.

[0053] Example 20: The method described in Example 12, which includes bit insertion, to resize grouped information to a common width.

[0054] While the above has been described in relation to exemplary embodiments, please understand that the term “exemplary” means merely illustrative rather than best or optimal. Therefore, this disclosure is intended to cover alternatives, modifications, and equivalents, which may be included within the scope of this disclosure.

[0055] While specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art that various alternative and / or equivalent embodiments can be substituted for the specific embodiments illustrated and described without departing from the scope of this disclosure. This disclosure is intended to cover any application or variation of any specific embodiment discussed herein.

Claims

1. An interconnect, wherein the interconnect is An input terminal that can be connected to the source, An encoder coupled to the input terminal, Equipped with, The encoder described above is The information received from the aforementioned source via the same channel is grouped together. The grouped information is resized to a common width. Apply protection to the grouped and sized information. It is configured in such a way, The interconnect is configured to directly transfer any protection information received at the input terminal to the output terminal of the interconnect via a sideband signal. Interconnect.

2. The received protection information is a parity bit, an error detection code (EDC), or an error correction code (ECC). The interconnect according to claim 1.

3. The aforementioned interconnect is, The decoder further comprises a decoder coupled to the output terminal of the interconnect and configured to perform inspection of the grouped and protected information. The interconnect according to claim 1.

4. The decoder is configured to output an alarm signal if the inspection of the grouped and protected information fails. The interconnect according to claim 3.

5. The encoder protection configured to be applied to the grouped and sized information is an error detection code (EDC) or error correction code (ECC). The interconnect according to claim 1.

6. The interconnect is configured to communicate with any source or destination configured by the AMBA (Advanced Microcontroller Bus Architecture) AXI (Advanced eXtensible Interface) protocol. The interconnect according to claim 1.

7. The interconnect is configured to receive injection errors at the input terminal for testing the interconnect. The interconnect according to claim 1.

8. The channel is a write address channel, a write data channel, a write response channel, a read address channel, or a read data channel. The interconnect according to claim 1.

9. The encoder is configured to resize the grouped information to the common width by bit insertion. The interconnect according to claim 1.

10. A microcontroller comprising the interconnect described in claim 1.

11. A method for interconnecting information between a sender and a recipient, wherein the method is: The steps include: grouping information received at the interconnect input terminal from the source via the same channel; The steps include: setting the grouped information to a common width, The steps include applying protection to the grouped and sized information using an encoder coupled to the input terminal of the interconnect, The steps include: directly transferring any protection information received at the input terminal of the interconnect to the output terminal of the interconnect via a sideband signal; A method that includes this.

12. The received protection information is a parity bit, an error detection code (EDC), or an error correction code (ECC). The method according to claim 11.

13. The aforementioned method, The step further includes performing an inspection of the grouped and protected information by a decoder coupled to the output terminal of the interconnect, The method according to claim 11.

14. The aforementioned method, The further step includes outputting an alarm signal if the decoder fails to inspect the grouped and protected information, The method according to claim 13.

15. The step of applying protection to the grouped and sized information includes the step of applying an error detection code (EDC) or an error correction code (ECC), The method according to claim 11.

16. The aforementioned method, The process further includes receiving injection errors at the input terminal of the interconnect to test the interconnect, The method according to claim 11.

17. The channel is a write address channel, a write data channel, a write response channel, a read address channel, or a read data channel. The method according to claim 11.

18. The step of resizing the grouped information to the common width includes bit insertion, The method according to claim 11.

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