Power supply unit and semiconductor device

Abstract

To suitably control supply of a power supply voltage to a circuit.SOLUTION: A power supply device comprises a switching circuit, a first control circuit, a second control circuit, and reset wiring. The switching circuit is provided between a regulator circuit and a terminal and switched to a first state where a second power supply voltage is supplied to the terminal or a second state where the supply of the second power supply voltage to the terminal is blocked. The first control circuit outputs a reset signal to have a first potential in a case where the switching circuit can be switched to the first state or the second state and to have a second potential in a case where the switching circuit is to be switched to the second state. The second control circuit performs control to switch the switching circuit to the first state or the second state in a case where the reset signal is at the first potential. The reset wiring transfers the reset signal from the first control circuit to the switching circuit. The switching circuit is switched to the second state when the reset signal is at the second potential.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments relate to a power supply device and a semiconductor device.

Background Art

[0002] There is a semiconductor device including a digital circuit such as a logic circuit or an analog circuit, and a voltage regulator that generates an internal power supply voltage supplied to these circuits. In such a semiconductor device, a PSW (power switch) may be disposed between the digital circuit or analog circuit and the voltage regulator. The PSW cuts off the supply of the internal power supply voltage to a part of the circuits included in the semiconductor device during standby or the like of the semiconductor device. Thereby, the semiconductor device can reduce unnecessary power consumption such as leakage current during standby and achieve low power consumption. Further, the semiconductor device includes a PSW control circuit that switches the PSW at an appropriate timing. The PSW control circuit is driven by the internal power supply voltage generated by the voltage regulator.

[0003] At the time of starting up the semiconductor device, the voltage regulator raises the internal power supply voltage from the ground potential to the target potential of the output voltage over time. The internal power supply voltage generated from the voltage regulator is supplied to the PSW control circuit and the like even during startup. In order to operate the PSW appropriately, it is required to design the semiconductor device so that the internal power supply voltage surely rises to the normal operating potential even at the time of startup.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] One embodiment aims to provide a power supply device and a semiconductor device that can suitably control the supply of power voltage to a circuit. [Means for solving the problem]

[0006] According to one embodiment, a power supply device is provided. The power supply device comprises a regulator circuit, terminals, a switching circuit, an output circuit, a control circuit, a reset wiring, a reset circuit, and a reset switch. The regulator circuit generates a stabilized second power supply voltage based on an input first power supply voltage, even if there are fluctuations in power consumption. The terminals output the second power supply voltage. The switching circuit is provided between the regulator circuit and the terminals and switches between a first state in which the second power supply voltage is supplied to the terminals, and a second state in which the supply of the second power supply voltage to the terminals is cut off. The output circuit is driven by the second power supply voltage and outputs a reset signal that is at a first potential when the switching circuit can be switched to the first or second state, and at a second potential different from the first potential when the switching circuit is in the second state. The control circuit is driven by the second power supply voltage and, when the reset signal is at the first potential, performs control to switch the switching circuit to the first or second state. The reset wiring transfers the reset signal from the output circuit to the switching circuit without going through the control circuit. The reset circuit is driven by the first power supply voltage and outputs a pre-reset signal that sets the reset signal to the first potential. The reset switch short-circuits the reset wiring and the potential corresponding to the second potential when the pre-reset signal is not output, and blocks the connection between the reset wiring and the potential corresponding to the second potential when the pre-reset signal is output. The control circuit outputs a control signal that becomes an H logic potential when the reset signal is at the second potential, and an L logic potential lower than the H logic potential or the H logic potential when the reset signal is at the first potential.The switching circuit includes a voltage input terminal to which the second power supply voltage generated from the regulator circuit is supplied, a main switch which is a MOSFET that receives the control signal output from the control circuit at its gate, short-circuits the voltage input terminal and the terminal when the gate is at the L logic potential, and blocks the connection between the voltage input terminal and the terminal when the gate is at the H logic potential, and an auxiliary switch which is a MOSFET that receives the reset signal at its gate via the reset wiring, blocks the connection between the gate of the main switch and the voltage input terminal when the gate is at the first potential, and short-circuits the gate of the main switch and the voltage input terminal when the gate is at the second potential. The second power supply voltage is the H logic potential. Equivalent to . [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows the configuration of a semiconductor device according to the first embodiment. [Figure 2] Figure 2 shows the changes in the external power supply voltage and internal power supply voltage during startup. [Figure 3] Figure 3 shows the configuration of a semiconductor device according to the second embodiment. [Figure 4] Figure 4 shows the configuration of the sub-switching circuit. [Figure 5] Figure 5 shows the configuration of a switching circuit according to the second embodiment. [Figure 6] Figure 6 shows an example of the arrangement of the power supply circuit according to the second embodiment on a semiconductor chip. [Figure 7] Figure 7 shows the configuration of the power supply circuit according to the third embodiment. [Figure 8] Figure 8 shows an example of the arrangement of the power supply circuit according to the third embodiment on a semiconductor chip. [Figure 9] Figure 9 shows the configuration of the switching circuit according to the fourth embodiment. [Figure 10] Figure 10 shows the configuration of the power supply circuit according to the fifth embodiment. [Figure 11] Figure 11 shows the configuration of a memory system to which the power supply circuits according to the first to fifth embodiments are applied. [Modes for carrying out the invention]

[0008] Embodiments will be described in detail below with reference to the attached drawings. However, the present invention is not limited by these embodiments.

[0009] (First Embodiment) Figure 1 is a diagram showing the configuration of the semiconductor device 10 according to the first embodiment.

[0010] The semiconductor device 10 according to the first embodiment includes a target circuit 12 and a power supply circuit 20.

[0011] The target circuit 12 is supplied with an internal power supply voltage VDDC (second power supply voltage) from the power supply circuit 20 and is driven by the internal power supply voltage VDDC. In this embodiment, the target circuit 12 is a digital circuit such as a logic circuit or an analog circuit such as a memory circuit. The target circuit 12 may also be a circuit in which digital and analog circuits are mixed.

[0012] The power supply circuit 20 is supplied with an external power supply voltage VCC (first power supply voltage). The power supply circuit 20 supplies an internal power supply voltage VDDC to the target circuit 12. The power supply circuit 20 is an example of a power supply device. The power supply circuit 20 may be mounted on a chip separate from the target circuit 12. Furthermore, the power supply circuit 20 may be composed of one chip, multiple chips, or discrete circuits.

[0013] The power supply circuit 20 includes terminals 21, a voltage regulator 22 (regulator circuit), a switching circuit 24, a reset circuit 26, an output circuit 28, a control circuit 30, a reset wiring 32, and a reset switch 34. The output circuit 28 and the reset switch 34 correspond to the first control circuit. The control circuit 30 corresponds to the second control circuit.

[0014] Terminal 21 is connected to the target circuit 12. The internal power supply voltage VDDC generated by the power supply circuit 20 is supplied to the target circuit 12 via terminal 21.

[0015] The voltage regulator 22 is supplied with an external power supply voltage VCC. Based on the input external power supply voltage VCC, the voltage regulator 22 generates an internal power supply voltage VDDC to be output externally. The internal power supply voltage VDDC is supplied to the output circuit 28 and the control circuit 30. The internal power supply voltage VDDC is further supplied to the target circuit 12 via the switching circuit 24. The voltage regulator 22 stabilizes the internal power supply voltage VDDC at a predetermined potential. The predetermined potential is the target potential of the voltage output by the voltage regulator 22. Hereinafter, this potential is referred to as the normal operating potential. Thereby, even if the power consumption of the target circuit 12 fluctuates, the target circuit 12 can receive the internal power supply voltage VDDC stabilized at the normal operating potential.

[0016] The switching circuit 24 is provided between the voltage regulator 22 and the terminal 21. The switching circuit 24 switches to an on state (first state) in which the internal power supply voltage VDDC generated from the voltage regulator 22 is supplied to the terminal 21, or an off state (second state) in which the supply of the internal power supply voltage VDDC to the terminal 21 is cut off. That is, the on state is the output state of the internal power supply voltage VDDC, and the off state is the cut-off state of the internal power supply voltage VDDC. Note that the first state is a state in which the internal power supply voltage VDDC can be supplied to the target circuit 12 via the terminal 21, and the second state is a state in which the internal power supply voltage VDDC cannot be supplied to the target circuit 12 via the terminal 21.

[0017] For example, the switching circuit 24 includes a voltage input terminal 42 and a voltage output terminal 44. The voltage input terminal 42 is connected to the voltage regulator 22. The voltage input terminal 42 receives the internal power supply voltage VDDC from the voltage regulator 22. The voltage output terminal 44 is connected to the target circuit 12 via the terminal 21. The voltage output terminal 44 supplies the internal power supply voltage VDDC received from the voltage input terminal 42 to the target circuit 12 via the terminal 21. The switching circuit 24 short - circuits between the voltage input terminal 42 and the voltage output terminal 44 in the on - state. The switching circuit 24 disconnects between the voltage input terminal 42 and the voltage output terminal 44 in the off - state.

[0018] The switching circuit 24 is connected to the control circuit 30. The switching circuit 24 switches between the on - state and the off - state according to the control by the control circuit 30. In the present embodiment, the switching circuit 24 switches between the on - state and the off - state according to the potential of the control signal CT output from the control circuit 30. Also, the switching circuit 24 is connected to the reset switch 34 via the reset wiring 32. The switching circuit 24 becomes a state where it switches between the on - state and the off - state by the control signal CT or a state where it is forced to be in the off - state according to the reset signal RS received from the reset wiring 32. More specifically, when the reset signal RS is at the first potential, the switching circuit 24 becomes a state where it switches between the on - state and the off - state by the control signal CT. Also, when the reset signal RS is at a second potential different from the first potential, the switching circuit 24 is forced to be in the off - state. In the present embodiment, the second potential is the ground potential. The first potential is a potential higher than the ground potential and is, for example, the H - logic potential.

[0019] The reset circuit 26 is driven by an external power supply voltage VCC. The reset circuit 26 outputs a pre-reset signal PR that sets the reset signal RS to either a first or second potential. In this embodiment, the pre-reset signal PR becomes a high logic potential when the reset signal RS is set to the first potential. The pre-reset signal PR becomes a low logic potential when the reset signal RS is set to the second potential (ground potential in this embodiment). The high logic potential is the potential that turns on the N-channel MOSFET and turns off the P-channel MOSFET. The low logic potential is lower than the high logic potential and is the potential that turns off the N-channel MOSFET and turns on the P-channel MOSFET.

[0020] The output circuit 28 is connected to the reset circuit 26, the reset wiring 32, and the reset switch 34. The output circuit 28 outputs a reset signal RS to the reset wiring 32. The reset signal RS is at the first potential when the switching circuit 24 can be switched to the first or second state. The reset signal RS is at the second potential, corresponding to the ground potential, when the switching circuit 24 is forcibly turned off.

[0021] The output circuit 28 receives a pre-reset signal PR from the reset circuit 26. The output circuit 28 outputs a forced reset signal CR to the reset switch 34. For example, the output circuit 28 includes a first buffer circuit 52 and a second buffer circuit 54.

[0022] The first buffer circuit 52 is driven by the internal power supply voltage VDDC. The first buffer circuit 52 receives a pre-reset signal PR and outputs a reset signal RS having the same logic potential as the pre-reset signal PR. Specifically, if the pre-reset signal PR is a logic (H logic potential in this embodiment) indicating that the internal power supply voltage VDDC can be supplied to the target circuit 12, the first buffer circuit 52 outputs a reset signal RS at a first potential. Also, if the pre-reset signal PR is a logic (L logic potential in this embodiment) indicating that the supply of the internal power supply voltage VDDC to the target circuit 12 is cut off, the first buffer circuit 52 outputs a reset signal RS at a second potential (ground potential). Note that the first buffer circuit 52 receives a signal from the reset circuit 26, which is driven by the external power supply voltage VCC, so the voltage withstand capability of the input terminal is high.

[0023] The second buffer circuit 54 is driven by an external power supply voltage VCC. The second buffer circuit 54 receives a pre-reset signal PR and outputs a forced reset signal CR having a logic potential inverted from the logic potential of the pre-reset signal PR. If the pre-reset signal PR is a logic (H logic potential in this embodiment) indicating that the internal power supply voltage VDDC can be supplied to the target circuit 12, the second buffer circuit 54 sets the forced reset signal CR to a potential (L logic potential) that turns off the N-channel MOSFET. Also, if the pre-reset signal PR is a logic (L logic potential in this embodiment) indicating that the supply of the internal power supply voltage VDDC to the target circuit 12 is cut off, the second buffer circuit 54 sets the forced reset signal CR to a potential (H logic potential) that turns on the N-channel MOSFET.

[0024] The control circuit 30 is driven by the internal power supply voltage VDDC. The control circuit 30 receives a reset signal RS from the output circuit 28. If the received reset signal RS is at the first potential, the control circuit 30 performs control to switch the switching circuit 24 to the ON state or the OFF state. If the received reset signal RS is at the second potential (ground potential in this embodiment), the control circuit 30 controls the switching circuit 24 to the OFF state. The control circuit 30 also outputs a control signal CT to the switching circuit 24. The control signal CT becomes a high logic potential when the reset signal RS is at the ground potential corresponding to the second potential. The control signal CT can be set to a high logic potential or a low logic potential when the reset signal RS is at the first potential. The switching circuit 24 is in the OFF state when the control signal CT is at the high logic potential, and in the ON state when the control signal CT is at the low logic potential.

[0025] Such a control circuit 30 switches the switching circuit 24 to the off state, for example, during standby mode or when the target circuit 12 is not operating. As a result, the control circuit 30 can reduce the power consumption of the semiconductor device 10 by eliminating leakage current during standby mode or when the target circuit 12 is not operating.

[0026] The reset wiring 32 is located between the output circuit 28 and the switching circuit 24. The reset wiring 32 transfers the reset signal RS output from the output circuit 28 to the switching circuit 24 without going through the control circuit 30.

[0027] The reset switch 34 is provided between the reset wiring 32 and the potential corresponding to the second potential. In this embodiment, the reset switch 34 short-circuits or interrupts the connection between the reset wiring 32 and the ground potential corresponding to the second potential. The reset switch 34 is connected to the output circuit 28. The reset switch 34 switches in accordance with the forced reset signal CR output from the second buffer circuit 54, which is driven by the external power supply voltage VCC. Specifically, the reset switch 34 interrupts the connection between the reset wiring 32 and the ground potential when the forced reset signal CR is an L logic potential. That is, the reset switch 34 interrupts the connection between the reset wiring 32 and the ground potential when the pre-reset signal PR is a logic (H logic potential in this embodiment) indicating that the internal power supply voltage VDDC can be supplied to the target circuit 12. Also, the reset switch 34 short-circuits the connection between the reset wiring 32 and the ground potential when the forced reset signal CR is an H logic potential. In other words, if the pre-reset signal PR is a logic (L logic potential in this embodiment) that indicates interrupting the supply of the internal power supply voltage VDDC to the target circuit 12, the reset switch 34 short-circuits the reset wiring 32 and the ground potential.

[0028] For example, the reset switch 34 is an N-channel MOSFET. In this case, the drain of the reset switch 34 is connected to the reset wiring 32, and the source is connected to ground potential. The reset switch 34 is then subjected to a forced reset signal CR at its gate.

[0029] Such a reset switch 34 can connect the reset wiring 32 to ground potential via a second buffer circuit 54 driven by an external power supply voltage VCC. In other words, the reset switch 34 can forcibly set the reset signal RS to ground potential when the pre-reset signal PR is a logic (L logic potential in this embodiment) indicating that the supply of the internal power supply voltage VDDC to the target circuit 12 is interrupted. As a result, the reset switch 34 can forcibly set the reset signal RS to ground potential even when the control circuit 30 does not operate because the internal power supply voltage VDDC is lower than the normal operating potential.

[0030] The reset signal RS is received by the switching circuit 24. The switching circuit 24 switches to the off state regardless of control by the control circuit 30 if the reset signal RS received from the reset wiring 32 is at ground potential. In other words, even if the control circuit 30 does not operate because the internal power supply voltage VDDC is lower than the normal operating potential, the switching circuit 24 will switch to the off state if the reset signal RS received via the reset wiring 32 is at ground potential, thereby cutting off the supply of the internal power supply voltage VDDC to the target circuit 12.

[0031] In this embodiment, the switching circuit 24 includes a main switch 56 and an auxiliary switch 58. The switching circuit 24 also includes a signal input terminal 48. The signal input terminal 48 is supplied with a control signal CT output from the control circuit 30.

[0032] The main switch 56 short-circuits or disconnects the voltage input terminal 42 and the voltage output terminal 44 in accordance with the control signal CT applied to the signal input terminal 48. Specifically, the main switch 56 short-circuits the voltage input terminal 42 and the voltage output terminal 44 when the control signal CT is at an L logic potential. Also, the main switch 56 disconnects the voltage input terminal 42 and the voltage output terminal 44 when the control signal CT is at an H logic potential. For example, the main switch 56 is a P-channel MOSFET. In this case, the source of the main switch 56 is connected to the voltage input terminal 42, the drain is connected to the voltage output terminal 44, and the control signal CT is applied to the gate.

[0033] The auxiliary switch 58 receives the reset signal RS via the reset wiring 32. That is, the auxiliary switch 58 directly receives the reset signal RS supplied via the reset wiring 32 without going through the control circuit 30. Then, depending on the reset signal RS it receives, the auxiliary switch 58 short-circuits or disconnects the connection between the input terminal of the control signal CT and the voltage input terminal 42 of the main switch 56. Specifically, when the reset signal RS is at the first potential, the auxiliary switch 58 disconnects the connection between the input terminal of the control signal CT and the voltage input terminal 42 of the main switch 56. Also, when the reset signal RS is at the second potential (ground potential), the auxiliary switch 58 short-circuits the connection between the input terminal of the control signal CT and the voltage input terminal 42 of the main switch 56. For example, the auxiliary switch 58 is a P-channel MOSFET. In this case, the source of the auxiliary switch 58 is connected to the voltage input terminal 42, and the drain is connected to the input terminal (gate) of the control signal CT of the main switch 56. The gate of the auxiliary switch 58 is connected to the reset wiring 32, and the reset signal RS is supplied to the gate.

[0034] As a result, when the reset signal RS is at the first potential, the auxiliary switch 58 disconnects the connection between the input terminal (gate) of the control signal CT in the main switch 56 and the voltage input terminal 42. Therefore, when the reset signal RS is at the first potential, the main switch 56 short-circuits or disconnects the connection between the voltage input terminal 42 and the voltage output terminal 44 in accordance with the control signal CT provided by the control circuit 30. In other words, when the reset signal RS is at the first potential, the switching circuit 24 switches to an ON state or an OFF state in accordance with the control by the control circuit 30.

[0035] Furthermore, when the reset signal RS is at the second potential (ground potential), the auxiliary switch 58 short-circuits the input terminal (gate) of the control signal CT in the main switch 56 and the voltage input terminal 42 (source). When the gate and source of the main switch 56 are short-circuited, the internal power supply voltage VDDC is applied to the gate of the main switch 56. That is, when the gate and source of the main switch 56 are short-circuited, a high logic potential is applied to the gate of the main switch 56. When a high logic potential is applied to the gate of the main switch 56, the main switch 56 disconnects the connection between the voltage input terminal 42 and the voltage output terminal 44. In other words, when the reset signal RS is at ground potential, the switching circuit 24 switches to the off state regardless of the control signal CT, that is, regardless of the control by the control circuit 30. Therefore, when the reset signal RS is at ground potential, the switching circuit 24 can forcibly cut off the supply of the internal power supply voltage VDDC to the target circuit 12.

[0036] Figure 2 shows the changes in the external power supply voltage VCC and the internal power supply voltage VDDC during startup of the semiconductor device 10.

[0037] During startup of the semiconductor device 10, the external power supply voltage VCC rises from ground potential (0V) over time, as shown in Figure 2A, and stabilizes when it reaches a predetermined voltage value. During startup, if normal, the internal power supply voltage VDDC rises from ground potential (0V) over time, following the external power supply voltage VCC, as shown in Figure 2B, after the external power supply voltage VCC has risen to a certain extent, and stabilizes at the normal operating potential (normal value) after a predetermined time has elapsed.

[0038] However, during startup, the internal power supply voltage VDDC passes through a voltage that prevents the control circuit 30 from operating as it rises from ground potential (0V) to normal operating potential. If the switching circuit 24 were to turn on during this period when the control circuit 30 is unable to operate, the target circuit 12 would operate and current would begin to flow, potentially balancing the generated current with the amount of current that the voltage regulator 22 can supply. In this case, if the current generated by the switching circuit 24 turning on during the period when the control circuit 30 is unable to operate balances the amount of current that the voltage regulator 22 can supply, the internal power supply voltage VDDC will stabilize at a potential lower than the normal operating potential (an abnormal value), as shown in Figure 2C. In such a case, the control circuit 30 will not operate and will not be able to control the switching circuit 24 to the off state.

[0039] In contrast, the power supply circuit 20 according to this embodiment includes a reset wire 32 that transfers the reset signal RS to the switching circuit 24 without going through the control circuit 30. The switching circuit 24 can be forcibly switched to the off state by the reset signal RS received from the reset wire 32, regardless of control by the control circuit 30. As a result, even if the control circuit 30 does not operate because the internal power supply voltage VDDC is at a lower potential than the desired potential, the power supply circuit 20 can turn off the switching circuit 24 and cut off the supply of the internal power supply voltage VDDC to the target circuit 12. Therefore, the power supply circuit 20 can reliably raise the internal power supply voltage VDDC to the normal operating potential, for example, during startup.

[0040] Furthermore, the power supply circuit 20 according to this embodiment includes a reset switch 34 that short-circuits or interrupts the connection between the reset wiring 32 and the ground potential. The reset switch 34 is switched by a circuit driven by an external power supply voltage VCC, for example, by a forced reset signal CR output from a second buffer circuit 54 in the output circuit 28. The switching circuit 24 switches to the off state regardless of control by the control circuit 30 when the reset signal RS received from the reset wiring 32 is at the second potential (ground potential).

[0041] The external power supply voltage VCC reliably rises to a predetermined potential during startup, even if the internal power supply voltage VDDC is at a low potential. Therefore, the second buffer circuit 54 in the output circuit 28, which is driven by the external power supply voltage VCC, can reliably operate even if the internal power supply voltage VDDC is at a potential lower than the normal operating potential. As a result, the power supply circuit 20 can reliably set the reset signal RS to ground potential and turn off the switching circuit 24, even if the internal power supply voltage VDDC is at a potential lower than the normal operating potential.

[0042] As described above, the power supply circuit 20 according to this embodiment can reliably cut off the supply of the internal power supply voltage VDDC to the target circuit 12 even when the internal power supply voltage VDDC is at a low potential. As a result, the power supply circuit 20 can reliably raise the internal power supply voltage VDDC to the normal operating potential, for example, during startup, and avoid the internal power supply voltage VDDC stabilizing at a low voltage. Therefore, the power supply circuit 20 can be designed without considering the circuit operation when the internal power supply voltage VDDC is at a low voltage, such as malfunctions and leakage currents in the control circuit 30 and switching circuit 24, as well as the supplyable current characteristics of the voltage regulator 22. As a result, the power supply circuit 20 can be designed more easily.

[0043] (Second Embodiment) Figure 3 shows the configuration of the semiconductor device 10a according to the second embodiment. The power supply circuit 20a of the semiconductor device 10a according to the second embodiment has substantially the same function and configuration as the power supply circuit 20 of the semiconductor device 10 according to the first embodiment. In the description of the semiconductor device 10a of the second embodiment, circuits and signals etc. that have the same function and configuration as those of the first embodiment are given the same reference numerals, and detailed explanations are omitted except for differences.

[0044] In the second embodiment, the power supply circuit 20a includes a switching circuit 24a instead of the switching circuit 24 according to the first embodiment. The switching circuit 24a includes a plurality of sub-switching circuits 60. For example, the switching circuit 24a includes m (where m is an integer of 1 or more) × n (where n is an integer of 2 or more) sub-switching circuits 60. Each of the plurality of sub-switching circuits 60 (for example, m × n sub-switching circuits 60) is provided between the voltage input terminal 42 and the voltage output terminal 44. That is, each of the m × n sub-switching circuits 60 is provided between the voltage regulator 22 and terminal 21. Furthermore, each of the plurality of sub-switching circuits 60 (for example, m × n sub-switching circuits 60) is connected to the control circuit 30. Furthermore, each of the plurality of sub-switching circuits 60 (for example, m × n sub-switching circuits 60) is connected to the reset switch 34 via the reset wiring 32.

[0045] Each of the multiple sub-switching circuits 60 operates in the same way as the switching circuit 24 in the first embodiment. Each of the multiple sub-switching circuits 60 switches between an ON state, which supplies the internal power supply voltage VDDC generated from the voltage regulator 22 to terminal 21, and an OFF state, which cuts off the supply of the internal power supply voltage VDDC to terminal 21. Specifically, in the ON state, each of the multiple sub-switching circuits 60 short-circuits the voltage input terminal 42 and the voltage output terminal 44. In the OFF state, each of the multiple sub-switching circuits 60 cuts off the connection between the voltage input terminal 42 and the voltage output terminal 44.

[0046] Each of the multiple sub-switching circuits 60 switches to an on state or an off state depending on the potential of the control signal CT output from the control circuit 30. Each of the multiple sub-switching circuits 60 is in an off state when the control signal CT is at a high logic potential, and in an on state when the control signal CT is at a low logic potential.

[0047] Furthermore, each of the multiple sub-switching circuits 60 receives a reset signal RS supplied via the reset wiring 32. Then, each of the multiple sub-switching circuits 60 switches to an ON state or an OFF state, or is forcibly turned OFF, depending on the reset signal RS received from the reset wiring 32. More specifically, each of the multiple sub-switching circuits 60 switches to an ON state or an OFF state, depending on the control signal CT, when the reset signal RS is at the first potential. Also, each of the multiple sub-switching circuits 60 is forcibly turned OFF when the reset signal RS is at the second potential (ground potential). As a result, even if the control circuit 30 does not operate because the internal power supply voltage VDDC is lower than the normal operating potential, each of the multiple sub-switching circuits 60 will turn OFF if the reset signal RS received via the reset wiring 32 is at the second potential (ground potential), thereby cutting off the supply of the internal power supply voltage VDDC to the target circuit 12.

[0048] Figure 4 shows the configuration of the sub-switching circuit 60. The sub-switching circuit 60 includes a main switch 56, an auxiliary switch 58, and a transfer buffer circuit 62.

[0049] The main switch 56 short-circuits or disconnects the voltage input terminal 42 and the voltage output terminal 44 in accordance with the control signal CT. Specifically, the main switch 56 short-circuits the voltage input terminal 42 and the voltage output terminal 44 when the control signal CT is at an L logic potential. The main switch 56 disconnects the voltage input terminal 42 and the voltage output terminal 44 when the control signal CT is at an H logic potential. For example, the main switch 56 is a P-channel MOSFET. In this case, the source of the main switch 56 is connected to the voltage input terminal 42 and the drain is connected to the voltage output terminal 44. The control signal CT is then applied to the gate of the main switch 56. As a result, the sub-switching circuit 60 can be switched to the ON state when the control signal CT is at an L logic potential. The sub-switching circuit 60 can also be switched to the OFF state when the control signal CT is at an H logic potential.

[0050] The auxiliary switch 58 receives a reset signal RS via the reset wiring 32. Depending on the received reset signal RS, the auxiliary switch 58 short-circuits or disconnects the gate, which is the input terminal for the control signal CT in the main switch 56, from the source, which is connected to the voltage input terminal 42. Specifically, the auxiliary switch 58 disconnects the gate and source of the main switch 56 when the reset signal RS is at a first potential. Furthermore, the auxiliary switch 58 short-circuits the gate and source of the main switch 56 when the reset signal RS is at a second potential (ground potential). For example, the auxiliary switch 58 is a P-channel MOSFET. In this case, the source of the auxiliary switch 58 is connected to the voltage input terminal 42, and the drain is connected to the gate of the main switch 56. The gate of the auxiliary switch 58 is connected to the reset wiring 32, and the reset signal RS is applied to the gate.

[0051] As a result, the auxiliary switch 58 disconnects the gate and source of the main switch 56 when the reset signal RS is at the first potential. Therefore, when the reset signal RS is at the first potential, the main switch 56 short-circuits or disconnects the voltage input terminal 42 and the voltage output terminal 44 in accordance with the control signal CT provided by the control circuit 30. As a result, the sub-switching circuit 60 switches to an ON state or an OFF state in accordance with the control by the control circuit 30 when the reset signal RS is at the first potential.

[0052] Furthermore, the auxiliary switch 58 short-circuits the gate and source of the main switch 56 when the reset signal RS is at the second potential. When the gate and source of the main switch 56 are short-circuited, the internal power supply voltage VDDC is applied to the gate of the main switch 56. That is, when the gate and source of the main switch 56 are short-circuited, a high logic potential is applied to the gate of the main switch 56. When a high logic potential is applied to the gate of the main switch 56, the main switch 56 disconnects the connection between the voltage input terminal 42 and the voltage output terminal 44. As a result, when the reset signal RS is at the second potential, the sub-switching circuit 60 switches to the off state regardless of control by the control circuit 30. Therefore, when the reset signal RS is at the second potential, the sub-switching circuit 60 can forcibly cut off the supply of the internal power supply voltage VDDC to the target circuit 12.

[0053] The transfer buffer circuit 62 receives the control signal CT, buffers it, and outputs it. The transfer buffer circuit 62 outputs the received control signal CT with a predetermined time delay. The transfer buffer circuit 62 may receive the control signal CT from the control circuit 30, or it may receive the control signal CT output from another sub-switching circuit 60. The gate of the main switch 56 may be supplied with the control signal CT output from the output terminal of the transfer buffer circuit 62, or it may be supplied with the control signal CT supplied to the input terminal of the transfer buffer circuit 62.

[0054] Figure 5 shows the configuration of the switching circuit 24a according to the second embodiment. The multiple sub-switching circuits 60 are divided into multiple groups, each containing two or more sub-switching circuits 60. For example, in the example of Figure 5, each of the n groups contains m sub-switching circuits 60.

[0055] Two or more sub-switching circuits 60 included in each of the multiple groups are connected in a cascade to sequentially transfer the control signal CT. For example, in the example in Figure 5, m sub-switching circuits 60 are connected in a cascade to sequentially transfer the control signal CT.

[0056] The first of two or more sub-switching circuits 60 connected in a cascade receives a control signal CT from the control circuit 30. Each of the two or more sub-switching circuits 60 then outputs a control signal CT to the next sub-switching circuit 60 via the transfer buffer circuit 62. That is, each of the two or more sub-switching circuits 60 outputs the received control signal CT to the next sub-switching circuit 60 after a predetermined delay. With this configuration, the two or more sub-switching circuits 60 included in each of the multiple groups can have their switching timings between the on and off states staggered by a predetermined amount of time.

[0057] Furthermore, the switching circuit 24a may include different signal input terminals 48 for each of the multiple groups. For example, in the example in Figure 5, the switching circuit 24a includes the first signal input terminal 48-1 to the nth signal input terminal 48-n.

[0058] Furthermore, the control circuit 30 may provide different control signals CT to each of the multiple groups. In this case, the control circuit 30 can make the output timing of the control signals CT different for each of the multiple groups. For example, the control circuit 30 outputs the control signals CT with a predetermined time difference for each group, or for each predetermined number of groups. This allows the control circuit 30 to shift the switching timing between the on state and the off state by a predetermined time for each group, or for each predetermined number of groups.

[0059] A switching circuit 24a with this configuration can increase the current by a predetermined amount over time when supplying the internal power supply voltage VDDC from the voltage regulator 22 to the target circuit 12. Conversely, when the supply of the internal power supply voltage VDDC from the voltage regulator 22 to the target circuit 12 is interrupted, the switching circuit 24a can decrease the current by a predetermined amount over time.

[0060] Figure 6 shows an example of the arrangement of the power supply circuit 20a on the semiconductor chip 70 according to the second embodiment. Note that Figure 6 does not show the target circuit 12, voltage regulator 22, wiring for transmitting the external power supply voltage VCC, and wiring for transmitting the internal power supply voltage VDDC, etc., but these are formed in any region of the die of the semiconductor chip 70.

[0061] The switching circuit 24a is divided into, for example, a plurality of distributed switching circuits 72. Each of the plurality of distributed switching circuits 72 includes a plurality of sub-switching circuits 60 that are included in one or more groups.

[0062] Each of the multiple distributed switching circuits 72 is distributed and positioned at different locations on the die of the semiconductor chip 70. The reset wiring 32 electrically connects the region where the output circuit 28 and reset switch 34 are formed with the multiple regions where each of the multiple distributed switching circuits 72 is provided.

[0063] Here, each of the multiple distributed switching circuits 72 includes, for example, a number of MOSFETs that constitute an auxiliary switch 58. In each of the multiple distributed switching circuits 72, a number of MOSFETs are switched in response to a reset signal RS. Therefore, when the level of the reset signal RS changes, a very large inrush current flows through the reset wiring 32. Accordingly, the reset wiring 32 is formed with a sufficiently wide wiring width so that a sufficiently large current can flow when the level of the reset signal RS changes.

[0064] (Third embodiment) Figure 7 shows the configuration of the power supply circuit 20b according to the third embodiment. The power supply circuit 20b provided in the semiconductor device 10b according to the third embodiment has substantially the same function and configuration as the power supply circuit 20a provided in the semiconductor device 10a according to the second embodiment. In the description of the semiconductor device 10b of the third embodiment, circuits and signals etc. that have the same function and configuration as those of the second embodiment are given the same reference numerals, and detailed explanations are omitted except for differences.

[0065] The power supply circuit 20b according to the third embodiment includes, in addition to the configuration of the power supply circuit 20a according to the second embodiment, a plurality of distributed output circuits 74 and a plurality of distributed reset switches 76. In the third embodiment, the power supply circuit 20b includes a switching circuit 24b instead of the switching circuit 24a according to the second embodiment. Furthermore, the power supply circuit 20b according to the third embodiment includes a plurality of distributed reset wires 78 and a pre-reset wire 80 instead of the reset wire 32.

[0066] The pre-reset wiring 80 transfers the pre-reset signal PR output from the reset circuit 26 to each of the multiple distributed output circuits 74.

[0067] The switching circuit 24b, like the switching circuit 24a in the second embodiment, includes m × n sub-switching circuits 60. The multiple sub-switching circuits 60 included in the switching circuit 24b are divided into multiple groups. For example, the m × n sub-switching circuits 60 are divided into n groups, each containing m sub-switching circuits 60. Two or more sub-switching circuits 60 included in each group correspond to any one of the multiple distributed output circuits 74. The two or more sub-switching circuits 60 included in each group are connected to the corresponding distributed output circuit 74 from the multiple distributed output circuits 74 via one of the multiple distributed reset wirings 78. Instead of receiving a reset signal RS from the reset wiring 32, the two or more sub-switching circuits 60 included in each group receive a distributed reset signal DR via the connected distributed reset wiring 78.

[0068] Each of the multiple distributed output circuits 74 corresponds to one of several groups obtained by dividing the multiple sub-switching circuits 60 included in the switching circuit 24b. Each of the multiple distributed output circuits 74 may correspond to one of the multiple groups, or to two or more predetermined groups.

[0069] Each of the multiple distributed output circuits 74 has the same configuration as the output circuit 28. Each of the multiple distributed output circuits 74 receives a pre-reset signal PR output from the reset circuit 26 via the pre-reset wiring 80. Then, each of the multiple distributed output circuits 74 outputs a distributed reset signal DR. The distributed reset signal DR is a signal similar to the reset signal RS. That is, the distributed reset signal DR becomes the second potential (ground potential) when the supply of the internal power supply voltage VDDC from the switching circuit 24b to the target circuit 12 is interrupted. Also, the distributed reset signal DR becomes the first potential when the switching circuit 24b supplies or interrupts the internal power supply voltage VDDC to the target circuit 12 in accordance with the control by the control circuit 30.

[0070] The multiple distributed reset wires 78 correspond to the multiple distributed output circuits 74. That is, each of the multiple distributed reset wires 78 corresponds to one of the multiple distributed output circuits 74. Each of the multiple distributed reset wires 78 transfers the distributed reset signal DR output from the corresponding distributed output circuit 74 to the multiple sub-switching circuits 60 belonging to the corresponding group, which are included in the switching circuit 24b, without going through the control circuit 30.

[0071] Multiple distributed reset switches 76 correspond to multiple distributed output circuits 74. More specifically, each of the multiple distributed reset switches 76 corresponds to one of the multiple distributed output circuits 74. Each of the multiple distributed reset switches 76 short-circuits or interrupts the connection between the corresponding distributed reset wiring 78 of the multiple distributed reset wiring 78 and ground potential. The multiple distributed reset switches 76 switch in response to signals output from circuits driven by an external power supply voltage VCC.

[0072] In this embodiment, each of the multiple distributed reset switches 76 switches in accordance with the forced reset signal CR output from the second buffer circuit 54 included in the corresponding distributed output circuit 74. Each of the multiple distributed reset switches 76 has the same configuration as the reset switch 34 and operates in the same manner.

[0073] Furthermore, each of the multiple sub-switching circuits 60 switches to the off state regardless of control by the control circuit 30 if the distributed reset signal DR received from the corresponding distributed output circuit 74 among the multiple distributed output circuits 74 via the distributed reset wiring 78 is at the second potential (ground potential).

[0074] Figure 8 shows an example of the arrangement of the power supply circuit 20b according to the third embodiment on the semiconductor chip 70b. The semiconductor chip 70b shown in Figure 8 according to the third embodiment will be described in terms of the differences from the configuration of the semiconductor chip 70 according to the second embodiment shown in Figure 6.

[0075] Each of the multiple distributed output circuits 74 is located near a distributed switching circuit 72 which includes one or more sub-switching circuits 60 belonging to a corresponding group. Similarly, each of the multiple distributed reset switches 76 is located near a corresponding distributed output circuit 74.

[0076] Therefore, the distance between each of the distributed switching circuits 72 and the corresponding distributed output circuits 74 becomes relatively short. Conversely, the distance between the reset circuit 26 and each of the multiple distributed output circuits 74 becomes relatively long. Consequently, the wiring length of each of the multiple distributed reset wires 78 becomes shorter than the wiring of the pre-reset wire 80.

[0077] Furthermore, each of the multiple distributed output circuits 74 is composed of a relatively small number of MOSFETs. Therefore, when the logic of the pre-reset signal PR changes, a relatively small inrush current flows through the pre-reset wiring 80. For this reason, the pre-reset wiring 80 only needs to be formed with a relatively narrow wiring width. For example, the wiring width of the pre-reset wiring 80 can be formed to be narrower than the wiring width of the reset wiring 32 according to the second embodiment.

[0078] In contrast, each of the multiple distributed switching circuits 72 includes, for example, a number of MOSFETs that constitute an auxiliary switch 58. In each of the multiple distributed switching circuits 72, a number of MOSFETs are switched in response to the distributed reset signal DR. Therefore, each of the multiple distributed reset wirings 78 experiences a very large inrush current when the level of the distributed reset signal DR changes. Accordingly, each of the multiple distributed reset wirings 78 is formed with a sufficiently wide wiring width compared to the pre-reset wiring 80 so that it can handle a sufficiently large current when the level of the distributed reset signal DR changes.

[0079] By arranging the circuit in this manner relative to the semiconductor chip 70b, the power supply circuit 20b according to the third embodiment can reduce the wiring width of the pre-reset wiring 80, which has a relatively long wiring length. As a result, the power supply circuit 20b according to the third embodiment can increase the wiring length of the pre-reset wiring 80, which has a narrow wiring width, and shorten the wiring length of the distributed reset wiring 78, which has a wide wiring width, thus enabling efficient circuit arrangement.

[0080] (Fourth Embodiment) Figure 9 shows the configuration of the switching circuit 24c according to the fourth embodiment. The semiconductor device 10c according to the fourth embodiment has substantially the same function and configuration as the semiconductor device 10a according to the second embodiment or the semiconductor device 10b according to the third embodiment. In the description of the semiconductor device 10c of the fourth embodiment, circuits and signals etc. having the same function and configuration as the second and third embodiments are denoted by the same reference numerals, and detailed descriptions are omitted except for differences.

[0081] The semiconductor device 10c according to the fourth embodiment includes a switching circuit 24c in place of the switching circuit 24a according to the second embodiment or the switching circuit 24b according to the third embodiment. The switching circuit 24c according to the fourth embodiment includes, as a plurality of sub-switching circuits 60, one or more first sub-switching circuits 60-1 and one or more second sub-switching circuits 60-2. That is, a portion of the plurality of sub-switching circuits 60 is one or more first sub-switching circuits 60-1. Also, the other portion of the plurality of sub-switching circuits 60 that is not one or more first sub-switching circuits 60-1 is one or more second sub-switching circuits 60-2.

[0082] Each first sub-switching circuit 60-1 has the same configuration as the sub-switching circuit 60 shown in Figure 4. That is, each first sub-switching circuit 60-1 includes a main switch 56, an auxiliary switch 58, and a transfer buffer circuit 62.

[0083] Furthermore, each second sub-switching circuit 60-2 has the same configuration as the sub-switching circuit 60 shown in Figure 4, but with the auxiliary switch 58 removed. That is, each second sub-switching circuit 60-2 includes a main switch 56 and a transfer buffer circuit 62.

[0084] A switching circuit 24c with this configuration can eliminate the auxiliary switches 58 of some of the sub-switching circuits 60 among the multiple sub-switching circuits 60, thus reducing the size of the circuit. Furthermore, even when the reset signal RS is set to the second potential (ground potential), a switching circuit 24c with this configuration may still supply current to the target circuit 12 without each second sub-switching circuit 60-2 turning off. However, if the current supplied by each second sub-switching circuit 60-2 is sufficiently less than the current supply capacity of the voltage regulator 22, the internal power supply voltage VDDC can be raised to the normal operating potential even if current is supplied to the target circuit 12 during startup.

[0085] However, if the current supplied by each second sub-switching circuit 60-2 is greater than the current supply capacity of the voltage regulator 22, the internal power supply voltage VDDC may not rise to the normal operating potential during startup. Therefore, it is necessary to design the number of second sub-switching circuits 60-2 such that the current supplied by each second sub-switching circuit 60-2 is sufficiently smaller than the current supply capacity of the voltage regulator 22.

[0086] Furthermore, in the multiple sub-switching circuits 60 included in each group, the control signal CT is transmitted by multiple transfer buffer circuits 62 connected in cascade. When the auxiliary switch 58 is operating on the internal power supply voltage VDDC, it forcibly pulls up the control signal CT to the internal power supply voltage VDDC.

[0087] (Fifth embodiment) Figure 10 shows the configuration of the power supply circuit 20d according to the fifth embodiment. The semiconductor device 10d according to the fifth embodiment has substantially the same function and configuration as the semiconductor device 10a according to the second embodiment. In the description of the semiconductor device 10d of the fifth embodiment, circuits and signals having the same function and configuration as those of the second embodiment are given the same reference numerals, and detailed explanations are omitted except for differences.

[0088] The semiconductor device 10d according to the fifth embodiment includes a power supply circuit 20d instead of the power supply circuit 20a according to the second embodiment. Compared to the power supply circuit 20a according to the second embodiment, the power supply circuit 20d according to the fifth embodiment does not include a reset wiring 32 that transfers a reset signal RS to the switching circuit 24d. Furthermore, each of the multiple sub-switching circuits 60 included in the switching circuit 24d according to the fifth embodiment does not include an auxiliary switch 58. In other words, each of the multiple sub-switching circuits 60 in the switching circuit 24d according to the fifth embodiment has the same configuration as the second sub-switching circuit 60-2 shown in the fourth embodiment.

[0089] The power supply circuit 20d according to this fifth embodiment can reliably supply the reset signal RS to the control circuit 30 even when the internal power supply voltage VDDC is at a low potential. As a result, the power supply circuit 20d can reliably cut off the supply of the internal power supply voltage VDDC to the target circuit 12, at least as long as the control circuit 30 is operating, even when the internal power supply voltage VDDC is at a low potential.

[0090] (Example of application of power supply circuit 20) Figure 11 shows the configuration of a memory system 100 to which power supply circuits 20, 20a, 20b, 20c, and 20d according to the first to fifth embodiments are applied.

[0091] The memory system 100 is connected to the host device 200 via a bus. The memory system 100 functions as an external storage device for the host device 200. The memory system 100 is, for example, an SSD (Solid State Drive) or a UFS (Universal Flash Storage) device. The host device 200 is, for example, an information processing device including a computer or a processor.

[0092] The memory system 100 includes a power supply circuit 2000, a memory device 110, and a controller 120. The memory device 110 and the controller 120 are connected via a bus wiring 216.

[0093] The power supply circuit 2000 has the same configuration as the power supply circuits 20, 20a, 20b, 20c, or 20d shown in any of the first to fifth embodiments. The power supply circuit 2000 supplies the internal power supply voltage VDDC to the controller 120.

[0094] The memory device 110 is one or more non-volatile semiconductor memories. Non-volatile semiconductor memories are, for example, NAND flash memory. Alternatively, the memory device 110 may be one or more volatile semiconductor memories such as DRAM.

[0095] The controller 120 sends and receives information with the host device 200. The controller 120 performs memory access such as writing and reading data to the memory device 110 in response to requests from the host device 200.

[0096] The controller 120 includes a memory interface 122 (memory I / F). The memory interface 122 transmits and receives signals with the memory device 110 via bus wiring 216. The controller 120 also includes a host interface 124. The host interface 124 transmits and receives data with the host device 200 via a bus that conforms to a predetermined interface standard.

[0097] By applying the power supply circuit 2000 to such a memory system 100, the internal power supply voltage VDDC can be reliably raised to the normal operating voltage, for example, during startup, thereby ensuring reliable operation of the memory system 100.

[0098] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0099] (Note) Furthermore, the above embodiments can be summarized in the following technical proposal.

[0100] [Technical proposal 1] A regulator circuit that generates a second power supply voltage based on the input first power supply voltage, The terminal for outputting the second power supply voltage, A switching circuit provided between the regulator circuit and the terminal, which switches between a first state in which the second power supply voltage is supplied to the terminal, and a second state in which the supply of the second power supply voltage to the terminal is cut off, A first control circuit that outputs a reset signal which, when the switching circuit is switchable between the first state and the second state, is at a first potential, and when the switching circuit is at the second state, is at a second potential different from the first potential, A second control circuit, driven by the second power supply voltage, which performs control to switch the switching circuit to a first state or a second state when the reset signal is at the first potential, A reset wire that transfers the reset signal from the first control circuit to the switching circuit without going through the second control circuit, Equipped with, The switching circuit switches to the second state regardless of control by the second control circuit when the reset signal received via the reset wiring is at the second potential. power supply.

[0101] [Technical proposal 2] The first control circuit further includes a reset switch that short-circuits or interrupts the connection between the reset wiring and the potential corresponding to the second potential, The reset switch switches in accordance with the signal output from the circuit driven by the first power supply voltage. The power supply device described in Technical Proposal 1.

[0102] [Technical proposal 3] The system further includes a reset circuit that is driven by the first power supply voltage and outputs a pre-reset signal that sets the reset signal to a first potential or a second potential, The first control circuit is, A first buffer circuit driven by the second power supply voltage, which receives the pre-reset signal and outputs the reset signal having the same logic potential as the pre-reset signal, A second buffer circuit is driven by the first power supply voltage, receives the pre-reset signal, and outputs a forced reset signal having a logic potential inverted from the logic potential of the pre-reset signal. including, The power supply device described in Technical Proposal 2.

[0103] [Technical proposal 4] The reset switch switches in response to the forced reset signal. The power supply device described in Technical Proposal 3.

[0104] [Technical proposal 5] The reset switch is an N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), with its drain connected to the reset wiring, its source connected to the second potential, and the gate receiving the forced reset signal. The second buffer circuit sets the forced reset signal to a potential that turns off the N-channel MOSFET when the pre-reset signal is logic indicating that the second power supply voltage can be supplied, and sets the forced reset signal to a potential that turns on the N-channel MOSFET when the pre-reset signal is logic indicating that the supply of the second power supply voltage is cut off. The power supply device described in Technical Proposal 4.

[0105] [Technical proposal 6] The second control circuit outputs a control signal that becomes an H logic potential when the reset signal is at the second potential, and an L logic potential lower than the H logic potential or the H logic potential when the reset signal is at the first potential. The aforementioned switching circuit is A signal input terminal receives the control signal, and when the control signal is at the L logic potential, a main switch short-circuits the voltage input terminal which receives the second power supply voltage and the voltage output terminal which supplies the received second power supply voltage to the terminal, and when the control signal is at the H logic potential, a main switch which disconnects the voltage input terminal and the voltage output terminal. An auxiliary switch that receives the reset signal via the reset wiring, and when the reset signal is at the first potential, disconnects the signal input terminal and the voltage input terminal, and when the reset signal is at the second potential, short-circuits the signal input terminal and the voltage input terminal, Equipped with The power supply device described in Technical Proposal 2.

[0106] [Technical proposal 7] The main switch is a P-channel MOSFET, with its source connected to the voltage input terminal, its drain connected to the voltage output terminal, and its gate connected to the signal input terminal. The auxiliary switch is a P-channel MOSFET, with its source connected to the voltage input terminal, its drain connected to the gate of the main switch, and its gate connected to the reset wiring. The power supply device described in Technical Proposal 6.

[0107] [Technical proposal 8] The second control circuit outputs a control signal that becomes an H logic potential when the reset signal is at the second potential, and an L logic potential lower than the H logic potential or the H logic potential when the reset signal is at the first potential. The switching circuit includes a plurality of sub-switching circuits, each of which is provided between the regulator circuit and the terminal. Each of the above-mentioned sub-switching circuits is A signal input terminal receives the control signal, and when the control signal is at the L logic potential, a main switch short-circuits the voltage input terminal which receives the second power supply voltage and the voltage output terminal which supplies the received second power supply voltage to the terminal, and when the control signal is at the H logic potential, a main switch which disconnects the voltage input terminal and the voltage output terminal. An auxiliary switch that receives the reset signal via the reset wiring, and when the reset signal is at the first potential, disconnects the signal input terminal and the voltage input terminal, and when the reset signal is at the second potential, short-circuits the signal input terminal and the voltage input terminal, Equipped with The power supply device described in Technical Proposal 2.

[0108] [Technical proposal 9] The main switch is a P-channel MOSFET, with its source connected to the voltage input terminal, its drain connected to the voltage output terminal, and its gate connected to the signal input terminal. The auxiliary switch is a P-channel MOSFET, with its source connected to the voltage input terminal, its drain connected to the gate of the main switch, and its gate connected to the reset wiring. The power supply device described in Technical Proposal 8.

[0109] [Technical proposal 10] The aforementioned plurality of sub-switching circuits are divided into a plurality of groups, each containing two or more sub-switching circuits. The second control circuit outputs different control signals to each of the plurality of groups. The power supply device described in Technical Proposal 8.

[0110] [Technical proposal 11] The two or more sub-switching circuits included in each of the aforementioned groups are connected in cascade to sequentially transfer the control signal. The first of the two or more sub-switching circuits connected in cascade receives the control signal from the second control circuit, Each of the two or more sub-switching circuits outputs the received control signal to a subsequent sub-switching circuit after delaying it for a predetermined time. The power supply device described in Technical Proposal 10.

[0111] [Technical proposal 12] The second control circuit causes the output timing of the control signal to differ for each of the plurality of groups. The power supply device described in Technical Proposal 10.

[0112] [Technical proposal 13] Multiple distributed output circuits corresponding to each of the aforementioned multiple groups, A plurality of distributed reset switches corresponding to each of the plurality of distributed output circuits, Multiple groups, multiple distributed output circuits, and multiple distributed reset switches, each connected to a multiple distributed reset wiring, Furthermore, Each of the plurality of distributed output circuits outputs a distributed reset signal via the corresponding distributed reset wiring among the plurality of distributed reset wirings, which is at the first potential when the switching circuit is switched to the first state or the second state, and at the second potential when the switching circuit is in the second state. Each of the plurality of distributed reset switches shorts or interrupts the connection between the corresponding distributed reset wiring among the plurality of distributed reset wirings and the potential corresponding to the second potential. Each of the plurality of sub-switching circuits switches to the second state regardless of control by the second control circuit if the distributed reset signal received from the corresponding distributed output circuit among the plurality of distributed output circuits via the distributed reset wiring is at the second potential. The power supply device described in Technical Proposal 10.

[0113] [Technical proposal 14] The system further includes a reset circuit that is driven by the first power supply voltage and outputs a pre-reset signal via pre-reset wiring that sets the reset signal to a first potential or a second potential, Each of the plurality of distributed output circuits includes a first buffer circuit that is driven by the second power supply voltage, receives the pre-reset signal via the pre-reset wiring, and outputs the distributed reset signal corresponding to the pre-reset signal via the distributed reset wiring. Each of the aforementioned multiple distributed reset wires is formed with a wider wire width than the pre-reset wire. The power supply device described in Technical Proposal 13.

[0114] [Technical proposal 15] The second control circuit outputs a control signal that becomes an H logic potential when the reset signal is at the second potential, and an L logic potential lower than the H logic potential or the H logic potential when the reset signal is at the first potential. The switching circuit includes one or more first sub-switching circuits and one or more second sub-switching circuits, each provided between the regulator circuit and the terminals. Each of the one or more first sub-switching circuits is: A signal input terminal receives the control signal, and when the control signal is at the L logic potential, a main switch short-circuits the voltage input terminal which receives the second power supply voltage and the voltage output terminal which supplies the received second power supply voltage to the terminal, and when the control signal is at the H logic potential, a main switch which disconnects the voltage input terminal and the voltage output terminal. An auxiliary switch that receives the reset signal via the reset wiring, and when the reset signal is at the first potential, disconnects the connection to the signal input terminal, and when the reset signal is at the second potential, short-circuits the connection to the signal input terminal, Equipped with, Each of the one or more second sub-switching circuits is: The main switch is provided as described above. The power supply device described in Technical Proposal 2.

[0115] [Technical proposal 16] A regulator circuit that generates a second power supply voltage based on the input first power supply voltage, The terminal for outputting the second power supply voltage, A switching circuit provided between the regulator circuit and the terminal, which switches between a first state in which the second power supply voltage is supplied to the terminal, and a second state in which the supply of the second power supply voltage to the terminal is cut off, When the switching circuit can be switched between the first state and the second state, a control circuit outputs a reset signal that is at a first potential, and when the switching circuit is in the second state, a reset signal that is at a second potential different from the first potential. Equipped with, The control circuit includes a reset switch that short-circuits or interrupts the connection between the output terminal of the reset signal and the potential corresponding to the second potential, in accordance with a signal output from a circuit driven by the first power supply voltage. The switching circuit switches to the second state regardless of control by the control circuit when the reset switch short-circuits the output terminal of the reset signal and the potential corresponding to the second potential, causing the reset signal to become the second potential. power supply.

[0116] [Technical proposal 17] The target circuit and A power supply device according to any one of the technical proposals 1 to 16 that supplies the second power supply voltage to the target circuit via the terminal, A semiconductor device equipped with a semiconductor device. [Explanation of Symbols]

[0117] CT control signals PR pre-reset signal CR forced reset signal RS reset signal DR Distributed Reset Signal VCC External power supply voltage VDDC Internal power supply voltage 10 Semiconductor Devices 12 Target Circuits 20,20a,20b,20c,20d,2000 Power supply circuit 21 terminals 22 Voltage Regulators 24, 24a, 24b, 24c, 24d Switching Circuits 26 Reset circuit 28 Output Circuit 30 Control circuits 32 Reset wiring 34 Reset switch 42 Voltage input terminals 44 Voltage output terminals 48 Signal input terminals 52 First Buffer Circuit 54 Second Buffer Circuit 56 Main Switch 58 Auxiliary switch 60 Sub-switching circuits 62 Transfer Buffer Circuit 70,70b semiconductor chip 72 Distributed Switching Circuits 74 Distributed Output Circuits 76 Distributed Reset Switch 78 Distributed Reset Wiring 80 Pre-reset wiring

Claims

1. A regulator circuit that generates a stabilized second power supply voltage based on the input first power supply voltage, even if power consumption fluctuates. The terminal that outputs the second power supply voltage, A switching circuit provided between the regulator circuit and the terminal, which switches between a first state in which the second power supply voltage is supplied to the terminal, and a second state in which the supply of the second power supply voltage to the terminal is cut off, An output circuit that is driven by the second power supply voltage and outputs a reset signal that is at a first potential when the switching circuit is switched to the first state or the second state, and at a second potential different from the first potential when the switching circuit is in the second state, A control circuit, driven by the second power supply voltage, which performs control to switch the switching circuit to a first state or a second state when the reset signal is at the first potential, A reset wire that transfers the reset signal from the output circuit to the switching circuit without going through the control circuit, A reset circuit driven by the first power supply voltage and outputting a pre-reset signal that sets the reset signal to a first potential, A reset switch that, when the pre-reset signal is not output, short-circuits the reset wiring and the potential corresponding to the second potential, and when the pre-reset signal is output, interrupts the connection between the reset wiring and the potential corresponding to the second potential, Equipped with, The control circuit outputs a control signal that becomes an H logic potential when the reset signal is the second potential, and an L logic potential lower than the H logic potential or the H logic potential when the reset signal is the first potential. The aforementioned switching circuit is A voltage input terminal to which the second power supply voltage generated from the regulator circuit is supplied, A main switch is a MOSFET that receives the control signal output from the control circuit at its gate, short-circuits the voltage input terminal and the terminal when the gate is at the L logic potential, and blocks the voltage input terminal and the terminal when the gate is at the H logic potential. An auxiliary switch is a MOSFET that receives the reset signal at its gate via the reset wiring, and when the gate is at the first potential, it disconnects the gate of the main switch from the voltage input terminal, and when the gate is at the second potential, it short-circuits the gate of the main switch from the voltage input terminal. It has, The second power supply voltage is equal to the H logic potential. power supply.

2. The output circuit described above is A first buffer circuit driven by the second power supply voltage, receiving the pre-reset signal and outputting the reset signal having the same logic potential as the pre-reset signal, A second buffer circuit is driven by the first power supply voltage, receives the pre-reset signal, and outputs a forced reset signal having a logic potential inverted from the logic potential of the pre-reset signal. including, The power supply device according to claim 1.

3. A regulator circuit that generates a stabilized second power supply voltage based on the input first power supply voltage, even if power consumption fluctuates. The terminal that outputs the second power supply voltage, A switching circuit provided between the regulator circuit and the terminal, which switches between a first state in which the second power supply voltage is supplied to the terminal, and a second state in which the supply of the second power supply voltage to the terminal is cut off, An output circuit that is driven by the second power supply voltage and outputs a reset signal that is at a first potential when the switching circuit is switched to the first state or the second state, and at a second potential different from the first potential when the switching circuit is in the second state, A control circuit, driven by the second power supply voltage, which performs control to switch the switching circuit to a first state or a second state when the reset signal is at the first potential, A reset wire that transfers the reset signal from the output circuit to the switching circuit without going through the control circuit, A reset circuit driven by the first power supply voltage and outputting a pre-reset signal that sets the reset signal to a first potential, A reset switch that, when the pre-reset signal is not output, short-circuits the reset wiring and the potential corresponding to the second potential, and when the pre-reset signal is output, interrupts the connection between the reset wiring and the potential corresponding to the second potential, Equipped with, The control circuit outputs a control signal that becomes an H logic potential when the reset signal is the second potential, and an L logic potential lower than the H logic potential or the H logic potential when the reset signal is the first potential. The switching circuit includes a plurality of sub-switching circuits, each of which is provided between the regulator circuit and the terminal. Each of the above-mentioned sub-switching circuits is A voltage input terminal to which the second power supply voltage generated from the regulator circuit is supplied, A main switch is a MOSFET that receives the control signal output from the control circuit at its gate, short-circuits the voltage input terminal and the terminal when the gate is at the L logic potential, and blocks the voltage input terminal and the terminal when the gate is at the H logic potential. An auxiliary switch is a MOSFET that receives the reset signal at its gate via the reset wiring, and when the gate is at the first potential, it disconnects the gate of the main switch from the voltage input terminal, and when the gate is at the second potential, it short-circuits the gate of the main switch from the voltage input terminal. It has, The second power supply voltage is equal to the H logic potential. power supply.

4. The aforementioned plurality of sub-switching circuits are divided into a plurality of groups, each containing two or more sub-switching circuits. The control circuit outputs different control signals to each of the plurality of groups. The power supply device according to claim 3.

5. A regulator circuit that generates a stabilized second power supply voltage based on the input first power supply voltage, even if power consumption fluctuates. The terminal that outputs the second power supply voltage, A switching circuit provided between the regulator circuit and the terminal, which switches between a first state in which the second power supply voltage is supplied to the terminal, and a second state in which the supply of the second power supply voltage to the terminal is cut off, An output circuit that is driven by the second power supply voltage and outputs a reset signal that is at a first potential when the switching circuit is switched to the first state or the second state, and at a second potential different from the first potential when the switching circuit is in the second state, A control circuit, driven by the second power supply voltage, which performs control to switch the switching circuit to a first state or a second state when the reset signal is at the first potential, A reset wire that transfers the reset signal from the output circuit to the switching circuit without going through the control circuit, A reset circuit driven by the first power supply voltage and outputting a pre-reset signal that sets the reset signal to a first potential, A reset switch that, when the pre-reset signal is not output, short-circuits the reset wiring and the potential corresponding to the second potential, and when the pre-reset signal is output, interrupts the connection between the reset wiring and the potential corresponding to the second potential, Equipped with, The control circuit outputs a control signal that becomes an H logic potential when the reset signal is the second potential, and an L logic potential lower than the H logic potential or the H logic potential when the reset signal is the first potential. The switching circuit includes one or more first sub-switching circuits and one or more second sub-switching circuits, each provided between the regulator circuit and the terminal. Each of the one or more first sub-switching circuits is: A voltage input terminal to which the second power supply voltage generated from the regulator circuit is supplied, A main switch is a MOSFET that receives the control signal output from the control circuit at its gate, short-circuits the voltage input terminal and the terminal when the gate is at the L logic potential, and blocks the voltage input terminal and the terminal when the gate is at the H logic potential. An auxiliary switch is a MOSFET that receives the reset signal at its gate via the reset wiring, and when the gate is at the first potential, it disconnects the gate of the main switch from the voltage input terminal, and when the gate is at the second potential, it short-circuits the gate of the main switch from the voltage input terminal. It has, Each of the one or more second sub-switching circuits is: Having the aforementioned main switch, The second power supply voltage is equal to the H logic potential. power supply.

6. The target circuit and A power supply device according to any one of claims 1 to 5, which supplies the second power supply voltage to the target circuit via the terminal, A semiconductor device equipped with a semiconductor device.

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