Gate drive device and power converter equipped therewith

Abstract

To allow for greater flexibility in setting at least one of the following periods: a continuous on state or a continuous off state. [Solution] The operation of the receiving circuit includes at least one of the following preparatory operations: a first preparatory operation in which, when the waveform of the gate voltage when it is turned on is changed twice in a row, the reception of a first data signal indicating a first parameter related to the waveform of the second on-time is started before the off-time immediately preceding the second on-time; and a second preparatory operation in which, when the waveform of the gate voltage when it is turned off is changed twice in a row, the reception of a second data signal indicating a second parameter related to the waveform of the second off-time is started before the on-time immediately preceding the second off-time.

Description

[Technical Field]

[0001] This disclosure relates to a gate drive device for applying a gate voltage to a semiconductor switch and a power conversion device equipped therewith. [Background technology]

[0002] Patent Document 1 discloses a gate drive device for applying a gate voltage to a semiconductor switch. This gate drive device includes a memory for storing parameters relating to the on-waveform and off-waveform of the gate voltage, a drive circuit that refers to a gate drive signal indicating the on / off state of the semiconductor switch and the parameters stored in the memory, and applies a gate voltage with a waveform corresponding to the parameters to the semiconductor switch, and a receiving circuit that outputs the parameters to the memory via an external input. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 7325632 [Overview of the project] [Problems that the invention aims to solve]

[0004] In the gate drive device disclosed in Patent Document 1, if the receiving circuit starts receiving parameters related to the waveform of the gate voltage when it is ON after the completion of the previous OFF operation, the receiving circuit needs to receive these parameters between the previous OFF operation and the current ON operation. Therefore, it is necessary to limit the period from OFF operation to ON operation, i.e., the period of consecutive OFF states, to be longer than the time required to receive the parameters.

[0005] Similarly, if the receiving circuit begins receiving parameters related to the gate voltage waveform when it is off after the previous on operation has finished, the receiving circuit must receive these parameters between the previous on operation and the current off operation. Therefore, the period from on operation to off operation, i.e., the period of continuous on states, must be limited to be longer than the time required to complete the reception of the parameters.

[0006] The purpose of this disclosure is to allow for greater flexibility in setting at least one of the following: a period of continuous ON state or a period of continuous OFF state. [Means for solving the problem]

[0007] A first aspect of the present disclosure is a gate drive device for applying a gate voltage to a semiconductor switch (12), comprising: a rewritable storage unit (40) having a first storage area (41) for storing a first parameter (PA1) relating to the waveform of the gate voltage (GS) when it is ON, and a second storage area (42) for storing a second parameter (PA2) relating to the waveform of the gate voltage (GS) when it is OFF; a drive circuit (50) that refers to a gate drive signal (GD) and the first and second parameters (PA1, PA2) stored in the storage unit (40) and applies a gate voltage (GS) with a waveform corresponding to the first and second parameters (PA1, PA2) to the semiconductor switch (12); and a drive circuit (50) that receives a first data signal (DT1) indicating the first parameter (PA1) and a second data signal (DT2) indicating the second parameter (PA2), and the The device includes a receiving circuit (30) that outputs a first parameter (PA1) corresponding to a data signal (DT1) and a second parameter (PA2) corresponding to a second data signal (DT2) to the storage unit (40), wherein the operation of the receiving circuit (30) includes at least one of the following preparatory operations: a first preparatory operation in which, when the waveform of the gate voltage (GS) when it is ON is changed twice in a row, the reception of the first data signal (DT1) indicating the first parameter (PA1) relating to the waveform of the second ON is started before the OFF time immediately preceding the second ON time; and a second preparatory operation in which, when the waveform of the gate voltage (GS) when it is OFF is changed twice in a row, the reception of the second data signal (DT2) indicating the second parameter (PA2) relating to the waveform of the second OFF is started before the ON time immediately preceding the second OFF time.

[0008] In the first embodiment, if the operation of the receiving circuit (30) includes a first preparatory operation, the time from the off operation immediately preceding the second on operation to the second on operation does not need to be set to be longer than the time required to receive the first data signal (DT1) relating to the waveform at the second on operation. Therefore, the period of consecutive off states can be set more freely.

[0009] Furthermore, if the operation of the receiving circuit (30) includes a second preparatory operation, the time from the ON operation immediately preceding the second OFF operation to the second OFF operation does not need to be set to be longer than the time required to receive the second data signal (DT2) relating to the waveform at the second OFF operation. Therefore, the period of continuous ON states can be set more freely.

[0010] A second aspect of the present disclosure, in the first aspect, the receiving circuit (30) receives the first and second data signals (DT1, DT2) via different communication lines (21, 22).

[0011] In the second embodiment, the communication speeds on each communication line (21, 22) can be set slower compared to the case where the first and second data signals (DT2) are received on a common communication line.

[0012] A third aspect of the present disclosure, in the first aspect, the receiving circuit (30) receives the first and second data signals (DT1, DT2) on a common communication line (23) and also receives identification information (AD), and allocates the first parameter (PA1) corresponding to the received first data signal (DT1) and the second parameter (PA2) corresponding to the received second data signal (DT2) to the first and second storage areas (41, 42) of the storage unit (40) with reference to the identification information (AD).

[0013] In the third embodiment, it is not necessary to provide separate communication lines for the communication of the first and second data signals (DT1, DT2), thus reducing the number of communication lines.

[0014] A fourth aspect of the present disclosure, in the first aspect, the receiving circuit (30) receives the first and second data signals (DT1, DT2) on a common communication line (23), and allocates the first parameter (PA1) corresponding to the received first data signal (DT1) and the second parameter (PA2) corresponding to the received second data signal (DT2) to the first and second storage areas (41, 42) of the storage unit (40) with reference to the gate drive signal (GD).

[0015] In the fourth aspect, since it is not necessary to receive the identification information (AD) for allocating the first and second data signals (DT1, DT2) to the first and second storage areas (41, 42) via the communication line (23), the communication speed via the communication line (23) can be set slower than when the identification information (AD) is received via the communication line (23).

[0016] A fifth aspect of the present disclosure is that in any one of the first to fourth aspects, the first and second storage areas (41, 42) each include first and second partition areas (41a, 41b, 42a, 42b), and when the reception circuit (30) receives the first data signal (DT1), a first parameter (PA1) corresponding to the first data signal (DT1) is output to a partition area (41a, 41b) different from the partition area (41a, 41b) storing the first parameter (PA1) most recently referred to by the drive circuit (50) among the first and second partition areas (41a, 41b) in the first storage area (41). When the second data signal (DT2) is received, a second parameter (PA2) corresponding to the second data signal (DT2) is output to a partition area (42a, 42b) different from the partition area (42a, 42b) storing the second parameter (PA2) most recently referred to by the drive circuit (50) among the first and second partition areas (42a, 42b) in the second storage area (42).

[0017] In the fifth aspect, it is possible to suppress simultaneous writing and reading to the common area of the storage areas (41, 42).

[0018] A sixth aspect of the present disclosure is a power conversion device (1) including a gate drive device according to any one of the first to fifth aspects and a semiconductor switch (12).

Brief Description of Drawings

[0019] [Figure 1] FIG. 1 is a block diagram showing a configuration of a power conversion device including a gate drive device according to Embodiment 1 of the present disclosure. [Figure 2] FIG. 2 is a block diagram showing the configuration of the first receiving circuit. [Figure 3] FIG. 3 is a block diagram showing the configuration of the variable gate drive circuit. [Figure 4] FIG. 4 is a timing chart illustrating the transitions of each data and each signal in the gate drive device according to Embodiment 1 of the present disclosure. [Figure 5] FIG. 5 is a timing chart illustrating a triangular wave, a modulation wave, and a gate drive signal in PWM control. [Figure 6] FIG. 6 is a diagram corresponding to FIG. 1 of Embodiment 2. [Figure 7] FIG. 7 is a diagram corresponding to FIG. 4 of Embodiment 2. [Figure 8] FIG. 8 is a diagram corresponding to FIG. 1 of Embodiment 3. [Figure 9] FIG. 9 is a block diagram showing the configurations of a receiving circuit, a memory, and a selection circuit. [Figure 10] FIG. 10 is a diagram corresponding to FIG. 4 of Embodiment 3.

BEST MODE FOR CARRYING OUT THE INVENTION

[0020] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the following embodiments are essentially preferred examples and are not intended to limit the scope of the present invention, its applications, or its uses.

[0021] (Embodiment 1) FIG. 1 shows a power conversion device (1). This power conversion device (l) is used, for example, to supply power to a compressor provided in a heat pump device such as an air conditioner. This power conversion device (1) includes an inverter circuit (10) and a gate drive device (20) according to Embodiment Ⅰ of the present disclosure.

[0022] The inverter circuit (10) comprises, for example, three switching legs, one end of which is connected to a power line and the other end to ground. Figure 1 shows only one of the three switching legs. The number of switching legs is not limited to three. Each switching leg has a first switching element (11) on the upper arm and a second switching element (12) on the lower arm, connected in series with each other. In each switching leg, the midpoint between the first switching element (11) on the upper arm and the second switching element (12) on the lower arm is connected to a load (2). The load (2) is, for example, a compressor motor. For example, the inverter circuit (10) drives the motor as the load (2) by PWM control. In this case, the midpoints between the first switching element (11) on the upper arm and the second switching element (12) on the lower arm in the three switching legs are connected to the coils of each phase (u-phase, v-phase, and w-phase coils), respectively. Each switching element (11, 12) is connected in antiparallel to a freewheeling diode (11a, 12a). The inverter circuit (10) converts DC power to AC power and supplies it to the load (2) through the switching operation of the first switching element (11) and the second switching element (12). Each switching element (11, 12) is a MOSFET (metal-oxide-semiconductor field-effect transistor). However, each switching element (11, 12) may be another transistor, such as an IGBT (Insulated Gate Bipolar Transistor) or a HEMT (High Electron Mobility Transistor).

[0023] A gate drive device (20) is provided for each switching element (11, 12) of the inverter circuit (10). Figure 1 shows only the gate drive device (20) that applies the gate voltage to the second switching element (12). The configuration and operation of the gate drive device (20) for the second switching element (12) will be described below. The configuration and operation of the gate drive device (20) for the first switching element (11) are the same as those of the gate drive device (20) for the second switching element (12).

[0024] The gate drive device (20) comprises a receiving circuit (30), a memory (40) as a storage unit, and a variable gate drive circuit (50). The receiving circuit (30), the memory (40), and the variable gate drive circuit (50) are housed in a common package (not shown).

[0025] The receiving circuit (30) has a first receiving circuit (30a) and a second receiving circuit (30b). The first receiving circuit (30a) receives a first data signal (DT1) indicating a first parameter (PA1) from outside the package via a first communication line (21). The first parameter (PA1) is a parameter relating to the waveform of the gate voltage of the second switching element (12) when it is ON. The first receiving circuit (30a) then outputs the first parameter (PA1) corresponding to the first data signal (DT1) to the memory (40). The second receiving circuit (30b) receives a second data signal (DT2) indicating a second parameter (PA2) from outside the package via a second communication line (22). The receiving circuit (30) receives the first and second data signals (DT1, DT2) via different communication lines (21, 22). The second parameter (PA2) is a parameter relating to the waveform of the gate voltage of the second switching element (12) when it is off. The second receiving circuit (30b) outputs the second parameter (PA2) corresponding to the second data signal (DT2) to the memory (40).

[0026] Specifically, the first receiving circuit (30a) includes a shift register (31) and a synchronization circuit (32), as shown in Figure 2.

[0027] The shift register (31) receives the first clock signal (CLK1) along with the first data signal (DT1). The shift register (31) then converts the first data signal (DT1), which is serial data, into parallel data using the first clock signal (CLK1) and outputs it to the first data path (33).

[0028] The synchronization circuit (32) receives a communication completion signal (CC) from outside the package to indicate whether or not communication has been completed. When the communication completion signal (CC) indicates that communication has been completed, the synchronization circuit (32) outputs the first data signal (DT1), which has been output in parallel to the first data path (33) by the shift register (31), as the first parameter (PA1) to the second data bus (34).

[0029] The configuration of the second receiving circuit (30b) is the same as that of the first receiving circuit (30a). The second receiving circuit (30b) receives and uses a first clock signal (CLK1) and a communication completion signal (CC) that are different from those of the first receiving circuit (30a). If the first and second data signals (DT1, DT2) are synchronized with each other, the second receiving circuit (30b) may use a first clock signal (CLK1) and a communication completion signal (CC) that are common to the first receiving circuit (30a).

[0030] The memory (40) is a rewritable memory. The memory (40) has a first storage area (41) that stores the first parameter (PA1) output by the first receiving circuit (30a), and a second storage area (42) that stores the second parameter (PA2) output by the second receiving circuit (30b). The first storage area (41) and the second storage area (42) are memory circuits, and are composed of, for example, SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory). The first storage area (41) holds the first parameter (PA1) when the first parameter (PA1) is written from the first receiving circuit (30a) to the second data bus (34), and outputs it to the third data bus (43). The second memory area (41) holds the second parameter (PA2) when the second receiving circuit (30b) writes the second parameter (PA2) to the second data bus (34), and outputs it to the third data bus (43).

[0031] The variable gate drive circuit (50) refers to the gate drive signal (GD) and the first and second parameters (PA1, PA2) stored in the memory (40), and applies a gate signal (gate voltage) (GS) with a waveform corresponding to the first and second parameters (PA1, PA2) to the second switching element (12). The gate drive signal (GD) is input from outside the package.

[0032] Specifically, the variable gate drive circuit (50) includes a time-series data generation unit (51) and a gate current generation unit (52), as shown in Figure 3.

[0033] The time-series data generation unit (51) includes an edge detection unit (51a), an oscillator (51b), an address counter (51c), and a register (51d).

[0034] The edge detection unit (51a) detects the edges of the gate drive signal (GD).

[0035] The oscillator (51b) generates the timing clock (CLK2).

[0036] The address counter (51c) counts the rising edge of the timing clock (CLK2). The count value of the address counter (51c) is initialized when an edge is detected by the edge detection unit (51a). The count value of the address counter (51c) may be initialized to different values ​​depending on whether the edge detected by the edge detection unit (51a) is a rising or falling edge.

[0037] Register (51d) holds the first and second parameters (PA1, PA2) output to the third data bus (43) by memory (40). The first and second parameters (PA1, PA2) are multiple data, and register (51d) holds multiple data corresponding to multiple addresses. The first and second parameters (PA1, PA2) held in register (51d) are binary code data. Register (51d) outputs the first or second parameter (PA1, PA2) for an address corresponding to the count value of the address counter (51c). The first or second parameter (PA1, PA2) output by register (51d) is time-series data.

[0038] The gate current generation unit (52) applies a gate signal (gate voltage) (GS) with a waveform corresponding to the first and second parameters (PA1, PA2) to the second switching element (12). The voltage level of the gate signal (gate voltage) (GS) at each timing corresponds to the level of the first or second parameter (PA1, PA2) at each timing output by the register (51d).

[0039] Specifically, the gate current generation unit (52) includes a first weighted sign conversion unit (52a), a second weighted sign conversion unit (52a), and a variable current source (521). The variable current source (521) includes a plurality of first transistors (52c) and a plurality of second transistors (52d). One end of the plurality of first transistors (52c) is connected to a common voltage source, and one end of the plurality of second transistors (52d) is grounded. The other ends of the plurality of first transistors (52c) and the other ends of the plurality of second transistors (52d) are connected to the gate of the second switching element (12). In other words, the plurality of first transistors (52c) are connected in parallel to each other between the common voltage source and the output terminal. The plurality of second transistors (52d) are connected in parallel to each other between the reference potential point and the output terminal. The first transistors (52c) and the second transistors (52d) are MOSFETs.

[0040] The first weight code conversion unit (52a) converts the first parameter (PA1) output by the register (51d) into a weight code and outputs it. Specifically, the first weight code conversion unit (52a) outputs a signal indicating the number of first transistors (52c) that are turned on among a plurality of first transistors (52c) based on the first parameter (PA1) output by the register (51d).

[0041] The second weight code conversion unit (52a) converts the second parameter (PA2) output by the register (51d) into a weight code and outputs it. Specifically, the second weight code conversion unit (52a) outputs a signal indicating the number of second transistors (52d) that are turned on among the multiple second transistors (52d) based on the second parameter (PA2) output by the register (51d).

[0042] Multiple first transistors (52c) are switched on and off in response to the signal output by the first weighted code conversion unit (52a). The number of first transistors (52c) that are turned on among the multiple first transistors (52c) is the number indicated by the signal output by the first weighted code conversion unit (52a).

[0043] Multiple second transistors (52d) are switched on and off in response to the signal output by the second weight code conversion unit (52b). The number of second transistors (52d) that are turned on among the multiple second transistors (52d) is the number indicated by the signal output by the second weight code conversion unit (52b).

[0044] With the configuration described above, the output of the register (51d) is immediately reflected in the output current of the variable current source (521), i.e., the drive current of the second switching element (12).

[0045] Figure 4 illustrates the transitions of each data and signal in the gate drive device (20) according to Embodiment 1 of this disclosure.

[0046] In Figure 4, the first data signals (DT1), data 1, data 3, and data 5, respectively, show the waveforms of the gate voltage when it is ON during periods T12, T14, and T16. The second data signals (DT2), data 2 and data 4, respectively, show the waveforms of the gate voltage when it is OFF during periods T13 and T15. During period T11, the register (51d) is initialized.

[0047] The operation of the first receiving circuit (30a) includes a first preparatory operation in which, when the waveform of the gate voltage (GS) is changed twice in a row, the reception of a first data signal (DT1) indicating a first parameter (PA1) relating to the waveform of the second on-time is started before the off-time immediately preceding the second on-time.

[0048] In Figure 4, the ON waveform of the gate voltage (GS) of the second switching element (12) is changed twice consecutively during periods T12 and T14. Reception of data 3, which is the first data signal (DT1) indicating the first parameter (PA1) related to the waveform during the second ON period (waveform during period T14), begins before the OFF period immediately preceding the second ON period (start of period T13).

[0049] Therefore, in this embodiment 1, when the waveform of the gate voltage (GS) is changed twice in a row, the time from the off operation immediately preceding the second on operation to the second on operation does not need to be set to be longer than the time required to receive the first data signal (DT1) related to the waveform of the second on operation. Thus, the period of consecutive off states can be set more freely.

[0050] Furthermore, the time required to receive the first data signal (DT1) related to the waveform during the second ON operation can be set to be longer than the time from the OFF operation immediately preceding the second ON operation to the second ON operation, thus allowing for a slower communication speed.

[0051] The operation of the second receiving circuit (30b) includes a second preparatory operation in which, when the waveform of the gate voltage (GS) is changed twice in a row when it is off, the reception of a second data signal (DT2) indicating a second parameter (PA2) relating to the waveform when it is off is started before the ON time immediately preceding the second OFF time.

[0052] In Figure 4, the waveform of the gate voltage (GS) of the second switching element (12) during the off state is changed twice consecutively during periods T13 and T15. Reception of data 4, which is a second data signal (DT2) indicating a second parameter (PA2) related to the waveform during the second off state (waveform during period T15), is started before the on state immediately preceding the second off state (start of period T14).

[0053] Therefore, in this embodiment 1, when the waveform of the gate voltage (GS) is changed twice in a row during the off state, the time from the ON operation immediately preceding the second off state to the second off operation does not need to be set to be longer than the time required to receive the second data signal (DT2) related to the waveform during the second off state. Thus, the period of consecutive ON states can be set more freely.

[0054] In addition, since the time taken to receive the second data signal (DT2) related to the waveform at the second OFF can be set to be longer than the time from the immediately preceding ON operation to the second OFF operation at the second OFF, the required communication speed can be reduced.

[0055] When performing PWM control on a motor as the load (2), particularly when setting the carrier frequency of the PWM control high, for example, when setting the carrier frequency to 20 kHz or more outside the audible range of humans, it is required to narrow the pulse width of the gate voltage (GS). Since the disclosed technology can reduce the required communication speed as described above, it is suitable when performing PWM control, particularly when setting the carrier frequency high.

[0056] FIG. 5 illustrates a triangular wave, a modulated wave, and a gate drive signal (GD) when performing PWM control on the inverter circuit (10). In FIG. 5, the switching frequency is f sw (Hz), the switching period is T SW , the ON time is T ON is shown.

[0057] The duty ratio D is expressed as follows.

[0058] D = T ON / T SW Here, let the number of data of the first and second data signals (DT1, DT2) be N (bit) respectively, the communication rate be f scan (bps), and the minimum value of the duty ratio D be D min .

[0059] When starting the reception of the second data signal (DT2) indicating the waveform at OFF at the timing t2 after the immediately preceding ON timing t1, it is necessary to complete the reception of the second data signal (DT2) between the timing t1 and the timing t2. Therefore, it is necessary to satisfy the following formula.

[0060] f scan ≧ 2N * f sw / Dmin 2N = 216 (bits), D min If we set fsw = 0.01 (1%) and fsw = 5000 (Hz), the communication rate f scan The (bps) must be 108 (Mbps) or higher.

[0061] In contrast, in this embodiment 1, reception of the first data signal (DT1) showing the waveform when the device is ON at timing t3 can be started before timing t2, which is the previous OFF time. For example, if reception of the first data signal (DT1) showing the waveform when the device is ON at timing t3 is to be started at timing t1, which is the previous ON time, then the following equation must be satisfied.

[0062] f scan ≥N*2f sw N=108(bit), D min If we set fsw = 0.01 (1%) and fsw = 5000 (Hz), the communication rate f scan The (bps) only needs to be 1.08 (Mbps) or higher. In this way, the required transmission rate can be reduced to 1 / 100 compared to the case where the reception of the second data signal (DT2) must be completed between timing t1 and timing t2.

[0063] Furthermore, in this embodiment 1, since the first and second data signals (DT1, DT2) are received via different communication lines (21, 22), the communication speeds of each communication line (21, 22) can be set slower compared to the case where the first and second data signals (DT2) are received via a common communication line.

[0064] (Embodiment 2) Figure 6 is a diagram corresponding to Figure 1 of Embodiment 2. In Embodiment 2, the receiving circuit (30) receives first and second data signals (DT1, DT2) and an address (AD) as identification information on a common communication line (23). The address (AD) indicates the address in the memory (40). The first data signal (DT1) transmitted on the communication line (23) is associated with the address (AD) of the first storage area (41). The second data signal (DT2) transmitted on the communication line (23) is associated with the address (AD) of the second storage area (42).

[0065] The receiving circuit (30) has a decoder that reads the address (AD). The receiving circuit (30) then allocates a first parameter (PA1) corresponding to the received first data signal (DT1) and a second parameter (PA2) corresponding to the received second data signal (DT2) to the first and second storage areas (41, 42) of the memory (40) by referring to the address (AD).

[0066] Figure 7 is a diagram corresponding to Figure 4 of Embodiment 2.

[0067] In Figure 7, address 1 represents the address of the first memory area (41), and address 2 represents the address of the second memory area (42). In Figure 7, the first data signals (DT1), data 1, data 3, and data 5, respectively, show the waveforms of the gate voltage when it is ON during periods T22, T24, and T26. The second data signals (DT2), data 2 and data 4, respectively, show the waveforms of the gate voltage when it is OFF during periods T23 and T25.

[0068] In Figure 7, the ON waveform of the gate voltage of the second switching element (12) is changed twice consecutively during periods T24 and T26. The reception of data 5, which is the first data signal (DT1) indicating the first parameter (PA2) related to the waveform during the second ON period (waveform in period T26), starts before the OFF period immediately preceding the second ON period (start of period T25). The pulse width of the rising pulse at the start of reception of data 5 is small, and the gate drive signal (GD) falls (changes) while data 5 is being written to the first memory area (41) (while the first memory area (41) is being rewritten). However, the second parameter (PA2) related to this falling waveform (waveform in period T25) is read from the second memory area (42), so the write and read operations to the common memory areas (41, 42) do not occur simultaneously.

[0069] Since the other components are the same as in Embodiment 1, the same reference numerals are used for the same components, and their detailed descriptions are omitted.

[0070] According to this second embodiment, similar to the first embodiment, the effect of being able to more freely set the periods of consecutive off states and consecutive on states is obtained.

[0071] Furthermore, since there is no need to provide separate communication lines for the communication of the first and second data signals (DT1, DT2), the number of communication lines can be reduced.

[0072] (Embodiment 3) Figure 8 is a diagram corresponding to Figure 1 of Embodiment 3. In Embodiment 3, the receiving circuit (30) receives the first and second data signals (DT1, DT2) on a common communication line (23), but does not receive the address (AD). When the gate drive signal (GD) is rising, the first data signal (DT1) relating to the ON waveform is transmitted to the communication line (23) by an external communication device. On the other hand, when the gate drive signal (GD) is falling, the second data signal (DT2) relating to the OFF waveform is transmitted to the communication line (23) by an external communication device. In addition, the first and second storage areas (41, 42) of the memory (40) each include the first and second partition areas (41a, 41b, 42a, 42b). The receiving circuit (30) allocates a first parameter (PA1) corresponding to the received first data signal (DT1) and a second parameter (PA2) corresponding to the received second data signal (DT2) to the first and second partition areas (41a, 41b, 42a, 42b) of the first and second storage areas (41, 42) of the memory (40) by referring to the gate drive signal (GD). When the receiving circuit (30) receives the first data signal (DT1), it outputs the first parameter (PA1) corresponding to the first data signal (DT1) to one of the partition areas (41a, 41b) in the first storage area (41). One of the partitioned areas (41a, 41b) is a different partitioned area (41a, 41b) from the first and second partitioned areas (41a, 41b) that stores the first parameter (PA1) most recently referenced by the variable gate drive circuit (50). Similarly, when the receiving circuit (30) receives the second data signal (DT2), it outputs the second parameter (PA2) corresponding to the second data signal (DT2) to one of the partitioned areas (42a, 42b) in the second storage area (42). This one partitioned area (42a, 42b) is a different partitioned area (42a, 42b) from the first and second partitioned areas (42a, 42b) that stores the second parameter (PA2) most recently referenced by the variable gate drive circuit (50). Furthermore, the gate drive device (20) is further equipped with a selection circuit (60).This selection circuit (60) switches the memory area to be read (referenced) between the first and second partition areas (41a, 41b) in the first memory area (41), and also between the first and second partition areas (42a, 42b) in the second memory area (42).

[0073] Specifically, as shown in Figure 9, the receiving circuit (30) includes a D flip-flop (35) and first to fourth selectors (36 to 39).

[0074] The D flip-flop (35) outputs a phase signal (FS) from its non-inverting output that switches (toggles) with each rising edge of the gate drive signal (GD). The non-inverting output (phase signal (FS)) of the D flip-flop (35) is input as a selection signal to the first and fourth selectors (36, 39). The inverting output of the D flip-flop (35) is input as a D input to the D flip-flop (35). The inverting output of the D flip-flop (35) is input as a selection signal to the second and third selectors (37, 38). The first and second data signals (DT1, DT2) are input serially to one of the two input terminals of the first to fourth selectors (36 to 39). An invalid signal (DS), which is always 0, is input to the other of the two input terminals of the first to fourth selectors (36 to 39).

[0075] The selection circuit (60) has fifth and sixth selectors (61, 62). The output of the first partition area (41a) of the first memory area (41) is input to one input terminal of the fifth selector (61). The output of the second partition area (41b) of the first memory area (41) is input to the other input terminal of the fifth selector (61). The inverted output of the D flip-flop (35) is input to the fifth selector (61) as the selection signal. The output of the first partition area (42a) of the second memory area (42) is input to one input terminal of the sixth selector (62). The output of the second partition area (41b) of the second memory area (41) is input to the other input terminal of the sixth selector (62). The non-inverted output (phase signal (FS)) of the D flip-flop (35) is input to the sixth selector (62) as the selection signal.

[0076] Therefore, when the phase signal (FS) is at a low level, the receiving circuit (30) allocates the data signals (DT1, DT2) of the communication line (23) to the second partition area (41b) of the first memory area (41) and the first partition area (42a) of the second memory area (42). The fifth selector (61) outputs the first parameter (PA1) from the first partition area (41a) of the first memory area (41). The sixth selector (62) outputs the second parameter (PA2) from the second partition area (42b) of the second memory area (42).

[0077] On the other hand, when the phase signal (FS) is at a high level, the receiving circuit (30) allocates the data signals (DT1, DT2) of the communication line (23) to the first partition area (41a) of the first memory area (41) and the second partition area (42b) of the second memory area (42). The fifth selector (61) outputs the first parameter (PA1) from the second partition area (41b) of the first memory area (41). The sixth selector (62) outputs the second parameter (PA2) from the first partition area (42a) of the second memory area (42). The outputs of the fifth and sixth selectors (61, 62) are input to the register (51d) of the variable gate drive circuit (50).

[0078] Figure 10 is a diagram corresponding to Figure 4 of Embodiment 3.

[0079] In Figure 10, memory 11 indicates that data is written to the first partition area (41a) of the first storage area (41), and memory 12 indicates that data is written to the second partition area (41b) of the first storage area (41). Similarly, memory 21 indicates that data is written to the first partition area (42a) of the second storage area (42), and memory 22 indicates that data is written to the second partition area (42b) of the second storage area (42). In Figure 10, data 1, data 3, and data 5 show the waveforms of the gate voltage when it is ON during periods T32, T34, and T36, respectively. The second data signals (DT2), data 2 and data 4, show the waveforms of the gate voltage when it is OFF during periods T33 and T35, respectively.

[0080] During period T32, the variable gate drive circuit (50) reads the first parameter (PA1) indicated by data 1 from the first partition area (41a) of the first memory area (41). During period T33, the variable gate drive circuit (50) reads the second parameter (PA2) indicated by data 2 from the first partition area (42a) of the second memory area (42). During period T34, the variable gate drive circuit (50) reads the first parameter (PA1) indicated by data 3 from the second partition area (41b) of the first memory area (41). During period T35, the variable gate drive circuit (50) reads the second parameter (PA2) indicated by data 4 from the second partition area (42b) of the second memory area (42). During period T36, the variable gate drive circuit (50) reads out the first parameter (PA1) indicated by data 5 from the first partition area (41a) of the first memory area (41).

[0081] Thus, in this embodiment 3, when the receiving circuit (30) receives a first data signal (DT1), it outputs a first parameter (PA1) corresponding to the first data signal (DT1) to a partition area (41a, 41b) in the first memory area (41) that is different from the partition area (41a, 41b) that stores the first parameter (PA1) most recently referenced by the variable gate drive circuit (50). In this specification, the partition area (41a, 41b) most recently referenced by the variable gate drive circuit (50) includes the partition area (41a, 41b) that is currently being referenced (read out). Furthermore, when the receiving circuit (30) receives the second data signal (DT2), it outputs a second parameter (PA2) corresponding to the second data signal (DT2) to a partition area (42a, 42b) in the second memory area (42) that is different from the partition area (42a, 42b) that stores the second parameter (PA2) most recently referenced by the variable gate drive circuit (50).

[0082] Since the other components are the same as in Embodiment 1, the same reference numerals are used for the same components, and their detailed descriptions are omitted.

[0083] Therefore, according to this third embodiment, simultaneous writing and reading operations on the common partition area (41a, 41b, 42a, 42b) can be suppressed.

[0084] Furthermore, since it is not necessary to receive identification information (AD) for allocating the first and second data signals (DT1, DT2) to the first and second memory areas (41, 42) via the communication line (23), the communication speed via the communication line (23) can be set slower compared to when the identification information (AD) is received via the communication line (23).

[0085] In this third embodiment, the first and second partitioned areas (41a, 41b, 42a, 42b) of the first and second storage areas (41, 42) of the memory (40) do not have to be fixed storage areas. For example, there may be timings for using a predetermined storage area as the first storage area (41) and timings for using it as the second storage area (42).

[0086] In the above embodiment 2, the receiving circuit (30) allocated the first and second parameters (PA1, PA2) to the first and second memory areas (41, 42) by referring to the address (AD) sent to the common communication line (23) with the first and second data signals (DT1, DT2). However, the receiving circuit (30) may also allocate the first and second parameters (PA1, PA2) to the first and second memory areas (41, 42) by referring to the gate drive signal (GD). For example, the memory areas (41, 42) to be allocated may be determined based on whether or not transmission has started within the rising edge of the gate drive signal (GD) or within a predetermined period based on the rising edge. As a result, it is not necessary to receive addresses (AD) for assigning the first and second data signals (DT1, DT2) to the first and second memory areas (41, 42) via the communication line (23). Therefore, the communication speed via the communication line (23) can be set slower compared to when the addresses (AD) are received via the communication line (23).

[0087] Furthermore, in embodiments 1 to 3 described above, the first or second parameter (PA1, PA2) output by the register (51d) is made into time-series data, thereby making the gate voltage (GS) waveform a waveform that changes over time. However, the first or second parameter (PA1, PA2) may not be made into time-series data, and the gate voltage (GS) waveform may not change over time.

[0088] Furthermore, in embodiments 1 to 3 described above, if the waveform of the gate voltage (GS) when it is turned on is changed twice in a row, and the time from the off operation immediately preceding the second on operation to the second on operation is longer than the time required to receive the first data signal (DT1) relating to the waveform when it is turned on the second time, the first receiving circuit (30a) may start receiving the first data signal (DT1) after the off operation immediately preceding the second on operation. Also, the first receiving circuit (30a) may perform the first preparatory operation only if the time from the off operation immediately preceding the second on operation to the second on operation is shorter than the time required to receive the first data signal (DT1) relating to the waveform when it is turned on the second time. In other words, it is sufficient that the operation of the first receiving circuit (30a) includes the first preparatory operation.

[0089] The same applies to the second preparatory action.

[0090] Furthermore, in embodiments 1 to 3 described above, the operation of the receiving circuit (30) included both the first and second preparatory operations, but it is also possible to include only one of the preparatory operations.

[0091] Furthermore, in embodiments 1 to 3 described above, the variable gate drive circuit (50) is configured to adjust the gate voltage (GS) by providing multiple transistors (52c, 52d) and adjusting the number of transistors (52c, 52d) that are turned on. However, the variable gate drive circuit (50) may also be configured to adjust the gate voltage (GS) by providing multiple resistors or batteries and adjusting the number of resistors or batteries through which current flows.

[0092] While embodiments have been described above, it will be understood that various modifications to the form and details are possible without departing from the spirit and scope of the claims. Furthermore, the above embodiments and modifications may be combined or substituted as appropriate, as long as they do not impair the functions covered by this disclosure. [Industrial applicability]

[0093] This disclosure is useful as a gate drive device for applying a gate voltage to a semiconductor switch and a power conversion device equipped therewith. [Explanation of Symbols]

[0094] 1. Power converter 12. Second switching element (semiconductor switch) 20 Gate drive unit 21. First communication line 22 Second communication line 23 Communication lines 30 Receiving Circuit 40 Memory (storage unit) 41. First memory area 41a First partitioned area 41b Second partition area 42 Second memory area 42a First partitioned area 42b Second partition area 50 Variable gate drive circuit AD Address (Identification Information) DT1 First data signal DT2 Second data signal PA1 First parameter PA2 Second parameter GD gate drive signal GS gate signal (gate voltage)

Claims

1. A gate drive device for applying a gate voltage (GS) to a semiconductor switch (12), A rewritable storage unit (40) having a first storage area (41) for storing a first parameter (PA1) relating to the waveform when the gate voltage (GS) is ON, and a second storage area (42) for storing a second parameter (PA2) relating to the waveform when the gate voltage (GS) is OFF, A drive circuit (50) that refers to a gate drive signal (GD) and first and second parameters (PA1, PA2) stored in the memory unit (40), and applies a gate voltage (GS) with a waveform corresponding to the first and second parameters (PA1, PA2) to the semiconductor switch (12), The system includes a receiving circuit (30) that receives a first data signal (DT1) indicating the first parameter (PA1) and a second data signal (DT2) indicating the second parameter (PA2), and outputs the first parameter (PA1) corresponding to the first data signal (DT1) and the second parameter (PA2) corresponding to the second data signal (DT2) to the storage unit (40). The operation of the receiving circuit (30) is as follows: A first preparatory operation in which, when the waveform of the gate voltage (GS) is changed twice in a row, the reception of the first data signal (DT1) indicating the first parameter (PA1) related to the waveform of the second on-time is started before the off-time immediately preceding the second on-time, A gate drive device that includes at least one of the following preparatory operations: a second preparatory operation in which, when the waveform of the gate voltage (GS) is changed twice in a row while it is off, reception of a second data signal (DT2) indicating a second parameter (PA2) relating to the waveform during the second off-time is started before the on-time immediately preceding the second off-time.

2. In the gate drive device according to claim 1, The receiving circuit (30) is a gate drive device that receives the first and second data signals (DT1, DT2) via different communication lines (21, 22).

3. In the gate drive device according to claim 1, The receiving circuit (30) receives the first and second data signals (DT1, DT2) on a common communication line (23), receives identification information (AD), and is a gate drive device that allocates the first parameter (PA1) corresponding to the received first data signal (DT1) and the second parameter (PA2) corresponding to the received second data signal (DT2) to the first and second storage areas (41, 42) of the storage unit (40) by referring to the identification information (AD).

4. In the gate drive device according to claim 1, The receiving circuit (30) receives the first and second data signals (DT1, DT2) on a common communication line (23), and is a gate drive device that allocates the first parameter (PA1) corresponding to the received first data signal (DT1) and the second parameter (PA2) corresponding to the received second data signal (DT2) to the first and second storage areas (41, 42) of the storage unit (40) with reference to the gate drive signal (GD).

5. In the gate drive device according to claim 1, The first and second memory areas (41, 42) each include the first and second partition areas (41a, 41b, 42a, 42b), When the receiving circuit (30) receives the first data signal (DT1), it outputs a first parameter (PA1) corresponding to the first data signal (DT1) to a partition area (41a, 41b) in the first memory area (41) that is different from the partition area (41a, 41b) that stores the first parameter (PA1) most recently referenced by the driving circuit (50). A gate drive device that, upon receiving the second data signal (DT2), outputs a second parameter (PA2) corresponding to the second data signal (DT2) to a partition area (42a, 42b) in the second memory area (42) that is different from the partition area (42a, 42b) that stores the second parameter (PA2) most recently referenced by the drive circuit (50).

6. A gate drive device according to any one of claims 1 to 5, A power conversion device comprising the aforementioned semiconductor switch (12).

Images