Display device including thin-film transistors, and method for manufacturing the same

Abstract

SOLUTION: A display 110 includes: a substrate 120 including a display area DA and a non-display area NDA surrounding the display area; a first semiconductor layer 124 containing a polycrystalline semiconductor material and a second semiconductor layer 126 containing an oxide semiconductor material, which are disposed in a non-display area on the substrate; a first gate insulating layer 128 placed on the first and second semiconductor layers; a first gate electrode 130 and a second gate electrode 132, corresponding to the first and second semiconductor layers, respectively, and located on the first gate insulating layer; a first interlayer dielectric layer 136 placed over the first and second gate electrodes; a first source electrode 146 disposed on the first interlayer insulating layer and connected to both ends of the first semiconductor layer; and a second source electrode 152 and a second drain electrode 154 disposed on the first drain electrode 148 and the first interlayer insulating layer and connected to both ends of the second semiconductor layer respectively.EFFECT: By forming thin film transistors of polycrystalline semiconductor materials and thin-film transistors of oxide semiconductor materials on a same substrate, power consumption and manufacturing costs can be reduced.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a display device, and more particularly to an organic light-emitting diode including a polycrystalline thin-film transistor and an oxide thin-film transistor, as well as a method for manufacturing the same. [Background technology]

[0002] In recent years, with the advent of the information society, interest in information displays that process and display vast amounts of information has increased, and in response to the growing demand for portable information media, various lightweight and thin flat display devices have been developed and are attracting attention.

[0003] Among these flat-panel displays, organic light-emitting diode (OLED) displays are self-illuminating elements that do not require a separate light source such as a backlight. Because they offer advantages in terms of viewing angle, contrast ratio, and power consumption, they are widely used in various fields.

[0004] The drive unit and pixels of the organic light-emitting diode display device each include thin-film transistors, but it is preferable that the thin-film transistors of the drive unit have relatively high mobility, and the thin-film transistors of the pixels have relatively low off-current.

[0005] However, when the thin-film transistors of the drive unit and the thin-film transistors of the pixels are formed from the same semiconductor material using the same process, there is a problem in that it is difficult to achieve high mobility in the thin-film transistors of the drive unit and low off-current in the thin-film transistors of the pixels.

[0006] Furthermore, the inability to employ driving methods such as variable refresh rate (VRR) limited the reduction in power consumption. [Overview of the project] [Problems that the invention aims to solve]

[0007] The present invention is presented to solve the aforementioned problems and aims to provide a display device that reduces power consumption by forming a thin-film transistor of a polycrystalline semiconductor material and a thin-film transistor of an oxide semiconductor material on the same substrate, as well as a method for manufacturing the same.

[0008] Another objective of the present invention is to provide a display device and a method for manufacturing the same, which simplify the manufacturing process and reduce manufacturing costs by forming a thin-film transistor of a polycrystalline semiconductor material and a thin-film transistor of an oxide semiconductor material using a gate insulating layer and a gate electrode of the same layer. [Means for solving the problem]

[0009] To solve the aforementioned problems, the present invention provides a display device comprising: a substrate including a display area and a non-display area surrounding the display area; a first semiconductor layer disposed in the non-display area on the substrate and containing a polycrystalline semiconductor material; a second semiconductor layer disposed in the display area on the substrate and containing an oxide semiconductor material; a first gate insulating layer disposed on the first semiconductor layer and the second semiconductor layer; a first gate electrode and a second gate electrode disposed on the first gate insulating layer corresponding to the first semiconductor layer and the second semiconductor layer, respectively; a first interlayer insulating layer disposed on the first gate electrode and the second gate electrode; a first source electrode and a first drain electrode disposed on the first interlayer insulating layer and connected to both ends of the first semiconductor layer, respectively; and a second source electrode and a second drain electrode disposed on the first interlayer insulating layer and connected to both ends of the second semiconductor layer, respectively.

[0010] Furthermore, the first semiconductor layer and the second semiconductor layer may be in the same layer.

[0011] The display device may further include a first buffer layer disposed between the substrate and the first and second semiconductor layers, a second buffer layer, a second interlayer insulating layer, a first planarization layer, and a second planarization layer sequentially disposed on the first interlayer insulating layer, a storage capacitor disposed between the first gate insulating layer and the second buffer layer, a light-emitting diode disposed on the second planarization layer, and a first sealing layer, a second sealing layer, and a third sealing layer sequentially disposed on the light-emitting diode.

[0012] Furthermore, the display device further includes a first gate extension electrode and a second gate extension electrode connected to the first gate electrode and the second gate electrode, respectively, and a capacitor extension electrode connected to the storage capacitor. The first gate extension electrode, the first source electrode, the first drain electrode, the second gate extension electrode, the second source electrode, and the second drain electrode can all be formed on the second interlayer insulating layer in the same layer and from the same material.

[0013] Furthermore, the display device further includes a second gate insulating layer disposed over the entire surface of the first semiconductor layer, and the second semiconductor layer may be disposed on the second gate insulating layer.

[0014] Furthermore, the display device may further include a second gate insulating layer disposed on the first semiconductor layer and below the second semiconductor layer.

[0015] Furthermore, the first semiconductor layer and the second gate insulating layer on the first semiconductor layer may have the same shape, and the second semiconductor layer and the second gate insulating layer beneath the second semiconductor layer may have the same shape.

[0016] In addition, the display device further includes a first gate extension electrode disposed on the first interlayer insulating layer and connected to the first gate electrode, and a second gate extension electrode disposed on the first interlayer insulating layer and connected to the second gate electrode. The first gate extension electrode, the first source electrode, the first drain electrode, the second gate extension electrode, the second source electrode, and the second drain electrode can be formed of the same material in the same layer on the first interlayer insulating layer.

[0017] In addition, the display device can further include a first buffer layer disposed between the substrate and the first semiconductor layer and the second semiconductor layer, a second buffer layer, a first planarization layer, and a second planarization layer sequentially disposed on the first interlayer insulating layer, a storage capacitor disposed between the first gate insulating layer and the second buffer layer, a light-emitting diode disposed on the second planarization layer, and a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer sequentially disposed on the light-emitting diode.

[0018] In addition, the display device further includes a first source extension electrode, a first drain extension electrode, a second source extension electrode, and a second drain extension electrode respectively connected to the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode. The first source extension electrode, the first drain extension electrode, the second source extension electrode, and the second drain extension electrode can be formed of the same material in the same layer on the first planarization layer.

[0019] In addition, the second source electrode can be connected to the storage capacitor.

Advantages of the Invention

[0020] The present invention has the effect of reducing power consumption by forming a thin-film transistor of a polycrystalline semiconductor material and a thin-film transistor of an oxide semiconductor material on the same substrate.

[0021] Furthermore, the present invention simplifies the manufacturing process and reduces manufacturing costs by forming thin-film transistors of polycrystalline semiconductor material and thin-film transistors of oxide semiconductor material using the gate insulating layer and gate electrode of the same layer. [Brief explanation of the drawing]

[0022] [Figure 1] This figure shows a display device according to the first embodiment of the present invention. [Figure 2] This is a cross-sectional view showing the non-display area and the display area in a display device according to the first embodiment of the present invention. [Figure 3A] This is a cross-sectional view illustrating a method for manufacturing a display device according to the first embodiment of the present invention. [Figure 3B] This is a cross-sectional view illustrating a method for manufacturing a display device according to the first embodiment of the present invention. [Figure 3C] This is a cross-sectional view illustrating a method for manufacturing a display device according to the first embodiment of the present invention. [Figure 3D] This is a cross-sectional view illustrating a method for manufacturing a display device according to the first embodiment of the present invention. [Figure 3E] This is a cross-sectional view illustrating a method for manufacturing a display device according to the first embodiment of the present invention. [Figure 3F] This is a cross-sectional view illustrating a method for manufacturing a display device according to the first embodiment of the present invention. [Figure 4] This is a cross-sectional view showing the non-display area and the display area in a display device according to a second embodiment of the present invention. [Figure 5A] This is a cross-sectional view illustrating a method for manufacturing a display device according to a second embodiment of the present invention. [Figure 5B] This is a cross-sectional view illustrating a method for manufacturing a display device according to a second embodiment of the present invention. [Figure 5C] This is a cross-sectional view illustrating a method for manufacturing a display device according to a second embodiment of the present invention. [Figure 5D] This is a cross-sectional view illustrating a method for manufacturing a display device according to a second embodiment of the present invention. [Figure 5E]This is a cross-sectional view illustrating a method for manufacturing a display device according to a second embodiment of the present invention. [Figure 5F] This is a cross-sectional view illustrating a method for manufacturing a display device according to a second embodiment of the present invention. [Figure 6] This is a cross-sectional view showing the non-display area and the display area in a display device according to a third embodiment of the present invention. [Figure 7A] This is a cross-sectional view illustrating a method for manufacturing a display device according to a third embodiment of the present invention. [Figure 7B] This is a cross-sectional view illustrating a method for manufacturing a display device according to a third embodiment of the present invention. [Figure 7C] This is a cross-sectional view illustrating a method for manufacturing a display device according to a third embodiment of the present invention. [Figure 7D] This is a cross-sectional view illustrating a method for manufacturing a display device according to a third embodiment of the present invention. [Figure 7E] This is a cross-sectional view illustrating a method for manufacturing a display device according to a third embodiment of the present invention. [Figure 7F] This is a cross-sectional view illustrating a method for manufacturing a display device according to a third embodiment of the present invention. [Figure 8] This is a cross-sectional view showing the non-display area and the display area in a display device according to the fourth embodiment of the present invention. [Figure 9A] This is a cross-sectional view illustrating a method for manufacturing a display device according to a fourth embodiment of the present invention. [Figure 9B] This is a cross-sectional view illustrating a method for manufacturing a display device according to a fourth embodiment of the present invention. [Figure 9C] This is a cross-sectional view illustrating a method for manufacturing a display device according to a fourth embodiment of the present invention. [Figure 9D] This is a cross-sectional view illustrating a method for manufacturing a display device according to a fourth embodiment of the present invention. [Figure 9E] This is a cross-sectional view illustrating a method for manufacturing a display device according to a fourth embodiment of the present invention. [Modes for carrying out the invention]

[0023] The following description of a display device including a thin-film transistor according to the present invention will be given with reference to the drawings.

[0024] Figure 1 shows a display device according to a first embodiment of the present invention, and the display device may be an organic light-emitting diode device (OLED display device).

[0025] As shown in Figure 1, the display device 110 according to the first embodiment of the present invention may include a timing control unit TC, a data drive unit DD, a first gate drive unit GD1, a second gate drive unit GD2, and a display panel DP.

[0026] The timing control unit TC can generate video data, data control signals, and gate control signals using multiple timing signals such as video signals, data enable signals, horizontal synchronization signals, vertical synchronization signals, and clock signals transmitted from an external system (not shown), such as a graphics card or television system. The timing control unit TC also transmits the generated video data and data control signals to the data drive unit DD, and transmits the generated gate control signals to the first gate drive unit GD1 and the second gate drive unit GD2.

[0027] The data drive unit DD generates a data signal (data voltage) using the data control signal and video data transmitted from the timing control unit TC, and applies the generated data signal to the data wiring DL of the display panel DP.

[0028] The first gate drive unit GD1 and the second gate drive unit GD2 generate a gate signal (gate voltage) using a gate control signal transmitted from the timing control unit TC, and apply the generated gate signal to the gate wiring GL of the display panel DP.

[0029] For example, a gate signal can include a scan signal, a sensing signal, and a light emission signal.

[0030] The first gate drive unit GD1 and the second gate drive unit GD2 each include a shift register containing multiple stages connected in a cascaded manner, and each stage in the shift register contains multiple circuit thin-film transistors (T1 in Figure 2), and at least one of the multiple circuit thin-film transistors T1 may include a semiconductor layer (active layer) made of a polycrystalline semiconductor material such as polycrystalline silicon.

[0031] Here, the first gate driver unit GD1 and the second gate driver unit GD2 may be of the gate driver in panel (GIP) type, formed together on the substrate of the display panel DP where the gate wiring GL, data wiring DL, and pixels P are formed, and located in the non-display area NDA.

[0032] In the embodiment shown in Figure 1, the first gate drive unit GD1 and the second gate drive unit GD2 are arranged on both sides of the display panel DP. However, in another embodiment, one gate drive unit may be arranged on one side of the display panel DP.

[0033] The display panel DP includes a central display area DA and a non-display area NDA surrounding the display area DA, and displays images using gate signals and data signals. The display panel DP includes multiple pixels P, multiple gate lines GL, and multiple data lines DL arranged in the display area DA to display images.

[0034] Each of the multiple pixels P includes a first sub-pixel SP1 to a fourth sub-pixel SP4, and the gate wiring GL and data wiring DL intersect with each other, demarcating the first sub-pixel SP1 to the fourth sub-pixel SP4. Furthermore, the first sub-pixel SP1 to the fourth sub-pixel SP4 are connected to the gate wiring GL and data wiring DL, respectively. For example, the first sub-pixel SP1 to the fourth sub-pixel SP4 can correspond to red, green, blue, and white, respectively.

[0035] Each of the first to fourth sub-pixels SP1 to SP4 includes multiple pixel thin-film transistors (T2 in Figure 2), such as a switching thin-film transistor, a driving thin-film transistor, and a reference thin-film transistor, as well as a storage capacitor (Cs in Figure 2) and a light-emitting diode (De in Figure 2). At least one of the multiple pixel thin-film transistors T2 may include a semiconductor layer (active layer) made of an oxide semiconductor material such as indium gallium zinc oxide (IGZO).

[0036] The cross-sectional configuration of the display device 110 will be explained with reference to the drawings.

[0037] Figure 2 is a cross-sectional view showing the non-display area and the display area in a display device according to the first embodiment of the present invention. It will be explained with reference to both Figure 1 and Figure 2.

[0038] As shown in Figure 2, in the display device 110 according to the first embodiment of the present invention, a first thin-film transistor T1, which is a circuit thin-film transistor, is arranged in the first gate drive unit GD1 and the second gate drive unit GD2 of the non-display area NDA, and a second thin-film transistor T2, which is a pixel thin-film transistor, a storage capacitor Cs, and a light-emitting diode De are arranged in each sub-pixel SP1 to SP4 of the display area DA.

[0039] To explain in more detail, a first buffer layer 122 is arranged across the entire surface of the substrate 120, and a first semiconductor layer 124 and a second semiconductor layer 126 are arranged on the first gate drive unit GD1 and the second gate drive unit GD2 of the non-display area NDA, and on each of the sub-pixels SP1 to SP4 of the display area DA, respectively.

[0040] For example, the first buffer layer 122 is made of silicon oxide (SiO2) and silicon nitride (SiN x It may be a single layer or multilayer made of inorganic insulating material such as ).

[0041] The first semiconductor layer 124 includes an undoped channel region 124a and impurity-doped source regions 124b and drain regions 124c on either side of the channel region 124a. The second semiconductor layer 126 includes an undoped channel region 126a and impurity-doped (or conductor-made) source regions 126b and drain regions 126c on either side of the channel region 126a.

[0042] For example, the first semiconductor layer 124 may consist of a polycrystalline semiconductor material such as polycrystalline silicon, and the second semiconductor layer 126 may consist of oxide semiconductor materials such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), and indium aluminum zinc oxide (IAZO).

[0043] A first gate insulating layer 128 is placed over the entire surface of the first semiconductor layer 124 and the second semiconductor layer 126. A first gate electrode 130 and a second gate electrode 132 are placed on the first gate insulating layer 128 corresponding to the first semiconductor layer 124 and the second semiconductor layer 126, respectively. A first capacitor electrode 134 is placed on each of the sub-pixels SP1 to SP4 of the display area DA on the first gate insulating layer 128.

[0044] For example, the first gate insulating layer 128 is made of silicon oxide (SiO2) and silicon nitride (SiN x It may be a single layer or multilayer made of inorganic insulating material such as ).

[0045] The first gate electrode 130, the second gate electrode 132, and the first capacitor electrode 134 can be formed in the same layer from the same material.

[0046] For example, the first gate electrode 130, the second gate electrode 132, and the first capacitor electrode 134 may be single-layer or multi-layer structures made of a metallic material such as one of the following: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0047] The first gate electrode 130, the first gate insulating layer 128, and the first semiconductor layer 124 constitute the first thin-film transistor T1, and the second gate electrode 132, the first gate insulating layer 128, and the second semiconductor layer 126 constitute the second thin-film transistor T2.

[0048] A first interlayer insulating layer 136 is placed over the entire surface of the first gate electrode 130, the second gate electrode 132, and the first capacitor electrode 134, and a second capacitor electrode 138 is placed on the first interlayer insulating layer 136 corresponding to the first capacitor electrode 134.

[0049] For example, the first interlayer insulating layer 136 is made of silicon oxide (SiO2) and silicon nitride (SiN x It may be a single layer or multilayer made of inorganic insulating material such as ).

[0050] For example, the second capacitor electrode 138 may be a single layer or a multilayer made of a metallic material such as one of the following: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0051] The first capacitor electrode 134, the first interlayer insulating layer 136, and the second capacitor electrode 138 constitute a storage capacitor Cs.

[0052] A second buffer layer 140 can be placed over the entire surface of the second capacitor electrode 138, and a second interlayer insulating layer 142 can be placed over the entire surface of the second buffer layer 140.

[0053] For example, the second buffer layer 140 is made of silicon oxide (SiO2) and silicon nitride (SiN x The second interlayer insulating layer 142 may be a single layer or multilayer made of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiN). x It may be a single layer or multilayer made of inorganic insulating material such as ).

[0054] On the second interlayer insulating layer 142 corresponding to the first thin-film transistor T1, a first gate extension electrode 144, a first source electrode 146, and a first drain electrode 148 are arranged. On the second interlayer insulating layer 142 corresponding to the second thin-film transistor T2, a second gate extension electrode 150, a second source electrode 152, and a second drain electrode 154 are arranged. In addition, a capacitor extension electrode 156 is arranged on the second interlayer insulating layer 142 corresponding to the storage capacitor Cs, and a first planarization layer 158 is arranged over the entire surface of the first gate extension electrode 144, the first source electrode 146, the first drain electrode 148, the second gate extension electrode 150, the second source electrode 152, the second drain electrode 154, and the capacitor extension electrode 156.

[0055] The first gate extension electrode 144 is connected to the first gate electrode 130 via the contact holes of the second interlayer insulating layer 142, the second buffer layer 140, and the first interlayer insulating layer 136; the first source electrode 146 is connected to the source region 124b of the first semiconductor layer 124 via the contact holes of the second interlayer insulating layer 142, the second buffer layer 140, the first interlayer insulating layer 136, and the first gate insulating layer 128; and the first drain electrode 148 is connected to the drain region 124c of the first semiconductor layer 124 via the contact holes of the second interlayer insulating layer 142, the second buffer layer 140, the first interlayer insulating layer 136, and the first gate insulating layer 128.

[0056] The second gate extension electrode 150 is connected to the second gate electrode 132 via the contact holes of the second interlayer insulating layer 142, the second buffer layer 140, and the first interlayer insulating layer 136; the second source electrode 152 is connected to the source region 126b of the second semiconductor layer 126 via the contact holes of the second interlayer insulating layer 142, the second buffer layer 140, the first interlayer insulating layer 136, and the first gate insulating layer 128; and the second drain electrode 154 is connected to the drain region 126c of the second semiconductor layer 126 via the contact holes of the second interlayer insulating layer 142, the second buffer layer 140, the first interlayer insulating layer 136, and the first gate insulating layer 128.

[0057] The capacitor extension electrode 156 is connected to the second capacitor electrode 138 via contact holes in the second interlayer insulating layer 142 and the second buffer layer 140.

[0058] The first gate extension electrode 144, the first source electrode 146, the first drain electrode 148, the second gate extension electrode 150, the second source electrode 152, the second drain electrode 154, and the capacitor extension electrode 156 can be formed in the same layer from the same material.

[0059] For example, the first gate extension electrode 144, the first source electrode 146, the first drain electrode 148, the second gate extension electrode 150, the second source electrode 152, the second drain electrode 154, and the capacitor extension electrode 156 may be single-layer or multi-layer structures made of a metallic material such as one of the following: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0060] For example, the first planarization layer 158 may be a single layer or a multilayer made of an organic insulating material such as photoacrylic or benzocyclobutene (BCB).

[0061] A first connecting electrode 160 and a second connecting electrode 162 are placed at each subpixel SP1 to SP4 of the display area DA on the first flattening layer 158, and a second flattening layer 164 is placed over the entire surface of the first connecting electrode 160 and the second connecting electrode 162.

[0062] The first connecting electrode 160 is connected to the second drain electrode 154 through a contact hole in the first planarization layer 158.

[0063] Although not shown in the diagram, the second connecting electrode 162 can be connected to the second source electrode 152 and the capacitor extension electrode 156.

[0064] The first connecting electrode 160 and the second connecting electrode 162 can be formed in the same layer from the same material.

[0065] For example, the first connecting electrode 160 and the second connecting electrode 162 may be a single layer or a multilayer made of a metallic material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0066] For example, the second planarization layer 164 may be a single layer or a multilayer made of an organic insulating material such as photoacrylic or benzocyclobutene (BCB).

[0067] A first electrode 166 is placed on each subpixel SP1 to SP4 of the display area DA on the second flattening layer 164, and a bank layer 168 is placed over the entire surface of the first electrode 166.

[0068] The first electrode 166 is connected to the first connecting electrode 160 through a contact hole in the second planarization layer 164.

[0069] For example, the first electrode 166 may be an anode. It may also be a single layer or multilayer made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a translucent or opaque metallic material such as molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), titanium (Ti), or alloys thereof.

[0070] The bank layer 168 has an opening that covers the end of the first electrode 166 while exposing the central part of the first electrode 166.

[0071] For example, the bank layer 168 may be a single layer or a multilayer made of an organic insulating material such as photoacrylic or benzocyclobutene (BCB).

[0072] Trench TR can be formed on the bank layer 168 corresponding to the boundary between subpixels SP1 to SP4, and spacers 170 can be placed on the bank layer 168. Multiple trench TRs may exist between adjacent subpixels, and the bottom surface of the trench TR may abut against the second flattening layer 164, exposing the second flattening layer 164.

[0073] A light-emitting layer 172 is placed over the entire surface of the first electrode 166, and a second electrode 174 is placed over the entire surface of the light-emitting layer 172.

[0074] The light-emitting layer 172 is in contact with the first electrode 166 exposed through the opening of the bank layer 168, the side wall of the opening of the bank layer 168, the upper surface of the bank layer 168, and the side wall and upper surface of the spacer 170, but can be separated at the boundaries between the subpixels SP1 to SP4 by the trench TR.

[0075] The light-emitting layer 172 may include hole-related layers such as hole injection layers and hole transport layers, a light-emitting material layer, and electron-related layers such as electron transport layers and electron injection layers.

[0076] The second electrode 174 is not separated in the trench TR and can be extended while connected on the trench TR.

[0077] For example, the second electrode 174 may be a cathode. It may also be a single layer or multilayer made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a translucent or opaque metallic material such as molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), titanium (Ti), or alloys thereof.

[0078] The first electrode 166, the light-emitting layer 172, and the second electrode 174 constitute a light-emitting diode De.

[0079] A first sealing layer 176, a second sealing layer 178, and a third sealing layer 180 are sequentially arranged on the entire surface of the second electrode 174 to suppress moisture penetration.

[0080] For example, the first sealing layer 176 and the third sealing layer 180 are made of silicon oxide (SiO2) and silicon nitride (SiN x The second sealing layer 178 may consist of a single layer or multiple layers made of an inorganic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0081] The manufacturing method of such display device 110 will be explained with reference to the drawings.

[0082] Figures 3A to 3F are cross-sectional views illustrating the manufacturing method of a display device according to the first embodiment of the present invention. The explanation will be given with reference to both Figures 1 and 2.

[0083] As shown in Figure 3A, the first buffer layer 122 is formed over the entire surface of the substrate 120.

[0084] Subsequently, a polycrystalline semiconductor material layer (not shown) is formed on the first buffer layer 122, and then patterning is performed to form the first semiconductor layer 124 in the first gate drive section GD1 and the second gate drive section GD2 of the non-display area NDA.

[0085] Subsequently, an oxide semiconductor material layer (not shown) is formed on the first semiconductor layer 124 and the first buffer layer 122, and then patterning is performed to form the second semiconductor layer 126 on each sub-pixel SP1 to SP4 of the display area DA.

[0086] As shown in Figure 3B, the first gate insulating layer 128 is formed over the entire surface of the first semiconductor layer 124 and the second semiconductor layer 126.

[0087] As shown in Figure 3C, a first metallic material layer (not shown) is formed on the first gate insulating layer 128, and then patterning is performed to form a first gate electrode 130 corresponding to the first semiconductor layer 124, a second gate electrode 132 corresponding to the second semiconductor layer 126, and first capacitor electrodes 134 on each sub-pixel SP1 to SP4 of the display area DA.

[0088] Subsequently, the first gate electrode 130 and the second gate electrode 132 are used as doping masks to inject N-type or P-type impurities into the first semiconductor layer 124 and the second semiconductor layer 126. This divides the first semiconductor layer 124 into an undoped channel region 124a and impurity-doped source regions 124b and drain regions 124c on either side of the channel region 124a. The second semiconductor layer 126 is divided into an undoped channel region 126a and impurity-doped (or conductor-made) source regions 126b and drain regions 126c on either side of the channel region 126a.

[0089] The first gate electrode 130, the first gate insulating layer 128, and the first semiconductor layer 124 constitute the first thin-film transistor T1, and the second gate electrode 132, the first gate insulating layer 128, and the second semiconductor layer 126 constitute the second thin-film transistor T2.

[0090] Subsequently, a first interlayer insulating layer 136 is formed over the entire surface of the first gate electrode 130, the second gate electrode 132, and the first capacitor electrode 134.

[0091] As shown in Figure 3D, a second metallic material layer (not shown) is formed on the first interlayer insulating layer 136, and then patterning is performed to form the second capacitor electrode 138 corresponding to the first capacitor electrode 134.

[0092] The first capacitor electrode 134, the first interlayer insulating layer 136, and the second capacitor electrode 138 constitute a storage capacitor Cs.

[0093] Subsequently, a second buffer layer 140 is formed over the entire surface of the second capacitor electrode 138, and a second interlayer insulating layer 142 is formed over the entire surface of the second buffer layer 140. After patterning, contact holes exposing the first gate electrode 130 are formed in the second interlayer insulating layer 142, the second buffer layer 140, and the first interlayer insulating layer 136. Contact holes exposing the source region 124b of the first semiconductor layer 124 are formed in the second interlayer insulating layer 142, the second buffer layer 140, the first interlayer insulating layer 136, and the first gate insulating layer 128. Contact holes exposing the drain region 124c of the first semiconductor layer 124 are formed in the second interlayer insulating layer 142, the second buffer layer 140, the first interlayer insulating layer 136, and the first gate insulating layer 128. Furthermore, contact holes are formed in the second interlayer insulating layer 142, the second buffer layer 140, and the first interlayer insulating layer 136 to expose the second gate electrode 132; contact holes are formed in the second interlayer insulating layer 142, the second buffer layer 140, the first interlayer insulating layer 136, and the first gate insulating layer 128 to expose the source region 126b of the second semiconductor layer 126; contact holes are formed in the second interlayer insulating layer 142, the second buffer layer 140, the first interlayer insulating layer 136, and the first gate insulating layer 128 to expose the drain region 126c of the second semiconductor layer 126; and contact holes are formed in the second interlayer insulating layer 142 and the second buffer layer 140 to expose the second capacitor electrode 138.

[0094] Subsequently, a third metallic material layer (not shown) is formed over the entire surface of the second interlayer insulating layer 142, and then patterning is performed to form the first gate extension electrode 144, the first source electrode 146, and the first drain electrode 148 corresponding to the first thin-film transistor T1, the second gate extension electrode 150, the second source electrode 152, and the second drain electrode 154 corresponding to the second thin-film transistor T2, and the capacitor extension electrode 156 corresponding to the storage capacitor Cs.

[0095] As shown in Figure 3E, a first planarization layer 158 is formed over the entire surface of the first gate extension electrode 144, the first source electrode 146, the first drain electrode 148, the second gate extension electrode 150, the second source electrode 152, the second drain electrode 154, and the capacitor extension electrode 156, and then patterning is performed to form a contact hole in the first planarization layer 158 that exposes the second drain electrode 154.

[0096] Subsequently, a fourth metallic material layer (not shown) is formed over the entire surface of the first planarization layer 158, and then patterning is performed to form the first connecting electrode 160 and the second connecting electrode 162 on each sub-pixel SP1 to SP4 of the display area DA.

[0097] As shown in Figure 3F, a second planarization layer 164 is formed over the entire surface of the first connecting electrode 160 and the second connecting electrode 162, and then patterning is performed to form a contact hole in the second planarization layer 164 that exposes the first connecting electrode 160.

[0098] Subsequently, a first electrode material layer (not shown) is formed over the entire surface of the second planarization layer 164, and then patterning is performed to form the first electrode 166 on each sub-pixel SP1 to SP4 of the display area DA.

[0099] Subsequently, a bank layer 168 is formed on the first electrode 166, having an opening that covers the end of the first electrode 166 while exposing the central part of the first electrode 166. A spacer 170 is then formed on the bank layer 168, but a trench TR is formed on the bank layer 168 corresponding to the boundary between subpixels SP1 to SP4.

[0100] Subsequently, a light-emitting layer 172 is formed over the entire surface of the first electrode 166, but the light-emitting layer 172 can be separated at the boundaries between subpixels SP1 to SP4 by trenches TR.

[0101] Subsequently, a second electrode 174 is formed over the entire surface of the light-emitting layer 172. The second electrode 174 is not separated in the trench TR, but can be extended while remaining connected on the trench TR.

[0102] The first electrode 166, the light-emitting layer 172, and the second electrode 174 constitute a light-emitting diode De.

[0103] Subsequently, the first sealing layer 176, the second sealing layer 178, and the third sealing layer 180 are sequentially formed on the entire surface of the second electrode 174 to complete the display device 110.

[0104] As described above, in the display device 110 according to the first embodiment of the present invention, by forming a first thin-film transistor T1 using a polycrystalline semiconductor material as the semiconductor layer (active layer) and a second thin-film transistor T2 using an oxide semiconductor material as the semiconductor layer (active layer) on a single substrate 120, the first thin-film transistor T1 in the first gate drive unit GD1 and the second gate drive unit GD2 can have relatively high mobility, and the second thin-film transistor T2 in each sub-pixel SP1 to SP4 can have a relatively low off-current. As a result, a driving method such as variable refresh rate (VRR) can be adopted, which drives at a relatively low refresh rate for still images and a relatively high refresh rate for moving images, thereby reducing power consumption.

[0105] Furthermore, by forming a first semiconductor layer 124 containing a polycrystalline semiconductor material and a second semiconductor layer 126 containing an oxide semiconductor material in the same layer, forming a first gate insulating layer 128 in common on the first semiconductor layer 124 and the second semiconductor layer 126, and forming the first gate electrode 130 and the second gate electrode 132 in the same layer from the same material, the manufacturing process is simplified and manufacturing costs are reduced.

[0106] In another embodiment, a second gate insulating layer can be formed between the first semiconductor layer and the second semiconductor layer to improve the reliability of the first semiconductor layer, which will be explained with reference to the figure.

[0107] Figure 4 is a cross-sectional view showing the non-display area and the display area in a display device according to a second embodiment of the present invention. Descriptions of parts similar to those in the first embodiment are omitted.

[0108] As shown in Figure 4, in the display device 210 according to the second embodiment of the present invention, a first thin-film transistor T1, which is a circuit thin-film transistor, is arranged in the first gate drive unit GD1 and the second gate drive unit GD2 of the non-display area NDA, and a second thin-film transistor T2, which is a pixel thin-film transistor, a storage capacitor Cs, and a light-emitting diode De are arranged in each sub-pixel SP1 to SP4 of the display area DA.

[0109] Specifically, a first buffer layer 222 is placed over the entire surface of the substrate 220, and a first semiconductor layer 224 is placed in the first gate drive unit GD1 and the second gate drive unit GD2 of the non-display area NDA on the first buffer layer 222.

[0110] For example, the first buffer layer 222 is made of silicon oxide (SiO2) and silicon nitride (SiN x It may be a single layer or multilayer made of inorganic insulating material such as ).

[0111] The first semiconductor layer 224 includes an undoped channel region 224a and impurity-doped source regions 224b and drain regions 224c located on either side of the channel region 224a.

[0112] For example, the first semiconductor layer 224 may be made of a polycrystalline semiconductor material such as polycrystalline silicon.

[0113] A second gate insulating layer 225 is placed over the entire surface of the first semiconductor layer 224, and a second semiconductor layer 226 is placed on each sub-pixel SP1 to SP4 of the display area DA on the second gate insulating layer 225.

[0114] For example, the second gate insulating layer 225 is made of silicon oxide (SiO2) and silicon nitride (SiN x It may be a single layer or multilayer made of inorganic insulating material such as ).

[0115] The second semiconductor layer 226 includes an undoped channel region 226a and impurity-doped (or conductor-made) source region 226b and drain region 226c on either side of the channel region 226a.

[0116] For example, the second semiconductor layer 226 can consist of oxide semiconductor materials such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), and indium aluminum zinc oxide (IAZO).

[0117] A first gate insulating layer 228 is placed over the entire surface of the second semiconductor layer 226. A first gate electrode 230 and a second gate electrode 232 are placed on the first gate insulating layer 228 corresponding to the first semiconductor layer 224 and the second semiconductor layer 226, respectively. A first capacitor electrode 234 is placed on each of the sub-pixels SP1 to SP4 of the display area DA on the first gate insulating layer 228.

[0118] A second gate insulating layer 225 is disposed on the first semiconductor layer 224, a second semiconductor layer 226 is disposed on the second gate insulating layer 225, and a first gate insulating layer 228 is commonly disposed on the first semiconductor layer 224 and the second semiconductor layer 226, so that suitable conditions for the first semiconductor layer 224 of the polycrystalline semiconductor material (for example, changes in the characteristics of the first semiconductor layer 224 due to an etching solution, changes in the characteristics due to the deposition temperature of the first semiconductor layer 224 and the second gate insulating layer 225, changes in the characteristics due to a surface treatment for the first semiconductor layer 224) are satisfied, the second gate insulating layer 225 is formed, and the first gate insulating layer 228 is formed so as to satisfy suitable conditions for the second semiconductor layer 226 of the oxide semiconductor material. As a result, the reliability of the first semiconductor layer 224 and the second semiconductor layer 226 can be improved.

[0119] For example, the thickness of the second gate insulating layer 225 may be thinner than the thickness of the first gate insulating layer 228, and the first gate insulating layer 228 may be a single layer or a multilayer made of an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x ).

[0120] The first gate electrode 230, the second gate electrode 232, and the first capacitor electrode 234 can be formed of the same material in the same layer.

[0121] For example, the first gate electrode 230, the second gate electrode 232, and the first capacitor electrode 234 may be a single layer or a multilayer made of a metal material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0122] The first gate electrode 230, the second gate insulating layer 225, the first gate insulating layer 228, and the first semiconductor layer 224 constitute the first thin film transistor T1, and the second gate electrode 232, the first gate insulating layer 228, and the second semiconductor layer 226 constitute the second thin film transistor T2.

[0123] A first interlayer insulating layer 236 is placed over the entire surface of the first gate electrode 230, the second gate electrode 232, and the first capacitor electrode 234, and a second capacitor electrode 238 is placed on the first interlayer insulating layer 236 corresponding to the first capacitor electrode 234.

[0124] For example, the first interlayer insulating layer 236 is made of silicon oxide (SiO2) and silicon nitride (SiN x It may be a single layer or multilayer made of inorganic insulating material such as ).

[0125] For example, the second capacitor electrode 238 may be a single layer or a multilayer made of a metallic material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0126] The first capacitor electrode 234, the first interlayer insulating layer 236, and the second capacitor electrode 238 constitute the storage capacitor Cs.

[0127] A second buffer layer 240 is placed over the entire surface of the second capacitor electrode 238, and a second interlayer insulating layer 242 is placed over the entire surface of the second buffer layer 240.

[0128] For example, the second buffer layer 240 is made of silicon oxide (SiO2) and silicon nitride (SiN x The second interlayer insulating layer 242 may be a single layer or multilayer made of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiN). x It may be a single layer or multilayer made of inorganic insulating material such as ).

[0129] On the second interlayer insulating layer 242 corresponding to the first thin-film transistor T1, a first gate extension electrode 244, a first source electrode 246, and a first drain electrode 248 are arranged. On the second interlayer insulating layer 242 corresponding to the second thin-film transistor T2, a second gate extension electrode 250, a second source electrode 252, and a second drain electrode 254 are arranged. In addition, a capacitor extension electrode 256 is arranged on the second interlayer insulating layer 242 corresponding to the storage capacitor Cs, and a first planarization layer 258 is arranged over the entire surface of the first gate extension electrode 244, the first source electrode 246, the first drain electrode 248, the second gate extension electrode 250, the second source electrode 252, the second drain electrode 254, and the capacitor extension electrode 256.

[0130] The first gate extension electrode 244 is connected to the first gate electrode 230 via the contact holes of the second interlayer insulating layer 242, the second buffer layer 240, and the first interlayer insulating layer 236; the first source electrode 246 is connected to the source region 224b of the first semiconductor layer 224 via the contact holes of the second interlayer insulating layer 242, the second buffer layer 240, the first interlayer insulating layer 236, the first gate insulating layer 228, and the second gate insulating layer 225; and the first drain electrode 248 is connected to the drain region 224c of the first semiconductor layer 224 via the contact holes of the second interlayer insulating layer 242, the second buffer layer 240, the first interlayer insulating layer 236, the first gate insulating layer 228, and the second gate insulating layer 225.

[0131] The second gate extension electrode 250 is connected to the second gate electrode 232 via contact holes in the second interlayer insulating layer 242, the second buffer layer 240, and the first interlayer insulating layer 236; the second source electrode 252 is connected to the source region 226b of the second semiconductor layer 226 via contact holes in the second interlayer insulating layer 242, the second buffer layer 240, the first interlayer insulating layer 236, and the first gate insulating layer 228; and the second drain electrode 254 is connected to the drain region 226c of the second semiconductor layer 226 via contact holes in the second interlayer insulating layer 242, the second buffer layer 240, the first interlayer insulating layer 236, and the first gate insulating layer 228.

[0132] The capacitor extension electrode 256 is connected to the second capacitor electrode 238 via contact holes in the second interlayer insulating layer 242 and the second buffer layer 240.

[0133] The first gate extension electrode 244, the first source electrode 246, the first drain electrode 248, the second gate extension electrode 250, the second source electrode 252, the second drain electrode 254, and the capacitor extension electrode 256 can be formed in the same layer from the same material.

[0134] For example, the first gate extension electrode 244, the first source electrode 246, the first drain electrode 248, the second gate extension electrode 250, the second source electrode 252, the second drain electrode 254, and the capacitor extension electrode 256 may be single-layer or multi-layer structures made of a metallic material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0135] For example, the first planarization layer 258 may be a single layer or a multilayer made of an organic insulating material such as photoacrylic or benzocyclobutene (BCB).

[0136] A first connecting electrode 260 and a second connecting electrode 262 are placed at each subpixel SP1 to SP4 of the display area DA on the first flattening layer 258, and a second flattening layer 264 is placed over the entire surface of the first connecting electrode 260 and the second connecting electrode 262.

[0137] The first connecting electrode 260 is connected to the second drain electrode 254 through a contact hole in the first planarization layer 258.

[0138] Although not shown in the diagram, the second connecting electrode 262 can be connected to the second source electrode 252 and the capacitor extension electrode 256.

[0139] The first connecting electrode 260 and the second connecting electrode 262 can be formed in the same layer from the same material.

[0140] For example, the first connecting electrode 260 and the second connecting electrode 262 may be a single layer or a multilayer made of a metallic material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0141] For example, the second planarization layer 264 may be a single layer or a multilayer made of an organic insulating material such as photoacrylic or benzocyclobutene (BCB).

[0142] A first electrode 266 is placed on each subpixel SP1 to SP4 of the display area DA on the second flattening layer 264, and a bank layer 268 is placed over the entire surface of the first electrode 266.

[0143] The first electrode 266 is connected to the first connecting electrode 260 through a contact hole in the second planarization layer 264.

[0144] For example, the first electrode 266 may be an anode. It may also be a single layer or multilayer made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a translucent or opaque metallic material such as molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), titanium (Ti), or alloys thereof.

[0145] The bank layer 268 has an opening that covers the end of the first electrode 266 while exposing the central part of the first electrode 266.

[0146] For example, the bank layer 268 may be a single layer or a multilayer made of an organic insulating material such as photoacrylic or benzocyclobutene (BCB).

[0147] A trench TR is formed on the bank layer 268 corresponding to the boundary between subpixels SP1 to SP4, and a spacer 270 is placed on the bank layer 268.

[0148] A light-emitting layer 272 is placed over the entire surface of the first electrode 266, and a second electrode 274 is placed over the entire surface of the light-emitting layer 272.

[0149] The light-emitting layer 272 is in contact with the first electrode 266 exposed through the opening of the bank layer 268, the side wall of the opening of the bank layer 268, the top surface of the bank layer 268, and the side wall and top surface of the spacer 270, but can be separated at the boundaries between subpixels SP1 to SP4 by the trench TR.

[0150] The light-emitting layer 272 may include hole-related layers such as hole injection layers and hole transport layers, a light-emitting material layer, and electron-related layers such as electron transport layers and electron injection layers.

[0151] The second electrode 274 is not separated in the trench TR and can be extended while connected on the trench TR.

[0152] For example, the second electrode 274 may be a cathode. It may also be a single layer or multilayer made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a translucent or opaque metallic material such as molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), titanium (Ti), or alloys thereof.

[0153] The first electrode 266, the light-emitting layer 272, and the second electrode 274 constitute a light-emitting diode De.

[0154] A first sealing layer 276, a second sealing layer 278, and a third sealing layer 280 are sequentially arranged on the entire surface of the second electrode 274 to suppress moisture penetration.

[0155] For example, the first sealing layer 276 and the third sealing layer 280 are made of silicon oxide (SiO2) and silicon nitride (SiN xThe second sealing layer 278 may consist of a single layer or multiple layers made of an inorganic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0156] The manufacturing method of the display device 210 will be explained with reference to the drawings.

[0157] Figures 5A to 5F are cross-sectional views illustrating a method for manufacturing a display device according to a second embodiment of the present invention. They will be explained with reference to Figure 4.

[0158] As shown in Figure 5A, the first buffer layer 222 is formed over the entire surface of the substrate 220.

[0159] Subsequently, a polycrystalline semiconductor material layer (not shown) is formed on the first buffer layer 222, and then patterning is performed to form the first semiconductor layer 224 in the first gate drive section GD1 and the second gate drive section GD2 of the non-display area NDA.

[0160] Subsequently, a second gate insulating layer 225 is formed over the entire surface of the first semiconductor layer 224 and the first buffer layer 222.

[0161] As shown in Figure 5B, an oxide semiconductor material layer (not shown) is formed over the entire surface of the second gate insulating layer 225, and then patterning is performed to form the second semiconductor layer 126 on each sub-pixel SP1 to SP4 of the display area DA.

[0162] Subsequently, the first gate insulating layer 228 is formed over the entire surface of the second semiconductor layer 226.

[0163] In this way, by arranging the second gate insulating layer 225 on the first semiconductor layer 224, arranging the second semiconductor layer 226 on the second gate insulating layer 225, and arranging the first gate insulating layer 228 in common on the first semiconductor layer 224 and the second semiconductor layer 226, the second gate insulating layer 225 can be formed to satisfy suitable conditions for the first semiconductor layer 224 of a polycrystalline semiconductor material (for example, changes in the properties of the first semiconductor layer 224 due to etching solution, changes in the properties of the first semiconductor layer 224 and the second gate insulating layer 225 due to deposition temperature, and changes in the properties of the first semiconductor layer 224 due to surface treatment), and the first gate insulating layer 228 can be formed to satisfy suitable conditions for the second semiconductor layer 226 of an oxide semiconductor material. As a result, the reliability of the first semiconductor layer 224 and the second semiconductor layer 226 can be improved.

[0164] As shown in Figure 5C, a first metallic material layer (not shown) is formed on the first gate insulating layer 228, and then patterning is performed to form a first gate electrode 230 corresponding to the first semiconductor layer 224, a second gate electrode 232 corresponding to the second semiconductor layer 226, and a first capacitor electrode 234 for each sub-pixel SP1 to SP4 in the display area DA.

[0165] Subsequently, the first gate electrode 230 and the second gate electrode 232 are used as doping masks to inject N-type or P-type impurities into the first semiconductor layer 224 and the second semiconductor layer 226. This divides the first semiconductor layer 224 into an undoped channel region 224a and impurity-doped source regions 224b and drain regions 224c on either side of the channel region 224a. The second semiconductor layer 226 is divided into an undoped channel region 226a and impurity-doped (or conductor-made) source regions 226b and drain regions 226c on either side of the channel region 226a.

[0166] The first gate electrode 230, the first gate insulating layer 228, the second gate insulating layer 225, and the first semiconductor layer 224 constitute the first thin-film transistor T1, and the second gate electrode 232, the first gate insulating layer 228, and the second semiconductor layer 226 constitute the second thin-film transistor T2.

[0167] Subsequently, a first interlayer insulating layer 236 is formed over the entire surface of the first gate electrode 230, the second gate electrode 232, and the first capacitor electrode 234.

[0168] As shown in Figure 5D, a second metallic material layer (not shown) is formed on the first interlayer insulating layer 236, and then patterning is performed to form the second capacitor electrode 238 corresponding to the first capacitor electrode 234.

[0169] The first capacitor electrode 234, the first interlayer insulating layer 236, and the second capacitor electrode 238 constitute a storage capacitor Cs.

[0170] Subsequently, a second buffer layer 240 is formed over the entire surface of the second capacitor electrode 238, and a second interlayer insulating layer 242 is formed over the entire surface of the second buffer layer 240. After patterning, contact holes exposing the first gate electrode 230 are formed in the second interlayer insulating layer 242, the second buffer layer 240, and the first interlayer insulating layer 236. Contact holes exposing the source region 224b of the first semiconductor layer 224 are formed in the second interlayer insulating layer 242, the second buffer layer 240, the first interlayer insulating layer 236, the first gate insulating layer 228, and the second gate insulating layer 225. Contact holes exposing the drain region 224c of the first semiconductor layer 224 are formed in the second interlayer insulating layer 242, the second buffer layer 240, the first interlayer insulating layer 236, the first gate insulating layer 228, and the second gate insulating layer 225. Furthermore, contact holes exposing the second gate electrode 232 are formed in the second interlayer insulating layer 242, the second buffer layer 240, and the first interlayer insulating layer 236; contact holes exposing the source region 226b of the second semiconductor layer 226 are formed in the second interlayer insulating layer 242, the second buffer layer 240, the first interlayer insulating layer 236, the first gate insulating layer 228, and the second gate insulating layer 225; contact holes exposing the drain region 226c of the second semiconductor layer 226 are formed in the second interlayer insulating layer 242, the second buffer layer 240, the first interlayer insulating layer 236, the first gate insulating layer 228, and the second gate insulating layer 225; and contact holes exposing the second capacitor electrode 238 are formed in the second interlayer insulating layer 242 and the second buffer layer 240.

[0171] Subsequently, a third metallic material layer (not shown) is formed over the entire surface of the second interlayer insulating layer 242, and then patterning is performed to form the first gate extension electrode 244, the first source electrode 246, and the first drain electrode 248 corresponding to the first thin-film transistor T1, the second gate extension electrode 250, the second source electrode 252, and the second drain electrode 254 corresponding to the second thin-film transistor T2, and the capacitor extension electrode 256 corresponding to the storage capacitor Cs.

[0172] As shown in Figure 5E, a first planarization layer 258 is formed over the entire surface of the first gate extension electrode 244, the first source electrode 246, the first drain electrode 248, the second gate extension electrode 250, the second source electrode 252, the second drain electrode 254, and the capacitor extension electrode 256, and then patterning is performed to form a contact hole in the first planarization layer 258 that exposes the second drain electrode 254.

[0173] Subsequently, a fourth metallic material layer (not shown) is formed over the entire surface of the first planarization layer 258, and then patterning is performed to form the first connecting electrode 260 and the second connecting electrode 262 on each sub-pixel SP1 to SP4 of the display area DA.

[0174] As shown in Figure 5F, a second planarization layer 264 is formed over the entire surface of the first connecting electrode 260 and the second connecting electrode 262, and then patterning is performed to form a contact hole in the second planarization layer 264 that exposes the first connecting electrode 260.

[0175] Subsequently, a first electrode material layer (not shown) is formed over the entire surface of the second planarization layer 264, and then patterning is performed to form the first electrode 266 on each sub-pixel SP1 to SP4 of the display area DA.

[0176] Subsequently, a bank layer 268 is formed on the first electrode 266, having an opening that covers the end of the first electrode 266 while exposing the central part of the first electrode 266. A spacer 270 is then formed on the bank layer 268, and a trench TR is formed on the bank layer 268 corresponding to the boundary between subpixels SP1 to SP4.

[0177] Subsequently, a light-emitting layer 272 is formed over the entire surface of the first electrode 266, but the light-emitting layer 272 can be separated at the boundaries between subpixels SP1 to SP4 by trenches TR.

[0178] Subsequently, a second electrode 274 is formed over the entire surface of the light-emitting layer 272. The second electrode 274 is not separated in the trench TR, but can be extended while remaining connected on the trench TR.

[0179] The first electrode 266, the light-emitting layer 272, and the second electrode 274 constitute a light-emitting diode De.

[0180] Subsequently, the first sealing layer 276, the second sealing layer 278, and the third sealing layer 280 are sequentially formed on the entire surface of the second electrode 274 to complete the display device 210.

[0181] As described above, in the display device 210 according to the second embodiment of the present invention, by forming a first thin-film transistor T1 using a polycrystalline semiconductor material as the semiconductor layer (active layer) and a second thin-film transistor T2 using an oxide semiconductor material as the semiconductor layer (active layer) on a single substrate 220, the first thin-film transistor T1 in the first gate drive unit GD1 and the second gate drive unit GD2 can have relatively high mobility, and the second thin-film transistor T2 in each sub-pixel SP1 to SP4 can have a relatively low off-current. As a result, a driving method such as variable refresh rate (VRR) can be adopted, which drives at a relatively low refresh rate for still images and a relatively high refresh rate for moving images, thereby reducing power consumption.

[0182] Furthermore, by forming a first gate insulating layer 228 on both the first semiconductor layer 224 containing a polycrystalline semiconductor material and the second semiconductor layer 226 containing an oxide semiconductor material, and by forming the first gate electrode 230 and the second gate electrode 232 on the same layer from the same material, the manufacturing process is simplified and manufacturing costs are reduced.

[0183] Furthermore, by placing a second gate insulating layer 225 on the first semiconductor layer 224, a second semiconductor layer 226 on the second gate insulating layer 225, and a first gate insulating layer 228 commonly placed on both the first semiconductor layer 224 and the second semiconductor layer 226, the reliability of the first semiconductor layer 224 and the second semiconductor layer 226 is improved.

[0184] In another embodiment, the first and second semiconductor layers can be formed using a single mask, simplifying the manufacturing process. This will be explained with reference to the figure.

[0185] Figure 6 is a cross-sectional view showing the non-display area and the display area in a display device according to the third embodiment of the present invention. Descriptions of parts similar to those in the first and second embodiments are omitted.

[0186] As shown in Figure 6, in the display device 310 according to the third embodiment of the present invention, a first thin-film transistor T1, which is a circuit thin-film transistor, is arranged in the first gate drive unit GD1 and the second gate drive unit GD2 of the non-display area NDA, and a second thin-film transistor T2, which is a pixel thin-film transistor, a storage capacitor Cs, and a light-emitting diode De are arranged in each sub-pixel SP1 to SP4 of the display area DA.

[0187] Specifically, a first buffer layer 322 is placed over the entire surface of the substrate 320, and a first semiconductor layer 324 is placed in the first gate drive unit GD1 and the second gate drive unit GD2 of the non-display area NDA on the first buffer layer 322.

[0188] For example, the first buffer layer 322 is made of silicon oxide (SiO2) and silicon nitride (SiN x It may be a single layer or multilayer made of inorganic insulating material such as ).

[0189] The first semiconductor layer 324 includes an undoped channel region 324a and impurity-doped source regions 324b and drain regions 324c located on either side of the channel region 324a.

[0190] For example, the first semiconductor layer 324 may be made of a polycrystalline semiconductor material such as polycrystalline silicon.

[0191] A second gate insulating layer 325 is placed on each sub-pixel SP1 to SP4 of the display area DA on the first semiconductor layer 324 and the first buffer layer 322, and a second semiconductor layer 326 is placed on the second gate insulating layer 325 of each sub-pixel SP1 to SP4 of the display area DA.

[0192] The first semiconductor layer 324 and the second gate insulating layer 325 above it may have the same shape in a plan view. Furthermore, the second semiconductor layer 326 and the second gate insulating layer 325 below it may have the same shape in a plan view.

[0193] For example, the second gate insulating layer 325 is made of silicon oxide (SiO2), silicon nitride (SiN x It may be a single layer or multilayer made of inorganic insulating material such as ).

[0194] The second semiconductor layer 326 includes an undoped channel region 326a and impurity-doped (or conductor-made) source region 326b and drain region 326c on either side of the channel region 326a.

[0195] For example, the second semiconductor layer 326 can consist of oxide semiconductor materials such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), and indium aluminum zinc oxide (IAZO).

[0196] A first gate insulating layer 328 is placed over the entire surface of the second gate insulating layer 325 on the first semiconductor layer 324 and the entire surface of the second semiconductor layer 326. A first gate electrode 330 and a second gate electrode 332 are placed on the first gate insulating layer 328 corresponding to the first semiconductor layer 324 and the second semiconductor layer 326, respectively. A first capacitor electrode 334 is placed on each of the sub-pixels SP1 to SP4 of the display area DA on the first gate insulating layer 328.

[0197] By arranging a second gate insulating layer 325 on a first semiconductor layer 324, arranging a second semiconductor layer 326 on the second gate insulating layer 325, and arranging a first gate insulating layer 328 in common on both the first and second semiconductor layers 324 and 326, the second gate insulating layer 325 can be formed to satisfy suitable conditions for the first semiconductor layer 324 of a polycrystalline semiconductor material (for example, changes in the properties of the first semiconductor layer 324 due to etching solution, changes in the properties of the first semiconductor layer 324 and the second gate insulating layer 325 due to deposition temperature, and changes in the properties of the first semiconductor layer 324 due to surface treatment), and the first gate insulating layer 328 can be formed to satisfy suitable conditions for the second semiconductor layer 326 of an oxide semiconductor material. As a result, the reliability of the first semiconductor layer 324 and the second semiconductor layer 326 can be improved.

[0198] For example, the thickness of the second gate insulating layer 325 may be thinner than the thickness of the first gate insulating layer 328, and the first gate insulating layer 328 may be silicon oxide (SiO2), silicon nitride (SiN x It may be a single layer or multilayer made of inorganic insulating material such as ).

[0199] The first gate electrode 330, the second gate electrode 332, and the first capacitor electrode 334 can be formed in the same layer from the same material.

[0200] For example, the first gate electrode 330, the second gate electrode 332, and the first capacitor electrode 334 may be a single layer or a multilayer made of a metallic material such as one of the following: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0201] The first gate electrode 330, the second gate insulating layer 325, the first gate insulating layer 328, and the first semiconductor layer 324 constitute the first thin-film transistor T1, and the second gate electrode 332, the first gate insulating layer 328, and the second semiconductor layer 326 constitute the second thin-film transistor T2.

[0202] A first interlayer insulating layer 336 is placed over the entire surface of the first gate electrode 330, the second gate electrode 332, and the first capacitor electrode 334, and a second capacitor electrode 338 is placed on the first interlayer insulating layer 336 corresponding to the first capacitor electrode 334.

[0203] For example, the first interlayer insulating layer 336 is made of silicon oxide (SiO2) and silicon nitride (SiN x It may be a single layer or multilayer made of inorganic insulating material such as ).

[0204] For example, the second capacitor electrode 338 may be a single layer or a multilayer made of a metallic material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0205] The first capacitor electrode 334, the first interlayer insulating layer 336, and the second capacitor electrode 338 constitute a storage capacitor Cs.

[0206] A second buffer layer 340 is placed over the entire surface of the second capacitor electrode 338, and a second interlayer insulating layer 342 is placed over the entire surface of the second buffer layer 340.

[0207] For example, the second buffer layer 340 is made of silicon oxide (SiO2) and silicon nitride (SiN x The second interlayer insulating layer 342 may be a single layer or multilayer made of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiN). x It may be a single layer or multilayer made of inorganic insulating material such as ).

[0208] On the second interlayer insulating layer 342 corresponding to the first thin-film transistor T1, a first gate extension electrode 344, a first source electrode 346, and a first drain electrode 348 are arranged. On the second interlayer insulating layer 342 corresponding to the second thin-film transistor T2, a second gate extension electrode 350, a second source electrode 352, and a second drain electrode 354 are arranged. In addition, a capacitor extension electrode 356 is arranged on the second interlayer insulating layer 342 corresponding to the storage capacitor Cs, and a first planarization layer 358 is arranged over the entire surface of the first gate extension electrode 344, the first source electrode 346, the first drain electrode 348, the second gate extension electrode 350, the second source electrode 352, the second drain electrode 354, and the capacitor extension electrode 356.

[0209] The first gate extension electrode 344 is connected to the first gate electrode 330 via the contact holes of the second interlayer insulating layer 342, the second buffer layer 340, and the first interlayer insulating layer 336; the first source electrode 346 is connected to the source region 324b of the first semiconductor layer 324 via the contact holes of the second interlayer insulating layer 342, the second buffer layer 340, the first interlayer insulating layer 336, the first gate insulating layer 328, and the second gate insulating layer 325; and the first drain electrode 348 is connected to the drain region 324c of the first semiconductor layer 324 via the contact holes of the second interlayer insulating layer 342, the second buffer layer 340, the first interlayer insulating layer 336, the first gate insulating layer 328, and the second gate insulating layer 325.

[0210] The second gate extension electrode 350 is connected to the second gate electrode 332 via the contact holes of the second interlayer insulating layer 342, the second buffer layer 340, and the first interlayer insulating layer 336; the second source electrode 352 is connected to the source region 326b of the second semiconductor layer 326 via the contact holes of the second interlayer insulating layer 342, the second buffer layer 340, the first interlayer insulating layer 336, the first gate insulating layer 328, and the second gate insulating layer 325; and the second drain electrode 354 is connected to the drain region 326c of the second semiconductor layer 326 via the contact holes of the second interlayer insulating layer 342, the second buffer layer 340, the first interlayer insulating layer 336, the first gate insulating layer 328, and the second gate insulating layer 325.

[0211] The capacitor extension electrode 356 is connected to the second capacitor electrode 338 via contact holes in the second interlayer insulating layer 342 and the second buffer layer 340.

[0212] The first gate extension electrode 344, the first source electrode 346, the first drain electrode 348, the second gate extension electrode 350, the second source electrode 352, the second drain electrode 354, and the capacitor extension electrode 356 can be formed in the same layer from the same material.

[0213] For example, the first gate extension electrode 344, the first source electrode 346, the first drain electrode 348, the second gate extension electrode 350, the second source electrode 352, the second drain electrode 354, and the capacitor extension electrode 356 may be single-layer or multi-layer structures made of a metallic material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0214] For example, the first planarization layer 358 may be a single layer or a multilayer made of an organic insulating material such as photoacrylic or benzocyclobutene (BCB).

[0215] A first connecting electrode 360 ​​and a second connecting electrode 362 are placed on each subpixel SP1 to SP4 of the display area DA on the first flattening layer 358, and a second flattening layer 364 is placed over the entire surface of the first connecting electrode 360 ​​and the second connecting electrode 362.

[0216] The first connecting electrode 360 ​​is connected to the second drain electrode 354 through a contact hole in the first planarization layer 358.

[0217] Although not shown in the diagram, the second connecting electrode 362 can be connected to the second source electrode 352 and the capacitor extension electrode 356.

[0218] The first connecting electrode 360 ​​and the second connecting electrode 362 can be formed in the same layer from the same material.

[0219] For example, the first connecting electrode 360 ​​and the second connecting electrode 362 may be a single layer or a multilayer made of a metallic material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0220] For example, the second planarization layer 364 may be a single layer or a multilayer made of an organic insulating material such as photoacrylic or benzocyclobutene (BCB).

[0221] A first electrode 366 is placed on each subpixel SP1 to SP4 of the display area DA on the second flattening layer 364, and a bank layer 368 is placed over the entire surface of the first electrode 366.

[0222] The first electrode 366 is connected to the first connecting electrode 360 ​​through a contact hole in the second planarization layer 364.

[0223] For example, the first electrode 366 may be an anode. It may also be a single layer or multilayer made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a translucent or opaque metallic material such as molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), titanium (Ti), or alloys thereof.

[0224] The bank layer 368 has an opening that covers the end of the first electrode 366 while exposing the central part of the first electrode 366.

[0225] For example, the bank layer 368 may be a single layer or a multilayer made of an organic insulating material such as photoacrylic or benzocyclobutene (BCB).

[0226] A trench TR is formed on the bank layer 368 corresponding to the boundary between sub-pixels SP1 to SP4, and a spacer 370 is placed on the bank layer 368.

[0227] A light-emitting layer 372 is placed over the entire surface of the first electrode 366, and a second electrode 374 is placed over the entire surface of the light-emitting layer 372.

[0228] The light-emitting layer 372 is in contact with the first electrode 366 exposed through the opening of the bank layer 368, the side wall of the opening of the bank layer 368, the top surface of the bank layer 368, and the side wall and top surface of the spacer 370, but can be separated at the boundaries between the subpixels SP1 to SP4 by the trench TR.

[0229] The light-emitting layer 372 may include hole-related layers such as hole injection layers and hole transport layers, a light-emitting material layer, and electron-related layers such as electron transport layers and electron injection layers.

[0230] The second electrode 374 is not separated in the trench TR and can be extended while connected on the trench TR.

[0231] For example, the second electrode 374 may be a cathode. It may also be a single layer or multilayer made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a translucent or opaque metallic material such as molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), titanium (Ti), or alloys thereof.

[0232] The first electrode 366, the light-emitting layer 372, and the second electrode 374 constitute a light-emitting diode De.

[0233] A first sealing layer 376, a second sealing layer 378, and a third sealing layer 380 are sequentially arranged on the entire surface of the second electrode 374 to suppress moisture penetration.

[0234] For example, the first sealing layer 376 and the third sealing layer 380 are made of silicon oxide (SiO2) and silicon nitride (SiN x The second sealing layer 378 consists of an inorganic insulating material such as ), and may consist of an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0235] The manufacturing method of such display device 310 will be explained with reference to the drawings.

[0236] Figures 7A to 7F are cross-sectional views illustrating a method for manufacturing a display device according to a third embodiment of the present invention. They will be explained with reference to Figure 6.

[0237] As shown in Figure 7A, the first buffer layer 322 is formed over the entire surface of the substrate 320.

[0238] Subsequently, an amorphous semiconductor material layer (not shown) is formed on the first buffer layer 322. Then, the amorphous semiconductor material layers of the first gate drive section GD1 and the second gate drive section GD2 of the non-display region NDA are selectively crystallized, and the non-crystallized amorphous semiconductor material layers are selectively removed to form a polycrystalline semiconductor pattern 323 on the first gate drive section GD1 and the second gate drive section GD2 of the non-display region NDA.

[0239] Subsequently, a second gate insulating layer 325 is formed over the entire surface of the polycrystalline semiconductor pattern 323 and the first buffer layer 322, and an oxide semiconductor material layer 327 is formed over the entire surface of the second gate insulating layer 325.

[0240] As shown in Figure 7B, using a semitransparent mask, the oxide semiconductor material layer 327, the second gate insulating layer 325, and the polycrystalline semiconductor pattern 323 of the non-display region NDA are etched, as are the oxide semiconductor material layer 327 and the second gate insulating layer 325 of the display region DA. Then, the oxide semiconductor material layer 327 of the non-display region NDA is exposed by ashing of the photoresist. The exposed oxide semiconductor material layer 327 of the non-display region NDA is removed, and the first semiconductor layer 324 and the second gate insulating layer 325 are formed on the first gate drive unit GD1 and the second gate drive unit GD2 of the non-display region NDA on the first buffer layer 322, and the second gate insulating layer 325 and the second semiconductor layer 326 are formed on each subpixel SP1 to SP4 of the display region DA on the first buffer layer 322.

[0241] By using a single mask to pattern the first semiconductor layer 324, the second gate insulating layer 325, and the second semiconductor layer 326, the manufacturing process can be simplified and manufacturing costs can be reduced.

[0242] Subsequently, the first gate insulating layer 328 is formed over the entire surface of the second gate insulating layer 325 and the second semiconductor layer 326.

[0243] As shown in Figure 7C, a first metallic material layer (not shown) is formed on the first gate insulating layer 328, and then patterning is performed to form a first gate electrode 330 corresponding to the first semiconductor layer 324, a second gate electrode 332 corresponding to the second semiconductor layer 326, and first capacitor electrodes 334 on each sub-pixel SP1 to SP4 of the display area DA.

[0244] Subsequently, the first gate electrode 330 and the second gate electrode 332 are used as doping masks to inject N-type or P-type impurities into the first semiconductor layer 324 and the second semiconductor layer 326. This divides the first semiconductor layer 324 into an undoped channel region 324a and impurity-doped source regions 324b and drain regions 324c on either side of the channel region 324a. The second semiconductor layer 326 is divided into an undoped channel region 326a and impurity-doped (or conductor-made) source regions 326b and drain regions 326c on either side of the channel region 326a.

[0245] The first gate electrode 330, the first gate insulating layer 328, the second gate insulating layer 325, and the first semiconductor layer 324 constitute the first thin-film transistor T1, and the second gate electrode 332, the first gate insulating layer 328, and the second semiconductor layer 326 constitute the second thin-film transistor T2.

[0246] Subsequently, a first interlayer insulating layer 336 is formed over the entire surface of the first gate electrode 330, the second gate electrode 332, and the first capacitor electrode 334.

[0247] As shown in Figure 7D, a second metallic material layer (not shown) is formed on the first interlayer insulating layer 336, and then patterning is performed to form the second capacitor electrode 338 corresponding to the first capacitor electrode 334.

[0248] The first capacitor electrode 334, the first interlayer insulating layer 336, and the second capacitor electrode 338 constitute a storage capacitor Cs.

[0249] Subsequently, a second buffer layer 340 is formed over the entire surface of the second capacitor electrode 338, and a second interlayer insulating layer 342 is formed over the entire surface of the second buffer layer 340. After patterning, contact holes exposing the first gate electrode 330 are formed in the second interlayer insulating layer 342, the second buffer layer 340, and the first interlayer insulating layer 336. Contact holes exposing the source region 324b of the first semiconductor layer 324 are formed in the second interlayer insulating layer 342, the second buffer layer 340, the first interlayer insulating layer 336, the first gate insulating layer 328, and the second gate insulating layer 325. Contact holes exposing the drain region 324c of the first semiconductor layer 324 are formed in the second interlayer insulating layer 342, the second buffer layer 340, the first interlayer insulating layer 336, the first gate insulating layer 328, and the second gate insulating layer 325. Furthermore, contact holes exposing the second gate electrode 332 are formed in the second interlayer insulating layer 342, the second buffer layer 340, and the first interlayer insulating layer 336; contact holes exposing the source region 326b of the second semiconductor layer 326 are formed in the second interlayer insulating layer 342, the second buffer layer 340, the first interlayer insulating layer 336, and the first gate insulating layer 328; contact holes exposing the drain region 326c of the second semiconductor layer 326 are formed in the second interlayer insulating layer 342, the second buffer layer 340, the first interlayer insulating layer 336, and the first gate insulating layer 328; and contact holes exposing the second capacitor electrode 338 are formed in the second interlayer insulating layer 342 and the second buffer layer 340.

[0250] Subsequently, a third metallic material layer (not shown) is formed over the entire surface of the second interlayer insulating layer 342, and then patterning is performed to form the first gate extension electrode 344, the first source electrode 346, and the first drain electrode 348 corresponding to the first thin-film transistor T1, the second gate extension electrode 350, the second source electrode 352, and the second drain electrode 354 corresponding to the second thin-film transistor T2, and the capacitor extension electrode 356 corresponding to the storage capacitor Cs.

[0251] As shown in Figure 7E, a first planarization layer 358 is formed over the entire surface of the first gate extension electrode 344, the first source electrode 346, the first drain electrode 348, the second gate extension electrode 350, the second source electrode 352, the second drain electrode 354, and the capacitor extension electrode 356, and then patterning is performed to form a contact hole in the first planarization layer 358 that exposes the second drain electrode 354.

[0252] Subsequently, a fourth metallic material layer (not shown) is formed over the entire surface of the first planarization layer 358, and then patterning is performed to form the first connecting electrode 360 ​​and the second connecting electrode 362 on each sub-pixel SP1 to SP4 of the display area DA.

[0253] As shown in Figure 7F, a second planarization layer 364 is formed over the entire surface of the first connecting electrode 360 ​​and the second connecting electrode 362, and then patterning is performed to form a contact hole in the second planarization layer 364 that exposes the first connecting electrode 360.

[0254] Subsequently, a first electrode material layer (not shown) is formed over the entire surface of the second planarization layer 364, and then patterning is performed to form the first electrode 366 on each sub-pixel SP1 to SP4 of the display area DA.

[0255] Subsequently, a bank layer 368 is formed on the first electrode 366, having an opening that covers the end of the first electrode 366 while exposing the central part of the first electrode 366. A spacer 370 is then formed on the bank layer 368, but a trench TR is formed on the bank layer 368 corresponding to the boundary between subpixels SP1 to SP4.

[0256] Subsequently, a light-emitting layer 372 is formed over the entire surface of the first electrode 366, but the light-emitting layer 372 can be separated at the boundaries between sub-pixels SP1 to SP4 by trenches TR.

[0257] Subsequently, a second electrode 374 is formed over the entire surface of the light-emitting layer 372. The second electrode 374 is not separated in the trench TR, but can be extended while remaining connected on the trench TR.

[0258] Subsequently, the first sealing layer 376, the second sealing layer 378, and the third sealing layer 380 are sequentially formed on the entire surface of the second electrode 374 to complete the display device 310.

[0259] As described above, in the display device 310 according to the third embodiment of the present invention, by forming a first thin-film transistor T1 using a polycrystalline semiconductor material as the semiconductor layer (active layer) and a second thin-film transistor T2 using an oxide semiconductor material as the semiconductor layer (active layer) on a single substrate 320, the first thin-film transistor T1 in the first gate drive unit GD1 and the second gate drive unit GD2 can have relatively high mobility, and the second thin-film transistor T2 in each sub-pixel SP1 to SP4 can have a relatively low off-current. As a result, a driving method such as variable refresh rate (VRR) can be adopted, which drives at a relatively low refresh rate for still images and a relatively high refresh rate for moving images, thereby reducing power consumption.

[0260] Furthermore, by forming a first gate insulating layer 328 on both the first semiconductor layer 324 containing a polycrystalline semiconductor material and the second semiconductor layer 326 containing an oxide semiconductor material, and by forming the first gate electrode 330 and the second gate electrode 332 on the same layer from the same material, the manufacturing process is simplified and manufacturing costs are reduced.

[0261] Furthermore, by placing a second gate insulating layer 325 on the first semiconductor layer 324, a second semiconductor layer 326 on the second gate insulating layer 325, and a first gate insulating layer 328 commonly placed on both the first semiconductor layer 324 and the second semiconductor layer 326, the reliability of the first semiconductor layer 324 and the second semiconductor layer 326 is improved.

[0262] Furthermore, by patterning the first semiconductor layer 324, the second gate insulating layer 325, and the second semiconductor layer 326 with a single mask, the manufacturing process is further simplified and manufacturing costs are further reduced.

[0263] In another embodiment, the source electrode and the drain electrode can be formed of the same material in the same layer as the gate extension electrode, which simplifies the manufacturing process. This will be described with reference to the drawings.

[0264] FIG. 8 is a cross-sectional view showing a non-display region and a display region in a display device according to a fourth embodiment of the present invention. Descriptions of the same parts as in the first to third embodiments are omitted.

[0265] As shown in FIG. 8, a first thin film transistor T1, which is a circuit thin film transistor, is disposed in the first gate driving unit GD1 and the second gate driving unit GD2 of the non-display region NDA in the display device 410 according to the fourth embodiment of the present invention. In each sub-pixel SP1 to SP4 in the display region DA, a second thin film transistor T2, which is a pixel thin film transistor, a storage capacitor Cs, and a light emitting diode De are disposed.

[0266] Specifically, a first buffer layer 422 is disposed on the entire surface of the substrate 420, and a first semiconductor layer 424 is disposed in the first gate driving unit GD1 and the second gate driving unit GD2 of the non-display region NDA on the first buffer layer 422.

[0267] For example, the first buffer layer 422 may be a single layer or a multi-layer made of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiN x ).

[0268] The first semiconductor layer 424 includes an undoped channel region 424a and impurity-doped source regions 424b and drain regions 424c on both sides of the channel region 424a.

[0269] For example, the first semiconductor layer 424 may be made of a polycrystalline semiconductor material such as polycrystalline silicon.

[0270] A second gate insulating layer 425 is placed on each sub-pixel SP1 to SP4 of the display area DA on the first semiconductor layer 424 and the first buffer layer 422, and a second semiconductor layer 426 is placed on the second gate insulating layer 425 of each sub-pixel SP1 to SP4 of the display area DA.

[0271] The first semiconductor layer 424 and the second gate insulating layer 425 above it may have the same shape in a plan view. Furthermore, the second semiconductor layer 426 and the second gate insulating layer 425 below it may have the same shape in a plan view.

[0272] For example, the second gate insulating layer 425 is made of silicon oxide (SiO2) and silicon nitride (SiN x It may be a single layer or multilayer made of inorganic insulating material such as ).

[0273] The second semiconductor layer 426 includes an undoped channel region 426a and impurity-doped (or conductor-made) source region 426b and drain region 426c located on either side of the channel region 426a.

[0274] For example, the second semiconductor layer 426 can consist of oxide semiconductor materials such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), and indium aluminum zinc oxide (IAZO).

[0275] A first gate insulating layer 428 is placed over the entire surface of the second gate insulating layer 425 on the first semiconductor layer 424 and the entire surface of the second semiconductor layer 426. A first gate electrode 430 and a second gate electrode 432 are placed on the first gate insulating layer 428 corresponding to the first semiconductor layer 424 and the second semiconductor layer 426, respectively. A first capacitor electrode 434 is placed on each of the sub-pixels SP1 to SP4 of the display area DA on the first gate insulating layer 428.

[0276] By arranging a second gate insulating layer 425 on a first semiconductor layer 424, arranging a second semiconductor layer 426 on the second gate insulating layer 425, and arranging a first gate insulating layer 428 in common on both the first and second semiconductor layers 424 and 426, the second gate insulating layer 425 can be formed to satisfy suitable conditions for the first semiconductor layer 424 of a polycrystalline semiconductor material (for example, changes in the properties of the first semiconductor layer 424 due to etching solution, changes in the properties of the first semiconductor layer 424 and the second gate insulating layer 425 due to deposition temperature, and changes in the properties of the first semiconductor layer 424 due to surface treatment), and the first gate insulating layer 428 can be formed to satisfy suitable conditions for the second semiconductor layer 426 of an oxide semiconductor material. As a result, the reliability of the first semiconductor layer 424 and the second semiconductor layer 426 can be improved.

[0277] For example, the thickness of the second gate insulating layer 425 may be thinner than the thickness of the first gate insulating layer 428, and the first gate insulating layer 428 may be silicon oxide (SiO2), silicon nitride (SiN x It may be a single layer or multilayer made of inorganic insulating material such as ).

[0278] The first gate electrode 430, the second gate electrode 432, and the first capacitor electrode 434 can be formed in the same layer from the same material.

[0279] For example, the first gate electrode 430, the second gate electrode 432, and the first capacitor electrode 434 may be a single layer or a multilayer made of a metallic material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0280] The first gate electrode 430, the second gate insulating layer 425, the first gate insulating layer 428, and the first semiconductor layer 424 constitute the first thin-film transistor T1, and the second gate electrode 432, the first gate insulating layer 428, and the second semiconductor layer 426 constitute the second thin-film transistor T2.

[0281] A first interlayer insulating layer 436 is placed over the entire surface of the first gate electrode 430, the second gate electrode 432, and the first capacitor electrode 434. A first gate extension electrode 444, a first source electrode 446, and a first drain electrode 448 are placed on the first interlayer insulating layer 436 corresponding to the first thin-film transistor T1. A second gate extension electrode 450, a second source electrode 452, and a second drain electrode 454 are placed on the first interlayer insulating layer 436 corresponding to the second thin-film transistor T2. A second capacitor electrode 438 is placed on the first interlayer insulating layer 436 corresponding to the first capacitor electrode 434.

[0282] For example, the first interlayer insulating layer 436 is made of silicon oxide (SiO2) and silicon nitride (SiN x It may be a single layer or multilayer made of inorganic insulating material such as ).

[0283] The first gate extension electrode 444 is connected to the first gate electrode 430 via a contact hole in the first interlayer insulating layer 436, the first source electrode 446 is connected to the source region 424b of the first semiconductor layer 424 via contact holes in the first interlayer insulating layer 436, the first gate insulating layer 428, and the second gate insulating layer 425, and the first drain electrode 448 is connected to the drain region 424c of the first semiconductor layer 424 via contact holes in the first interlayer insulating layer 436, the first gate insulating layer 428, and the second gate insulating layer 425.

[0284] The second gate extension electrode 450 is connected to the second gate electrode 432 via a contact hole in the first interlayer insulating layer 436, the second source electrode 452 is connected to the source region 426b of the second semiconductor layer 426 via contact holes in the first interlayer insulating layer 436 and the first gate insulating layer 428, and the second drain electrode 454 is connected to the drain region 426c of the second semiconductor layer 426 via contact holes in the first interlayer insulating layer 436 and the first gate insulating layer 428.

[0285] The first capacitor electrode 434, the first interlayer insulating layer 436, and the second capacitor electrode 438 constitute a storage capacitor Cs.

[0286] For example, the first gate extension electrode 444, the first source electrode 446, the first drain electrode 448, the second gate extension electrode 450, the second source electrode 452, the second drain electrode 454, and the second capacitor electrode 438 may be single-layer or multi-layer structures made of a metallic material such as one of the following: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0287] A second buffer layer 440 is placed over the entire surface of the first gate extension electrode 444, the first source electrode 446, the first drain electrode 448, the second gate extension electrode 450, the second source electrode 452, the second drain electrode 454, and the second capacitor electrode 438, and a first planarization layer 458 is placed over the entire surface of the second buffer layer 440.

[0288] For example, the second buffer layer 440 is made of silicon oxide (SiO2) and silicon nitride (SiN x The first planarization layer 458 may be a single layer or multilayer made of an inorganic insulating material such as .

[0289] A first source extension electrode 463 and a first drain extension electrode 461 are placed on the first planarization layer 458 corresponding to the first thin-film transistor T1, a second source extension electrode 462 and a second drain extension electrode 460 are placed on the first planarization layer 458 corresponding to the second thin-film transistor T2, and a second planarization layer 464 is placed over the entire surface of the first source extension electrode 463, the first drain extension electrode 461, the second source extension electrode 462, and the second drain extension electrode 460.

[0290] The first source extension electrode 463 is connected to the first source electrode 446 through the contact holes of the second buffer layer 440 and the first planarization layer 458. The first drain extension electrode 461 is connected to the first drain electrode 448 through the contact holes of the second buffer layer 440 and the first planarization layer 458. The second source extension electrode 462 is connected to the second source electrode 452 and the second capacitor electrode 438 through the contact holes of the second buffer layer 440 and the first planarization layer 458. The second drain extension electrode 460 is connected to the second drain electrode 454 through the contact holes of the second buffer layer 440 and the first planarization layer 458.

[0291] The first source extension electrode 463, the first drain extension electrode 461, the second source extension electrode 462, and the second drain extension electrode 460 can be formed from the same material in the same layer.

[0292] For example, the first source extension electrode 463, the first drain extension electrode 461, the second source extension electrode 462, and the second drain extension electrode 460 can be a single layer or multiple layers made of a metallic material such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0293] For example, the second planarization layer 464 can be a single layer or multiple layers made of an organic insulating material such as photoacrylic or benzocyclobutene (BCB).

[0294] On each sub-pixel SP1 to SP4 of the display area DA on the second planarization layer 464, the first electrode 466 is disposed, and a bank layer 468 is disposed on the entire surface of the first electrode 466.

[0295] The first electrode 466 is connected to the second drain extension electrode 460 through the contact hole of the second planarization layer 464.

[0296] For example, the first electrode 466 may be an anode. It may also be a single layer or multilayer made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a translucent or opaque metallic material such as molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), titanium (Ti), or alloys thereof.

[0297] The bank layer 468 has an opening that covers the end of the first electrode 466 while exposing the central part of the first electrode 466.

[0298] For example, the bank layer 468 may be a single layer or a multilayer made of an organic insulating material such as photoacrylic or benzocyclobutene (BCB).

[0299] A trench TR is formed on the bank layer 468 corresponding to the boundary between sub-pixels SP1 to SP4, and a spacer 470 is placed on the bank layer 468.

[0300] A light-emitting layer 472 is placed over the entire surface of the first electrode 466, and a second electrode 474 is placed over the entire surface of the light-emitting layer 472.

[0301] The light-emitting layer 472 is in contact with the first electrode 466 exposed through the opening of the bank layer 468, the side wall of the opening of the bank layer 468, the upper surface of the bank layer 468, and the side wall and upper surface of the spacer 70, but can be separated at the boundaries between the subpixels SP1 to SP4 by the trench TR.

[0302] The light-emitting layer 472 may include hole-related layers such as hole injection layers and hole transport layers, a light-emitting material layer, and electron-related layers such as electron transport layers and electron injection layers.

[0303] The second electrode 474 is not separated in the trench TR and can be extended while connected on the trench TR.

[0304] For example, the second electrode 474 may be a cathode. It may also be a single layer or multilayer made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a translucent or opaque metallic material such as molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), titanium (Ti), or alloys thereof.

[0305] The first electrode 466, the light-emitting layer 472, and the second electrode 474 constitute a light-emitting diode De.

[0306] A first sealing layer 476, a second sealing layer 478, and a third sealing layer 480 are sequentially arranged on the entire surface of the second electrode 474 to suppress moisture penetration.

[0307] For example, the first sealing layer 476 and the third sealing layer 480 are made of silicon oxide (SiO2) and silicon nitride (SiN x The second sealing layer 478 consists of an inorganic insulating material such as ), and may consist of an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0308] The manufacturing method of such display device 410 will be explained with reference to the drawings.

[0309] Figures 9A to 9E are cross-sectional views illustrating a method for manufacturing a display device according to a fourth embodiment of the present invention. They will be explained with reference to Figure 8.

[0310] As shown in Figure 9A, the first buffer layer 422 is formed over the entire surface of the substrate 420.

[0311] Subsequently, an amorphous semiconductor material layer (not shown) is formed on the first buffer layer 422. Then, the amorphous semiconductor material layers of the first gate drive section GD1 and the second gate drive section GD2 of the non-display region NDA are selectively crystallized, and the non-crystallized amorphous semiconductor material layers are selectively removed to form a polycrystalline semiconductor pattern 423 on the first gate drive section GD1 and the second gate drive section GD2 of the non-display region NDA.

[0312] Subsequently, a second gate insulating layer 425 is formed over the entire surface of the polycrystalline semiconductor pattern 423 and the first buffer layer 422, and an oxide semiconductor material layer 427 is formed over the entire surface of the second gate insulating layer 425.

[0313] As shown in Figure 9B, using a semitransparent mask, the oxide semiconductor material layer 427, the second gate insulating layer 425, and the polycrystalline semiconductor pattern 423 of the non-display region NDA are etched, as are the oxide semiconductor material layer 427 and the second gate insulating layer 425 of the display region DA. Then, the oxide semiconductor material layer 427 of the non-display region NDA is exposed by ashing of the photoresist. The exposed oxide semiconductor material layer 427 of the non-display region NDA is removed, and the first semiconductor layer 424 and the second gate insulating layer 425 are formed on the first gate drive unit GD1 and the second gate drive unit GD2 of the non-display region NDA on the first buffer layer 422, and the second gate insulating layer 425 and the second semiconductor layer 426 are formed on each subpixel SP1 to SP4 of the display region DA on the first buffer layer 422.

[0314] By using a single mask to pattern the first semiconductor layer 424, the second gate insulating layer 425, and the second semiconductor layer 426, the manufacturing process can be simplified and manufacturing costs can be reduced.

[0315] Subsequently, the first gate insulating layer 428 is formed over the entire surface of the second gate insulating layer 425 and the second semiconductor layer 426.

[0316] As shown in Figure 9C, a first metallic material layer (not shown) is formed on the first gate insulating layer 428, and then patterning is performed to form a first gate electrode 430 corresponding to the first semiconductor layer 424, a second gate electrode 432 corresponding to the second semiconductor layer 426, and first capacitor electrodes 434 on each sub-pixel SP1 to SP4 of the display area DA.

[0317] Subsequently, the first gate electrode 430 and the second gate electrode 432 are used as doping masks to inject N-type or P-type impurities into the first semiconductor layer 424 and the second semiconductor layer 426. This divides the first semiconductor layer 424 into an undoped channel region 424a and impurity-doped source regions 424b and drain regions 424c on either side of the channel region 424a. The second semiconductor layer 426 is divided into an undoped channel region 426a and impurity-doped (or conductor-activated) source regions 426b and drain regions 426c on either side of the channel region 426a.

[0318] The first gate electrode 430, the first gate insulating layer 428, the second gate insulating layer 425, and the first semiconductor layer 424 constitute the first thin-film transistor T1, and the second gate electrode 432, the first gate insulating layer 428, and the second semiconductor layer 426 constitute the second thin-film transistor T2.

[0319] Subsequently, a first interlayer insulating layer 436 is formed over the entire surface of the first gate electrode 430, the second gate electrode 432, and the first capacitor electrode 434.

[0320] As shown in Figure 9D, patterning is performed on the first interlayer insulating layer 436 to form a contact hole on the first interlayer insulating layer 436 that exposes the first gate electrode 430, a contact hole is formed on the first interlayer insulating layer 436, the first gate insulating layer 428, and the second gate insulating layer 425 that exposes the source region 424b of the first semiconductor layer 424, and a contact hole is formed on the first interlayer insulating layer 436, the first gate insulating layer 428, and the second gate insulating layer 425 that exposes the drain region 424c of the first semiconductor layer 424. Furthermore, a contact hole is formed in the first interlayer insulating layer 436 to expose the second gate electrode 432, contact holes are formed in the first interlayer insulating layer 436, the first gate insulating layer 428, and the second gate insulating layer 425 to expose the source region 426b of the second semiconductor layer 426, and contact holes are formed in the first interlayer insulating layer 436, the first gate insulating layer 428, and the second gate insulating layer 425 to expose the drain region 426c of the second semiconductor layer 426.

[0321] Subsequently, a second metallic material layer (not shown) is formed on the first interlayer insulating layer 436, and then patterning is performed to form a first gate extension electrode 444, a first source electrode 446, and a first drain electrode 448 corresponding to the first thin-film transistor T1, a second gate extension electrode 450, a second source electrode 452, and a second drain electrode 454 corresponding to the second thin-film transistor T2, and a second capacitor electrode 438 corresponding to the first capacitor electrode 434.

[0322] The first capacitor electrode 434, the first interlayer insulating layer 436, and the second capacitor electrode 438 constitute a storage capacitor Cs.

[0323] Subsequently, a second buffer layer 440 is formed over the entire surface of the first gate extension electrode 444, the first source electrode 446, the first drain electrode 448, the second gate extension electrode 450, the second source electrode 452, the second drain electrode 454, and the second capacitor electrode 438. A first planarization layer 458 is then formed over the entire surface of the second buffer layer 440, followed by patterning. Contact holes exposing the first source electrode 446 are formed in the first planarization layer 458 and the second buffer layer 440. Contact holes are formed in the first planarization layer 458 and the second buffer layer 440 to expose the rain electrode 448, contact holes are formed in the first planarization layer 458 and the second buffer layer 440 to expose the second source electrode 452, contact holes are formed in the first planarization layer 458 and the second buffer layer 440 to expose the second drain electrode 454, and contact holes are formed in the first planarization layer 458 and the second buffer layer 440 to expose the second capacitor electrode 438.

[0324] Subsequently, a third metallic material layer (not shown) is formed over the entire surface of the first planarization layer 458, and then patterning is performed to form a first source-extended electrode 463 and a first drain-extended electrode 461 corresponding to the first thin-film transistor T1, a second source-extended electrode 462 corresponding to the second thin-film transistor T2 and storage capacitor Cs, and a second drain-extended electrode 460 corresponding to the second thin-film transistor T2.

[0325] As shown in Figure 9E, a second planarization layer 464 is formed over the entire surface of the first source extension electrode 463, the first drain extension electrode 461, the second source extension electrode 462, and the second drain extension electrode 460, and then patterning is performed to form a contact hole in the second planarization layer 464 that exposes the second drain extension electrode 460.

[0326] Subsequently, a first electrode material layer (not shown) is formed over the entire surface of the second planarization layer 464, and then patterning is performed to form the first electrode 466 on each sub-pixel SP1 to SP4 of the display area DA.

[0327] Subsequently, a bank layer 468 is formed on the first electrode 466, having an opening that covers the end of the first electrode 466 while exposing the central part of the first electrode 466. A spacer 470 is then formed on the bank layer 468, but a trench TR is formed on the bank layer 468 corresponding to the boundary between the subpixels SP1 to SP4.

[0328] Subsequently, a light-emitting layer 472 is formed over the entire surface of the first electrode 466, but the light-emitting layer 472 can be separated at the boundaries between sub-pixels SP1 to SP4 by trenches TR.

[0329] Subsequently, a second electrode 474 is formed over the entire surface of the light-emitting layer 472. The second electrode 474 is not separated in the trench TR, but can be extended while remaining connected on the trench TR.

[0330] The first electrode 466, the light-emitting layer 472, and the second electrode 474 constitute a light-emitting diode De.

[0331] Subsequently, the first sealing layer 476, the second sealing layer 478, and the third sealing layer 480 are sequentially formed on the entire surface of the second electrode 474 to complete the display device 410.

[0332] As described above, in the display device 410 according to the fourth embodiment of the present invention, by forming a first thin-film transistor T1 using a polycrystalline semiconductor material as the semiconductor layer (active layer) and a second thin-film transistor T2 using an oxide semiconductor material as the semiconductor layer (active layer) on a single substrate 420, the first thin-film transistor T1 in the first gate drive unit GD1 and the second gate drive unit GD2 can have relatively high mobility, and the second thin-film transistor T2 in each sub-pixel SP1 to SP4 can have a relatively low off-current. As a result, a driving method such as variable refresh rate (VRR) can be adopted, which drives at a relatively low refresh rate for still images and a relatively high refresh rate for moving images, thereby reducing power consumption.

[0333] Furthermore, by forming a first gate insulating layer 428 on a first semiconductor layer 424 containing a polycrystalline semiconductor material and a second semiconductor layer 426 containing an oxide semiconductor material, and by forming the first gate electrode 430 and the second gate electrode 432 on the same layer from the same material, the manufacturing process is simplified and manufacturing costs are reduced.

[0334] Furthermore, by placing a second gate insulating layer 425 on the first semiconductor layer 424, a second semiconductor layer 426 on the second gate insulating layer 425, and a first gate insulating layer 428 commonly placed on both the first semiconductor layer 424 and the second semiconductor layer 426, the reliability of the first semiconductor layer 424 and the second semiconductor layer 426 is improved.

[0335] Furthermore, by patterning the first semiconductor layer 424, the second gate insulating layer 425, and the second semiconductor layer 426 with a single mask, the manufacturing process is further simplified and manufacturing costs are further reduced.

[0336] Furthermore, by forming the first gate-stretched electrode 444, the first source electrode 446, the first drain electrode 448, the second gate-stretched electrode 450, the second source electrode 452, and the second drain electrode 454 in the same layer from the same material, and by forming the first source-stretched electrode 463, the first drain-stretched electrode 461, the second source-stretched electrode 462, and the second drain-stretched electrode 460 in the same layer from the same material, the manufacturing process is further simplified and manufacturing costs are further reduced.

[0337] As described above with reference to preferred embodiments of the present invention, those skilled in the art will understand that the present invention can be modified and altered in various ways without departing from the technical idea and scope of the invention as described in the claims. [Explanation of Symbols]

[0338] 110, 210, 310, 410… Display devices; 120, 220, 320, 420… Substrates; T1… First thin-film transistor; T2… Second thin-film transistor; 124, 224, 324, 424… First semiconductor layer; 126, 226, 326, 426… Second semiconductor layer; De… Light-emitting diode

Claims

1. A substrate including a display area and a non-display area surrounding the display area, A first semiconductor layer comprising a polycrystalline semiconductor material is disposed in the non-display region on the substrate, and a second semiconductor layer comprising an oxide semiconductor material is disposed in the display region on the substrate. A first gate insulating layer disposed on the first semiconductor layer and the second semiconductor layer, wherein the first gate insulating layer on the first semiconductor layer extends to the first gate insulating layer on the second semiconductor layer, A first gate electrode and a second gate electrode are disposed on the first gate insulating layer, corresponding to the first semiconductor layer and the second semiconductor layer, respectively. A first interlayer insulating layer disposed on the first gate electrode and the second gate electrode, A first source electrode and a first drain electrode are disposed on the first interlayer insulating layer and connected to both ends of the first semiconductor layer, respectively, and a second source electrode and a second drain electrode are disposed on the first interlayer insulating layer and connected to both ends of the second semiconductor layer, respectively. The first semiconductor layer includes a second gate insulating layer disposed on the first semiconductor layer, The second semiconductor layer is disposed on the second gate insulating layer, and the device is a display device.

2. The display device according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are in the same layer.

3. A first buffer layer disposed between the substrate and the first semiconductor layer and the second semiconductor layer, A second buffer layer, a second interlayer insulating layer, a first planarization layer, and a second planarization layer are sequentially arranged on the first interlayer insulating layer, A storage capacitor is disposed between the first gate insulating layer and the second buffer layer, A light-emitting diode disposed on the second planarization layer, The display device according to claim 2, further comprising a first sealing layer, a second sealing layer, and a third sealing layer sequentially arranged on the light-emitting diode.

4. A first gate extension electrode and a second gate extension electrode connected to the first gate electrode and the second gate electrode, respectively, The system further includes a capacitor extension electrode connected to the storage capacitor, The display device according to claim 3, wherein the first gate stretch electrode, the first source electrode, the first drain electrode, the second gate stretch electrode, the second source electrode, the second drain electrode, and the capacitor stretch electrode are arranged on a flat surface of the second interlayer insulating layer, have substantially the same thickness, and are formed of the same material.

5. The display device according to claim 3, wherein the first gate electrode, the second gate electrode, and the first capacitor electrode of the storage capacitor are arranged on the same layer and formed of the same material.

6. The display device according to claim 5, wherein the first interlayer insulating layer is arranged over the entire surface of the substrate and is placed on the first gate electrode, the second gate electrode, and the first capacitor electrode, and the second capacitor electrode of the storage capacitor is placed on the first interlayer insulating layer corresponding to the first capacitor electrode.

7. The display device according to claim 6, wherein the second buffer layer is arranged over the entire surface of the substrate and is positioned on the second capacitor electrode.

8. The display device according to claim 1, wherein the second gate insulating layer is disposed between the first semiconductor layer and the first gate insulating layer, and between the substrate and the second semiconductor layer, and the second gate insulating layer between the first semiconductor layer and the first gate insulating layer extends to the second gate insulating layer between the substrate and the second semiconductor layer.

9. The display device according to claim 1, wherein the second gate insulating layer is arranged over the entire surface of the substrate.

10. A substrate including a display area and a non-display area surrounding the display area, A first semiconductor layer comprising a polycrystalline semiconductor material is disposed in the non-display region on the substrate, and a second semiconductor layer comprising an oxide semiconductor material is disposed in the display region on the substrate. A first gate insulating layer disposed on the first semiconductor layer and the second semiconductor layer, A second gate insulating layer disposed on the first semiconductor layer and below the second semiconductor layer, A first gate electrode and a second gate electrode are disposed on the first gate insulating layer, corresponding to the first semiconductor layer and the second semiconductor layer, respectively. A first interlayer insulating layer disposed on the first gate electrode and the second gate electrode, The first interlayer insulating layer includes a first source electrode and a first drain electrode, which are disposed on the first interlayer insulating layer and connected to both ends of the first semiconductor layer, respectively, and a second source electrode and a second drain electrode, which are disposed on the first interlayer insulating layer and connected to both ends of the second semiconductor layer, respectively. The first semiconductor layer and the second gate insulating layer on the first semiconductor layer have the same shape. A display device in which the second semiconductor layer and the second gate insulating layer beneath the second semiconductor layer have the same shape.

11. A substrate including a display area and a non-display area surrounding the display area, A first semiconductor layer comprising a polycrystalline semiconductor material is disposed in the non-display region on the substrate, and a second semiconductor layer comprising an oxide semiconductor material is disposed in the display region on the substrate. A first gate insulating layer disposed on the first semiconductor layer and the second semiconductor layer, A second gate insulating layer disposed on the first semiconductor layer and below the second semiconductor layer, A first gate electrode and a second gate electrode are disposed on the first gate insulating layer, corresponding to the first semiconductor layer and the second semiconductor layer, respectively. A first interlayer insulating layer disposed on the first gate electrode and the second gate electrode, A first source electrode and a first drain electrode are disposed on the first interlayer insulating layer and connected to both ends of the first semiconductor layer, respectively, and a second source electrode and a second drain electrode are disposed on the first interlayer insulating layer and connected to both ends of the second semiconductor layer, respectively. A first planarization layer and a second planarization layer are sequentially arranged on the first interlayer insulating layer, The system includes the first source electrode, the first drain electrode, the second source electrode, and a first source extension electrode, a first drain extension electrode, a second source extension electrode, and a second drain extension electrode connected to the second drain electrode, respectively. A display device comprising a first source stretching electrode, a first drain stretching electrode, a second source stretching electrode, and a second drain stretching electrode, arranged on a first planarization layer, having substantially the same thickness and being formed of the same material.

12. The device further includes a first gate extension electrode disposed on the first interlayer insulating layer and connected to the first gate electrode, and a second gate extension electrode disposed on the first interlayer insulating layer and connected to the second gate electrode, The display device according to claim 11, wherein the first gate stretching electrode, the first source electrode, the first drain electrode, the second gate stretching electrode, the second source electrode, and the second drain electrode are arranged on the first interlayer insulating layer, have substantially the same thickness, and are formed of the same material.

13. A first buffer layer is disposed between the substrate and the first semiconductor layer and between the substrate and the second semiconductor layer, A second buffer layer, a first planarization layer, and a second planarization layer are sequentially arranged on the first interlayer insulating layer, A storage capacitor is disposed between the first gate insulating layer and the second buffer layer, A light-emitting diode disposed on the second planarization layer, The display device according to claim 12, further comprising a first sealing layer, a second sealing layer, and a third sealing layer sequentially arranged on the light-emitting diode.

14. The display device according to claim 13, wherein the second source electrode is connected to the storage capacitor.

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