Electronic apparatus

Abstract

Provided is a novel electronic apparatus. This electronic apparatus includes: a display device; an arithmetic unit; and a line-of-sight detection unit. The display device includes: a functional circuit; and a display unit which is divided into a plurality of sub-display sections. The line-of-sight detection unit has a function for detecting the line-of-sight of a user. The arithmetic unit has a function for sorting each of the plurality of sub-display sections into a first area or a second area, by using the detection results from the line-of-sight detection unit. The first area has a region that overlaps with a gaze point. The functional circuit has a function for setting a drive frequency in the second area to be lower than a drive frequency in the first area.

Description

electronic equipment

[0001] 1. Field of the Invention One aspect of the present invention relates to an electronic device. 1. Field of the Invention One aspect of the present invention relates to a wearable electronic device including a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof.

[0003] In recent years, head-mounted display (HMD) type electronic devices suitable for applications such as virtual reality (VR), augmented reality (AR), etc. HMDs are capable of displaying images in a 360-degree area around a user in response to the user's head movements, line of sight, or operations, allowing the user to experience a highly immersive and realistic experience.

[0004] An HMD is configured to enlarge an image displayed on a display device using optical components or the like, and the user views the enlarged image. In this case, there is a risk that the inclusion of optical components will increase the size of the housing, or that the user will be more likely to see the pixels and perceive them as grainy, so high-definition and compact display devices are required. For example, Patent Document 1 discloses an HMD with fine pixels achieved by using transistors capable of high-speed operation.

[0005] Japanese Patent Application Laid-Open No. 2000-2856

[0006] HMD-type electronic devices require high rendering capabilities that respond to the user's head movements, line of sight, and operations. Driving a high-resolution, compact display device with a computation circuit with high rendering capabilities can result in increased power consumption. Furthermore, a computation circuit with high rendering capabilities requires a heat dissipation mechanism to cool the computation circuit, which can lead to an increase in the size of the electronic device.

[0007] Alternatively, in a configuration in which a functional circuit such as an application processor for driving a display device is provided in an area overlapping with the display unit, there is a risk that the drawing processing capability will be insufficient in the case of a display device that is designed to have high definition and be compact.

[0008] An object of one embodiment of the present invention is to provide an electronic device with reduced power consumption.An object of one embodiment of the present invention is to provide an electronic device with reduced size and weight.An object of one embodiment of the present invention is to provide an electronic device with excellent drawing processing capability.An object of one embodiment of the present invention is to provide a novel electronic device.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0010] One aspect of the present invention is an electronic device having a display device, a calculation unit, and a gaze detection unit, wherein the display device has a functional circuit and a display unit divided into multiple sub-display units, the gaze detection unit has the function of detecting a user's gaze, the calculation unit has the function of using the detection result of the gaze detection unit to allocate each of the multiple sub-display units to a first area or a second area, and the functional circuit has the function of setting a second drive frequency, which is the drive frequency of the sub-display units included in the second area, lower than a first drive frequency, which is the drive frequency of the sub-display units included in the first area.

[0011] The first area includes an area overlapping with the user's gaze point. The second area is set outside the first area. The second driving frequency is preferably equal to or less than half, more preferably equal to or less than one-fifth of the first driving frequency.

[0012] The sub-display unit may have a plurality of pixel circuits and a plurality of light-emitting elements. The display device may have a plurality of gate driver circuits and a plurality of source driver circuits. For example, one of the plurality of gate driver circuits and one of the plurality of source driver circuits is electrically connected to one of the plurality of sub-display units. The display device may also have a first layer, a second layer on the first layer, and a third layer on the second layer. For example, a plurality of gate driver circuits and a plurality of source driver circuits may be provided on the first layer, a plurality of pixel circuits on the second layer, and a plurality of light-emitting elements on the third layer.

[0013] The pixel circuit may include a first transistor, a second transistor having a source or a drain electrically connected to a gate of the first transistor, and a capacitor electrically connected to the gate of the first transistor, and the channel formation region of the second transistor may include an oxide semiconductor. The light-emitting element may be, for example, an organic EL element.

[0014] The display device may also include a storage device that has the function of storing image data for each of the plurality of sub-display sections.

[0015] According to one embodiment of the present invention, an electronic device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, an electronic device with reduced size and weight can be provided. Alternatively, according to one embodiment of the present invention, an electronic device with excellent drawing processing capability can be provided. Alternatively, according to one embodiment of the present invention, a novel electronic device can be provided.

[0016] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0017] FIGS. 1A and 1B are diagrams illustrating an example of the configuration of an electronic device. FIGS. 2A and 2B are diagrams illustrating an example of the configuration of an electronic device. FIGS. 3A and 3B are diagrams illustrating an example of the configuration of a display device. FIG. 4 is a diagram illustrating an example of the configuration of a display device. FIGS. 5A to 5C are perspective views of a display module. FIG. 6 is a diagram illustrating an example of the operation of an electronic device. FIGS. 7A and 7B are schematic diagrams illustrating an example of the configuration of an electronic device. FIGS. 8A and 8B are schematic diagrams illustrating an example of the configuration of an electronic device. FIGS. 9A and 9B are schematic diagrams illustrating an example of the configuration of an electronic device. FIGS. 10A and 10B are diagrams illustrating an example of the configuration of a display device. FIGS. 11A to 11D are diagrams illustrating an example of the configuration of a display device. FIGS. 12A to 12D are diagrams illustrating an example of the configuration of a display device. FIG. 13 is a timing chart illustrating a method of driving a display device. FIGS. 14A and 14B are diagrams illustrating an example of the configuration of a display device. FIGS. 15A and 15B are diagrams illustrating an example of the operation of a display device. FIGS. 16A and 16B are diagrams illustrating an example of the configuration of a display device. FIGS. 17A to 17D are diagrams illustrating an example of the configuration of a display device. FIGS. 18A to 18C are diagrams illustrating an example of the configuration of a display device. FIG. 19 is a block diagram illustrating an example of the configuration of a display device. FIG. 20 is a block diagram illustrating an example of the configuration of a display device. FIGS. 21A and 21B are diagrams illustrating an example of the configuration of a display device. FIG. 22 is a diagram illustrating an example of the configuration of a display device. FIG. 23 is a diagram illustrating an example of the configuration of a display device. FIG. 24A is a diagram illustrating a sub-display unit. FIGS. 24B1 to 24B7 are diagrams illustrating an example of the configuration of a pixel. FIGS. 25A to 25G are diagrams illustrating an example of the configuration of a pixel. FIG. 26 is a diagram illustrating a display unit. FIGS. 27A and 27B are diagrams illustrating an example of the configuration of a display device. FIGS. 28A to 28D are diagrams illustrating an example of the configuration of a light-emitting element. FIGS. 29A to 29D are diagrams illustrating an example of the configuration of a light-emitting element. FIGS. 30A to 30D are diagrams illustrating an example of the configuration of a light-emitting element. 31A to 31C are diagrams illustrating configuration examples of a light-emitting element, Fig. 32 is a diagram illustrating configuration examples of a display device, and Fig. 33 is a diagram illustrating configuration examples of a display device.34A and 34B are diagrams illustrating an example of the configuration of a display device. FIGS. 35A and 35B are diagrams illustrating an example of the configuration of a display device. FIGS. 36A and 36B are diagrams illustrating an example of the configuration of a display device. FIG. 37 is a diagram illustrating an example of the configuration of a display device. FIG. 38 is a diagram illustrating an example of the configuration of a display device. FIG. 39 is a diagram illustrating an example of the configuration of a display device. FIG. 40 is a diagram illustrating an example of the configuration of a display device. FIGS. 41A to 41C are diagrams illustrating an example of the configuration of a transistor. FIG. 42A is a diagram illustrating classification of crystal structures. FIG. 42B is a diagram illustrating an XRD spectrum of a CAAC-IGZO film. FIG. 42C is a diagram illustrating a microelectron beam diffraction pattern of a CAAC-IGZO film. FIGS. 43A to 43D are diagrams illustrating an example. FIG. 44 is a diagram illustrating an example.

[0018] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different forms and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0019] In this specification and the like, unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state) when a voltage V between the gate and the source of an n-channel transistor is applied. ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0020] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used in an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, the term "OS transistor" in this specification and the like can be rephrased as a transistor including an oxide or an oxide semiconductor.

[0021] Embodiment 1 In this embodiment, an electronic device according to one embodiment of the present invention will be described. The electronic device according to one embodiment of the present invention can be suitably used as a wearable electronic device for VR or AR applications.

[0022] 1A shows a perspective view of an eyeglass-type (goggle-type) electronic device 100 as an example of a wearable electronic device. The electronic device 100 shown in FIG. 1A includes a pair of display devices 10 (display device 10_L and display device 10_R), a motion detection unit 101, a gaze detection unit 102, a calculation unit 103, and a communication unit 104 in a housing 105.

[0023] 1B is a block diagram of the electronic device 100 of FIG. 1A. Similar to FIG. 1A, the electronic device 100 includes a display device 10_L, a display device 10_R, a motion detection unit 101, a gaze detection unit 102, a calculation unit 103, and a communication unit 104, which transmit and receive various signals to and from each other via a bus wiring BW. The display device 10_L and the display device 10_R each include multiple pixels 230, a drive circuit 30, and a function circuit 40. Each pixel 230 includes one light-emitting element 61 and one pixel circuit 51. Thus, the display device 10_L and the display device 10_R each include multiple light-emitting elements 61 and multiple pixel circuits 51.

[0024] The motion detection unit 101 has a function of detecting the movement of the housing 105, i.e., the movement of the head of the user wearing the electronic device 100. The motion detection unit 101 may use, for example, a motion sensor using MEMS technology. The motion sensor may be a three-axis motion sensor or a six-axis motion sensor. Information regarding the movement of the housing 105 detected by the motion detection unit 101 may be referred to as first information, first data, motion data, or the like.

[0025] The gaze detection unit 102 has a function of acquiring information about the user's gaze. Specifically, it has a function of detecting the user's gaze. The user's gaze may be acquired by an eye tracking method such as the Pupil Center Corneal Reflection method or the Bright / Dark Pupil Effect method. Alternatively, the gaze may be acquired by an eye tracking method using a laser or ultrasound. The user's gaze may be detected for one eye or both eyes. For example, by detecting the gaze for both eyes, the distance from the user to the gaze point can be predicted.

[0026] The calculation unit 103 has a function of calculating the user's gaze point using the gaze detection result of the gaze detection unit 102. For example, the calculation unit 103 can know the gaze point on the display device 10. That is, it can know which object the user is gazing at in the images displayed on the display device 10_L and the display device 10_R. It can also know whether the user is gazing at a location other than the screen. Note that information about the user's gaze obtained by the gaze detection unit 102 (gaze detection result) may be referred to as second information, gaze information, or the like.

[0027] The calculation unit 103 has a function of performing drawing processing in accordance with the movement of the housing 105. The drawing processing in accordance with the movement of the housing 105 in the calculation unit 103 is performed using the first information and image data input from the outside via the communication unit 104. As the image data, for example, 360-degree omnidirectional image data can be used. The 360-degree omnidirectional image data is data generated by an omnidirectional camera (omnidirectional camera, 360° camera) or computer graphics, etc. Specifically, the calculation unit 103 has a function of converting the 360-degree omnidirectional image data in accordance with the first information into image data that can be displayed on the display devices 10_L and 10_R.

[0028] The calculation unit 103 also has a function of using the second information to determine the sizes and shapes of multiple areas to be set on the display unit of each of the display devices 10_L and 10_R. Specifically, the calculation unit 103 calculates a gaze point on the display unit in accordance with the second information, and sets a first area S1 to a third area S3, etc., which will be described later, on the display unit based on the gaze point.

[0029] Microprocessors such as a central processing unit (CPU), a digital signal processor (DSP), or a graphics processing unit (GPU), either singly or in combination, can be used as the calculation unit 103. These microprocessors may also be implemented as programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs) or field programmable analog arrays (FPAAs).

[0030] The arithmetic unit 103 performs various data processing and program control by interpreting and executing instructions from various programs using a processor. The programs that can be executed by the processor may be stored in a memory area of ​​the processor or in a separately provided storage unit. The storage unit may be, for example, a storage device that uses non-volatile storage elements such as flash memory, MRAM (Magnetoresistive Random Access Memory), PRAM (Phase change RAM), ReRAM (Resistive RAM), or FeRAM (Ferroelectric RAM), or a storage device that uses volatile storage elements such as DRAM (Dynamic RAM) and SRAM (Static RAM).

[0031] The communication unit 104 has a function of communicating with external devices wirelessly or via a wired connection to acquire various data such as image data. The communication unit 104 may be provided with, for example, a high-frequency circuit (RF circuit) for transmitting and receiving RF signals. The high-frequency circuit is a circuit that converts between electromagnetic signals and electric signals in a frequency band defined by the laws of each country, and uses the electromagnetic signals to communicate wirelessly with other communication devices. When wireless communication is performed, communication standards such as LTE (Long Term Evolution), GSM (Global System for Mobile Communication: registered trademark), EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000 (Code Division Multiple Access 2000), and WCDMA (Wideband Code Division Multiple Access: registered trademark), or specifications standardized by IEEE such as Wi-Fi (registered trademark), Bluetooth (registered trademark), and ZigBee (registered trademark), can be used as communication protocols or communication technologies. It is also possible to use the third generation mobile communication system (3G), fourth generation mobile communication system (4G), or fifth generation mobile communication system (5G) defined by the International Telecommunications Union (ITU).

[0032] The communication unit 104 may also have external ports such as a terminal for connecting to a LAN (Local Area Network), a terminal for receiving digital broadcasts, and a terminal for connecting an AC adapter.

[0033] The display device 10_L and the display device 10_R each have a plurality of light-emitting elements 61, a plurality of pixel circuits 51, a drive circuit 30, and a function circuit 40. The pixel circuit 51 has a function of controlling the light emission of the light-emitting elements 61. The drive circuit 30 has a function of controlling the pixel circuit 51.

[0034] The information on the multiple regions on the display unit of the display device 10 determined by the calculation unit 103 is used for driving the display unit to have different resolutions for each region. The function circuit 40 has a function of controlling the drive circuit 30 to perform high-resolution display in regions close to the gaze point, and to control the drive circuit 30 to perform low-resolution display in regions farther from the gaze point.

[0035] For example, a display with a low resolution can be achieved by rewriting image data every other pixel or every several pixels. Reducing the number of pixels for which image data is rewritten can reduce the power consumption of the display device.

[0036] As in one embodiment of the present invention, a calculation unit 103 may be provided separately from the functional circuit 40. By providing the calculation unit 103, it is possible to offload high-load calculation processes, such as drawing processing in response to the movement of the housing 105 and determining multiple regions (first region S1 to third region S3) according to the gaze point, to the calculation unit 103. On the other hand, by offloading processing for controlling the drive circuit 30 to the functional circuit 40, it is possible to reduce the circuit size and power consumption. In particular, wearable electronic devices require high-speed calculation processing because they must detect the user's head movement, line of sight movement, and the like within a short period of time, resulting in high power consumption for calculation. On the other hand, in one embodiment of the present invention, the function of outputting a control signal for the drive circuit 30 can be separated from the calculation unit 103 and performed by the functional circuit 40. Therefore, the load is not concentrated on a single calculation unit, and the load on the calculation unit can be reduced. Consequently, overall power consumption can be reduced.

[0037] The electronic device 100 may also be provided with a sensor 125. The sensor 125 may have a function of acquiring information from one or more of the user's visual, auditory, tactile, gustatory, and olfactory senses. More specifically, the sensor 125 may have a function of detecting or measuring information from one or more of force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, magnetism, temperature, sound, time, electric field, current, voltage, power, radiation, humidity, gradient, vibration, odor, and infrared light. The electronic device 100 may include one or more sensors 125.

[0038] The sensor 125 may be used to measure ambient temperature, humidity, illuminance, odor, and the like. The sensor 125 may also be used to acquire information for personal authentication using, for example, a fingerprint, palm print, iris, retina, pulse shape (including vein shape and artery shape), or face. The sensor 125 may also be used to measure the user's blink frequency, eyelid movement, pupil size, body temperature, pulse rate, or blood oxygen saturation, and detect the user's fatigue level and health condition. The electronic device 100 may detect the user's fatigue level and health condition, and display a warning or the like on the display device 10.

[0039] Furthermore, the operation of electronic device 100 may be controlled by detecting the movement of the user's line of sight and eyelids. The detection of the user's line of sight and eyelid movements may be performed for one or both of the user's eyes. For example, the operation of electronic device 100 may be controlled by combining the movements of the left and right eyelids. Because the user does not need to use both hands to operate electronic device 100, input operations can be performed with the user holding nothing in both hands (with both hands free).

[0040] 2A is a perspective view showing electronic device 100. In Fig. 2A, housing 105 of electronic device 100 includes, in addition to a pair of display devices 10_L and 10_R and a calculation unit 103, a mounting unit 106, a buffer member 107, a pair of lenses 108, and the like, as one example. The pair of display devices 10_L and 10_R are each provided in a position inside housing 105 that can be viewed through lens 108.

[0041] 2A is provided with an input terminal 109 and an output terminal 110. A cable can be connected to the input terminal 109 to supply an image signal (image data) from a video output device or the like, or power for charging a battery provided within the housing 105. The output terminal 110 functions as, for example, an audio output terminal, and can be connected to earphones, headphones, or the like.

[0042] Furthermore, the housing 105 preferably has a mechanism for adjusting the left-right positions of the lens 108 and the display devices 10_L and 10_R so that they are optimally positioned according to the position of the user's eyes. Also, the housing 105 preferably has a mechanism for adjusting the focus by changing the distance between the lens 108 and the display devices 10_L and 10_R.

[0043] The cushioning member 107 is a portion that comes into contact with the user's face (forehead, cheeks, etc.). The cushioning member 107 makes close contact with the user's face, preventing light leakage and enhancing the sense of immersion. It is preferable to use a soft material for the cushioning member 107 so that it can come into close contact with the user's face when the user wears the electronic device 100. Using such a material is preferable because it feels pleasant to the touch and prevents the user from feeling cold when worn in cold seasons. It is preferable to make the components that come into contact with the user's skin, such as the cushioning member 107 or the attachment portion 106, removable, for easier cleaning or replacement.

[0044] The electronic device according to one embodiment of the present invention may further include an earphone 106A. The earphone 106A includes a communication unit (not shown) and has a wireless communication function. The earphone 106A can output audio data using the wireless communication function. The earphone 106A may also have a vibration mechanism to function as a bone conduction earphone.

[0045] 2B, the earphone 106A can be directly connected to the attachment unit 106 or connected by wire. The earphone 106B and the attachment unit 106 may have a magnet. This allows the earphone 106B to be fixed to the attachment unit 106 by magnetic force, which is preferable as it makes storage easier.

[0046] <Configuration Example of Display Device> The configuration of a display device 10A that can be applied to the display devices 10_L and 10_R shown in FIGS. 1A and 1B will be described with reference to FIGS. 3A, 3B, and 4. FIG.

[0047] FIG. 3A is a perspective view of a display device 10A that can be used with the display devices 10_L and 10_R shown in FIGS. 1A and 1B.

[0048] The display device 10A has a substrate 11 and a substrate 12. The display device 10A has a display unit 13 composed of elements provided between the substrate 11 and the substrate 12. The display unit 13 is an area in the display device 10A that displays an image. The display unit 13 has a plurality of pixels 230. Each pixel 230 has a pixel circuit 51 and a light-emitting element 61.

[0049] Furthermore, when the pixels 230 are arranged in a matrix of 1920 x 1080 pixels, a display unit 13 capable of displaying at a resolution of so-called full high-definition (also referred to as "2K resolution," "2K1K," or "2K") can be realized. Furthermore, when the pixels 230 are arranged in a matrix of 3840 x 2160 pixels, for example, a display unit 13 capable of displaying at a resolution of so-called ultra high-definition (also referred to as "4K resolution," "4K2K," or "4K") can be realized. Furthermore, when the pixels 230 are arranged in a matrix of 7680 x 4320 pixels, for example, a display unit 13 capable of displaying at a resolution of so-called super high-definition (also referred to as "8K resolution," "8K4K," or "8K") can be realized. By increasing the number of pixels 230, a display unit 13 capable of displaying at a resolution of 16K or even 32K can also be realized.

[0050] The pixel density (resolution) of the display unit 13 is preferably 1000 ppi or more and 10000 ppi or less, but may be, for example, 2000 ppi or more and 6000 ppi or less, or 3000 ppi or more and 5000 ppi or less.

[0051] There are no particular limitations on the screen ratio (aspect ratio) of the display unit 13. The display unit 13 can support various screen ratios, such as 1:1 (square), 4:3, 16:9, and 16:10.

[0052] In this specification and the like, the term “element” may be replaced with “device.” For example, a display element, a light-emitting element, and a liquid crystal element may be replaced with a display device, a light-emitting device, and a liquid crystal device.

[0053] The display device 10A receives various signals and power supply potentials from the outside via the terminal unit 14, and can display images using display elements provided in the display unit 13. Various elements can be used as the display elements. Representative examples include light-emitting elements that have a function of emitting light, such as organic EL elements and LED elements, liquid crystal elements, and MEMS (Micro Electro Mechanical Systems) elements.

[0054] A plurality of layers are provided between the substrate 11 and the substrate 12, and each layer is provided with a transistor for performing circuit operation or a display element for emitting light. The plurality of layers are provided with pixel circuits having a function of controlling the operation of the display elements, drive circuits having a function of controlling the pixel circuits, function circuits having a function of controlling the drive circuits, and the like.

[0055] FIG. 3B is a perspective view showing a schematic configuration of each layer provided between the substrate 11 and the substrate 12. As shown in FIG.

[0056] A layer 20 is provided on the substrate 11. The layer 20 includes a driver circuit 30, a functional circuit 40, and an input / output circuit 80. The layer 20 includes a transistor 21 (also referred to as a Si transistor) having silicon in a channel formation region 22. The substrate 11 is, for example, a silicon substrate. A silicon substrate is preferable because it has higher thermal conductivity than a glass substrate. By providing the driver circuit 30, the functional circuit 40, and the input / output circuit 80 on the same layer, the wiring electrically connecting the driver circuit 30, the functional circuit 40, and the input / output circuit 80 can be shortened. This shortens the charging and discharging time of the control signal used by the functional circuit 40 to control the driver circuit 30, thereby reducing power consumption. Furthermore, the charging and discharging time required for the input / output circuit 80 to supply signals to the functional circuit 40 and the driver circuit 30 is shortened, thereby reducing power consumption.

[0057] The transistor 21 can be, for example, a transistor having single crystal silicon in a channel formation region (also referred to as a "c-Si transistor"). In particular, when a transistor having single crystal silicon in a channel formation region is used as the transistor provided in the layer 20, the on-state current of the transistor can be increased. Therefore, it is preferable because the circuit included in the layer 20 can be driven at high speed. Furthermore, since a Si transistor can be formed by microfabrication so that the channel length is 3 nm to 10 nm, the display device 10A can be provided with an accelerator such as a CPU or a GPU, an application processor, or the like, integrated with the display unit.

[0058] Alternatively, a transistor having polycrystalline silicon in a channel formation region (also referred to as a "poly-Si transistor") may be provided in the layer 20. Low temperature polysilicon (LTPS) may be used as the polycrystalline silicon. Note that a transistor having LTPS in a channel formation region is also referred to as an "LTPS transistor." Alternatively, an OS transistor may be provided in the layer 20.

[0059] The driving circuit 30 can be various circuits such as a shift register, a level shifter, an inverter, a latch, an analog switch, and a logic circuit. The driving circuit 30 includes, for example, a gate driver circuit, a source driver circuit, and the like. The driving circuit 30 may also include an arithmetic circuit, a memory circuit, a power supply circuit, and the like. Because the gate driver circuit, the source driver circuit, and other circuits can be arranged overlapping the display unit 13, the width of the non-display area (also called a frame) around the periphery of the display unit 13 of the display device 10A can be made significantly narrower than when these circuits and the display unit 13 are arranged side by side, thereby enabling the display device 10A to be made more compact.

[0060] The functional circuit 40 has, for example, the function of an application processor for controlling each circuit in the display device 10A and generating signals for controlling each circuit. The functional circuit 40 may also have a circuit for correcting image data, such as a GPU, and a CPU. The functional circuit 40 may also have an LVDS (Low Voltage Differential Signaling) circuit, a MIPI (Mobile Industry Processor Interface) circuit, a D / A (Digital to Analog) conversion circuit, and the like, which function as an interface for receiving image data and the like from outside the display device 10A. The functional circuit 40 may also have a circuit for compressing and decompressing image data, a power supply circuit, and the like.

[0061] A layer 50 is provided over the layer 20. The layer 50 includes a pixel circuit group 55 including a plurality of pixel circuits 51. An OS transistor may be provided in the layer 50. The pixel circuit 51 may include an OS transistor. Note that the layer 50 can be stacked over the layer 20.

[0062] A Si transistor may be provided in the layer 50. For example, the pixel circuit 51 may be configured to include a transistor having single crystal silicon or polycrystalline silicon in the channel formation region. LTPS may be used as the polycrystalline silicon. For example, the layer 50 may be formed on a separate substrate and then bonded to the layer 20.

[0063] Furthermore, for example, the pixel circuit 51 may be configured with multiple types of transistors using different semiconductor materials. When the pixel circuit 51 is configured with multiple types of transistors using different semiconductor materials, the transistors may be provided in different layers for each type of transistor. For example, when the pixel circuit 51 is configured with Si transistors and OS transistors, the Si transistors and the OS transistors may be provided overlapping each other. By providing the transistors overlapping each other, the area occupied by the pixel circuit 51 can be reduced. This can improve the resolution of the display device 10A. Note that a configuration in which an LTPS transistor and an OS transistor are combined is sometimes referred to as LTPO.

[0064] The transistor 52, which is an OS transistor, is preferably a transistor including an oxide containing at least one of indium, an element M (the element M is aluminum, gallium, yttrium, or tin), and zinc in a channel formation region. Such an OS transistor has a characteristic of extremely low off-state current. Therefore, it is preferable to use an OS transistor, particularly as a transistor provided in a pixel circuit, because analog data written to the pixel circuit can be held for a long period of time.

[0065] A layer 60 is provided on the layer 50. A substrate 12 is provided on the layer 60. The substrate 12 is preferably a light-transmitting substrate or a layer made of a light-transmitting material. A plurality of light-emitting elements 61 are provided on the layer 60. The layer 60 can be configured to be stacked on the layer 50. The light-emitting elements 61 can be, for example, organic electroluminescence elements (also referred to as organic EL elements). However, the light-emitting elements 61 are not limited thereto, and for example, inorganic EL elements made of inorganic materials can also be used. Note that "organic EL elements" and "inorganic EL elements" may be collectively referred to as "EL elements." The light-emitting elements 61 may include inorganic compounds such as quantum dots. For example, quantum dots can be used in the light-emitting layer to function as a light-emitting material.

[0066] As shown in FIG. 3B , the display device 10A of one embodiment of the present invention can have a stacked structure including the light-emitting element 61, the pixel circuit 51, the driver circuit 30, and the functional circuit 40. This allows for an extremely high pixel aperture ratio (effective display area ratio). For example, the pixel aperture ratio can be 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, the pixel circuits 51 can be arranged at extremely high density, thereby achieving extremely high pixel resolution. For example, in the display portion 13 of the display device 10A (a region where the pixel circuit 51 and the light-emitting element 61 are stacked), pixels can be arranged with a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and further preferably 6000 ppi or more, and 20,000 ppi or less, or 30,000 ppi or less.

[0067] Because the display device 10A has extremely high resolution, it can be suitably used in VR devices such as head-mounted displays or eyeglass-type AR devices. For example, even in a configuration in which the display unit of the display device 10A is viewed through an optical component such as a lens, the display device 10A has an extremely high-resolution display unit, so that pixels are not visible even when the display unit is enlarged with a lens, thereby providing a highly immersive display.

[0068] When display device 10A is used as a wearable VR or AR display device, the diagonal size of display unit 13 can be 0.1 inches or more and 5.0 inches or less, preferably 0.5 inches or more and 2.0 inches or less, and more preferably 1 inch or more and 1.7 inches or less. For example, the diagonal size of display unit 13 may be 1.5 inches or close to 1.5 inches. Setting the diagonal size of display unit 13 to 2.0 inches or less allows processing with a single exposure process using an exposure device (typically a scanner device), thereby improving the productivity of the manufacturing process.

[0069] Furthermore, the display device 10A according to one embodiment of the present invention can be applied to devices other than wearable electronic devices. In this case, the diagonal size of the display unit 13 may exceed 2.0 inches. The configuration of the transistors used in the pixel circuits 51 may be appropriately selected depending on the diagonal size of the display unit 13. For example, when single-crystal Si transistors are used in the pixel circuits 51, the diagonal size of the display unit 13 is preferably 0.1 inches to 3 inches. When LTPS transistors are used in the pixel circuits 51, the diagonal size of the display unit 13 is preferably 0.1 inches to 30 inches, and more preferably 1 inch to 30 inches. When LTPO is used in the pixel circuits 51, the diagonal size of the display unit 13 is preferably 0.1 inches to 50 inches, and more preferably 1 inch to 50 inches. When OS transistors are used in the pixel circuits 51, the diagonal size of the display unit 13 is preferably 0.1 inches to 200 inches, and more preferably 50 inches to 100 inches.

[0070] Display devices using single-crystal Si transistors are very difficult to increase in size because it is difficult to increase the size of the single-crystal Si substrate. Furthermore, when LTPS transistors are used in display devices, it is difficult to accommodate larger screen sizes (typically, diagonal screen sizes exceeding 30 inches) because a laser crystallization apparatus is used in the manufacturing process. On the other hand, OS transistors are not restricted by the use of a laser crystallization apparatus or can be manufactured at a relatively low process temperature (typically, 450° C. or lower) in the manufacturing process, and therefore can accommodate display devices with relatively large areas (typically, diagonal screen sizes of 50 inches to 100 inches). Furthermore, LTPO transistors can accommodate diagonal screen sizes between those using LTPS transistors and those using OS transistors (typically, 1 inch to 50 inches).

[0071] A specific configuration example of the drive circuit 30 and the functional circuit 40 will be described with reference to Fig. 4. Fig. 4 is a block diagram illustrating pixel circuits 51 in the display device 10A, a plurality of wirings connecting the drive circuit 30 and the functional circuit 40, and bus wiring and the like within the display device 10A.

[0072] In the display device 10A shown in FIG. 4, a layer 50 has a plurality of pixel circuits 51 arranged in a matrix.

[0073] 4 , the layer 20 includes a drive circuit 30, a functional circuit 40, and an input / output circuit 80. The drive circuit 30 includes, for example, a source driver circuit 31, a digital-to-analog converter (DAC) 32, an amplifier circuit 35, a gate driver circuit 33, and a level shifter 34. The functional circuit 40 includes, for example, a memory device 41, a GPU (AI accelerator) 42, an EL correction circuit 43, a timing controller 44, a CPU 45, a sensor controller 46, and a power supply circuit 47. The functional circuit 40 has the function of an application processor.

[0074] The input / output circuit 80 supports transmission methods such as LVDS (Low Voltage Differential Signaling), and has a function of distributing control signals, image data, and the like input via the terminal unit 14 to the drive circuit 30 and the function circuit 40. The input / output circuit 80 also has a function of outputting information from the display device 10A to the outside via the terminal unit 14.

[0075] In addition, the display device 10A in FIG. 4 illustrates a configuration in which the circuits included in the drive circuit 30 and the circuits included in the functional circuit 40 are electrically connected to the bus line BSL.

[0076] For example, the source driver circuit 31 has a function of transmitting image data to the pixel circuit 51 of the pixel 230. Therefore, the source driver circuit 31 is electrically connected to the pixel circuit 51 via the wiring SL. Note that a plurality of source driver circuits 31 may be provided.

[0077] The digital-analog conversion circuit 32 has a function of converting image data that has been digitally processed by a GPU, a correction circuit, etc., which will be described later, into analog data. The image data converted into analog data is amplified by an amplifier circuit 35, such as an operational amplifier, and transmitted to the pixel circuits 51 via the source driver circuit 31. Note that the image data may be transmitted in the order of the source driver circuit 31, the digital-analog conversion circuit 32, and the pixel circuits 51. The digital-analog conversion circuit 32 and the amplifier circuit 35 may also be included in the source driver circuit 31.

[0078] For example, the gate driver circuit 33 has a function of selecting a pixel circuit 51 to which image data is to be sent. Therefore, the gate driver circuit 33 is electrically connected to the pixel circuit 51 through a wiring GL. Note that a plurality of gate driver circuits 33 may be provided corresponding to the source driver circuits 31.

[0079] The level shifter 34 has a function of converting signals input to the source driver circuit 31, the digital-to-analog conversion circuit 32, the gate driver circuit 33, etc., to appropriate levels, for example.

[0080] For example, the storage device 41 has a function of storing image data to be displayed on the pixel circuits 51. The storage device 41 can be configured to store the image data as digital data or analog data.

[0081] Furthermore, when image data is stored in the storage device 41, it is preferable to use a nonvolatile memory as the storage device 41. In this case, for example, a NAND type memory or the like can be used as the storage device 41.

[0082] Furthermore, when temporary data generated by the GPU 42, the EL correction circuit 43, the CPU 45, etc. is stored in the storage device 41, it is preferable to use a volatile memory as the storage device 41. In this case, for example, an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), etc. can be used as the storage device 41.

[0083] As an example, the GPU 42 has a function of performing processing to output image data read from the storage device 41 to the pixel circuit 51. In particular, the GPU 42 is configured to perform pipeline processing in parallel, and therefore can quickly process image data to be output to the pixel circuit 51. The GPU 42 can also have a function as a decoder for restoring encoded images.

[0084] The functional circuit 40 may also include multiple circuits capable of improving the display quality of the display device 10A. For example, such circuits may include a correction circuit (color adjustment, dimming) that detects color unevenness in the displayed image and corrects the color unevenness to produce an optimal image. For example, if a light-emitting device using an organic EL is used as the display element, the functional circuit 40 may include an EL correction circuit that corrects image data in accordance with the characteristics of the light-emitting device. As an example, the functional circuit 40 includes an EL correction circuit 43.

[0085] Furthermore, artificial intelligence may be used for the image correction described above. For example, the current flowing through the pixel circuit (or the voltage applied to the pixel circuit) may be monitored and acquired, and the displayed image may be acquired by an image sensor or the like, and the current (or voltage) and the image may be treated as input data for an artificial intelligence calculation (e.g., an artificial neural network), and the output result may be used to determine whether or not the image should be corrected.

[0086] Furthermore, the AI ​​calculations can be applied not only to image correction but also to up-conversion processing that increases the resolution of image data. As an example, the GPU 42 in Figure 4 shows blocks for performing various correction calculations (color unevenness correction 42a, up-conversion 42b, etc.).

[0087] The algorithm for performing the upconversion process of image data can be selected from the nearest neighbor method, the bilinear method, the bicubic method, the rapid and accurate image super-resolution (RAISR) method, the anchored neighborhood regression (ANR) method, the A+ method, the super-resolution convolutional neural network (SRCNN) method, and the like.

[0088] The upconversion process may be configured to use a different algorithm for each region determined according to the point of gaze. For example, the upconversion process for the region at and near the point of gaze may be performed using a slow but highly accurate algorithm, while the upconversion process for regions other than the point of gaze may be performed using a fast but less accurate algorithm. This configuration can shorten the time required for the upconversion process. It can also reduce the power consumption required for the upconversion process.

[0089] Furthermore, in addition to up-conversion processing, down-conversion processing may be performed to reduce the resolution of image data. If the resolution of the image data is greater than the resolution of the display unit 13, a portion of the image data may not be displayed on the display unit 13. In such a case, down-conversion processing can be performed to display the entire image data on the display unit 13.

[0090] For example, the timing controller 44 has a function of controlling the drive frequency (frame frequency, frame rate, refresh rate, etc.) at which an image is displayed. For example, when a still image is displayed on the display device 10A, the drive frequency can be lowered by the timing controller 44, thereby reducing the power consumption of the display device 10A.

[0091] The CPU 45 has a function of performing general-purpose processing such as, for example, running an operating system, controlling data, performing various calculations, and running programs. The CPU 45 has a role of issuing commands such as writing or reading image data to or from the storage device 41, correcting image data, and operating a sensor (described later). The CPU 45 may also have a function of transmitting a control signal to at least one of the circuits included in the functional circuit 40.

[0092] The sensor controller 46 has a function of controlling the sensor, for example. In addition, in Fig. 4, a wiring SNCL is illustrated as a wiring for electrically connecting to the sensor.

[0093] The sensor may be, for example, a touch sensor that can be provided in the display unit 13. Alternatively, the sensor may be, for example, an illuminance sensor.

[0094] For example, the power supply circuit 47 has a function of generating voltages to be supplied to the pixel circuits 51, the drive circuits 30, the functional circuits 40, etc. The power supply circuit 47 may also have a function of selecting the circuits to which the voltage is supplied. For example, the power supply circuit 47 can reduce the power consumption of the entire display device 10A by stopping the voltage supply to the CPU 45, the GPU 42, etc. during the period when a still image is being displayed.

[0095] As described above, the display device of one embodiment of the present invention can have a stacked structure including a display element, a pixel circuit, a driver circuit, and a functional circuit 40. The driver circuit and the functional circuit, which are peripheral circuits, can be arranged to overlap with the pixel circuit, and the width of the frame can be significantly reduced, thereby enabling a miniaturized display device. Furthermore, the display device of one embodiment of the present invention can be lightweight because the wiring connecting the circuits can be shortened by stacking the circuits. Furthermore, the display device of one embodiment of the present invention can have a display portion with improved pixel resolution, thereby enabling a display device with excellent display quality.

[0096] <Configuration Example of Display Module> Next, a configuration example of a display module including the display device 10A will be described.

[0097] 5A to 5C are perspective views of a display module 500. The display module 500 has a structure in which an FPC (Flexible Printed Circuit) 504 is provided on the terminal portion 14 of the display device 10A. The FPC 504 has a structure in which wiring is provided on a film made of an insulating material. The FPC 504 is flexible. The FPC 504 functions as wiring for supplying video signals, control signals, power supply potential, and the like from the outside to the display device 10A. An IC may also be mounted on the FPC 504.

[0098] 5B has a configuration in which the display device 10A is provided on a printed wiring board 501. The printed wiring board 501 has a structure in which wiring is provided inside or on the surface, or inside and on the surface, of a substrate made of an insulating material.

[0099] 5B, the terminal portion 14 of the display device 10A is electrically connected to the terminal portion 502 of the printed wiring board 501 via the wire 503. The wire 503 can be formed by wire bonding. The wire bonding can be ball bonding or wedge bonding.

[0100] After the wires 503 are formed, they may be covered with a resin material or the like. Note that the electrical connection between the display device 10A and the printed wiring board 501 may be achieved by a method other than wire bonding. For example, the electrical connection between the display device 10A and the printed wiring board 501 may be achieved by an anisotropic conductive adhesive, a bump, or the like.

[0101] 5B , the terminal portion 502 of the printed wiring board 501 is electrically connected to the FPC 504. For example, if the pitch of the electrodes in the terminal portion 14 of the display device 10A differs from the pitch of the electrodes in the FPC 504, the terminal portion 14 and the FPC 504 may be electrically connected via the printed wiring board 501. Specifically, the spacing (pitch) between the multiple electrodes in the terminal portion 14 can be converted to the spacing between the multiple electrodes in the terminal portion 502 using wiring formed on the printed wiring board 501. In other words, even if the pitch of the electrodes in the terminal portion 14 differs from the pitch of the electrodes in the FPC 504, electrical connection between the electrodes can be achieved.

[0102] Furthermore, the printed wiring board 501 can be provided with various elements such as resistor elements, capacitor elements, and semiconductor elements.

[0103] 5C , the terminal unit 502 may be electrically connected to a connection unit 505 provided on the lower surface (the surface on which the display device 10A is not provided) of the printed wiring board 501. For example, by using a socket-type connection unit as the connection unit 505, the display module 500 can be easily attached to and detached from other devices.

[0104] <Example of Operation of Electronic Device> An example of operation of the electronic device 100 will be described with reference to the drawings. FIG. 6 is a flowchart for explaining an example of operation of the electronic device 100.

[0105] The motion detection unit 101 acquires first information (information relating to the motion of the housing 105) (step E11).

[0106] The gaze detection unit 102 acquires second information (information relating to the user's gaze) (step E12).

[0107] The calculation unit 103 performs a rendering process of the 360-degree omnidirectional image data based on the first information (step E13).

[0108] Step E13 will be described with a specific example. The schematic diagram shown in Fig. 7A illustrates a user 112 positioned at the center of 360-degree omnidirectional image data 111. The user 112 can view an image 114A in a direction 113A displayed on the display device 10A of the electronic device 100.

[0109] 7B shows a state in which user 112 moves his / her head from the schematic diagram of Fig. 7A to view image 114B in direction 113B. Image 114A changes to image 114B in accordance with the movement of the housing of electronic device 100, allowing user 112 to recognize the space represented by image data 111 in all 360-degree directions.

[0110] 7A and 7B, the user 112 moves the housing of the electronic device 100 in accordance with the movement of his or her head. The higher the rendering processing capability used to process the image obtained from the 360-degree omnidirectional image data 111 in accordance with the movement of the electronic device 100, the more the user 112 can recognize a virtual space that is more in line with the space in the real world.

[0111] Based on the second information, the calculation unit 103 determines a plurality of regions of the display unit of the display device corresponding to the gaze point G (step E14). For example, as shown in Fig. 8A, a first region S1 including the gaze point G is determined, and a second region S2 adjacent to the first region S1 is determined. The outside of the second region is defined as a third region S3.

[0112] Step E14 will be described using a specific example.

[0113] Generally, human visual fields are broadly classified into the following five categories, although there are individual differences. The discriminative visual field is the area where visual functions such as visual acuity and color discrimination are best, and refers to the area within approximately 5° of the center of the visual field (the area including the point of gaze). The effective visual field is the area where specific information can be instantly identified using eye movement alone, and refers to the area adjacent to the discriminative visual field, within approximately 30° horizontally and 20° vertically of the center of the visual field (point of gaze). The stable gaze field is the area where specific information can be identified effortlessly with head movement, and refers to the area adjacent to the effective visual field, within approximately 90° horizontally and 70° vertically of the center of the visual field. The induced visual field is the area where the presence of a specific object can be detected but the ability to identify it is low, and refers to the area adjacent to the stable gaze field, within approximately 100° horizontally and 85° vertically of the center of the visual field. The auxiliary visual field is an area in which the ability to distinguish specific objects is significantly reduced, but the presence of stimuli can be detected. It is an area within approximately 100° to 200° horizontally and approximately 85° to 130° vertically from the center of the visual field, adjacent to the induced visual field.

[0114] From the above, it can be seen that the image quality from the discriminative field to the effective field is important in the image 114. In particular, the image quality of the discriminative field is crucial.

[0115] 8A is a schematic diagram showing a state in which a user 112 is observing an image 114 displayed on a display unit of a display device 10A of an electronic device 100 from the front (image display surface). The image 114 shown in FIG. 8A also corresponds to the display unit. A fixation point G at the end of the line of sight 113 of the user 112 is also shown on the image 114. In this specification, the area on the image 114 that includes the discriminative visual field is referred to as a "first area S1," and the area that includes the effective visual field is referred to as a "second area S2." The area that includes the stable fixation visual field, the induced visual field, and the auxiliary visual field is referred to as a "third area S3."

[0116] In FIG. 8A , the boundary (outline) between the first region S1 and the second region S2 is shown as a curve, but this is not limiting. As shown in FIG. 8B , the boundary (outline) between the first region S1 and the second region S2 may be rectangular or polygonal. It may also have a shape that combines straight lines and curves. The display unit of the display device 10A may also be divided into two regions, with the region that includes the discriminative visual field and the effective visual field being designated as the first region S1 and the other region being designated as the second region S2. In this case, the third region S3 is not formed.

[0117] 9A is a top view of image 114 displayed on the display unit of display device 10A of electronic device 100, and FIG. 9B is a side view of image 114 displayed on the display unit of display device 10A of electronic device 100. In this specification, the horizontal angle of first region S1 is referred to as "angle θx1," and the horizontal angle of second region S2 is referred to as "angle θx2" (see FIG. 9A). Also, in this specification, the vertical angle of first region S1 is referred to as "angle θy1," and the vertical angle of second region S2 is referred to as "angle θy2" (see FIG. 9B).

[0118] For example, by setting the angle θx1 to 10° and the angle θy1 to 10°, the area of ​​the first region S1 can be increased. In this case, part of the effective visual field is included in the first region S1. Furthermore, by setting the angle θx2 to 45° and the angle θy2 to 35°, the area of ​​the second region S2 can be increased. In this case, part of the stable visual field is included in the second region S2.

[0119] The position of the gaze point G fluctuates slightly due to fluctuations in the line of sight of the user 112. For this reason, it is preferable that the angles θx1 and θy1 are each greater than or equal to 5° and less than 20°. Setting the area of ​​the first region S1 to be larger than the discriminative field of view stabilizes the operation of the display device 10A and improves the visibility of the image.

[0120] When the line of sight 113 of the user 112 moves, the point of gaze G also moves. Therefore, the first area S1 and the second area S2 also move. For example, if the amount of change in the line of sight 113 exceeds a certain amount, it is determined that the line of sight 113 is moving. In other words, if the amount of change in the point of gaze G exceeds a certain amount, it is determined that the point of gaze G is moving. Furthermore, if the amount of change in the line of sight 113 becomes equal to or less than a certain amount, it is determined that the movement of the line of sight 113 has stopped, and the first area S1 to the third area S3 are determined. In other words, if the amount of change in the point of gaze G becomes equal to or less than a certain amount, it is determined that the movement of the point of gaze G has stopped, and the first area S1 to the third area S3 are determined.

[0121] In the functional circuit 40, the drive circuit 30 is controlled in accordance with the plurality of regions (first region S1 to third region S3) (step E15).

[0122] 10A and 10B show a configuration example of a pixel circuit 51 and a light-emitting element 61 connected to the pixel circuit 51. Fig. 10A is a diagram showing the connection of each element, and Fig. 10B is a diagram schematically showing the hierarchical relationship between a layer 20 including a driver circuit, a layer 50 including a plurality of transistors included in the pixel circuit, and a layer 60 including a light-emitting element.

[0123] 10A and 10B includes a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53. The transistors 52A, 52B, and 52C can be OS transistors. Each of the OS transistors 52A, 52B, and 52C preferably includes a back gate electrode. In this case, the back gate electrode can be configured to receive the same signal as the gate electrode, or a signal different from the gate electrode.

[0124] The transistor 52B includes a gate electrode electrically connected to the transistor 52A, a first electrode electrically connected to the light-emitting element 61, and a second electrode electrically connected to the wiring ANO. The wiring ANO is a wiring for applying a potential for supplying a current to the light-emitting element 61.

[0125] The transistor 52A has a first terminal electrically connected to the gate electrode of the transistor 52B, a second terminal electrically connected to the wiring SL that functions as a source line, and a gate electrode that has the function of controlling the conductive state or non-conductive state based on the potential of the wiring GL1 that functions as a gate line.

[0126] The transistor 52C includes a first terminal electrically connected to the wiring V0, a ​​second terminal electrically connected to the light-emitting element 61, and a gate electrode having a function of controlling a conductive state or a non-conductive state based on the potential of the wiring GL2 functioning as a gate line. The wiring V0 is a wiring for applying a reference potential and a wiring for outputting a current flowing through the pixel circuit 51 to the driver circuit 30 or the functional circuit 40.

[0127] The capacitor 53 includes a conductive film electrically connected to the gate electrode of the transistor 52B and a conductive film electrically connected to the second electrode of the transistor 52C.

[0128] The light-emitting element 61 includes a first electrode electrically connected to the first electrode of the transistor 52B and a second electrode electrically connected to a wiring VCOM. The wiring VCOM is a wiring for applying a potential for supplying a current to the light-emitting element 61.

[0129] This allows the intensity of light emitted by the light-emitting element 61 to be controlled in accordance with an image signal applied to the gate electrode of the transistor 52B. Furthermore, the reference potential of the wiring V0 applied via the transistor 52C can suppress variations in the gate-source potential difference of the transistor 52B.

[0130] Furthermore, a current value that can be used to set pixel parameters can be output from the wiring V0. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting element 61 to the outside. The current output to the wiring V0 is converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an A-D converter or the like and output to the functional circuit 40 or the like.

[0131] Note that the light-emitting element described in one embodiment of the present invention refers to a self-luminous display element such as an organic light-emitting diode (OLED). Note that the light-emitting element electrically connected to the pixel circuit can be a self-luminous light-emitting element such as an LED (light-emitting diode), a micro LED, a quantum-dot light-emitting diode (QLED), or a semiconductor laser.

[0132] In the configuration shown in FIG. 10B as an example, the wiring electrically connecting the pixel circuits 51 and the drive circuit 30 can be shortened, thereby reducing the wiring resistance of the wiring. This allows data to be written at high speed, enabling the display device 10A to be driven at high speed. This allows the display device 10A to have a sufficient frame period even if the number of pixel circuits 51 is increased, thereby increasing the pixel density of the display device 10A. Furthermore, increasing the pixel density of the display device 10A can increase the resolution of the image displayed by the display device 10A. For example, the pixel density of the display device 10A can be 1000 ppi or more, 5000 ppi or more, or 7000 ppi or more. Therefore, the display device 10A can be used as a display device for AR or VR, for example, and can be suitably applied to electronic devices such as HMDs, in which the display unit is close to the user.

[0133] 10A and 10B show an example of the pixel circuit 51 including three transistors in total, but one embodiment of the present invention is not limited thereto. Below, a configuration example of a pixel circuit applicable to the pixel circuit 51 and an example of a driving method thereof will be described.

[0134] 11A illustrates a pixel circuit 51A including a transistor 52A, a transistor 52B, and a capacitor 53. Also illustrated in FIG. 11A is a light-emitting element 61 connected to the pixel circuit 51A. The pixel circuit 51A is electrically connected to a wiring SL, a wiring GL, a wiring ANO, and a wiring VCOM. The pixel circuit 51A has a configuration in which the transistor 52C is removed from the pixel circuit 51 illustrated in FIG. 10A and the wirings GL1 and GL2 are replaced with a wiring GL.

[0135] The transistor 52A has a gate electrically connected to the wiring GL, one of its source and drain electrically connected to the wiring SL, and the other electrically connected to the gate of the transistor 52B and one electrode of the capacitor C1. The transistor 52B has one of its source and drain electrically connected to the wiring ANO, and the other electrically connected to the anode of the light-emitting element 61. The other electrode of the capacitor C1 is electrically connected to the anode of the light-emitting element 61. The light-emitting element 61 has a cathode electrically connected to the wiring VCOM.

[0136] 11B is configured by adding a transistor 52C to the pixel circuit 51A. A wiring V0 is electrically connected to the pixel circuit 51B.

[0137] A pixel circuit 51C shown in FIG. 11C is an example in which transistors having a pair of gates electrically connected are used as the transistors 52A and 52B of the pixel circuit 51A. A pixel circuit 51D shown in FIG. 11D is an example in which the same transistors are used as the pixel circuit 51B. This can increase the current that the transistors can pass. Note that, although transistors having a pair of gates electrically connected are used as all the transistors here, this is not a limitation. Alternatively, a transistor having a pair of gates electrically connected to different wirings may be used. For example, reliability can be improved by using a transistor in which one of the gates is electrically connected to a source.

[0138] 12A has a configuration in which a transistor 52D is added to the pixel circuit 51B. The pixel circuit 51E is electrically connected to wirings GL1, GL2, and GL3 that function as gate lines. Note that in this embodiment and other examples, the wirings GL1, GL2, and GL3 may be collectively referred to as wirings GL. Therefore, the number of wirings GL is not limited to one, and there may be multiple wirings GL.

[0139] The gate of the transistor 52D is electrically connected to a wiring GL3, one of the source and drain of the transistor 52D is electrically connected to the gate of the transistor 52B, and the other is electrically connected to a wiring V0. The gate of the transistor 52A is electrically connected to a wiring GL1, and the gate of the transistor 52C is electrically connected to a wiring GL2.

[0140] By simultaneously turning on the transistors 52C and 52D, the source and gate of the transistor 52B have the same potential, and the transistor 52B can be turned off. This makes it possible to forcibly cut off the current flowing through the light-emitting element 61. Such a pixel circuit is suitable for use in a display method in which display periods and off periods are alternately provided.

[0141] 12B is an example in which a capacitor 53A is added to the pixel circuit 51E. The capacitor 53A functions as a storage capacitor.

[0142] 12C and 12D are examples in which transistors each having a pair of gates are applied to the pixel circuit 51E or 51F, respectively. Transistors 52A, 52C, and 52D are transistors in which a pair of gates are electrically connected, and transistor 52B is a transistor in which one gate is electrically connected to a source.

[0143] Next, a description will be given of an example of a method for driving a display device to which pixel circuit 51 E is applied. Note that the same driving method can also be applied to display devices to which pixel circuits 51 F, 51 G, and 51 H are applied.

[0144] 13 is a timing chart illustrating a driving method of a display device using the pixel circuit 51E. The timing chart illustrates the transition of potentials of the wirings GL1[k], GL2[k], and GL3[k], which are gate lines in the kth row, and the wirings GL1[k+1], GL2[k+1], and GL3[k+1], which are gate lines in the k+1th row. The timing chart also illustrates the timing of signals applied to the wirings SL, which function as source lines.

[0145] Here, an example of a driving method is shown in which one horizontal period is divided into a light-on period and a light-off period. The horizontal period for the kth row and the horizontal period for the k+1th row are shifted by the selection period of the gate line.

[0146] In the lighting period of the kth row, a high-level potential is first applied to the wiring GL1[k] and the wiring GL2[k], and a source signal is applied to the wiring SL. This brings the transistors 52A and 52C into conduction, and a potential corresponding to the source signal is written from the wiring SL to the gate of the transistor 52B. After that, a low-level potential is applied to the wiring GL1[k] and the wiring GL2[k], bringing the transistors 52A and 52C into non-conduction, and the gate potential of the transistor 52B is maintained.

[0147] Subsequently, the lighting period of the k+1th row begins, and data is written in the same manner as above.

[0148] Next, the off-period will be described. During the off-period of the kth row, a high-level potential is applied to the wiring GL2[k] and the wiring GL3[k]. As a result, the transistors 52C and 52D are turned on, and the same potential is applied to the source and gate of the transistor 52B, so that almost no current flows through the transistor 52B. This turns off the light-emitting element 61. All subpixels located in the kth row are turned off. The subpixels in the kth row remain off until the next light-on period.

[0149] Next, the process transitions to the off period of the k+1th row, and all the sub-pixels of the k+1th row are in the off state in the same manner as above.

[0150] This driving method, in which the display is not always on during one horizontal period but has an off period during one horizontal period, can also be called duty driving. Duty driving can reduce the afterimage phenomenon when displaying moving images, thereby realizing a display device with high moving image display performance. In particular, in VR devices, reducing afterimages can alleviate so-called VR sickness.

[0151] In duty driving, the ratio of the on period to one horizontal period can be called the duty ratio. For example, a duty ratio of 50% means that the on period and the off period are the same length. The duty ratio can be freely set and can be adjusted as appropriate within a range of, for example, more than 0% and less than 100%.

[0152] Furthermore, a configuration different from the pixel circuit described above will be described with reference to FIGS. 14A and 14B.

[0153] Fig. 14A shows a block diagram of a pixel 230. The pixel shown in Fig. 14A has a memory circuit MEM (Memory) in addition to a switching transistor (Switching Tr), a driving transistor (Driving Tr), and a light-emitting element (LED).

[0154] Data DataW is supplied to the memory circuit MEM through the wiring SL2 and the transistor 52A. When the data DataW is supplied to the pixel in addition to the image data Data, the current flowing through the light-emitting element increases, and the display device can achieve high luminance.

[0155] FIG. 14B shows a specific circuit diagram of the pixel circuit 51I.

[0156] A pixel circuit 51I shown in Fig. 14B includes a transistor 52w, a transistor 52A, a transistor 52B, a transistor 52C, a capacitor 53s, and a capacitor 53w. Fig. 14B also shows a light-emitting element 61 connected to the pixel circuit 51I.

[0157] The transistor 52w functions as a switching transistor. The transistor 52B functions as a driving transistor. One of the source or drain of the transistor 52w is electrically connected to one electrode of a capacitor 53w. The other electrode of the capacitor 53w is electrically connected to one of the source or drain of the transistor 52A. One of the source or drain of the transistor 52A is electrically connected to the gate of the transistor 52B. The gate of the transistor 52B is electrically connected to one electrode of a capacitor 53s. The other electrode of the capacitor 53s is electrically connected to one of the source or drain of the transistor 52B. One of the source or drain of the transistor 52B is electrically connected to one of the source or drain of the transistor 52C. One of the source or drain of the transistor 52C is electrically connected to one electrode of the light-emitting element 61. Although each transistor shown in FIG. 14B has a backgate electrically connected to the gate, the connection of the backgate is not limited to this. Furthermore, the transistor does not necessarily have to have a backgate.

[0158] Here, a node NM is defined as a node to which the other electrode of the capacitor 53w, one of the source or drain of the transistor 52A, the gate of the transistor 52B, and one electrode of the capacitor 53s are connected, and a node NA is defined as a node to which the other electrode of the capacitor 53s, one of the source or drain of the transistor 52B, one of the source or drain of the transistor 52C, and one electrode of the light-emitting element 61 are connected.

[0159] The gate of the transistor 52w is electrically connected to the wiring GL1. The gate of the transistor 52C is electrically connected to the wiring GL1. The gate of the transistor 52A is electrically connected to the wiring GL2. The other of the source and the drain of the transistor 52w is electrically connected to the wiring SL1. The other of the source and the drain of the transistor 52C is electrically connected to the wiring V0. The other of the source and the drain of the transistor 52A is electrically connected to the wiring SL2. Note that in this embodiment and the like, the wirings SL1 and SL2 may be collectively referred to as wirings SL. Thus, the number of wirings SL is not limited to one, and may be multiple.

[0160] The other of the source and the drain of the transistor 52B is electrically connected to a wiring ANO. The other electrode of the light-emitting element 61 is electrically connected to a wiring VCOM.

[0161] The wirings GL1 and GL2 can function as signal lines for controlling the operation of the transistors. The wiring SL1 can function as a signal line for supplying image data Data to the pixels. The wiring SL2 can function as a signal line for writing data DataW to the memory circuit MEM. For example, the wiring SL2 can function as a signal line for supplying a correction signal to the pixels. The wiring V0 functions as a monitor line for acquiring electrical characteristics of the transistor 52B. Furthermore, by supplying a specific potential from the wiring V0 to the other electrode of the capacitor 53s through the transistor 52C, writing of an image signal can be stabilized.

[0162] The transistor 52A and the capacitor 53w constitute a memory circuit MEM. The node NM is a memory node, and data DataW supplied from the wiring SL2 can be written to the node NM by turning on the transistor 52A. By using an OS transistor with extremely low off-state current as the transistor 52A, the potential of the node NM can be held for a long time.

[0163] In the pixel circuit 51I, image data Data supplied from the wiring SL1 is supplied to a capacitor 53w via a transistor 52w. One of the source or drain of the transistor 52w is capacitively coupled to a node NM. Therefore, the potential of the node NM to which data DataW is written changes in accordance with the image data Data. In addition, the node NA and the node NM are capacitively coupled via a capacitor 53s. Therefore, the potential of the node NA changes in accordance with the data DataW and the image data Data.

[0164] The transistor 52w functions as a selection transistor that determines whether or not image data Data is supplied. The transistor 52C functions as a reset transistor that determines whether or not the potential of the node NA is set equal to that of the wiring V0.

[0165] Furthermore, in the display device of one embodiment of the present invention, defective pixels can be detected by using the functional circuit 40 overlapping with the pixel circuit group 55. By using information about the defective pixels, display defects due to the defective pixels can be corrected, and normal display can be achieved.

[0166] A part or all of the correction methods exemplified below may be executed by a circuit provided outside the display device. Alternatively, a part of the correction method may be executed by the functional circuit 40, and another part may be executed by a circuit provided outside the display device.

[0167] A more specific example of the correction method will be described below. Fig. 15A is a flowchart of the correction method described below.

[0168] First, the correction operation is started in step E1.

[0169] Subsequently, in step E2, the pixel current is read out, for example, by driving each pixel to output a current to a monitor line electrically connected to the pixel.

[0170] When pixel circuit group 55 is divided into a plurality of sections 59, such as in a display device 10B described below, the current readout operation can be performed simultaneously for each section 59. By dividing pixel circuit group 55 into a plurality of sections 59, the current readout operation for all pixels can be performed in an extremely short time.

[0171] Next, in step E3, the read current is converted into a voltage. At this time, if a digital signal is to be handled in subsequent processing, it can be converted into digital data in step E3. For example, analog data can be converted into digital data using an analog-to-digital converter (ADC).

[0172] Next, in step E4, pixel parameters for each pixel are obtained based on the obtained data, such as the threshold voltage or field effect mobility of the driving transistor, the threshold voltage of the light-emitting element, and the current value at a predetermined voltage.

[0173] Next, in step E5, each pixel is judged to be abnormal based on the pixel parameter, for example, if the value of the pixel parameter exceeds (or falls below) a predetermined threshold value, the pixel is recognized as an abnormal pixel.

[0174] The abnormalities include dark spot defects with significantly low brightness relative to the input data potential, and bright spot defects with significantly high brightness.

[0175] In step E5, the address of the abnormal pixel and the type of defect can be identified and obtained.

[0176] Subsequently, in step E6, correction processing is performed.

[0177] An example of the correction process will be described with reference to Fig. 15B. Fig. 15B schematically shows a pixel, each of which is a set of 3 x 3 pixel circuits 51 and light-emitting elements 61. Here, it is assumed that the central pixel is pixel 151, which is a dark point defect. Fig. 15B schematically shows a state in which pixel 151 is turned off and the surrounding pixels 150 are turned on at a predetermined brightness.

[0178] A dark point defect is a defect in which the brightness of the pixel is unlikely to reach normal brightness even if a correction is made to increase the data potential input to the pixel. Therefore, as shown in Figure 15B, a correction is made to increase the brightness of pixels 150 surrounding a pixel 151 with a dark point defect. This makes it possible to display a normal image even if a dark point defect occurs.

[0179] In the case of a bright spot defect, the bright spot defect can be made less noticeable by lowering the brightness of the surrounding pixels.

[0180] In particular, in the case of a display device with high resolution (e.g., 1000 ppi or more), it is difficult to visually distinguish adjacent pixels, so it is particularly effective to use a correction method that compensates for abnormal pixels using surrounding pixels.

[0181] On the other hand, it is preferable to correct pixels in which an abnormality such as a dark spot defect or a bright spot defect has occurred so that no data potential is input.

[0182] In this way, correction parameters can be set for each pixel. By applying the correction parameters to input image data, corrected image data can be generated to display an optimal image on the display device 10A.

[0183] Furthermore, since variations exist in pixel parameters not only for abnormal pixels and pixels surrounding the abnormal pixels but also for pixels not determined to be abnormal pixels, unevenness due to the variations may be visible when an image is displayed. Therefore, for pixels not determined to be abnormal pixels, correction parameters can be set to cancel (level out) the variations in pixel parameters. For example, a reference value based on the median or average value of pixel parameters for some or all pixels can be set, and a correction value for canceling the difference between the pixel parameters of a specific pixel and the reference value can be set as the correction parameter for that pixel.

[0184] Furthermore, for pixels surrounding an abnormal pixel, it is preferable to set correction data that takes into consideration both the amount of correction for compensating for the abnormal pixel and the amount of correction for canceling variations in pixel parameters.

[0185] Then, in step E7, the correction operation is completed.

[0186] Thereafter, an image can be displayed based on the correction parameters acquired in the above correction operation and the input image data.

[0187] A neural network may be used in one of the steps of the correction operation. In the neural network, correction parameters can be determined based on inference results obtained by machine learning, for example. For example, when the correction parameters are determined using a neural network, high-precision correction can be performed so that abnormal pixels are not noticeable, without using a detailed correction algorithm.

[0188] The above is the explanation of the correction method.

[0189] 16A and 16B are perspective views of a display device 10B that is a modification of the display device 10A. Fig. 16B is a perspective view for explaining the configuration of each layer of the display device 10B. To reduce repetition of explanation, differences from the display device 10A will be mainly explained.

[0190] The display device 10B has a pixel circuit group 55 including a plurality of pixel circuits 51 and a drive circuit 30 stacked on top of each other. In the display device 10B, the pixel circuit group 55 is divided into a plurality of sections 59, and the drive circuit 30 is divided into a plurality of sections 39. Each of the plurality of sections 39 has a source driver circuit 31 and a gate driver circuit 33.

[0191] FIG. 17A shows an example of the configuration of a pixel circuit group 55 included in the display device 10B. FIG. 17B shows an example of the configuration of a drive circuit 30 included in the display device 10B. The partitions 59 and 39 are each arranged in a matrix of m rows and n columns (m and n are each integers equal to or greater than 1). In this specification, the partition 59 in the first row and first column is referred to as partition 59[1,1], and the partition 59 in the mth row and nth column is referred to as partition 59[m,n]. Similarly, the partition 39 in the first row and first column is referred to as partition 39[1,1], and the partition 39 in the mth row and nth column is referred to as partition 39[m,n]. FIGS. 17A and 17B show a case where m is 4 and n is 8. That is, the pixel circuit group 55 and the drive circuit 30 are each divided into 32 sections.

[0192] Each of the plurality of sections 59 has a plurality of pixel circuits 51, a plurality of wirings SL, and a plurality of wirings GL. In each of the plurality of sections 59, one of the plurality of pixel circuits 51 is electrically connected to at least one of the plurality of wirings SL and at least one of the plurality of wirings GL.

[0193] One of the sections 59 and one of the sections 39 are arranged to overlap (see FIG. 17C ). For example, section 59[i,j] (i is an integer between 1 and m, and j is an integer between 1 and n) and section 39[i,j] are arranged to overlap. The source driver circuit 31[i,j] of section 39[i,j] is electrically connected to the wiring SL of section 59[i,j]. The gate driver circuit 33[i,j] of section 39[i,j] is electrically connected to the wiring GL of section 59[i,j]. The source driver circuit 31[i,j] and the gate driver circuit 33[i,j] have the function of controlling the multiple pixel circuits 51 of section 59[i,j].

[0194] By overlapping the section 59[i,j] and the section 39[i,j], the connection distance (wiring length) between the pixel circuit 51 in the section 59[i,j] and the source driver circuit 31 and gate driver circuit 33 in the section 39[i,j] can be made extremely short. As a result, the wiring resistance and parasitic capacitance are reduced, which shortens the time required for charging and discharging, enabling high-speed driving. This also reduces power consumption. Furthermore, miniaturization and weight reduction can be achieved.

[0195] Furthermore, display device 10B has a configuration in which each section 39 has a source driver circuit 31 and a gate driver circuit 33. Therefore, display unit 13 can be divided into sections 59 corresponding to sections 39, and image data can be rewritten. For example, it is possible to rewrite image data only in sections of display unit 13 where changes have occurred in the image, and to retain image data in sections where no changes have occurred, thereby realizing a reduction in power consumption.

[0196] In the present embodiment and other embodiments, one of the display units 13 divided into sections 59 is referred to as a sub-display unit 19. Therefore, it can be said that the sub-display units 19 are divided into sections 39. The display device 10B described with reference to FIGS. 16 and 17 shows a case in which the display unit 13 is divided into 32 sub-display units 19 (see FIG. 16A ). The sub-display units 19 include a plurality of pixels 230 shown in FIG. 10 and other drawings. Specifically, one sub-display unit 19 includes one of the sections 59 including a plurality of pixel circuits 51, and a plurality of light-emitting elements 61. Furthermore, one section 39 has the function of controlling the plurality of pixels 230 included in one sub-display unit 19.

[0197] Furthermore, the display device 10B can arbitrarily set the drive frequency for image display for each sub-display unit 19 by using the timing controller 44 of the functional circuit 40. The functional circuit 40 has a function of controlling the operation of each of the multiple sections 39 and the multiple sections 59. In other words, the functional circuit 40 has a function of controlling the drive frequency and operation timing of each of the multiple sub-display units 19 arranged in a matrix. The functional circuit 40 also has a function of adjusting synchronization between the sub-display units.

[0198] Furthermore, a timing controller 441 and an input / output circuit 442 may be provided for each partition 39 (see FIG. 17D). The input / output circuit 442 may be, for example, an I2C (Inter-Integrated Circuit) interface. In FIG. 17, the timing controller 441 included in the partition 39[i,j] is indicated as timing controller 441[i,j]. Furthermore, the input / output circuit 442 included in the partition 39[i,j] is indicated as input / output circuit 442[i,j].

[0199] For example, the functional circuit 40 supplies to the input / output circuit 442[i,j] operation parameters such as setting signals for the scanning direction and drive frequency of the gate driver circuit 33[i,j], and the number of pixels to be thinned out of image data when reducing the resolution (the number of pixels not to be rewritten when rewriting image data). The source driver circuit 31[i,j] and the gate driver circuit 33[i,j] operate in accordance with these operation parameters.

[0200] Furthermore, if the sub-display unit 19 has a light-receiving element, which will be described later, the input / output circuit 442 outputs information photoelectrically converted by the light-receiving element to the function circuit 40 .

[0201] The display device 10B in the electronic device of one embodiment of the present invention has pixel circuits 51 and drive circuits 30 stacked together, and can achieve low power consumption by varying the drive frequency for each sub-display unit 19 in response to the movement of the user's line of sight.

[0202] FIG. 18A shows a display unit 13 having four rows and eight columns of sub-display units 19. FIG. 18A also shows a first region S1 to a third region S3 centered around a fixation point G. The calculation unit 103 assigns each of the multiple sub-display units 19 to either a first region 29A overlapping with the first region S1 or the second region S2, or a second region 29B overlapping with the third region S3. That is, the calculation unit 103 assigns each of the multiple sections 39 to either the first region 29A or the second region 29B. In this case, the first region 29A overlapping with the first region S1 or the second region S2 includes the region overlapping with the fixation point G. The second region 29B includes sub-display units 19 located outside the first region 29A (see FIG. 18B).

[0203] The operation of the drive circuits (source driver circuit 31 and gate driver circuit 33) included in each of the multiple sections 39 is controlled by the functional circuit 40. For example, the second section 29B overlaps with the third region S3, which includes the stable fixation field, the induced field, and the auxiliary field, and is an area where the user's ability to distinguish is low. Therefore, even if the number of times image data is rewritten per unit time (hereinafter also referred to as the "number of image rewrites") in the second section 29B is lower than that in the first section 29A, the actual display quality perceived by the user (hereinafter also referred to as the "actual display quality") is less degraded. In other words, even if the drive frequency (also referred to as the "second drive frequency") of the sub-display unit 19 included in the second section 29B is lower than the drive frequency (also referred to as the "first drive frequency") of the sub-display unit 19 included in the first section 29A, the actual display quality is less degraded.

[0204] Lowering the drive frequency can reduce the power consumption of the display device. On the other hand, lowering the drive frequency also reduces the display quality. In particular, the display quality when displaying moving images is reduced. According to one aspect of the present invention, by setting the second drive frequency lower than the first drive frequency, it is possible to reduce power consumption in areas where user visibility is low while suppressing a substantial reduction in display quality. According to one aspect of the present invention, it is possible to maintain display quality while reducing power consumption.

[0205] The first drive frequency may be 30 Hz or more and 500 Hz or less, preferably 60 Hz or more and 500 Hz or less. The second drive frequency is preferably equal to or less than the first drive frequency, more preferably equal to or less than half the first drive frequency, and even more preferably equal to or less than one-fifth the first drive frequency.

[0206] Furthermore, among the sub-display units 19 overlapping the third region S3, the area farther from the first area 29A may be designated as a third area 29C (see FIG. 18C ), and the drive frequency (also referred to as the "third drive frequency") of the sub-display units 19 included in the third area 29C may be set lower than that of the second area 29B. The third drive frequency is preferably equal to or lower than the second drive frequency, more preferably equal to or lower than half the second drive frequency, and even more preferably equal to or lower than one-fifth the second drive frequency. By significantly reducing the number of times the image is rewritten, power consumption can be further reduced. Furthermore, image data rewriting may be stopped as necessary. Stopping image data rewriting can further reduce power consumption.

[0207] When such a driving method is used, it is preferable to use a transistor with extremely low off-state current as the transistor constituting the pixel circuit 51. For example, it is preferable to use an OS transistor as the transistor constituting the pixel circuit 51. Because the off-state current of an OS transistor is extremely low, image data supplied to the pixel circuit 51 can be held for a long period of time. In particular, it is preferable to use an OS transistor as the transistor 52A.

[0208] Furthermore, when the video scene displayed on the display unit 13 changes, an image with significantly different brightness, contrast, or color tone from the immediately preceding image may be displayed. In such a case, a difference occurs in the timing of image switching between the first area 29A and an area with a lower drive frequency than the first area 29A, resulting in a significant difference in brightness, contrast, or color tone between the two areas, which may result in a loss of substantial display quality. In such a case, for example, when the video scene changes, the image data in areas other than the first area 29A may be rewritten at the same drive frequency as the first area 29A, and then the drive frequency for the areas other than the first area 29A may be lowered.

[0209] Furthermore, if it is determined that the amount of change in the gaze point G has exceeded a certain amount, the image data of areas other than the first area 29A may also be rewritten at the same drive frequency as the first area 29A, and if it is determined that the amount of change is within the certain amount, the drive frequency of the areas other than the first area 29A may be reduced. Furthermore, if it is determined that the amount of change in the gaze point G is small, the drive frequency of the areas other than the first area 29A may be further reduced.

[0210] Furthermore, if the display device 10B does not have a frame memory, which is a storage device that temporarily stores image data, or if it has one frame memory for the entire display unit 13, the second drive frequency and the third drive frequency must both be an integer multiple of the first drive frequency.

[0211] By providing a frame memory corresponding to each of the multiple sub-display units 19, the second drive frequency and the third drive frequency can be set to any value, not just an integer fraction of the first drive frequency. By setting the second drive frequency and the third drive frequency to any value, the degree of freedom in setting the drive frequency can be increased. Therefore, the actual degradation of display quality can be reduced.

[0212] 19 is a block diagram illustrating an example of the configuration of a display device 10B having a frame memory 443 for each sub-display unit 19. In Fig. 19, the input / output circuit 80 has an image information input unit 461 and a clock signal input unit 462. The functional circuit 40 also has an image data temporary storage unit 463, an operation parameter setting unit 464, an internal clock signal generation unit 465, an image processing unit 466, a memory controller 467, and multiple frame memories 443.

[0213] One of the plurality of frame memories 443 has a function of storing image data to be displayed on one of the plurality of sub-display units 19. For example, frame memory 443[1,1] has a function of storing image data to be displayed on sub-display unit 19[1,1]. Similarly, frame memory 443[m,n] has a function of storing image data to be displayed on sub-display unit 19[m,n].

[0214] 19, each of the plurality of sub-display sections 19 is electrically connected to one of the plurality of sections 39. In FIG. 19, each of the plurality of sections 39 includes a source driver circuit 31, a gate driver circuit 33, a timing controller 441, and an input / output circuit 442.

[0215] Image data to be displayed on the display unit 13 and operating parameters of the display device 10B are supplied from the outside to the image information input unit 461. A clock signal is supplied from the outside to the clock signal input unit 462. The clock signal is also supplied to an internal clock signal generation unit 465 via the clock signal input unit 462.

[0216] The internal clock signal generating unit 465 has a function of using an externally supplied clock signal to generate a clock signal (also referred to as an "internal clock signal") to be used within the display device 10B. The internal clock signal is supplied to the image data temporary storage unit 463, the operation parameter setting unit 464, the memory controller 467, the partition 39, etc., and is used to synchronize the operation timing of each circuit constituting the display device 10B.

[0217] The image data input via the image information input unit 461 is supplied to an image data temporary storage unit 463. The operation parameters input via the image information input unit 461 are supplied to an operation parameter setting unit 464.

[0218] The image data temporary storage unit 463 holds the supplied image data and, in synchronization with an internal clock signal, supplies the image data to the image processing unit 466. By providing the image data temporary storage unit 463, it is possible to eliminate the difference between the timing at which image data is supplied from the outside and the timing at which the image data is processed inside the display device 10B.

[0219] The operation parameter setting unit 464 has a function of holding the supplied operation parameters. The operation parameters include information for determining the drive frequency, scanning direction, resolution settings, etc. for each of the multiple sub-display units 19.

[0220] Image processing unit 466 has a function of performing arithmetic processing of the image data stored in image data temporary storage unit 463. For example, image processing unit 466 has a function of performing contrast adjustment, brightness adjustment, gamma correction, etc. of the image data. Image processing unit 466 also has a function of dividing the image data stored in image data temporary storage unit 463 for each sub-display unit 19.

[0221] The memory controller 467 has a function of controlling the operation of the plurality of frame memories 443. The image data divided for each sub-display unit 19 by the image processing unit 466 is stored in each of the plurality of frame memories 443. Furthermore, the plurality of frame memories 443 have a function of supplying image data to the respective partitions 39 in response to a read request signal (read) from the corresponding partition 39.

[0222] 20, the storage device 41 may be used as a frame memory 443. That is, the storage device 41 may store image data divided for each sub-display unit 19.

[0223] The frame memory 443 may be provided in a location other than the functional circuit 40. The frame memory 443 may be provided in a semiconductor device other than the display device 10B.

[0224] The areas set in the display unit 13 are not limited to the three areas, the first area 29A, the second area 29B, and the third area 29C. Four or more areas may be set in the display unit 13. By setting a plurality of areas in the display unit 13 and gradually lowering the drive frequency, it is possible to further reduce the actual degradation of display quality.

[0225] The image displayed in the first area 29A may be subjected to the above-described upconversion process. By displaying an upconverted image in the first area 29A, the display quality can be improved. The image displayed in areas other than the first area 29A may be subjected to the above-described upconversion process. By displaying an upconverted image in areas other than the first area 29A, the actual degradation in display quality when the drive frequency in areas other than the first area 29A is reduced can be further reduced.

[0226] It is also possible to use a high-precision algorithm to upconvert the image displayed in the first area 29A and a low-precision algorithm to upconvert the image displayed in areas other than the first area 29A. Even in this case, it is possible to further reduce the substantial degradation in display quality when the drive frequency for areas other than the first area 29A is reduced.

[0227] Furthermore, high-speed rewriting can be achieved by simultaneously rewriting image data for all sub-display sections 19 instead of for each sub-display section 19. In other words, high-speed rewriting can be achieved by simultaneously rewriting image data for all sections 39 instead of for each section 39.

[0228] Generally, in the case of line-sequential driving, the source driver circuit simultaneously writes image data to all pixels in one row while the gate driver circuit selects the pixels in that row. For example, if the display unit 13 is not divided into sub-display units 19 and has a resolution of 4000 x 2000 pixels, the source driver circuit must write image data to 4000 pixels while the gate driver circuit selects one row of pixels. When the frame frequency is 120 Hz, one frame time is approximately 8.3 msec. Therefore, the gate driver circuit must select 2000 rows of pixels in approximately 8.3 msec, and the time required to select one row of pixels, i.e., the time required to write image data per pixel, is approximately 4.17 μsec. In other words, the higher the resolution of the display unit and the higher the frame frequency, the more difficult it becomes to ensure sufficient time for rewriting image data.

[0229] In the display device 10B exemplified in this embodiment, the display unit 13 is divided into four sections in the row direction. Therefore, in one sub-display unit 19, the time required to write image data per pixel can be four times longer than when the display unit 13 is not divided. According to one aspect of the present invention, even when the frame frequency is set to 240 Hz or even 360 Hz, it is easy to ensure the time required to rewrite image data, thereby realizing a display device with high display quality.

[0230] Furthermore, in the display device 10B exemplified in this embodiment, the display unit 13 is divided into four in the row direction, so the length of the wiring SL electrically connecting the source driver circuit and the pixel circuit is reduced to one-fourth, which reduces the resistance and parasitic capacitance of the wiring SL to one-fourth, thereby shortening the time required to write (rewrite) image data.

[0231] In addition, in the display device 10B exemplified in this embodiment, the display unit 13 is divided into eight sections in the column direction, so the length of the wiring GL electrically connecting the gate driver circuit and the pixel circuit is reduced to one-eighth, which reduces the resistance and parasitic capacitance of the wiring GL to one-eighth, improving signal degradation and delay and making it easier to ensure sufficient time for rewriting image data.

[0232] According to the display device 10B of one embodiment of the present invention, it is easy to ensure sufficient time for writing image data, and therefore high-speed rewriting of the displayed image can be realized. As a result, a display device with high display quality can be realized, and in particular, a display device with excellent moving image display can be realized.

[0233] <Variation 2> Figures 21A and 21B show perspective views of a display device 10C, which is a variation of the display device 10A. Note that the display device 10C is also a variation of the display device 10B. Figure 21B is a perspective view for explaining the configuration of each layer of the display device 10C. To reduce repetition of explanation, differences from the display device 10A and the display device 10B will be mainly explained.

[0234] The pixel circuit group 55 including a plurality of pixel circuits 51, the drive circuit 30, the functional circuit 40, and the terminal section 14 may be provided on the same layer. The display device 10C has the pixel circuit group 55, the drive circuit 30, the functional circuit 40, and the terminal section 14 provided on the layer 20. By providing the pixel circuit group 55, the drive circuit 30, and the functional circuit 40 on the same layer, the wiring electrically connecting them can be shortened. This reduces wiring resistance and parasitic capacitance, and reduces power consumption.

[0235] For example, when c-Si transistors are used as the transistors used in the display device 10C, a single-crystal silicon substrate can be used as the layer 20 to provide the pixel circuit group 55, the drive circuit 30, the function circuit 40, and the terminal portion 14. Furthermore, by using a single-crystal silicon substrate as the layer 20, the substrate 11 can be omitted. This allows the weight of the display device 10C to be reduced. Furthermore, this allows the production cost of the display device 10C to be reduced. This improves the productivity of the display device 10C.

[0236] Note that the transistors used in the display device 10C are not limited to c-Si transistors, and various transistors such as poly-Si transistors or OS transistors can be used as the transistors used in the display device 10C.

[0237] In addition, in the display device 10C shown in Fig. 21, the display unit 13 is composed of sub-display units 19 arranged in a matrix of m rows and n columns. Therefore, the pixel circuit group 55 is divided into sections 59 arranged in a matrix of m rows and n columns. Fig. 22 shows a planar layout of the layer 20. Fig. 22 shows the sections 59 when m is 4 and n is 8.

[0238] In the display device 10C, the drive circuit 30 is divided into four regions: drive circuit 30a, drive circuit 30b, drive circuit 30c, and drive circuit 30d. The drive circuits 30a, 30b, 30c, and 30d are provided outside the pixel circuit group 55. Specifically, of the four sides of the periphery of the pixel circuit group 55, the drive circuit 30a is provided on a first side, the drive circuit 30c is provided on a third side facing the first side across the pixel circuit group 55, the drive circuit 30b is provided on a second side, and the drive circuit 30d is provided on a fourth side facing the second side across the pixel circuit group 55.

[0239] The drive circuit 30a and the drive circuit 30c each have 16 gate driver circuits 33. The drive circuit 30b and the drive circuit 30d each have 16 source driver circuits 31. One of the gate driver circuits 33 is electrically connected to a plurality of pixel circuits 51 included in one of the sections 59. One of the source driver circuits 31 is electrically connected to a plurality of pixel circuits 51 included in one of the sections 59.

[0240] 22, the gate driver circuit 33 electrically connected to the section 59[1,1] is indicated as gate driver circuit 33[1,1], and the source driver circuit 31 electrically connected to the section 59[1,1] is indicated as source driver circuit 31[1,1]. Similarly, the gate driver circuit 33 electrically connected to the section 59[4,8] is indicated as gate driver circuit 33[4,8], and the source driver circuit 31 electrically connected to the section 59[4,8] is indicated as source driver circuit 31[4,8].

[0241] The driver circuit 30a includes gate driver circuits 33[1,1] to 33[1,4], gate driver circuits 33[2,1] to 33[2,4], gate driver circuits 33[3,1] to 33[3,4], and gate driver circuits 33[4,1] to 33[4,4]. The driver circuit 30b includes source driver circuits 31[1,1] to 31[1,8] and source driver circuits 31[2,1] to 31[2,8]. The driver circuit 30c includes gate driver circuits 33[1,5] to 33[1,8], gate driver circuits 33[2,5] to 33[2,8], gate driver circuits 33[3,5] to 33[3,8], and gate driver circuits 33[4,5] to 33[4,8]. The driver circuit 30d includes source driver circuits 31[3,1] to 31[3,8] and source driver circuits 31[4,1] to 31[4,8].

[0242] The arrangement of the pixel circuit group 55, the drive circuit 30, and the function circuit 40 provided in the layer 20 is not limited to the configuration shown in Fig. 22 . For example, the configuration shown in Fig. 23 may be used. In Fig. 23 , the drive circuit 30 is divided into two regions, a drive circuit 30a and a drive circuit 30b. For example, the drive circuit 30a is provided with 32 gate driver circuits 33 (gate driver circuit 33[1,1] to gate driver circuit 33[4,8]), and the drive circuit 30b is provided with 32 source driver circuits 31 (source driver circuit 31[1,1] to source driver circuit 31[4,8]).

[0243] In the display devices 10B and 10C according to an embodiment of the present invention, the display unit 13 is divided into 32 sub-display units 19. However, the display unit 13 of the display devices 10B and 10C according to an embodiment of the present invention is not limited to 32 divisions, and may be divided into 16, 64, or 128 divisions, for example. Increasing the number of divisions of the display unit 13 can further reduce the actual degradation in display quality perceived by the user.

[0244] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be appropriately combined with other configuration examples or drawings.

[0245] (Embodiment 2) In this embodiment, an example of the configuration of a sub-display section 19 having a plurality of pixels 230 arranged in a matrix of p rows and q columns (p and q are each an integer of 2 or greater) will be described. Fig. 24A is a block diagram illustrating the sub-display section 19. The sub-display section 19 is electrically connected to a source driver circuit 31 and a gate driver circuit 33 provided in a section 39.

[0246] In Figure 24A, pixel 230 in the pth row and 1st column is shown as pixel 230[p,1], pixel 230 in the 1st row and qth column is shown as pixel 230[1,q], and pixel 230 in the pth row and qth column is shown as pixel 230[p,q].

[0247] The circuit included in the gate driver circuit 33 functions as, for example, a scanning line driving circuit, and the circuit included in the source driver circuit 31 functions as, for example, a signal line driving circuit.

[0248] For example, an OS transistor may be used as a transistor forming the pixel 230, and a Si transistor may be used as a transistor forming the driver circuit. OS transistors have low off-state current, which allows for reduced power consumption. Furthermore, Si transistors have a higher operating speed than OS transistors, so they are suitable for use in the driver circuit. Depending on the display device, OS transistors may be used as both the transistor forming the pixel 230 and the transistor forming the driver circuit. Depending on the display device, Si transistors may be used as both the transistor forming the pixel 230 and the transistor forming the driver circuit. Depending on the display device, Si transistors may be used as the transistor forming the pixel 230, and OS transistors may be used as the transistor forming the driver circuit.

[0249] Furthermore, both Si transistors and OS transistors may be used as transistors forming the pixel 230. Furthermore, both Si transistors and OS transistors may be used as transistors forming a driver circuit.

[0250] 24A also shows p wirings GL arranged substantially in parallel and whose potentials are controlled by the gate driver circuit 33, and q wirings SL arranged substantially in parallel and whose potentials are controlled by the source driver circuit 31. For example, a pixel 230 arranged in the rth row (r represents any number and is an integer of 1 to p in this embodiment and the like) is electrically connected to the gate driver circuit 33 via the rth wiring GL. A pixel 230 arranged in the sth column (s represents any number and is an integer of 1 to q in this embodiment and the like) is electrically connected to the source driver circuit 31 via the sth wiring SL.

[0251] Note that the number of wirings GL electrically connected to the pixels 230 included in one row is not limited to one. Also, the number of wirings SL electrically connected to the pixels 230 included in one column is not limited to one. Also, the wirings GL and SL are just an example, and the wirings connected to the pixels 230 are not limited to the wirings GL and SL.

[0252] A full-color display can be achieved by arranging a pixel 230 that controls red light, a pixel 230 that controls green light, and a pixel 230 that controls blue light in a striped pattern, collectively functioning as a single pixel 240, and controlling the light emission amount (light emission brightness) of each pixel 230. In other words, each of the three pixels 230 functions as a sub-pixel. That is, each of the three sub-pixels controls the light emission amount of red light, green light, or blue light (see FIG. 24B1). Note that the light colors controlled by each of the three sub-pixels are not limited to a combination of red (R), green (G), and blue (B), but may also be cyan (C), magenta (M), and yellow (Y) (see FIG. 24B2).

[0253] When the pixels 240 are arranged in a 1920 x 1080 matrix, the display unit 13 can be realized as a full-color display at so-called 2K resolution. Furthermore, when the pixels 240 are arranged in a 3840 x 2160 matrix, for example, the display unit 13 can be realized as a full-color display at so-called 4K resolution. Furthermore, when the pixels 240 are arranged in a 7680 x 4320 matrix, for example, the display unit 13 can be realized as a full-color display at so-called 8K resolution. By increasing the number of pixels 240, it is also possible to realize a display unit 13 that can be realized as a full-color display at 16K or even 32K resolution.

[0254] Furthermore, the three pixels 230 constituting one pixel 240 may be arranged in a delta arrangement (see FIG. 24B3). Specifically, the three pixels 230 constituting one pixel 240 may be arranged so that the line connecting the center points of each pixel 230 forms a triangle. Note that the arrangement of the pixels 230 is not limited to the stripe arrangement and the delta arrangement. The arrangement of the pixels 230 may also be a zigzag arrangement, an S-stripe arrangement, a Bayer arrangement, or a Pentile arrangement.

[0255] Furthermore, the areas of the three sub-pixels (pixels 230) do not have to be the same. If the luminous efficiency and reliability differ depending on the luminous color, the area of ​​the sub-pixel may be changed for each luminous color (see FIG. 24B4).

[0256] Alternatively, four subpixels may be combined to function as one pixel. For example, a subpixel that controls white light may be added to three subpixels that control red, green, and blue light, respectively (see FIG. 24B5). Adding a subpixel that controls white light can increase the brightness of the display area. Alternatively, a subpixel that controls yellow light may be added to three subpixels that control red, green, and blue light, respectively (see FIG. 24B6). Alternatively, a subpixel that controls white light may be added to three subpixels that control cyan, magenta, and yellow light, respectively (see FIG. 24B7).

[0257] By increasing the number of sub-pixels that function as one pixel and by appropriately combining sub-pixels that control red, green, blue, cyan, magenta, and yellow light, it is possible to improve the reproducibility of intermediate tones, and thus the display quality.

[0258] Furthermore, the display device of one embodiment of the present invention can reproduce color gamuts of various standards, such as the Phase Alternating Line (PAL) standard and the National Television System Committee (NTSC) standard used in television broadcasting, the standard RGB (sRGB) standard and the Adobe RGB standard widely used in display devices used in electronic devices such as personal computers, digital cameras, and printers, and the ITU-R BT.2000 standard used in high definition television (HDTV). It is possible to reproduce the color gamut of standards such as the International Telecommunication Union Radiocommunication Sector Broadcasting Service (Television) 709 (International Telecommunication Union Radiocommunication Sector Broadcasting Service (Television) 709) standard, the Digital Cinema Initiatives P3 (DCI-P3) standard used in digital cinema projection, and the ITU-R BT. 2020 (REC. 2020 (Recommendation 2020)) standard used in UHDTV (Ultra High Definition Television, also known as Super Hi-Vision).

[0259] Furthermore, a pixel 231 including a light receiving element may be provided in one pixel 240. The pixel 240 shown in Fig. 25A has a pixel 230 (G) that emits green light, a pixel 230 (B) that emits blue light, a pixel 230 (R) that emits red light, and a pixel 231 (S) that has a light receiving element arranged in a stripe pattern. Note that in this specification and the like, the pixel 231 is also referred to as an "imaging pixel."

[0260] The light receiving element of the pixel 231 is preferably an element that detects visible light, and more preferably an element that detects one or more of light of colors such as blue, purple, blue-purple, green, yellow-green, yellow, orange, red, etc. The light receiving element of the pixel 231 may also be an element that detects infrared light.

[0261] 25A is a stripe arrangement. When a pixel 231 having a light receiving element detects light of a specific color, it is preferable to arrange a pixel 230 that exhibits light of that color adjacent to the pixel 231, as this can improve detection accuracy.

[0262] 25B shows an example in which a pixel 240 includes three pixels 230 and one pixel 231 arranged in a matrix. In FIG. 25B, a pixel 230 emitting red light is adjacent to a pixel 231 having a light receiving element in the row direction, and a pixel 230 emitting blue light and a pixel 230 emitting green light are adjacent to each other in the row direction, but the present invention is not limited to this.

[0263] The pixel 240 shown in Fig. 25C has a configuration in which a pixel 231 is added to the S-stripe arrangement. The pixel 240 in Fig. 25C has one vertically elongated pixel 230, two horizontally elongated pixels 230, and one horizontally elongated pixel 231. Note that the vertically elongated pixel 230 may be any of R, G, and S, and there is no limitation on the order in which the horizontally elongated sub-pixels are arranged.

[0264] FIG. 25D shows an example in which pixels 240a and 240b are arranged alternately. Pixel 240a includes a pixel 230 that emits blue light, a pixel 230 that emits green light, and a pixel 231 that has a light-receiving element. Pixel 240b includes a pixel 230 that emits red light, a pixel 230 that emits green light, and a pixel 231 that has a light-receiving element. Pixels 240a and 240b are combined to function as a single pixel 240. In FIG. 25D, both pixel 240a and pixel 240b include a pixel 230 that emits green light and a pixel 231, but this is not limiting. By including pixel 231 in both pixel 240a and pixel 240b, the resolution of the captured pixels can be increased.

[0265] 25E shows an example in which a hexagonal close-packed layout is applied to the arrangement of pixels 230 and 231. The hexagonal close-packed layout is preferable because it can increase the aperture ratio of each sub-pixel. Also, FIG. 25E shows an example in which the top surface shape of pixels 230 and 231 is hexagonal.

[0266] The pixel 240 shown in FIG. 25F is an example in which the pixels 230 are arranged in one horizontal row, and the pixel 231 is arranged below them.

[0267] The pixel 240 shown in FIG. 25G is an example in which the pixel 230 and the pixel 230X are arranged in one horizontal row, and the pixel 231 is arranged below them.

[0268] The pixel 230X may be, for example, a pixel 230 that emits infrared light (IR). That is, the pixel 230X has a light-emitting element 61 that emits infrared light (IR). In this case, the pixel 231 preferably has a light-receiving element that detects infrared light. For example, while an image is displayed by the pixel 230 that emits visible light, the pixel 231 can detect reflected infrared light emitted by the sub-pixel X.

[0269] Furthermore, a single pixel 240 may include a plurality of pixels 231. In this case, the wavelength ranges of light detected by the plurality of pixels 231 may be the same or different. For example, some of the plurality of pixels 231 may detect visible light, and other pixels 231 may detect infrared light.

[0270] Furthermore, the pixel 231 does not have to be provided in every pixel 240. A pixel 240 including the pixel 231 may be provided for every certain number of pixels.

[0271] Using the pixel 231, or using the pixel 231 and the above-mentioned sensor 125, it is possible to detect information for personal authentication using, for example, a fingerprint, palm print, iris, retina, pulse shape (including vein shape and artery shape), face, etc. Furthermore, using the pixel 231, or using the pixel 231 and the sensor 125, it is possible to measure the number of times the user blinks, eyelid movement, pupil size, body temperature, pulse rate, oxygen saturation in the blood, etc., and to detect the user's fatigue level, health condition, etc.

[0272] The operation of an electronic device can be realized using the user's gaze movement, the number of blinks, the blink rhythm, and the like. Specifically, using the pixel 231, or using the pixel 231 and the sensor 125, information such as the user's gaze movement, the number of blinks, and the blink rhythm can be detected, and one or a combination of these pieces of information can be used as an operation signal for the electronic device. For example, it is possible to replace blinks with mouse clicks. By detecting the gaze movement and blinks, the user can perform input operations on the electronic device without holding anything in their hands. This improves the operability of the electronic device.

[0273] Furthermore, by providing a plurality of imaging pixels (pixels 231) in the display device 10, the plurality of imaging pixels can be used as the gaze detection unit 102. This allows for a reduction in the number of components of the electronic device, thereby realizing weight reduction, improved productivity, and cost reduction of the electronic device.

[0274] Fig. 26 shows an example of the configuration of the display unit 13 when the pixel 240 includes a pixel 231 having a light receiving element. Fig. 26 is a block diagram illustrating the display unit 13 including the pixel 231. The display unit 13 has a plurality of pixels 240 arranged in a matrix. Fig. 26 illustrates the pixel configuration of Fig. 25F as the pixel 240.

[0275] 26 , the display unit 13 is electrically connected to a first drive unit 141, a second drive unit 143, and a readout unit 142. Specifically, the first drive unit 141 is electrically connected to a plurality of pixels 231 via a plurality of wirings 161. One wiring 161 is electrically connected to a plurality of pixels 231 arranged in one row. In addition, the readout unit 142 is electrically connected to a plurality of pixels 231 via a plurality of wirings 162. One wiring 162 is electrically connected to a plurality of pixels 231 arranged in one column. In addition, the second drive unit 143 is electrically connected to the readout unit 142 via a plurality of wirings 163.

[0276] Note that the wirings connected to one pixel 231 are not limited to the wiring 161 and the wiring 162. Wirings other than the wiring 161 and the wiring 162 may be connected to the pixel 231.

[0277] The first driving unit 141, the readout unit 142, and the second driving unit 143 are electrically connected to the control unit 144. The control unit 144 has a function of controlling the operations of the first driving unit 141, the readout unit 142, and the second driving unit 143.

[0278] The first driving unit 141 has a function of selecting the pixels 231 for each row. The pixels 231 in the row selected by the first driving unit 141 output imaging data to the readout unit 142 via the wiring 162.

[0279] The readout unit 142 holds the imaging data supplied from the pixels 231 and performs noise removal processing, etc. As the noise removal processing, for example, CDS (Correlated Double Sampling) processing, etc. The readout unit 142 may also have a function of amplifying the imaging data, an AD conversion function for the imaging data, etc.

[0280] The second driving section 143 has a function of sequentially selecting the imaging data held in the reading section 142 and outputting the imaging data from the output terminal OUT to the outside.

[0281] As shown in Fig. 24, the plurality of pixels 230 are electrically connected to the source driver circuit 31 and the gate driver circuit 33, but this is not shown in Fig. 26. Also, Fig. 26 shows an example in which one first drive unit 141, one readout unit 142, one second drive unit 143, and a control unit 144 are provided for the display unit 13, but these may be provided for each sub-display unit 19.

[0282] By providing a first drive unit 141, a readout unit 142, a second drive unit 143, and a control unit 144 for each sub-display unit 19, it is possible to slow down the operation speed of the first drive unit 141, the readout unit 142, the second drive unit 143, and the control unit 144 for an area determined not to require imaging, or to stop these operations, thereby reducing the power consumption of the display device.

[0283] Similarly to the source driver circuit 31 and the gate driver circuit 33 , the first driver 141 , the readout unit 142 , the second driver 143 , and the control unit 144 may be provided on the layer 20 .

[0284] 27A is a circuit diagram illustrating an example of the circuit configuration of the pixel 231. The pixel 231 has a light receiving element 71 (also referred to as a "photoelectric conversion element" or an "imaging element") and a pixel circuit 72. Note that in this specification and elsewhere, the pixel circuit 72 may be referred to as an "imaging pixel circuit."

[0285] The pixel circuit 72 includes a transistor 132 and a read circuit 73. The read circuit 73 includes a transistor 133, a transistor 134, a transistor 135, and a capacitor 138. Note that the capacitor 138 need not be provided.

[0286] One electrode (cathode) of the light-receiving element 71 is electrically connected to one of the source or drain of the transistor 132. The other of the source or drain of the transistor 132 is electrically connected to one of the source or drain of the transistor 133. One of the source or drain of the transistor 133 is electrically connected to one electrode of the capacitor 138. One electrode of the capacitor 138 is electrically connected to the gate of the transistor 134. One of the source or drain of the transistor 134 is electrically connected to one of the source or drain of the transistor 135.

[0287] Here, a wiring that connects the other of the source and the drain of the transistor 132, one of the source and the drain of the transistor 133, one electrode of the capacitor 138, and the gate of the transistor 134 is referred to as a node FD. The node FD can function as a charge detection portion.

[0288] The other electrode (anode) of the light-receiving element 71 is electrically connected to the wiring 121. The gate of the transistor 132 is electrically connected to the wiring 127. The other of the source and the drain of the transistor 133 is electrically connected to the wiring 122. The other of the source and the drain of the transistor 134 is electrically connected to the wiring 123. The gate of the transistor 133 is electrically connected to the wiring 126. The gate of the transistor 135 is electrically connected to the wiring 128. The other electrode of the capacitor 138 is electrically connected to a reference potential line such as a GND wiring. The other of the source and the drain of the transistor 135 is electrically connected to the wiring 352.

[0289] The wirings 127, 126, and 128 function as signal lines for controlling the on / off state of each transistor. The wiring 352 functions as an output line.

[0290] 27A is a configuration in which the cathode side of the light-receiving element 71 is electrically connected to the transistor 132, and the node FD can be reset to a high potential. Therefore, the wiring 122 has a high potential (a higher potential than the wiring 121).

[0291] 27A shows a configuration in which the cathode of the light-receiving element 71 is electrically connected to the node FD, but a configuration in which the anode of the light-receiving element 71 is electrically connected to one of the source and the drain of the transistor 132 may be used. In this case, the node FD is reset to a low potential to operate, and therefore the wiring 122 may be set to a low potential (a potential lower than that of the wiring 121).

[0292] The transistor 132 has a function of controlling the potential of the node FD. The transistor 132 is also referred to as a "transfer transistor". The transistor 133 has a function of resetting the potential of the node FD. The transistor 133 is also referred to as a "reset transistor". The transistor 134 functions as a source follower circuit and can output the potential of the node FD as image data to the wiring 352. The transistor 135 has a function of selecting a pixel to output image data. The transistor 134 is also referred to as an "amplification transistor". The transistor 135 is also referred to as a "selection transistor".

[0293] 27B , a plurality of pairs of the light-receiving element 71 and the transistor 132 may be electrically connected to one node FD. That is, a plurality of pairs of the light-receiving element 71 and the transistor 132 may be electrically connected to one read circuit 73.

[0294] By sharing one readout circuit 73 with multiple pairs of light-receiving elements 71 and transistors 132, the area occupied by each pixel 231 can be reduced. This increases the packaging density of the pixels 231. For example, the readout circuit 73 may be formed on layer 20, and the light-receiving elements 71 and transistors 132 may be formed on layer 50. Alternatively, the light-receiving elements 71 may be formed on layer 60.

[0295] 27B , a first pair of a light-receiving element 71 and a transistor 132 are shown as a light-receiving element 71_1 and a transistor 132_1. The gate of the transistor 132_1 is electrically connected to a wiring 127_1. A second pair of a light-receiving element 71 and a transistor 132 are shown as a light-receiving element 71_2 and a transistor 132_2. The gate of the transistor 132_2 is electrically connected to a wiring 127_2. A kth pair (k is an integer greater than or equal to 1) of a light-receiving element 71 and a transistor 132 are shown as a light-receiving element 71_k and a transistor 132_k. The gate of the transistor 132_k is electrically connected to a wiring 127_k.

[0296] In the configuration shown in FIG. 27B , one pair of a light receiving element 71 and a transistor 132 can be considered as one pixel 231. In FIG. 27B , a pixel 231 configured with a light receiving element 71_1 and a transistor 132_1 is shown as pixel 231_1. A pixel 231 configured with a light receiving element 71_2 and a transistor 132_2 is shown as pixel 231_2. A pixel 231 configured with a light receiving element 71_k and a transistor 132_k is shown as pixel 231_k. In the configuration shown in FIG. 27B , the transistor 132 corresponds to the pixel circuit 72.

[0297] <Structure Example of Light-Emitting Element> A light-emitting element 61 that can be used in a display device according to one embodiment of the present invention will be described.

[0298] As shown in FIG. 28A , the light-emitting element 61 includes an EL layer 172 between a pair of electrodes (conductor 171 and conductor 173). The EL layer 172 can be composed of a plurality of layers, such as a layer 4420, a light-emitting layer 4411, and a layer 4430. The layer 4420 can include, for example, a layer containing a substance with high electron injection properties (electron injection layer) and a layer containing a substance with high electron transport properties (electron transport layer). The light-emitting layer 4411 includes, for example, a light-emitting compound. The layer 4430 can include, for example, a layer containing a substance with high hole injection properties (hole injection layer) and a layer containing a substance with high hole transport properties (hole transport layer).

[0299] A structure including the layer 4420, the light-emitting layer 4411, and the layer 4430 provided between a pair of electrodes can function as a single light-emitting unit, and the structure of FIG. 28A is referred to as a single structure in this specification and the like.

[0300] 28B shows a modified example of the EL layer 172 included in the light-emitting element 61 shown in Fig. 28A. Specifically, the light-emitting element 61 shown in Fig. 28B includes a layer 4430-1 on the conductor 171, a layer 4430-2 on the layer 4430-1, a light-emitting layer 4411 on the layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on the layer 4420-1, and a conductor 173 on the layer 4420-2. For example, when the conductor 171 is an anode and the conductor 173 is a cathode, the layer 4430-1 functions as a hole injection layer, the layer 4430-2 functions as a hole transport layer, the layer 4420-1 functions as an electron transport layer, and the layer 4420-2 functions as an electron injection layer. Alternatively, when the conductor 171 is a cathode and the conductor 173 is an anode, the layer 4430-1 functions as an electron injection layer, the layer 4430-2 functions as an electron transport layer, the layer 4420-1 functions as a hole transport layer, and the layer 4420-2 functions as a hole injection layer. Such a layer structure makes it possible to efficiently inject carriers into the light-emitting layer 4411 and increase the efficiency of carrier recombination in the light-emitting layer 4411.

[0301] Note that a structure in which a plurality of light-emitting layers (light-emitting layer 4411, light-emitting layer 4412, light-emitting layer 4413) are provided between layer 4420 and layer 4430 as shown in FIG. 28C is also an example of a single structure.

[0302] 28D , a configuration in which a plurality of light-emitting units (EL layers 172 a and 172 b) are connected in series via an intermediate layer (charge generating layer) 4440 is referred to as a tandem structure or a stack structure in this specification and elsewhere. Note that the tandem structure makes it possible to realize a light-emitting element capable of emitting light with high brightness.

[0303] 28D, the EL layers 172a and 172b may emit light of the same color. For example, the EL layers 172a and 172b may both emit green light.

[0304] Note that a full-color display can be achieved by using a light-emitting element 61 emitting red light (R), a light-emitting element 61 emitting green light (G), and a light-emitting element 61 emitting blue light (B) as sub-pixels to form one pixel. When one pixel includes three types of sub-pixels, R, G, and B, the light-emitting elements 61 may be arranged in tandem. Specifically, the EL layer 172a and the EL layer 172b of the R sub-pixel each contain a material capable of emitting red light, the EL layer 172a and the EL layer 172b of the G sub-pixel each contain a material capable of emitting green light, and the EL layer 172a and the EL layer 172b of the B sub-pixel each contain a material capable of emitting blue light. In other words, the light-emitting layer 4411 and the light-emitting layer 4412 may be made of the same material. By making the EL layer 172a and the EL layer 172b emit the same light, the current density per unit of light emission luminance can be reduced. Therefore, the reliability of the light emitting element 61 can be improved.

[0305] The light-emitting color of the light-emitting element can be red, green, blue, cyan, magenta, yellow, white, or the like, depending on the material constituting the EL layer 172. Furthermore, the color purity can be further improved by providing the light-emitting element with a microcavity structure.

[0306] The light-emitting layer may contain two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. It is preferable that a light-emitting element that emits white light has a configuration in which the light-emitting layer contains two or more types of light-emitting materials. To obtain white light emission, light-emitting materials may be selected such that the respective emissions of the two or more light-emitting materials have a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary colors, a light-emitting element that emits white light as a whole can be obtained. The same applies to a light-emitting element that has three or more light-emitting layers.

[0307] The light-emitting layer preferably contains two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. Alternatively, it is preferable that the light-emitting layer contains two or more light-emitting materials, and the light emitted by each of the light-emitting materials contains spectral components of two or more colors of R, G, and B. Furthermore, a material that emits near-infrared light can also be used as the light-emitting material.

[0308] Examples of the light-emitting substance include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), an inorganic compound (such as a quantum dot material), and a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material).

[0309] <Method of Forming Light-Emitting Element> An example of a method of forming the light-emitting element 61 will be described below.

[0310] FIG. 29A shows a schematic top view of a light-emitting element 61. The light-emitting element 61 includes a plurality of light-emitting elements 61R that emit red light, a plurality of light-emitting elements 61G that emit green light, and a plurality of light-emitting elements 61B that emit blue light. In FIG. 29A, the symbols R, G, and B are assigned within the light-emitting region of each light-emitting element to easily distinguish between the light-emitting elements. Also, while FIG. 29A illustrates a configuration having three emitted light colors, red (R), green (G), and blue (B), this is not limiting. For example, a configuration having four or more colors may also be used.

[0311] The light emitting elements 61R, 61G, and 61B are arranged in a matrix. Fig. 29A shows a so-called stripe arrangement in which light emitting elements of the same color are arranged in one direction, but the arrangement of the light emitting elements is not limited to this.

[0312] As the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B, it is preferable to use an organic EL element such as an OLED (organic light-emitting diode) or a QOLED (quantum-dot organic light-emitting diode). Examples of the light-emitting substance contained in the EL element include a fluorescent substance (fluorescent material), a phosphorescent substance (phosphorescent material), an inorganic compound (such as a quantum dot material), and a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF material).

[0313] FIG. 29B is a schematic cross-sectional view corresponding to the dashed-dotted line A1-A2 in FIG. 29A . FIG. 29B shows cross sections of the light-emitting elements 61R, 61G, and 61B. The light-emitting elements 61R, 61G, and 61B are each provided on an insulator 363 and include a conductor 171 functioning as a pixel electrode and a conductor 173 functioning as a common electrode. The insulator 363 can be an inorganic insulating film or an organic insulating film, or both. It is preferable to use an inorganic insulating film as the insulator 363. Examples of inorganic insulating films include oxide insulating films and nitride insulating films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film.

[0314] The light-emitting element 61R has an EL layer 172R between a conductor 171 functioning as a pixel electrode and a conductor 173 functioning as a common electrode. The EL layer 172R contains a light-emitting organic compound that emits light having an intensity at least in the red wavelength range. The EL layer 172G of the light-emitting element 61G contains a light-emitting organic compound that emits light having an intensity at least in the green wavelength range. The EL layer 172B of the light-emitting element 61B contains a light-emitting organic compound that emits light having an intensity at least in the blue wavelength range.

[0315] The EL layer 172R, the EL layer 172G, and the EL layer 172B may each have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in addition to a layer containing a light-emitting organic compound (light-emitting layer).

[0316] The conductor 171 functioning as a pixel electrode is provided for each light-emitting element. The conductor 173 functioning as a common electrode is provided as a continuous layer common to each light-emitting element. A conductive film that is transparent to visible light is used for either the conductor 171 functioning as a pixel electrode or the conductor 173 functioning as a common electrode, and a conductive film that is reflective is used for the other. By making the conductor 171 functioning as a pixel electrode transparent and the conductor 173 functioning as a common electrode reflective, a bottom-emission display device can be obtained. Conversely, by making the conductor 171 functioning as a pixel electrode reflective and the conductor 173 functioning as a common electrode transparent, a top-emission display device can be obtained. Note that by making both the conductor 171 functioning as a pixel electrode and the conductor 173 functioning as a common electrode light-transmitting, a dual-emission display device can also be obtained.

[0317] For example, when the light-emitting element 61R is a top-emission type, the light 175R emitted from the light-emitting element 61R is emitted toward the conductor 173. When the light-emitting element 61R is a top-emission type, the light 175G emitted from the light-emitting element 61G is emitted toward the conductor 173. When the light-emitting element 61B is a top-emission type, the light 175B emitted from the light-emitting element 61B is emitted toward the conductor 173.

[0318] An insulator 272 is provided to cover an end portion of the conductor 171 functioning as a pixel electrode. The end portion of the insulator 272 preferably has a tapered shape. The insulator 272 can be made of a material similar to that of the insulator 363.

[0319] The insulator 272 is provided to prevent erroneous light emission due to unintentional electrical short circuit between adjacent light-emitting elements 61. In addition, when a metal mask is used to form the EL layer 172, the insulator 272 also functions to prevent the metal mask from coming into contact with the conductor 171.

[0320] The EL layer 172R, the EL layer 172G, and the EL layer 172B each have a region in contact with the top surface of the conductor 171 that functions as a pixel electrode, and a region in contact with the surface of the insulator 272. Ends of the EL layer 172R, the EL layer 172G, and the EL layer 172B are located on the insulator 272.

[0321] As shown in Figure 29B, a gap is provided between two EL layers between light-emitting elements of different colors. In this manner, it is preferable that the EL layers 172R, 172G, and 172G are arranged so as not to contact each other. This can effectively prevent current from flowing through two adjacent EL layers, resulting in unintended light emission (also known as crosstalk). This can improve contrast and realize a display device with high display quality.

[0322] The EL layer 172R, the EL layer 172G, and the EL layer 172G can be separately formed by a vacuum deposition method using a shadow mask such as a metal mask. Alternatively, they may be separately formed by a photolithography method. By using the photolithography method, it is possible to realize a high-definition display device that is difficult to achieve when using a metal mask.

[0323] In this specification and the like, a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification and the like, a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure. Because a display device with an MML structure is fabricated without using a metal mask, it has a higher degree of design freedom in terms of pixel arrangement, pixel shape, and the like than a display device with an MM structure.

[0324] In addition, a protective layer 271 is provided on the conductor 173, which functions as a common electrode, to cover the light-emitting elements 61R, 61G, and 61B. The protective layer 271 has a function of preventing impurities such as water from diffusing from above into each light-emitting element.

[0325] The protective layer 271 may have, for example, a single-layer structure or a stacked structure including at least an inorganic insulating film. Examples of inorganic insulating films include oxide films or nitride films such as silicon oxide films, silicon oxynitride films, silicon nitride oxide films, silicon nitride films, aluminum oxide films, aluminum oxynitride films, and hafnium oxide films. Alternatively, semiconductor materials such as indium gallium oxide and indium gallium zinc oxide (IGZO) may be used for the protective layer 271. Note that the protective layer 271 may be formed using an ALD method, a CVD method, or a sputtering method. Note that, although the protective layer 271 includes an inorganic insulating film, this is not limiting. For example, the protective layer 271 may have a stacked structure including an inorganic insulating film and an organic insulating film.

[0326] In this specification, "nitride oxide" refers to a compound containing more nitrogen than oxygen. "oxynitride" refers to a compound containing more oxygen than nitrogen. The content of each element can be measured, for example, by Rutherford backscattering spectrometry (RBS).

[0327] When indium gallium zinc oxide is used as the protective layer 271, it can be processed by wet etching or dry etching. For example, when IGZO is used as the protective layer 271, a chemical solution such as oxalic acid, phosphoric acid, or a mixed chemical solution (for example, a mixed chemical solution of phosphoric acid, acetic acid, nitric acid, and water (also referred to as a mixed acid aluminum etching solution)) can be used. Note that the mixed acid aluminum etching solution can have a volume ratio of phosphoric acid:acetic acid:nitric acid:water=53.3:6.7:3.3:36.7 or a similar ratio.

[0328] The structure shown in FIG. 29B may be referred to as an SBS structure, which will be described later.

[0329] 29C shows a different example. Specifically, Fig. 29C shows a light-emitting element 61W that emits white light. The light-emitting element 61W has an EL layer 172W that emits white light between a conductor 171 that functions as a pixel electrode and a conductor 173 that functions as a common electrode.

[0330] The EL layer 172W may be configured by stacking two or more light-emitting layers selected so that the emitted light colors are complementary to each other. Alternatively, a stacked EL layer may be used in which a charge generating layer is sandwiched between the light-emitting layers.

[0331] 29C shows three light-emitting elements 61W lined up. A colored layer 264R is provided on the top of the left light-emitting element 61W. The colored layer 264R functions as a bandpass filter that transmits red light. Similarly, a colored layer 264G that transmits green light is provided on the top of the center light-emitting element 61W, and a colored layer 264B that transmits blue light is provided on the top of the right light-emitting element 61W. This allows the display device to display color images.

[0332] Here, the EL layer 172W and the conductor 173 functioning as a common electrode are separated between two adjacent light-emitting elements 61W. This prevents unintended light emission due to current flowing through the EL layer 172W between the two adjacent light-emitting elements 61W. In particular, when a stacked EL layer in which a charge generation layer is provided between two light-emitting layers is used as the EL layer 172W, the higher the resolution, i.e., the smaller the distance between adjacent pixels, the more pronounced the effect of crosstalk becomes, resulting in a decrease in contrast. Therefore, by using this configuration, a display device that combines high resolution and high contrast can be realized.

[0333] The separation of the EL layer 172W and the conductor 173 functioning as a common electrode is preferably performed by photolithography, which allows the spacing between the light-emitting elements to be narrowed, thereby achieving a display device with a higher aperture ratio than when a shadow mask such as a metal mask is used.

[0334] In the case of a bottom-emission light-emitting element, a colored layer may be provided between the conductor 171 functioning as a pixel electrode and the insulator 363 .

[0335] FIG. 29D shows an example different from the above. Specifically, FIG. 29D shows a configuration in which an insulator 272 is not provided between the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B. This configuration allows a display device with a high aperture ratio. Furthermore, by not providing the insulator 272, the unevenness of the light-emitting element 61 is reduced, thereby improving the viewing angle of the display device. Specifically, the viewing angle can be set to 150° or more and less than 180°, preferably 160° or more and less than 180°.

[0336] Furthermore, the protective layer 271 covers the side surfaces of the EL layer 172R, the EL layer 172G, and the EL layer 172B. This configuration can suppress impurities (typically, water, etc.) that can enter from the side surfaces of the EL layer 172R, the EL layer 172G, and the EL layer 172B. Furthermore, since leakage current between adjacent light-emitting elements 61 is reduced, the color saturation and contrast ratio are improved and power consumption is reduced.

[0337] 29D , the top surfaces of the conductor 171, the EL layer 172R, and the conductor 173 are generally the same. This structure can be formed all at once using a resist mask or the like after the conductor 171, the EL layer 172R, and the conductor 173 are formed. This process can also be called self-aligned patterning, since the EL layer 172R and the conductor 173 are processed using the conductor 173 as a mask. Note that although the EL layer 172R has been described here, the EL layer 172G and the EL layer 172B can also be configured in a similar manner.

[0338] 29D shows a structure in which a protective layer 273 is further provided on the protective layer 271. For example, the protective layer 271 may be formed using an apparatus (typically, an ALD apparatus) capable of depositing a film with high coverage, and the protective layer 273 may be formed using an apparatus (typically, a sputtering apparatus) capable of depositing a film with lower coverage than the protective layer 271, thereby providing a region 275 between the protective layer 271 and the protective layer 273. In other words, the region 275 is located between the EL layer 172R and the EL layer 172G, and between the EL layer 172G and the EL layer 172B.

[0339] The region 275 contains, for example, one or more elements selected from air, nitrogen, oxygen, carbon dioxide, and Group 18 elements (typically, helium, neon, argon, xenon, krypton, etc.). The region 275 may also contain, for example, a gas used when forming the protective layer 273. For example, when the protective layer 273 is formed by sputtering, the region 275 may contain one or more of the above Group 18 elements. When the region 275 contains a gas, the gas can be identified by gas chromatography or the like. When the protective layer 273 is formed by sputtering, the gas used during sputtering may also be contained in the protective layer 273. In this case, elements such as argon may be detected when the protective layer 273 is analyzed by energy dispersive X-ray analysis (EDX analysis) or the like.

[0340] Furthermore, if the refractive index of region 275 is lower than the refractive index of protective layer 271, light emitted from EL layer 172R, EL layer 172G, or EL layer 172B is reflected at the interface between protective layer 271 and region 275. This may prevent light emitted from EL layer 172R, EL layer 172G, or EL layer 172B from entering adjacent pixels. This prevents light of different colors from being mixed in with neighboring pixels, thereby improving the display quality of the display device.

[0341] 29D , the area between light-emitting element 61R and light-emitting element 61G or the area between light-emitting element 61G and light-emitting element 61B (hereinafter simply referred to as the distance between the light-emitting elements) can be narrowed. Specifically, the distance between the light-emitting elements can be set to 1 μm or less, preferably 500 nm or less, and more preferably 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. In other words, the distance between the side surface of EL layer 172R and the side surface of EL layer 172G or the distance between the side surface of EL layer 172G and the side surface of EL layer 172B has an area of ​​1 μm or less, preferably an area of ​​0.5 μm (500 nm) or less, and more preferably an area of ​​100 nm or less.

[0342] Furthermore, for example, when the region 275 contains gas, it is possible to isolate the light emitting elements while suppressing color mixing or crosstalk of light from each light emitting element.

[0343] The region 275 may be empty or filled with a filler. Examples of the filler include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Photoresist may also be used as the filler. The photoresist used as the filler may be a positive photoresist or a negative photoresist.

[0344] FIG. 30A shows a different example from the above. Specifically, the configuration shown in FIG. 30A differs from the configuration shown in FIG. 29D in the configuration of the insulator 363. The insulator 363 has a recess formed by removing a portion of its upper surface during processing of the light-emitting elements 61R, 61G, and 61B. A protective layer 271 is formed in the recess. In other words, the insulator 363 has a region where the lower surface of the protective layer 271 is located lower than the lower surface of the conductor 171 in a cross-sectional view. By providing this region, impurities (typically, water, etc.) that may enter the light-emitting elements 61R, 61G, and 61B from below can be suitably suppressed. The recess can be formed when impurities (also referred to as residue) that may adhere to the side surfaces of the light-emitting elements 61R, 61G, and 61B are removed by wet etching or the like during processing. After removing the residue, the side surfaces of the light-emitting elements are covered with the protective layer 271, resulting in a highly reliable display device.

[0345] FIG. 30B illustrates a different example. Specifically, the configuration illustrated in FIG. 30B includes an insulator 276 and a microlens array 277 in addition to the configuration illustrated in FIG. 30A . The insulator 276 functions as an adhesive layer. When the refractive index of the insulator 276 is lower than that of the microlens array 277, the microlens array 277 can focus the light emitted from the light-emitting elements 61R, 61G, and 61B. This improves the light extraction efficiency of the display device. This is particularly advantageous because it allows a bright image to be viewed when a user views the display surface from directly in front of the display surface. The insulator 276 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet-curable adhesive), a reactive-curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, materials with low moisture permeability, such as epoxy resin, are preferred. Two-component resins may also be used. Adhesive sheets may also be used.

[0346] FIG. 30C also shows a different example. Specifically, the configuration shown in FIG. 30C has three light-emitting elements 61W instead of the light-emitting elements 61R, 61G, and 61B in the configuration shown in FIG. 30A. An insulator 276 is provided above the three light-emitting elements 61W, and coloring layers 264R, 264G, and 264B are provided above the insulator 276. Specifically, a coloring layer 264R that transmits red light is provided at a position overlapping the left light-emitting element 61W, a coloring layer 264G that transmits green light is provided at a position overlapping the center light-emitting element 61W, and a coloring layer 264B that transmits blue light is provided at a position overlapping the right light-emitting element 61W. This allows the semiconductor device to display a color image. The configuration shown in FIG. 30C is also a variation of the configuration shown in FIG. 29C.

[0347] Fig. 30D shows an example different from the above. Specifically, in the configuration shown in Fig. 30D, protective layer 271 is provided adjacent to the side surfaces of conductor 171 and EL layer 172. Conductor 173 is provided as a continuous layer common to each light-emitting element. In the configuration shown in Fig. 30D, region 275 is preferably filled with a filler material.

[0348] The color purity of the emitted color can be increased by providing a micro-optical resonator (microcavity) structure to the light-emitting element 61. To provide the light-emitting element 61 with a microcavity structure, the product (optical path) of the distance d between the conductors 171 and 173 and the refractive index n of the EL layer 172 should be configured to be m times half the wavelength λ (m is an integer of 1 or greater). The distance d can be calculated using Equation 1.

[0349] d = m × λ / (2 × n)... Equation 1.

[0350] According to Equation 1, the distance d of the light-emitting element 61 having the microcavity structure is determined according to the wavelength (emission color) of the emitted light. The distance d corresponds to the thickness of the EL layer 172. Therefore, the EL layer 172G may be provided thicker than the EL layer 172B, and the EL layer 172R may be provided thicker than the EL layer 172G.

[0351] Strictly speaking, the distance d is the distance from the reflective region of the conductor 171, which functions as a reflective electrode, to the reflective region of the conductor 173, which functions as an electrode (semi-transmissive / semi-reflective electrode) that is transparent and reflective to the emitted light. For example, if the conductor 171 is a laminate of silver and a transparent conductive film, ITO (Indium Tin Oxide), and the ITO is on the EL layer 172 side, the distance d can be set according to the emitted color by adjusting the film thickness of the ITO. In other words, even if the thicknesses of the EL layers 172R, 172G, and 172B are the same, the distance d appropriate for the emitted color can be obtained by changing the thickness of the ITO.

[0352] However, it may be difficult to precisely determine the positions of the reflection regions in the conductors 171 and 173. In this case, it is assumed that the microcavity effect can be fully obtained by assuming that any position in the conductors 171 and 173 is the reflection region.

[0353] The light-emitting element 61 is composed of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, etc. Detailed configuration examples of the light-emitting element 61 will be described in other embodiments. In order to increase the light extraction efficiency in the microcavity structure, it is preferable to set the optical distance from the conductor 171 functioning as a reflective electrode to the light-emitting layer to an odd multiple of λ / 4. To achieve this optical distance, it is preferable to appropriately adjust the thickness of each layer constituting the light-emitting element 61.

[0354] Furthermore, when light is emitted from the conductor 173 side, it is preferable that the reflectance of the conductor 173 is greater than the transmittance. The light transmittance of the conductor 173 is preferably 2% or more and 50% or less, more preferably 2% or more and 30% or less, and even more preferably 2% or more and 10% or less. By reducing the transmittance of the conductor 173 (increasing the reflectance), the effect of the microcavity can be enhanced.

[0355] Fig. 31A shows an example different from the above. Specifically, in the configuration shown in Fig. 31A, the EL layer 172 extends beyond the end of the conductor 171 in each of the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B. For example, in the light-emitting element 61R, the EL layer 172R extends beyond the end of the conductor 171. In the light-emitting element 61G, the EL layer 172G extends beyond the end of the conductor 171. In the light-emitting element 61B, the EL layer 172B extends beyond the end of the conductor 171.

[0356] In each of the light-emitting elements 61R, 61G, and 61B, the EL layer 172 and the protective layer 271 have an overlapping region with the insulator 270 interposed therebetween. In addition, in the region between adjacent light-emitting elements 61, an insulator 278 is provided on the protective layer 271.

[0357] Examples of the insulator 278 include epoxy resin, acrylic resin, silicone resin, phenol resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Photoresist may also be used as the insulator 278. The photoresist used as the insulator 278 may be a positive photoresist or a negative photoresist.

[0358] Furthermore, a common layer 174 is provided on the light-emitting elements 61R, 61G, and 61B and the insulator 278, and a conductor 173 is provided on the common layer 174. The common layer 174 has a region in contact with the EL layer 172R, a region in contact with the EL layer 172G, and a region in contact with the EL layer 172B. The common layer 174 is shared by the light-emitting elements 61R, 61G, and 61B.

[0359] The common layer 174 may be one or more of a hole injection layer, a hole transport layer, a hole blocking layer, an electron blocking layer, an electron transport layer, and an electron injection layer. For example, the common layer 174 may be a carrier injection layer (hole injection layer or electron injection layer). The common layer 174 can also be said to be a part of the EL layer 172. Note that the common layer 174 may be provided as needed. When the common layer 174 is provided, it is not necessary to provide a layer having the same function as the common layer 174 among the layers included in the EL layer 172.

[0360] In addition, a protective layer 273 is provided over the conductor 173 , and an insulator 276 is provided over the protective layer 273 .

[0361] FIG. 31B also shows an example different from the above. Specifically, the configuration shown in FIG. 31B has three light-emitting elements 61W instead of the light-emitting elements 61R, 61G, and 61B in the configuration shown in FIG. 31A. An insulator 276 is provided above the three light-emitting elements 61W, and coloring layers 264R, 264G, and 264B are provided above the insulator 276. Specifically, a coloring layer 264R that transmits red light is provided at a position overlapping the left light-emitting element 61W, a coloring layer 264G that transmits green light is provided at a position overlapping the center light-emitting element 61W, and a coloring layer 264B that transmits blue light is provided at a position overlapping the right light-emitting element 61W. This allows the semiconductor device to display a color image. The configuration shown in FIG. 31B is also a variation of the configuration shown in FIG. 30C.

[0362] 31C, a light-emitting element 61R, a light-emitting element 61G, and a light-receiving element 71 may be provided on an insulator 363. The light-receiving element 71 shown in FIG. 31C can be realized by replacing the EL layer 172 of the light-emitting element 61 with an active layer 182 (also referred to as a "light-receiving layer") that functions as a photoelectric conversion layer. The active layer 182 has a characteristic that its resistance value changes depending on the wavelength and intensity of incident light. The active layer 182 can be formed of an organic compound, similar to the EL layer 172. Note that the active layer 182 may also be made of an inorganic material such as silicon.

[0363] The light receiving element 71 has a function of detecting light Lin incident from outside the display device through the protective layer 273, the conductor 173, and the common layer 174. A colored layer that transmits light in a desired wavelength range may be provided on the incident side of the light receiving element 71, overlapping the light receiving element 71.

[0364] <Materials Applicable to Light-Emitting and Light-Receiving Elements> Materials applicable to light-emitting elements and light-receiving elements will be described.

[0365] The hole injection layer is a layer that injects holes from the anode into the hole transport layer and contains a material with high hole injection properties, such as an aromatic amine compound and a composite material containing a hole transport material and an acceptor material (electron acceptor material).

[0366] The hole transport layer is a layer that transports holes injected from the anode by the hole injection layer to the light emitting layer. The hole transport layer is a layer that contains a hole transport material. The hole transport material is a material having a concentration of 1×10 −６ cm ２ A substance having a hole mobility of 1 / Vs or more is preferred. Note that other substances can also be used as long as they have a higher hole transporting property than electron transporting property. As the hole transporting material, a material having a high hole transporting property, such as a π-electron-rich heteroaromatic compound (e.g., a carbazole derivative, a thiophene derivative, a furan derivative, etc.) or an aromatic amine (a compound having an aromatic amine skeleton), is preferred.

[0367] The electron transport layer is a layer that transports electrons injected from the cathode by the electron injection layer to the light emitting layer. The electron transport layer is a layer that contains an electron transporting material. The electron transporting material is a material having a molecular weight of 1×10 −６ cm ２A substance having an electron mobility of 1 / Vs or more is preferred. Note that other substances can also be used as long as they have a higher electron transporting property than holes. Examples of electron-transporting materials that can be used include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, and metal complexes having a thiazole skeleton, as well as oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives having a quinoline ligand, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, and other π-electron-deficient heteroaromatic compounds including nitrogen-containing heteroaromatic compounds.

[0368] The electron injection layer is a layer that injects electrons from the cathode to the electron transport layer and contains a material with high electron injection properties. Examples of the material with high electron injection properties include alkali metals, alkaline earth metals, and compounds thereof. Examples of the material with high electron injection properties include a composite material containing an electron transport material and a donor material (electron donor material).

[0369] The electron injection layer may be formed of, for example, lithium, cesium, ytterbium, lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF ｘ , x is an arbitrary number), 8-(quinolinolato)lithium (abbreviation: Liq), 2-(2-pyridyl)phenolatolithium (abbreviation: LiPP), 2-(2-pyridyl)-3-pyridinolatolithium (abbreviation: LiPPy), 4-phenyl-2-(2-pyridyl)phenolatolithium (abbreviation: LiPPP), lithium oxide (LiO ｘ ), alkali metals such as cesium carbonate, alkaline earth metals, or compounds thereof can be used. The electron injection layer may have a stacked structure of two or more layers. For example, the stacked structure may have a structure in which lithium fluoride is used in the first layer and ytterbium is used in the second layer.

[0370] Alternatively, an electron transporting material may be used for the electron injection layer. For example, a compound having an unshared electron pair and an electron-deficient heteroaromatic ring may be used as the electron transporting material. Specifically, a compound having at least one of a pyridine ring, a diazine ring (pyrimidine ring, pyrazine ring, pyridazine ring), and a triazine ring may be used.

[0371] The organic compound having an unshared electron pair preferably has a lowest unoccupied molecular orbital (LUMO) of -3.6 eV to -2.3 eV. Generally, the highest occupied molecular orbital (HOMO) level and the LUMO level of an organic compound can be estimated by cyclic voltammetry (CV), photoelectron spectroscopy, optical absorption spectroscopy, inverse photoelectron spectroscopy, or the like.

[0372] For example, 4,7-diphenyl-1,10-phenanthroline (abbreviation: BPhen), 2,9-di(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviation: NBPhen), diquinoxalino[2,3-a:2',3'-c]phenazine (abbreviation: HATNA), 2,4,6-tris[3'-(pyridin-3-yl)biphenyl-3-yl]-1,3,5-triazine (abbreviation: TmPPPyTz), etc. can be used as the organic compound having an unshared electron pair. Note that NBPhen has a higher glass transition point (Tg) and is superior in heat resistance compared to BPhen.

[0373] The light-receiving element has an active layer that functions as at least a photoelectric conversion layer between a pair of electrodes. In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.

[0374] Of the pair of electrodes that a light-receiving element has, one electrode functions as an anode and the other electrode functions as a cathode. The following description will be given taking as an example a case where the pixel electrode functions as the anode and the common electrode functions as the cathode. The light-receiving element can detect light incident on the light-receiving element, generate charge, and extract it as a current by applying a reverse bias between the pixel electrode and the common electrode. Alternatively, the pixel electrode may function as a cathode and the common electrode may function as an anode.

[0375] The active layer of the light-receiving element includes a semiconductor. Examples of the semiconductor include inorganic semiconductors such as silicon and organic semiconductors containing organic compounds. In this embodiment, an example in which an organic semiconductor is used as the semiconductor of the active layer is shown. By using an organic semiconductor, the light-emitting layer and the active layer can be formed by the same method (for example, vacuum deposition), which is preferable because it allows the use of a common manufacturing device.

[0376] The n-type semiconductor material of the active layer is fullerene (e.g., C ６０ , C ７０ Examples of electron-accepting organic semiconductor materials include fullerene derivatives and the like. Fullerenes have a soccer ball-like shape, and this shape is energetically stable. Fullerenes have deep (low) HOMO and LUMO levels. Because fullerenes have a deep LUMO level, they have extremely high electron-accepting (acceptor) properties. Normally, when π-electron conjugation (resonance) spreads on a plane, as in benzene, electron-donating (donor) properties increase, but fullerenes have a spherical shape, so they have high electron-accepting properties despite the wide spread π-electron conjugation. High electron-accepting properties cause charge separation quickly and efficiently, making them useful as light-receiving elements. C ６０ , C ７０ Both have a wide absorption band in the visible light region, and C ７０ is C ６０Other fullerene derivatives include [6,6]-Phenyl-C71-butylic acid methyl eSter (abbreviation: PC70BM), [6,6]-Phenyl-C61-butylic acid methyl ester (abbreviation: PC60BM), and 1',1",4',4"-Tetrahydro-di[1,4]methanenaphthaleno[1,2:2',3',56,60:2",3"][5,6]fullerene-C60 (abbreviation: ICBA).

[0377] Furthermore, examples of materials for n-type semiconductors include perylene tetracarboxylic acid derivatives such as N,N'-dimethyl-3,4,9,10-perylene tetracarboxylic acid diimide (abbreviation: Me-PTCDI).

[0378] An example of an n-type semiconductor material is 2,2'-(5,5'-(thieno[3,2-b]thiophene-2,5-diyl)bis(thiophene-5,2-diyl))bis(methane-1-yl-1-ylidene)dimalononitrile (abbreviation: FT2TDMN).

[0379] Examples of n-type semiconductor materials include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, metal complexes having a thiazole skeleton, oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, naphthalene derivatives, anthracene derivatives, coumarin derivatives, rhodamine derivatives, triazine derivatives, and quinone derivatives.

[0380] Examples of the p-type semiconductor material of the active layer include electron-donating organic semiconductor materials such as copper(II) phthalocyanine (CuPc), tetraphenyldibenzoperiflanthene (DBP), zinc phthalocyanine (ZnPc), tin phthalocyanine (SnPc), quinacridone, and rubrene.

[0381] Examples of p-type semiconductor materials include carbazole derivatives, thiophene derivatives, furan derivatives, compounds having an aromatic amine skeleton, etc. Examples of p-type semiconductor materials include naphthalene derivatives, anthracene derivatives, pyrene derivatives, triphenylene derivatives, fluorene derivatives, pyrrole derivatives, benzofuran derivatives, benzothiophene derivatives, indole derivatives, dibenzofuran derivatives, dibenzothiophene derivatives, indolocarbazole derivatives, porphyrin derivatives, phthalocyanine derivatives, naphthalocyanine derivatives, quinacridone derivatives, rubrene derivatives, tetracene derivatives, polyphenylenevinylene derivatives, polyparaphenylene derivatives, polyfluorene derivatives, polyvinylcarbazole derivatives, polythiophene derivatives, etc.

[0382] The HOMO level of the electron-donating organic semiconductor material is preferably shallower (higher) than the HOMO level of the electron-accepting organic semiconductor material, and the LUMO level of the electron-donating organic semiconductor material is preferably shallower (higher) than the LUMO level of the electron-accepting organic semiconductor material.

[0383] It is preferable to use a spherical fullerene as the electron-accepting organic semiconductor material and a planar organic semiconductor material as the electron-donating organic semiconductor material. Molecules with similar shapes tend to aggregate together, and when molecules of the same type aggregate, the energy levels of their molecular orbitals become close, which can improve carrier transport properties.

[0384] For example, the active layer is preferably formed by co-evaporating an n-type semiconductor and a p-type semiconductor, or may be formed by laminating an n-type semiconductor and a p-type semiconductor.

[0385] The light-receiving element may further include, as a layer other than the active layer, a layer containing a substance with high hole-transporting properties, a substance with high electron-transporting properties, a bipolar substance (a substance with high electron-transporting properties and high hole-transporting properties), etc. Furthermore, without being limited to the above, the light-receiving element may further include a layer containing a substance with high hole-injecting properties, a hole-blocking material, a material with high electron-injecting properties, an electron-blocking material, etc.

[0386] The light-receiving element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-receiving element can be formed by a method such as vapor deposition (including vacuum vapor deposition), transfer, printing, inkjet printing, or coating.

[0387] For example, the hole transport material or electron blocking material may be a polymer compound such as poly(3,4-ethylenedioxythiophene) / (polystyrene sulfonic acid) (abbreviated as PEDOT / PSS), or an inorganic compound such as molybdenum oxide or copper iodide (CuI). The electron transport material or hole blocking material may be an inorganic compound such as zinc oxide (ZnO), or an organic compound such as polyethyleneimine ethoxylate (PEIE). The light-receiving element may have, for example, a mixed film of PEIE and ZnO.

[0388] Furthermore, a polymer compound such as Poly[[4,8-bis[5-(2-ethylhexyl)-2-thienyl]benzo[1,2-b:4,5-b']dithiophene-2,6-diyl]-2,5-thiophenediyl[5,7-bis(2-ethylhexyl)-4,8-dioxo-4H,8H-benzo[1,2-c:4,5-c']dithiophene-1,3-diyl]] polymer (abbreviated as PBDB-T) or a PBDB-T derivative, which functions as a donor, can be used in the active layer. For example, a method of dispersing an acceptor material in PBDB-T or a PBDB-T derivative can be used.

[0389] The active layer may also contain a mixture of three or more materials. For example, in order to broaden the wavelength range, a third material may be mixed in addition to an n-type semiconductor material and a p-type semiconductor material. In this case, the third material may be a low-molecular-weight compound or a high-molecular-weight compound.

[0390] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be appropriately combined with other configuration examples or drawings.

[0391] Embodiment 3 In this embodiment, an example of a cross-sectional structure of a display device 10 (a display device 10A, a display device 10B, or a display device 10C) according to one embodiment of the present invention will be described.

[0392] 32 is a cross-sectional view showing an example of the configuration of the display device 10. The display device 10 has a substrate 11 and a substrate 12, and the substrates 11 and 12 are bonded together with a sealant 712.

[0393] The substrate 11 may be, for example, a glass substrate or a single crystal silicon substrate.

[0394] A semiconductor substrate 15 is provided over a substrate 11, and a transistor 445 and a transistor 601 are provided. The transistor 445 and the transistor 601 can be the transistor 21 provided in the layer 20 described in Embodiment 1.

[0395] The transistor 445 includes a conductor 448 functioning as a gate electrode, an insulator 446 functioning as a gate insulator, and a part of the substrate 11, and includes a semiconductor region 447 including a channel formation region, a low-resistance region 449 a functioning as one of a source region and a drain region, and a low-resistance region 449 b functioning as the other of the source region and the drain region. The transistor 445 may be either a p-channel type or an n-channel type.

[0396] The transistor 445 is electrically isolated from other transistors by the element isolation layer 403. Fig. 32 shows a case where the transistor 445 and the transistor 601 are electrically isolated by the element isolation layer 403. The element isolation layer 403 can be formed by a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or the like.

[0397] 32 , a semiconductor region 447 has a convex shape. A conductor 448 is provided to cover the side surface and the top surface of the semiconductor region 447 with an insulator 446 interposed therebetween. Note that the conductor 448 covering the side surface of the semiconductor region 447 is not shown in FIG. A material that adjusts the work function can be used for the conductor 448.

[0398] A transistor having a convex semiconductor region, such as the transistor 445, can be called a fin transistor because it utilizes a convex portion of a semiconductor substrate. Note that an insulator that is in contact with the top of the convex portion and functions as a mask for forming the convex portion may be provided. Also, although FIG. 32 shows a configuration in which the convex portion is formed by processing a part of the substrate 11, a semiconductor having a convex portion may be formed by processing an SOI substrate.

[0399] 32 is just an example, and the transistor 445 is not limited to this configuration and may have an appropriate configuration depending on the circuit configuration, the operation method of the circuit, etc. For example, the transistor 445 may be a planar transistor.

[0400] The transistor 601 can have a structure similar to that of the transistor 445 .

[0401] In addition to the element isolation layer 403, the transistor 445, and the transistor 601, an insulator 405, an insulator 407, an insulator 409, and an insulator 411 are provided on the substrate 11. A conductor 451 is embedded in the insulator 405, the insulator 407, the insulator 409, and the insulator 411. Here, the height of the top surface of the conductor 451 and the height of the top surface of the insulator 411 can be made approximately the same.

[0402] An insulator 421 and an insulator 214 are provided on the conductor 451 and the insulator 411. A conductor 453 is embedded in the insulator 421 and the insulator 214. Here, the height of the top surface of the conductor 453 and the height of the top surface of the insulator 214 can be made approximately the same.

[0403] An insulator 216 is provided on the conductor 453 and the insulator 214. A conductor 455 is embedded in the insulator 216. Here, the height of the top surface of the conductor 455 and the height of the top surface of the insulator 216 can be made approximately the same.

[0404] Insulators 222, 224, 254, 280, 274, and 281 are provided on conductor 455 and insulator 216. Conductor 305 is embedded in insulator 222, insulator 224, insulator 254, insulator 280, insulator 274, and insulator 281. Here, the height of the top surface of conductor 305 and the height of the top surface of insulator 281 can be made approximately the same.

[0405] An insulator 361 is provided on the conductor 305 and the insulator 281. The conductor 317 and the conductor 337 are embedded in the insulator 361. Here, the height of the top surface of the conductor 337 and the height of the top surface of the insulator 361 can be made approximately the same.

[0406] An insulator 363 is provided on the conductor 337 and on the insulator 361. The conductors 347, 353, 355, and 357 are embedded in the insulator 363. Here, the height of the top surfaces of the conductors 353, 355, and 357 can be made approximately the same as the height of the top surface of the insulator 363.

[0407] A connection electrode 760 is provided on the conductor 353, the conductor 355, the conductor 357, and the insulator 363. An anisotropic conductor 780 is provided so as to be electrically connected to the connection electrode 760, and an FPC (Flexible Printed Circuit) 716 is provided so as to be electrically connected to the anisotropic conductor 780. Various signals and the like are supplied to the display device 10 from outside the display device 10 via the FPC 716.

[0408] 32 , the low-resistance region 449b, which functions as the other of the source region and the drain region of the transistor 445, is electrically connected to the FPC 716 through the conductor 451, the conductor 453, the conductor 455, the conductor 305, the conductor 317, the conductor 337, the conductor 347, the conductor 353, the conductor 355, the conductor 357, the connection electrode 760, and the anisotropic conductor 780. Here, in FIG. 32 , the conductor 353, the conductor 355, and the conductor 357 are shown as three conductors each having a function of electrically connecting the connection electrode 760 and the conductor 347, but one embodiment of the present invention is not limited thereto. The number of conductors each having a function of electrically connecting the connection electrode 760 and the conductor 347 may be one, two, or four or more. By providing a plurality of conductors each having a function of electrically connecting the connection electrode 760 and the conductor 347, contact resistance can be reduced.

[0409] A transistor 750 is provided over the insulator 214. The transistor 750 can be the transistor 52 provided in the layer 50 described in Embodiment 1. For example, the transistor 750 can be a transistor provided in the pixel circuit 51. An OS transistor can be suitably used as the transistor 750. An OS transistor has an extremely low off-state current. Therefore, the retention time of image data and the like can be extended, thereby reducing the frequency of a refresh operation. Therefore, the power consumption of the display device 10 can be reduced.

[0410] Conductors 301a and 301b are embedded in the insulators 254, 280, 274, and 281. The conductor 301a is electrically connected to one of the source and the drain of the transistor 750, and the conductor 301b is electrically connected to the other of the source and the drain of the transistor 750. Here, the height of the top surfaces of the conductors 301a and 301b can be made approximately the same as the height of the top surface of the insulator 281.

[0411] The conductors 311, 313, 331, the capacitor 790, the conductor 333, and the conductor 335 are embedded in the insulator 361. The conductors 311 and 313 are electrically connected to the transistor 750 and function as wirings. The conductors 333 and 335 are electrically connected to the capacitor 790. Here, the height of the top surfaces of the conductors 331, 333, and 335 can be made approximately the same as the height of the top surface of the insulator 361.

[0412] The conductors 341, 343, and 351 are embedded in the insulator 363. Here, the height of the top surface of the conductor 351 and the height of the top surface of the insulator 363 can be made to be approximately the same.

[0413] The insulators 405, 407, 409, 411, 421, 214, 280, 274, 281, 361, and 363 each function as an interlayer film and may also function as a planarizing film that covers uneven shapes below the insulators 405, 407, 409, 411, 421, 214, 280, 274, 281, 361, and 363. For example, the top surface of the insulator 363 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0414] As shown in Fig. 32 , the capacitor 790 has a lower electrode 321 and an upper electrode 325. An insulator 323 is provided between the lower electrode 321 and the upper electrode 325. That is, the capacitor 790 has a layered structure in which the insulator 323, which functions as a dielectric, is sandwiched between a pair of electrodes. Note that while Fig. 32 shows an example in which the capacitor 790 is provided on the insulator 281, the capacitor 790 may also be provided on an insulator different from the insulator 281.

[0415] FIG. 32 shows an example in which conductors 301a, 301b, and 305 are formed in the same layer. It also shows an example in which conductors 311, 313, 317, and a lower electrode 321 are formed in the same layer. It also shows an example in which conductors 331, 333, 335, and 337 are formed in the same layer. It also shows an example in which conductors 341, 343, and 347 are formed in the same layer. It also shows an example in which conductors 351, 353, 355, and 357 are formed in the same layer. Forming multiple conductors in the same layer can simplify the manufacturing process of the display device 10, thereby reducing the manufacturing cost of the display device 10. These conductors may be formed in different layers and may be made of different types of materials.

[0416] 32 includes a light-emitting element 61. The light-emitting element 61 includes a conductor 772, an EL layer 786, and a conductor 788. The EL layer 786 includes an organic compound or an inorganic compound such as quantum dots.

[0417] Materials that can be used for the organic compounds include fluorescent materials and phosphorescent materials, while materials that can be used for the quantum dots include colloidal quantum dot materials, alloy quantum dot materials, core-shell quantum dot materials, and core quantum dot materials.

[0418] The conductor 772 is electrically connected to the other of the source and the drain of the transistor 750 through the conductors 351, 341, 331, 313, and 301b. The conductor 772 is formed over the insulator 363 and functions as a pixel electrode.

[0419] A material that is transparent to visible light or a material that is reflective to visible light can be used for the conductor 772. As a light-transmitting material, for example, an oxide material containing indium, zinc, tin, or the like can be used. As a reflective material, for example, a material containing aluminum, silver, or the like can be used.

[0420] Although not shown in FIG. 32, the display device 10 can be provided with optical members (optical substrates) such as a polarizing member, a phase difference member, an anti-reflection member, and the like.

[0421] A light-shielding layer 738 and an insulator 734 in contact with the light-shielding layer 738 are provided on the substrate 12 side. The light-shielding layer 738 has a function of blocking light emitted from an adjacent region. Alternatively, the light-shielding layer 738 has a function of blocking external light from reaching the transistor 750 and the like.

[0422] 32, an insulator 730 is provided over an insulator 363. Here, the insulator 730 can be configured to cover part of a conductor 772. The light-emitting element 61 includes a light-transmitting conductor 788 and can be a top-emission light-emitting element.

[0423] The light-shielding layer 738 is provided to have a region overlapping with the insulator 730. The light-shielding layer 738 is covered with the insulator 734. The space between the light-emitting element 61 and the insulator 734 is filled with the sealing layer 732.

[0424] Furthermore, the structure 778 is provided between the insulator 730 and the EL layer 786. The structure 778 is also provided between the insulator 730 and the insulator 734.

[0425] FIG. 33 shows a modified example of the display device 10 shown in FIG. 32 . The display device 10 shown in FIG. 33 differs from the display device 10 shown in FIG. 32 in that a colored layer 736 is provided. The colored layer 736 is provided so as to have an area overlapping with the light-emitting element 61. By providing the colored layer 736, the color purity of the light extracted from the light-emitting element 61 can be increased. This allows the display device 10 to display a high-quality image. Furthermore, since, for example, all of the light-emitting elements 61 of the display device 10 can be light-emitting elements that emit white light, it is not necessary to form the EL layer 786 by different colors, and the display device 10 can have high definition.

[0426] The light-emitting element 61 can have a micro-optical resonator (microcavity) structure. This allows light of a predetermined color (e.g., RGB) to be extracted without providing a colored layer, and the display device 10 can perform color display. By configuring the display device 10 without providing a colored layer, it is possible to suppress light absorption by the colored layer. This allows the display device 10 to display high-brightness images and reduce the power consumption of the display device 10. Note that even when the EL layer 786 is formed in an island shape for each pixel or in a striped shape for each pixel column, i.e., formed by coloring, a configuration without providing a colored layer can be used. Note that the brightness of the display device 10 can be, for example, 500 cd / m ２ or more, preferably 1000 cd / m ２ More than 10000cd / m ２ More preferably, 2000 cd / m or less ２ More than 5000cd / m ２ It can be as follows:

[0427] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be appropriately combined with other configuration examples or drawings.

[0428] Fourth Embodiment In this embodiment, an example of a cross-sectional configuration of the display device 10 that is different from that of the third embodiment will be described.

[0429] 34A shows an example of a cross-sectional configuration of the display device 10. The display device 10 shown in FIG.

[0430] The light-emitting element 61R has a function of emitting red light (R). The light-emitting element 61G has a function of emitting green light (G). The transistor 300 and the transistor 310 are transistors having a channel formation region in a substrate 16. The substrate 16 can be, for example, a semiconductor substrate such as a single crystal silicon substrate. The transistor 300 and the transistor 310 include a part of the substrate 16, a conductor 371, a low-resistance region 372, an insulator 373, and an insulator 374. The conductor 371 functions as a gate electrode. The insulator 373 is located between the substrate 16 and the conductor 371 and functions as a gate insulator. The low-resistance region 372 is a region in which the substrate 16 is doped with impurities and functions as a source or drain. The insulator 374 is provided to cover a side surface of the conductor 371.

[0431] The transistor 300 corresponds to, for example, the transistor 52B described in the above embodiment, and the transistor 310 corresponds to, for example, the transistor 132 described in the above embodiment.

[0432] Furthermore, an element isolation layer 403 is provided between two adjacent transistors 300 so as to be embedded in the substrate 16 .

[0433] In addition, an insulator 261 is provided to cover the transistor 310 , and a capacitor 791 is provided over the insulator 261 .

[0434] The capacitor 791 has a conductor 792, a conductor 794, and an insulator 793 located therebetween. The conductor 792 functions as one electrode of the capacitor 791, the conductor 794 functions as the other electrode of the capacitor 791, and the insulator 793 functions as a dielectric of the capacitor 791.

[0435] The conductor 792 is provided over the insulator 261 and is embedded in the conductor 795. The conductor 792 is electrically connected to one of the source and drain of the transistor 300 by a plug 257 embedded in the insulator 261. The insulator 793 is provided to cover the conductor 792. The conductors 792 and 794 have a region where they overlap with each other with the insulator 793 interposed therebetween.

[0436] An insulator 255a is provided covering the capacitor 791, an insulator 255b is provided on the insulator 255a, and an insulator 255c is provided on the insulator 255b. The light-emitting element 61R and the light-emitting element 61G are provided on the insulator 255c. Insulators are provided in the regions between adjacent light-emitting devices and in the regions between adjacent light-emitting devices and light-receiving devices. In Figure 34A and other figures, a protective layer 271 and an insulator 278 on the protective layer 271 are provided in these regions.

[0437] An insulator 270 is provided over each of the EL layer 172R of the light-emitting element 61R and the EL layer 172G of the light-emitting element 61G. A common layer 174 is provided over the EL layer 172R, the EL layer 172G, and the insulator 278, and a conductor 173 is provided over the common layer 174. A protective layer 273 is provided over the conductor 173.

[0438] The conductor 171 is electrically connected to one of the source and drain of the transistor 310 by a plug 256 embedded in the insulators 793, 255a, 255b, and 255c, a conductor 792 embedded in the conductor 795, and a plug 257 embedded in the insulator 261. The height of the top surface of the insulator 255c and the height of the plug 256 are the same or approximately the same. Various conductive materials can be used for the plug.

[0439] Furthermore, an insulator 276 is provided on the light-emitting element 61R, the light-emitting element 61G, and the light-receiving element 71. The components from the conductor 171 to the insulator 276 correspond to layer 60. A substrate 12 is provided on the insulator 276. The insulator 276 functions as an adhesive layer. The layered structure from the substrate 16 to the insulator 255c corresponds to layer 50 of the display device 10A and the display device 10B, and corresponds to layer 20 of the display device 10C.

[0440] In the configuration example shown in FIG. 34A, the light emitting element is formed on the layer 60, and the light receiving element is formed on the layer 50 or the layer 20.

[0441] The light receiving element 71 has a function of detecting light Lin that is incident from the outside of the display device via the insulator 276, the insulator 255a, the insulator 261, and the like.

[0442] Figure 34B shows an example of a cross-sectional configuration different from the example of the cross-sectional configuration of the display device 10 shown in Figure 34A. Figure 34B is a modified example of Figure 34A. The display device 10 shown in Figure 34B has a light-emitting element 61W instead of light-emitting element 61R and light-emitting element 61G, and has a colored layer in a region on insulator 276 that overlaps with light-emitting element 61W. Figure 34B shows an example of a cross-sectional configuration of display device 10 that has colored layer 264R that overlaps one light-emitting element 61W and colored layer 264G that overlaps another light-emitting element 61W.

[0443] The light-emitting element 61W has a function of emitting white light. Furthermore, the coloring layer 264R has a function of transmitting red light, and the coloring layer 264G has a function of transmitting green light. The white light (W) emitted from the light-emitting element 61W is emitted as red light to the outside of the display device through the coloring layer 264R. Furthermore, the white light (W) emitted from the light-emitting element 61W is emitted as green light to the outside of the display device through the coloring layer 264G. Although not shown in FIG. 34B , a coloring layer that transmits light in wavelength ranges other than red light and green light, such as blue light, may also be used.

[0444] Furthermore, a colored layer 264X may be provided in a region of the insulator 276 that overlaps with the light receiving element 71. A colored layer that transmits light in any wavelength range can be provided as the colored layer 264X. By providing the colored layer 264X, only light that transmits through the colored layer 264X can be detected by the light receiving element 71.

[0445] 34B has an insulator 258 on the colored layer 264R, the colored layer 264G, and the colored layer 264X, and has a substrate 12 on the insulator 258. The insulator 258 functions as an adhesive layer.

[0446] Figure 35A shows a modified example of the display device 10 shown in Figure 34B. The display device 10 shown in Figure 35A has a configuration in which an EL layer 172W is shared by adjacent light-emitting elements 61W. The EL layer 172W also remains in the region overlapping with the light-receiving element 71. If the EL layer 172W has a thickness that allows light Lin to pass through, light Lin can be detected even if the EL layer 172W remains in the region overlapping with the light-receiving element 71.

[0447] Fig. 35B shows a modification of the display device 10 shown in Fig. 34A. As described in the above embodiment, the light-receiving element 71 can be realized by replacing the EL layer 172 of the light-emitting element 61 with the active layer 182 that functions as a photoelectric conversion layer.

[0448] 35B, a light-emitting element 61 and a light-receiving element 71 are provided in a layer 60. The light-receiving element 71 provided in the layer 60 is electrically connected to one of the source and drain of the transistor 310 via a plug 256 and a plug 257.

[0449] Furthermore, as shown in FIG. 36A, colored layers 264R and 264G may be provided overlapping the light-emitting element 61W, and a colored layer 264X may be provided overlapping the light-receiving element 71.

[0450] 36B, a configuration may be adopted in which colored layers 264R and 264G are provided overlapping the light-emitting element 61W, and no colored layer is provided on the light-receiving element 71.

[0451] Fig. 37 shows a modification of the display device 10 shown in Fig. 34A. The display device 10 shown in Fig. 37 has a configuration in which a transistor 300 and a transistor 302 are stacked. The transistor 300 has a channel formed in a substrate 16. The transistor 302 has a channel formed in a substrate 17. Both the substrate 16 and the substrate 17 are semiconductor substrates.

[0452] The display device 10 shown in FIG. 37 has a structure in which a substrate 16 provided with a transistor 300, a capacitor 791, and a light-receiving element 71 and a substrate 17 provided with a transistor 302 are bonded together.

[0453] Here, it is preferable to provide an insulator 345 on the lower surface of the substrate 16. It is also preferable to provide an insulator 346 on the insulator 262 provided on the substrate 17. The insulators 345 and 346 are insulators that function as protective layers and can suppress the diffusion of impurities into the substrates 16 and 17.

[0454] Furthermore, an insulator 796 and an insulator 797 may be provided between the insulator 261 and the conductor 792. Furthermore, a conductor 798 may be provided over the insulator 261. The conductor 798 is preferably provided so as to be embedded in the insulator 797.

[0455] A plug 342 penetrating the substrate 16 and an insulator 345 is provided in the substrate 16. Here, an insulator 344 is preferably provided to cover the side surface of the plug 342. The insulator 344 is an insulator that functions as a protective layer and can suppress the diffusion of impurities into the substrate 16. When the substrate 16 is a silicon substrate, the plug 342 is also called a through silicon via (TSV).

[0456] Furthermore, a conductor 348 is provided on the back surface of the substrate 16 (the surface opposite to the substrate 12 side), below the insulator 345. The conductor 348 is preferably provided so as to be embedded in the insulator 332. Furthermore, the bottom surfaces of the conductor 348 and the insulator 332 are preferably flattened. Here, the conductor 348 is electrically connected to the conductor 798 via the plug 342.

[0457] On the other hand, the substrate 17 has a conductor 349 provided on an insulator 346. The conductor 349 is preferably provided so as to be embedded in the insulator 336. The top surfaces of the conductor 349 and the insulator 336 are preferably flattened.

[0458] The conductor 348 and the conductor 349 are joined together to electrically connect the substrate 17 and the substrate 16. Here, by improving the flatness of the surface formed by the conductor 348 and the insulator 332 and the surface formed by the conductor 349 and the insulator 336, the joining state of the conductor 348 and the conductor 349 can be improved.

[0459] It is preferable to use the same conductive material for the conductors 348 and 349. For example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film containing the above elements (titanium nitride film, molybdenum nitride film, tungsten nitride film), etc., can be used. In particular, it is preferable to use copper for the conductors 348 and 349. This allows for the application of Cu-Cu (copper-copper) direct bonding technology (technology that achieves electrical conductivity by connecting Cu (copper) pads together).

[0460] 37, the layered structure from conductor 348 and insulator 332 to insulator 255c corresponds to layer 50 of display device 10A and display device 10B. Also, the layered structure from substrate 17 to conductor 349 and insulator 336 corresponds to layer 20 of display device 10A and display device 10B.

[0461] As in the display device 10 shown in FIG. 38 , a bump 358 may be provided between the conductor 348 and the conductor 349, and the conductor 348 and the conductor 349 may be electrically connected via the bump 358. The bump 358 may be formed using a conductive material containing, for example, gold (Au), nickel (Ni), indium (In), tin (Sn), or the like. Alternatively, for example, solder may be used as the bump 358. An adhesive layer 359 may be provided between the insulator 332 and the insulator 336. Furthermore, when the bump 358 is provided, the insulators 332 and 336 may not be provided.

[0462] Fig. 39 shows a modification of the display device 10 shown in Fig. 36. The display device 10 shown in Fig. 39 has a transistor 380 over a substrate 16. Thus, the display device 10 shown in Fig. 39 has a structure in which the transistor 380 and the transistor 302 are stacked. The transistor 380 is a transistor having a back gate. A semiconductor substrate or a substrate made of another material may be used as the substrate 16.

[0463] 39, the light receiving element 71 shown in FIG. 35B is used as the light receiving element 71. Specifically, an organic semiconductor is used for the active layer that functions as a photoelectric conversion layer.

[0464] The transistor 380 includes a semiconductor 382, ​​an insulator 384, a conductor 385, a pair of conductors 383, an insulator 326, and a conductor 381. The semiconductor 382 may be an oxide semiconductor, for example.

[0465] 39 includes an insulator 324 on the substrate 16. The insulator 324 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 16 side to the transistor 380 and prevents oxygen from being released from the semiconductor 382 toward the insulator 324. The insulator 324 can be, for example, an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film.

[0466] The conductor 381 is provided over the insulator 324, and the insulator 326 is provided to cover the conductor 381. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulator 326 that is in contact with the semiconductor 382. The top surface of the insulator 326 is preferably planarized.

[0467] The semiconductor 382 is provided over the insulator 326. A pair of conductors 383 is provided over and in contact with the semiconductor 382 and functions as a source electrode and a drain electrode.

[0468] An insulator 327 is provided to cover the top surfaces and side surfaces of the pair of conductors 383 and the side surfaces of the semiconductor 382, ​​and the insulator 261 is provided over the insulator 327. The insulator 327 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulator 261 or the like to the semiconductor 382 and prevents oxygen from being released from the semiconductor 382. The insulator 327 can be an insulating film similar to that of the insulator 324.

[0469] Openings reaching the semiconductor 382 are provided in the insulator 327 and the insulator 261. Inside the openings, an insulator 384 in contact with the side surfaces of the insulator 261, the insulator 327, and the conductor 383 and the top surface of the semiconductor 382, ​​and a conductor 385 in contact with the insulator 384 are buried.

[0470] The conductor 385 serves as a first gate electrode of the transistor 380, and the insulator 384 serves as a first gate insulator. The conductor 381 serves as a second gate electrode of the transistor 380, and a portion of the insulator 326 serves as a second gate insulator.

[0471] When one of the first gate electrode and the second gate electrode is referred to as a "gate" or a "gate electrode," the other of the first gate electrode and the second gate electrode may be referred to as a "back gate" or a "back gate electrode."

[0472] The top surfaces of the conductor 385, the insulator 384, and the insulator 261 are planarized so that their heights are the same or approximately the same, and the insulators 329 and 263 are provided to cover them.

[0473] The insulators 261 and 263 function as interlayer insulators. The insulator 329 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulator 263 side into the transistor 380. The insulator 329 can be an insulating film similar to the insulators 327 and 324.

[0474] A plug 799 electrically connected to one of the pair of conductors 383 is provided so as to be embedded in openings provided in insulators 796, 797, 263, 329, 261, and 327.

[0475] Here, it is preferable that the plug 799 be made of a conductive material that is resistant to diffusion of hydrogen and oxygen at the portions that contact the side surfaces of the openings of insulators 796, 797, 263, 329, 261, and 327, and at the portions that contact a portion of conductor 383 at the bottom of the openings.

[0476] 39, the plug 342 is provided so as to penetrate the insulators 263, 329, 261, 327, 326, 324, the substrate 16, and the insulator 345. As described above, it is preferable to provide the insulator 344 so as to cover the side surface of the plug 342.

[0477] 40 , a bump 358 may be provided between the conductor 348 and the conductor 349, and the conductor 348 and the conductor 349 may be electrically connected via the bump 358. An adhesive layer 359 may be provided between the insulator 332 and the insulator 336. The display device 10 shown in FIG. 40 is a modified example of the display device 10 shown in FIG. 39 , but is also a modified example of the display device 10 shown in FIG. 37 .

[0478] Furthermore, as shown in FIG. 35A, a colored layer 264X may be provided so as to overlap the light receiving element 71.

[0479] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be appropriately combined with other configuration examples or drawings.

[0480] (Embodiment 5) <Structure Example of OS Transistor> In this embodiment, a structure example of an OS transistor that can be used in a display device that is one embodiment of the present invention will be described. FIGS. 41A, 41B, and 41C are a top view and a cross-sectional view of a transistor 750 that can be used in a display device that is one embodiment of the present invention and the periphery of the transistor 750. The transistor 750 can also be applied to the transistor 380, etc.

[0481] FIG. 41A is a top view of the transistor 750. Also, FIGS. 41B and 41C are cross-sectional views of the transistor 750. Here, FIG. 41B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 41A and is also a cross-sectional view of the transistor 750 in the channel length direction. Also, FIG. 41C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 41A and is also a cross-sectional view of the transistor 750 in the channel width direction. Note that some elements are omitted from the top view in FIG. 41A for clarity.

[0482] As shown in Figures 41 to 41C, the transistor 750 has a metal oxide 220a disposed on a substrate (not shown), a metal oxide 220b disposed on the metal oxide 220a, a conductor 242a and a conductor 242b disposed spaced apart from each other on the metal oxide 220b, an insulator 280 disposed on the conductors 242a and 242b and having an opening formed between the conductors 242a and 242b, a conductor 260 disposed in the opening, an insulator 250 disposed among the metal oxide 220b, the conductors 242a, the conductors 242b, the insulator 280, and the conductor 260, and a metal oxide 220c disposed among the metal oxide 220b, the conductors 242a, the conductors 242b, the insulator 280, and the insulator 250. 41B and 41C , it is preferable that the top surface of conductor 260 substantially coincides with the top surfaces of insulators 250, 254, metal oxide 220c, and insulator 280. Note that, hereinafter, metal oxide 220a, metal oxide 220b, and metal oxide 220c may be collectively referred to as metal oxide 220. Furthermore, conductors 242a and 242b may be collectively referred to as conductor 242.

[0483] 41 to 41C , the side surfaces of the conductors 242a and 242b facing the conductor 260 have a substantially vertical shape. Note that the transistor 750 shown in FIGS. 41 to 41C is not limited to this, and the angle formed between the side surface and the bottom surface of the conductors 242a and 242b may be 10° to 80°, preferably 30° to 60°. Furthermore, the opposing side surfaces of the conductors 242a and 242b may have multiple surfaces.

[0484] 41 to 41C, it is preferable that an insulator 254 be disposed between the insulator 224, the metal oxide 220a, the metal oxide 220b, the conductor 242a, the conductor 242b, and the metal oxide 220c and the insulator 280. Here, it is preferable that the insulator 254 be in contact with the side surface of the metal oxide 220c, the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, the side surfaces of the metal oxide 220a and the metal oxide 220b, and the top surface of the insulator 224, as shown in FIGS.

[0485] Although the transistor 750 has a three-layer structure including the metal oxide 220a, the metal oxide 220b, and the metal oxide 220c in and around a region where a channel is formed (hereinafter also referred to as a channel formation region), the present invention is not limited to this structure. For example, a two-layer structure including the metal oxide 220b and the metal oxide 220c or a stacked structure of four or more layers may be provided. Although the transistor 750 has a two-layer structure including the conductor 260, the present invention is not limited to this structure. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers. Furthermore, each of the metal oxide 220a, the metal oxide 220b, and the metal oxide 220c may have a stacked structure of two or more layers.

[0486] For example, when metal oxide 220c has a layered structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, it is preferable that the first metal oxide has a composition similar to that of metal oxide 220b, and the second metal oxide has a composition similar to that of metal oxide 220a.

[0487] Here, the conductor 260 functions as the gate electrode of the transistor, and the conductors 242a and 242b function as source and drain electrodes, respectively. As described above, the conductor 260 is formed so as to be embedded in the opening of the insulator 280 and in the region sandwiched between the conductors 242a and 242b. Here, the arrangements of the conductors 260, 242a, and 242b are selected in a self-aligned manner with respect to the opening of the insulator 280. That is, in the transistor 750, the gate electrode can be arranged between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 260 can be formed without providing an alignment margin, thereby reducing the area occupied by the transistor 750. This allows for a high-resolution display device. Furthermore, the frame of the display device can be narrowed.

[0488] As shown in Figures 41 to 41C, it is preferable that the conductor 260 has a conductor 260a provided inside the insulator 250 and a conductor 260b provided so as to be embedded inside the conductor 260a.

[0489] The transistor 750 preferably includes an insulator 214 disposed on a substrate (not shown), an insulator 216 disposed on the insulator 214, a conductor 205 disposed so as to be embedded in the insulator 216, an insulator 222 disposed on the insulator 216 and the conductor 205, and an insulator 224 disposed on the insulator 222. A metal oxide 220a is preferably disposed on the insulator 224.

[0490] The insulator 274, which functions as an interlayer film, and the insulator 281 are preferably provided over the transistor 750. Here, the insulator 274 is preferably provided in contact with top surfaces of the conductor 260, the insulator 250, the insulator 254, the metal oxide 220c, and the insulator 280.

[0491] It is preferable that insulators 222, 254, and 274 have the function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). For example, it is preferable that insulators 222, 254, and 274 have lower hydrogen permeability than insulators 224, 250, and 280. It is also preferable that insulators 222 and 254 have the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, it is preferable that insulators 222 and 254 have lower oxygen permeability than insulators 224, 250, and 280.

[0492] Here, the insulator 224, the metal oxide 220, and the insulator 250 are separated by the insulator 222 and the insulator 274. Therefore, impurities such as hydrogen and excess oxygen contained in the layer above the insulator 274 and the layer below the insulator 222 can be prevented from being mixed into the insulator 224, the metal oxide 220, and the insulator 250.

[0493] It is preferable that a conductor 245 (conductor 245a and conductor 245b) electrically connected to the transistor 750 and functioning as a plug be provided. Note that the insulator 241 (insulator 241a and insulator 241b) is provided in contact with the side surface of the conductor 245 functioning as a plug. That is, the insulator 241 is provided in contact with the inner walls of the openings of the insulators 254, 280, 274, and 281. Alternatively, a first conductor of the conductor 245 may be provided in contact with the side surface of the insulator 241, and a second conductor of the conductor 245 may be provided further inside. Here, the height of the top surface of the conductor 245 and the height of the top surface of the insulator 281 can be made approximately the same. Note that, although the transistor 750 illustrates a structure in which the first conductor of the conductor 245 and the second conductor of the conductor 245 are stacked, the present invention is not limited to this. For example, the conductor 245 may be provided as a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, the layers may be distinguished by assigning an ordinal number to indicate the order of formation.

[0494] In the transistor 750, a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the metal oxide 220 (the metal oxide 220a, the metal oxide 220b, and the metal oxide 220c) including the channel formation region. For example, a metal oxide that serves as the channel formation region of the metal oxide 220 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more.

[0495] The metal oxide preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable that it contains indium (In) and zinc (Zn). Furthermore, it is preferable that it contains an element M in addition to these. The element M can be one or more of aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), or cobalt (Co). In particular, it is preferable that the element M is one or more of aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn). Furthermore, it is more preferable that the element M contains either or both of Ga and Sn.

[0496] 41B , the film thickness of the metal oxide 220b in the region that does not overlap with the conductor 242 may be thinner than the film thickness of the region that overlaps with the conductor 242. This is formed by removing a portion of the upper surface of the metal oxide 220b when forming the conductors 242a and 242b. When a conductive film that will become the conductor 242 is formed on the upper surface of the metal oxide 220b, a low-resistance region may be formed near the interface with the conductive film. In this way, by removing the low-resistance region located between the conductors 242a and 242b on the upper surface of the metal oxide 220b, it is possible to prevent a channel from being formed in that region.

[0497] According to one embodiment of the present invention, a display device having high definition and a small transistor can be provided. Alternatively, a display device having high luminance and a transistor with high on-state current can be provided. Alternatively, a display device having high-speed operation and a transistor with stable electrical characteristics can be provided. Alternatively, a display device having low power consumption and a transistor with low off-state current can be provided.

[0498] A detailed structure of a transistor 750 that can be used in a display device that is one embodiment of the present invention will be described.

[0499] The conductor 205 is arranged to have a region overlapping with the metal oxide 220 and the conductor 260. In addition, the conductor 205 is preferably embedded in the insulator 216.

[0500] The conductor 205 includes conductor 205a, conductor 205b, and conductor 205c. The conductor 205a is provided in contact with the bottom surface and sidewall of an opening provided in the insulator 216. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the top surface of the conductor 205b is lower than the top surface of the conductor 205a and the top surface of the insulator 216. The conductor 205c is provided in contact with the top surface of the conductor 205b and the side surface of the conductor 205a. Here, the height of the top surface of the conductor 205c is approximately the same as the height of the top surface of the conductor 205a and the height of the top surface of the insulator 216. In other words, the conductor 205b is configured to be enclosed by the conductors 205a and 205c.

[0501] The conductors 205a and 205c are made of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0502] By using a conductive material that has the function of reducing hydrogen diffusion for the conductor 205a and the conductor 205c, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the metal oxide 220 via the insulator 224 or the like. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the conductor 205a and the conductor 205c, it is possible to prevent the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials that have the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 205a may be a single layer or a multilayer of the above conductive materials. For example, the conductor 205a may be made of titanium nitride.

[0503] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0504] Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. The conductor 205 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the potential applied to the conductor 205 may be changed independently of the potential applied to the conductor 260, thereby controlling the V ｔｈ In particular, applying a negative potential to the conductor 205 can control the V ｔｈ Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be made smaller than when no negative potential is applied.

[0505] The conductor 205 is preferably provided to be larger than the channel formation region in the metal oxide 220. In particular, as shown in Fig. 41C, the conductor 205 preferably extends also in a region outside the end portion intersecting with the channel width direction of the metal oxide 220. In other words, the conductor 205 and the conductor 260 preferably overlap with each other with an insulator interposed therebetween on the outside of the side surface of the metal oxide 220 in the channel width direction.

[0506] With the above structure, the channel formation region of the metal oxide 220 can be electrically surrounded by the electric field of the conductor 260 that functions as a first gate electrode and the electric field of the conductor 205 that functions as a second gate electrode.

[0507] 41C, the conductor 205 is extended to function as wiring. However, without being limited to this, a conductor functioning as wiring may be provided below the conductor 205.

[0508] The insulator 214 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 750 from the substrate side. Therefore, the insulator 214 prevents hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (i.e., copper atoms are less likely to penetrate the impurities), or that has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., oxygen is less likely to penetrate the insulating material).

[0509] For example, aluminum oxide, silicon nitride, or the like is preferably used as the insulator 214. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulator 214 to the transistor 750 side. Alternatively, it can prevent oxygen contained in the insulator 224 or the like from diffusing to the substrate side of the insulator 214.

[0510] The insulators 216, 280, and 281, which function as interlayer films, preferably have a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like can be used as appropriate for the insulators 216, 280, and 281.

[0511] The insulators 222 and 224 function as gate insulators.

[0512] Here, the insulator 224 in contact with the metal oxide 220 preferably releases oxygen by heating. In this specification, oxygen released by heating is sometimes referred to as excess oxygen. For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the metal oxide 220, oxygen vacancies in the metal oxide 220 can be reduced and the reliability of the transistor 750 can be improved.

[0513] Specifically, an oxide material from which some oxygen is released by heating is preferably used as the insulator 224. The oxide from which oxygen is released by heating is an oxide from which the amount of released oxygen converted into oxygen atoms is 1.0×10 in thermal desorption spectroscopy (TDS) analysis. １８ atoms / cm ３ or more, preferably 1.0 × 10 １９ atoms / cm ３ More preferably, 2.0 × 10 １９ atoms / cm ３ or more, or 3.0 x 10 ２０ atoms / cm ３ The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0514] 41C , the thickness of the region of insulator 224 that does not overlap with insulator 254 and metal oxide 220b may be thinner than the thickness of the other region. It is preferable that the thickness of the region of insulator 224 that does not overlap with insulator 254 and metal oxide 220b is a thickness that allows sufficient diffusion of the oxygen.

[0515] Like the insulator 214, the insulator 222 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 750 from the substrate side. For example, the insulator 222 preferably has lower hydrogen permeability than the insulator 224. By surrounding the insulator 224, the metal oxide 220, the insulator 250, etc. with the insulators 222, 254, and 274, impurities such as water or hydrogen can be prevented from entering the transistor 750 from the outside.

[0516] Furthermore, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate). For example, the insulator 222 preferably has lower oxygen permeability than the insulator 224. The insulator 222 preferably has a function of suppressing the diffusion of oxygen and impurities, which can reduce the diffusion of oxygen contained in the metal oxide 220 toward the substrate side. Furthermore, the conductor 205 can be prevented from reacting with oxygen contained in the insulator 224 or the metal oxide 220.

[0517] The insulator 222 may be an insulator containing an oxide of one or both of insulating materials, such as aluminum and hafnium. Examples of the insulator containing an oxide of one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the metal oxide 220 and the intrusion of impurities such as hydrogen into the metal oxide 220 from the periphery of the transistor 750.

[0518] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0519] The insulator 222 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), or strontium titanate (SrTiO ３ ) or (Ba,Sr)TiO ３ Insulators containing so-called high-k materials such as BST may be used in a single layer or a multilayer configuration. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinner gate insulators. By using a high-k material as the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0520] The insulator 222 and the insulator 224 may have a stacked structure of two or more layers. In this case, the stacked structures are not limited to those made of the same material, and may be those made of different materials. For example, an insulator similar to the insulator 224 may be provided below the insulator 222.

[0521] The metal oxide 220 includes a metal oxide 220a, a metal oxide 220b on the metal oxide 220a, and a metal oxide 220c on the metal oxide 220b. By providing the metal oxide 220a below the metal oxide 220b, it is possible to suppress the diffusion of impurities from structures formed below the metal oxide 220a to the metal oxide 220b. Furthermore, by providing the metal oxide 220c on the metal oxide 220b, it is possible to suppress the diffusion of impurities from structures formed above the metal oxide 220c to the metal oxide 220b.

[0522] The metal oxide 220 preferably has a stacked structure of multiple oxide layers with different atomic ratios of each metal atom. For example, when the metal oxide 220 contains at least indium (In) and the element M, the ratio of the number of atoms of the element M contained in the metal oxide 220a to the number of atoms of all elements constituting the metal oxide 220a is preferably higher than the ratio of the number of atoms of the element M contained in the metal oxide 220b to the number of atoms of all elements constituting the metal oxide 220b. Furthermore, the atomic ratio of the element M contained in the metal oxide 220a to In is preferably higher than the atomic ratio of the element M contained in the metal oxide 220b to In. Here, the metal oxide 220c can be the same as the metal oxide that can be used for the metal oxide 220a or the metal oxide 220b.

[0523] The energy of the conduction band minimum of the metal oxide 220a and the metal oxide 220c is preferably higher than the energy of the conduction band minimum of the metal oxide 220b. In other words, the electron affinity of the metal oxide 220a and the metal oxide 220c is preferably lower than the electron affinity of the metal oxide 220b. In this case, the metal oxide 220c is preferably a metal oxide that can be used for the metal oxide 220a. Specifically, the ratio of the number of atoms of the element M contained in the metal oxide 220c to the number of atoms of all elements constituting the metal oxide 220c is preferably higher than the ratio of the number of atoms of the element M contained in the metal oxide 220b to the number of atoms of all elements constituting the metal oxide 220b. Furthermore, the atomic ratio of the element M contained in the metal oxide 220c to In is preferably higher than the atomic ratio of the element M contained in the metal oxide 220c to In.

[0524] Here, the energy level of the conduction band minimum changes smoothly at the junction between the metal oxides 220a, 220b, and 220c. In other words, the energy level of the conduction band minimum at the junction between the metal oxides 220a, 220b, and 220c changes continuously or forms a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layers formed at the interface between the metal oxides 220a and 220b and at the interface between the metal oxides 220b and 220c.

[0525] Specifically, when the metal oxide 220a and the metal oxide 220b, or the metal oxide 220b and the metal oxide 220c, share a common element other than oxygen (as a main component), a mixed layer with a low defect level density can be formed. For example, when the metal oxide 220b is an In—Ga—Zn oxide, the metal oxide 220a and the metal oxide 220c may be made of an In—Ga—Zn oxide, a Ga—Zn oxide, gallium oxide, or the like. The metal oxide 220c may also have a stacked structure. For example, a stacked structure of an In—Ga—Zn oxide and a Ga—Zn oxide on the In—Ga—Zn oxide, or a stacked structure of an In—Ga—Zn oxide and a gallium oxide on the In—Ga—Zn oxide, may be used. In other words, a stacked structure of an In—Ga—Zn oxide and an oxide not containing In may be used as the metal oxide 220c.

[0526] Specifically, metal oxide 220a may have an atomic ratio of In:Ga:Zn=1:3:4 or thereabouts, or an atomic ratio of 1:1:0.5 or thereabouts. Metal oxide 220b may have an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, or an atomic ratio of 3:1:2 or thereabouts. Metal oxide 220c may have an atomic ratio of In:Ga:Zn=1:3:4 or thereabouts, In:Ga:Zn=4:2:3 or thereabouts, Ga:Zn=2:1 or thereabouts, or Ga:Zn=2:5 or thereabouts. Specific examples of the metal oxide 220c having a stacked structure include a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or a ratio thereof near thereto and Ga:Zn=2:1 [atomic ratio] or a ratio thereof near thereto, a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or a ratio thereof near thereto and Ga:Zn=2:5 [atomic ratio] or a ratio thereof near thereto, and a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or a ratio thereof near thereto and gallium oxide.

[0527] In this case, the main carrier path is the metal oxide 220b. By configuring the metal oxide 220a and the metal oxide 220c as described above, the defect state density at the interface between the metal oxide 220a and the metal oxide 220b and at the interface between the metal oxide 220b and the metal oxide 220c can be reduced. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 750 to achieve a high on-state current and high frequency characteristics. Note that when the metal oxide 220c has a stacked structure, in addition to the effect of reducing the defect state density at the interface between the metal oxide 220b and the metal oxide 220c, it is expected that the diffusion of constituent elements of the metal oxide 220c toward the insulator 250 can be suppressed. More specifically, by configuring the metal oxide 220c as a stacked structure and positioning an oxide not containing In above the stacked structure, it is possible to suppress In that may diffuse toward the insulator 250. The insulator 250 functions as a gate insulator, and diffusion of In leads to poor transistor characteristics. Therefore, by forming the metal oxide 220c into a stacked structure, it is possible to provide a highly reliable display device.

[0528] Conductors 242 (conductors 242a and 242b) functioning as a source electrode and a drain electrode are provided on the metal oxide 220b. The conductor 242 is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, or lanthanum, or an alloy containing the above metal element or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain their conductivity even when they absorb oxygen.

[0529] By providing the conductor 242 so as to be in contact with the metal oxide 220, the oxygen concentration may decrease in the vicinity of the conductor 242 of the metal oxide 220. Furthermore, a metal compound layer containing the metal contained in the conductor 242 and components of the metal oxide 220 may be formed in the vicinity of the conductor 242 of the metal oxide 220. In such a case, the carrier concentration increases in the region of the metal oxide 220 in the vicinity of the conductor 242, and this region becomes a low-resistance region.

[0530] Here, the region between the conductor 242a and the conductor 242b is formed to overlap the opening of the insulator 280. This allows the conductor 260 to be arranged in a self-aligned manner between the conductor 242a and the conductor 242b.

[0531] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the metal oxide 220c. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat.

[0532] The insulator 250 preferably has a reduced concentration of impurities such as water or hydrogen, similar to the insulator 224. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0533] A metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. This makes it possible to suppress oxidation of the conductor 260 due to oxygen in the insulator 250.

[0534] The metal oxide may function as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, it is preferable to use a metal oxide that is a high-k material with a high dielectric constant. By forming the gate insulator into a stacked structure of the insulator 250 and the metal oxide, a stacked structure that is stable against heat and has a high dielectric constant can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0535] Specifically, it is possible to use a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. In particular, it is preferable to use an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0536] Although the conductor 260 is shown as having a two-layer structure in FIGS. 41 to 41C, it may have a single-layer structure or a laminated structure of three or more layers.

[0537] The conductor 260a is a material containing the above-mentioned hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use a conductor that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0538] The conductor 260a has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0539] The conductor 260b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Furthermore, the conductor 260b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0540] 41A and 41C , in a region of the metal oxide 220b that does not overlap with the conductor 242, in other words, in the channel formation region of the metal oxide 220, the side surface of the metal oxide 220 is arranged to be covered with the conductor 260. This makes it easier for the electric field of the conductor 260, which functions as the first gate electrode, to act on the side surface of the metal oxide 220. This increases the on-state current of the transistor 750 and improves its frequency characteristics.

[0541] Like the insulator 214, the insulator 254 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 750 from the insulator 280 side. For example, the insulator 254 preferably has lower hydrogen permeability than the insulator 224. Furthermore, as shown in FIGS. 41B and 41C , the insulator 254 preferably contacts the side surface of the metal oxide 220c, the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, the side surfaces of the metal oxide 220a and the metal oxide 220b, and the top surface of the insulator 224. This configuration can prevent hydrogen contained in the insulator 280 from entering the metal oxide 220 from the top or side surfaces of the conductor 242a, the conductor 242b, the metal oxide 220a, the metal oxide 220b, and the insulator 224.

[0542] Furthermore, it is preferable that the insulator 254 has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate). For example, it is preferable that the insulator 254 has lower oxygen permeability than the insulator 280 or the insulator 224.

[0543] The insulator 254 is preferably formed by a sputtering method. By forming the insulator 254 by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the insulator 224 near a region in contact with the insulator 254. This allows oxygen to be supplied from this region into the metal oxide 220 through the insulator 224. The insulator 254 has a function of suppressing upward oxygen diffusion, thereby preventing oxygen from diffusing from the metal oxide 220 to the insulator 280. The insulator 222 has a function of suppressing downward oxygen diffusion, thereby preventing oxygen from diffusing from the metal oxide 220 toward the substrate. In this manner, oxygen is supplied to the channel formation region of the metal oxide 220. This reduces oxygen vacancies in the metal oxide 220 and suppresses the transistor from becoming normally on.

[0544] For example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed as the insulator 254. Note that as the insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like.

[0545] The insulator 224, the insulator 250, and the metal oxide 220 are covered with the insulator 254, which has a barrier property against hydrogen, so that the insulator 280 is separated from the insulator 224, the metal oxide 220, and the insulator 250 by the insulator 254. This can prevent impurities such as hydrogen from penetrating from the outside of the transistor 750, thereby providing the transistor 750 with good electrical characteristics and reliability.

[0546] The insulator 280 is provided over the insulator 224, the metal oxide 220, and the conductor 242 with the insulator 254 interposed therebetween. For example, the insulator 280 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are particularly preferred because they can easily form a region containing oxygen that is released by heating.

[0547] It is preferable that the concentration of impurities such as water or hydrogen is reduced in the insulator 280. The top surface of the insulator 280 may be flattened.

[0548] Similar to the insulator 214, the insulator 274 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the insulator 280 from above. As the insulator 274, for example, an insulator that can be used for the insulator 214, the insulator 254, etc. may be used.

[0549] An insulator 281 functioning as an interlayer film is preferably provided over the insulator 274. Like the insulator 224, the insulator 281 preferably has a reduced concentration of impurities such as water or hydrogen.

[0550] The conductor 245a and the conductor 245b are arranged in openings formed in the insulator 281, the insulator 274, the insulator 280, and the insulator 254. The conductor 245a and the conductor 245b are arranged opposite each other with the conductor 260 interposed therebetween. The height of the upper surfaces of the conductor 245a and the conductor 245b may be flush with the upper surface of the insulator 281.

[0551] Note that insulator 241a is provided in contact with the inner walls of the openings of insulators 281, 274, 280, and 254, and a first conductor of conductor 245a is formed in contact with the side surface of insulator 241a. Conductor 242a is located on at least a portion of the bottom of the openings, and conductor 245a is in contact with conductor 242a. Similarly, insulator 241b is provided in contact with the inner walls of the openings of insulators 281, 274, 280, and 254, and a first conductor of conductor 245b is formed in contact with the side surface of insulator 241b. Conductor 242b is located on at least a portion of the bottom of the openings, and conductor 245b is in contact with conductor 242b.

[0552] The conductors 245a and 245b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 245a and 245b may have a layered structure.

[0553] When the conductor 245 has a layered structure, it is preferable to use the above-mentioned conductors that have the function of suppressing the diffusion of impurities such as water or hydrogen for the conductors in contact with the metal oxide 220a, the metal oxide 220b, the conductor 242, the insulator 254, the insulator 280, the insulator 274, and the insulator 281. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. Furthermore, the conductive material that has the function of suppressing the diffusion of impurities such as water or hydrogen may be used in a single layer or a layered structure. Using such a conductive material can suppress the absorption of oxygen added to the insulator 280 by the conductors 245a and 245b. Furthermore, it is possible to suppress the intrusion of impurities such as water or hydrogen from layers above the insulator 281 into the metal oxide 220 through the conductors 245a and 245b.

[0554] The insulators 241a and 241b may be, for example, an insulator that can be used for the insulator 254. The insulators 241a and 241b are provided in contact with the insulator 254, and therefore can prevent impurities such as water or hydrogen from the insulator 280 or the like from being mixed into the metal oxide 220 through the conductors 245a and 245b. Furthermore, the oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 245a and 245b.

[0555] Although not shown, a conductor functioning as wiring may be disposed in contact with the upper surface of the conductor 245a and the upper surface of the conductor 245b. The conductor functioning as wiring is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may also have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0556] <Constituent Materials of Transistor> Constituent materials that can be used for the transistor will be described.

[0557] [Substrate] The substrate on which a transistor is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates such as silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride and a metal oxide. Examples of other substrates include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate provided with elements may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0558] [Insulator] Examples of insulators include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, which have insulating properties.

[0559] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select a material depending on the function of the insulator.

[0560] Examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0561] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, and resin.

[0562] The electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding it with an insulator (such as the insulator 214, the insulator 222, the insulator 254, and the insulator 274) that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, a single-layer or stacked insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide; and metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, and silicon nitride.

[0563] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the metal oxide 220, oxygen vacancies in the metal oxide 220 can be compensated for.

[0564] [Conductor] As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal element as a component, or an alloy combining the above metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0565] A plurality of conductors formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may also be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may also be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0566] When a metal oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure of a combination of a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0567] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0568] <Classification of Crystal Structures in Oxide Semiconductors> Classification of crystal structures in oxide semiconductors will be described with reference to Fig. 42A. Fig. 42A is a diagram illustrating the classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0569] As shown in FIG. 42A , oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." Furthermore, "amorphous" includes completely amorphous. Furthermore, "crystalline" includes c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), and cloud-aligned composite (CAC) (excluding single crystal and poly crystal). The "Crystalline" category excludes single crystal, poly crystal, and completely amorphous. The "Crystal" category includes single crystal and poly crystal.

[0570] The structure within the bold frame shown in Figure 42A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "Amorphous" and "Crystal."

[0571] The crystalline structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Here, FIG. 42B shows an XRD spectrum obtained by GIXD (Grazing-Incident XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also called the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in FIG. 42B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in FIG. 42B is In:Ga:Zn=4:2:3 [atomic ratio] or nearby. The thickness of the CAAC-IGZO film shown in FIG. 42B is 500 nm.

[0572] As shown in Figure 42B, a peak indicating clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected at or near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 42B, the peak at or near 2θ = 31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0573] The crystalline structure of the film or substrate can be evaluated by a diffraction pattern (also referred to as a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 42C. FIG. 42C is a diffraction pattern observed by NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in FIG. 42C is In:Ga:Zn=4:2:3 [atomic ratio] or nearby. In nanobeam electron diffraction, electron beam diffraction is performed using a probe diameter of 1 nm.

[0574] As shown in FIG. 42C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0575] [Structure of Oxide Semiconductor] Note that oxide semiconductors may be classified differently from those shown in FIG. 42A when focusing on their crystal structures. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0576] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0577] [CAAC-OS] A CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction refers to the thickness direction of the CAAC-OS film, the normal direction to the surface where the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region is also a region with a uniform lattice arrangement. Furthermore, a CAAC-OS has a region where multiple crystalline regions are connected in the a-b plane direction, and the region may have distortion. Note that distortion refers to a portion where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with another uniform lattice arrangement in a region where multiple crystalline regions are connected. In other words, a CAAC-OS is an oxide semiconductor whose c-axes are aligned and whose orientation is not clearly aligned in the a-b plane direction.

[0578] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nanometers.

[0579] In an In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, and the like), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain the element M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0580] When a CAAC-OS film is subjected to structural analysis using an XRD apparatus, for example, a peak indicating c-axis orientation is detected at or near 2θ = 31° in out-of-plane XRD measurement using θ / 2θ scanning. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type, composition, and the like of the metal elements constituting the CAAC-OS.

[0581] For example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film, and the spots are observed at positions that are point-symmetric with respect to a spot of an incident electron beam that has passed through the sample (also referred to as a direct spot).

[0582] When a crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The distortion may also have a pentagonal, heptagonal, or other lattice arrangement. In CAAC-OS, no clear grain boundary can be identified even near the distortion. This indicates that the distortion in the lattice arrangement suppresses the formation of grain boundaries. This is thought to be because CAAC-OS can tolerate distortion due to the lack of a dense arrangement of oxygen atoms in the a-b plane and the change in interatomic bond distance caused by the substitution of metal atoms.

[0583] Note that a crystal structure in which clear grain boundaries are observed is called polycrystalline. The grain boundaries act as recombination centers, and are likely to trap carriers, resulting in a decrease in the on-state current of a transistor and a decrease in field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. Note that a structure containing Zn is preferable for forming a CAAC-OS. For example, In—Zn oxide and In—Ga—Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0584] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities or the generation of defects, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (oxygen vacancies, etc.). Therefore, an oxide semiconductor having a CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having a CAAC-OS is heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0585] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. Furthermore, the nc-OS does not exhibit regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS and an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scanning. When an nc-OS film is subjected to electron diffraction (also referred to as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of a nanocrystal (e.g., 50 nm or more), a diffraction pattern resembling a halo pattern is observed. On the other hand, when an nc-OS film is subjected to electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter close to or smaller than that of a nanocrystal (e.g., 1 nm to 30 nm), an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0586] [a-Like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0587] [Structure of Oxide Semiconductor] Next, the above-described CAC-OS will be described in detail. Note that the CAC-OS relates to a material structure.

[0588] [CAC-OS] CAC-OS is a material in which, for example, elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that, hereinafter, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0589] Furthermore, the CAC-OS has a mosaic structure in which a material is separated into a first region and a second region, and the first region is distributed throughout the film (hereinafter also referred to as a cloud structure). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0590] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In—Ga—Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In—Ga—Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0591] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0592] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0593] For example, in the case of CAC-OS in an In—Ga—Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) can confirm that the CAC-OS has a structure in which a region containing In as a main component (first region) and a region containing Ga as a main component (second region) are unevenly distributed and mixed.

[0594] When a CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, thereby providing the CAC-OS with a switching function (a function of turning on / off). That is, a CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and functions as a semiconductor as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using a CAC-OS in a transistor, a high on-current (I ｏｎ ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0595] Oxide semiconductors have a variety of structures, each of which has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0596] <Transistor Having Oxide Semiconductor> Next, a case where the oxide semiconductor is used for a transistor will be described.

[0597] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0598] For the transistor, an oxide semiconductor having a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 １７ cm −３ Below 1 × 10, preferably １５ cm −３ More preferably, 1×10 １３ cm −３ Less than 1×10, more preferably 1×10 １１ cm −３ More preferably, 1×10 １０ cm −３ is less than 1×10 −９ cm −３That is all. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0599] A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore, the density of trap states may also be low.

[0600] Charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0601] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0602] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0603] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by SIMS) are calculated to be 2×10 １８ atoms / cm ３ Below 2 × 10, preferably １７ atoms / cm ３ The following applies.

[0604] When an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0605] When nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is measured to be 5×10 １９ atoms / cm ３ Less than 5×10 １８ atoms / cm ３ Less than 1×10, more preferably 1×10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ Do the following:

[0606] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by SIMS is 1×10 ２０ atoms / cm ３ less than 1×10１９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ Make it less than.

[0607] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0608] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be appropriately combined with other configuration examples or drawings.

[0609] <Additional Notes Regarding the Description of the Present Specification, etc.> The following additional notes are provided regarding the above-described embodiments and the explanations of the respective configurations in the embodiments.

[0610] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0611] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, or with the content (or even a part of the content) described in one or more other embodiments.

[0612] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0613] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, with another figure (or even a part thereof) described in that embodiment, or with a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0614] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0615] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0616] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.

[0617] Furthermore, the terms "electrode" and "wiring" used in this specification and elsewhere do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" and "wirings" are integrally formed.

[0618] Furthermore, in this specification and the like, the terms voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), then voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0619] In this specification and the like, terms such as "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0620] In this specification, a switch refers to a device that has a function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0621] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0622] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the region where the channel is formed in a direction perpendicular to the channel length direction.

[0623] In this specification, "A and B are connected" includes not only a direct connection between A and B, but also an electrical connection between A and B. Here, "A and B are electrically connected" means that when an object having some kind of electrical effect exists between A and B, transmission of an electrical signal between A and B is possible.

[0624] In this specification and the like, a structure in which different light-emitting layers are formed or different light-emitting layers are painted for each color light-emitting device (e.g., blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. In this specification and the like, a light-emitting device that can emit white light may be referred to as a white light-emitting device. In addition, a white light-emitting device can be combined with a colored layer (e.g., a color filter) to realize a full-color display device.

[0625] Furthermore, light-emitting devices can be broadly divided into single structures and tandem structures. A single-structure device has one light-emitting unit between a pair of electrodes, and the light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission, two or more light-emitting layers may be selected so that the light emitted from each of the two or more light-emitting layers has a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary, a configuration in which the entire light-emitting device emits white light can be obtained. The same applies to light-emitting devices having three or more light-emitting layers.

[0626] A tandem-structure device preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission, light from the light-emitting layers of the light-emitting units may be combined to obtain white light emission. The configuration for obtaining white light emission is the same as that of the single-structure device. In a tandem-structure device, it is preferable to provide an intermediate layer such as a charge-generating layer between the light-emitting units.

[0627] Furthermore, when comparing the above-described white light-emitting device (single structure or tandem structure) with a light-emitting device having an SBS structure, the light-emitting device having an SBS structure can reduce power consumption compared to the white light-emitting device. If it is desired to reduce power consumption, it is preferable to use a light-emitting device having an SBS structure. On the other hand, the manufacturing process of a white light-emitting device is simpler than that of a light-emitting device having an SBS structure, and therefore the manufacturing cost can be reduced or the manufacturing yield can be increased, making it preferable.

[0628] Ordinal numbers such as "first" and "second" used in this specification are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes, stacking order, or arrangement order. Furthermore, even if a term is not used in this specification, an ordinal number may be used in the claims to avoid confusion between components. Furthermore, even if a term is used in this specification, a different ordinal number may be used in the claims. Furthermore, even if a term is used in this specification, the ordinal number may be omitted in the claims.

[0629] Generally, a "capacitance" has a configuration in which two electrodes face each other with an insulator (dielectric) interposed therebetween. In this specification, etc., the term "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, etc., the term "capacitance element" includes a configuration in which two electrodes face each other with an insulator interposed therebetween, a configuration in which two wires face each other with an insulator interposed therebetween, or a configuration in which two wires are arranged with an insulator interposed therebetween.

[0630] In this embodiment, a reduction in power consumption by changing the frame frequency for each sub-display section 19 will be described.

[0631] In this example, a display device was assumed in which the display unit 13 was divided into sub-display units 19 arranged in 4 rows and 8 columns, the diagonal size of the display unit 13 was 1.5 inches, and the resolution was 3000 x 4000 pixels, and power consumption was calculated when the frame frequency was changed for each sub-display unit 19. The power consumption was calculated using simulation software SPICE.

[0632] In this example, the power consumption was calculated for four modes, modes A to D. Figures 43A to 43D show the operating state of the display unit 13 in each mode.

[0633] Mode A is assumed to be a state in which the frame frequency of all sub-display sections 19 is 120 Hz (see FIG. 43A).

[0634] In Mode B, the frame frequencies of the sub-display unit 19 in the second row and fourth column (sub-display unit 19[2,4]) and the sub-display unit 19 in the second row and fifth column (sub-display unit 19[2,5]) are assumed to be 120 Hz, the frame frequencies of the sub-display units 19 adjacent to the outside of sub-display unit 19[2,4] or sub-display unit 19[2,5] are 90 Hz, the frame frequencies of the sub-display units 19 adjacent to the outside further out are 60 Hz, and the frame frequencies of the sub-display units 19 in the first and eighth columns are assumed to be 30 Hz (see Figure 43B).

[0635] In mode C, the frame frequency of the sub-display units 19 in the third to sixth columns was assumed to be 120 Hz, and the frame frequency of the sub-display units 19 in the first, second, seventh, and eighth columns was assumed to be 1 Hz (see Figure 43C).

[0636] Mode D is assumed to be a state in which the frame frequency of all sub-display sections 19 is 1 Hz (see FIG. 43D).

[0637] Fig. 44 is a graph showing the calculation results of power consumption for each mode. The horizontal axis of Fig. 44 represents each mode. The vertical axis of Fig. 44 represents values ​​obtained by normalizing the calculation results for each mode using the calculation results for mode A as the reference. Note that Fig. 44 also includes a notation for the normalized power consumption values ​​for each mode.

[0638] 44 also shows the power consumption in each mode, separated into the power consumption of the digital circuit and the...

Claims

1. A display device, a computing unit, and a gaze detection unit, wherein the display device includes a functional circuit and a display unit divided into a plurality of sub-display units, each of the plurality of sub-display units includes a gate driver circuit and a source driver circuit, each of the plurality of sub-display units is provided overlapping the gate driver circuit and the source driver circuit, each of the plurality of sub-display units is electrically connected to the gate driver circuit and the source driver circuit, the gaze detection unit has a function of detecting the user's gaze, the computing unit uses the detection result of the gaze detection unit, to allocate each of the plurality of sub-display units to a first area or a second area, the functional circuit, has a function of making a second driving frequency, which is the driving frequency of the sub-display units included in the second area, lower than a first driving frequency, which is the driving frequency of the sub-display units included in the first area, an electronic device.

2. In claim 1, the first area includes a region overlapping the user's fixation point, an electronic device.

3. In claim 1, the second driving frequency is 1 / 2 or less of the first driving frequency, an electronic device.

4. In any one of claims 1 to 3, each of the plurality of sub-display units includes a plurality of pixel circuits and a plurality of light-emitting elements, an electronic device.

5. In any one of claims 1 to 3, the gate driver circuit and the source driver circuit are each provided on a first layer, the plurality of pixel circuits are provided on a second layer on the first layer, the plurality of light-emitting elements are provided on a third layer on the second layer, an electronic device.

6. In any one of claims 1 to 3, it has a storage device, the storage device has a function of storing the image data of each of the plurality of sub-display units, an electronic device.