Imaging device, ranging device, and method for controlling imaging device

Abstract

An imaging device (100) comprises: a first semiconductor layer (170); a unit cell that includes n (n is a natural number) pixels (201) and a charge storage unit (FD) for storing charge generated by the n pixels; and a drive circuit (130). The n pixels each include a photoelectric conversion unit (211), a first transfer transistor (221) having a first control terminal (221g), and a second transfer transistor (231) having a second control terminal (231g). The drive circuit (130) supplies a voltage corresponding to one operation mode selected from among a plurality of operation modes to the first semiconductor layer (170) and to the first control terminal (221g) or the second control terminal (231g).

Description

Image capture device, distance measuring device, and method for controlling image capture device

[0001] The present disclosure relates to an imaging device, a distance measuring device, and a control method for an imaging device.

[0002] Patent Document 1 discloses an imaging device having a pixel array in which a plurality of pixels formed on a substrate are electrically isolated by an insulating trench. Each pixel includes a photodiode and two transfer transistors. In the imaging device disclosed in Patent Document 1, a positive voltage is applied to the substrate so that the transfer transistors are turned off at 0 V.

[0003] US Patent Application Publication No. 2022 / 0272291

[0004] In the imaging device disclosed in Patent Document 1, when attempting to simultaneously perform imaging and distance measurement, a deep potential is required for the photodiode to achieve high saturation during imaging and obtain high-resolution images. Meanwhile, during distance measurement, signal charge must be read out from the photodiode at high speed. To read out signal charge at high speed, the control voltage of the transfer transistor must be set high, which increases power consumption. Thus, the imaging device disclosed in Patent Document 1 has a problem in that it cannot simultaneously obtain high-resolution images and perform distance measurement with low power consumption.

[0005] Therefore, the present disclosure provides an imaging device and the like that can achieve both high-resolution image acquisition and distance measurement with low power consumption.

[0006] An imaging device according to one aspect of the present disclosure includes a first semiconductor layer, a unit cell provided on the first semiconductor layer, the unit cell including n pixels (n is a natural number) and a charge accumulation section for accumulating charge generated in the n pixels, and a drive circuit, wherein each of the n pixels includes a photoelectric conversion section, a first transfer transistor having a first control terminal, a first input / output terminal connected to the photoelectric conversion section, and a second input / output terminal connected to the charge accumulation section, and a second transfer transistor having a second control terminal, a third input / output terminal connected to the photoelectric conversion section, and a fourth input / output terminal different from the third input / output terminal, and the drive circuit supplies a voltage to the first semiconductor layer, or the first control terminal, or the second control terminal, according to one operation mode selected from a plurality of operation modes.

[0007] A distance measuring device according to one aspect of the present disclosure includes a light source, an imaging device according to the above aspect, and an arithmetic circuit that calculates a distance to an object based on a signal output from the imaging device.

[0008] A control method for an imaging device according to one aspect of the present disclosure includes, in an operating mode in which at least one of the n pixels is exposed to flashing light of a second wavelength, repeatedly switching between conductive and non-conductive states of the first transfer transistor and the second transfer transistor so that they are not simultaneously in a conductive state during the exposure period to the flashing light of the second wavelength, and, in an operating mode in which at least one of the n pixels is exposed to light of a first wavelength, maintaining the first transfer transistor and the second transfer transistor in a non-conductive state during the exposure period to light of the first wavelength, and switching only the first transfer transistor into a conductive state at a predetermined timing.

[0009] Furthermore, one aspect of the present disclosure can be realized as a program that causes a computer to execute the control method, or as a computer-readable non-transitory recording medium storing the program.

[0010] According to the present disclosure, it is possible to provide an imaging device and the like that can achieve both high-resolution image acquisition and distance measurement with low power consumption.

[0011] FIG. 1 is a diagram illustrating a configuration of an endoscope system according to an embodiment. FIG. 2 is a diagram illustrating a configuration of an imaging device according to an embodiment. FIG. 3 is a diagram illustrating a circuit configuration of a unit cell according to an embodiment. FIG. 4 is a diagram illustrating an example of control of operation modes in an imaging device according to an embodiment. FIG. 5 is a diagram illustrating a distance measurement method based on a CW-ToF system. FIG. 6 is a diagram illustrating a distance measurement method based on a pulsed ToF system. FIG. 7A is a timing chart illustrating a first driving example of a CW-ToF distance measurement mode. FIG. 7B is a diagram illustrating the relationship between irradiated light, reflected light, and each frame period in the first driving example illustrated in FIG. 7A. FIG. 8 is a timing chart illustrating a second driving example of a CW-ToF distance measurement mode. FIG. 9A is a timing chart illustrating a third driving example of a CW-ToF distance measurement mode. FIG. 9B is a timing chart illustrating a modified example of the third driving example of a CW-ToF distance measurement mode. FIG. 10A is a timing chart illustrating a driving example of a pulsed ToF distance measurement mode. FIG. 10B is a diagram showing the relationship between irradiated light and reflected light and each frame period in the example shown in FIG. 10A . FIG. 10C is a diagram showing an example of control signals supplied to two transfer transistors in the example shown in FIG. 10A . FIG. 11 is a timing chart showing a first driving example in RGB mode. FIG. 12 is a timing chart showing a second driving example in RGB mode. FIG. 13A is a diagram showing the potential within a unit cell in RGB mode. FIG. 13B is a diagram showing the potential within a unit cell in ToF mode. FIG. 14 is a schematic plan view showing an example of a pixel according to an embodiment. FIG. 15A is a schematic plan view showing another example of a pixel according to an embodiment. FIG. 15B is a schematic plan view showing another example of a pixel according to an embodiment. FIG. 15C is a schematic plan view showing another example of a pixel according to an embodiment. FIG. 15D is a schematic plan view showing another example of a pixel according to an embodiment. FIG. 15E is a schematic plan view showing another example of a pixel according to an embodiment. FIG. 15F is a schematic plan view showing another example of a pixel according to an embodiment. FIG. 16 is a diagram illustrating a configuration of a drive circuit according to an embodiment.FIG. 17 is a diagram showing the circuit configurations of a pixel control circuit and a substrate voltage supply circuit according to an embodiment. FIG. 18A is a diagram showing an example of a potential supplied to a control terminal of a transfer transistor in RGB mode. FIG. 18B is a diagram showing an example of a potential supplied to a control terminal of a transfer transistor in ToF mode. FIG. 18C is a diagram showing another example of a potential supplied to a control terminal of a transfer transistor in ToF mode. FIG. 19A is a diagram showing an example of a potential supplied to each control terminal of a transfer transistor and a reset transistor in RGB mode. FIG. 19B is a diagram showing an example of a potential supplied to each control terminal of a transfer transistor and a reset transistor in ToF mode. FIG. 20A is a diagram showing an example of a potential supplied to each control terminal of a transfer transistor and a reset transistor, and to each substrate, in RGB mode. FIG. 20B is a diagram showing an example of a potential supplied to each control terminal of a transfer transistor and a reset transistor, and to each substrate, in ToF mode. FIG. 20C is a diagram showing a modified example of a potential supplied to each control terminal of a transfer transistor and a reset transistor, and to each substrate, in ToF mode. Fig. 21 is a diagram showing the potential in a unit cell when the capacitor voltage is controlled in ToF mode. Fig. 22 is a plan view of a photoelectric conversion unit according to an embodiment. Fig. 23A is a cross-sectional view taken along line XXIII-XXIII in Fig. 22. Fig. 23B is a cross-sectional view of a pixel according to a comparative example, corresponding to line XXIII-XXIII in Fig. 22. Fig. 24 is a cross-sectional view showing the cross-sectional configuration of the photoelectric conversion unit when a negative voltage is supplied to the control terminal of the transfer transistor. Fig. 25 is a diagram showing the dynamic range of an imaging device relative to the area ratio of a hole accumulation region.

[0012] (Summary of the Present Disclosure) An imaging device according to a first aspect of the present disclosure includes a first semiconductor layer, a unit cell provided on the first semiconductor layer, the unit cell including n pixels (n is a natural number) and a charge accumulation unit for accumulating charge generated in the n pixels, and a drive circuit, wherein each of the n pixels includes a photoelectric conversion unit, a first transfer transistor having a first control terminal, a first input / output terminal connected to the photoelectric conversion unit, and a second input / output terminal connected to the charge accumulation unit, and a second transfer transistor having a second control terminal, a third input / output terminal connected to the photoelectric conversion unit, and a fourth input / output terminal different from the third input / output terminal, and the drive circuit supplies a voltage to the first semiconductor layer, or the first control terminal, or the second control terminal, according to one operation mode selected from a plurality of operation modes.

[0013] In this way, the imaging device according to this aspect can supply an appropriate voltage to the first semiconductor layer, the first control terminal, or the second control terminal depending on the operating mode. Therefore, even if the potential of the photoelectric conversion unit is increased to obtain a high-resolution image, it is possible to reduce power consumption and perform high-precision distance measurement. This makes it possible to achieve both high-resolution image acquisition and low-power distance measurement.

[0014] An imaging device according to a second aspect of the present disclosure is an imaging device according to the first aspect, wherein the plurality of operating modes include a first operating mode in which at least one of the n pixels is exposed to light of a first wavelength, and a second operating mode in which at least one of the n pixels is exposed to flashing light of a second wavelength.

[0015] This makes it possible to acquire high-quality images in the first operation mode and to perform distance measurement with low power consumption in the second operation mode.

[0016] An imaging device according to a third aspect of the present disclosure is an imaging device according to the first or second aspect, wherein the drive circuit includes a first voltage supply circuit that supplies a voltage to the first semiconductor layer, and a second voltage supply circuit that supplies a voltage to at least one of the first control terminal and the second control terminal.

[0017] This allows appropriate voltages to be supplied to the first semiconductor layer and at least one of the first control terminal and the second control terminal, respectively, thereby achieving both high-resolution image acquisition and distance measurement with low power consumption.

[0018] An imaging device according to a fourth aspect of the present disclosure is the imaging device according to the second aspect, wherein the drive circuit includes a first voltage supply circuit that supplies a voltage to the first semiconductor layer, and the first voltage supply circuit includes a first signal line that is set to a first potential, a second signal line that is set to a second potential that is different from the first potential, and a first connection circuit that switches between the first signal line and the second signal line depending on the operating mode and connects them to the first semiconductor layer.

[0019] This allows multiple voltage levels (potentials) to be set on the two signal lines, and by switching the connection relationship between the first semiconductor layer and the two signal lines, the voltage level of the voltage supplied to the first semiconductor layer can be easily changed.

[0020] An imaging device according to a fifth aspect of the present disclosure is the imaging device according to the fourth aspect, wherein the second potential is lower than the first potential, and the first connection circuit connects the first signal line to the first semiconductor layer when the first operating mode is selected, and connects the second signal line to the first semiconductor layer when the second operating mode is selected.

[0021] As a result, in the second operation mode, by lowering the voltage level of the voltage supplied to the first semiconductor layer, it is possible to efficiently read out the signal charges from the photoelectric conversion unit even if the fluctuation width (amplitude) of the voltage of the transfer transistor is small, thereby enabling high-speed and accurate readout of the signal charges and improving the distance measurement accuracy.

[0022] An imaging device according to a sixth aspect of the present disclosure is an imaging device according to any one of the second, fourth, and fifth aspects, wherein the drive circuit includes a second voltage supply circuit that supplies a voltage to at least one of the first control terminal and the second control terminal, and the second voltage supply circuit includes one or more third signal lines that are set to at least one of a third potential and a fourth potential higher than the third potential, one or more fourth signal lines that are set to at least one of a fifth potential and a sixth potential higher than the fifth potential, and a second connection circuit that switches the one or more third signal lines and the one or more fourth signal lines depending on the operating mode to connect them to at least one of the first control terminal and the second control terminal.

[0023] This makes it possible to set multiple voltage levels (potentials) to multiple signal lines, and by switching the connection relationship between the first semiconductor layer and each control terminal and each signal line, the voltage level of the voltage supplied to the first semiconductor layer and each control terminal can be easily changed.

[0024] An imaging device according to a seventh aspect of the present disclosure is an imaging device according to the sixth aspect, wherein the potential difference between the fourth potential and the third potential is different from the potential difference between the sixth potential and the fifth potential.

[0025] This makes it possible to set multiple voltage levels (potentials) to multiple signal lines, and by switching the connection relationship between the first semiconductor layer and each control terminal and each signal line, the voltage level of the voltage supplied to the first semiconductor layer and each control terminal can be easily changed.

[0026] An imaging device according to an eighth aspect of the present disclosure is an imaging device according to the sixth or seventh aspect, wherein the potential difference between the fourth potential and the third potential is greater than the potential difference between the sixth potential and the fifth potential, and the second connection circuit connects the one or more third signal lines to at least one of the first control terminal and the second control terminal when the first operating mode is selected, and connects the one or more fourth signal lines to at least one of the first control terminal and the second control terminal when the second operating mode is selected.

[0027] As a result, in the second operation mode, the fluctuation width (amplitude) of the voltage of the transfer transistor can be reduced, thereby reducing power consumption.

[0028] An imaging device according to a ninth aspect of the present disclosure is an imaging device according to the second, fourth, or fifth aspect, wherein the drive circuit includes a second voltage supply circuit that supplies a voltage to at least one of the first control terminal and the second control terminal, and the second voltage supply circuit includes a seventh signal line that is set to a seventh potential, an eighth signal line that is set to an eighth potential that is different from the seventh potential, and a third connection circuit that switches the seventh signal line and the eighth signal line depending on the operating mode to connect them to at least one of the first control terminal and the second control terminal.

[0029] This makes it possible to easily change the voltage level of the voltage supplied to at least one of the first control terminal and the second control terminal by setting multiple voltage levels (potentials) on the two signal lines and switching the connection relationship between at least one of the first control terminal and the second control terminal and the two signal lines.

[0030] An imaging device according to a tenth aspect of the present disclosure is the imaging device according to the ninth aspect, wherein the eighth potential is lower than the seventh potential, and the third connection circuit connects the seventh signal line to at least one of the first control terminal and the second control terminal when the first operating mode is selected, and connects the eighth signal line to at least one of the first control terminal and the second control terminal when the second operating mode is selected.

[0031] As a result, in the second operation mode, by lowering the voltage level of the voltage supplied to at least one of the first control terminal and the second control terminal, it is possible to efficiently read out signal charges from the photoelectric conversion unit even if the fluctuation width (amplitude) of the voltage of the transfer transistor is small, thereby enabling high-speed and accurate readout of signal charges and improving distance measurement accuracy.

[0032] An imaging device according to an eleventh aspect of the present disclosure is an imaging device according to any one of the second, fourth to tenth aspects, wherein the unit cell includes a capacitor having a first electrode and a second electrode, and a switching element connected in series between the first electrode and the charge storage unit, and the switching element maintains the capacitor and the charge storage unit in a conductive state in the second operating mode, and brings the capacitor and the charge storage unit into a non-conductive state in the first operating mode.

[0033] This allows a portion of the charge stored in the photoelectric conversion unit to also be stored in the capacitor in the second operation mode, thereby achieving high saturation.

[0034] An imaging device according to a twelfth aspect of the present disclosure is an imaging device according to the eleventh aspect, wherein, in the second operating mode, the driving circuit makes the potential supplied to the second electrode lower than the potential supplied to the fourth input / output terminal.

[0035] This allows the potential of the charge storage section and the capacitor to be lowered, so that the signal charge can be read out from the photoelectric conversion section at high speed and with high accuracy, thereby further improving the accuracy of distance measurement.

[0036] A distance measuring device according to a thirteenth aspect of the present disclosure includes a light source, an imaging device according to any one of the first to eighth aspects, and an arithmetic circuit that calculates the distance to an object based on a signal output from the imaging device.

[0037] This makes it possible to obtain high-resolution images and perform distance measurement with low power consumption, similar to the imaging device described above.

[0038] A control method for an imaging device according to a fourteenth aspect of the present disclosure includes, in an operating mode in which at least one of the n pixels is exposed to flashing light of a second wavelength, repeatedly switching between conductive and non-conductive states of the first transfer transistor and the second transfer transistor so that they are not simultaneously in a conductive state during the exposure period to the flashing light of the second wavelength, and, in an operating mode in which at least one of the n pixels is exposed to light of a first wavelength, maintaining the first transfer transistor and the second transfer transistor in a non-conductive state during the exposure period to light of the first wavelength, and switching only the first transfer transistor into a conductive state at a predetermined timing.

[0039] This makes it possible to obtain high-resolution images and perform distance measurement with low power consumption, similar to the imaging device described above.

[0040] In each of the above-described embodiments, the unit cell is formed in a first semiconductor layer, which may be, for example, a substrate, a well, or an epitaxial layer.

[0041] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0042] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0043] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0044] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, such as rectangular, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0045] Furthermore, in this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are applied not only to a case where two components are arranged with a gap between them and another component exists between the two components, but also to a case where two components are arranged closely together and the two components are in contact with each other.

[0046] In this specification, the term "thickness direction" refers to the thickness direction of the substrate, i.e., the direction perpendicular to the main surface of the substrate. Furthermore, unless otherwise specified, the term "plan view" refers to the view from the direction perpendicular to the main surface of the substrate.

[0047] In this specification, the visible light band is considered to be a wavelength band of 380 nm or more and 780 nm or less, and the near-infrared light band is considered to be a wavelength band of 780 nm or more and 2500 nm or less.

[0048] In addition, in this specification, the "input / output terminal" of a transistor means a terminal where a current (charge) or a voltage is input or output, or both. When the transistor is a field effect transistor (FET) such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or a TFT (Thin Film Transistor), the source and drain are the input / output terminals, respectively. When the transistor is a bipolar transistor, the emitter and collector are the input / output terminals, respectively. The gate of an FET and the base of a bipolar transistor are control terminals.

[0049] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0050] (Embodiment) [Endoscope System] First, an endoscope system according to an embodiment will be described with reference to Fig. 1. Fig. 1 is a diagram showing the configuration of an endoscope system 1 according to the present embodiment.

[0051] An endoscope system 1 is an example of a distance measuring device equipped with an imaging device. As shown in Fig. 1, the endoscope system 1 can measure the distance to an object 2 by irradiating light L1 onto the object 2 and receiving light L2 reflected by the object 2 from the irradiated light L1. The endoscope system 1 can also obtain a visible light image of the object 2. The endoscope system 1 according to this embodiment has multiple operating modes. The multiple operating modes include an imaging mode that generates a visible light image and a distance measuring mode that generates a distance image.

[0052] 1, the endoscope system 1 includes a main body 10 and an insertion section 20. The endoscope system 1 is used by inserting the insertion section 20 into the body of a human or animal. That is, the target object 2 is a part of the body.

[0053] The main body 10 is a part of the endoscope system 1 that is not inserted into the body. As shown in Fig. 1 , the main body 10 includes a light source 11, a light source drive circuit 12, an ISP (Image Signal Processor) 13, an output unit 14, a system control circuit 15, and a power supply IC (Integrated Circuit) 16.

[0054] The light source 11 emits light to illuminate the object 2. Specifically, the light source 11 can emit light of a first wavelength for the imaging mode and flashing light of a second wavelength for the ranging mode. The first wavelength is, for example, included in the visible light band. The light of the first wavelength is, for example, white light. The second wavelength is a wavelength different from the first wavelength. For example, the second wavelength is included in the near-infrared light band. The flashing light is light whose brightness changes periodically. The flashing light has a frequency cycle of, for example, 1 MHz or more and 200 MHz or less, and is, for example, 50 MHz, but is not limited to this.

[0055] The light source 11 includes, for example, an LED (Light Emitting Diode), a semiconductor laser element, or an organic EL (Electroluminescence) element. As an example, the light source 11 includes a blue LED or blue laser element that emits blue light and a yellow phosphor that is excited by the blue light to emit yellow light, and emits white light as light of a first wavelength that is a mixture of the blue light and the yellow light. The light source 11 also includes a near-infrared laser element that emits near-infrared light as blinking light of a second wavelength.

[0056] The light source drive circuit 12 is a circuit that drives the light source 11, and specifically controls the timing of turning on and off the light source 11. The light source drive circuit 12 generates power for turning on the light source 11 based on, for example, power supplied from the power supply IC 16, and supplies the generated power to the light source 11. The light source drive circuit 12 can control the timing of turning on and off the light source 11 by adjusting the timing of starting and stopping the supply of power to the light source 11.

[0057] The light source drive circuit 12 is configured by combining one or more of various electronic components such as ICs, resistors, transistors, diodes, capacitors, inductors, and transformers. The light source drive circuit 12 may be configured integrally with other components such as a power supply IC 16 or a system control circuit 15.

[0058] The ISP 13 is an example of an arithmetic circuit, and processes signals output from the imaging device 100, i.e., sensor output data. In imaging mode, the ISP 13 uses the sensor output data to generate a visible light image. In ranging mode, the ISP 13 uses the sensor output data to calculate the distance to the object 2. The ISP 13 generates a distance image that indicates the distance to the object 2 for each pixel. The visible light image and the distance image are each a still image or a moving image (video).

[0059] The output unit 14 outputs the visible light image and the distance image generated by the ISP 13. For example, the output unit 14 is a communication IF for wired or wireless communication with an external device such as a display. For example, the output unit 14 is an output terminal to which a communication cable can be connected. Alternatively, the output unit 14 may include an antenna and a wireless processing circuit.

[0060] The system control circuit 15 performs overall control of the endoscope system 1. Specifically, the system control circuit 15 selects (switches) the operation mode of the endoscope system 1 and outputs control signals to each component included in the endoscope system 1 according to the selected operation mode.

[0061] The system control circuit 15 is realized, for example, by an LSI (Large Scale Integration) integrated circuit. The integrated circuit is not limited to an LSI and may be a dedicated circuit or a general-purpose processor. For example, the system control circuit 15 may be a microcontroller. The microcontroller includes, for example, a nonvolatile memory storing a program, a volatile memory serving as a temporary storage area for executing the program, input / output ports, and a processor for executing the program. The system control circuit 15 may also be a programmable FPGA (Field Programmable Gate Array) or a reconfigurable processor in which the connections and settings of circuit cells within the LSI can be reconfigured. The functions performed by the system control circuit 15 may be realized by software or hardware.

[0062] The power supply IC 16 is a power supply circuit that processes power supplied from an external power source such as a commercial power source or a power storage device, etc. For example, the power supply IC 16 includes an AC / DC converter and / or a DC / DC converter.

[0063] 1, the endoscope system 1 may include an operation unit that accepts operation input from a user. The operation unit may be a physical operation button or operation switch, or may be a touch panel or the like. The operation unit may be a communication IF that accepts operation input via a remote control terminal such as a remote controller.

[0064] The insertion section 20 is a flexible section, and at least its tip portion (the end portion opposite the main body section 10) is inserted into the body when the endoscope system 1 is in use. The length of the insertion section 20 is between 3 m and 5 m, but is not particularly limited. As shown in FIG. 1 , the insertion section 20 includes a light-guiding member 21, an objective lens 22, a condenser lens 23, and an imaging device 100.

[0065] The light guide member 21 guides the light emitted by the light source 11 to the tip portion and emits the light as light L1 from the tip portion toward the object 2. The light guide member 21 is, for example, an optical fiber, but is not limited to this.

[0066] The objective lens 22 and the condenser lens 23 are an optical system that allows the imaging device 100 to receive the reflected light L2 from the object 2. The type and number of lenses are not particularly limited as long as the reflected light L2 can be received by the imaging device 100. Optical elements other than lenses may also be provided.

[0067] The imaging device 100 outputs an image signal obtained by photoelectrically converting reflected light L2 from the object 2. Specifically, in the imaging mode, the imaging device 100 photoelectrically converts light (reflected light L2) that is reflected by the object 2 out of light of a first wavelength emitted from the light source 11. In the distance measurement mode, the imaging device 100 photoelectrically converts light (reflected light L2) that is reflected by the object 2 out of blinking light of a second wavelength emitted from the light source 11.

[0068] The imaging device 100 is connected to the ISP 13 via one or more cables (not shown). The imaging device 100 operates based on sensor control pulses transmitted from the ISP 13 via the cables. The sensor control pulses include, for example, a master clock MCLK and a vertical synchronization signal VD. The imaging device 100 also outputs an image signal to the ISP 13 as sensor output data. In this embodiment, the imaging device 100 is a so-called CMOS (Complementary Metal-Oxide-Semiconductor) image sensor (CIS). The imaging device 100 is, for example, a back-illuminated CIS.

[0069] [Image Capture Apparatus] Next, a specific configuration of the image capture apparatus 100 will be described with reference to Fig. 2. Fig. 2 is a diagram showing the configuration of the image capture apparatus 100 according to this embodiment.

[0070] 2 , the imaging device 100 includes a sensor array 110, a drive circuit 130, and a signal output circuit 140. The imaging device 100 also includes a plurality of control lines 150, a plurality of power supply lines (not shown), and a plurality of vertical signal lines 160.

[0071] The sensor array 110 includes a plurality of unit cells 120 arranged two-dimensionally in a matrix. The number of unit cells 120 is, for example, several hundred or several thousand or more in each of the row and column directions, but is not limited to this. The plurality of unit cells 120 are provided in a first semiconductor layer. The first semiconductor layer is, for example, a substrate. The substrate is, for example, a semiconductor substrate containing a semiconductor such as silicon as a main component. The first semiconductor layer may be a well region or an epitaxial layer.

[0072] Each of the unit cells 120 has n pixels, where n is a natural number. Each of the n pixels includes a photoelectric conversion unit. Specific configurations of the pixels and the unit cells 120 will be described later.

[0073] In Fig. 2, the area surrounded by a dashed line in the sensor array 110 is the effective pixel area. Effective pixels are pixels used for recording and outputting video signals and for distance measurement calculations. Pixels other than the effective pixels are also called dummy pixels, and in Fig. 2, they are arranged around the effective pixel area. Dummy pixels do not necessarily have to be provided, and all the pixels of the unit cells 120 included in the sensor array 110 may be effective pixels.

[0074] The drive circuit 130 is a circuit that controls each of the multiple unit cells 120. The drive circuit 130 and each unit cell 120 are electrically connected by multiple control lines 150. The drive circuit 130 drives each control line 150 in accordance with one operation mode selected from multiple operation modes. Specifically, the drive circuit 130 controls the exposure timing, signal output timing, etc. of each pixel included in each unit cell 120 by outputting a control signal to each control line 150. The drive circuit 130 may also change the value (potential, voltage level) of the power supply voltage supplied to the multiple power supply lines. Specific configurations and operation examples of the drive circuit 130 will be described later.

[0075] The signal output circuit 140 is connected to each unit cell 120 via a plurality of vertical signal lines 160. The signal output circuit 140 outputs signals read out from each unit cell 120 or each pixel via the plurality of vertical signal lines 160 to the ISP 13 as image signals.

[0076] [Unit Cell] Next, a specific circuit configuration of the unit cell 120 will be described with reference to Fig. 3. Fig. 3 is a diagram showing the circuit configuration of the unit cell 120 according to this embodiment.

[0077] Since the multiple unit cells 120 provided in the sensor array 110 have the same configuration, the following description will be given of only one of them as a representative. In addition, in this embodiment, the number n of pixels included in the unit cell 120 is 4.

[0078] 3 , the unit cell 120 includes four pixels 201, 202, 203, and 204, and a charge storage unit FD for storing charges generated in the four pixels 201, 202, 203, and 204. The unit cell 120 further includes a reset transistor 121, a capacitance-connected transistor 122, a capacitor 123, a readout transistor 124, and a selection transistor 125.

[0079] Furthermore, control lines TG1, TG2, TG3, and TG4, PRS1, PRS2, PRS3, and PRS4, and RS, GC, and SEL are connected to the unit cell 120 as a plurality of control lines 150. The control lines TG1, TG2, TG3, and TG4, PRS1, PRS2, PRS3, and PRS4, and RS, GC, and SEL are connected to the same components of each of the plurality of unit cells 120 arranged in the row direction. For example, the control line TG1 is an example of a first control line and is connected to the gate of the first transfer transistor 221 of each pixel 201 of the plurality of unit cells 120 arranged in the row direction. The control line PRS1 is an example of a second control line and is connected to the gate of the second transfer transistor 231 of each pixel 201 of the plurality of unit cells 120 arranged in the row direction. Furthermore, for example, the control line RS is connected to the gate of each reset transistor 121 of a plurality of unit cells 120 arranged in the row direction.

[0080] The unit cell 120 is also provided with a plurality of power supply lines, including power supply lines AVDDP and VMIM, and a power supply line GND (not shown) set to ground potential. The ground potential is an example of a reference potential, e.g., 0 V. The power supply lines AVDDP, VMIM, and GND are each connected to the same components of the plurality of unit cells 120 arranged in at least one of the row and column directions. For example, the power supply line VMIM is connected to one electrode (second electrode) of the capacitor 123 of each of the plurality of unit cells 120 arranged in a matrix. At least one of the plurality of power supply lines may be a power supply line for supplying a voltage (substrate voltage) to a substrate on which the plurality of unit cells 120 (plurality of pixels) are provided.

[0081] The four pixels 201, 202, 203, and 204 correspond to red pixels (R), green pixels (Gr, Gb), and blue pixels (B) required to generate an RGB image (color image), which is an example of a visible light image. Specifically, pixels 201 and 204 are green pixels (Gr, Gb), pixel 202 is a red pixel (R), and pixel 203 is a blue pixel (B). RGB are arranged in a so-called Bayer array. Note that the RGB array is not particularly limited.

[0082] Furthermore, each of the four pixels 201, 202, 203, and 204 has sensitivity not only to the visible light band but also to a second wavelength (near-infrared light band), which allows each of the four pixels 201, 202, 203, and 204 to receive blinking light of the second wavelength, thereby generating a distance image.

[0083] The pixel 201 includes a photoelectric conversion unit 211, and a first transfer transistor 221 and a second transfer transistor 231 connected to the photoelectric conversion unit 211. The pixel 201 may have a filter (not shown) that passes green light (light of a first wavelength) and near-infrared light (light of a second wavelength) among incident light, and suppresses the passage of light other than these.

[0084] The photoelectric conversion unit 211 photoelectrically converts incident light to generate an amount of charge corresponding to the light intensity. The photoelectric conversion unit 211 is, for example, a photodiode provided in the substrate. The photoelectric conversion unit 211 is sensitive to both green light and near-infrared light.

[0085] The anode of the photoelectric conversion unit 211 (photodiode) is connected to the ground potential. The cathode of the photoelectric conversion unit 211 is connected to each of the first transfer transistor 221 and the second transfer transistor 231. The connection point between the first transfer transistor 221, the second transfer transistor 231, and the photoelectric conversion unit 211 is illustrated as node N1.

[0086] The first transfer transistor 221 is an FET having a gate, a source, and a drain. The gate of the first transfer transistor 221 is an example of a first control terminal and is connected to a control line TG1. One of the source and drain of the first transfer transistor 221 is an example of a first input / output terminal and is connected to the photoelectric conversion unit 211. The other of the source and drain of the first transfer transistor 221 is an example of a second input / output terminal different from the first input / output terminal and is connected to the charge accumulation unit FD.

[0087] The second transfer transistor 231 is an FET having a gate, a source, and a drain. The gate of the second transfer transistor 231 is an example of a second control terminal and is connected to a control line PRS1. One of the source and the drain of the second transfer transistor 231 is an example of a third input / output terminal and is connected to the photoelectric conversion unit 211. The other of the source and the drain of the second transfer transistor 231 is an example of a fourth input / output terminal different from the third input / output terminal and is connected to a power supply line AVDDP.

[0088] The pixel 202 includes a photoelectric conversion unit 212, and a first transfer transistor 222 and a second transfer transistor 232 connected to the photoelectric conversion unit 212. The pixel 202 may have a filter (not shown) that passes red light (light of a first wavelength) and near-infrared light (light of a second wavelength) among incident light, and suppresses the passage of light other than these.

[0089] The photoelectric conversion unit 212 converts incident light into an electric charge in an amount corresponding to the light intensity. The photoelectric conversion unit 212 is, for example, a photodiode provided in the substrate. The photoelectric conversion unit 212 is sensitive to both red light and near-infrared light.

[0090] The anode of the photoelectric conversion unit 212 (photodiode) is connected to the ground potential. The cathode of the photoelectric conversion unit 212 is connected to each of the first transfer transistor 222 and the second transfer transistor 232. The connection point between the first transfer transistor 222, the second transfer transistor 232, and the photoelectric conversion unit 212 is illustrated as node N2.

[0091] The first transfer transistor 222 is an FET having a gate, a source, and a drain. The gate of the first transfer transistor 222 is an example of a first control terminal and is connected to a control line TG2. One of the source and drain of the first transfer transistor 222 is an example of a first input / output terminal and is connected to the photoelectric conversion unit 212. The other of the source and drain of the first transfer transistor 222 is an example of a second input / output terminal different from the first input / output terminal and is connected to the charge accumulation unit FD.

[0092] The second transfer transistor 232 is an FET having a gate, a source, and a drain. The gate of the second transfer transistor 232 is an example of a second control terminal and is connected to a control line PRS2. One of the source and the drain of the second transfer transistor 232 is an example of a third input / output terminal and is connected to the photoelectric conversion unit 212. The other of the source and the drain of the second transfer transistor 232 is an example of a fourth input / output terminal different from the third input / output terminal and is connected to a power supply line AVDDP.

[0093] The pixel 203 includes a photoelectric conversion unit 213, and a first transfer transistor 223 and a second transfer transistor 233 connected to the photoelectric conversion unit 213. The pixel 203 may have a filter (not shown) that passes blue light (light of a first wavelength) and near-infrared light (light of a second wavelength) among incident light, and suppresses the passage of light other than these.

[0094] The photoelectric conversion unit 213 photoelectrically converts incident light to generate an amount of charge corresponding to the light intensity. The photoelectric conversion unit 213 is, for example, a photodiode provided in the substrate. The photoelectric conversion unit 213 is sensitive to both blue light and near-infrared light.

[0095] The anode of the photoelectric conversion unit 213 (photodiode) is connected to the ground potential. The cathode of the photoelectric conversion unit 213 is connected to each of the first transfer transistor 223 and the second transfer transistor 233. The connection point between the first transfer transistor 223, the second transfer transistor 233, and the photoelectric conversion unit 213 is illustrated as node N3.

[0096] The first transfer transistor 223 is an FET having a gate, a source, and a drain. The gate of the first transfer transistor 223 is an example of a first control terminal and is connected to a control line TG3. One of the source and drain of the first transfer transistor 223 is an example of a first input / output terminal and is connected to the photoelectric conversion unit 213. The other of the source and drain of the first transfer transistor 223 is an example of a second input / output terminal different from the first input / output terminal and is connected to the charge accumulation unit FD.

[0097] The second transfer transistor 233 is an FET having a gate, a source, and a drain. The gate of the second transfer transistor 233 is an example of a second control terminal and is connected to a control line PRS3. One of the source and the drain of the second transfer transistor 233 is an example of a third input / output terminal and is connected to the photoelectric conversion unit 213. The other of the source and the drain of the second transfer transistor 233 is an example of a fourth input / output terminal different from the third input / output terminal and is connected to a power supply line AVDDP.

[0098] The pixel 204 includes a photoelectric conversion unit 214, and a first transfer transistor 224 and a second transfer transistor 234 connected to the photoelectric conversion unit 214. The pixel 204 may have a filter (not shown) that passes green light (light of a first wavelength) and near-infrared light (light of a second wavelength) among incident light, and suppresses the passage of light other than these.

[0099] The photoelectric conversion unit 214 converts incident light into an electric charge in an amount corresponding to the light intensity. The photoelectric conversion unit 214 is, for example, a photodiode provided in the substrate. The photoelectric conversion unit 214 is sensitive to both green light and near-infrared light.

[0100] The anode of the photoelectric conversion unit 214 (photodiode) is connected to the ground potential. The cathode of the photoelectric conversion unit 214 is connected to each of the first transfer transistor 224 and the second transfer transistor 234. The connection point between the first transfer transistor 224, the second transfer transistor 234, and the photoelectric conversion unit 214 is illustrated as node N4.

[0101] The first transfer transistor 224 is an FET having a gate, a source, and a drain. The gate of the first transfer transistor 224 is an example of a first control terminal and is connected to a control line TG4. One of the source and drain of the first transfer transistor 224 is an example of a first input / output terminal and is connected to the photoelectric conversion unit 214. The other of the source and drain of the first transfer transistor 224 is an example of a second input / output terminal different from the first input / output terminal and is connected to the charge accumulation unit FD.

[0102] The second transfer transistor 234 is an FET having a gate, a source, and a drain. The gate of the second transfer transistor 234 is an example of a second control terminal and is connected to a control line PRS4. One of the source and the drain of the second transfer transistor 234 is an example of a third input / output terminal and is connected to the photoelectric conversion unit 214. The other of the source and the drain of the second transfer transistor 234 is an example of a fourth input / output terminal different from the third input / output terminal and is connected to a power supply line AVDDP.

[0103] The charge storage unit FD is shared by four pixels 201, 202, 203, and 204. Specifically, the charge storage unit FD can store charges generated in the photoelectric conversion units 211, 212, 213, and 214 of each pixel. The charge storage unit FD is an impurity region provided in a semiconductor substrate, and plugs, wiring, and the like connected to the impurity region.

[0104] The reset transistor 121 is provided to reset the potential of the charge storage unit FD. The reset transistor 121 is an example of a switching element and is connected in series between the power supply line AVDDP and the charge storage unit FD. In this embodiment, the reset transistor 121 is connected to the charge storage unit FD via the capacitance-connected transistor 122. The reset transistor 121 is an FET having a gate, a source, and a drain. The gate of the reset transistor 121 is connected to a control line RS. One of the source and the drain of the reset transistor 121 is connected to the power supply line AVDDP. The other of the source and the drain of the reset transistor 121 is connected to the charge storage unit FD via the capacitance-connected transistor 122. When the reset transistor 121 is made conductive (in this embodiment, the capacitance-connected transistor 122 is also made conductive), the charge storage unit FD is connected to the power supply line AVDDP, and the potential of the charge storage unit FD is reset.

[0105] The capacitance-connection transistor 122 is provided to switch the connection between the capacitor 123 and the charge storage unit FD. The capacitance-connection transistor 122 is an example of a switching element, and is connected in series between the capacitor 123 and the charge storage unit FD. The capacitance-connection transistor 122 is an FET having a gate, a source, and a drain. The gate of the capacitance-connection transistor 122 is connected to a control line GC. One of the source and drain of the capacitance-connection transistor 122 is connected to one electrode (first electrode) of the capacitor 123. The other of the source and drain of the capacitance-connection transistor 122 is connected to the charge storage unit FD. The capacitance-connection transistor 122 may also be used to reset the potential of the charge storage unit FD.

[0106] The capacitor 123 is provided to increase the amount of charge that can be stored in the unit cell 120 and widen the dynamic range. The capacitor 123 has a first electrode and a second electrode. The first electrode of the capacitor 123 is connected to the charge storage unit FD via the capacitance-connected transistor 122. The second electrode of the capacitor 123 is connected to the power supply line VMIM. When the capacitance-connected transistor 122 is conductive, a portion of the charge flowing from each pixel into the charge storage unit FD can be stored in the capacitor 123. The capacitor 123 is, for example, a capacitor having an MIM (Metal Insulator Metal) structure provided above a semiconductor substrate, but the specific configuration is not particularly limited. For example, parasitic capacitance due to wiring, electrodes, etc. may be used as the capacitor 123.

[0107] The readout transistor 124 is provided to read out the charge stored in the charge storage unit FD, specifically, to output a signal corresponding to the amount of charge to the vertical signal line 160. The readout transistor 124 is an FET having a gate, a source, and a drain. The gate of the readout transistor 124 is connected to the charge storage unit FD. One of the source and drain of the readout transistor 124 is connected to the power supply line AVDDP. The other of the source and drain of the readout transistor 124 is connected to the vertical signal line 160 via the selection transistor 125.

[0108] The selection transistor 125 is provided to control the timing at which the readout transistor 124 reads out the charge stored in the charge storage unit FD. The selection transistor 125 is an FET having a gate, a source, and a drain. The gate of the selection transistor 125 is connected to a control line SEL. One of the source and drain of the selection transistor 125 is connected to the readout transistor 124. The other of the source and drain of the selection transistor 125 is connected to a vertical signal line 160. When the selection transistor 125 is made conductive, the readout transistor 124 reads out the charge.

[0109] Each transistor included in the unit cell 120 includes impurity regions provided in a semiconductor substrate as a source and a drain, and an electrode provided above the semiconductor substrate with a gate insulating film interposed therebetween as a gate. Two transistors connected in series may share an impurity region. For example, the other of the source and drain of the reset transistor 121 and one of the source and drain of the capacitor-connected transistor 122 may share one impurity region.

[0110] The above-described configuration of the unit cell 120 is merely an example and can be modified as appropriate. For example, the number n of pixels included in the unit cell 120 may be 1, 2, or 5 or more. Furthermore, for example, the selection transistor 125 may be connected between the readout transistor 124 and the power supply line AVDDP. Furthermore, for example, the capacitance-connected transistor 122 and the capacitor 123 may not be provided. Furthermore, for example, each transistor included in the unit cell 120 is an n-channel transistor, but may also be a p-channel transistor. Alternatively, each transistor may also be a bipolar transistor.

[0111] [Operation] Next, the operation of the endoscope system 1 according to this embodiment will be described.

[0112] As described above, the endoscope system 1 has a plurality of operation modes including the imaging mode and the distance measurement mode. The imaging device 100 included in the endoscope system 1 performs different operations depending on the operation mode.

[0113] The imaging mode is an example of a first operation mode of the imaging device 100, and is an operation mode in which at least one of the n pixels 201 to 204 included in the unit cell 120 is exposed to light of a first wavelength. In this embodiment, the imaging mode is an RGB mode that generates an RGB image (color image), and therefore all four pixels 201 to 204 included in the unit cell 120 are exposed to light. In the RGB mode, the light source 11 emits white light as light of the first wavelength, and the reflected light is received by each pixel of the imaging device 100. Note that an RGB image is an image in which each pixel of the image corresponds to a unit cell 120 of the imaging device 100 and includes each RGB value (brightness value).

[0114] The ranging mode is an example of a second operating mode of the image capture device 100, and is an operating mode in which at least one of the n pixels 201 to 204 included in the unit cell 120 is exposed to flashing light of a second wavelength. In this embodiment, the ranging mode is a ToF (Time of Flight) mode that uses a ToF method. In the ToF mode, the distance to the object 2 is calculated based on the time it takes for light emitted from the light source 11 to return to each pixel via the object 2 (the time of flight of light), and a distance image is generated. Specifically, in the ToF mode, the light source 11 emits flashing light in the near-infrared light band as flashing light of a second wavelength, and the reflected light is received by at least one of the multiple pixels of the image capture device 100. Note that the distance image is an image in which each pixel represents the distance to the object 2.

[0115] FIG. 4 is a diagram showing an example of switching of operating modes in the imaging device 100 according to the present embodiment. As shown in FIG. 4, the RGB mode and the ToF mode are continuously switched alternately. This allows RGB images and distance images to be obtained in one measurement (one insertion of the insertion unit 20 into the body). While avoiding contact of the insertion unit 20 into the body based on the distance image, visual confirmation of the inside of the body based on the RGB image can be performed simultaneously in parallel. Note that switching between the RGB mode and the ToF mode may be performed manually based on a user's operational input, etc.

[0116] Although details will be described later, in the control method of the imaging device 100 according to this embodiment, in the ToF mode, during the exposure period to the blinking light of the second wavelength (reflected light L2), the first transfer transistor and the second transfer transistor are repeatedly switched between conductive and non-conductive states so that they are not simultaneously conductive. Also, in the RGB mode, during the exposure period to the light of the first wavelength (reflected light L2), the first transfer transistor and the second transfer transistor are maintained in a non-conductive state, and only the first transfer transistor is switched to a conductive state at a predetermined timing (within a pulse period). This makes it possible to achieve both high-precision distance measurement and the acquisition of high-resolution RGB images.

[0117] [ToF Mode] Next, a specific example of the ToF mode will be described.

[0118] The ToF mode is performed by irradiating the target 2 with flashing light, receiving the light (flashing light) reflected by the target 2, and processing the electrical signal obtained by photoelectric conversion. The ToF mode includes a CW (Continuous-Wave)-ToF method that uses continuous waves (light), and a pulsed ToF method that uses pulsed light.

[0119] Fig. 5 is a diagram for explaining a distance measurement method based on the CW-ToF method. As shown in Fig. 5, the intensity of the light irradiated onto the target object 2 changes continuously at a predetermined period. The irradiated light is a continuous wave with a constant period and amplitude. The period of the intensity change is expressed as 1 / fmod, where fmod is the modulation frequency.

[0120] The reflected light has a phase delay φ compared to the irradiated light depending on the distance to the object 2. In the CW-ToF method, the irradiated light is received for each exposure section, which is obtained by dividing the cycle of the irradiated light into four sections, and the phase delay φ is calculated based on equation (1) using the intensities C0, C1, C2, and C3 for each exposure section.

[0121]

[0122] If the speed of light is c, the distance Z to the object 2 is expressed by equation (2) using the phase delay φ.

[0123]

[0124] Although the reflected light contains background light components (noise components), the background light components are cancelled out because the difference in intensity is calculated in each of the numerator and denominator on the right side of equation (1).

[0125] In the CW-ToF method, the accuracy of distance measurement can be improved by increasing the modulation frequency fmod. On the other hand, as the modulation frequency fmod increases, the measurable range (measurable distance range) becomes smaller. The maximum measurable distance Z is Z ｍａｘ This is because, in equation (2), when φ=2π (=360°), it is expressed as c / (2fmod). To address the reduction in the ranging range, the ranging range can be expanded by performing ranging using a plurality of different modulation frequencies and combining the ranging results.

[0126] 6 is a diagram for explaining a distance measurement method based on the pulse ToF method. As shown in FIG. 6, pulsed light having a pulse width (period) Tp is repeatedly irradiated onto the target 2 at predetermined time intervals.

[0127] The reflected light is delayed by a certain time ΔT compared to the pulsed light depending on the distance to the object 2. In the pulse ToF method, light is received in at least two exposure intervals set at different times relative to the pulsed light. In the example shown in FIG. 6 , the first exposure interval is set to be the same interval as the pulsed light, the second exposure interval is set to be an interval that starts simultaneously with the cessation of the pulsed light, and the third exposure interval is set to be an interval in which reflected light cannot be received. The third exposure interval is provided to detect the background light component BG. If the background light component BG is sufficiently small, the third exposure interval does not need to be set.

[0128] The distance Z to the object 2 is expressed by the following equation (3) based on the delay time ΔT.

[0129]

[0130] A0 and A1 are the intensities of the reflected light received in the first exposure section and the second exposure section, respectively. Specifically, A0 is obtained by subtracting the signal intensity (background light component BG) obtained in the third exposure section from the signal intensity obtained in the first exposure section. A1 is obtained by subtracting the signal intensity (background light component BG) obtained in the third exposure section from the signal intensity obtained in the second exposure section.

[0131] In the pulse ToF method, the accuracy of distance measurement can be improved by shortening the pulse width Tp. On the other hand, if the pulse width Tp is increased, the measurable range (measurable distance range) becomes smaller. The maximum measurable distance Z is Z ｍａｘ This is because, in equation (3), when A0 = 0, it is expressed as (c × Tp) / 2. To cope with a reduction in the distance measurement range, the distance measurement range can be expanded by performing distance measurement with multiple exposures and combining the distance measurement results.

[0132] [CW-ToF Method] The specific operation of the imaging device 100 in the CW-ToF distance measurement mode will be described below.

[0133] In this embodiment, the reset transistor 121, the capacitance-connection transistor 122, the selection transistor 125, the first transfer transistors 221, 222, 223, and 224, and the second transfer transistors 231, 232, 233, and 234 included in the unit cell 120 are all in a conductive state (ON) when the voltage level (potential) supplied to their gates is high (High), and are in a non-conductive state (OFF) when the voltage level (potential) supplied to their gates is low (Low).

[0134] 7A and 7B, a first driving example of the CW-ToF imaging device 100 will be described. In the first driving example, all of the four pixels 201 to 204 included in the unit cell 120 are used for distance measurement.

[0135] Fig. 7A is a timing chart showing a first driving example in a CW-ToF distance measurement mode, and Fig. 7B is a diagram showing the relationship between the irradiated light and the reflected light and each frame period in the first driving example shown in Fig. 7A.

[0136] 7A, RS indicates the change over time in the voltage level (potential) of the control line RS connected to the gate of the reset transistor 121. GC indicates the change over time in the voltage level (potential) of the control line GC connected to the gate of the capacitance-connected transistor 122. VMIM indicates the change over time in the voltage level (potential) of the power supply line VMIM connected to the second electrode of the capacitor 123.

[0137] PRSn (n = 1 to 4) respectively represent the change over time in the voltage level (potential) of the control lines PRS1, PRS2, PRS3, and PRS4 connected to the gates of the second transfer transistors 231, 232, 233, and 234. TG1, TG2, TG3, and TG4 respectively represent the change over time in the voltage level (potential) of the control lines TG1, TG2, TG3, and TG4 connected to the gates of the first transfer transistors 221, 222, 223, and 224. In this specification, TG1 to TG4 may be expressed as TGn (n = 1 to 4).

[0138] Frame 1, frame 2, frame 3, and frame 4 are frame periods of the same length. The frame period corresponds to a unit period of processing by the imaging device 100 (endoscopic system 1). Frame 1, frame 2, frame 3, and frame 4 each include an exposure period and a readout period.

[0139] The exposure period is a period during which each pixel included in the unit cell 120 receives reflected light. The readout period is a period during which the charge accumulated in the charge accumulation unit FD (and capacitor 123) is read out to the vertical signal line 160. The readout process is the same as the readout process performed by a general CMOS image sensor, so a description thereof will be omitted. Note that during the readout period, the control line RS goes high, resetting the potential of the charge accumulation unit FD. This suppresses signal mixing between frames and improves distance measurement accuracy.

[0140] The four squares arranged in two rows and two columns shown in the bottom row of Fig. 7A correspond to the four pixels 201, 202, 203, and 204 included in the unit cell 120. C0, C1, C2, and C3 shown in the squares represent the types of signal intensities obtained at each pixel for each frame, and specifically correspond to C0, C1, C2, and C3 shown in Fig. 5.

[0141] During the exposure period, the voltage levels of the control lines TG1 to TG4 and the control lines PRS1 to PRS4 alternate between high and low levels, i.e., the first transfer transistors 221 to 224 and the second transfer transistors 231 to 234 alternate between on and off.

[0142] Here, the voltage levels of the control lines TG1 to TG4 change in the same phase. That is, the first transfer transistors 221 to 224 turn on and off at the same timing. Similarly, the voltage levels of the control lines PRS1 to PRS4 change in the same phase. The second transfer transistors 231 to 234 turn on and off at the same timing.

[0143] In addition, for one pixel, the high and low levels of the control lines PRSn and TGn are mutually exclusive. In other words, the voltage levels of the control lines PRSn and TGn are 180° out of phase with each other.

[0144] That is, within one pixel, the on / off states of the first transfer transistor and the on / off states of the second transfer transistor are mutually exclusive. For example, while the first transfer transistor 221 is on, the second transfer transistor 231 is off, and while the first transfer transistor 221 is off, the second transfer transistor 231 is on.

[0145] In each frame and each pixel, when the second transfer transistors 231 to 234 are turned off (when the control line PRSn switches from high to low), the charge generated in the photoelectric conversion units 211 to 214 can be accumulated (the charge accumulation period begins). The charge generated in the photoelectric conversion units 211 to 214 is accumulated in the charge accumulation unit FD (and the capacitor 123) via the first transfer transistors 221 to 224. When the first transfer transistors 221 to 224 are turned off (when the control line TGn switches from high to low), the accumulation of the charge generated in the photoelectric conversion units 211 to 214 ends (the charge accumulation period ends). When the first transfer transistors 221 to 224 are turned off, the second transfer transistors 231 to 234 are turned on, so the potentials of the photoelectric conversion units 211 to 214 and the nodes N1 to N4 can be reset. In this embodiment, the charge accumulation period of each pixel is substantially the same as the ON period of the first transfer transistor (or the OFF period of the second transfer transistor).

[0146] In the example shown in Fig. 7A, the charge accumulation periods of frames 1 to 4 correspond to the first to fourth exposure sections shown in Fig. 5. Here, the length of the charge accumulation period is half the period of the irradiated light (equivalent to 180°), and is set so that the phase shifts by 90° in the order of frames 1 to 4. Therefore, there is no overlap in the charge accumulation periods between frames 1 and 3, and there is no overlap in the charge accumulation periods between frames 2 and 4.

[0147] As shown in Figure 7B, during each charge accumulation period (period during which the signal level is high) of frames 1 to 4, signal intensities C0 to C3 are obtained according to the intensity of the reflected light. Since charge accumulation periods are repeatedly set within the exposure period in each frame period, even if the signal intensity obtained during each charge accumulation period is weak, a sufficiently strong signal intensity can be obtained within the exposure period. Furthermore, variation between charge accumulation periods can be suppressed. This allows for an improved signal-to-noise ratio.

[0148] In addition, in the first driving example, all four pixels 201 to 204 are used to detect reflected light. The signal charge obtained from each of the four pixels 201 to 204 can be accumulated in the charge accumulation unit FD. This makes it possible to suppress variations between pixels, further increasing the signal-to-noise ratio.

[0149] As described above, in the first driving example, the four pixels 201 to 204 included in the unit cell 120 are exposed to the reflected light L2 at different timings for each frame period. The exposure start and end timings for the four pixels 201 to 204 are the same within each frame period. Signal intensities C0 to C3 can be obtained within the exposure period in order from frame 1 to frame 4. The signal intensities C0 to C3 are read from each of the unit cells 120 and output from the imaging device 100 to the ISP 13 as sensor output data. Using the signal intensities C0 to C3 for each unit cell 120, the ISP 13 can calculate the distance to the object 2 for each unit cell 120 using the above-described equations (1) and (2), thereby generating a distance image.

[0150] 7A, the voltage level of the control line GC is maintained at a high level. That is, the capacitance-connected transistor 122 is always on, and the charge storage unit FD and the capacitor 123 are connected. This allows charge to be stored in the capacitor 123 as well. This increases the amount of charge that can be stored, thereby widening the dynamic range.

[0151] <Second Driving Example> Next, a second driving example of the CW-ToF imaging device 100 will be described with reference to Fig. 8. In the second driving example, only two of the four pixels 201 to 204 included in the unit cell 120 are used for distance measurement.

[0152] Fig. 8 is a timing chart showing a second driving example of the CW-ToF ranging mode. Note that the contents represented by RS, GC, VMIM, PRS1 to PRS4, and TG1 to TG4 in Fig. 8 are the same as those in Fig. 7A. The following explanation will focus on the differences from the first driving example, and will omit a description of the commonalities.

[0153] In this driving example, pixels 201 and 204 are used for distance measurement, and pixels 202 and 203 are not used. Specifically, in each frame period, the voltage levels of control lines PRS2 and PRS3 are maintained at a high level, and the voltage levels of control lines TG2 and TG3 are maintained at a low level, so that charges generated in pixels 202 and 203 are not accumulated in the charge accumulation unit FD. The changes over time in the voltage levels of control lines PRS1 and PRS4 and control lines TG1 and TG4 are the same as in the first driving example shown in FIG. 7A. Therefore, signal charges generated in the photoelectric conversion unit 211 of pixel 201 and the photoelectric conversion unit 214 of pixel 204 are accumulated in the charge accumulation unit FD in each of frames 1 to 4.

[0154] In this driving example, only two of the four pixels are used, but this is not limiting. The number of pixels used may be only one or only three. That is, if the unit cell 120 includes n pixels, only m pixels (m is a natural number less than n) may be used in the CW-ToF ranging mode. That is, in the ranging mode, m pixels may be exposed to reflected light L2 without using all n pixels. Since the number of pixels to be driven can be reduced, power consumption can be reduced.

[0155] <Third Driving Example> Next, a third driving example of the CW-ToF imaging device 100 will be described with reference to FIGS. 9A and 9B.

[0156] Fig. 9A is a timing chart showing a third driving example of the CW-ToF ranging mode. Note that the contents represented by RS, GC, VMIM, PRS1 to PRS4, and TG1 to TG4 in Fig. 9A are the same as those in Fig. 7A. The following explanation will focus on the differences from the first driving example, and will omit a description of the commonalities.

[0157] 9A, the charge accumulation period differs for each Pix group (unit cell 120) within one frame period. Specifically, the phase of the time change in the voltage level of the control line PRSn (n = 1 to 4) is set to shift by 90° in the order of Pix group 0, Pix group 1, Pix group 2, and Pix group 3. Within each Pix group (unit cell 120), the voltage levels of PRSn (n = 1 to 4) change in the same phase.

[0158] The same is true for the control lines TGn (n = 1 to 4). The control lines TGn (n = 1 to 4) are set so that the phase of the time change in the voltage level is shifted by 90° in the order of Pix group 0, Pix group 1, Pix group 2, and Pix group 3. Within a Pix group (unit cell 120), the voltage levels of TGn (n = 1 to 4) change in the same phase.

[0159] In this way, by making the charge accumulation period different for each unit cell 120 within one frame period, it is possible to suppress the occurrence of motion blur.

[0160] In this embodiment, an example in which a charge accumulation unit FD is provided common to the four pixels 201 to 204 has been shown, but a charge accumulation unit (memory) may be provided in each pixel. In this case, as shown in FIG. 9B, the charge accumulation period of each pixel can be made different within one frame period. In other words, the timing of the start and end of exposure for each of the four pixels can be made different within the frame period. FIG. 9B is a timing chart showing a modified example of the third driving example in the CW-ToF ranging mode.

[0161] Specifically, the time change in the voltage levels of the control lines PRS1 to PRS4 is set so that the phases are shifted by 90° in this order. The time change in the voltage levels of the control lines TG1 to TG4 is set so that the phases are shifted by 90° in this order. In this case as well, motion blur can be suppressed.

[0162] [Pulse ToF Method] Next, a specific operation of the imaging device 100 in a distance measurement mode using the pulse ToF method will be described with reference to FIGS. 10A, 10B, and 10C.

[0163] FIG. 10A is a timing chart showing an example of driving in a distance measurement mode using the pulse ToF method. FIG. 10B is a diagram showing the relationship between the irradiated light and the reflected light and each frame period in the example shown in FIG. 10A. FIG. 10C is a diagram showing an example of control signals supplied to two transfer transistors in the example shown in FIG. 10A. Note that the contents represented by RS, GC, VMIM, PRS1 to PRS4, and TG1 to TG4 in FIG. 10A are the same as those in FIG. 7A. The following description will focus on the differences from the first driving example using the CW-ToF method, and will omit a description of the commonalities.

[0164] As shown in FIG. 10A, the charge accumulation periods of frames 1 to 3 correspond to the first to third exposure intervals shown in FIG. 6. Specifically, as shown in FIG. 10B, in frame 1, the charge accumulation period is set in the same interval as the irradiated light (pulsed light). In frame 2, the charge accumulation period is set in an interval that starts simultaneously with the cessation of the irradiated light. In frame 3, the charge accumulation period is set in an interval where no reflected light is present. That is, in frame 3, the light source 11 stops emitting light. The length of the charge accumulation period of each frame is the same as the pulse width of the irradiated light. In frame 3, the signal intensity A2 of the background light (corresponding to the background light component BG in FIG. 6) is obtained. By using the signal intensity A2 of the background light, the signal intensities A0 and A1 of the reflected light can be obtained from the detection results of frames 1 and 2, respectively. Using the obtained signal intensities A0 and A1, the distance to the object 2 can be calculated for each unit cell 120 using the above-described equation (3), and a distance image can be generated.

[0165] As shown in Figure 10C, the charge accumulation period is the period from the time when the second transfer transistors 231 to 234 are turned off (when the control line PRSn is switched from high level to low level) to the time when the first transfer transistors 221 to 224 are turned off (when the control line TGn is switched from high level to low level).

[0166] As shown in FIG. 10C, the rising edge of the voltage level of the control line TGn is delayed relative to the falling edge of the voltage level of the control line PRSn. Furthermore, the rising edge of the voltage level of the control line PRSn is delayed relative to the falling edge of the voltage level of the control line TGn. This prevents the first transfer transistors 221-224 and the second transfer transistors 231-234 from being turned on simultaneously. This prevents unexpected inflow and / or outflow of charge stored in the charge storage unit FD, thereby improving the accuracy of distance measurement. This driving method can also be used in the CW-ToF method.

[0167] Even in the pulse ToF method, some of the four pixels included in the unit cell 120 may not be used. That is, if the unit cell 120 includes n pixels, only m pixels (m is a natural number less than n) may be used in the pulse ToF ranging mode. Reducing the number of pixels to be driven can reduce power consumption.

[0168] [RGB Mode] Next, a specific operation of the imaging device 100 in the RGB mode will be described.

[0169] First Driving Example First, a first driving example of the imaging device 100 in RGB mode will be described with reference to Fig. 11. In the first driving example, the capacitor-connected transistor 122 is used to reset the charge storage unit FD.

[0170] Fig. 11 is a timing chart showing a first driving example in RGB mode. The contents represented by RS, GC, VMIM, PRS1 to PRS4, and TG1 to TG4 in Fig. 11 are the same as those in Fig. 7A. The following explanation will focus on the differences from the first driving example of the CW-ToF method, and will omit explanation of the commonalities.

[0171] 11 is a period (half horizontal period) that is half the length of the horizontal period H and corresponds to a frame period in the ranging mode. The horizontal period H is a period for reading out pixels that are arranged in the row direction among the multiple pixels included in the imaging device 100.

[0172] In the example shown in FIG. 11 , the voltage level of the control line GC is set to a high level at the beginning of a half horizontal period, thereby resetting the potential of the charge storage unit FD. Since the voltage level of the control line RS is maintained at a high level, the reset transistor 121 is maintained in a conductive state (ON). Therefore, by turning on the capacitance-connected transistor 122, the charge storage unit FD and the power supply line AVDDP can be made conductive. The power supply line VMIM is maintained at a constant voltage level. The voltage level of the power supply line VMIM is maintained at, for example, the same voltage level as the power supply line AVDDP. The voltage level of the power supply line VMIM is not particularly limited and may be maintained at, for example, 0 V.

[0173] In the RGB mode, the voltage level of the control line PRSn is maintained at a low level. The voltage levels of the control lines TG1 to TG4 are maintained at a low level except for a predetermined pulse period (charge accumulation period). For example, in frame 1, the voltage level of the control line TG1 becomes a high level, and the first transfer transistor 221 is turned on. As a result, the charge (corresponding to the intensity of green light) generated by the photoelectric conversion unit 211 is accumulated in the charge accumulation unit FD. Although not shown in FIG. 11 , after the voltage level of the control line TG1 switches from a high level to a low level, the selection transistor 125 is turned on and the charge is read out to the vertical signal line 160 at a predetermined timing during the period in frame 1 in which the voltage level is maintained at a low level.

[0174] In frame 2, the voltage level of the control line TG2 is set to high, thereby turning on the first transfer transistor 222. As a result, the charge (corresponding to the intensity of red light) generated in the photoelectric conversion unit 212 is accumulated in the charge accumulation unit FD and then read out. In frame 3, the voltage level of the control line TG3 is set to high, thereby turning on the first transfer transistor 223. As a result, the charge (corresponding to the intensity of blue light) generated in the photoelectric conversion unit 213 is accumulated in the charge accumulation unit FD and then read out. In frame 4, the voltage level of the control line TG4 is set to high, thereby turning on the first transfer transistor 224. As a result, the charge (corresponding to the intensity of green light) generated in the photoelectric conversion unit 214 is accumulated in the charge accumulation unit FD and then read out.

[0175] In this way, the signal intensities of each of the RGB can be obtained from the unit cells 120. The RGB signal intensities are read out from each of the plurality of unit cells 120 and output as sensor output data from the imaging device 100 to the ISP 13. The ISP 13 can generate an RGB image using the RGB signal intensities of each unit cell 120.

[0176] According to the first driving example, signal readout is performed with the capacitance-connected transistor 122 turned off, and the charge storage unit FD is reset by turning on the capacitance-connected transistor 122. By setting the capacitance component connected to the gate of the readout transistor 124 to a small capacitance of only the charge storage unit FD, signal readout with high gain becomes possible.

[0177] <Second Driving Example> Next, a second driving example of the imaging device 100 in the RGB mode will be described with reference to Fig. 12. In the second driving example, the reset transistor 121 is used to reset the charge storage unit FD.

[0178] Fig. 12 is a timing chart showing a second driving example in RGB mode. The contents represented by RS, GC, VMIM, PRS1 to PRS4, and TG1 to TG4 in Fig. 12 are the same as those in Fig. 7A. The following explanation will focus on the differences from the first driving example of the CW-ToF method, and will omit explanation of the commonalities.

[0179] In the example shown in FIG. 12 , the voltage level of the control line RS is set to a high level at the beginning of a half horizontal period, thereby resetting the potential of the charge storage unit FD. Since the voltage level of the control line GC is maintained at a high level, the capacitance-connected transistor 122 is maintained in a conductive state (ON). Therefore, by turning on the reset transistor 121, the charge storage unit FD and the power supply line AVDDP can be made conductive. The power supply line VMIM is maintained at a constant voltage level. The voltage level of the power supply line VMIM is maintained at, for example, the same voltage level as the power supply line AVDDP. The voltage level of the power supply line VMIM is not particularly limited and may be maintained at, for example, 0 V.

[0180] According to the second driving example, the capacitance-connected transistor 122 is maintained in an on state, the reset transistor 121 is kept off, and the signal is read out, and the charge storage unit FD is reset by turning on the reset transistor 121. The capacitance component connected to the gate of the readout transistor 124 can be increased by the charge storage unit FD and the capacitor 123, making it possible to read out a signal at a low gain. The low gain makes it possible to read out a saturated signal without exceeding the dynamic range of the subsequent circuit.

[0181] [Capacitor] Next, the function of the capacitor 123 will be described with reference to FIGS. 13A and 13B.

[0182] 13A and 13B are diagrams showing the potentials in the unit cell 120 in the RGB mode and the ToF mode, respectively.

[0183] In Figures 13A and 13B, PRS, TG, GC, and RS correspond to the control lines PRS, TG, GC, and RS, respectively, and represent the gates of the second transfer transistor 231 (or any of 232 to 234), the first transfer transistor 221 (or any of 222 to 224), the capacitance-connected transistor 122, and the reset transistor 121. Low indicates that the voltage level of the corresponding control line is low, and the corresponding transistor is in an off state. High indicates that the voltage level of the corresponding control line is high, and the corresponding transistor is in an on state. Pulse indicates that a signal that alternates between high and low levels is supplied. PD indicates the photoelectric conversion unit 211 (or any of 212 to 214), FD indicates the charge storage unit FD, and MIM indicates the capacitor 123. The circles shown near PD and FD represent signal charges.

[0184] 13A , in the RGB mode, the first transfer transistor 221 and the second transfer transistor 231 are in an off state while the photoelectric conversion unit 211 is exposed to light. Therefore, the generated signal charge is accumulated in the photoelectric conversion unit 211, node N1, etc. When reading out a signal, the first transfer transistor 221 is turned on, and then the selection transistor 125 (not shown) is turned on, thereby reading out the signal to the vertical signal line 160. In the RGB mode, noise can be suppressed by reading out the signal at a high gain without using the capacitor 123.

[0185] On the other hand, in the ToF mode, the capacitor-connected transistor 122 is maintained in an on state. Therefore, as shown in Fig. 13B, the signal charges generated in the photoelectric conversion units 211 to 214 are accumulated in the charge accumulation unit FD and the capacitor 123. By increasing the amount of accumulated charge, high saturation can be achieved.

[0186] As described above, in this embodiment, the capacitance-connected transistor 122 maintains the capacitor 123 and the charge storage unit FD in a conductive state in the ToF mode, and does not conduct the capacitor 123 and the charge storage unit FD in the RGB mode, thereby achieving both highly accurate distance measurement and the acquisition of high-quality RGB images.

[0187] [Relationship between Transfer Transistors and Control Lines] Next, the relationship between the first transfer transistor and the second transfer transistor in each pixel and the control lines connected to their gates will be described with reference to Fig. 14. In the following, pixel 201 will be described as a representative, but the same applies to pixels 202 to 204.

[0188] 14 is a schematic plan view showing an example of a pixel 201 according to the present embodiment. The photoelectric conversion unit 211 has a rectangular (square or oblong) shape in plan view, for example. The photoelectric conversion unit 211 includes a p-type semiconductor region and an n-type semiconductor region provided on a semiconductor substrate (see FIG. 23A shown later). The n-type semiconductor region and the p-type semiconductor region are stacked in the thickness direction of the substrate. The p-type semiconductor region is provided closer to the surface (upper surface) of the semiconductor substrate than the n-type semiconductor region.

[0189] As shown in FIG. 14 , a gate 221g of the first transfer transistor 221 and a gate 231g of the second transfer transistor 231 are provided so as to overlap a portion of the photoelectric conversion unit 211 in a plan view. An insulating film (not shown) is provided between the gates 221g and 231g and the photoelectric conversion unit 211 (p-type semiconductor region). The gates 221g and 231g are each formed using a conductive material such as metal or conductive polysilicon. The shape of each of the gates 221g and 231g in a plan view is rectangular, but is not limited to this. In this embodiment, the material, shape, and size of the gates 221g and 231g are the same.

[0190] The term "same size" not only means that the areas (or volumes) are completely equal, but also includes cases where the difference in area (or volume) is 5% or less of the area (or volume) of one gate. The term "same shape" not only means that the shapes are completely identical, but also includes cases where the difference in area (or volume) due to the difference in shape is 5% or less of the area (or volume) of the other gate. The term "same material" not only means that the composition ratios of the materials are completely identical, but also includes cases where the difference in composition ratio is 5% or less of the other gate. Differences in size, shape, and material due to manufacturing errors, as well as differences in composition ratio due to impurities inevitably mixed in during manufacturing, are also considered "same." While the "5% or less" limit is defined in consideration of current manufacturing errors, it is not necessarily limited to 5% if the error is acceptable as a manufacturing or design factor. These terms apply not only to gates 221g and 231g, but also to the materials, shapes, and sizes of other components (e.g., the control lines described below).

[0191] The gate 221g is connected to the drive circuit 130 via a wiring 241 and a via 241v. Specifically, the wiring 241 is arranged above the gate 221g via an interlayer insulating film (not shown) so as to overlap the gate 221g in a plan view. The via 241v penetrates the interlayer insulating film and connects the wiring 241 and the gate 221g. The wiring 241 and the via 241v constitute a control line TG1, which is an example of a first control line.

[0192] The gate 231g is connected to the drive circuit 130 via a wiring 251 and a via 251v. Specifically, the wiring 251 is arranged above the gate 231g via an interlayer insulating film (not shown) so as to overlap the gate 231g in a plan view. The via 251v penetrates the interlayer insulating film and connects the wiring 251 and the gate 231g. The wiring 251 and the via 251v constitute a control line PRS1, which is an example of a second control line.

[0193] In this embodiment, the load of the control line TG1 is equal to the load of the control line PRS1. Specifically, the load of the control line TG1 from the drive circuit 130 to the gate 221g is equal to the load of the control line PRS1 from the drive circuit 130 to the gate 231g. The load of the control line is the parasitic resistance and parasitic capacitance (RC components) of the control line. Specifically, the RC components of the wiring 241 and the via 241v are equal to the RC components of the wiring 251 and the via 251v.

[0194] The term "equal loads (RC components)" does not only mean that the loads are completely equal, but also includes the case where the difference between the loads is 5% or less of one of the loads. However, if an error is allowable as a manufacturing factor or design element, it is not necessarily limited to 5%.

[0195] For example, the control line TG1 and the control line PRS1 are identical in material, shape, and size. Specifically, the wiring 241 and the wiring 251 are identical in material, shape, and size. The vias 241v and the vias 251v are identical in material, shape, and size. By making the materials, shapes, and sizes identical, it is possible to easily equalize the loads between the wirings and between the vias. In other words, it is easy to select materials and design layouts to equalize the loads.

[0196] In this embodiment, in a plan view of the unit cell 120, the control line TG1 and the first transfer transistor 221, and the control line PRS1 and the second transfer transistor 231 are arranged in line symmetry with respect to a straight line (the dashed line in FIG. 14 ) that passes through the center of the photoelectric conversion unit 211. By arranging them in line symmetry, the loads on the control lines TG1 and PRS1 can be easily made equal. In other words, a layout can be easily designed to make the loads equal.

[0197] The load on the control line can be a factor that dulls the waveform of the control signal output from the drive circuit 130. In particular, in the ToF mode, the control lines TG1 and PRS1 alternately alternate between high and low levels at high speeds, and if the waveform of one of the lines dulls more than the other, a difference occurs in the amount of accumulated charge, which can lead to a decrease in distance measurement accuracy.

[0198] In contrast, in this embodiment, the load of the control line TG1 is equal to the load of the control line PRS1. As a result, even if the waveform of the control signal output from the drive circuit 130 is dulled, the difference in dullness between the control lines TG1 and PRS1 can be reduced. As a result, it is possible to suppress a decrease in distance measurement accuracy.

[0199] In addition, in this embodiment, the number of effective pixels connected to the control line TG1 is equal to the number of effective pixels connected to the control line PRS1, which makes it easy to equalize the loads on the control line TG1 and the control line PRS1, thereby preventing a decrease in distance measurement accuracy.

[0200] 14 shows an example in which the control lines TG1 and PRS1 are made of the same material, have the same shape, and are arranged symmetrically with respect to a line, but this is not limiting. As shown in FIG. 15A, the control lines TG1 and PRS1 may have different shapes.

[0201] 15A is a schematic plan view showing another example of the pixel 201 according to the present embodiment. In the example shown in Fig. 15A, the gate 221g of the first transfer transistor 221 is connected to the drive circuit 130 via wirings 241a and 241b and vias 241v, 241c, and 241d.

[0202] The wiring 241b is located at a different height from the wiring 241a and is connected to the wiring 241a through vias 241c and 241d. For example, there are cases where the control line TG1 and the control line PRS1 cannot be located at the same height (same layer) due to the presence of other wirings or electrodes. The example shown in FIG. 15A is an example that addresses such a case.

[0203] In addition, when a control line includes multiple wirings located at different heights, the wiring that occupies the largest proportion of the total distance from the drive circuit 130 to the connection to the first transfer transistor or the second transfer transistor is referred to as the main wiring. For example, in FIG. 15A , if the ratio of the distance between wiring 241a and wiring 241b in the total distance from the drive circuit 130 to gate 221g is 1:9, then wiring 241b is the main wiring of control line TG1. For example, in the example shown in FIG. 14 , wiring 241 is the main wiring of control line TG1, and wiring 251 is the main wiring of control line PRS1. Wiring 241 and wiring 251 are equal in height. On the other hand, FIG. 15A shows an example in which wiring 241b, the main wiring of control line TG1, and wiring 251, the main wiring of control line PRS1, are different in height.

[0204] The control line TG1 has a longer path than the control line PRS1. Normally, as the path becomes longer, the wiring resistance increases. Therefore, the wiring 241b is made thicker than the wiring 241a. In other words, by making the cross-sectional area of ​​the wiring 241b larger than the cross-sectional area of ​​the wiring 241a, the wiring resistance of the wiring 241b can be reduced. By adjusting the wiring resistance in this manner, the load of the control line TG1 and the load of the control line PRS1 can be made equal. Note that the load of the control line TG1 and the load of the control line PRS1 may also be made equal by using different materials for the control lines TG1 and PRS1. As long as the load of the control line TG1 and the load of the control line PRS1 can be made equal, there are no particular limitations on the specific method for achieving this.

[0205] 15B to 15F are all schematic plan views showing another example of a pixel 201 according to this embodiment. In the example shown in FIG. 15B, the number of vias 241v is different from the number of vias 251v. The number of vias 241v is an example of the number of first contacts connecting a first control line (control line TG1) and a first transfer transistor 221. The number of vias 251v is an example of the number of second contacts connecting a second control line (control line PRS1) and a second transfer transistor 231. In the example shown in FIG. 15B, the number of vias 241v is three, while the number of vias 251v is one. Note that the numbers of vias 241v and 251v may be the same, but the shapes of the vias 241v and 251v may be different. Alternatively, the vias 241v and 251v may differ in both number and shape.

[0206] In this way, the loads on the two control lines TG1 and PRS1 can be adjusted by varying the number of contacts, and the difference in the dullness of the waveforms of the control signals transmitted through the two control lines TG1 and PRS1 can be reduced, thereby suppressing a decrease in distance measurement accuracy.

[0207] 15C , in a plan view of the unit cell 120, the control line TG1 and the first transfer transistor 221, and the control line PRS1 and the second transfer transistor 231 are disposed at positions rotated 180° with respect to the center Q of the photoelectric conversion unit 211. That is, the first transfer transistor 221 and the second transfer transistor 231 have a positional relationship and shapes that are point-symmetric with respect to the center Q of the photoelectric conversion unit 211.

[0208] 15D , in a plan view of the unit cell 120, the control line TG1 and the first transfer transistor 221, and the control line PRS1 and the second transfer transistor 231 are arranged symmetrically with respect to a straight line (a dashed-dotted line in the figure) that passes through the center of the photoelectric conversion unit 211. In the example shown in Fig. 15D , the gate 221g of the first transfer transistor 221 and the gate 231g of the second transfer transistor 231 are each arranged to overlap one of the four sides of the photoelectric conversion unit 211, which has a rectangular shape in a plan view. In this way, the first transfer transistor 221 and the second transfer transistor 231 may be arranged at a position offset to one side from the center of the photoelectric conversion unit 211.

[0209] 15E , in a plan view of the unit cell 120, the control line TG1 and the first transfer transistor 221, and the control line PRS1 and the second transfer transistor 231 are arranged at positions rotated by 90° with respect to the center Q of the photoelectric conversion unit 211. Specifically, the control line TG1 and the first transfer transistor 221 are arranged at a position rotated by 90° clockwise from the control line PRS1 and the second transfer transistor 231. Note that the rotation direction may be counterclockwise.

[0210] In each drawing, only the first transfer transistor 221 and the second transfer transistor 231 may be arranged line-symmetrically with respect to a straight line passing through the center of the photoelectric conversion unit 211, or may be arranged at a position rotated 90° or 180° with respect to the center Q of the photoelectric conversion unit 211. In other words, the control lines TG1 and PRS2 do not have to be arranged line-symmetrically with respect to a straight line passing through the center of the photoelectric conversion unit 211, and may not have to be arranged at a position rotated 90° or 180° with respect to the center Q of the photoelectric conversion unit 211.

[0211] 15F, the first transfer transistor 221 and the second transfer transistor 231 are not symmetrical to each other, and the control line TG1 and the control line PRS1 are not symmetrical to each other. In the example shown in FIG. 15F, in a plan view, at least one of the distance D1 between the first side 221ga of the gate 221g and the first line VL1 and the distance D2 between the second side 231ga of the gate 231g and the second line VL2 is longer than the length D of one side of the photoelectric conversion unit 211. ＰＤ The first side 221ga is the side closest to the center Q of the photoelectric conversion unit 211 among the four sides of the gate 221g. The second side 231ga is the side closest to the center Q of the photoelectric conversion unit 211 among the four sides of the gate 231g. The first straight line VL1 is a side that passes through the center Q of the photoelectric conversion unit 211 and is parallel to the first side 221ga. The second straight line VL2 is a side that passes through the center Q of the photoelectric conversion unit 211 and is parallel to the second side 231ga. The length D ＰＤ is, for example, the length of the shortest side of the four sides of the photoelectric conversion unit 211, but is not limited to this.

[0212] In this way, the positions of the gates 221g and 231g can be adjusted so that they are not too far away from the photoelectric conversion unit 211. In other words, it is possible to adjust the load such as parasitic capacitance. This makes it possible to reduce the difference in the dullness of the waveforms of the control signals transmitted through the two control lines TG1 and PRS1, thereby suppressing a decrease in distance measurement accuracy.

[0213] 15A to 15F , the load of the control line TG1 and the load of the control line PRS1 may be made equal by appropriately adjusting and arranging the control lines TG1 and PRS1 and the first transfer transistor 221 and the second transfer transistor 231 according to the material, shape, size, and the like of the control lines TG1 and PRS1. In other words, as long as the load of the control line TG1 and the load of the control line PRS1 can be made equal, there are no particular limitations on the specific method for achieving this.

[0214] [Specific Configuration and Operation of the Drive Circuit] Next, a specific configuration and operation of the drive circuit 130 will be described. Note that, of the multiple pixels controlled by the drive circuit 130, the following description will be given taking pixel 201 as an example. Pixels 202 to 204 are similar to pixel 201, and therefore description thereof will be omitted.

[0215] <Configuration> First, the configuration of the drive circuit 130 will be described with reference to Fig. 16 and Fig. 17. Fig. 16 is a diagram showing the configuration of the drive circuit 130 according to the present embodiment. Fig. 17 is a diagram showing the circuit configurations of a pixel control circuit 136 and a substrate voltage supply circuit 134 according to the present embodiment.

[0216] The drive circuit 130 according to this embodiment supplies a voltage corresponding to one operation mode selected from a plurality of operation modes to the substrate 170, or to the first control terminal of the first transfer transistor or the second control terminal of the second transfer transistor. Specifically, the drive circuit 130 changes the voltage level of the voltage supplied to the substrate 170 according to the operation mode. The drive circuit 130 also changes the magnitude (potential) of at least one of the high level and low level of the voltage supplied to the gate of the first transfer transistor and the gate of the second transfer transistor according to the operation mode.

[0217] As shown in FIG. 16, the drive circuit 130 includes an operation mode control circuit 132 , a substrate voltage supply circuit 134 , and a pixel control circuit 136 .

[0218] The operation mode control circuit 132 is an example of a mode control circuit, and controls the substrate voltage supply circuit 134 and the pixel control circuit 136 according to the operation mode. Specifically, the operation mode control circuit 132 outputs a first control signal according to one operation mode selected from a plurality of operation modes to the substrate voltage supply circuit 134. The operation mode control circuit 132 also outputs a second control signal according to one operation mode selected from the plurality of operation modes to the pixel control circuit 136.

[0219] Substrate voltage supply circuit 134 is an example of a first voltage supply circuit, and supplies a voltage to substrate 170. Substrate voltage supply circuit 134 can change the value (voltage level) of the voltage supplied to substrate 170 based on a first control signal output from operation mode control circuit 132. As shown in FIG. 17 , substrate voltage supply circuit 134 includes two signal lines 311 and 312 and a first connection circuit 321.

[0220] The signal line 311 is an example of a first signal line set to a first potential. The first potential is, for example, the ground potential (0 V). The signal line 311 is a ground wiring set to the ground potential.

[0221] The signal line 312 is an example of a second signal line that is set to a second potential that is different from the first potential. Specifically, the second potential is lower than the first potential. The second potential is, for example, −1 V, but is not limited to this.

[0222] The first connection circuit 321 switches between the signal lines 311 and 312 depending on the operation mode and connects them to the substrate 170. In the present embodiment, the first connection circuit 321 switches between the signal lines 311 and 312 based on a first control signal and connects them to the substrate 170. Specifically, when the imaging mode is selected, the first connection circuit 321 connects the signal line 311 to the substrate 170. When the ranging mode is selected, the first connection circuit 321 connects the signal line 312 to the substrate 170.

[0223] 17, the first connection circuit 321 includes two switching elements 301 and 302. For example, the switching elements 301 and 302 are FETs each having a gate, a source, and a drain.

[0224] The switching element 301 switches between conduction and non-conduction between the signal line 311 and the substrate 170. The gate of the switching element 301 is connected to the operation mode control circuit 132 and receives an input of a first control signal. One of the source and drain of the switching element 301 is connected to the signal line 311. The other of the source and drain of the switching element 301 is connected to the substrate 170.

[0225] The switching element 302 switches between conduction and non-conduction between the signal line 312 and the substrate 170. The gate of the switching element 302 is connected to the operation mode control circuit 132 via an inverter 135 and receives an input of a first control signal. One of the source and drain of the switching element 302 is connected to the signal line 312. The other of the source and drain of the switching element 302 is connected to the substrate 170.

[0226] A signal obtained by inverting the first control signal input to the gate of switching element 301 is input to the gate of switching element 302 via inverter 135. Therefore, switching elements 301 and 302 operate mutually exclusive. Specifically, when switching element 301 is on, switching element 302 is turned off, and when switching element 302 is on, switching element 301 is turned off.

[0227] The pixel control circuit 136 is an example of a second voltage supply circuit, and supplies a voltage to at least one of the gate 221g of the first transfer transistor 221 and the gate 231g of the second transfer transistor 231. The pixel control circuit 136 can change the value (voltage level) of the voltage supplied to the gates 221g and 231g based on a second control signal output from the operation mode control circuit 132. As shown in FIG. 17 , the pixel control circuit 136 includes signal lines 313a, 313b, 314a, and 314b, and a second connection circuit 322.

[0228] The signal lines 313a and 313b are an example of one or more third signal lines set to at least one of a third potential and a fourth potential higher than the third potential. Specifically, the signal line 313a is set to the third potential (low level). The third potential is, for example, −1.4 V, but is not limited to this and may be, for example, −1 V. In this embodiment, the signal line 313a is the same as the signal line 312, but may be different. The signal line 313b is set to the fourth potential (high level). The fourth potential is, for example, 3.3 V, but is not limited to this and may be, for example, 2.8 V or 3.8 V.

[0229] The signal lines 314a and 314b are examples of one or more fourth signal lines that are set to at least one of a fifth potential and a sixth potential higher than the fifth potential. Specifically, the signal line 314a is set to the fifth potential (low level). The fifth potential is, for example, ground potential (0 V). The signal line 314a is a ground wiring set to ground potential. The signal line 314a may be the same as the signal line 311. The signal line 314b is set to the sixth potential (high level). The sixth potential is, for example, 2 V, but is not limited to this and may be 1.2 V.

[0230] The signal line 314a is an example of a seventh signal line set to a seventh potential, and the signal line 313a is an example of an eighth signal line set to an eighth potential. In this case, the eighth potential is lower than the seventh potential and corresponds to the third potential (e.g., −1.4 V). In this case, the seventh potential corresponds to the fifth potential (e.g., 0 V).

[0231] The signal line 313b is also an example of a seventh signal line set to a seventh potential, and the signal line 314b is also an example of an eighth signal line set to an eighth potential. In this case, the eighth potential is lower than the seventh potential and corresponds to the sixth potential (e.g., 2 V) described above. The seventh potential in this case corresponds to the fourth potential (e.g., 3.3 V) described above.

[0232] In this embodiment, the potential difference between the fourth potential and the third potential is different from the potential difference between the sixth potential and the fifth potential. Specifically, the potential difference between the fourth potential and the third potential is greater than the potential difference between the sixth potential and the fifth potential. As an example, the potential difference between the fourth potential and the third potential is at least twice the potential difference between the sixth potential and the fifth potential, but may be at least three times the potential difference between the sixth potential and the fifth potential.

[0233] The second connection circuit 322 switches between the signal lines 313a and 313b and the signal lines 314a and 314b depending on the operation mode, and connects them to at least one of the gates 221g and 231g. In the present embodiment, the second connection circuit 322 switches between the signal lines 313a and 313b and the signal lines 314a and 314b based on a second control signal, and connects them to the gates 221g and 231g. Specifically, when the imaging mode is selected, the second connection circuit 322 connects the signal lines 313a and 313b to the gates 221g and 231g. Specifically, the second connection circuit 322 connects one of the signal lines 313a and 313b to one of the gates 221g and 231g, and connects the other of the signal lines 313a and 313b to the other of the gates 221g and 231g. That is, the signal lines 313a and 313b are not connected to the same gate at the same time. Furthermore, when the distance measurement mode is selected, the second connection circuit 322 connects the signal lines 314a and 314b to the gates 221g and 231g. Specifically, the second connection circuit 322 connects one of the signal lines 314a and 314b to one of the gates 221g and 231g, and connects the other of the signal lines 314a and 314b to the other of the gates 221g and 231g. That is, the signal lines 314a and 314b are not connected to the same gate at the same time.

[0234] As shown in FIG. 17, the second connection circuit 322 includes switching elements 301n, 302n, 303n, 304n, 305n, 306n, 301p, 302p, 303p, 304p, 305p, and 306p, and a control signal generation circuit 323.

[0235] Each of the switching elements 301n to 306n is an n-channel FET having a gate, a source, and a drain, and each of the switching elements 301p to 306p is a p-channel FET having a gate, a source, and a drain.

[0236] The switching elements 301n and 301p are configured to select one of the set of low-level signal lines 313a and 314a and the set of high-level signal lines 313b and 314b and connect it to the control line TG1. Specifically, the connection point of the switching elements 301n and 301p (either the source or the drain) is connected to the control line TG1 (gate 221g). The gates of the switching elements 301n and 301p are connected to each other, and a control signal is input from the control signal generation circuit 323. Therefore, when one of the switching elements 301n and 301p is in a conductive state (on), the other is in a non-conductive state (off). Specifically, when switching element 301n is on, the potential of one of signal lines 313a and 314a is supplied to control line TG1 (gate 221g), and when switching element 301p is on, the potential of one of signal lines 313b and 314b is supplied to control line TG1 (gate 221g).

[0237] The switching elements 302n and 302p are configured to select one of the set of low-level signal lines 313a and 314a and the set of high-level signal lines 313b and 314b and connect it to the control line PRS1. Specifically, the connection point of the switching elements 302n and 302p (either the source or the drain) is connected to the control line PRS1 (gate 231g). The gates of the switching elements 302n and 302p are connected to each other, and a control signal is input from the control signal generation circuit 323. Therefore, when one of the switching elements 302n and 302p is in a conductive state (on), the other is in a non-conductive state (off). Specifically, when switching element 302n is on, the potential of one of signal lines 313a and 314a is supplied to control line PRS1 (gate 231g), and when switching element 302p is on, the potential of one of signal lines 313b and 314b is supplied to control line PRS1 (gate 231g).

[0238] The switching element 303n is provided to switch the conduction and non-conduction between the signal line 313a and the control line TG1 (gate 221g). The switching element 304n is provided to switch the conduction and non-conduction between the signal line 313a and the control line PRS1 (gate 231g). The gates of the switching elements 303n and 304n are connected to each other and receive a control signal from the control signal generation circuit 323. Therefore, the switching elements 303n and 304n are simultaneously turned on and off. When the switching element 303n is on and the switching element 301n is on, the potential of the signal line 313a is supplied to the control line TG1. When the switching element 304n is on and the switching element 302n is on, the potential of the signal line 313a is supplied to the control line PRS1.

[0239] The switching element 303p is provided to switch the conduction and non-conduction between the signal line 313b and the control line TG1 (gate 221g). The switching element 304p is provided to switch the conduction and non-conduction between the signal line 313b and the control line PRS1 (gate 231g). The gates of the switching elements 303p and 304p are connected to each other and receive a control signal from the control signal generation circuit 323. Therefore, the switching elements 303p and 304p are simultaneously turned on and off. When the switching element 303p is on and the switching element 301p is on, the potential of the signal line 313b is supplied to the control line TG1. When the switching element 304p is on and the switching element 302p is on, the potential of the signal line 313b is supplied to the control line PRS1.

[0240] The switching element 305n is provided to switch the conduction and non-conduction between the signal line 314a and the control line TG1 (gate 221g). The switching element 306n is provided to switch the conduction and non-conduction between the signal line 314a and the control line PRS1 (gate 231g). The gates of the switching elements 305n and 306n are connected to each other and receive a control signal from the control signal generation circuit 323. Therefore, the switching elements 305n and 306n are simultaneously turned on and off. When the switching element 305n is on and the switching element 301n is on, the potential of the signal line 314a is supplied to the control line TG1. When the switching element 306n is on and the switching element 302n is on, the potential of the signal line 314a is supplied to the control line PRS1.

[0241] The switching element 305p is provided to switch the conduction and non-conduction between the signal line 314b and the control line TG1 (gate 221g). The switching element 306p is provided to switch the conduction and non-conduction between the signal line 314b and the control line PRS1 (gate 231g). The gates of the switching elements 305p and 306p are connected to each other and receive a control signal from the control signal generation circuit 323. Therefore, the switching elements 305p and 306p are simultaneously turned on and off. When the switching element 305p is on and the switching element 301p is on, the potential of the signal line 314b is supplied to the control line TG1. When the switching element 306p is on and the switching element 302p is on, the potential of the signal line 314b is supplied to the control line PRS1.

[0242] The control signal generation circuit 323 controls the on / off of each of the switching elements 301n to 306n and 301p to 304p based on a second control signal from the operation mode control circuit 132. The control signal generation circuit 323 is connected to the gates of each of the switching elements 301n to 306n and 301p to 304p, and outputs a control signal to each gate. The control signal can be either high level or low level.

[0243] <Operation> Next, a specific operation of the drive circuit 130 will be described with reference to FIGS. 18A, 18B, and 18C.

[0244] 18A is a diagram showing an example of the potential supplied to the gate 221g of the first transfer transistor 221 in the RGB mode. Figures 18B and 18C are both diagrams showing examples of the potential supplied to the gate 221g of the first transfer transistor 221 in the ToF mode. In each of Figures 18A to 18C, TG and SUB represent the time changes in the voltage levels (potentials) of the control line TG1 and the substrate 170, respectively.

[0245] 18A, in the RGB mode, the low level of the control line TG1 is −1.4 V, and the high level is 3.3 V. In contrast, as shown in FIGS. 18B and 18C, in the ToF mode, the low level of the control line TG1 is 0 V, and the high level is 2.0 V. In this way, the level difference (potential difference, amplitude) between the high level and low level of the control line TG1 in the ToF mode is smaller than the level difference (potential difference, amplitude) between the high level and low level of the control line TG1 in the RGB mode.

[0246] In RGB mode, a highly saturated photoelectric conversion unit 211 is desirable to obtain high-resolution RGB images. To achieve a highly saturated photoelectric conversion unit 211, the potential of the photoelectric conversion unit 211 must be deep (high), and therefore the potential of the first transfer transistor 221 must be higher when reading out signal charges. In this case, the voltage level supplied to the gate 221g of the first transfer transistor 221 must be increased. In this embodiment, as shown in FIG. 18A , a large difference is ensured between the high and low levels of the control line TG1 (gate 221g). This allows high-resolution RGB images to be obtained.

[0247] On the other hand, in the ToF mode, in order to improve distance measurement accuracy, it is necessary to repeatedly switch the control line TG1 between high and low levels at high speed. However, when the voltage level of the high level is high, the high speed switching increases power consumption.

[0248] Therefore, in this embodiment, as shown in Fig. 18B, the high-level voltage level is suppressed to reduce the level difference between the high level and the low level. This makes it possible to suppress an increase in power consumption. In this way, the imaging device 100 and the endoscope system 1 according to this embodiment can achieve both the acquisition of high-resolution RGB images and distance measurement with reduced power consumption.

[0249] In addition, in the ToF mode, if the level difference of the control line TG1 becomes small, the potential of the photoelectric conversion unit 211 becomes deep, which may prevent sufficient readout of the signal charge from the photoelectric conversion unit 211. In response to this, as shown in Fig. 18C, by lowering the voltage level of the substrate 170, the potential of the photoelectric conversion unit 211 can be lowered, thereby realizing high-speed readout of the signal charge. In this way, the imaging device 100 and the endoscope system 1 according to the present embodiment can achieve both the acquisition of high-resolution RGB images and highly accurate distance measurement with reduced power consumption.

[0250] The operation of the drive circuit 130 for realizing the operation modes shown in FIGS. 18A to 18C will be described below with reference to FIG.

[0251] In the RGB mode shown in FIG. 18A , in the substrate voltage supply circuit 134, switching element 301 maintains an on state and switching element 302 maintains an off state. As a result, ground potential (0 V) is supplied to the substrate 170 from signal line 311. In the pixel control circuit 136, when the voltage level of control line TG1 is set to a low level, switching elements 301 n and 303 n are turned on to supply the potential (−1.4 V) set to signal line 313 a to control line TG1. When the voltage level of control line TG1 is set to a high level, switching elements 301 p and 303 p are turned on to supply the potential (3.3 V) set to signal line 313 b to control line TG1.

[0252] In the RGB mode, the second transfer transistor 231 is maintained in the off state. Specifically, the switching elements 302n and 304n are turned on, and the potential (-1.4 V) set on the signal line 313a is supplied to the control line PRS1.

[0253] In the ToF mode shown in FIG. 18B , in the substrate voltage supply circuit 134, switching element 301 maintains an on state and switching element 302 maintains an off state. As a result, ground potential (0 V) is supplied to the substrate 170 from signal line 311. In the pixel control circuit 136, when the voltage level of control line TG1 is set to a low level, switching elements 301 n and 305 n are turned on to supply the potential (0 V) set to signal line 314 a to control line TG1. When the voltage level of control line TG1 is set to a high level, switching elements 301 p and 305 p are turned on to supply the potential (2.0 V) set to signal line 314 b to control line TG1.

[0254] In the ToF mode, the second transfer transistor 231 is repeatedly switched on and off in a state in which the phase is inverted from that of the first transfer transistor 221. Specifically, when the voltage level of the control line PRS1 is set to a low level, the switching elements 302n and 306n are turned on to supply the potential (0 V) set to the signal line 314a to the control line PRS1. When the voltage level of the control line PRS1 is set to a high level, the switching elements 302p and 306p are turned on to supply the potential (2.0 V) set to the signal line 314b to the control line PRS1.

[0255] In the ToF mode shown in Fig. 18C, the operation of the substrate voltage supply circuit 134 is different from that in the ToF mode shown in Fig. 18B. Specifically, in the substrate voltage supply circuit 134, the switching element 302 maintains the on state, and the switching element 301 maintains the off state. As a result, a potential (-1.4 V) lower than the ground potential is supplied to the substrate 170 from the signal line 312.

[0256] 18A to 18C are merely examples, and various modifications are possible in the RGB mode and the ToF mode.

[0257] 19A is a diagram showing an example of potentials supplied to the gates of the first transfer transistor 221 and the reset transistor 121 in the RGB mode. Fig. 19B is a diagram showing an example of potentials supplied to the gates of the first transfer transistor 221, the second transfer transistor 231, and the reset transistor 121 in the ToF mode. Note that in Figs. 19A and 19B, TG, PRS, and RS represent the time changes in the voltage levels (potentials) of the control lines TG1, PRS1, and RS, respectively.

[0258] In the RGB mode, as shown in Figures 11 and 12, the first transfer transistor 221 is turned on once per frame. Specifically, as shown in Figure 19A, the voltage level of the control line TG1 is maintained at a low level (-1 V), switched to a high level (2.8 V) at a predetermined timing, and then maintained at a low level again. In this case, the level difference between the high level and the low level of the control line TG1 is 3.8 V. This makes it possible to obtain a high-resolution RGB image, as described above.

[0259] In contrast, in the ToF mode, as shown in FIGS. 11 and 12 , the first transfer transistor 221 and the second transfer transistor 231 are repeatedly and exclusively turned on and off at high speed within one frame. Specifically, as shown in FIG. 19B , the voltage level of the control line TG1 alternates between a low level (1.2 V) and a high level (2.8 V). This also applies to the control line PRS1. In this case, the level difference between the high level and the low level of the control line TG1 is 2.6 V. As a result, in the ToF mode, the level difference of the control line TG1 can be made smaller than in the RGB mode, thereby suppressing the increase in power consumption associated with high-speed switching.

[0260] 19A and 19B, the high level value of the control line TG1 is the same. In other words, it is possible to simply change the low level value of the control line TG1, and even in this case, it is possible to achieve both the acquisition of a high-resolution RGB image and distance measurement with reduced power consumption.

[0261] 18C , the voltage level supplied to the substrate 170 may be changed. Fig. 20A is a diagram showing an example of potentials supplied to the gates of the first transfer transistor 221 and the reset transistor 121, and the substrate 170 in the RGB mode. Fig. 20B is a diagram showing an example of potentials supplied to the gates of the first transfer transistor 221, the second transfer transistor 231, and the reset transistor 121, and the substrate 170 in the ToF mode.

[0262] 20A, in the RGB mode, the voltage level supplied to the substrate 170 is 0 V. In the example shown in FIG. 20A, the high level of the control line TG1 is 3.8 V, which achieves even higher saturation of the photoelectric conversion unit 211 in the RGB mode. In other words, it is possible to read out a highly saturated signal from the photodiode.

[0263] 20B, in the ToF mode, the voltage level supplied to the substrate 170 is −1 V, which is lower than that in the RGB mode. This reduces the potential of the photoelectric conversion unit 211 in the ToF mode, thereby enabling faster signal readout.

[0264] In the present embodiment, an example has been described in which the drive circuit 130 changes both the voltage supplied to the substrate and the voltage supplied to the gate of the transfer transistor depending on the operation mode, but this is not limiting. The drive circuit 130 does not need to change either the voltage supplied to the substrate or the voltage supplied to the gate of the transfer transistor. Specifically, the drive circuit 130 may supply a constant voltage to the substrate regardless of the operation mode. Alternatively, the drive circuit 130 may supply the same high-level and low-level values ​​of the voltage supplied to the gate of the transfer transistor regardless of the operation mode.

[0265] 20C , the drive circuit 130 may change the voltage supplied to the substrate 170 during the exposure period and the readout period. Note that Fig. 20C is a diagram showing modified examples of the potentials supplied to the gates of the first transfer transistor 221, the second transfer transistor 231, and the reset transistor 121, and the substrate 170 in the ToF mode.

[0266] Although the present embodiment has shown an example in which two third signal lines and two fourth signal lines are provided, one each may be provided. In this case, the voltage level (potential) set to one third signal line is switched between the third potential and the fourth potential. Similarly, the voltage level (potential) set to one fourth signal line is switched between the fifth potential and the sixth potential.

[0267] In the present embodiment, the drive circuit 130 may control the voltage level of the power supply line VMIM. Fig. 21 is a diagram showing the potential within the unit cell 120 when the voltage of the capacitor 123 is controlled in the ToF mode.

[0268] In the RGB mode, the drive circuit 130 supplies a voltage level V1 to the power supply line VMIM, and in the ToF mode, the drive circuit 130 supplies a voltage level V2 to the power supply line VMIM. The voltage level V2 is higher than the voltage level V1. Note that the voltage level V1 is the same as the voltage level supplied to the power supply line AVDDP, for example. That is, in the ToF mode, the drive circuit 130 makes the potential supplied to the second electrode of the capacitor 123 higher than the potential supplied to the power supply line AVDDP.

[0269] In Fig. 21, the potentials of the charge storage unit FD and the capacitor 123 in the RGB mode are shown by dashed lines. As shown in Fig. 21, in the ToF mode, the potentials of the charge storage unit FD and the capacitor 123 become deeper, which makes it easier to read out signals from the photoelectric conversion unit 211. This enables high-speed readout, thereby improving distance measurement accuracy.

[0270] The capacitor 123 may have an MIM structure, but is not limited to this. For example, a parasitic capacitance generated between a power supply line and a wiring connected to the charge storage unit FD or the source or drain of the capacitor-connected transistor 122 may be used as the capacitor 123.

[0271] [Positional Relationship Between Photoelectric Conversion Unit and Gate of Transfer Transistor] Next, a description will be given of the positional relationship between the photoelectric conversion unit 211 and the gate 221g of the first transfer transistor 221 and the gate 231g of the second transfer transistor 231. Note that, in the following, the pixel 201 will be described as an example out of the multiple pixels to be controlled by the drive circuit 130. Pixels 202 to 204 are similar to pixel 201, and therefore description thereof will be omitted.

[0272] Fig. 22 is a plan view of photoelectric conversion unit 211 according to the present embodiment. Fig. 23A is a cross-sectional view taken along line XXIII-XXIII in Fig. 22. As shown in Fig. 23A, photoelectric conversion unit 211 includes n-type impurity region 211n and p-type impurity region 211p.

[0273] The n-type is an example of the first conductivity type. A state in which the concentration of n-type impurities is high, that is, a state in which the n-type impurities are heavily doped, is called n ＋ The concentration of n-type impurities is low, and the so-called lightly doped state is called n － These are also examples of the first conductivity type. The p-type is an example of the second conductivity type, which is the opposite polarity to the first conductivity type. A state in which the concentration of p-type impurities is high, or in other words, a heavily doped state, is called p ＋ The concentration of p-type impurities is low, and the so-called lightly doped state is called p － When the substrate 170 is a silicon substrate, pentavalent elements such as phosphorus and arsenic can be used as n-type impurities, and trivalent elements such as boron and aluminum can be used as p-type impurities.

[0274] The n-type impurity region 211n is an example of a first semiconductor region, and is provided in the substrate 170. The impurity region 211n is provided closer to the back surface (light incident side) of the substrate 170 than the impurity region 211p.

[0275] The p-type impurity region 211p is an example of a second semiconductor region, and is provided on the impurity region 211n within the substrate 170. The impurity region 211p is provided closer to the surface of the substrate 170 (the side opposite to the light incident side) than the impurity region 211n. The upper surface of the impurity region 211p corresponds to the upper surface of the substrate 170.

[0276] The impurity regions 211n and 211p are formed by doping predetermined regions of the substrate 170 with n-type impurities or p-type impurities by ion implantation or the like. Alternatively, the impurity regions 211n and 211p may be formed by epitaxial growth while selectively introducing impurities into the substrate body.

[0277] In this embodiment, the thickness of the photoelectric conversion unit 211 is 3 μm or less. The thickness of the photoelectric conversion unit 211 corresponds to the depth of the photoelectric conversion unit 211, and is the distance from the upper surface of the substrate 170, i.e., the upper surface of the p-type impurity region 211p, to the lower surface of the n-type impurity region. By reducing the thickness (depth) of the photoelectric conversion unit 211, high-speed readout of signal charges can be achieved.

[0278] If the thickness of the photoelectric conversion unit 211 is 6 μm or more, defects are likely to occur at the interface with the device isolation region (Deep Trench Isolation (DTI)) that separates the photoelectric conversion unit 211 into individual pixels, resulting in increased dark current through the defects. By setting the thickness of the photoelectric conversion unit 211 to 3 μm or less, the generation of dark current can be suppressed, thereby improving ranging accuracy. In particular, when using visible light as light for ranging, highly accurate ranging can be achieved even if the thickness of the photoelectric conversion unit 211 is 3 μm or less. Note that, if interface defects can be sufficiently suppressed, the thickness of the photoelectric conversion unit 211 may be greater than 3 μm.

[0279] 22 , in the present embodiment, the gate 221g of the first transfer transistor 221 and the gate 231g of the second transfer transistor 231 each overlap with the impurity region 211n in a plan view of the substrate 170. In this case, an area S1 where the gate 221g and the impurity region 211n overlap is equal to or greater than half of an area Sg1 of the gate 221g. An area S2 where the gate 231g and the impurity region 211n overlap is equal to or greater than half of an area Sg2 of the gate 231g. Note that the area S1 where the gate 221g and the impurity region 211n overlap may be equal to or greater than 55%, 60%, 70%, or 80% of the area Sg1 of the gate 221g. The area S2 where the gate 231g and the impurity region 211n overlap may be 55% or more, 60% or more, 70% or more, or 80% or more of the area Sg2 of the gate 231g.

[0280] Alternatively, the sum of the area S1 where the gate 221g and the impurity region 211n overlap and the area S2 where the gate 231g and the impurity region 211n overlap is equal to the area S of the photoelectric conversion unit 211. ＰＤ The sum of the area S1 where the gate 221g and the impurity region 211n overlap and the area S2 where the gate 231g and the impurity region 211n overlap is 20% or more of the area S ＰＤ It may be 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, or 80% or more of the total.

[0281] In addition, in the arrangement direction of the gates 221g and 231g (first direction, direction parallel to line XXIII-XXIII in FIG. 22 ), the sum of the length L1 over which the gate 221g and the impurity region 211n overlap and the length L2 over which the gate 231g and the impurity region 211n overlap is 20% or more of the length L of the photoelectric conversion unit 211. Note that the sum of the length L1 and the length L2 may be 30% or more of the length L, 40% or more, or 50% (half) or more.

[0282] As described above, in this embodiment, the gate 221g of the first transfer transistor 221 and the gate 231g of the second transfer transistor 231 are provided so as to overlap the photoelectric conversion unit 211 in a plan view of the substrate 170.

[0283] Conventionally, both the gates 221g and 231g are arranged to sandwich the photoelectric conversion unit 211 without covering the photoelectric conversion unit 211 in a plan view of the substrate 170. In addition, in order to suppress dark current flowing between the gates 221g and 231g via the surface of the substrate 170, as shown in FIG. 23B, a p-type impurity region 211p having a higher p-type impurity concentration than the impurity region 211p is used. ＋ Type or sufficiently high p ＋＋ 23B is a cross-sectional view of a pixel according to a comparative example taken along line XXIII-XXIII in FIG.

[0284] However, when miniaturizing pixels, the distance between the gate 221g of the first transfer transistor 221 and the gate 231g of the second transfer transistor 231 becomes shorter, so that p ＋＋ In particular, in the case of a pixel including multiple gates for distance measurement or a global shutter, it is difficult to form a p ＋＋ It is difficult to secure a high-density impurity region, which results in an increase in dark current and a decrease in distance measurement accuracy.

[0285] In contrast, in the present embodiment, the gates 221g and 231g are each provided to overlap the p-type impurity region 211p in a plan view of the substrate 170. As shown in Fig. 24 , when the drive circuit 130 supplies a negative voltage to the gates 221g and 231g, a hole accumulation region 211pa in which holes are accumulated is formed in the impurity region 211p in a region directly below the gates 221g and 231g. Fig. 24 is a cross-sectional view showing the cross-sectional configuration of the photoelectric conversion unit 211 when a negative voltage is supplied to each gate of the first transfer transistor 221 and the second transfer transistor 231.

[0286] The hole accumulation region 211pa is an example of a fifth semiconductor region, and is a part of the impurity region 211p. The carrier concentration of the hole accumulation region 211pa is higher than that of the fourth semiconductor region, which is another part of the impurity region 211p, specifically, the impurity region 211pb. ＋＋ The dark current can be suppressed without providing a type impurity region.

[0287] By suppressing the dark current, the dynamic range of the image pickup device 100 can be expanded. The dynamic range is a parameter indicating the range of light intensity that can be measured by the image pickup device 100. The dynamic range is determined based on the saturation of the photoelectric conversion unit 211 and the magnitude of the dark current. The saturation of the photoelectric conversion unit 211 is determined by the area S of the photoelectric conversion unit 211. ＰＤ The magnitude of the dark current is inversely proportional to the area S1+S2 of the hole accumulation region 211pa.

[0288] Area S of the photoelectric conversion unit 211 ＰＤ is usually a predetermined fixed value because it is determined by the size of the unit cell 120. Therefore, in order to expand the dynamic range, it is necessary to increase the area of ​​the hole accumulation region 211pa.

[0289] 25 is a diagram showing the dynamic range of the image pickup device 100 relative to the area ratio of the hole accumulation region 211pa. In FIG. 25, the horizontal axis represents the area S of the photoelectric conversion unit 211. ＰＤ The vertical axis represents the ratio of the area S1+S2 of the hole accumulation region 211pa to the total area S1 of the gate 221g and the impurity region 211n. The vertical axis represents the dynamic range of the image pickup device 100. The area of ​​the hole accumulation region 211pa corresponds to the sum of the area S1 where the gate 221g and the impurity region 211n overlap and the area S2 where the gate 231g and the impurity region 211n overlap.

[0290] 25, the larger the area S1+S2 of the hole accumulation region 211pa, the larger the dynamic range of the image pickup device 100. In particular, ＰＤ When the ratio of the area S1+S2 of the hole accumulation region 211pa to the area S1+S2 of the photoelectric conversion unit 211 is between 10% and 20%, the dynamic range is greatly expanded.ＰＤ When the ratio of the area S1+S2 of the hole accumulation region 211pa to the total area is 20% or more, the dynamic range can be made sufficiently large.

[0291] In addition, if the relationship between the area ratio of the hole accumulation region 211pa and the dynamic range is improved with future developments in process technology, the area S ＰＤ The ratio of the area S1+S2 of the hole accumulation region 211pa to the area S1+S2 of the photoelectric conversion unit 211 is not necessarily 20% or more. ＰＤ The ratio of the area S1+S2 of the hole accumulation region 211pa to the total area S1 may be 10% or more.

[0292] The photoelectric conversion unit may further include a third semiconductor region provided on the p-type second semiconductor region. ＋ Type or p ＋＋ In this case, p ＋ Type or p ＋＋ In this case, the total area of ​​the overlap between the control terminal (gate) of the first transfer transistor and the photoelectric conversion unit and the area of ​​the overlap between the control terminal (gate) of the second transfer transistor and the photoelectric conversion unit may be 10% or more of the area of ​​the photoelectric conversion unit, and the same dark current suppression effect as in the above-described embodiment can be expected.

[0293] The imaging device may also include an electrode disposed in a portion of the photoelectric conversion unit where the control terminal (gate) of the first transfer transistor and the control terminal (gate) of the second transfer transistor are not disposed, and a drive circuit that supplies a voltage equal to or lower than the substrate potential to the electrode. In this case, a hole accumulation layer can be formed in the region directly below the electrode. This allows the hole accumulation layer to perform the same function as a high-concentration p-type impurity layer. This allows the area of ​​the hole accumulation layer to be increased, so the sum of the overlapping area between the control terminal (gate) of the first transfer transistor and the photoelectric conversion unit and the overlapping area between the control terminal (gate) of the second transfer transistor and the photoelectric conversion unit may be 10% or more of the area of ​​the photoelectric conversion unit, and the same dark current suppression effect as in the above-described embodiment can be expected.

[0294] Furthermore, dark current due to the gate insulating film is governed by the energy band gap. When an insulating film material with a wide energy band gap is used, dark current can be suppressed by the gate insulating film. In this case, the sum of the overlapping area between the control terminal (gate) of the first transfer transistor and the photoelectric conversion unit and the overlapping area between the control terminal (gate) of the second transfer transistor and the photoelectric conversion unit may be 10% or more of the area of ​​the photoelectric conversion unit, and the same dark current suppression effect as in the above-described embodiment can be expected. Note that the above example is an example of dark current suppression by the gate insulating film.

[0295] A manufacturing method for such an imaging device 100 includes a first step of forming a photoelectric conversion section 211 in a substrate 170, and a second step of forming a first transfer transistor 221 and a second transfer transistor 231 connected to the photoelectric conversion section 211.

[0296] In the first step, the photoelectric conversion unit 211 including the impurity region 211p is formed on the impurity region 211n. In the first step, the impurity regions 211n and 211p are formed, for example, by doping predetermined regions of the substrate 170 with n-type impurities or p-type impurities by ion implantation. Alternatively, the impurity regions 211n and 211p may be formed by epitaxial growth while selectively introducing impurities into the substrate body.

[0297] In the second step, the gate 221g of the first transfer transistor 221 and the gate 231g of the second transfer transistor 231 are each formed to overlap the impurity region 211p in a planar view of the substrate 170. For example, in the second step, the gates 221g and 231g are each disposed on the impurity region 211p via an insulating film in a planar view of the substrate 170. Specifically, in the second step, the gates 221g and 231g are each formed to overlap the impurity region 211p such that, in a planar view of the substrate 170, an area S1 where the gate 221g and the impurity region 211p overlap is equal to or greater than half of an area Sg1 of the gate 221g, and an area S2 where the gate 231g and the impurity region 211p overlap is equal to or greater than half of an area Sg2 of the gate 231g. Alternatively, in the second step, the sum of an area S1 where the gate 221g and the impurity region 211p overlap and an area S2 where the gate 231g and the impurity region 211p overlap in a plan view of the substrate 170 is equal to the area S of the photoelectric conversion unit 211. ＰＤ Alternatively, in the second step, the gates 221g and 231g are formed to overlap the impurity region 211p so that the sum of a length L1 over which the gate 221g and the impurity region 211p overlap and a length L2 over which the gate 231g and the impurity region 211p overlap in the alignment direction of the gate 221g and the gate 231g in a plan view of the substrate 170 is 20% or more of the length L of the photoelectric conversion unit 211.

[0298] For example, first, an insulating film is formed so as to cover the surface of the substrate 170. The insulating film is formed, for example, by plasma CVD (Chemical Vapor Deposition) or the like. After the insulating film is formed, a conductive film is formed. The conductive film is formed by sputtering, vapor deposition, or the like. The formed conductive film is patterned to form the gates 221g and 231g. The patterning is performed by photolithography and dry etching or wet etching, or the like. At this time, by patterning the conductive film so as to leave a portion that covers the photoelectric conversion unit 211, the gates 221g and 231g are formed to overlap the photoelectric conversion unit 211 in a plan view of the substrate 170.

[0299] While the imaging device, ranging device, imaging device control method, and manufacturing method according to one or more aspects have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and forms constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0300] For example, in the above embodiment, the endoscope system 1 is shown as an example of a distance measuring device, but this is not limiting. The distance measuring device may be, for example, a surveillance camera or an object detection device installed in a predetermined building or structure. Alternatively, the distance measuring device may be a sensor device mounted on a moving object such as an autonomous vehicle or a drone. In these cases, the target object 2 may be a stationary object or a moving object.

[0301] Furthermore, for example, the visible light image does not have to be an RGB image. The visible light image may be a monochromatic image such as a black and white image. Furthermore, for example, the first wavelength of the light used in the first operation mode and the second wavelength of the flashing light used in the second operation mode may be the same. Furthermore, the image acquired in the imaging mode may be a still image or a moving image.

[0302] Furthermore, the first operation mode and the second operation mode do not have to be the image capture mode and the distance measurement mode. For example, the first operation mode and the second operation mode may be a short exposure mode and a long exposure mode in the image capture mode.

[0303] Alternatively, the first operation mode and the second operation mode may be two modes with different frequencies in the ToF mode, or two modes with different pulse widths, etc. Alternatively, the first operation mode and the second operation mode may be a pulse ToF mode or a CW-ToF mode.

[0304] Furthermore, the communication method between the devices described in the above embodiment is not particularly limited. When wireless communication is performed between the devices, the wireless communication method (communication standard) is, for example, short-range wireless communication such as ZigBee (registered trademark), Bluetooth (registered trademark), or wireless LAN (Local Area Network). Alternatively, the wireless communication method (communication standard) may be communication via a wide-area communication network such as the Internet. Furthermore, wired communication may be performed between the devices instead of wireless communication. Specifically, wired communication is communication using power line communication (PLC) or a wired LAN.

[0305] Furthermore, in the above-described embodiments, the processing performed by a specific processing unit may be performed by another processing unit. Furthermore, the order of multiple processes may be changed, or multiple processes may be performed in parallel. Furthermore, the allocation of components included in a distance measuring device (distance measuring system) to multiple devices is an example. For example, components included in one device may be included in another device.

[0306] For example, the processing described in the above embodiments may be realized by centralized processing using a single device (system), or may be realized by distributed processing using multiple devices. Furthermore, the processor that executes the program may be a single processor or multiple processors. That is, centralized processing or distributed processing may be performed.

[0307] In the above-described embodiments, all or some of the components such as the control unit may be configured with dedicated hardware, or may be realized by executing a software program suitable for each component. Each component may be realized by a program execution unit such as a CPU (Central Processing Unit) or a processor reading and executing a software program recorded on a recording medium such as an HDD (Hard Disk Drive) or semiconductor memory.

[0308] Furthermore, the components such as the control unit may be configured with one or more electronic circuits, each of which may be a general-purpose circuit or a dedicated circuit.

[0309] The one or more electronic circuits may include, for example, a semiconductor device, an IC, or an LSI. The IC or LSI may be integrated on a single chip or on multiple chips. Although the IC or LSI is referred to here as an IC or LSI, the name may vary depending on the degree of integration, and may be called a system LSI, a VLSI (Very Large Scale Integration), or an ULSI (Ultra Large Scale Integration). An FPGA, which is programmed after the LSI is manufactured, can also be used for the same purpose.

[0310] Furthermore, the general or specific aspects of the present disclosure may be realized as a system, an apparatus, a method, an integrated circuit, or a computer program. Alternatively, the general or specific aspects may be realized as a computer-readable non-transitory recording medium such as an optical disk, a HDD, or a semiconductor memory on which the computer program is stored. Alternatively, the general or specific aspects of the present disclosure may be realized as any combination of a system, an apparatus, a method, an integrated circuit, a computer program, and a recording medium.

[0311] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to the above-described embodiments within the scope of the claims or their equivalents.

[0312] The present disclosure can be used as an imaging device that can be used for high-precision distance measurement, and can be used in, for example, an endoscope system, a surveillance camera, and the like.

[0313] REFERENCE SIGNS LIST 1 Endoscope system 2 Object 10 Main body 11 Light source 12 Light source driving circuit 13 ISP 14 Output section 15 System control circuit 16 Power supply IC 20 Insertion section 21 Light guide member 22 Objective lens 23 Condenser lens 100 Imaging device 110 Sensor array 120 Unit cell 121 Reset transistor 122 Capacitor-connected transistor 123 Capacitor 124 Readout transistor 125 Selection transistor 130 Drive circuit 132 Operation mode control circuit 134 Substrate voltage supply circuit 135 Inverter 136 Pixel control circuit 140 Signal output circuit 150 Control line 160 Vertical signal line 170 Substrate 201, 202, 203, 204 Pixels 211, 212, 213, 214 Photoelectric conversion section 211n, 211p, 211pb, 211pp impurity region 211pa hole accumulation region 221, 222, 223, 224 first transfer transistor 221g, 231g gate 221ga first side 231, 232, 233, 234 second transfer transistor 231ga second side 241, 241a, 241b, 251 wiring 241c, 241d, 241v, 251v via 301, 301n, 301p, 302, 302n, 302p, 303n, 303p, 304n, 304p, 305n, 305p, 306n, 306p switching element 311, 312, 313a, 313b, 314a, 314b signal lines 321 first connection circuit 322 second connection circuit 323 control signal generation circuit

Claims

1. A first semiconductor layer; A unit cell provided in the first semiconductor layer, the unit cell including n pixels (n is a natural number) and a charge storage unit for storing charges generated in the n pixels; A drive circuit, Each of the n pixels is A photoelectric conversion unit; a first transfer transistor having a first control terminal, a first input / output terminal connected to the photoelectric conversion unit, and a second input / output terminal connected to the charge accumulation unit; a second transfer transistor having a second control terminal, a third input / output terminal connected to the photoelectric conversion unit, and a fourth input / output terminal different from the third input / output terminal; the drive circuit supplies a voltage corresponding to one operation mode selected from a plurality of operation modes to the first semiconductor layer, the first control terminal, or the second control terminal; Imaging device.

2. The plurality of operation modes include: a first mode of operation exposing at least one of the n pixels to light at a first wavelength; a second mode of operation exposing at least one of the n pixels to a blinking light of a second wavelength. The imaging device according to claim 1 .

3. The drive circuit includes: a first voltage supply circuit that supplies a voltage to the first semiconductor layer; a second voltage supply circuit that supplies a voltage to at least one of the first control terminal and the second control terminal. The imaging device according to claim 1 .

4. the drive circuit includes a first voltage supply circuit that supplies a voltage to the first semiconductor layer; The first voltage supply circuit includes: a first signal line set to a first potential; a second signal line set to a second potential different from the first potential; a first connection circuit that switches the first signal line and the second signal line in accordance with the operation mode to connect to the first semiconductor layer, The imaging device according to claim 2 .

5. the second potential is lower than the first potential; the first connection circuit connects the first signal line to the first semiconductor layer when the first operation mode is selected, and connects the second signal line to the first semiconductor layer when the second operation mode is selected. The imaging device according to claim 4.

6. the drive circuit includes a second voltage supply circuit that supplies a voltage to at least one of the first control terminal and the second control terminal; The second voltage supply circuit includes: one or more third signal lines set to at least one of a third potential and a fourth potential higher than the third potential; one or more fourth signal lines set to at least one of a fifth potential and a sixth potential higher than the fifth potential; a second connection circuit that switches the one or more third signal lines and the one or more fourth signal lines in accordance with the operation mode to connect the one or more third signal lines to at least one of the first control terminal and the second control terminal, The imaging device according to claim 2 .

7. a potential difference between the fourth potential and the third potential is different from a potential difference between the sixth potential and the fifth potential; The imaging device according to claim 6.

8. a potential difference between the fourth potential and the third potential is greater than a potential difference between the sixth potential and the fifth potential; the second connection circuit connects the one or more third signal lines to at least one of the first control terminal and the second control terminal when the first operation mode is selected, and connects the one or more fourth signal lines to at least one of the first control terminal and the second control terminal when the second operation mode is selected. The imaging device according to claim 6.

9. the drive circuit includes a second voltage supply circuit that supplies a voltage to at least one of the first control terminal and the second control terminal; The second voltage supply circuit includes: a seventh signal line set to a seventh potential; an eighth signal line set to an eighth potential different from the seventh potential; a third connection circuit that switches the seventh signal line and the eighth signal line in accordance with the operation mode to connect the seventh signal line and the eighth signal line to at least one of the first control terminal and the second control terminal. The imaging device according to claim 2 .

10. the eighth potential is lower than the seventh potential; the third connection circuit connects the seventh signal line to at least one of the first control terminal and the second control terminal when the first operation mode is selected, and connects the eighth signal line to at least one of the first control terminal and the second control terminal when the second operation mode is selected. The imaging device according to claim 9.

11. The unit cell includes a capacitor having a first electrode and a second electrode, and a switching element connected in series between the first electrode and the charge storage portion, the switching element maintains the capacitor and the charge storage unit in a conductive state in the second operation mode, and brings the capacitor and the charge storage unit into a non-conductive state in the first operation mode. The imaging device according to claim 2 .

12. the drive circuit, in the second operation mode, makes a potential supplied to the second electrode lower than a potential supplied to the fourth input / output terminal; The imaging device according to claim 11.

13. A light source; An imaging device according to any one of claims 1 to 12, A calculation circuit that calculates a distance to an object based on a signal output from the imaging device. Ranging device.

14. A control method for an imaging device according to any one of claims 1 to 12, comprising: in an operation mode in which at least one of the n pixels is exposed to a blinking light of a second wavelength, during a period of exposure to the blinking light of the second wavelength, the first transfer transistor and the second transfer transistor are repeatedly switched between a conductive state and a non-conductive state so that they are not simultaneously in a conductive state; In an operation mode in which at least one of the n pixels is exposed to light of a first wavelength, the first transfer transistor and the second transfer transistor are maintained in a non-conductive state during a period of exposure to the light of the first wavelength, and only the first transfer transistor is brought into a conductive state at a predetermined timing. A method for controlling an imaging device.