Power detector

Abstract

A power detector according to the present invention comprises: a main current mirror circuit that outputs a detection current indicating the power of a high-frequency signal from an output terminal; a reference current mirror circuit that is identical to the main current mirror circuit; a connection current mirror circuit that has an input terminal connected to the output terminal of the reference current mirror circuit, and an output terminal connected to a main output terminal, and that outputs a reference current; and a differential amplifier that generates a power detection signal on the basis of an input voltage of a first-stage transistor to which the high-frequency signal in the main current mirror circuit is inputted, and an input bias voltage of a corresponding transistor corresponding to the first-stage transistor in the reference current mirror circuit. In the main current mirror circuit, the input bias voltage of the first-stage transistor is set on the basis of a first reference current, and, in the reference current mirror circuit, the input bias voltage of the corresponding transistor is set on the basis of the total current of a second reference current and a deviation current between the detection current and the reference current.

Description

Power Detector

[0001] This application claims priority to Japanese Patent Application No. 2023-106853, filed on June 29, 2023, the contents of which are incorporated herein by reference.

[0002] Patent Document 1 discloses a power detector for detecting high-frequency power. As shown in Figure 2 and other figures of Patent Document 1, this power detector includes an original rectifier that half-wave rectifies a high-frequency signal, a replica rectifier that has the same circuit characteristics as the original rectifier, a low-pass filter that smooths the output of the original rectifier, and a differential amplifier that differentially amplifies the output of the low-pass filter and the output of the replica rectifier. This power detector reduces variations in the detection amount due to manufacturing variations and temperature fluctuations of the original rectifier by differentially amplifying the output of the low-pass filter and the output of the replica rectifier in the differential amplifier.

[0003] U.S. Patent No. 6,791,312

[0004] However, the power detector of Patent Document 1 uses a differential amplifier to differentially amplify the output voltage of the original rectifier and the output voltage of the replica rectifier, which makes it susceptible to external noise. In other words, with existing power detectors, the detected amount fluctuates due to external noise, making it difficult to obtain an accurate detected amount. For example, power detection of high-frequency signals in the gigahertz band is more susceptible to external noise than power detection of low-frequency signals, so suppressing the effects of external noise in power detectors is an extremely important technical challenge.

[0005] The present invention has been made in view of the above circumstances, and has as its object to provide a power detector that can suppress the influence of external noise.

[0006] In order to achieve the above object, a first aspect of the present invention is a power detector comprising: a main current mirror circuit that rectifies a high-frequency signal and outputs a detection current indicating the power of the high-frequency signal from a main output terminal; a reference current mirror circuit having the same circuit configuration and circuit performance as the main current mirror circuit; a connection current mirror circuit having an input terminal connected to a reference output terminal of the reference current mirror circuit and a connection output terminal connected to the main output terminal, and outputting a reference current; and a differential amplifier that generates a power detection signal by differentially amplifying an input voltage of an initial-stage transistor to which the high-frequency signal is input in the main current mirror circuit and an input bias voltage of a corresponding transistor corresponding to the initial-stage transistor in the reference current mirror circuit, wherein the input bias voltage of the initial-stage transistor in the main current mirror circuit is set based on a first reference current, and the input bias voltage of the corresponding transistor in the reference current mirror circuit is set based on the sum of a current deviation between the detection current and the reference current and a second reference current, and the first reference current and the second reference current are the same.

[0007] A second aspect of the present invention is the power detector of the first aspect, wherein the main current mirror circuit comprises a first main current mirror circuit composed of n-type transistors and including the initial stage transistor, and a second main current mirror circuit connected to the output terminal of the first main current mirror circuit and composed of p-type transistors, and the reference current mirror circuit comprises a first reference current mirror circuit composed of n-type transistors and including the corresponding transistor, and a second reference current mirror circuit connected to the output terminal of the first reference current mirror circuit and composed of p-type transistors.

[0008] A third aspect of the present invention is the power detector according to the second aspect, wherein the second main current mirror circuit and the second reference current mirror circuit have mirror ratios set to values ​​greater than one.

[0009] A fourth aspect of the present invention is the power detector of the second or third aspect, wherein the first main current mirror circuit and the first reference current mirror circuit have mirror ratios set to 1 or a value smaller than 1.

[0010] A fifth aspect of the present invention is the power detector of any one of the second to fourth aspects, wherein the n-type transistor is an n-type metal-oxide-semiconductor field effect transistor (MOSFET), and the p-type transistor is a p-type metal-oxide-semiconductor field effect transistor (MOSFET).

[0011] A sixth aspect of the present invention is the power detector according to any one of the first to fifth aspects, wherein the differential amplifier is an instrumentation amplifier.

[0012] A seventh aspect of the present invention is the power detector of any one of the first to sixth aspects, further comprising: a voltage-current conversion circuit that converts the output voltage of the differential amplifier into a current; and a current-voltage conversion circuit that converts the output current of the voltage-current conversion circuit into a voltage.

[0013] An eighth aspect of the present invention is a power detector according to any one of the first to seventh aspects, comprising a plurality of power detection units each including a main circuit constituted by a main rectifier, a first resistor circuit, and a second resistor circuit, a reference circuit constituted by a replica rectifier, the first resistor circuit, and the second resistor circuit, and a differential amplifier, and detecting the power of the high-frequency signal by averaging the power detection signals of the plurality of power detection units.

[0014] A ninth aspect of the present invention is a power detector according to any one of the first to seventh aspects, comprising a main circuit constituted by a main rectifier, a first resistor circuit, and a second resistor circuit, a reference circuit constituted by a replica rectifier, the first resistor circuit, and the second resistor circuit, a differential amplifier, and an open / close switch, and detecting the power of a high-frequency signal input to and output from each of the plurality of power detection units by sequentially switching the power detection signal of each of the plurality of power detection units using the open / close switch and transmitting it to an output circuit.

[0015] According to the present invention, it is possible to provide a power detector that can suppress the influence of external noise.

[0016] FIG. 1 is a circuit diagram showing the overall configuration of a power detector according to a first embodiment of the present invention. FIG. 2 is a schematic diagram showing the relationship between a main rectifier, a replica rectifier, a first resistor circuit, and a second resistor circuit in the first embodiment of the present invention. FIG. 3 is a circuit diagram showing a detailed configuration of a main rectifier of a power detector according to a first embodiment of the present invention. FIG. 4 is a circuit diagram showing a detailed configuration of a replica rectifier of a power detector according to a first embodiment of the present invention. FIG. 5 is a circuit diagram showing a detailed configuration of a first resistor circuit and a second resistor circuit of a power detector according to a first embodiment of the present invention. FIG. 6 is a circuit diagram showing a detailed configuration of a differential amplifier of a power detector according to a first embodiment of the present invention. FIG. 7 is a circuit diagram showing a detailed configuration of a voltage-current conversion circuit of a power detector according to a first embodiment of the present invention. FIG. 8 is a circuit diagram showing a detailed configuration of an output circuit of a power detector according to a second embodiment of the present invention.

[0017] 1 to 6B, a first embodiment of the present invention will be described below. As shown in Fig. 1, a power detector A according to this embodiment includes n (n: a natural number of 2 or more) power detection units U1 to Un and a single output circuit W. That is, the power detector A includes a plurality of power detection units U1 to Un.

[0018] As shown in the figure, n power detection units U1 to Un are respectively input with radio frequency signals RFin1 to RFinn having the same subscript. For example, radio frequency signal RFin1 is input to power detection unit U1, and radio frequency signal RFin2 is input to power detection unit U2. Note that hereinafter, the n radio frequency signals RFin1 to RFinn will be collectively referred to as radio frequency signal RFin.

[0019] Each of the n power detection units U1 to Un receives one of the n radio frequency signals RFin1 to RFinn as an input, and outputs a detection current Is indicating the power of each of the n radio frequency signals RFin1 to RFinn to the output circuit W. For example, the power detection unit U1 outputs a detection current Is1 indicating the power of the radio frequency signal RFin1 to the output circuit W, and the power detection unit U2 outputs a detection current Is2 indicating the power of the radio frequency signal RFin2 to the output circuit W.

[0020] All of the n power detection units U1 to Un have the same circuit configuration, and each of the n power detection units U1 to Un specifically includes a main rectifier 1, a replica rectifier 2, a first resistor circuit 3, a second resistor circuit 4, a differential amplifier 5, and a voltage-current conversion circuit 6.

[0021] Of these circuits, the main rectifier 1, the first resistor circuit 3, and the second resistor circuit 4 constitute a main circuit in the present invention. The replica rectifier 2, the first resistor circuit 3, and the second resistor circuit 4 constitute a reference circuit in the present invention. The differential amplifier 5 corresponds to a differential amplifier in the present invention.

[0022] Details will be described later, but the main rectifier 1 receives a high-frequency signal RFin and a reference voltage Vr as input, and outputs a detection current by half-wave rectifying and smoothing the high-frequency signal RFin. It also outputs to the replica rectifier 2 a deviation current Idiff between this detection current and a reference current based on the reference voltage Vr input from the replica rectifier 2.

[0023] Furthermore, the main rectifier 1 outputs the gate voltage (input voltage) of an n-type transistor (first-stage transistor) to which the high-frequency signal RFin is input as a main operating voltage Vm to the differential amplifier 5. This main operating voltage Vm is a mixed voltage of an input bias voltage (DC voltage) set based on the first reference current Iref and the high-frequency signal RFin (AC).

[0024] The replica rectifier 2 has the same circuit configuration and circuit performance as the main rectifier 1. The replica rectifier 2 generates a reference voltage Vr based on an input bias voltage that is set based on the total current of a second reference current Iref, which is set to be the same as the first reference current Iref, and the deviation current Idiff. The replica rectifier 2 outputs the reference voltage Vr to the main rectifier 1.

[0025] Furthermore, the replica rectifier 2 outputs the gate voltage (input bias voltage) of an n-type transistor (corresponding transistor) corresponding to the n-type transistor of the main rectifier 1 as a reference operating voltage Vb to the differential amplifier 5. Since the high-frequency signal RFin is not input to the replica rectifier 2, the reference operating voltage Vb is a DC voltage.

[0026] The first resistor circuit 3 is a resistive voltage divider circuit that generates a first bias voltage V1 by resistive voltage division. The second resistor circuit 4 is a resistive voltage divider circuit that generates a second bias voltage V2 different from the first bias voltage V1 by resistive voltage division. Note that the first resistor circuit 3 and the second resistor circuit 4, i.e., the functions of generating the first bias voltage V1 and the second bias voltage V2, may be provided within the main rectifier 1 and the replica rectifier 2, rather than being provided as circuits separate from the main rectifier 1 and the replica rectifier 2.

[0027] As described above, the first resistor circuit 3 and the second resistor circuit 4 are auxiliary circuits that supply the first bias voltage V1 and the second bias voltage V2 to the main rectifier 1 and the replica rectifier 2. That is, the main rectifier 1 and the replica rectifier 2 perform the desired circuit functions by receiving the first bias voltage V1 and the second bias voltage V2 from the first resistor circuit 3 and the second resistor circuit 4.

[0028] The main rectifier 1, replica rectifier 2, first resistor circuit 3, and second resistor circuit 4 have the functional relationship shown in Fig. 2. That is, the main rectifier 1, the first resistor circuit 3, and the second resistor circuit 4 constitute a first main current mirror circuit M1 and a second main current mirror circuit M2. Furthermore, the first main current mirror circuit M1 and the second main current mirror circuit M2 constitute a main current mirror circuit M.

[0029] The replica rectifier 2, the first resistor circuit 3, and the second resistor circuit 4 constitute a first reference current mirror circuit R1 and a second reference current mirror circuit R2. The first reference current mirror circuit R1 and the second reference current mirror circuit R2 also constitute a reference current mirror circuit R.

[0030] The main rectifier 1, replica rectifier 2, first resistor circuit 3, and second resistor circuit 4 constitute a connecting current mirror circuit C. That is, the connecting current mirror circuit C is a current mirror circuit spanning the main rectifier 1 and replica rectifier 2. A high-frequency signal RFin is input to the input terminal of the first main current mirror circuit M1.

[0031] The output terminal of the first main current mirror circuit M1 is connected to the input terminal of the second main current mirror circuit M2. The output terminal (main output terminal) of the second main current mirror circuit M2 is connected to the output terminal (connection output terminal) of the connecting current mirror circuit C and also to the input terminal of the first reference current mirror circuit R1. The output terminal of the first reference current mirror circuit R1 is connected to the input terminal of the second reference current mirror circuit R2. The output terminal (reference output terminal) of the second reference current mirror circuit R2 is also connected to the input terminal of the connecting current mirror circuit C.

[0032] The differential amplifier 5 receives the main operating voltage Vm and the reference operating voltage Vb as inputs, and generates a difference voltage Vs by differentially amplifying the main operating voltage Vm and the reference operating voltage Vb. This difference voltage Vs is a signal indicating the power of the radio frequency signal RFin. The differential amplifier 5 outputs this difference voltage Vs to the voltage-current conversion circuit 6. Note that an instrumentation amplifier capable of variably setting the gain may be used as the differential amplifier 5.

[0033] The voltage-current conversion circuit 6 converts the differential voltage Vs input from the differential amplifier 5 into a current to generate a differential current Is. This differential current Is is the output of each of the n power detection units U1 to Un. The output terminals of the voltage-current conversion circuits 6 in each of the n power detection units U1 to Un are connected to each other as shown in the figure, and are also connected to the input terminal of the output circuit W.

[0034] The output circuit W is a current-voltage conversion circuit that receives as its input signal the differential current Is input from each of the n power detection units U1 to Un. That is, the output circuit W averages the n differential currents Is, converts them into an output voltage Vout, and outputs it to the outside. The power detector A is a redundant power detection circuit that includes the n power detection units U1 to Un.

[0035] Further description will be given of each of the n power detection units U1 to Un and the output circuit W. As shown in Fig. 3, the main rectifier 1 includes a coupling capacitor 1a, a first transistor 1b, a second transistor 1c, a first resistor 1d, a first capacitor 1e, a third transistor 1f, a fourth transistor 1g, a constant current source 1h, a fifth transistor 1i, a sixth transistor 1j, a second resistor 1k, a second capacitor 1m, a seventh transistor 1n, an eighth transistor 1p, a ninth transistor 1q, and a tenth transistor 1r.

[0036] The coupling capacitor 1a has a predetermined capacitance. The radio frequency signal RFin is input to one end of the coupling capacitor 1a, and the other end is connected to the gate terminal of the first transistor 1b, one end of the first resistor 1d, the output terminal of the constant current source 1h, and the drain terminal of the fourth transistor 1g. The coupling capacitor 1a serves to remove the DC signal component contained in the radio frequency signal RFin and maintain the DC component of the voltage Vm at an input bias voltage set based on the first reference current Iref. In other words, the coupling capacitor 1a applies only the AC component of the radio frequency signal RFin to the gate terminal of the first transistor 1b.

[0037] The first transistor 1b is an n-type transistor. As shown in the figure, the gate terminal of the first transistor 1b is connected to the other end of the coupling capacitor 1a, one end of the first resistor 1d, the output terminal of the constant current source 1h, and the drain terminal of the fourth transistor 1g, the drain terminal is connected to the source terminal of the second transistor 1c, and the source terminal is grounded. This first transistor 1b half-wave rectifies the radio frequency signal RFin using the bias voltage (input bias voltage) of the gate terminal as a rectification threshold, and outputs the obtained half-wave rectified signal to the source terminal of the second transistor 1c. This first transistor 1b is the initial-stage transistor of the present invention.

[0038] The second transistor 1c is an n-type transistor. As shown in the figure, the second transistor 1c is a cascode transistor cascode-connected to the first transistor 1b (first-stage transistor). That is, the source terminal of the second transistor 1c is connected to the drain terminal of the first transistor 1b. The gate terminal of the second transistor 1c is connected to the output terminal of the first resistor circuit 3, and a first bias voltage V1 is applied to the gate terminal. Furthermore, the drain terminal of the second transistor 1c is connected to the drain terminal of the fifth transistor 1i, the gate terminal of the sixth transistor 1j, and one end of the second resistor 1k.

[0039] The first resistor 1d has a predetermined resistance value. One end of the first resistor 1d is connected to the other end of the coupling capacitor 1a, the gate terminal of the first transistor 1b, the output terminal of the constant current source 1h, and the drain terminal of the fourth transistor 1g, and the other end is connected to one end of the first capacitor 1e and the gate terminal of the third transistor 1f. The first resistor 1d, together with the first capacitor 1e, forms a low-pass filter having a predetermined time constant and prevents the AC component of the high-frequency signal RFin from being input to the gate terminal of the third transistor 1f.

[0040] The first capacitor 1e has a predetermined capacitance. One end of the first capacitor 1e is connected to the other end of the first resistor 1d and the gate terminal of the third transistor 1f, and the other end is grounded. The first capacitor 1e, together with the first resistor 1d, forms a low-pass filter with a predetermined time constant, and prevents the AC component of the high-frequency signal RFin from being input to the gate terminal of the third transistor 1f. In other words, only the DC component of the main output voltage Vm is input to the gate terminal of the third transistor 1f.

[0041] The third transistor 1f is an n-type transistor. As shown in the figure, the gate terminal of the third transistor 1f is connected to the other end of the first resistor 1d and one end of the first capacitor 1e, the drain terminal is connected to the source terminal of the fourth transistor 1g, and the source terminal is grounded.

[0042] The fourth transistor 1g is an n-type transistor. As shown in the figure, the fourth transistor 1g is a cascode transistor cascode-connected to the third transistor 1f. That is, the source terminal of the fourth transistor 1g is connected to the drain terminal of the third transistor 1f. The gate terminal of the fourth transistor 1g is connected to the output terminal of the first resistor circuit 3, and a first bias voltage V1 is applied to the gate terminal. The drain terminal of the fourth transistor 1g is connected to the output terminal of the constant current source 1h, the other terminal of the coupling capacitor 1a, the gate terminal of the first transistor 1b, and one terminal of the first resistor 1d.

[0043] The output terminal of the constant current source 1h is connected to the other terminal of the coupling capacitor 1a, the gate terminal of the first transistor 1b, one terminal of the first resistor 1d, and the drain terminal of the fourth transistor 1g, and outputs a first reference current Iref (DC current) from the output terminal.

[0044] Here, the gate voltage of the first transistor 1b is the main operating voltage Vm as shown in the figure, which is a mixed voltage obtained by superimposing the AC component of the high frequency signal RFin on an input bias voltage (DC voltage) set by the first reference current Iref, the first resistor 1d, the first capacitor 1e, the third transistor 1f, and the fourth transistor 1g.

[0045] The gate bias voltage at the main operating voltage Vm is a threshold value when the first transistor 1b half-wave rectifies the radio frequency signal RFin. That is, the gate bias voltage of the first transistor 1b sets the operating point of the half-wave rectification of the radio frequency signal RFin. The radio frequency signal RFin that has been half-wave rectified with the gate bias voltage as the operating point, i.e., the half-wave rectified signal, is output to the drain terminal of the second transistor 1c cascode-connected to the first transistor 1b.

[0046] The fifth transistor 1i is a p-type transistor. As shown in the figure, the fifth transistor 1i is a cascode transistor cascode-connected to the sixth transistor 1j. That is, the source terminal of the fifth transistor 1i is connected to the drain terminal of the sixth transistor 1j. The fifth transistor 1i receives the half-wave rectified signal from the drain terminal of the second transistor 1c.

[0047] The gate terminal of the fifth transistor 1i is connected to the output terminal of the second resistor circuit 4, and a second bias voltage V2 is applied to the gate terminal. The drain terminal of the fifth transistor 1i is connected to the drain terminal of the second transistor 1c, the gate terminal of the sixth transistor 1j, and one end of the second resistor 1k.

[0048] The sixth transistor 1j is a p-type transistor. As shown in the figure, the gate terminal of the sixth transistor 1j is connected to the drain terminal of the second transistor 1c, the drain terminal of the fifth transistor 1i, and one end of the second resistor 1k, the drain terminal is connected to the source terminal of the fifth transistor 1i, and the source terminal is connected to the power supply Vcc.

[0049] One end of the second resistor 1k is connected to the drain terminal of the second transistor 1c, the drain terminal of the fifth transistor 1i, and the gate terminal of the sixth transistor 1j, and the other end is connected to one end of the second capacitor 1m and the gate terminal of the seventh transistor 1n. The second resistor 1k and the second capacitor 1m form a low-pass filter having a predetermined time constant, and prevent the AC component of the half-wave rectified signal input from the drain terminal of the second transistor 1c from being input to the gate terminal of the seventh transistor 1n.

[0050] The second capacitor 1m has a predetermined capacitance. One end of the second capacitor 1m is connected to the other end of the second resistor 1k and the gate terminal of the seventh transistor 1n, and the other end is connected to the power supply Vcc, the source terminal of the sixth transistor 1j, and the source terminal of the seventh transistor 1n. The second capacitor 1m, together with the second resistor 1k, forms a low-pass filter with a predetermined time constant, smoothing the half-wave rectified signal and inputting it to the gate terminal of the seventh transistor 1n. That is, a DC voltage obtained by smoothing the half-wave rectified signal is input to the gate terminal of the seventh transistor 1n. This DC voltage is a detection voltage indicating the power of the radio frequency signal RFin.

[0051] The seventh transistor 1n is a p-type transistor. As shown in the figure, the gate terminal of the seventh transistor 1n is connected to the other end of the second resistor 1k and one end of the second capacitor 1m, the drain terminal is connected to the source terminal of the eighth transistor 1p, and the source terminal is connected to the power supply Vcc, the other end of the second capacitor 1m, and the source terminal of the sixth transistor 1j. The seventh transistor 1n amplifies the detection voltage input to the gate terminal and outputs it from the drain terminal to the source terminal of the eighth transistor 1p.

[0052] The eighth transistor 1p is a p-type transistor. As shown in the figure, the eighth transistor 1p is a cascode transistor cascode-connected to the seventh transistor 1n. That is, the source terminal of the eighth transistor 1p is connected to the drain terminal of the seventh transistor 1n. The detection voltage is input to the eighth transistor 1p from the drain terminal of the seventh transistor 1n.

[0053] The gate terminal of the eighth transistor 1p is connected to the output terminal of the second resistor circuit 4, and a second bias voltage V2 is applied to the gate terminal. Furthermore, the drain terminal of the eighth transistor 1p is connected to the drain terminal of the ninth transistor 1q, and is connected to the gate terminal of the first transistor 2b, the drain terminal of the fourth transistor 2g, one end of the first resistor 2d, and the output terminal of the constant current source 2h in the replica rectifier 2, as shown in FIG. 4. That is, the drain terminal of the eighth transistor 1p outputs the deviation current Idiff to the replica rectifier 2.

[0054] The ninth transistor 1q is an n-type transistor. As shown in the figure, the ninth transistor 1q is a cascode transistor cascode-connected to the tenth transistor 1r. That is, the source terminal of the ninth transistor 1q is connected to the drain terminal of the tenth transistor 1r. The gate terminal of the ninth transistor 1q is connected to the output terminal of the first resistor circuit 3, and a first bias voltage V1 is applied to the gate terminal. Furthermore, the drain terminal of the ninth transistor 1q is connected to the drain terminal of the eighth transistor 1p.

[0055] The tenth transistor 1r is an n-type transistor. As shown in the figure, the tenth transistor 1r has a gate terminal to which a reference voltage Vr is input from the replica rectifier 2, a drain terminal connected to the source terminal of the ninth transistor 1q, and a source terminal grounded. That is, the gate terminal of the tenth transistor 1r is connected to the drain terminal of the eighth transistor 2p in the replica rectifier 2, the drain terminal of the ninth transistor 2q, and the gate terminal of the tenth transistor 2r, as shown in FIG.

[0056] The ninth transistor 1q and the tenth transistor 1r, which are connected in cascode in this manner, amplify the reference voltage Vr input to the gate terminal of the tenth transistor 1r and output the amplified voltage to the drain terminal of the tenth transistor 1r. Since the drain terminal of the tenth transistor 1r is connected to the source terminal of the ninth transistor 1q, a deviation current Idiff, which is the difference between the detection current based on the half-wave rectified signal of the radio frequency signal RFin and the reference current based on the reference voltage Vr, is output from the ninth transistor 1q to the replica rectifier 2.

[0057] Here, among the components of the main rectifier 1, the first transistor 1b, the second transistor 1c, the first resistor 1d, the first capacitor 1e, the third transistor 1f, the fourth transistor 1g, the constant current source 1h, the fifth transistor 1i, the sixth transistor 1j, the second resistor 1k, the second capacitor 1m, the seventh transistor 1n, and the eighth transistor 1p, the first resistor circuit 3, and the second resistor circuit 4 constitute a main current mirror circuit M.

[0058] The first transistor 1b, second transistor 1c, first resistor 1d, first capacitor 1e, third transistor 1f, fourth transistor 1g, and constant current source 1h of the main rectifier 1, together with the first resistor circuit 3, constitute a first main current mirror circuit M1 using an n-type metal-oxide-semiconductor field effect transistor (MOSFET). Note that the n-type MOSFET is an example of an n-type transistor.

[0059] The reference current (source current) flowing through the first transistor 1b and the second transistor 1c and the first reference current Iref are related to each other by the mirror ratio of the first main current mirror circuit M1, which is set to, for example, 1 or a value smaller than 1.

[0060] The fifth transistor 1i, the sixth transistor 1j, the second resistor 1k, the second capacitor 1m, the seventh transistor 1n, and the eighth transistor 1p of the main rectifier 1 and the second resistor circuit 4 constitute a second main current mirror circuit M2 using a p-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The p-type MOSFET is an example of a p-type transistor.

[0061] The reference current (source current) flowing through the fifth transistor 1i and the sixth transistor 1j and the source current flowing through the seventh transistor 1n and the eighth transistor 1p are related to each other by the mirror ratio of the second main current mirror circuit M2. That is, the source currents of the seventh transistor 1n and the eighth transistor 1p are determined by the reference current flowing through the fifth transistor 1i and the sixth transistor 1j and the mirror ratio of the second main current mirror circuit M2. The mirror ratio of the second main current mirror circuit M2 is set to a value greater than 1, for example.

[0062] In addition, when the mirror ratio of the first main current mirror circuit M1 and the mirror ratio of the second main current mirror circuit M2 are both set to 1, when no high-frequency signal RFin is input to the main rectifier 1, the same operating current flows through all transistors, i.e., the first transistor 1b, the second transistor 1c, the third transistor 1f, the fourth transistor 1g, the fifth transistor 1i, the sixth transistor 1j, the seventh transistor 1n, the eighth transistor 1p, the ninth transistor 1q, and the tenth transistor 1r.

[0063] Next, we will explain the detailed configuration of the replica rectifier 2. As shown in Fig. 4, the replica rectifier 2 includes a first transistor 2b, a second transistor 2c, a first resistor 2d, a first capacitor 2e, a third transistor 2f, a fourth transistor 2g, a constant current source 2h, a fifth transistor 2i, a sixth transistor 2j, a second resistor 2k, a second capacitor 2m, a seventh transistor 2n, an eighth transistor 2p, a ninth transistor 2q, and a tenth transistor 2r.

[0064] 3 and 4, the replica rectifier 2 has, with the exception of the coupling capacitor 1a, the same circuit configuration and circuit performance as the main rectifier 1. Furthermore, the element performance (specifications such as element values) of each of the multiple circuit elements of the replica rectifier 2 is the same as the element performance of each of the multiple circuit elements of the main rectifier 1.

[0065] Furthermore, the reference current Iref of the replica rectifier 2 is set to be the same as the reference current Iref of the main rectifier 1, and the replica rectifier 2 is placed in the same temperature environment as the main rectifier 1. As a result, when no high-frequency signal RFin is input to the main rectifier 1, the same operating current flows through all the transistors of the replica rectifier 2 and all the transistors of the main rectifier 1.

[0066] The first transistor 2b is an n-type transistor. The gate terminal of the first transistor 2b is connected to the drain terminal of the fourth transistor 2g, one end of the first resistor 2d, and the output terminal of the constant current source 2h, and is also connected to the drain terminal of the eighth transistor 1p and the drain terminal of the ninth transistor 1q of the main rectifier 1 as shown in Figure 3. The drain terminal of this first transistor 2b is connected to the source terminal of the second transistor 2c, and the source terminal is grounded. This first transistor 2b is a corresponding transistor in the present invention.

[0067] Here, the gate voltage of the first transistor 2b (corresponding transistor) is set based on the second reference current Iref, the first resistor 2d, the first capacitor 2e, the third transistor 2f, the fourth transistor 2g, and the deviation current Idiff input from the main rectifier 1. That is, the gate voltage of the first transistor 2b is set to the reference operating voltage Vb (DC voltage) based on the second reference current Iref and the deviation current Idiff.

[0068] This reference operating voltage Vb is a voltage higher by the deviation current Idiff than the main operating voltage Vm in a state where the high-frequency signal RFin is not input to the main rectifier 1. Therefore, a source current (reference current) that is larger than the copy current of the second reference current Iref by the copy current of the deviation current Idiff flows through the first transistor 2b.

[0069] The second transistor 2c is an n-type transistor. As shown in the figure, the second transistor 2c is a cascode transistor cascode-connected to the first transistor 2b. That is, the source terminal of the second transistor 2c is connected to the drain terminal of the first transistor 2b. The gate terminal of the second transistor 2c is connected to the output terminal of the first resistor circuit 3, and a first bias voltage V1 is applied to the gate terminal.

[0070] Furthermore, the drain terminal of the second transistor 2c is connected to the drain terminal of the fifth transistor 2i, the gate terminal of the sixth transistor 2j, and one end of the second resistor 2k. The second transistor 2c is cascode-connected to the first transistor 2b. As a result, like the source current of the first transistor 2b, a source current (reference current) that is greater than the copy current of the second reference current Iref by the amount of the copy current of the deviation current Idiff also flows through the second transistor 2c.

[0071] The first resistor 2d has a predetermined resistance value. One end of the first resistor 2d is connected to the gate terminal of the first transistor 2b, the output terminal of the constant current source 2h, and the drain terminal of the fourth transistor 2g, and is also connected to the drain terminal of the eighth transistor 1p and the drain terminal of the ninth transistor 1q of the main rectifier 1 as shown in FIG. 3. The other end of the first resistor 2d is connected to one end of the first capacitor 2e and the gate terminal of the third transistor 2f. The first resistor 2d, together with the first capacitor 2e, constitutes a low-pass filter having a predetermined time constant.

[0072] The first capacitor 2e has a predetermined capacitance. One end of the first capacitor 2e is connected to the other end of the first resistor 2d and the gate terminal of the third transistor 2f, and the other end is grounded. The first capacitor 2e, together with the first resistor 2d, constitutes a low-pass filter having a predetermined time constant.

[0073] The third transistor 2f is an n-type transistor. As shown in the figure, the gate terminal of the third transistor 2f is connected to the other end of the first resistor 2d and one end of the first capacitor 2e, and the drain terminal is connected to the source terminal of the fourth transistor 2g, which is grounded. The third transistor 2f is diode-connected via the fourth transistor 2g. That is, the collector terminal of the third transistor 2f is connected to the gate terminal via the fourth transistor 2g.

[0074] The fourth transistor 2g is an n-type transistor. The fourth transistor 2g is a cascode transistor cascode-connected to the third transistor 2f. That is, the source terminal of the fourth transistor 2g is connected to the drain terminal of the third transistor 2f. The gate terminal of the fourth transistor 2g is connected to the output terminal of the first resistor circuit 3, and a first bias voltage V1 is applied to the gate terminal. The drain terminal of the fourth transistor 2g is connected to the output terminal of the constant current source 2h, the gate terminal of the first transistor 2b, one end of the first resistor 2d, and the drain terminal of the eighth transistor 1p and the drain terminal of the ninth transistor 1q of the main rectifier 1, as shown in FIG. 3 .

[0075] The constant current source 2h is connected to the gate terminal of the first transistor 2b, one end of the first resistor 2d, and the drain terminal of the fourth transistor 2g, and is also connected to the drain terminal of the eighth transistor 1p and the drain terminal of the ninth transistor 1q of the main rectifier 1 as shown in Figure 3. This constant current source 2h outputs a second reference current Iref (DC current) from its output terminal.

[0076] The fifth transistor 2i is a p-type transistor. As shown in the figure, the fifth transistor 2i is a cascode transistor cascode-connected to the sixth transistor 2j. That is, the source terminal of the fifth transistor 2i is connected to the drain terminal of the sixth transistor 2j. The gate terminal of the fifth transistor 2i is connected to the output terminal of the second resistor circuit 4, and a second bias voltage V2 is applied to the gate terminal. The drain terminal of the fifth transistor 2i is connected to the drain terminal of the second transistor 2c, the gate terminal of the sixth transistor 2j, and one end of the second resistor 2k.

[0077] The sixth transistor 2j is a p-type transistor. As shown in the figure, the gate terminal of the sixth transistor 2j is connected to the drain terminal of the second transistor 2c, the drain terminal of the fifth transistor 2i, and one end of the second resistor 2k, the drain terminal is connected to the source terminal of the fifth transistor 2i, and the source terminal is connected to the power supply Vcc, the other end of the second capacitor 2m, and the source terminal of the seventh transistor 2n.

[0078] A source current (reference current) based on the reference operating voltage Vb flows through the fifth transistor 2i and sixth transistor 2j in a cascode connection, similar to the first transistor 2b and second transistor 2c also in a cascode connection.

[0079] One end of the second resistor 2k is connected to the drain terminal of the second transistor 2c, the drain terminal of the fifth transistor 2i, and the gate terminal of the sixth transistor 2j, and the other end is connected to one end of the second capacitor 2m and the gate terminal of the seventh transistor 2n. The second resistor 2k and the second capacitor 2m form a low-pass filter having a predetermined time constant.

[0080] The second capacitor 2m has a predetermined capacitance. One end of the second capacitor 2m is connected to the other end of the second resistor 2k and the gate terminal of the seventh transistor 2n, and the other end is connected to the power supply Vcc, the source terminal of the sixth transistor 2j, and the source terminal of the seventh transistor 2n. The second capacitor 2m, together with the second resistor 2k, constitutes a low-pass filter having a predetermined time constant.

[0081] The seventh transistor 2n is a p-type transistor. As shown in the figure, the seventh transistor 2n has a gate terminal connected to the other end of the second resistor 2k and one end of the second capacitor 2m, a drain terminal connected to the source terminal of the eighth transistor 2p, and a source terminal connected to the power supply Vcc, the source terminal of the sixth transistor 2j, and the other end of the second capacitor 2m. Like the fifth transistor 2i and the sixth transistor 2j, a source current similar to the reference current flows through the seventh transistor 2n.

[0082] The eighth transistor 2p is a p-type transistor. As shown in the figure, the eighth transistor 2p is a cascode transistor cascode-connected to the seventh transistor 2n. That is, the source terminal of the eighth transistor 2p is connected to the drain terminal of the seventh transistor 2n. The gate terminal of the eighth transistor 2p is connected to the output terminal of the second resistor circuit 4, and a second bias voltage V2 is applied to the gate terminal.

[0083] Furthermore, the drain terminal of the eighth transistor 2p is connected to the drain terminal of the ninth transistor 2q and the gate terminal of the tenth transistor 2r, and is also connected to the gate terminal of the tenth transistor 1r of the main rectifier 1. In other words, the drain terminal of the eighth transistor 2p is an output terminal that outputs the reference voltage Vr to the main rectifier 1.

[0084] This reference voltage Vr is a DC voltage set by the source current of the eighth transistor 2p and the tenth transistor 2r in the replica rectifier 2, and the tenth transistor 1r of the main rectifier 1. In other words, this reference voltage Vr is a DC voltage that indicates the reference current of the replica rectifier 2.

[0085] The ninth transistor 2q is an n-type transistor. As shown in the figure, the ninth transistor 2q is a cascode transistor cascode-connected to the tenth transistor 2r. That is, the source terminal of the ninth transistor 2q is connected to the drain terminal of the tenth transistor 2r. The gate terminal of the ninth transistor 2q is connected to the output terminal of the first resistor circuit 3, and a first bias voltage V1 is applied to the gate terminal. Furthermore, the drain terminal of the ninth transistor 2q is connected to the drain terminal of the eighth transistor 2p.

[0086] The tenth transistor 2r is an n-type transistor. As shown in the figure, the gate terminal of the tenth transistor 2r is connected to the drain terminal of the eighth transistor 2p and the drain terminal of the ninth transistor 2q, and is also connected to the gate terminal of the tenth transistor 1r of the main rectifier 1. The drain terminal of the tenth transistor 2r is connected to the source terminal of the ninth transistor 2q, and the source terminal is grounded.

[0087] Here, among the components of the replica rectifier 2, the first transistor 2b, the second transistor 2c, the first resistor 2d, the first capacitor 2e, the third transistor 2f, the fourth transistor 2g, the constant current source 2h, the fifth transistor 2i, the sixth transistor 2j, the second resistor 2k, the second capacitor 2m, the seventh transistor 2n, and the eighth transistor 2p, as well as the first resistor circuit 3 and the second resistor circuit 4, constitute a reference current mirror circuit R.

[0088] In addition, the first transistor 2b, the second transistor 2c, the first resistor 2d, the first capacitor 2e, the third transistor 2f, the fourth transistor 2g, and the constant current source 2h of the replica rectifier 2, and the first resistor circuit 3, form a first reference current mirror circuit R1 using an n-type MOSFET.

[0089] The reference current (source current) flowing through the first transistor 2b and the second transistor 2c and the source current flowing through the third transistor 2f and the fourth transistor 2g are related to each other by the mirror ratio of the first reference current mirror circuit R1. That is, the source currents of the third transistor 2f and the fourth transistor 2g are set based on the reference current of the first transistor 2b and the second transistor 2c and the mirror ratio of the first reference current mirror circuit R1. The mirror ratio of the first reference current mirror circuit R1 is set to, for example, 1 or a value smaller than 1.

[0090] Furthermore, as can be seen from the wiring state, the fifth transistor 2i, the sixth transistor 2j, the second resistor 2k, the second capacitor 2m, the seventh transistor 2n, the eighth transistor 2p, and the second resistor circuit 4 form a second reference current mirror circuit R2 using p-type MOSFETs.

[0091] The source currents flowing through the fifth transistor 2i and the sixth transistor 2j and the source currents flowing through the seventh transistor 2n and the eighth transistor 2p are related to each other by the mirror ratio of the second reference current mirror circuit R2. That is, the source currents of the seventh transistor 2n and the eighth transistor 2p are set based on the source currents of the fifth transistor 2i and the sixth transistor 2j and the mirror ratio of the second reference current mirror circuit R2. The mirror ratio of the second reference current mirror circuit R2 is set to a value greater than 1, for example.

[0092] In addition, when the mirror ratio of the first reference current mirror circuit R1 and the mirror ratio of the second reference current mirror circuit R2 are both set to 1, when no high-frequency signal RFin is input to the main rectifier 1, the same operating current flows through all transistors of the replica rectifier 2, i.e., the first transistor 2b, the second transistor 2c, the third transistor 2f, the fourth transistor 2g, the fifth transistor 2i, the sixth transistor 2j, the seventh transistor 2n, the eighth transistor 2p, the ninth transistor 2q, and the tenth transistor 2r.

[0093] Furthermore, the drain terminal of the tenth transistor 2r in the replica rectifier 2 is connected to the gate terminal via the ninth transistor 2q. Therefore, the ninth transistor 1q and the tenth transistor 1r of the main rectifier 1, the ninth transistor 2q and the tenth transistor 2r of the replica rectifier 2, and the first resistor circuit 3 constitute a connection current mirror circuit C using n-type MOSFETs.

[0094] Of this connection current mirror circuit C, the input terminal (drain terminal of the 9th transistor 2q in the replica rectifier 2) is connected to the output terminal (drain terminal of the 8th transistor 2p in the replica rectifier 2) of the second reference current mirror circuit R2, and the output terminal (drain terminal of the 9th transistor 1q in the main rectifier 1) is connected to the output terminal (drain terminal of the 8th transistor 1p in the main rectifier 1) of the second main current mirror circuit M2.

[0095] That is, the main parts of the main rectifier 1 (first main current mirror circuit M1 and second main current mirror circuit M2) and the main parts of the replica rectifier 2 (first reference current mirror circuit R1 and second reference current mirror circuit R2) are interconnected to form a closed loop by the connecting current mirror circuit C. This closed loop is a negative feedback loop that applies negative feedback to the main rectifier 1 and replica rectifier 2 using current as a medium.

[0096] The coupling current mirror circuit C has a mirror ratio set to, for example, 1. That is, the coupling current mirror circuit C sets the source currents of the ninth transistor 1q and the tenth transistor 1r to a current equal to the reference current, i.e., the reference current, based on the reference current flowing from the output terminal of the second reference current mirror circuit R2.

[0097] 5A, the first resistor circuit 3 includes a first resistor 3a, a second resistor 3b, and a capacitor 3c, and outputs a first bias voltage V1. The first resistor 3a has a predetermined resistance value. One end of the first resistor 3a is connected to a power supply Vcc, and the other end is connected to one end of the second resistor 3b and one end of the capacitor 3c.

[0098] The second resistor 3b has a predetermined resistance value. One end of the second resistor 3b is connected to the other end of the first resistor 3a and one end of the capacitor 3c, and the other end is grounded. That is, the second resistor 3b is connected in series with the first resistor 3a and constitutes a first resistor voltage divider circuit together with the first resistor 3a. The first resistor voltage divider circuit outputs a first bias voltage V1 obtained by dividing the DC voltage (power supply voltage) of the power supply Vcc using the resistance values ​​of the first resistor 3a and the second resistor 3b.

[0099] One end of the capacitor 3c is connected to the other end of the first resistor 3a and one end of the second resistor 3b, and the other end is grounded. The capacitor 3c, together with the first resistor 3a and the second resistor 3b, forms a low-pass filter and prevents external noise from being superimposed on the first bias voltage V1.

[0100] 5B, the second resistor circuit 4 includes a first resistor 4a, a second resistor 4b, and a capacitor 4c, and outputs a second bias voltage V2. The first resistor 4a has a predetermined resistance value. One end of the first resistor 4a is connected to the power supply Vcc, and the other end is connected to one end of the second resistor 4b and one end of the capacitor 4c.

[0101] The second resistor 4b has a predetermined resistance value. One end of the second resistor 4b is connected to the other end of the first resistor 4a and one end of the capacitor 4c, and the other end is grounded. That is, the second resistor 4b is connected in series with the first resistor 4a and forms a second resistive voltage divider circuit together with the first resistor 4a. The second resistive voltage divider circuit outputs a second bias voltage V2 obtained by dividing the DC voltage (power supply voltage) of the power supply Vcc using the resistance values ​​of the first resistor 4a and the second resistor 4b.

[0102] One end of the capacitor 4c is connected to the other end of the first resistor 4a and one end of the second resistor 4b, and the other end is grounded. The capacitor 4c, together with the first resistor 4a and the second resistor 4b, forms a low-pass filter and prevents external noise from being superimposed on the second bias voltage V2.

[0103] 5B , the differential amplifier 5 includes a first resistor 5a, a first capacitor 5b, a second resistor 5c, a second capacitor 5d, an operational amplifier 5e, a feedback resistor 5f, and a voltage source 5g, and generates a difference voltage Vs by differentially amplifying the main operating voltage Vm of the main rectifier 1 and the reference operating voltage Vb of the replica rectifier 2. This difference voltage Vs is the power detection signal of the present invention.

[0104] The first resistor 5a has a predetermined resistance value. One end of the first resistor 5a serves as one input end of the differential amplifier 5 and is connected to the main rectifier 1 to receive the main operating voltage Vm. That is, one end of the first resistor 5a is connected to the other end of the coupling capacitor 1a in the main rectifier 1, the gate terminal of the first transistor 1b, one end of the first resistor 1d, the drain terminal of the fourth transistor 1g, and the output end of the constant current source 1h. The other end of the first resistor 5a is connected to one end of the first capacitor 5b, the negative-phase input terminal of the operational amplifier 5e, and one end of the feedback resistor 5f. The first resistor 5a and the first capacitor 5b constitute a low-pass filter.

[0105] The first capacitor 5b has a predetermined capacitance. One end of the first capacitor 5b is connected to the other end of the first resistor 5a, the negative-phase input terminal of the operational amplifier 5e, and one end of the feedback resistor 5f, and the other end is grounded. The first capacitor 5b and the first resistor 5a form a low-pass filter that removes AC components superimposed on the main operating voltage Vm and inputs only DC components of the main operating voltage Vm to the negative-phase input terminal of the operational amplifier 5e.

[0106] The second resistor 5c has a predetermined resistance value. One end of the second resistor 5c serves as the other input terminal of the differential amplifier 5 and is connected to the replica rectifier 2 to receive the reference operating voltage Vb. That is, one end of the second resistor 5c is connected to the gate terminal of the first transistor 2b, one end of the first resistor 2d, the collector terminal of the fourth transistor 2g, and the constant current source 2h in the replica rectifier 2, as well as to the drain terminal of the eighth transistor 1p and the drain terminal of the ninth transistor 1q in the main rectifier 1. The other end of the second resistor 5c is connected to one end of the second capacitor 5d and the positive input terminal of the operational amplifier 5e. The second resistor 5c and the second capacitor 5d constitute a low-pass filter.

[0107] The second capacitor 5d has a predetermined capacitance. One end of the second capacitor 5d is connected to the other end of the second resistor 5c and the positive-phase input terminal of the operational amplifier 5e, and the other end is grounded. The second capacitor 5d and the second resistor 5c form a low-pass filter that removes AC components that may be superimposed on the reference operating voltage Vb and allows only the DC component of the reference operating voltage Vb to be input to the positive-phase input terminal of the operational amplifier 5e.

[0108] The operational amplifier 5e is an integrated circuit having a negative-phase input terminal, a positive-phase input terminal, an output terminal, and an offset terminal. As shown in the figure, the negative-phase input terminal of the operational amplifier 5e is connected to the other end of the first resistor 5a, one end of the first capacitor 5b, and one end of the feedback resistor 5f. The positive-phase input terminal of the operational amplifier 5e is connected to the other end of the second resistor 5c and one end of the second capacitor 5d.

[0109] The output terminal of the operational amplifier 5e is connected to the other end of the feedback resistor 5f and to the input terminal of the voltage-current conversion circuit 6. The offset terminal of the operational amplifier 5e is connected to the output terminal of the voltage source 5g. In this operational amplifier 5e, the offset voltage between the negative phase input terminal and the positive phase input terminal is corrected by an offset correction voltage (DC voltage) applied to the offset terminal.

[0110] The feedback resistor 5f has a predetermined resistance value. One end of the feedback resistor 5f is connected to the inverting input terminal of the operational amplifier 5e, the other end of the first resistor 5a, and one end of the first capacitor 5b, and the other end is connected to the output terminal of the operational amplifier 5e and the input terminal of the voltage-current conversion circuit 6. The feedback resistor 5f, together with the first resistor 5a, sets the amplification factor of the differential amplifier 5. That is, the amplification factor of the differential amplifier 5 is set based on the ratio between the resistance value of the first resistor 5a and the resistance value of the feedback resistor 5f.

[0111] The output terminal of voltage source 5g is connected to the offset terminal of operational amplifier 5e. This offset terminal is used to boost (offset) the output voltage Vs of differential amplifier 5. This voltage source 5g generates a predetermined offset correction voltage (DC voltage) and outputs it to the offset terminal of operational amplifier 5e.

[0112] The output voltage (differential voltage Vs) of the differential amplifier 5 approaches 0 when the radio frequency signal RFin is small, and therefore cannot exceed the threshold voltage of the downstream voltage-current conversion circuit 6 unless the radio frequency signal RFin becomes large to a certain extent. In other words, the differential amplifier 5 cannot output a current to the voltage-current conversion circuit 6 unless the radio frequency signal RFin becomes large to a certain extent. In the differential amplifier 5 of this embodiment, an offset correction voltage is applied to the offset terminal from a voltage source 5g, thereby improving the sensitivity to the radio frequency signal RFin.

[0113] The differential voltage Vs output by the differential amplifier 5 to the voltage-current conversion circuit 6 is a DC voltage indicating the difference between the main operating voltage Vm of the main rectifier 1 and the reference operating voltage Vb of the replica rectifier 2, and is a detection voltage indicating the power of the high-frequency signal RFin. Furthermore, the main rectifier 1 and the replica rectifier 2 are configured with the same circuit configuration and circuit elements and are placed in the same temperature environment. This allows the differential voltage Vs to be a detection voltage that is free from the effects of manufacturing variations and temperature fluctuations in the first transistor 1b of the main rectifier 1.

[0114] 6A, the voltage-current conversion circuit 6 includes a transistor 6a and a resistor 6b, and converts the differential voltage Vs input from the differential amplifier 5 into a differential current Is. As shown in the figure, the transistor 6a is an n-type MOSFET. The gate terminal of the transistor 6a is connected to the output terminal of the differential amplifier 5 (the output terminal of the operational amplifier 5e), the drain terminal is connected to the input terminal of the output circuit W, and the source terminal is connected to one end of the resistor 6b.

[0115] The resistor 6b has a predetermined resistance value. One end of the resistor 6b is connected to the source terminal of the transistor 6a, and the other end is grounded. In the voltage-current conversion circuit 6, the differential current Is is set based on the differential voltage Vs applied to the gate terminal of the transistor 6a and the resistance value of the resistor 6b.

[0116] 6B, the output circuit W includes a first transistor 8a, a first resistor 8b, a second transistor 8c, a second resistor 8d, a third transistor 8e, and a third resistor 8f. The output circuit W is a current-voltage conversion circuit that converts the difference current Is into the output voltage Vout of the power detector A.

[0117] As shown in the figure, the first transistor 8a and the second transistor 8c in the output circuit W are p-type MOSFETs. The third transistor 8e in the output circuit W is an n-type MOSFET. As can be seen from the wiring, the first transistor 8a, the first resistor 8b, the second transistor 8c, the second resistor 8d, and the third transistor 8e form a current mirror circuit.

[0118] The gate terminal of the first transistor 8a is connected to its own drain terminal and the gate terminal of the second transistor 8c, and its drain terminal is connected to its own gate terminal, the gate terminal of the second transistor 8c, and the drain terminal of the transistor 6a. The source terminal of the first transistor 8a is connected to one end of the first resistor 8b. That is, the gate terminal and drain terminal of the first transistor 8a are diode-connected.

[0119] The first resistor 8b has a predetermined resistance value. One end of the first resistor 8b is connected to the source terminal of the first transistor 8a, and the other end is connected to the power supply Vcc and the other end of the second resistor 8d. The first resistor 8b, together with the second resistor 8d, sets the mirror ratio of the current mirror circuit.

[0120] The gate terminal of the second transistor 8c is connected to the gate terminal and drain terminal of the first transistor 8a and to the drain terminal of the transistor 6a. The drain terminal of the second transistor 8c is connected to the drain terminal and gate terminal of the third transistor 8e and to a next-stage circuit (not shown). The source terminal of the second transistor 8c is connected to one end of the second resistor 8d.

[0121] The drain terminal of the second transistor 8c is the output terminal of the output circuit W, and outputs an output voltage Vout to the next-stage circuit. This output voltage Vout is a DC voltage set by the source current of the second transistor 8c and the third transistor 8e and third resistor 8f, which are the loads of the second transistor 8c, and is a detection voltage that indicates the power of the high-frequency signal RFin.

[0122] One end of the second resistor 8d is connected to the source terminal of the second transistor 8c, and the other end is connected to the power supply Vcc and the other end of the first resistor 8b. The second resistor 8d, together with the first resistor 8b, sets the mirror ratio of the current mirror circuit. That is, the source current of the second transistor 8c is the difference current Is multiplied by the mirror ratio.

[0123] The third transistor 8e has a gate terminal connected to its own drain terminal and the next-stage circuit, a drain terminal connected to its own gate terminal and the next-stage circuit, and a source terminal connected to one end of the third resistor 8f. The third transistor 8e, together with the third resistor 8f, constitutes a load for the second transistor 8c, and generates an output voltage Vout based on the source current of the second transistor 8c.

[0124] The third resistor 8f has a predetermined resistance value. One end of the third resistor 8f is connected to the source terminal of the third transistor 8e, and the other end is grounded. The third resistor 8f, together with the third transistor 8e, constitutes a load for the second transistor 8c, and generates an output voltage Vout based on the source current of the second transistor 8c and its own resistance value.

[0125] The power detector A according to this embodiment generally comprises n first main current mirror circuits M1, n second main current mirror circuits M2, n first reference current mirror circuits R1, n second reference current mirror circuits R2, n connecting current mirror circuits C, a differential amplifier 5, and a voltage-current conversion circuit 6, as well as a single output circuit W.

[0126] Next, the operation and performance of the power detector A according to this embodiment will be described in detail.

[0127] First, in the first main current mirror circuit M1 of the main rectifier 1, the gate bias voltage of the first transistor 1b (initial stage transistor) is set based on the first reference current Iref output from the constant current source 1h. An externally input radio frequency signal RFin is half-wave rectified by the first transistor 1b using the gate bias voltage as a threshold value. That is, in the main rectifier 1, the radio frequency signal RFin is half-wave rectified in the first main current mirror circuit M1.

[0128] In the main rectifier 1, the output terminal of the first main current mirror circuit M1 is connected to the input terminal of the second main current mirror circuit M2. As a result, the half-wave rectified signal generated by the first main current mirror circuit M1 is input to the second main current mirror circuit M2, where it is smoothed and becomes a detection voltage (DC voltage) that indicates the power of the high-frequency signal RFin. This detection voltage is input to the gate terminal of the seventh transistor 1n of the second main current mirror circuit M2, where it is converted into a detection current, i.e., the source current of the seventh transistor 1n and the eighth transistor 1p.

[0129] Meanwhile, in the main rectifier 1, the output terminal of the second main current mirror circuit M2 is connected to the output terminal of the connecting current mirror circuit C. Therefore, the source currents of the ninth transistor 1q and the tenth transistor 1r that constitute the connecting current mirror circuit C are set to a reference current based on the reference voltage Vr input from the replica rectifier 2 to the gate terminal of the tenth transistor 1r.

[0130] Therefore, in the main rectifier 1, a deviation current Idiff, which is the difference between the detected current and the reference current, is output from the output terminal of the second main current mirror circuit M2, i.e., the output terminal of the connecting current mirror circuit C, to the replica rectifier 2. Such deviation current Idiff indicates the power of the high-frequency signal RFin, and is a current signal that indicates the operating state of the replica rectifier 2 when the high-frequency signal RFin is not input.

[0131] Next, in the first reference current mirror circuit R1 of the replica rectifier 2, the gate bias voltage of the first transistor 2b (corresponding transistor) is set based on the total current of the deviation current Idiff and the second reference current Iref, and the source currents of the first transistor 2b and the second transistor 2c are set to an amount obtained by multiplying the total current by the mirror ratio of the first reference current mirror circuit R1.

[0132] In the replica rectifier 2, the output terminal of the first reference current mirror circuit R1 is connected to the input terminal of the second reference current mirror circuit R2, so the reference current of the second reference current mirror circuit R2 is the output current of the first reference current mirror circuit R1, i.e., the source current of the first transistor 2b and the second transistor 2c. In other words, the second reference current mirror circuit R2 sets the source current (reference current) of the seventh transistor 2n and the eighth transistor 2p to the amount obtained by multiplying the reference current by its own mirror ratio.

[0133] Since the output terminal of the second reference current mirror circuit R2 is connected to the input terminal of the connecting current mirror circuit C, the reference current is the reference current of the connecting current mirror circuit C. In other words, the connecting current mirror circuit C sets the source current of the ninth transistor 1q and the tenth transistor 1r of the main rectifier 1 to the amount obtained by multiplying the reference current by its own mirror ratio.

[0134] That is, the main rectifier 1 and replica rectifier 2 in the power detector A according to this embodiment are in a mutual feedback (negative feedback) relationship. In a reference state in which no high-frequency signal RFin is input to the main rectifier 1, the deviation current Idiff generated by the main rectifier 1 is zero.

[0135] That is, in the reference state where no high-frequency signal RFin is input to the main rectifier 1, the gate voltage of the first transistor 1b (first-stage transistor) of the main rectifier 1, i.e., the main operating voltage Vm, and the gate voltage of the first transistor 2b (corresponding transistor) of the replica rectifier 2, i.e., the reference operating voltage Vb, are equal.

[0136] In contrast, in an operating state in which the radio frequency signal RFin is input to the main rectifier 1, the deviation current Idiff increases from zero in accordance with the power (amplitude) of the radio frequency signal RFin. As a result, the reference operating voltage Vb of the replica rectifier 2 also increases, and the main operating voltage Vm and the reference operating voltage Vb have a deviation in accordance with the power of the radio frequency signal RFin.

[0137] The main operating voltage Vm and the reference operating voltage Vb are converted into a difference voltage Vs by being differentially amplified by the differential amplifier 5. This difference voltage Vs is a voltage signal based on the difference between the main operating voltage Vm and the reference operating voltage Vb, which are generated by the main rectifier 1 and the replica rectifier 2, which have the same circuit configuration and circuit performance.

[0138] That is, in addition to indicating the power of the high-frequency signal RFin, the differential voltage Vs corrects manufacturing variations in the first transistor 1b (initial stage transistor) of the main rectifier 1 by the manufacturing variations in the first transistor 2b (corresponding transistor) of the replica rectifier 2, which is identical to the first transistor 1b, and corrects operational variations due to temperature fluctuations of the first transistor 1b by the operational variations due to temperature fluctuations of the first transistor 2b of the replica rectifier 2, which is identical to the first transistor 1b.

[0139] Such a difference voltage Vs is converted into a difference current Is by the voltage-current conversion circuit 6, and the difference current Is is input to the output circuit W. Since the difference current Is is input to the output circuit W from each of the n power detection units U1 to Un, the n difference currents Is are averaged at the input terminal of the output circuit W. In other words, the detection error that may be contained in the n difference currents Is is reduced by the averaging process.

[0140] The difference current Is after this averaging process is converted into an output voltage Vout in the output circuit W. This output voltage Vout is the output signal of the power detector A according to this embodiment, and is a signal that indicates the power of the high-frequency signal RFin in which the effects of manufacturing variations and temperature fluctuations of the first transistor 1b (initial-stage transistor) of the main rectifier 1 have been corrected.

[0141] In such a power detector A, the first main current mirror circuit M1 and the second main current mirror circuit M2, which are the main parts of the main rectifier 1, and the first reference current mirror circuit R1 and the second reference current mirror circuit R2, which are the main parts of the replica rectifier 2, are interconnected by a connecting current mirror circuit C, thereby forming a negative feedback loop using current as a medium (current negative feedback loop). Therefore, according to this embodiment, it is possible to suppress the effects of external noise compared to when a negative feedback loop using voltage as a medium (voltage negative feedback loop) is formed as in the background art.

[0142] Furthermore, according to this embodiment, the negative feedback loop is formed by interconnecting a first main current mirror circuit M1 formed of n-type transistors, a second main current mirror circuit M2 formed of p-type transistors, a first reference current mirror circuit R1 formed of n-type transistors, a second reference current mirror circuit R2 formed of p-type transistors, and a coupling current mirror circuit C formed of n-type transistors, thereby making it possible to reduce the number of parts.

[0143] In addition, in the power detector A according to this embodiment, the mirror ratios of the second main current mirror circuit M2 and the second reference current mirror circuit R2 are set to values ​​greater than 1, and the mirror ratios of the first main current mirror circuit M1 and the first reference current mirror circuit R1 are set to values ​​less than or equal to 1.

[0144] That is, the mirror ratio of the second main current mirror circuit M2 and the second reference current mirror circuit R2 is set to be larger than the mirror ratio of the first main current mirror circuit M1 and the first reference current mirror circuit R1. According to this embodiment, it is possible to improve the sensitivity in detecting the power of the radio frequency signal RFin compared to when the mirror ratio of the second main current mirror circuit M2 and the second reference current mirror circuit R2 is set to be smaller than the mirror ratio of the first main current mirror circuit M1 and the first reference current mirror circuit R1.

[0145] Furthermore, according to this embodiment, n power detection units U1 to Un are provided, and the detected current Is of each of the power detection units U1 to Un is averaged, which improves the detection accuracy of the power of the radio frequency signal RFin compared to when a single power detection unit is provided.

[0146] Second Embodiment A second embodiment of the present invention will be described below with reference to Fig. 7. In the following description, components common to the first embodiment are designated by the same reference numerals, and redundant description will be omitted. The following description will focus on differences from the first embodiment.

[0147] FIG. 7 is a circuit diagram showing the overall configuration of a power detector A1 according to a second embodiment of the present invention. The power detector A1 according to the second embodiment differs from the power detector A according to the first embodiment in that each of the n power detection units U1 to Un further includes an open / close switch 7. One contact of the open / close switch 7 is connected to the output terminal of the voltage-current conversion circuit 6, and the other contact is connected to the input terminal of the output circuit W. Specifically, the drain terminal of the transistor 6a of the voltage-current conversion circuit 6 is connected to one contact of the open / close switch 7, and the drain and gate terminals of the first transistor 8a included in the output circuit W are connected to the other contact of the open / close switch 7. The open / close switch 7 is selectively set to a closed state for each of the n power detection units U1 to Un. In other words, one of the n difference currents Is generated by the n power detection units U1 to Un is input to the output circuit W.

[0148] The power detector A1 of this embodiment as a whole comprises n first main current mirror circuits M1, n second main current mirror circuits M2, n first reference current mirror circuits R1, n second reference current mirror circuits R2, n connection current mirror circuits C, n differential amplifiers 5, n voltage-current conversion circuits 6, n open / close switches 7, and a single output circuit W.

[0149] According to the power detector A1 of this embodiment, the power detection signals of the multiple power detection units are sequentially switched using an open / close switch and transmitted to an output circuit, thereby making it possible to detect the power of the high-frequency signals input to and output from each of the multiple power detection units.

[0150] The present invention is not limited to the first and second embodiments. For example, the following modifications are possible: (1) In the first and second embodiments, MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) are used as the transistors that make up each current mirror circuit, but the present invention is not limited to this. For example, transistors of a type other than MOSFETs, such as junction transistors, may be used.

[0151] (2) In the first and second embodiments, the mirror ratios of the second main current mirror circuit M2 and the second reference current mirror circuit R2 are set to values ​​greater than 1, and the mirror ratios of the first main current mirror circuit M1 and the first reference current mirror circuit R1 are set to values ​​less than or equal to 1. However, the present invention is not limited to this. Furthermore, the mirror ratio of the coupling current mirror circuit C is not limited to 1.

[0152] (3) In the first and second embodiments, n power detection units U1 to Un are provided, but the present invention is not limited to this. For example, if averaging of detected power is not required, it is sufficient to provide only one power detection unit.

[0153] A, A1 power detector, C connection current mirror circuit, M main current mirror circuit, M1 first main current mirror circuit, M2 second main current mirror circuit, R reference current mirror circuit, R1 first reference current mirror circuit, R2 second reference current mirror circuit, U1 to Un power detection unit, W output circuit, 1 main rectifier, 2 replica rectifier, 3 first resistor circuit, 4 second resistor circuit, 5 differential amplifier, 6 voltage current conversion circuit, 7 open / close switch

Claims

1. A main current mirror circuit that rectifies a high-frequency signal and outputs a detection current indicating the power of the high-frequency signal from the main output terminal, A reference current mirror circuit having the same circuit configuration and performance as the main current mirror circuit, A connecting current mirror circuit whose input terminal is connected to the reference output terminal of the reference current mirror circuit and whose connecting output terminal is connected to the main output terminal, and which outputs a reference current, A differential amplifier generates a power detection signal by differentially amplifying the input voltage of the first-stage transistor to which the high-frequency signal is input in the main current mirror circuit and the input bias voltage of the corresponding transistor to which the first-stage transistor is input in the reference current mirror circuit. Equipped with, In the main current mirror circuit, the input bias voltage of the first stage transistor is set based on the first reference current. In the aforementioned reference current mirror circuit, the input bias voltage of the corresponding transistor is set based on the sum of the deviation current between the detection current and the reference current and the second reference current. The first reference current and the second reference current are the same. Power detector.

2. The aforementioned main current mirror circuit is A first main current mirror circuit, which is composed of n-type transistors and includes the first stage transistor, A second main current mirror circuit, which is connected to the output terminal of the first main current mirror circuit and is composed of a p-type transistor, Equipped with, The aforementioned reference current mirror circuit is A first reference current mirror circuit, which is composed of n-type transistors and includes the corresponding transistors, A second reference current mirror circuit, which is connected to the output terminal of the first reference current mirror circuit and is composed of a p-type transistor, Equipped with, The power detector according to claim 1.

3. The second main current mirror circuit and the second reference current mirror circuit are configured such that the mirror ratio is set to a value greater than 1. The power detector according to claim 2.

4. The first main current mirror circuit and the first reference current mirror circuit are configured such that the mirror ratio is set to a value of 1 or less than 1. The power detector according to claim 2 or 3.

5. The aforementioned n-type transistor is It is an n-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), The aforementioned p-type transistor is It is a p-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The power detector according to claim 2 or 3.

6. The differential amplifier is It is an instrumentation amplifier. The power detector according to claim 1 or 2.

7. A voltage-to-current conversion circuit that converts the output voltage of the differential amplifier into current, A current-voltage conversion circuit that converts the output current of the voltage-current conversion circuit into a voltage, Furthermore, The power detector according to claim 1 or 2.

8. The main circuit consists of a main rectifier, a first resistor circuit, and a second resistor circuit, A reference circuit comprising a replica rectifier, the first resistor circuit, and the second resistor circuit, A differential amplifier and It is equipped with multiple power detection units, each having the following: The power of the high-frequency signal is detected by averaging the power detection signals of the plurality of power detection units. The power detector according to claim 1 or 2.

9. The main circuit consists of a main rectifier, a first resistor circuit, and a second resistor circuit, A reference circuit comprising a replica rectifier, the first resistor circuit, and the second resistor circuit, A differential amplifier and Open / close switch, It is equipped with multiple power detection units, each having the following: The power of the high-frequency signals input to and output from each of the multiple power detection units is detected by sequentially switching the power detection signals of each of the multiple power detection units using the on / off switch and transmitting them to the output circuit. The power detector according to claim 1 or 2.