Display device

Abstract

The display device includes a substrate having a display area, a non-display area outside the display area, a pad area located within the non-display area, a bending area between the display area and the pad area, and a peripheral area between the pad area and the bending area, a fan-out portion disposed on the substrate and including a plurality of conductive lines connecting the display area and the pad area, and a strain gauge disposed on the substrate and located in the peripheral area.

Description

Technology Field

[0001] The present invention relates to a display device. More specifically, the present invention relates to a display device with improved reliability. Background Technology

[0002] As the field of display technology for visually representing various electrical signal information develops rapidly, a variety of flat panel display devices with excellent characteristics such as thinness, lightness, and low power consumption are being introduced. Furthermore, display devices have recently been introduced in which physical buttons and other elements are removed from the front surface, and the display area for images is expanded. The problem to be solved

[0003] Meanwhile, for the display device to operate, a semiconductor chip called a display driver IC (DDI) located in the driving circuit is used. The DDI plays the role of controlling pixels by transmitting signals to thin-film transistors.

[0004] If an impact is applied to the area surrounding the driving circuit (hereinafter referred to as the surrounding area), a defect may occur in the display device. Furthermore, if the stress caused by the impact applied to the surrounding area approaches a critical threshold, there is a high probability that a defect will occur in the display device; however, since the display device operates normally, it may be difficult to detect this in advance.

[0005] Accordingly, embodiments of the present invention provide a display device capable of preventing defects in the display device by more accurately identifying stress caused by impact applied to a surrounding area. means of solving the problem

[0006] To achieve one objective of the present invention as described above, a display device according to one embodiment of the present invention may include a substrate having a display area, a non-display area outside the display area, a pad area located within the non-display area, a bending area between the display area and the pad area, and a peripheral area between the pad area and the bending area, a fan-out portion disposed on the substrate and including a plurality of conductive lines connecting the display area and the pad area, and a strain gauge disposed on the substrate and located in the peripheral area.

[0007] According to one embodiment, the display device may further include a main voltage line positioned between the display area and the bending area and a connecting portion protruding from the main voltage line and extending toward the pad area and crossing the bending area.

[0008] According to one embodiment, the connection may be placed on the same layer as the strain gauge.

[0009] According to one embodiment, the fan-out portion includes a first fan-out portion and a second fan-out portion spaced apart from each other in at least the surrounding area, the first fan-out portion is located in the center of the surrounding area, the second fan-out portion is located on the side of the surrounding area, and the connecting portion may be located in the spaced-out area between the first fan-out portion and the second fan-out portion in the bending area.

[0010] According to one embodiment, the strain gauge may be located in the first fan-out portion.

[0011] According to one embodiment, the strain gauge may be extended in a direction parallel to the connection part.

[0012] According to one embodiment, the strain gauge may be located in the second fan-out portion.

[0013] According to one embodiment, the strain gauge may be extended in a direction parallel to the main voltage line.

[0014] According to one embodiment, each of the plurality of conductive lines includes a first region located between the display area and the bending area, a second region located in the surrounding area, and a connecting conductive layer that electrically connects the first region and the second region and crosses the bending area, and the connecting conductive layer may include a first connecting conductive layer and a second connecting conductive layer that are connected in parallel with each other and overlap each other on a plane.

[0015] According to one embodiment, the first region and the second region may be disposed on the same layer, and the connecting conductive layer may be disposed on a different layer from the first region.

[0016] According to one embodiment, the second connecting conductive layer is disposed on the first connecting conductive layer, and the second connecting conductive layer may be disposed on the same layer as the strain gauge.

[0017] According to one embodiment, the display area may have a plurality of pixel circuits, a plurality of light-emitting elements electrically connected to each of the plurality of pixel circuits, and a plurality of data lines electrically connected to the plurality of pixel circuits, and the plurality of conductive lines are electrically connected to the plurality of data lines to transmit an electrical signal from a driving circuit unit located in the pad area to the plurality of data lines, and the first connecting conductive layer may be disposed on the same layer as the plurality of data lines.

[0018] According to one embodiment, driving voltage supply lines that provide driving signals to the plurality of pixel circuits are further located in the display area, and the strain gauge may be disposed on the same layer as the driving voltage supply lines.

[0019] According to one embodiment, the strain gauge and the driving voltage supply lines may include the same material.

[0020] According to one embodiment, the strain gauge includes a resistance wire that reciprocates a plurality of times to form a bend, and the resistance wire can be electrically connected to a driving circuit located in the pad area.

[0021] According to one embodiment, the strain gauge can detect stress generated when an impact is applied to the surrounding area.

[0022] To achieve one objective of the present invention as described above, a display device according to another embodiment of the present invention may include a substrate having a display area, a non-display area outside the display area, a pad area located within the non-display area, a bending area between the display area and the pad area, and a peripheral area between the pad area and the bending area; a fan-out portion disposed on the substrate and including a first fan-out portion located in the center of the peripheral area and a second fan-out portion located on the side of the peripheral area; and a strain gauge including a first strain gauge located in the first fan-out portion and a second strain gauge located in the second fan-out portion.

[0023] According to one embodiment, the first strain gauge and the second strain gauge may be placed on the same layer.

[0024] According to one embodiment, the first strain gauge may extend from the surrounding area toward the bending area, and the second strain gauge may extend in a direction perpendicular to the first strain gauge. Effects of the invention

[0025] According to embodiments of the present invention, by accurately identifying the stress occurring in the surrounding area of ​​the display device, the reliability of the display device can be improved by detecting in advance whether damage occurs in the surrounding area.

[0026] However, the effects of the present invention are not limited to the effects described above, and may be extended in various ways without departing from the spirit and scope of the present invention. Brief explanation of the drawing

[0027] FIG. 1 is a schematic plan view illustrating a display device according to one embodiment of the present invention. FIG. 2 is a perspective view schematically illustrating the bending shape of the display device of FIG. 1. Figure 3 is an equivalent circuit diagram of one pixel of the display device of Figure 1. FIG. 4 is a schematic cross-sectional view illustrating an example of the I-I' section of FIG. 1. Figure 5 is a schematic plan view of section A of Figure 1 enlarged. FIG. 6 is a schematic plan view illustrating a strain gauge located in the first fan-out section of FIG. 5. FIG. 7 is a schematic plan view illustrating a strain gauge located in the second fan-out section of FIG. 5. FIG. 8 is a schematic cross-sectional view illustrating an example of the II-II' section of FIG. 6. Figure 9 is a schematic plan view of section B of Figure 5 enlarged. FIG. 10 is a schematic cross-sectional view illustrating an example of the III-III' section of FIG. 9. FIG. 11 is a schematic cross-sectional view illustrating an example of the IV-IV' section of FIG. 9. FIG. 12 is a schematic cross-sectional view illustrating an example of the V-V' section of FIG. 9. FIG. 13 is a schematic cross-sectional view illustrating an example of the VI-VI' section of FIG. 9. FIG. 14 is a schematic cross-sectional view illustrating an example of the VII-VII' section of FIG. 9. Specific details for implementing the invention

[0028] Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are given the same reference numerals, and redundant descriptions of identical components are omitted.

[0029] FIG. 1 is a plan view schematically illustrating a display device according to one embodiment of the present invention, and FIG. 2 is a perspective view schematically illustrating the bending shape of the display device of FIG. 1.

[0030] Referring to FIGS. 1 and 2, a display device (1) according to one embodiment of the present invention includes a display area (DA) where a plurality of pixels are located, and a non-display area (NDA) located outside the display area (DA). Additionally, the non-display area (NDA) may include a pad area (PDA) located on one side of the display area (DA) and an area to which various electronic components such as an integrated circuit (IC) or a printed circuit board are electrically attached, a bending area (BA) between the display area (DA) and the pad area (PDA), and a peripheral area (SA) between the pad area (PDA) and the bending area (BA). These display area (DA), non-display area (NDA), pad area (PDA), bending area (BA), and peripheral area (SA) may be partitioned on a substrate (100).

[0031] Meanwhile, FIG. 1 is a plan view illustrating the shape of a substrate (100), etc., during the manufacturing process of a display device (1). As shown in FIG. 2, the substrate (100), etc., can have a bending area (BA) bent based on a bending axis (BAX) extended in a first direction (D1). At this time, the bending direction can be set so that the pad area (PDA) is located behind the display area (DA). Accordingly, the area of ​​the non-display area (NDA) recognized by the user can be minimized.

[0032] To this end, the substrate (100) may include various materials having flexible, bendable, or rollable properties. For example, the substrate (100) may include a polymer resin such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene napthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP). Additionally, the substrate (100) may have a multilayer structure comprising two layers containing the above-mentioned polymer resin and a barrier layer containing an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, etc.) interposed between the layers.

[0033] Meanwhile, in the substrate (100), the width of the first direction (D1) of the non-display area (NDA), including the bending area (BA), may be smaller than the width of the first direction (D1) of the portion where the display area (DA) is located. Additionally, the corner portion (100c) of the edge of the substrate (100) may have a rounded shape. Such a shape may also be applied to the display area (DA).

[0034] For example, when the display area (DA) has a shape similar to a rectangle or a square overall, including mutually facing first edges (E1) and second edges (E2), and mutually facing third edges (E3) and fourth edges (E4) located between the first edges (E1) and second edges (E2), it may have rounded shapes at the corners. Additionally, the display area (DA) may have rounded shapes in other parts of the edges as well.

[0035] A peripheral area (SA) is adjacent to the fourth edge (E4) among the first edge (E1) to the fourth edge (E4), and a fan-out section (20) in which a plurality of conductive lines (CL in FIG. 4) are extended and arranged may be disposed in the peripheral area (SA). The conductive lines (CL in FIG. 4) cross a bending area (BA), and one end may be electrically connected to a pixel circuit (PC) of a display area (DA), and the other end may be connected to a driving circuit section (30) including various electronic components such as an integrated circuit (IC).

[0036] FIG. 3 is an equivalent circuit diagram of one pixel of the display device of FIG. 1, and FIG. 4 is a cross-sectional view schematically illustrating an example of the I-I' section of FIG. 1.

[0037] First, referring to FIG. 3, a pixel (PX) may include a pixel circuit (PC) connected to a scan line (SL) and a data line (DL) and a light-emitting element (300 in FIG. 4). The light-emitting element may be an organic light-emitting diode (OLED).

[0038] The pixel circuit (PC) may include a driving thin-film transistor (Td), a switching thin-film transistor (Ts), and a storage capacitor (Cst).

[0039] The switching thin-film transistor (Ts) is connected to the scan line (SL) and the data line (DL), and can transmit the data signal input through the data line (DL) to the driving thin-film transistor (Td) according to the scan signal input through the scan line (SL).

[0040] The storage capacitor (Cst) is connected to the switching thin-film transistor (Ts) and the driving voltage supply line (PL), and can store a voltage corresponding to the difference between the voltage received from the switching thin-film transistor (Ts) and the driving voltage (ELVDD) supplied to the driving voltage supply line (PL).

[0041] The driving thin-film transistor (Td) is connected to the driving voltage supply line (PL) and the storage capacitor (Cst), and can control the driving current flowing from the driving voltage supply line (PL) to the organic light-emitting diode (OLED) in correspondence with the voltage value stored in the storage capacitor (Cst). The organic light-emitting diode (OLED) can emit light having a predetermined brightness by the driving current. The organic light-emitting diode (OLED) can emit, for example, red, green, blue, or white light.

[0042] Meanwhile, FIG. 3 describes a case where one pixel (PX) includes two thin-film transistors (Ts, Td) and one storage capacitor (Cst), but the present invention is not limited thereto. In other embodiments, the pixel circuit (PC) may be varied in various ways, such as including three or more thin-film transistors or two or more storage capacitors.

[0043] Below, the structure of the display device (1 in FIG. 1) will be explained in more detail with reference to FIG. 4.

[0044] Referring to FIG. 4, the light-emitting element (300) can be electrically connected to the first and second thin-film transistors (T1, T2) and the storage capacitor (Cst). The light-emitting element (300), the first thin-film transistor (T1), the second thin-film transistor (T2), and the storage capacitor (Cst) may correspond to the organic light-emitting element (OLED of FIG. 3), the driving thin-film transistor (Td of FIG. 3), the switching thin-film transistor (Ts of FIG. 3), and the storage capacitor (Cst of FIG. 3) described in FIG. 3, respectively.

[0045] The first thin-film transistor (T1) includes a first semiconductor layer (Act1) and a first gate electrode (G1), and the second thin-film transistor (T2) may include a second semiconductor layer (Act2) and a second gate electrode (G2).

[0046] The first semiconductor layer (Act1) and the second semiconductor layer (Act2) may include amorphous silicon, polycrystalline silicon, oxide semiconductor, or organic semiconductor material. The first semiconductor layer (Act1) has a channel region (C1) and source regions (S1) and drain regions (D1) disposed on both sides of the channel region (C1), and the second semiconductor layer (Act2) may have a channel region (C2) and source regions (S2) and drain regions (D2) disposed on both sides of the channel region (C2).

[0047] The source regions (S1, S2) and drain regions (D1, D2) of the first and second semiconductor layers (Act1, Act2) can be understood as the source electrode and drain electrode of the first and second thin-film transistors (T1, T2), respectively.

[0048] The first gate electrode (G1) and the second gate electrode (G2) may be arranged to overlap the channel region (C1) of the first semiconductor layer (Act1) and the channel region (C2) of the second semiconductor layer (Act2), respectively, with the gate insulating layer (120) in between. The first and second gate electrodes (G1, G2) may be a single film or a multilayer film made of a conductive material comprising at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti).

[0049] Meanwhile, FIG. 4 illustrates that the first gate electrode (G1) and the second gate electrode (G2) are disposed on the same layer, but the present invention is not limited thereto. In another embodiment, the first gate electrode (G1) and the second gate electrode (G2) may be disposed on different layers. Also, FIG. 4 illustrates the first and second gate electrodes (G1, G2) as a top gate type disposed on the first and second semiconductor layers (Act1, Act2), but the present invention is not limited thereto. In another embodiment, the first and second gate electrodes (G1, G2) may be a bottom gate type disposed below the first and second semiconductor layers (Act1, Act2).

[0050] A storage capacitor (Cst) may include a first storage electrode (CE1) and a second storage electrode (CE2) that overlap each other. The first and second storage electrodes (CE1, CE2) may include a low-resistance conductive material comprising at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti).

[0051] A storage capacitor (Cst) may overlap with a first thin-film transistor (T1), and the first thin-film transistor (T1) may be a driving thin-film transistor. FIG. 4 illustrates a case where the storage capacitor (Cst) is arranged to overlap with the first thin-film transistor (T1) and the first storage electrode (CE1) is the first gate electrode (G1) of the first thin-film transistor (T1), but the present invention is not limited thereto. In another embodiment, the storage capacitor (Cst) may be arranged so as not to overlap with the first thin-film transistor (T1).

[0052] A buffer layer (110) may be disposed between the substrate (100) and the first and second thin-film transistors (T1, T2). The buffer layer (110) may include an inorganic insulating material. For example, the buffer layer (110) may be a single film or a multilayer film comprising at least one of silicon oxynitride (SiON), silicon oxide (SiOx), and silicon nitride (SiNx).

[0053] A gate insulating layer (120) may be disposed between the first and second gate electrodes (G1, G2) and the first and second semiconductor layers (Act1, Act2). The gate insulating layer (120) may include an inorganic insulating material. For example, the gate insulating layer (120) may be a single film or a multilayer film comprising at least one of silicon oxynitride (SiON), silicon oxide (SiOx), and silicon nitride (SiNx).

[0054] The first and second thin-film transistors (T1, T2) may be covered by first and second interlayer insulating layers (131, 132). The first interlayer insulating layer (131) may be placed directly above the first and second thin-film transistors (T1, T2) and / or directly above the first storage electrode (CE1). The second interlayer insulating layer (132) may be placed on the second storage electrode (CE2). The first and second interlayer insulating layers (131, 132) may each be a single film or a multilayer film comprising at least one of silicon oxynitride (SiON), silicon oxide (SiOx), and silicon nitride (SiNx). In one embodiment, the first interlayer insulating layer (131) may be a single film of silicon nitride (SiNx), and the second interlayer insulating layer (132) may be a multilayer film of silicon nitride (SiNx) and silicon oxide (SiOx).

[0055] A data line (DL) may be disposed on the second interlayer insulating layer (132). The data line (DL) may be electrically connected to the first thin-film transistor (T1) to provide a data signal. The data line (DL) may be a single film or a multilayer film comprising at least one of aluminum (Al), copper (Cu), titanium (Ti), and alloys thereof. In one embodiment, the data line (DL) may be a three-layer film of Ti / Al / Ti.

[0056] The driving voltage supply line (PL) can provide a driving signal to the second thin-film transistor (T2). The driving voltage supply line (PL) may be placed on a different layer from the data line (DL). In this specification, "A and B are placed on different layers" indicates a case where at least one insulating layer is interposed between A and B, so that one of A and B is placed below at least one insulating layer and the other is placed above at least one insulating layer. A first flattening insulating layer (141) may be placed between the driving voltage supply line (PL) and the data line (DL).

[0057] The driving voltage supply line (PL) may be a single film or a multilayer film comprising at least one of aluminum (Al), copper (Cu), titanium (Ti), and alloys thereof. In one embodiment, the driving voltage supply line (PL) may be a three-layer film of Ti / Al / Ti. FIG. 4 illustrates a configuration in which the driving voltage supply line (PL) is placed only on the first flattening insulating layer (141), but the present invention is not limited thereto. In another embodiment, the driving voltage supply line (PL) may be connected to a lower additional voltage line (not shown) formed together with a data line (DL) through a through hole (not shown) formed in the first flattening insulating layer (141) to reduce resistance.

[0058] The second flattening insulating layer (142) can cover the driving voltage supply line (PL). The first and second flattening insulating layers (141, 142) may include organic materials. The organic materials may include imide-based polymers, general-purpose polymers such as polymethylmethacrylate (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, aryl ether-based polymers, amide-based polymers, fluorine-based polymers, p-xylene-based polymers, vinyl alcohol-based polymers, and blends thereof.

[0059] On the second flattening insulating layer (142), a light-emitting element (300) may be positioned having a pixel electrode (310), a common electrode (330), and an intermediate layer (320) interposed between the pixel electrode (310) and the common electrode (330) and including a light-emitting layer.

[0060] A pixel defining film (150) may be disposed on the pixel electrode (310). The pixel defining film (150) serves to define pixels by having openings corresponding to each pixel, that is, openings that expose at least the central part of the pixel electrode (310). Additionally, the pixel defining film (150) can prevent the occurrence of arcs, etc. between the edges of the pixel electrode (310) and the common electrode (330) by increasing the distance between them. The pixel defining film (150) may be formed from an organic material such as polyimide or HMDSO (hexamethyldisiloxane).

[0061] The pixel electrode (310) can be electrically connected to a pixel circuit, such as a pixel circuit (PC of FIG. 3) including first and second thin-film transistors (T1, T2) and a storage capacitor (Cst), through first and second connecting metals (CM1, CM2).

[0062] The intermediate layer (320) may include low molecular weight or high molecular weight materials. If it includes low molecular weight materials, it may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL) are stacked in a single or composite structure, and may include various organic materials including copper phthalocyanine (CuPc), N,N-Di(naphthalene-1-yl)-N,N'-diphenyl-benzidine (NPB), and tris-8-hydroxyquinoline aluminum (Alq3). These layers may be formed by vacuum deposition.

[0063] When the intermediate layer (320) includes a polymer material, it may generally have a structure including a hole transport layer (HTL) and an emitting layer (EML). In this case, the hole transport layer (HTL) may include PEDOT, and the emitting layer (EML) may include polymer materials such as PPV (Poly-Phenylenevinylene) and Polyfluorene. The structure of the intermediate layer (320) is not limited to the above and may have various structures. For example, the intermediate layer (320) may include a layer that is integral across a plurality of pixel electrodes (310), or a layer patterned to correspond to each of the plurality of pixel electrodes (310).

[0064] The common electrode (330) can be positioned to cover the display area (DA). That is, the common electrode (330) can be formed as a single unit to cover a plurality of organic light-emitting elements (300).

[0065] An encapsulation layer (500) is located on the upper portion of the common electrode (330). The encapsulation layer (500) can serve to protect the organic light-emitting element (300) from moisture or oxygen from the outside. To this end, the encapsulation layer (500) may have a shape that extends not only to the display area (DA) where the organic light-emitting element (300) is located, but also to the surrounding area (PA) outside the display area (DA). This encapsulation layer (500) may include a first inorganic encapsulation layer (510), an organic encapsulation layer (520), and a second inorganic encapsulation layer (530) that are sequentially stacked.

[0066] The first inorganic encapsulation layer (510) is formed on the common electrode (330) and may include silicon oxide, silicon nitride and / or silicon oxynitride, etc. This first inorganic encapsulation layer (510) may be formed along the underlying structure.

[0067] The organic encapsulation layer (520) is positioned on the first inorganic encapsulation layer (510) and has sufficient thickness so that the upper surface of the organic encapsulation layer (520) can be substantially flat. This organic encapsulation layer (520) may comprise one or more materials selected from the group consisting of polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane.

[0068] The second inorganic sealing layer (530) covers the organic sealing layer (520) and may include silicon oxide, silicon nitride and / or silicon oxynitride, etc. The first inorganic sealing layer (510) and the second inorganic sealing layer (530) have a larger surface area than the organic sealing layer (520) and may come into contact with each other on the outside of the organic sealing layer (520). That is, the organic sealing layer (520) can be prevented from being exposed to the outside by the first inorganic sealing layer (510) and the second inorganic sealing layer (530).

[0069] As such, the bag layer (500) includes a first inorganic bag layer (510), an organic bag layer (520), and a second inorganic bag layer (530). Through this multilayer structure, even if a crack occurs within the bag layer (500), the crack can be prevented from connecting between the first inorganic bag layer (510) and the organic bag layer (520), or between the organic bag layer (520) and the second inorganic bag layer (530). This prevents or minimizes the formation of a path for moisture or oxygen from the outside to penetrate into the display area (DA in FIG. 1).

[0070] FIG. 5 is a schematic plan view showing an enlarged view of section A of FIG. 1, FIG. 6 is a schematic plan view showing a strain gauge located in the first fan-out section of FIG. 5, FIG. 7 is a schematic plan view showing a strain gauge located in the second fan-out section of FIG. 5, and FIG. 8 is a schematic cross-sectional view showing an example of the II-II' section of FIG. 6.

[0071] Referring to FIGS. 5 to 8, a first voltage line (40), a second voltage line (50), a fan-out section (20), etc. may be located in the non-display area (NDA) between the display area (DA) and the pad area (PDA) of the substrate (100).

[0072] The first voltage line (40) may be a first power supply voltage (ELVDD) line, and the second voltage line (50) may be a second power supply voltage (ELVSS) line. The first voltage line (40) is connected to a driving voltage supply line (PL in FIG. 4), and the second voltage line (50) may be connected to a common electrode (330 in FIG. 4) directly or via other wiring.

[0073] The first voltage line (40) may include a first main voltage line (42) extending in a first direction (D1) from one side of the display area (DA), for example, outside the fourth edge (E4), and a first connection part (44) protruding in a second direction (D2) from the first main voltage line (42). A plurality of first connection parts (44) may be provided, and each may be connected to a driving circuit part (30) located in the pad area (PDA) across the bending area (BA) and the surrounding area (SA).

[0074] The second voltage line (50) may surround the remaining edges of the display area (DA) (e.g., the first to third edges (E1, E2, E3) of FIG. 1), excluding one edge of the display area (DA) adjacent to the first voltage line (40) (e.g., the fourth edge (E4)). The second voltage line (50) may include a second main voltage line (52) corresponding to both ends of the first main voltage line (42) and the remaining areas of the display area (DA), and a second connecting part (54) extending along the second direction (D2) from the end of the second main voltage line (52). The second connecting part (54) may be connected to the driving circuit part (30).

[0075] The fan-out section (20) includes a plurality of conductive lines (CL), and the plurality of conductive lines (CL) are electrically connected to data lines (DL in FIG. 4) so ​​as to be able to transmit a data signal applied from the driving circuit section (30) to the pixel circuit (PC in FIG. 3).

[0076] For convenience of explanation, the area between the bending area (BA) and the display area (DA) among the non-display areas (NDA) of the substrate (100), as shown in FIG. 5, will be defined as the first non-display area (NDA1). The peripheral area (SA) is an area that is not visible from the front when the bending area (BA) is bent, and may be the area between the bending area (BA) and the driving circuit part (30).

[0077] Multiple conductive lines (CL) may be arranged to sequentially pass through a first non-display area (NDA1), a bending area (BA), and a surrounding area (SA). Meanwhile, the length of the pad area (PDA) may be shorter than one side of the display area (DA) adjacent to the pad area (PDA), and accordingly, the spacing between the conductive lines (CL) may narrow as they move from the display area (DA) to the pad area (PDA). Additionally, since the bending area (BA) is an area where stress is concentrated, the conductive lines (CL) may be extended in a direction parallel to the bending direction within the bending area to minimize damage to the conductive lines (CL) during bending. Therefore, multiple conductive lines (CL) may be bent in the first non-display area (NDA1) and the surrounding area (SA).

[0078] Meanwhile, the fan-out section (20) may be divided into multiple regions spaced apart from each other in at least the surrounding region (SA). For example, as shown in FIG. 5, the fan-out section (20) may include two second fan-out sections (22) respectively positioned on both sides of the first fan-out section (21) with the first fan-out section (21) at the center. However, the present invention is not limited thereto, and the fan-out section (20) may be divided into four or more regions.

[0079] In the bending area (BA), the first connecting part (44) may be located in the separation area (AA) between the first fan-out part (21) and the second fan-out part (22). This is to prevent a short circuit from occurring between the first connecting part (44), the second connecting part (54), and the conductive lines (CL) because they are located on the same layer in the bending area (BA), as described later. Additionally, as the first connecting part (44) is located in the separation area (AA), compared to when the first connecting part (44) is located on the outer edge of the conventional fan-out part (20), the current distribution through the first main voltage line (42) becomes more uniform across the entire display area (DA), and the heat generation phenomenon can be reduced. Meanwhile, FIG. 5 illustrates that the first connecting part (44) is located in the separation area (AA), but the second connecting part (54) may be located in the separation area (AA), or the first connecting part (44) and the second connecting part (54) may be located in the separation area (AA).

[0080] A first strain gauge (SG1) may be located in the first fan-out section (21) of the surrounding area (SA). The first strain gauge (SG1) can detect stress generated in the first direction (D1) of the surrounding area (SA) when an impact is applied to the surrounding area (SA). The first strain gauge (SG1) may be connected to a driving circuit section (30) by the first resistance wire (SGL1) reciprocating multiple times to form a bend. The resistance of the first resistance wire (SGL1) may vary depending on the degree of impact on the surrounding area (SA), and by sensing this change in resistance, the stress received by the surrounding area (SA) is detected, and the driving circuit section (30) can measure the stress applied to the surrounding area (SA).

[0081] The first resistance line (SGL1) is located on the first flattening insulation layer (141) and can be covered by the second flattening insulation layer (142). That is, the first resistance line (SGL1) is formed together with the driving voltage supply line (PL in FIG. 4) and can have the same structure as the driving voltage supply line (PL).

[0082] A second strain gauge (SG2) may be located in the second fan-out section (22) of the surrounding area (SA). The second strain gauge (SG2) can detect stress generated in the second direction (D2) of the surrounding area (SA) when an impact is applied to the surrounding area (SA). The second strain gauge (SG2) may be connected to the driving circuit section (30) by the second resistance wire (SGL2) reciprocating multiple times to form a bend. The resistance of the second resistance wire (SGL2) may vary depending on the degree of impact on the surrounding area (SA), and by sensing this change in resistance, the stress received by the surrounding area (SA) is detected, and the driving circuit section (30) can measure the stress applied to the surrounding area (SA).

[0083] The second resistance line (SGL2) is located on the first flattening insulation layer (141) and can be covered by the second flattening insulation layer (142). That is, the second resistance line (SGL2) is formed together with the driving voltage supply line (PL in FIG. 4) and can have the same structure as the driving voltage supply line (PL).

[0084] FIG. 9 is a schematic plan view showing an enlarged view of section B of FIG. 5, FIG. 10 is a schematic cross-sectional view showing an example of the III-III' section of FIG. 9, FIG. 11 is a schematic cross-sectional view showing an example of the IV-IV' section of FIG. 9, FIG. 12 is a schematic cross-sectional view showing an example of the V-V' section of FIG. 9, and FIG. 13 is a schematic cross-sectional view showing an example of the VI-VI' section of FIG. 9.

[0085] First, referring to FIGS. 9 through 12, the first fan-out section (21) and the second fan-out section (22) may each include a plurality of conductive lines (CL). Meanwhile, as the resolution of the display device (1 in FIG. 1) increases, the number of required conductive lines (CL) increases, and the spacing between the conductive lines (CL) may decrease, and as a result, the risk of a short circuit occurring between the conductive lines (CL) may increase. Accordingly, the above problem can be solved by including the first conductive lines (CL1) and the second conductive lines (CL2) located at different heights. Here, the meaning of different heights is that the distance from the substrate (100) is different.

[0086] As illustrated in FIG. 10, the first conductive lines (CL1) are located on the gate insulating layer (120), and the second conductive lines (CL2) are located on the first interlayer insulating layer (131), and the first conductive lines (CL1) and the second conductive lines (CL2) can be arranged alternately with each other. By doing so, even if the spacing between the first conductive lines (CL1) and the second conductive lines (CL2) is reduced in a planar manner, a short circuit between the first conductive lines (CL1) and the second conductive lines (CL2) can be prevented.

[0087] More specifically, each of the conductive lines (CL) may include a first region (CLa) located in the first non-marked area (NDA1), a second region (CLc) located in the surrounding area (SA), and a connecting conductive layer (CLb) connecting the first region (CLa) and the second region (CLc). The fact that the previously described adjacent first conductive lines (CL1) and second conductive lines (CL2) are at different heights means that the first regions (CLa) of the first conductive lines (CL1) and the second conductive lines (CL2) are located on different layers, and the second regions (CLc) of the first conductive lines (CL1) and the second conductive lines (CL2) are located on different layers. In contrast, the connecting conductive layer (CLb) crossing the bending area (BA) may be located at the same height as the first conductive lines (CL1) and the second conductive lines (CL2).

[0088] For example, FIG. 11 illustrates a first conductive line (CL1) in which a first region (CLa) and a second region (CLc) are located on a gate insulating layer (120) and connected by a connecting conductive layer (CLb), and FIG. 12 illustrates a second conductive line (CL2) in which a first region (CLa) and a second region (CLc) are located on a first interlayer insulating layer (131) and connected by a connecting conductive layer (CLb).

[0089] The connecting conductive layer (CLb) is formed to be longer than the bending region (BA), so that the contact points with the first region (CLa) and the second region (CLc) can be located in the first non-display region (NDA1) and the surrounding region (SA), respectively.

[0090] Additionally, the connecting conductive layer (CLb) may include a first connecting conductive layer (CLb1) and a second connecting conductive layer (CLb2) that are connected in parallel and overlap each other on a plane. Therefore, even if the first connecting conductive layer (CLb1) or the second connecting conductive layer (CLb2) is damaged by stress applied to the bending region (BA), the phenomenon of the electrical connection between the first region (CLa) and the second region (CLc) being interrupted can be prevented.

[0091] The first connecting conductive layer (CLb1) may be located on the second interlayer insulating layer (132), and the second connecting conductive layer (CLb2) may be located on the first flattening insulating layer (141). That is, the first connecting conductive layer (CLb1) may be formed together with the data line (DL) and may have the same structure as the data line (DL in FIG. 4), and the second connecting conductive layer (CLb2) may be formed together with the driving voltage supply line (PL in FIG. 4) and may have the same structure as the driving voltage supply line (PL). The second connecting conductive layer (CLb2) may be located on the same layer as the strain gauges (SG1, SG2 in FIG. 5).

[0092] Meanwhile, the connecting conductive layer (CLb) crosses the bending region (BA), which is an area where a portion of the buffer layer (110), gate insulating layer (120), first interlayer insulating layer (131), and second interlayer insulating layer (132) on the substrate (100) is removed, as shown in FIG. 11. Hereinafter, the buffer layer (110), gate insulating layer (120), first interlayer insulating layer (131), and second interlayer insulating layer (132) are collectively referred to as "inorganic insulating layers." That is, the inorganic insulating layer stacked on the substrate (100) can be understood to include a groove at a position corresponding to the bending region (BA). By removing a portion of the inorganic insulating layer in the bending region (BA), bending in the bending region (BA) is facilitated, and cracks or the like can be prevented from occurring in the inorganic insulating layer during bending.

[0093] An organic layer (400) may be filled in the area where the inorganic insulating layer has been removed. The organic layer (400) may extend from the bending area (BA) to the first non-display area (NDA) and surrounding area (SA) adjacent to the bending area (BA). The organic layer (400) can not only compensate for the step difference of the bending area (BA) where the inorganic insulating layer has been removed, but also absorb the stress generated by bending. Therefore, the concentration of stress generated during bending on the connecting conductive layer (CLb) located on the bending area (BA) to transmit an electrical signal from the driving circuit part (30) located in the pad area (PDA) to the display area (DA) can be effectively minimized.

[0094] Such an organic layer (400) may include at least one material selected from acrylic, methacryl, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylen, polyarylate, and hexamethyldisiloxane.

[0095] Meanwhile, although not shown in the drawing, a pixel defining film (150 in FIG. 4) is positioned on the second flattening insulating layer (142) in the bending region (BA), and a bending protection layer may be further disposed on the pixel defining film (150 in FIG. 4) to ensure that a stress neutral plane is positioned near the wiring in the bending region (BA) during bending.

[0096] Referring to FIG. 9 and FIG. 13, in the bending region (BA), the first connecting portion (44) may be located between the first fan-out portion (21) and the second fan-out portion (22). The width of the first connecting portion (44) may be greater than the width of the conductive lines (CL).

[0097] The first connecting portion (44) may be positioned across the bending region (BA) and on the first flattening insulating layer (141). Meanwhile, the first connecting portion (44) may also be positioned on the first flattening insulating layer (141) in the first non-display region (NDA1) and the surrounding region (SA). Therefore, in the bending region (BA), the first connecting portion (44) must be positioned spaced apart from the second connecting conductive layers (CLb2) because it is located on the same layer as the second connecting conductive layers (CLb2); however, in the first non-display region (NDA1) and the surrounding region (SA), since the first region (CLa) and the second region (CLc) are located on different layers from the first connecting portion (44), the first connecting portion (44) may be positioned overlapping the first region (CLa) and the second region (CLc) in a vertical direction.

[0098] Meanwhile, as previously explained, in order to prevent electrical connection between the first region (CLa) and the second region (CLc) from being severed due to a break in the connecting conductive layers (CLb) caused by stress occurring in the bending region (BA), the connecting conductive layers (CLb) include a first connecting conductive layer (CLb1) and a second connecting conductive layer (CLb2) connected in parallel. In contrast, since the width of the first connecting part (44) is greater than the width of the connecting conductive layers (CLb), the possibility of a break in the first connecting part (44) is lower compared to the connecting conductive layers (CLb). Therefore, the first connecting part (44) can be located only on the first flattened insulating layer (141).

[0099] Meanwhile, according to the present invention, the first connecting portion (44) is located in the spaced-out area (AA) between the first fan-out portion (21) and the second fan-out portion (22). That is, by the first connecting portion (44) being located between the conductive lines (CL), the first connecting portion (44) can be located closer to the center of the surrounding area (SA) compared to the conventional method. As a result, the first strain gauge (SG1) can be located closer to the center of the surrounding area (SA). Therefore, the first strain gauge (SG1) can measure the stress occurring in the center close to the driving circuit portion (30). FIG. 14 is a cross-sectional view schematically illustrating an example of the VII-VII' section of FIG. 9.

[0100] Referring to FIG. 14, in the surrounding area (SA), the first connection part (44) may be located between the first fan-out part (21) and the second fan-out part (22). The width of the first connection part (44) may be greater than the width of the conduction lines (CL).

[0101] The first fan-out section (21) includes a plurality of conductive lines (CL), and the plurality of conductive lines (CL) may include first conductive lines (CL1) and second conductive lines (CL2) located at different heights. Meanwhile, the first strain gauge (SG1) located in the first fan-out section (21) may be disposed on the first flattening insulating layer (141).

[0102] The second fan-out section (22) includes a plurality of conductive lines (CL), and the plurality of conductive lines (CL) may include first conductive lines (CL1) and second conductive lines (CL2) located at different heights. Meanwhile, the second strain gauge (SG2) located in the second fan-out section (22) may be disposed on the first flattening insulating layer (141).

[0103] A first connecting part (44) may be located in the spacing area (AA) between the first fan-out part (21) and the second fan-out part (22). Meanwhile, the first connecting part (44) may be placed on the first flattening insulating layer (141).

[0104] In other words, the first connecting part (44), the first strain gauge (SG1), and the second strain gauge (SG2) can be placed on the same layer. More specifically, the first connecting part (44), the first strain gauge (SG1), and the second strain gauge (SG2) may contain the same material and may be formed simultaneously.

[0105] The first connecting part (44), the first strain gauge (SG1), and the second strain gauge (SG2) may be placed on the same layer as the driving voltage supply line (PL in FIG. 4) and the second connecting metal (CM2 in FIG. 4). Accordingly, the first connecting part (44), the first strain gauge (SG1), the second strain gauge (SG2), the driving voltage supply line (PL in FIG. 4), and the second connecting metal (CM2 in FIG. 4) may contain the same material and may be formed simultaneously. In other words, no additional process may be required to form the first strain gauge (SG1) and the second strain gauge (SG2).

[0106] For example, during the manufacturing process of a display device (1 in FIG. 1), if an impact is applied to a peripheral area (SA), local stress may increase in the peripheral area (SA) due to the impact, which may increase the likelihood of defects such as disconnection of the connecting conductive layers (CLb). However, since such an increase in stress is difficult to detect, it was difficult to identify this increase in stress in advance before an actual defect occurred. However, according to the present invention, the stress applied in the first direction (D1) and the second direction (D2) of the peripheral area (SA) can be identified more accurately by the first strain gauge (SG1) and the second strain gauge (SG2) in the peripheral area (SA). Therefore, by identifying whether the stress applied to the peripheral area (SA) reaches a critical value of the connecting conductive layers (CLb) and thereby identifying in advance whether there is a possibility of damage to the display device (1 in FIG. 1), the reliability of the display device (1 in FIG. 1) can be improved.

[0107] As such, the present invention has been described with reference to an embodiment illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and variations of the embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Industrial applicability

[0108] The present invention may be applied to display devices and electronic devices including the same. For example, the present invention may be applied to high-resolution smartphones, mobile phones, smartpads, smartwatches, tablet PCs, vehicle navigation systems, televisions, computer monitors, laptops, etc.

[0109] Although the present invention has been described above with reference to exemplary embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as set forth in the following claims. Explanation of the symbols

[0110] DA: Display area NDA: Non-display area BA: Bending area PDA: Pad area SA: Surrounding area AA: Separation area SG1, SG2: Strain Gauge 20: Fan-out section 30: Driving circuit section 40: First voltage line 42: 1st main voltage line 44: 1st connection part 50 : Second voltage line CL : Multiple conductive lines

Claims

Claim 1 A display device comprising: a substrate having a display area, a non-display area outside the display area, a pad area located within the non-display area, a bending area between the display area and the pad area, and a peripheral area between the pad area and the bending area; a fan-out portion disposed on the substrate and including a plurality of conductive lines connecting the display area and the pad area; and a strain gauge disposed on the substrate and located in the peripheral area, wherein each of the plurality of conductive lines includes a first area located between the display area and the bending area, a second area located in the peripheral area, and a connecting conductive layer electrically connecting the first area and the second area and crossing the bending area, wherein the connecting conductive layer includes a first connecting conductive layer and a second connecting conductive layer connected in parallel and overlapping each other in a plane. Claim 2 A display device according to claim 1, further comprising a main voltage line disposed on the substrate and located between the display area and the bending area, and a voltage line including a connecting portion that protrudes from the main voltage line and extends toward the pad area and crosses the bending area. Claim 3 A display device according to claim 2, characterized in that the connecting portion is disposed on the same layer as the strain gauge. Claim 4 A display device according to claim 2, wherein the fan-out portion comprises a first fan-out portion and a second fan-out portion spaced apart from each other in at least the surrounding area, the first fan-out portion is located in the center of the surrounding area, the second fan-out portion is located on the side of the surrounding area, and the connecting portion is located in the spaced-out area between the first fan-out portion and the second fan-out portion in the bending area. Claim 5 A display device according to claim 4, characterized in that the strain gauge is located in the first fan-out portion. Claim 6 A display device according to claim 5, characterized in that the strain gauge extends in a direction parallel to the connection part. Claim 7 A display device according to claim 4, characterized in that the strain gauge is located in the second fan-out portion. Claim 8 A display device according to claim 7, characterized in that the strain gauge extends in a direction parallel to the main voltage line. Claim 9 delete Claim 10 A display device according to claim 1, characterized in that the first region and the second region are disposed on the same layer, and the connecting conductive layer is disposed on a different layer from the first region. Claim 11 A display device according to claim 10, wherein the second connecting conductive layer is disposed on the first connecting conductive layer, and the second connecting conductive layer is disposed on the same layer as the strain gauge. Claim 12 A display device according to claim 1, wherein the display area comprises a plurality of pixel circuits, a plurality of light-emitting elements electrically connected to each of the plurality of pixel circuits, and a plurality of data lines electrically connected to the plurality of pixel circuits, wherein the plurality of conductive lines are electrically connected to the plurality of data lines to transmit an electrical signal from a driving circuit unit located in the pad area to the plurality of data lines, and wherein the first connecting conductive layer is disposed on the same layer as the plurality of data lines. Claim 13 A display device according to claim 12, wherein driving voltage supply lines providing driving signals to the plurality of pixel circuits are further located in the display area, and the strain gauge is disposed on the same layer as the driving voltage supply lines. Claim 14 A display device according to claim 13, characterized in that the strain gauge and the driving voltage supply lines comprise the same material. Claim 15 A display device according to claim 1, wherein the strain gauge includes a resistance wire that reciprocates multiple times to form a bend, and the resistance wire is electrically connected to a driving circuit located in the pad area. Claim 16 A display device according to claim 1, characterized in that the strain gauge detects stress generated when an impact is applied to the surrounding area. Claim 17 A display device comprising: a substrate having a display area, a non-display area outside the display area, a pad area located within the non-display area, a bending area between the display area and the pad area, and a peripheral area between the pad area and the bending area; a fan-out portion disposed on the substrate and including a first fan-out portion located in the center of the peripheral area, a second fan-out portion located on the side of the peripheral area, and a plurality of conductive lines connecting the display area and the pad area; and a strain gauge including a first strain gauge located in the first fan-out portion and a second strain gauge located in the second fan-out portion, wherein each of the plurality of conductive lines includes a first area located between the display area and the bending area, a second area located in the peripheral area, and a connecting conductive layer electrically connecting the first area and the second area and crossing the bending area, wherein the connecting conductive layer includes a first connecting conductive layer and a second connecting conductive layer connected in parallel and overlapping each other on a plane. Claim 18 A display device according to claim 17, characterized in that the first strain gauge and the second strain gauge are disposed on the same layer. Claim 19 A display device according to claim 17, characterized in that the first strain gauge extends from the peripheral region toward the bending region, and the second strain gauge extends in a direction perpendicular to the first strain gauge.

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