Tiled display device and sub-display panel employed therein

Abstract

A tiled display device with improved staining at the junction and a sub-display panel employed therein are disclosed. The tiled display device comprises: a first sub-display panel having a plurality of unit pixels formed therein; and a second sub-display panel disposed adjacent to the first sub-display panel and having a plurality of unit pixels formed therein, wherein each of the unit pixels comprises a plurality of sub-pixels having a display element that emits color light and a pixel circuit that drives the display element, and wherein the arrangement order of sub-pixels within the unit pixels corresponding to the current row and the arrangement order of sub-pixels within the unit pixels corresponding to the previous row or the next row are different from each other. Accordingly, by configuring the arrangement order of sub-pixels within the unit pixels corresponding to the current row and the arrangement order of sub-pixels within the unit pixels corresponding to the previous row or the next row differently from each other, the visibility of staining caused by the sub-pixel arrangement near the junction area can be improved.

Description

Technology Field

[0001] The present invention relates to a tiled display device and a sub-display panel employed therein, and more specifically, to a tiled display device with improved staining at the joint and a sub-display panel employed therein. Background Technology

[0002] Generally, multiple display panels are connected and arranged to create extra-large TVs. This is called a tiled display device. The display panels can be connected in a matrix form or in a stripe form.

[0003] Typically, when connecting display panels, the display panel placed at the bottom is attached with the top display panel flipped 180 degrees relative to it. When striped pixels are formed on the display panels, the pixel positions are reversed at the joint. For example, the pixels of the upper display panel are arranged in the order of red sub-pixel, green sub-pixel, and blue sub-pixel, whereas the pixels of the lower display panel are arranged in the order of blue sub-pixel, green sub-pixel, and red sub-pixel. Consequently, there is a problem in which stains are visible in the joint area due to pixel asymmetry.

[0004] Therefore, it is necessary to change the pixel arrangement so that asymmetry does not occur at the joint even if the lower display panel is attached by flipping it 180 degrees.

[0005] In other words, if red, green, and blue are arranged in the order of 2n rows and blue, green, and red are arranged in the order of 2n+1 rows, there is a problem in that monochromatic and mixed color stains are visible. That is, the red sub-pixels and blue sub-pixels are staggered, but since the green sub-pixels are placed in the center, there is a problem in that stains are visible due to the green sub-pixels arranged in the vertical direction. Prior art literature

[0006] 0001) Korean Registered Patent No. 10-1157425 (June 12, 2012) 0002) Korean Registered Patent No. 10-1015275 (February 9, 2011) 0003) Korean Published Patent No. 2019-0072196 (June 25, 2019) The problem to be solved

[0007] Accordingly, the technical problem of the present invention is based on this point, and the objective of the present invention is to provide a tiled display device with improved staining at the joint where a plurality of display panels are attached.

[0008] Another objective of the present invention is to provide a sub-display panel employed in the tiled display device described above. means of solving the problem

[0009] To realize the purpose of the present invention as described above, a tiled display device according to one embodiment comprises: a first sub-display panel having a plurality of unit pixels formed therein; and a second sub-display panel arranged adjacent to the first sub-display panel and having a plurality of unit pixels formed therein, wherein each of the unit pixels includes a plurality of sub-pixels having a display element that emits color light and a pixel circuit that drives the display element, and wherein the arrangement order of sub-pixels within the unit pixels corresponding to the current row and the arrangement order of sub-pixels within the unit pixels corresponding to the previous row or the next row are different from each other.

[0010] In one embodiment, the display elements arranged in a column direction can emit different colored light.

[0011] In one embodiment, a sub-pixel corresponding to the n-th row and m-th column (where n and m are natural numbers) emits a first color light, and a sub-pixel corresponding to the n+1-th row and m-th column emits a second color light.

[0012] In one embodiment, the arrangement order of sub-pixels within a unit pixel corresponding to the 2n-th row (where n is a natural number) is C3-C1-C2 (where C1 is a first sub-pixel emitting a first color light, C2 is a second sub-pixel emitting a second color light, and C3 is a third sub-pixel emitting a third color light), and the arrangement order of sub-pixels within a unit pixel corresponding to the 2n-1th row may be C1-C2-C3.

[0013] In one embodiment, the arrangement order of sub-pixels within a unit pixel corresponding to the 3n-th row (where n is a natural number) is C2-C3-C1 (where C1 is a first sub-pixel emitting a first color light, C2 is a second sub-pixel emitting a second color light, and C3 is a third sub-pixel emitting a third color light), the arrangement order of sub-pixels within a unit pixel corresponding to the 3n-1th row is C3-C1-C2, and the arrangement order of sub-pixels within a unit pixel corresponding to the 3n-2th row is C1-C2-C3.

[0014] In one embodiment, the arrangement order of sub-pixels within a unit pixel corresponding to the 4n-th row (where n is a natural number) is C3-C1-C2 (where C1 is a first sub-pixel emitting a first color light, C2 is a second sub-pixel emitting a second color light, and C3 is a third sub-pixel emitting a third color light), the arrangement order of sub-pixels within a unit pixel corresponding to the 4n-1th row is C2-C3-C1, the arrangement order of sub-pixels within a unit pixel corresponding to the 4n-2nd row is C3-C1-C2, and the arrangement order of sub-pixels within a unit pixel corresponding to the 4n-3rd row is C1-C2-C3.

[0015] In one embodiment, the first sub-pixel emits red color light, the second sub-pixel emits green color light, and the third sub-pixel emits green color light.

[0016] In one embodiment, each of the unit pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, wherein the first sub-pixel is a red sub-pixel that emits red color light, the second sub-pixel is a green sub-pixel that emits green light, and the third sub-pixel is a blue sub-pixel that emits blue light.

[0017] In one embodiment, the number of sub-display panels may be four or more.

[0018] In one embodiment, the sub-pixel further comprises a current scan line, a first data line transmitting a data signal corresponding to a first color light, a second data line transmitting a data signal corresponding to a second color light, and a third data line transmitting a data signal corresponding to a third color light, and the pixel circuit comprises a first transistor connected to the display element; and a second transistor connected to the current scan line, and the source electrode of the second transistor may be connected to any one of the first data line, the second data line, and the third data line.

[0019] In one embodiment, the display element may be either an organic light-emitting diode or a nanodiode.

[0020] According to one embodiment, in order to realize another objective of the present invention described above, a plurality of sub-display panels for a tiled display device are attached to form a tiled display device. The sub-display panel for a tiled display device comprises: a first unit pixel comprising a plurality of sub-pixels arranged on a plane; and a second unit pixel disposed adjacent to the first unit pixel in a column direction and comprising a plurality of sub-pixels arranged on a plane, wherein each of the unit pixels comprises a plurality of sub-pixels having a display element that emits color light and a pixel circuit that drives the display element, and the arrangement order of sub-pixels within the unit pixels corresponding to the current row and the arrangement order of sub-pixels within the unit pixels corresponding to the previous row or the next row are different from each other.

[0021] In one embodiment, each of the first unit pixel and the second unit pixel includes a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light, and the arrangement order of the first to third sub-pixels provided in the first unit pixel and the arrangement order of the first to third sub-pixels provided in the second unit pixel may be different from each other.

[0022] In one embodiment, the arrangement order of sub-pixels within the first unit pixel is C3-C1-C2 (wherein C1 is a first sub-pixel emitting a first color light, C2 is a second sub-pixel emitting a second color light, and C3 is a third sub-pixel emitting a third color light), and the arrangement order of sub-pixels within the second unit pixel may be C1-C2-C3.

[0023] In one embodiment, the sub-display panel for the tiled display device further comprises a third unit pixel including a plurality of sub-pixels arranged in a row direction in a third order on a plane, which is arranged adjacently to the second unit pixel in a column direction, and the arrangement order of the sub-pixels within the first unit pixel is C2-C3-C1 (wherein C1 is a first sub-pixel emitting a first color light, C2 is a second sub-pixel emitting a second color light, and C3 is a third sub-pixel emitting a third color light), the arrangement order of the sub-pixels within the second unit pixel is C3-C1-C2, and the arrangement order of the sub-pixels within the third unit pixel may be C1-C2-C3.

[0024] In one embodiment, the sub-display panel for the tiled display device comprises a third unit pixel comprising a plurality of sub-pixels arranged in a third row order on a plane and positioned adjacent to the second unit pixel in a column direction; and further include a fourth unit pixel comprising a plurality of sub-pixels arranged in a row direction in a fourth order on a plane, arranged adjacently to the third unit pixel in a column direction, wherein the arrangement order of sub-pixels within the first unit pixel is C3-C1-C2 (wherein C1 is a first sub-pixel emitting a first color light, C2 is a second sub-pixel emitting a second color light, and C3 is a third sub-pixel emitting a third color light), the arrangement order of sub-pixels within the second unit pixel is C2-C3-C1, the arrangement order of sub-pixels within the third unit pixel is C3-C1-C2, and the arrangement order of sub-pixels within the fourth unit pixel is C1-C2-C3. Effects of the invention

[0025] According to this tiled display device and the sub-panel employed therein, by configuring the arrangement order of sub-pixels within unit pixels corresponding to the current row and the arrangement order of sub-pixels within unit pixels corresponding to the previous row or the next row differently from each other, the visibility of stains caused by the arrangement of sub-pixels near the junction area where multiple display panels are attached can be improved. Brief explanation of the drawing

[0026] FIG. 1 is a plan view schematically illustrating a tiled display device according to an embodiment of the present invention. FIG. 2 is a plan view for illustrating an example of a color arrangement corresponding to the joint area of ​​the tiled display device shown in FIG. 1. Figure 3 is a plan view illustrating an example of a color arrangement according to a comparative example. Figure 4 is an equivalent circuit diagram for explaining the sub-pixel shown in Figure 2. FIG. 5 is a plan view illustrating two unit pixels shown in FIG. 2. In particular, two adjacent unit pixels on the same column are shown. Figure 6 is an equivalent circuit diagram to explain the connection relationship of two unit pixels shown in Figure 5. FIGS. 7a to 7s are plan views for explaining a method of manufacturing a pixel illustrated in FIG. 4. FIG. 8 is a diagram illustrating the connection between sub-pixels and data lines corresponding to the color arrangement shown in FIG. 2. FIG. 9 is a plan view illustrating another example of a color arrangement corresponding to the joint area of ​​the tiled display device shown in FIG. 1. FIG. 10 is a diagram illustrating the connection between sub-pixels and data lines corresponding to the color arrangement shown in FIG. 9. FIG. 11 is a plan view illustrating another example of a color arrangement corresponding to the joint area of ​​the tiled display device shown in FIG. 1. FIG. 12 is a diagram illustrating the connection between sub-pixels and data lines corresponding to the color arrangement shown in FIG. 11. Specific details for implementing the invention

[0027] Hereinafter, the present invention will be described in more detail with reference to the attached drawings.

[0028] FIG. 1 is a plan view schematically illustrating a tiled display device according to an embodiment of the present invention.

[0029] Referring to FIG. 1, a tiled display device according to one embodiment of the present invention includes a first sub-display panel (110), a second sub-display panel (120), a third sub-display panel (130), and a fourth sub-display panel (140) in which a plurality of pixels are formed to define an image display section.

[0030] The first sub-display panel (110) is positioned in the first quadrant from the observer's perspective, and the second sub-display panel (120) is positioned in the second quadrant from the observer's perspective. The third sub-display panel (130) is positioned in the third quadrant from the observer's perspective, and the fourth sub-display panel (140) is positioned in the fourth quadrant from the observer's perspective.

[0031] The second sub-display panel (120) is attached with the first sub-display panel (110) flipped 180 degrees. The fourth sub-display panel (140) is attached with the third sub-display panel (130) flipped 180 degrees.

[0032] Each of the first to fourth sub-display panels (110, 120, 130, 140) includes a plurality of unit pixels corresponding to a plurality of lines. Each of the unit pixels may include a plurality of sub-pixels. The sub-pixels may include a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light. For example, the sub-pixels may include a red sub-pixel emitting red light, a green sub-pixel emitting green light, and a blue sub-pixel emitting blue light.

[0033] In each of the sub-display panels (110, 120, 130, 140), the arrangement order of sub-pixels within unit pixels corresponding to the current row and the arrangement order of sub-pixels within unit pixels corresponding to the previous row or the next row are arranged differently.

[0034] In other words, when observing sub-pixels within a unit pixel, the sub-pixels are arranged so that the current sub-pixel and the sub-pixel immediately below it emit different colored light.

[0035] Accordingly, the sub-pixel corresponding to the n-th row and m-th column (where n and m are natural numbers) emits a first color light, and the sub-pixel corresponding to the n+1-th row and m-th column emits a second color light.

[0036] FIG. 2 is a plan view illustrating an example of a color arrangement corresponding to a joint area of ​​a tiled display device illustrated in FIG. 1, and FIG. 3 is a plan view illustrating an example of a color arrangement according to a comparative example. In particular, FIG. 2 and FIG. 3 illustrate a joint area of ​​a tiled display device. Here, the joint area is defined as the area between adjacent sub-display panels.

[0037] Referring to FIG. 2, each of the unit pixels corresponding to the odd-numbered rows may include a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light. For example, each of the unit pixels may have sub-pixels arranged in the order of a red sub-pixel (R) emitting red light, a green sub-pixel (G) emitting green light, and a blue sub-pixel (B) emitting blue light, and each of the unit pixels corresponding to the even-numbered rows may have sub-pixels arranged in the order of a blue sub-pixel (B), a red sub-pixel (R), and a green sub-pixel (G).

[0038] In this way, sub-pixels within unit pixels corresponding to adjacent lines are arranged in an alternating pattern. In other words, within the unit pixels corresponding to the first row, sub-pixels are arranged in the order of RGB, and within the unit pixels corresponding to the second row, sub-pixels are arranged in the order of BRG.

[0039] Therefore, even if the second sub-display panel (120) is attached to the first sub-display panel (110) by inverting it 180 degrees relative to the first sub-display panel (110), stain visibility caused by pixel asymmetry in the joint can be prevented.

[0040] In addition, even if the first sub-display panel (110) and the second sub-display panel (120) are misaligned, stain visibility caused by pixel asymmetry at the joint can be prevented.

[0041] In contrast, referring to FIG. 3, for each unit pixel corresponding to every line, sub-pixels are arranged in the order of red sub-pixel (R), green sub-pixel (G), and blue sub-pixel (B).

[0042] Therefore, when the second sub-display panel (120) is attached to the first sub-display panel (110) by inverting it 180 degrees relative to the first sub-display panel (110), stains caused by pixel asymmetry at the joint can be seen.

[0043] Additionally, if the first sub-display panel (110) and the second sub-display panel (120) are misaligned, the stain may be more clearly visible due to pixel asymmetry at the joint.

[0044] Figure 4 is an equivalent circuit diagram for explaining the sub-pixel shown in Figure 2.

[0045] Referring to FIG. 4, a sub-pixel (PX) provided in a unit pixel includes a plurality of transistors (T1, T2, T3), a capacitor (Cst), and a diode (LED) connected to various signal lines. In this embodiment, the diode (LED) may be an organic light-emitting diode (OLED) or a nano diode.

[0046] The display device according to the embodiment of FIG. 1 illustrates a display device used in high resolution (4K or 8K), and the sub-pixel (PX) is controlled by a current scan line (211) that receives the same signal as the data line (215). In this embodiment, the data line (215) may be any one of a red data line connected to a red sub-pixel emitting red light, a green data line connected to a green sub-pixel emitting green light, and a blue data line connected to a blue sub-pixel emitting blue light.

[0047] A plurality of transistors (T1, T2, T3) included in a single sub-pixel (PX) include a driving transistor (T1) (or a first transistor (T1)), a switching transistor (T2) (or a second transistor (T2)) connected to the current scan line (211), and an initialization transistor (T3) (or a third transistor (T3)) (or a sensing transistor) connected to the previous scan line (213). The third transistor (T3) may be connected to a signal wiring that applies a gate-on voltage at a timing different from that of the previous scan line (213).

[0048] A plurality of signal lines included in one sub-pixel (PX) may include a current scan line (211), a previous scan line (213), a data line (215), an initial voltage line (217) (or a detection line), a driving high voltage line (219), and a driving low voltage line (221).

[0049] The current scan line (211) is connected to a gate driver (not shown) to transmit a scan signal (Sn) to the second transistor (T2).

[0050] The above-mentioned previous scan line (213) is connected to the gate driver and transmits a scan signal (Sn-1) applied to a sub-pixel (PX) located at the front end to the third transistor (T3).

[0051] The above data line (215) is a wiring that transmits a data voltage (Dm) generated by a data driver (not shown). The brightness of the diode emits changes according to the data voltage (Dm) provided to the sub-pixel (PX) along the above data line (215).

[0052] The driving high voltage line (219) applies a driving high voltage (VDD), and the driving low voltage line (221) applies a driving low voltage (VSS). According to the present embodiment, the driving high voltage line (219) and the driving low voltage line (221) may be formed into a mesh structure including wiring extending in the horizontal direction and wiring extending in the vertical direction. A constant voltage may be applied to each of the driving high voltage line (219) and the driving low voltage line (221). The driving high voltage (VDD) serves as an input voltage that generates an output current in the driving transistor (T1), and when the output current is applied to the diode (LED), the driving low voltage (VSS) is applied to the other electrode (hereinafter also referred to as the cathode).

[0053] FIG. 5 is a plan view illustrating two unit pixels illustrated in FIG. 2. FIG. 6 is an equivalent circuit diagram illustrating the connection relationship of two unit pixels illustrated in FIG. 5. In particular, two adjacent unit pixels on the same column are illustrated.

[0054] Referring to FIGS. 5 and 6, the display device may include a substrate (SUB), a wiring section, and unit pixels. Each of the unit pixels may include a plurality of sub-pixels. Each of the sub-pixels may include a pixel circuit and a display element (OLED). Here, the sub-pixels may include a red sub-pixel emitting red light, a green sub-pixel emitting green light, and a blue sub-pixel emitting blue light. The pixel circuit may include a first transistor (T1) to a third transistor (T3) and a storage capacitor (Cst). The display element (OLED) may be either an organic light-emitting diode or a nanodiode.

[0055] Each of the sub-pixels provided in a unit pixel may include a pixel circuit and a display element (OLED). Here, the sub-pixels may include a red sub-pixel emitting red light, a green sub-pixel emitting green light, and a blue sub-pixel emitting blue light. The pixel circuit may include a first transistor (T1) to a third transistor (T3) and a storage capacitor (Cst).

[0056] The substrate (SUB) includes a transparent insulating material that allows light to pass through. The substrate (SUB) may be a rigid substrate. For example, the substrate (SUB) may be one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystalline glass substrate.

[0057] Additionally, the substrate (SUB) may be a flexible substrate. Here, the substrate (SUB) may be one of a film substrate containing a polymer organic material and a plastic substrate. However, the material constituting the substrate (SUB) may vary and may include fiber reinforced plastic (FRP), etc.

[0058] The above wiring section provides signals to each of the pixels and may include scan lines (Sn-1, Sn), data lines (R, G, B), horizontal power lines (Pn-1, Pn), power lines (PL), and initialization power lines (IPL).

[0059] The above scan lines (Sn-1, Sn) may be extended in the horizontal direction. The above scan lines (Sn-1, Sn) may include the n-1th scan line (Sn-1) and the nth scan line (Sn) arranged sequentially along the vertical direction. The above scan lines (Sn-1, Sn) may receive a scan signal. For example, the n-1th scan line (Sn-1) may receive the n-1th scan signal, and the nth scan line (Sn) may receive the nth scan signal. The pixels of the nth row of the n-1th scan line (Sn-1) may be initialized by the n-1th scan signal.

[0060] The above horizontal power lines (Pn-1, Pn) can be extended in the horizontal direction. The above horizontal power lines (Pn-1, Pn) can be connected to power lines (PL) arranged in the vertical direction to form a mesh-type power supply line.

[0061] The above data lines (R, G, B) are extended in the vertical direction and can be arranged sequentially along the horizontal direction. The above data lines (R, G, B) can receive data signals.

[0062] The above driving high voltage line (VDW) may be extended along the vertical direction. The above driving high voltage line (VDW) may be spaced apart from the data lines (R, G, B). The above driving high voltage line (VDW) may receive a driving high voltage (VDD).

[0063] The above driving low voltage line (VSW1) may be extended along the vertical direction. The above driving low voltage line (VSW1) may be spaced apart from the data lines (R, G, B). The above driving low voltage line (VSW1) may receive a driving low voltage (VSS).

[0064] The initialization power line (SLW) may be extended along the vertical direction. The initialization power line (SLW) may receive an initialization power (Vint).

[0065] FIGS. 7a to 7s are plan views for explaining a method of manufacturing a unit pixel shown in FIG. 5.

[0066] Referring to FIG. 7a, a first conductive film (not shown) is formed on a substrate. The substrate is made of a transparent glass material and typically contains alkaline earth ions. A buffer layer having one of SiNx and SiO2 as a main component may be further formed on the upper surface of the substrate. The first conductive film may be made of a highly conductive metallic material used as an electrode material, and may include an alloy containing materials such as Al, Ti, Mo, Ag, Cr, Mo, Cu, etc., and may have a single layer or a multilayer structure of said material.

[0067] The first conductive film is patterned to have a conductive pattern by a photo process using a first photomask (not shown). A general photolithography process can be applied for the photo process. That is, a first photoresist film (not shown) is formed on the first conductive film, and after exposure through a first photomask (not shown), the first conductive film is patterned into a conductive pattern through a development and etching process, and the first photoresist film remaining on the first conductive film is removed.

[0068] The above conductive pattern is a conductive pattern comprising various signal lines including a first driving low voltage wire (VSW1), an initialization wire (SLW), a driving high voltage wire (VDW), a first storage electrode (SE1), a second storage electrode (SE2), a third storage electrode (SE3), a first data wire (DW1), a second data wire (DW2), a third data wire (DW3), and a second driving low voltage wire (VSW2). The first driving low voltage wire (VSW1) provides a driving low voltage to one side of a unit pixel, and the second driving low voltage wire (VSW2) provides a driving low voltage to the other side of a unit pixel. The first data wire (DW1) can transmit red data to a first sub-pixel, for example, the second data wire (DW2) can transmit green data to a second sub-pixel, for example, and the third data wire (DW3) can transmit blue data to a third sub-pixel.

[0069] Referring to FIGS. 7b and 7c, a first insulating film (not shown) is formed to cover the aforementioned conductive pattern on a substrate, and then an active layer is formed. The active layer may include any one of amorphous silicon, polycrystalline silicon, and oxide semiconductor.

[0070] In this embodiment, the active layer includes a first active pattern (AP11), a second active pattern (AP12), a third active pattern (AP13), a fourth active pattern (AP21), a fifth active pattern (AP22), a sixth active pattern (AP23), a seventh active pattern (AP31), an eighth active pattern (AP32), and a ninth active pattern (AP33).

[0071] A first active pattern (AP11) forms a channel layer of a first thin-film transistor provided in a first sub-pixel, a second active pattern (AP12) forms a channel layer of a second thin-film transistor provided in a first sub-pixel, and a third active pattern (AP13) forms a channel layer of a third thin-film transistor provided in a first sub-pixel. A fourth active pattern (AP21) forms a channel layer of a first thin-film transistor provided in a second sub-pixel, a fifth active pattern (AP22) forms a channel layer of a second thin-film transistor provided in a second sub-pixel, and a sixth active pattern (AP23) forms a channel layer of a third thin-film transistor provided in a second sub-pixel. The seventh active pattern (AP31) forms the channel layer of the first thin-film transistor provided in the third sub-pixel, the eighth active pattern (AP32) forms the channel layer of the second thin-film transistor provided in the third sub-pixel, and the ninth active pattern (AP33) forms the channel layer of the third thin-film transistor provided in the third sub-pixel.

[0072] Referring to FIGS. 7d ​​and 7e, a semiconductor layer (ACT) and a first gate insulating film (GI) are formed on the result shown in FIG. 7c, and then a second conductive film is applied. Here, the first gate insulating film (GI) may include an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon nitrate (SiOxNy). The first gate insulating film (GI) may have a single layer or a multilayer structure of the above-mentioned material. The second conductive film may use a highly conductive metallic material used as an electrode material, and may include an alloy containing materials such as Al, Ti, Mo, Ag, Cr, Mo, Cu, etc., and may have a single layer or a multilayer structure of the said material. By patterning the second conductive film, a first power connection pattern (PCP1), a second power connection pattern (PCP2), a first gate electrode pattern (GEP1), a second gate electrode pattern (GEP2), a third gate electrode pattern (GEP3), a fourth gate electrode pattern (GEP4), and a fifth gate electrode pattern (GEP5) are formed.

[0073] The first power connection pattern (PCP1) and the second power connection pattern (PCP2) extend in a vertical direction and are arranged to surround the first gate electrode pattern (GEP1), the second gate electrode pattern (GEP2), the third gate electrode pattern (GEP3), and the fourth gate electrode pattern (GEP4).

[0074] The first gate electrode pattern (GEP1) forms the gate electrode of the first thin-film transistor of the first sub-pixel. The second gate electrode pattern (GEP2) forms the gate electrode of the first thin-film transistor of the second sub-pixel. The third gate electrode pattern (GEP3) forms the gate electrode of the first thin-film transistor of the third sub-pixel. The fourth gate electrode pattern (GEP4) forms the gate electrode of the third thin-film transistor of the first sub-pixel, the gate electrode of the third thin-film transistor of the second sub-pixel, and the gate electrode of the third thin-film transistor of the third sub-pixel.

[0075] When viewed in a planar view, the fifth gate electrode pattern (GEP5) is formed in an inverted L-shape. When viewed in a planar view, the vertical extension of the fifth gate electrode pattern (GEP5) is positioned between the second power connection pattern (PCP2) and the first to third gate electrode patterns (GEP3), and the horizontal extension of the fifth gate electrode pattern (GEP5) is positioned below the third gate electrode pattern (GEP3).

[0076] The fifth gate electrode pattern (GEP5) forms the gate electrode of the second thin-film transistor of the first sub-pixel, the gate electrode of the second thin-film transistor of the second sub-pixel, and the gate electrode of the second thin-film transistor of the third sub-pixel.

[0077] Referring to FIG. 7f, a second insulating film is formed on the second conductive film to cover a first power connection pattern (PCP1), a second power connection pattern (PCP2), a first gate electrode pattern (GEP1), a second gate electrode pattern (GEP2), a third gate electrode pattern (GEP3), a fourth gate electrode pattern (GEP4), and a fifth gate electrode pattern (GEP5).

[0078] Next, the second insulating film is patterned using a photolithography process and an etching process to form a plurality of contact holes.

[0079] Specifically, a first contact hole (CT1) and a second contact hole (CT2) that expose a portion of the first driving low voltage wiring (VSW1), a third contact hole (CT3), a fourth contact hole (CT4), and a fifth contact hole (CT5) that expose a portion of the initialization wiring (SLW) are formed.

[0080] In addition, a sixth contact hole (CT6) and a seventh contact hole (CT7) that expose a portion of the driving high-voltage wiring (VDW), an eighth contact hole (CT8) that exposes a portion of the first storage electrode (SE1), and a ninth contact hole (CT9) that exposes a portion of the second storage electrode (SE2) are formed.

[0081] In addition, a 10th contact hole (CT10) exposing a portion of the third storage electrode (SE3), a 11th contact hole (CT11) exposing a portion of the first data wiring (DW1), and a 12th contact hole (CT12) exposing a portion of the second data wiring (DW2) are formed.

[0082] In addition, a 13th contact hole (CT13) exposing a portion of the 3rd data wiring (DW3), and a 14th contact hole (CT14) and a 15th contact hole (CT15) exposing a portion of the 2nd driving low voltage wiring (VSW2) are formed.

[0083] In addition, a 16th contact hole (CT16), a 17th contact hole (CT17), and an 18th contact hole (CT18) that expose a portion of the 1st active pattern (AP11), a 19th contact hole (CT19) and a 20th contact hole (CT20) that expose a portion of the 2nd active pattern (AP12), and a 21st contact hole (CT21) and a 22nd contact hole (CT22) that expose a portion of the 3rd active pattern (AP13) are formed.

[0084] In addition, a 23rd contact hole (CT23) and a 24th contact hole (CT24) exposing a portion of the 4th active pattern (AP21), a 25th contact hole (CT25) and a 26th contact hole (CT26) exposing a portion of the 5th active pattern (AP22), and a 27th contact hole (CT27) and a 27th contact hole (CT28) exposing a portion of the 6th active pattern (AP23) are formed.

[0085] In addition, a 29th contact hole (CT29) and a 30th contact hole (CT30) exposing a portion of the 7th active pattern (AP31), a 31st contact hole (CT31) and a 32nd contact hole (CT32) exposing a portion of the 8th active pattern (AP32), and a 33rd contact hole (CT33) and a 34th contact hole (CT34) exposing a portion of the 9th active pattern (AP33) are formed.

[0086] In addition, a 35th contact hole (CT35) and a 36th contact hole (CT36) exposing a portion of the first power connection pattern (PCP1), a 37th contact hole (CT37) and a 38th contact hole (CT38) exposing a portion of the second power connection pattern (PCP2), and a 39th contact hole (CT39) and a 40th contact hole (CT40) exposing a portion of the fifth gate electrode pattern (GEP5) are formed.

[0087] In addition, a 41st contact hole (CT41) exposing a portion of the 1st gate electrode pattern (GEP1) and a 42nd contact hole (CT42) exposing a portion of the 2nd gate electrode pattern (GEP2) are formed.

[0088] In addition, a 43rd contact hole (CT43) exposing a portion of the 3rd gate electrode pattern (GEP3) and a 44th contact hole (CT44) exposing a portion of the 4th gate electrode pattern (GEP4) are formed.

[0089] Referring to FIG. 7g and FIG. 7h, a third conductive film is applied on the second insulating film, and then a conductive pattern is formed by patterning the third conductive film. Here, the third conductive film may be a highly conductive metallic material used as an electrode material, and may include an alloy containing materials such as Al, Ti, Mo, Ag, Cr, Mo, Cu, etc., and may have a single layer or a multilayer structure of said material. The conductive pattern may be formed by a general photolithography process and an etching process.

[0090] That is, after applying a third conductive film on the second insulating film, a fifth resist film (not shown) is applied on the third conductive film. The fifth resist film is exposed and developed using a fourth photomask (not shown) to expose a certain area of ​​the third conductive film, and after etching the exposed third conductive film, the remaining fifth resist film is removed to obtain a third conductive film with a conductive pattern.

[0091] The above conductive pattern includes a first low-voltage connection pattern (LVP1), a second low-voltage connection pattern (LVP2), an initialization connection pattern (INTP), a high-voltage connection pattern (HVP), a scan line pattern (SLP), a horizontal power line pattern (PWH), a first connection electrode (SD1), a second connection electrode (SD2), a third connection electrode (SD3), a fourth connection electrode (SD4), a fifth connection electrode (SD5), a sixth connection electrode (SD6), a seventh connection electrode (SD7), an eighth connection electrode (SD8), a ninth connection electrode (SD9), a first data connection pattern (DCP1), a second data connection pattern (DCP2), and a third data connection pattern (DCP3).

[0092] The first low-voltage connection pattern (LVP1), the second low-voltage connection pattern (LVP2), the initialization connection pattern (INTP), and the high-voltage connection pattern (HVP) are extended in the vertical direction.

[0093] The scan line pattern (SLP) and the horizontal power line pattern (PWH) extend in a horizontal direction. The horizontal power line pattern (PWH) may be arranged to connect a first driving low voltage wiring (VSW1) and a second driving low voltage wiring (VSW2) arranged in a vertical direction. Accordingly, the lines supplying low voltage are formed in a mesh type to provide low voltage (VSS) to a display device.

[0094] Meanwhile, the horizontal power line pattern (PWH) can be arranged to connect the driving high-voltage wiring (VDW) arranged in a vertical direction. Accordingly, the lines supplying high voltage can be formed in a mesh type to provide high voltage (VDD) to the display device.

[0095] The first connecting electrode (SD1) is formed to connect the second active pattern (AP12) and the first gate electrode pattern (GEP1) through the 19th contact hole (CT19) and the 41st contact hole (CT41).

[0096] The second connecting electrode (SD2) is formed to connect the fifth active pattern (AP22) and the second gate electrode pattern (GEP2) through the 25th contact hole (CT25) and the 42nd contact hole (CT42).

[0097] The third connecting electrode (SD3) is formed to connect the eighth active pattern (AP32) and the third gate electrode pattern (GEP3) through the 31st contact hole (CT31) and the 43rd contact hole (CT43).

[0098] The fourth connecting electrode (SD4) is formed to be connected to the third active pattern (AP13) through the 22nd contact hole (CT22), connected to the first storage electrode (SE1) through the 8th contact hole (CT8), and connected to the first active pattern (AP11) through the 18th contact hole (CT18).

[0099] The above-mentioned fifth connecting electrode (SD5) is formed to be connected to the fourth active pattern (AP21) through the 28th contact hole (CT28), connected to the second storage electrode (SE2) through the 9th contact hole (CT9), and connected to the fourth active pattern (AP21) through the 24th contact hole (CT24).

[0100] The 6th connecting electrode (SD6) is formed to be connected to the 9th active pattern (AP33) through the 34th contact hole (CT34), connected to the 3rd storage electrode (SE3) through the 10th contact hole (CT10), and connected to the 7th active pattern (AP31) through the 30th contact hole (CT30).

[0101] The seventh connecting electrode (SD7) connects the first data wiring (DW1) and the second active pattern (AP12) through the first contact hole (CT11) and the second contact hole (CT20). The eighth connecting electrode (SD8) connects the second data wiring (DW2) and the fifth active pattern (AP22) through the second contact hole (CT12) and the second contact hole (CT26). The ninth connecting electrode (SD9) connects the third data wiring (DW3) and the eighth active pattern (AP32) through the third contact hole (CT13) and the third contact hole (CT32).

[0102] Meanwhile, in the above structure, the first active pattern (AP11), the first gate electrode pattern (GEP1), the fourth connection electrode (SD4), and the first connection electrode (SD1) form the first thin-film transistor (T1) of the first sub-pixel, the second active pattern (AP12), the fifth gate electrode pattern (GEP5), the first data connection pattern (DCP1), and the first connection electrode (SD1) form the second thin-film transistor (T2) of the first sub-pixel, and the third active pattern (AP13), the fourth gate electrode pattern (GEP4), the initialization connection pattern (INTP), and the high-voltage connection pattern (HVP) form the third thin-film transistor (T3) of the first sub-pixel.

[0103] Similarly, the first thin-film transistor (T1), the second thin-film transistor (T2), and the third thin-film transistor (T3) of the second sub-pixel are formed.

[0104] Referring to FIGS. 7i, 7j, and 7k, a third insulating film is formed on the result shown in FIG. 7h, and then the third insulating film is patterned using known photolithography and etching processes to form via holes (VIA1, VIA2, VIA3) that expose the drain electrodes of driving transistors. In this embodiment, the first via hole (VIA1) exposes the drain electrode of a driving transistor provided in a first sub-pixel, the second via hole (VIA2) exposes the drain electrode of a driving transistor provided in a second sub-pixel, and the third via hole (VIA3) exposes the drain electrode of a driving transistor provided in a third sub-pixel.

[0105] Next, after forming the fourth conductive film, the fourth conductive film is patterned by a photo process using a photomask to form the first low power supply voltage connection wiring (CL3), the second low power supply voltage connection wiring (CL4), the third low power supply voltage connection wiring (CL5), the first high power supply voltage connection wiring (CL6), the second high power supply voltage connection wiring (CL7), and the third high power supply voltage connection wiring (CL8). Here, the fourth conductive film may use a highly conductive metallic material used as an electrode material, and may include an alloy containing materials such as Al, Ti, Mo, Ag, Cr, Mo, Cu, etc., and may have a single layer or a multilayer structure of said material.

[0106] The first low power voltage connection wire (CL3), the second low power voltage connection wire (CL4), and the third low power voltage connection wire (CL5) can be electrically connected to the horizontal power line pattern (PWH) by means of contact holes. Through this, a low power voltage (ELVSS) can be applied to the first low power voltage connection wire (CL3), the second low power voltage connection wire (CL4), and the third low power voltage connection wire (CL5). The first low power voltage connection wire (CL3), the second low power voltage connection wire (CL4), and the third low power voltage connection wire (CL5) can be connected to the cathode electrode of a light-emitting element. In the embodiments, the light-emitting element may include an organic light-emitting diode (OLED), a quantum-dot organic light-emitting diode (QDOLED), a quantum-not nano light-emitting diode (QNED), etc.

[0107] The first high power supply voltage connection wiring (CL6) can be electrically connected to the first connection electrode (SD1) by the first via hole (VIA1). The first high power supply voltage connection wiring (CL6) can receive a high power supply voltage (ELVDD) from the first connection electrode (SD1). The first high power supply voltage connection wiring (CL6) can be electrically connected to the first anode electrode of the light-emitting element.

[0108] The second high power supply voltage connection wiring (CL7) can be electrically connected to the seventh connection electrode (SD7) by the third via hole (VIA3). The second high power supply voltage connection wiring (CL7) can receive a high power supply voltage (ELVDD) from the seventh connection electrode (SD7). The second high power supply voltage connection wiring (CL7) can be electrically connected to the second anode electrode of the light-emitting element.

[0109] The third high power supply voltage connection wiring (CL8) can be electrically connected to the fourth connection electrode (SD4) by the second via hole (VIA2). The third high power supply voltage connection wiring (CL8) can receive a high power supply voltage (ELVDD) from the fourth connection electrode (SD4). The third high power supply voltage connection wiring (CL8) can be electrically connected to the third anode electrode of the light-emitting element.

[0110] Referring to FIG. 71 and FIG. 7m, a plurality of partitions are formed within a unit pixel on the result shown in FIG. 7k. Here, the partitions may comprise polyamide. In this embodiment, the partitions include a first partition (W1), a second partition (W2), a third partition (W3), a fourth partition (W4), a fifth partition (W5), a sixth partition (W6), a seventh partition (W7), an eighth partition (W8), and a ninth partition (W9), and are formed vertically within the unit pixel from the observer's perspective. A reflective metal layer (not shown) is formed on the upper surface and side wall of the first through ninth partitions (W1, W2, W3, W4, W5, W6, W7, W8, W9). Holes may be formed in the partitions for contact between the reflective metal layer and a connecting electrode formed on the lower part of the partitions.

[0111] Referring to FIG. 7n and FIG. 7o, a first passivation layer (not shown) and a bank (BNK) are formed on the result shown in FIG. 7m. Here, the first passivation layer may include silicon oxide (SiOx), and the bank may include polyamide.

[0112] The first passivation layer is partially formed to cover a valley defined by adjacent partitions.

[0113] The bank (BNK) may include a first opening (OP1) formed to open an area corresponding to a first sub-pixel, a second opening (OP2) formed to open an area corresponding to a second sub-pixel, and a third opening (OP3) formed to open an area corresponding to a third sub-pixel.

[0114] After forming a first passivation layer and a bank, nano-sized diodes are placed in valleys defined by adjacent partitions. Here, the anodes or cathodes of the diodes are aligned in the same direction.

[0115] Referring to FIGS. 7p and FIGS. 7q, a pixel layer and a second passivation layer are formed on the result shown in FIGS. 7o. Here, the second passivation layer may include silicon oxide (SiOx).

[0116] The pixel layer comprises a first pixel line (PL11), a second pixel line (PL12), a third pixel line (PL13), a fourth pixel line (PL21), a fifth pixel line (PL22), a sixth pixel line (PL23), a seventh pixel line (PL31), an eighth pixel line (PL32), and a ninth pixel line (PL33). The first to third pixel lines (PL11, PL12, PL13) are formed in a first sub-pixel area, the fourth to sixth pixel lines (PL21, PL22, PL23) are formed in a second sub-pixel area, and the seventh to ninth pixel lines (PL31, PL32, PL33) are formed in a third sub-pixel area.

[0117] When viewed in a planar view, the first pixel line (PL11) and the second pixel line (PL12) have an I-shape, and the third pixel line (PL13) has a U-shape surrounding the second pixel line (PL12). When viewed in a planar view, the first pixel line (PL11) is formed on a part of the upper surface and right wall of the first partition (W1), and the second pixel line (PL12) is formed on a part of the upper surface and right wall of the second partition (W2). The third pixel line (PL13) is formed on a part of the upper surface and left wall of the second partition (W2), and on a part of the upper surface and left wall of the third partition (W3). Accordingly, one side width of the first to third pixel lines (PL11, PL12, PL13) contacts a reflective metal layer formed on the upper surface of the partitions, and the other side width of the first to third pixel lines (PL11, PL12, PL13) contacts nano-sized diodes disposed in the valley space between adjacent partitions.

[0118] When viewed in a planar view, the fourth pixel line (PL21) and the fifth pixel line (PL22) have an I-shape, and the sixth pixel line (PL23) has a U-shape surrounding the fifth pixel line (PL22). When viewed in a planar view, the fourth pixel line (PL21) is formed on a part of the upper surface and right wall of the fourth partition (W4), and the fifth pixel line (PL22) is formed on a part of the upper surface and right wall of the fifth partition (W5). The sixth pixel line (PL23) is formed on a part of the upper surface and left wall of the fifth partition (W5), and on a part of the upper surface and left wall of the sixth partition (W6). Accordingly, one side width of the fourth to sixth pixel lines (PL21, PL22, PL23) contacts a reflective metal layer formed on the upper surface of the partitions, and the other side width of the fourth to sixth pixel lines (PL21, PL22, PL23) contacts nano-sized diodes disposed in the valley space between adjacent partitions.

[0119] When viewed in a planar view, the 7th pixel line (PL31) and the 8th pixel line (PL32) have an I-shape, and the 9th pixel line (PL33) has a U-shape surrounding the 8th pixel line (PL32). When viewed in a planar view, the 7th pixel line (PL31) is formed on a part of the upper surface and right wall of the 7th partition (W7), and the 8th pixel line (PL32) is formed on a part of the upper surface and right wall of the 8th partition (W8). The 9th pixel line (PL33) is formed on a part of the upper surface and left wall of the 8th partition (W8), and on a part of the upper surface and left wall of the 9th partition (W9). Accordingly, one side width of the 7th to 9th pixel lines (PL31, PL32, PL33) contacts a reflective metal layer formed on the upper surface of the partitions, and the other side width of the 7th to 9th pixel lines (PL31, PL32, PL33) contacts nano-sized diodes disposed in the valley space between adjacent partitions.

[0120] A second passivation layer (not shown) is formed between adjacent pixel lines and covers a diode placed in the valley space between adjacent partitions. The second passivation layer can serve to block different pixel lines from coming into contact with each other on the diode.

[0121] In this embodiment, a metal reflective layer formed on one partition is connected to the drain electrode of a thin-film transistor below through a hole formed in the partition, and a metal reflective layer formed on another partition is connected to a low-voltage connection pattern below through a hole formed in the partition. Accordingly, one terminal of a diode placed in the valley space between adjacent partitions is connected to the drain electrode of a thin-film transistor through a pixel line and a metal reflective layer formed corresponding to one partition. Additionally, the other terminal of a diode placed in the valley space between adjacent partitions is connected to a low-voltage connection pattern through a pixel line and a metal reflective layer formed corresponding to the other partition.

[0122] Referring to FIGS. 7r and 7s, a light-blocking layer (BML) having a plurality of light-blocking windows (BMW) is formed on the result shown in FIG. 7q, and a quantum dot layer comprising red quantum dots (QDR), green quantum dots (QDG), and blue quantum dots (QDB) corresponding to each of the light-blocking windows (BMW) is formed. Here, a quantum dot (QD) refers to an ultrafine semiconductor particle with a diameter of only 2 to 10 nanometers that possesses unique electrical and optical properties. For example, a quantum dot crystal emits light of a specific frequency when exposed to light. These quantum dots make bright areas brighter and dark areas more fine and precise. The wavelength of the emitted light also varies depending on the size, enabling high color realization. Additionally, power consumption can be reduced.

[0123] The light-blocking windows (BMW) formed in the light-blocking layer (BML) expose each of the regions formed with pixel lines and diodes connected to the pixel lines.

[0124] A red quantum dot (QDR) is formed to cover pixel lines exposed by a single light-blocking window (BMW) and diodes connected to those pixel lines. Here, the diodes can emit blue light. When in operation, the red quantum dot (QDR) is excited as blue light is emitted from the diodes and emits red light.

[0125] A green quantum dot (QDG) is formed to cover pixel lines exposed by a single light-blocking window (BMW) and diodes connected to those pixel lines. When in operation, the green quantum dot (QDG) is excited as blue light is emitted from the diode and emits green light.

[0126] Blue quantum dots (QDBs) are formed to cover pixel lines exposed by a single light-blocking window (BMW) and diodes connected to those pixel lines. During operation, the blue quantum dots (QDBs) are excited as blue light is emitted from the diodes and emit blue light. In this embodiment, the area where the blue quantum dots (QDBs) are formed is smaller than the area where the red quantum dots (QDRs) or the green quantum dots (QDGs) are formed.

[0127] Although not shown, a light-blocking layer (BML), red quantum dots (QDR), green quantum dots (QDG), and blue quantum dots (QDB) may be formed, and then a first planarization layer, a color filter layer, and a second planarization layer may be sequentially formed on top thereof. The color filter layer may be formed by forming a red color filter layer, a green color filter layer, and a blue color filter layer, respectively, corresponding to each of the sub-pixels.

[0128] FIG. 8 is a diagram illustrating the connection between sub-pixels and data lines corresponding to the color arrangement shown in FIG. 2.

[0129] Referring to FIGS. 2, 4, and 8, the 2n-th (n is a natural number) unit pixel comprises a plurality of sub-pixels arranged in the order of blue, red, and green, and the 2n-1-th unit pixel comprises a plurality of sub-pixels arranged in the order of red, green, and blue. Each of the 2n-th and 2n-1-th unit pixels is connected to a red data line that transmits red data, a green data line that transmits green data, and a blue data line that transmits blue data. The pixel circuit of each unit pixel includes first, second, and third transistors (T1, T2, T3) and a capacitor (Cst), as shown in FIG. 4, but for convenience of explanation, only the switching transistor (T2) is shown.

[0130] In the 2n-th unit pixel, blue data applied to the blue data line is applied to the blue display element (B) via the switching transistor (T2). Also, red data applied to the red data line is applied to the red display element (R) via the switching transistor (T2). Also, green data applied to the green data line is applied to the green display element (G) via the switching transistor (T2).

[0131] Meanwhile, at the 2n-1th unit pixel, red data applied to the red data line is applied to the red display element (B) via the switching transistor (T2). Also, red data applied to the green data line is applied to the green display element (R) via the switching transistor (T2). Also, blue data applied to the blue data line is applied to the blue display element (B) via the switching transistor (T2).

[0132] In this way, even if the arrangement order of sub-pixels within adjacent unit pixels is staggered, the display operation can be performed normally. Additionally, since display elements emitting different colored light are arranged in the column direction, it is possible to prevent monochromatic or stained colors from being visible.

[0133] FIG. 9 is a plan view illustrating another example of a color arrangement corresponding to the joint area of ​​the tiled display device illustrated in FIG. 1. In particular, an example of a color arrangement that repeats in three cycles is illustrated. In FIG. 9, the sub-display panel placed above the joint is, for example, the first sub-display panel (110) illustrated in FIG. 1, and the sub-display panel placed below the joint is, for example, the second sub-display panel (120) illustrated in FIG. 1.

[0134] Referring to FIGS. 1 and 9, each of the sub-display panels includes a plurality of unit pixels corresponding to a plurality of lines. Here, each of the unit pixels corresponding to the 3n-th row is arranged in the order of a green sub-pixel, a blue sub-pixel, and a red sub-pixel, each of the unit pixels corresponding to the 3n-1-th row is arranged in the order of a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and each of the unit pixels corresponding to the 3n-2-th row is arranged in the order of a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0135] In this way, sub-pixels within unit pixels corresponding to adjacent lines are arranged in an alternating pattern. In other words, within the unit pixels corresponding to the first row, sub-pixels are arranged in the order of RGB, within the unit pixels corresponding to the second row, sub-pixels are arranged in the order of BRG, and within the unit pixels corresponding to the third row, sub-pixels are arranged in the order of GBR.

[0136] Therefore, even if the second sub-display panel (120) is attached to the first sub-display panel (110) by inverting it 180 degrees relative to the first sub-display panel (110), stain visibility caused by pixel asymmetry in the joint can be prevented.

[0137] In addition, even if the first sub-display panel (110) and the second sub-display panel (120) are misaligned, stain visibility caused by pixel asymmetry at the joint can be prevented.

[0138] FIG. 10 is a diagram illustrating the connection between sub-pixels and data lines corresponding to the color arrangement shown in FIG. 9. In particular, it shows the sub-pixels and data lines arranged in the first sub-display panel shown in FIG. 9.

[0139] Referring to FIGS. 9 and 10, the 3n-th (n is a natural number) unit pixel comprises a plurality of sub-pixels arranged in the order of green, blue, and red, the 3n-1-th unit pixel comprises a plurality of sub-pixels arranged in the order of blue, red, and green, and the 3n-2-th unit pixel comprises a plurality of sub-pixels arranged in the order of red, green, and blue. Each of the 3n-th, 3n-1-th, and 3n-2-th unit pixels is connected to a red data line that transmits red data, a green data line that transmits green data, and a blue data line that transmits blue data. The pixel circuit of each unit pixel includes first, second, and third transistors (T1, T2, T3) and a capacitor (Cst) as shown in FIG. 4, but for convenience of explanation, only the switching transistor (T2) is shown.

[0140] In the 3n-th unit pixel, green data applied to the green data line is applied to the green display element (B) via the switching transistor (T2). Also, blue data applied to the blue data line is applied to the blue display element (R) via the switching transistor (T2). Also, red data applied to the red data line is applied to the red display element (G) via the switching transistor (T2).

[0141] In the 3n-1th unit pixel, blue data applied to the blue data line is applied to the blue display element (B) via the switching transistor (T2). Also, red data applied to the red data line is applied to the red display element (R) via the switching transistor (T2). Also, green data applied to the green data line is applied to the green display element (G) via the switching transistor (T2).

[0142] Meanwhile, at the 3n-2th unit pixel, red data applied to the red data line is applied to the red display element (B) via the switching transistor (T2). Also, red data applied to the green data line is applied to the green display element (R) via the switching transistor (T2). Also, blue data applied to the blue data line is applied to the blue display element (B) via the switching transistor (T2).

[0143] In this way, even if the arrangement order of sub-pixels within adjacent unit pixels is staggered, the display operation can be performed normally. Additionally, since display elements emitting different colored light are arranged in the column direction, it is possible to prevent monochromatic or stained colors from being visible.

[0144] FIG. 11 is a plan view for illustrating another example of a color arrangement corresponding to the joint area of ​​the tiled display device illustrated in FIG. 1. In particular, an example of a color arrangement that repeats in four cycles is illustrated. In FIG. 11, the sub-display panel placed above the joint is, for example, the first sub-display panel (110) illustrated in FIG. 1, and the sub-display panel placed below the joint is, for example, the second sub-display panel (120) illustrated in FIG. 1.

[0145] Referring to FIGS. 1 and FIGS. 11, each of the sub-display panels includes a plurality of unit pixels corresponding to a plurality of lines. Here, each of the unit pixels corresponding to the 4n-th row is arranged in the order of a blue sub-pixel, a red sub-pixel, and a green sub-pixel; each of the unit pixels corresponding to the 4n-1-th row is arranged in the order of a green sub-pixel, a blue sub-pixel, and a red sub-pixel; each of the unit pixels corresponding to the 4n-2-th row is arranged in the order of a blue sub-pixel, a red sub-pixel, and a green sub-pixel; and each of the unit pixels corresponding to the 4n-3-th row is arranged in the order of a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0146] In this way, sub-pixels within unit pixels corresponding to adjacent lines are arranged in an alternating pattern. That is, within the unit pixels corresponding to the first row, sub-pixels are arranged in the order of BRG, within the unit pixels corresponding to the second row, sub-pixels are arranged in the order of GBR, within the unit pixels corresponding to the third row, sub-pixels are arranged in the order of BRG, and within the unit pixels corresponding to the fourth row, sub-pixels are arranged in the order of RGB.

[0147] Therefore, even if the second sub-display panel (120) is inverted 180 degrees relative to the first sub-display panel (110) and attached to the first sub-display panel (110), stain visibility caused by pixel asymmetry in the joint can be prevented.

[0148] In addition, even if the first sub-display panel (110) and the second sub-display panel (120) are misaligned, stain visibility caused by pixel asymmetry at the joint can be prevented.

[0149] FIG. 12 is a diagram illustrating the connection between sub-pixels and data lines corresponding to the color arrangement shown in FIG. 11.

[0150] Referring to FIGS. 11 and 12, the 4n-th (n is a natural number) unit pixel comprises a plurality of sub-pixels arranged in the order of blue, red, and green, and the 4n-1-th unit pixel comprises a plurality of sub-pixels arranged in the order of green, blue, and red. The 4n-2-th unit pixel comprises a plurality of sub-pixels arranged in the order of blue, red, and green, and the 4n-3-th unit pixel comprises a plurality of sub-pixels arranged in the order of red, green, and blue. Each of the 4n-th, 4n-1-th, 4n-2-th, and 4n-3-th unit pixels is connected to a red data line that transmits red data, a green data line that transmits green data, and a blue data line that transmits blue data. The pixel circuit of each unit pixel includes first, second, and third transistors (T1, T2, T3) and a capacitor (Cst) as shown in FIG. 4, but for convenience of explanation, only the switching transistor (T2) is shown.

[0151] In the 4n-th unit pixel, blue data applied to the blue data line is applied to the blue display element (B) via the switching transistor (T2). Also, red data applied to the red data line is applied to the red display element (R) via the switching transistor (T2). Also, green data applied to the green data line is applied to the green display element (G) via the switching transistor (T2).

[0152] In the 4n-1th unit pixel, green data applied to the green data line is applied to the green display element (B) via the switching transistor (T2). Also, blue data applied to the blue data line is applied to the blue display element (R) via the switching transistor (T2). Also, red data applied to the red data line is applied to the red display element (G) via the switching transistor (T2).

[0153] In the 4n-2th unit pixel, blue data applied to the blue data line is applied to the blue display element (B) via the switching transistor (T2). Also, red data applied to the red data line is applied to the red display element (R) via the switching transistor (T2). Also, green data applied to the green data line is applied to the green display element (G) via the switching transistor (T2).

[0154] Meanwhile, at the 4n-3rd unit pixel, red data applied to the red data line is applied to the red display element (B) via the switching transistor (T2). Also, red data applied to the green data line is applied to the green display element (R) via the switching transistor (T2). Also, blue data applied to the blue data line is applied to the blue display element (B) via the switching transistor (T2).

[0155] In this way, even if the arrangement order of sub-pixels within adjacent unit pixels is staggered, the display operation can be performed normally. Additionally, since display elements emitting different colored light are arranged in the column direction, it is possible to prevent monochromatic or stained colors from being visible.

[0156] As described above, according to the present invention, by configuring the arrangement order of sub-pixels within unit pixels corresponding to the current row and the arrangement order of sub-pixels within unit pixels corresponding to the previous row or the next row differently from each other, the visibility of stains caused by the arrangement of sub-pixels near the bonding area where a plurality of display panels are attached can be improved.

[0157] Although the invention has been described above with reference to embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as described in the following claims. Explanation of the symbols

[0158] 110: 1st sub-display panel 120: 2nd sub-display panel 130: 3rd sub-display panel 140: 4th sub-display panel PX: Sub-pixel T1, T2, T3: Transistor Cst: Capacitor LED: Diode 211: Current scan line 213: Previous scan line 215: Data line 217: Initialization voltage line 219: Driving high voltage line 221: Driving low voltage line

Claims

Claim 1 A tiled display device comprising: a first sub-display panel having a plurality of unit pixels formed therein; and a second sub-display panel disposed adjacent to the first sub-display panel and having a plurality of unit pixels formed therein, wherein each of the unit pixels includes a plurality of sub-pixels having a display element emitting color light and a pixel circuit driving the display element, wherein the arrangement order of sub-pixels within the unit pixels corresponding to the current row and the arrangement order of sub-pixels within the unit pixels corresponding to the previous row or the next row are different from each other, and the arrangement order of sub-pixels within the unit pixels corresponding to the k-th row (where k is a natural number) in the first sub-display panel is different from the arrangement order of sub-pixels within the unit pixels corresponding to the k-th row in the second sub-display panel. Claim 2 A tiled display device according to claim 1, characterized in that the upper and lower adjacent display elements in the column direction emit different colored light. Claim 3 A tiled display device according to claim 1, characterized in that a sub-pixel corresponding to the n-th row and m-th column (wherein and m are natural numbers) emits a first color light, and a sub-pixel corresponding to the n+1-th row and m-th column emits a second color light. Claim 4 A tiled display device according to claim 1, characterized in that the arrangement order of sub-pixels within a unit pixel corresponding to the 2n-th row (wherein is a natural number) is C3-C1-C2 (wherein C1 is a first sub-pixel emitting a first color light, C2 is a second sub-pixel emitting a second color light, and C3 is a third sub-pixel emitting a third color light), and the arrangement order of sub-pixels within a unit pixel corresponding to the 2n-1th row is C1-C2-C3. Claim 5 A tiled display device according to claim 1, characterized in that the arrangement order of sub-pixels within a unit pixel corresponding to the 3n-th row (wherein is a natural number) is C2-C3-C1 (wherein C1 is a first sub-pixel emitting a first color light, C2 is a second sub-pixel emitting a second color light, and C3 is a third sub-pixel emitting a third color light), the arrangement order of sub-pixels within a unit pixel corresponding to the 3n-1th row is C3-C1-C2, and the arrangement order of sub-pixels within a unit pixel corresponding to the 3n-2th row is C1-C2-C3. Claim 6 A tiled display device according to claim 1, characterized in that the arrangement order of sub-pixels within a unit pixel corresponding to the 4n-th row (where n is a natural number) is C3-C1-C2 (where C1 is a first sub-pixel emitting a first color light, C2 is a second sub-pixel emitting a second color light, and C3 is a third sub-pixel emitting a third color light), the arrangement order of sub-pixels within a unit pixel corresponding to the 4n-1th row is C2-C3-C1, the arrangement order of sub-pixels within a unit pixel corresponding to the 4n-2nd row is C3-C1-C2, and the arrangement order of sub-pixels within a unit pixel corresponding to the 4n-3rd row is C1-C2-C3. Claim 7 A tiled display device characterized in that, in any one of claims 4 to 6, the first sub-pixel emits red color light, the second sub-pixel emits green color light, and the third sub-pixel emits blue color light. Claim 8 A tiled display device according to claim 1, wherein each of the unit pixels comprises a first sub-pixel, a second sub-pixel, and a third sub-pixel, wherein the first sub-pixel is a red sub-pixel emitting red color light, the second sub-pixel is a green sub-pixel emitting green color light, and the third sub-pixel is a blue sub-pixel emitting blue color light. Claim 9 A tiled display device according to claim 1, characterized in that the number of sub-display panels is four or more. Claim 10 A tiled display device according to claim 1, wherein the sub-pixel further comprises a current scan line, a first data line transmitting a data signal corresponding to a first color light, a second data line transmitting a data signal corresponding to a second color light, and a third data line transmitting a data signal corresponding to a third color light, and the pixel circuit comprises a first transistor connected to the display element; and a second transistor connected to the current scan line, wherein the source electrode of the second transistor is connected to any one of the first data line, the second data line, and the third data line. Claim 11 A tiled display device according to claim 1, characterized in that the display element is either an organic light-emitting diode or a nanodiode. Claim 12 A sub-display panel for a tiled display device, wherein a plurality of such sub-display panels are attached to form a tiled display device, comprising: a first unit pixel including a plurality of sub-pixels arranged on a plane; and a second unit pixel arranged adjacent to the first unit pixel in a column direction and including a plurality of sub-pixels arranged on a plane, wherein each of the unit pixels includes a plurality of sub-pixels having a display element emitting color light and a pixel circuit driving the display element, wherein the arrangement order of sub-pixels within the unit pixels corresponding to the current row and the arrangement order of sub-pixels within the unit pixels corresponding to the previous row or the next row are different from each other, and wherein the arrangement order of sub-pixels within the unit pixels corresponding to the k-th row (where k is a natural number) in the sub-display panel for the tiled display device is different from the arrangement order of sub-pixels within the unit pixels corresponding to the k-th row in another sub-display panel for a tiled display device adjacent to the sub-display panel for the tiled display device. Claim 13 A sub-display panel for a tiled display device according to claim 12, wherein each of the first unit pixel and the second unit pixel comprises a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light, and wherein the arrangement order of the first to third sub-pixels provided in the first unit pixel and the arrangement order of the first to third sub-pixels provided in the second unit pixel are different from each other. Claim 14 A sub-display panel for a tiled display device, characterized in that, in claim 12, the arrangement order of sub-pixels within the first unit pixel is C3-C1-C2 (wherein C1 is a first sub-pixel emitting a first color light, C2 is a second sub-pixel emitting a second color light, and C3 is a third sub-pixel emitting a third color light), and the arrangement order of sub-pixels within the second unit pixel is C1-C2-C3. Claim 15 A sub-display panel for a tiled display device according to claim 12, further comprising a third unit pixel including a plurality of sub-pixels arranged in a row direction in a third order on a plane and arranged adjacently in a column direction to the second unit pixel, wherein the arrangement order of sub-pixels within the first unit pixel is C2-C3-C1 (wherein C1 is a first sub-pixel emitting a first color light, C2 is a second sub-pixel emitting a second color light, and C3 is a third sub-pixel emitting a third color light), the arrangement order of sub-pixels within the second unit pixel is C3-C1-C2, and the arrangement order of sub-pixels within the third unit pixel is C1-C2-C3. Claim 16 In claim 12, a third unit pixel comprising a plurality of sub-pixels arranged adjacently in a column direction to the second unit pixel and arranged in a third order in a row direction on a plane; A sub-display panel for a tiled display device, further comprising a fourth unit pixel that is arranged adjacently in a column direction to the third unit pixel and includes a plurality of sub-pixels arranged in a fourth order in a row direction on a plane, wherein the arrangement order of sub-pixels within the first unit pixel is C3-C1-C2 (wherein C1 is a first sub-pixel emitting a first color light, C2 is a second sub-pixel emitting a second color light, and C3 is a third sub-pixel emitting a third color light), the arrangement order of sub-pixels within the second unit pixel is C2-C3-C1, the arrangement order of sub-pixels within the third unit pixel is C3-C1-C2, and the arrangement order of sub-pixels within the fourth unit pixel is C1-C2-C3.

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