Display device

Abstract

A display device is provided. The display device comprises a first substrate including a display area and a non-display area surrounding the display area, a plurality of subpixels including a plurality of light-emitting elements disposed on the first substrate in the display area, a first bank surrounding the subpixels in the display area, a plurality of color control structures disposed within the area surrounded by the first bank on the light-emitting elements of the plurality of subpixels, a plurality of color filter layers disposed on the color control structures, a second bank disposed spaced apart from the first bank and surrounding the display area in the non-display area, and a plurality of color dams disposed on the second bank, wherein the color dams include a first color dam disposed on a portion disposed on the first side of the display area in the second bank, and a second color dam disposed on a portion disposed on the second side opposite to the first side of the display area in the second bank, and the first color dams and the second color dams comprise different materials.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] The importance of display devices is increasing along with the development of multimedia. In response to this, various types of display devices, such as Organic Light Emitting Displays (OLEDs) and Liquid Crystal Displays (LCDs), are being used.

[0003] There are self-luminous display devices that include a light-emitting element as a device for displaying images. Self-luminous display devices include organic light-emitting display devices that use organic materials as light-emitting materials as light-emitting elements, or inorganic light-emitting display devices that use inorganic materials as light-emitting materials. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a display device including a structure capable of preventing organic materials made of different materials from overflowing.

[0005] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A display device according to one embodiment for solving the above problem comprises: a first substrate including a display area and a non-display area surrounding the display area; a plurality of subpixels including a plurality of light-emitting elements disposed on the first substrate in the display area; a first bank surrounding the subpixels in the display area; a plurality of color control structures disposed within the area surrounded by the first bank on the light-emitting elements of the plurality of subpixels; a plurality of color filter layers disposed on the color control structures; a second bank disposed spaced apart from the first bank and surrounding the display area in the non-display area; and a plurality of color dams disposed on the second bank, wherein the color dams include a first color dam disposed on a portion disposed on the first side of the display area in the second bank, and a second color dam disposed on a portion disposed on the second side opposite to the first side of the display area in the second bank, and the first color dams and the second color dams include different materials.

[0007] The above subpixel includes a first subpixel and a second subpixel spaced apart from the first subpixel in one direction, the color control structure includes a first wavelength conversion layer disposed on the first subpixel and a light-transmitting layer disposed on the second subpixel, and the color filter layer may include a first color filter layer disposed on the first wavelength conversion layer and a second color filter layer disposed on the light-transmitting layer.

[0008] The first color dam and the second color dam are spaced apart in one direction with the display area in between, and the first color dam may include the same material as the first color filter layer and the second color dam may include the same material as the second color filter layer.

[0009] The above subpixel further includes a third subpixel disposed between the first subpixel and the second subpixel, the color control structure further includes a second wavelength conversion layer disposed on the third subpixel, the color filter layer further includes a third color filter layer disposed on the second wavelength conversion layer, and may further include a third color dam disposed on the first color dam and comprising the same material as the third color filter layer.

[0010] The width of the third color dam is greater than the width of the first color dam, and the outer surface of the first color dam can be covered by the third color dam.

[0011] It further includes a plurality of color patterns arranged to overlap with the first bank, wherein the color patterns include a first color pattern having the same material as the first color filter layer, a second color pattern having the same material as the second color filter layer, and a third color pattern having the same material as the third color filter layer, and the first color pattern may be arranged to overlap with the second color filter layer and the third color filter layer, respectively.

[0012] The first color dam and the second color dam are spaced apart in one direction with the display area in between, and the first color dam may include the same material as the second color filter layer, and the second color dam may include the same material as the first color filter layer.

[0013] The above color control structures further include a first capping layer disposed on the first bank and the second bank, a low-refractive index layer disposed on the first capping layer, and a second capping layer disposed on the low-refractive index layer, wherein the first color dam and the second color dam may be disposed on the second capping layer.

[0014] The apparatus further includes a flattening layer disposed between the second capping layer and the color filter layer, and the first color dam and the second color dam may each be directly disposed on the flattening layer on the second bank.

[0015] It may further include a light-blocking member disposed on the flattening layer and overlapping with the first bank, and an overcoat layer disposed on the light-blocking member and the color filter layer.

[0016] It may include a via layer disposed on the first substrate in the display area and the non-display area, a third bank disposed on the via layer and spaced apart from the second bank in the non-display area to surround the second bank, and a first valley portion disposed between the first bank and the second bank in the non-display area and penetrating the via layer.

[0017] The first color dam may be arranged in multiple numbers and placed on the portion on one side of the display area among the second bank and the third bank, respectively, and the second color dam may be arranged in multiple numbers and placed on the portion on the other side of the display area among the second bank and the third bank, respectively.

[0018] It may further include a plurality of bank partitions directly disposed on the via layer between the first bank and the first valley portion.

[0019] The first bank and the second bank each include a base layer and an upper layer disposed on the base layer, and the upper layer may have a width greater than that of the base layer.

[0020] The above subpixels include a plurality of electrodes that extend in one direction and are spaced apart from each other, and the plurality of light-emitting elements can be disposed on the plurality of electrodes that are spaced apart from each other.

[0021] The light-emitting element may include a first electrode disposed on the first substrate, an organic layer disposed on the first electrode, and a second electrode disposed on the organic layer.

[0022] A display device according to an embodiment for solving the above problem comprises: a display area; a non-display area surrounding the display area; a plurality of subpixels arranged in the display area and arranged in a first direction and a second direction intersecting the first direction, wherein the subpixels include a first electrode, a second electrode spaced apart from the first electrode, and a plurality of light-emitting elements having both ends placed on the first electrode and the second electrode; a first bank arranged extending in the display area in the first direction and the second direction and surrounding the subpixels; a plurality of color control structures arranged within the area surrounded by the first bank; a plurality of color filter layers arranged on the color control structures; a first valley portion arranged in the non-display area spaced apart from the first bank and surrounding the first bank; a second bank arranged in the non-display area spaced apart from the first valley portion and surrounding the first valley portion; a third bank arranged in the non-display area spaced apart from the second bank and surrounding the second bank; and among the non-display area The present invention includes a plurality of first color dams arranged extending in the first direction in a first dam area arranged on one side of the second direction of the present invention area, and a plurality of second color dams arranged extending in the first direction in a second dam area arranged on the other side of the second direction of the present invention area among the non-presentation areas, wherein the first color dam and the second color dam include different materials.

[0023] The plurality of first color dams may be arranged to overlap with the second bank and the third bank, respectively, which are arranged in the first dam area, and the plurality of second color dams may be arranged to overlap with the second bank and the third bank, respectively, which are arranged in the second dam area.

[0024] The color filter layer comprises a plurality of first color filter layers, a plurality of second color filter layers spaced apart from each of the plurality of first color filter layers in the second direction, and a plurality of third color filter layers spaced apart from each of the plurality of second color filter layers in the second direction, wherein the first color filter layer, the second color filter layer, and the third color filter layer are each alternately arranged along the second direction, and the first color dam may include the same material as the third color filter layer, and the second color dam may include the same material as the first color filter layer.

[0025] It may further include a third color dam disposed on the second color dam and containing the same material as the second color filter layer.

[0026] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0027] A display device according to one embodiment may include a plurality of color dams disposed in a non-display area as a structure disposed in the outer part of a display area. The color dams may include the same material as any one of the color filter layers of the display device, but the color dams disposed in different outer parts may include different materials. The display device may form different color dams together in the formation process of each different color filter layer, and the display device may prevent organic material from overflowing by adding a minimum number of process steps.

[0028] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0029] FIG. 1 is a schematic plan view of a display device according to one embodiment. FIG. 2 is a plan view showing one pixel of a display device according to one embodiment. Figure 3 is a cross-sectional view taken along the line N1-N1' of Figure 2. Figure 4 is a cross-sectional view taken along the line N2-N2' of Figure 2. FIG. 5 is a schematic diagram of a light-emitting element according to one embodiment. FIG. 6 is a cross-sectional view of a display device according to one embodiment. FIG. 7 is a schematic diagram showing banks arranged in a display area and a non-display area of ​​a display device according to one embodiment. Figure 8 is a cross-sectional view taken along the line A1-A1' of Figure 7. Figure 9 is a cross-sectional view taken along the line A2-A2' of Figure 7. FIG. 10 is a schematic diagram showing the arrangement of a color filter layer and a color dam of a display device according to one embodiment. FIG. 11 is a schematic diagram illustrating an area where a mask process is performed for forming a first color filter layer and a first color dam of a display device according to one embodiment. FIG. 12 is a schematic diagram illustrating an area where a mask process for forming a second color filter layer of a display device according to one embodiment is performed. FIG. 13 is a schematic diagram illustrating an area where a mask process is performed for forming a third color filter layer and a second color dam of a display device according to one embodiment. FIG. 14 is a cross-sectional view of a display device according to another embodiment. FIG. 15 is a cross-sectional view showing the outer part of the display device of FIG. 14. FIG. 16 is a cross-sectional view showing the outer portion of a display device according to another embodiment. FIG. 17 is a schematic diagram showing the arrangement of a color filter layer and a color dam of a display device according to another embodiment. FIGS. 18 and FIGS. 19 are cross-sectional views showing the outer periphery of the display device of FIG. 17. FIG. 20 is a cross-sectional view of a display device according to another embodiment. FIG. 21 is a cross-sectional view showing the outer part of the display device of FIG. 20. FIGS. 22 and FIGS. 23 are cross-sectional views showing the outer periphery of a display device according to another embodiment. FIG. 24 is a plan view showing one subpixel of a display device according to another embodiment. FIG. 25 is a cross-sectional view taken along the line N3-N3' of FIG. 24. FIG. 26 is a cross-sectional view taken along the line N4-N4' of FIG. 24. FIG. 27 is a plan view showing one subpixel of a display device according to another embodiment. FIG. 28 is a cross-sectional view taken along the line N5-N5' of FIG. 27. FIG. 29 is a cross-sectional view taken along the line N6-N6' of FIG. 27. FIG. 30 is a cross-sectional view taken along the line N7-N7' of FIG. 27. FIG. 31 is a cross-sectional view of a display device according to another embodiment. FIG. 32 is a cross-sectional view showing the outer part of the display device of FIG. 31. FIG. 33 is a cross-sectional view showing the outer portion of a display device according to another embodiment. Specific details for implementing the invention

[0030] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0031] Elements or layers referred to as "on" another element or layer include cases where another layer or element is interposed directly above or in the middle of another element. Likewise, "below," "left," and "right" refer to cases where they are interposed immediately adjacent to another element or where another layer or material is interposed in the middle. Throughout the specification, the same reference numerals refer to the same components.

[0032] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0033] Hereinafter, embodiments will be described with reference to the attached drawings.

[0034] FIG. 1 is a schematic plan view of a display device according to one embodiment.

[0035] Referring to FIG. 1, the display device (10) displays a video or a still image. The display device (10) may refer to any electronic device that provides a display screen. For example, a television, laptop, monitor, billboard, Internet of Things, mobile phone, smartphone, tablet PC (Personal Computer), electronic watch, smart watch, watch phone, head-mounted display, mobile communication terminal, electronic notebook, electronic book, PMP (Portable Multimedia Player), navigation, game console, digital camera, camcorder, etc. that provide a display screen may be included in the display device (10).

[0036] The display device (10) includes a display panel that provides a display screen. Examples of display panels include an inorganic light-emitting diode display panel, an organic light-emitting diode display panel, a quantum dot light-emitting diode display panel, a plasma display panel, a field emission display panel, etc. In the following examples, an inorganic light-emitting diode display panel is used as an example of a display panel, but it is not limited thereto, and if the same technical concept is applicable, it can be applied to other display panels.

[0037] The shape of the display device (10) can be varied in many ways. For example, the display device (10) may have a shape such as a horizontally elongated rectangle, a vertically elongated rectangle, a square, a rectangle with rounded corners (vertices), other polygons, or a circle. The shape of the display area (DPA) of the display device (10) may also be similar to the overall shape of the display device (10). In FIG. 1, a display device (10) in the shape of a rectangle with a long length in the second direction (DR2) is illustrated.

[0038] The display device (10) may include a display area (DPA) and a non-display area (NDA). The display area (DPA) is an area where the screen can be displayed, and the non-display area (NDA) is an area where the screen is not displayed. The display area (DPA) may also be referred to as an active area, and the non-display area (NDA) as an inactive area. The display area (DPA) may generally occupy the center of the display device (10).

[0039] The display area (DPA) may include a plurality of pixels (PX). The plurality of pixels (PX) may be arranged in a matrix direction. The shape of each pixel (PX) may be a planar rectangle or a square, but is not limited thereto, and may be a rhombus shape with each side tilted toward one direction. Each pixel (PX) may be arranged in a stripe type or an island type. Additionally, each of the pixels (PX) may include one or more light-emitting elements that emit light of a specific wavelength range to display a specific color.

[0040] A non-display area (NDA) may be placed around a display area (DPA). The non-display area (NDA) may surround the display area (DPA) in whole or in part. The display area (DPA) is rectangular in shape, and the non-display area (NDA) may be placed adjacent to the four sides of the display area (DPA). The non-display area (NDA) may form the bezel of the display device (10). In each non-display area (NDA), wiring or circuit drivers included in the display device (10) may be placed, or external devices may be mounted.

[0041] FIG. 2 is a plan view showing a pixel of a display device according to one embodiment. FIG. 2 illustrates the planar arrangement of electrodes (RME; RME1, RME2), bank patterns (BP1, BP2), a lower bank layer (LBN), a plurality of light-emitting elements (ED), and connecting electrodes (CNE; CNE1, CNE2) placed in a pixel (PX) of a display device (10).

[0042] Referring to FIG. 2, each of the pixels (PX) of the display device (10) may include a plurality of subpixels (SPXn). For example, one pixel (PX) may include a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3). The first subpixel (SPX1) may emit light of a first color, the second subpixel (SPX2) may emit light of a second color, and the third subpixel (SPX3) may emit light of a third color. As an example, the first color may be blue, the second color may be green, and the third color may be red. However, not limited thereto, each subpixel (SPXn) may emit light of the same color. In one embodiment, each subpixel (SPXn) may emit blue light. In the drawing, one pixel (PX) is illustrated as containing three subpixels (SPXn), but is not limited thereto, and the pixel (PX) may contain a larger number of subpixels (SPXn).

[0043] Each subpixel (SPXn) of the display device (10) may include a light-emitting region (EMA) and a non-light-emitting region. The light-emitting region (EMA) may be an area where a light-emitting element (ED) is placed and light of a specific wavelength range is emitted. The non-light-emitting region may be an area where a light-emitting element (ED) is not placed and light emitted from the light-emitting element (ED) does not reach and is not emitted.

[0044] The light-emitting region (EMA) may include an area where a light-emitting element (ED) is placed and an area adjacent to the light-emitting element (ED) through which light emitted from the light-emitting element (ED) is emitted. For example, the light-emitting region (EMA) may also include an area where light emitted from the light-emitting element (ED) is reflected or refracted by another component and emitted. A plurality of light-emitting elements (ED) are placed in each subpixel (SPXn), and the light-emitting region (EMA) may be formed by including the area where they are placed and an area adjacent thereto.

[0045] In the drawings, the light-emitting regions (EMAs) of each subpixel (SPXn) are illustrated as having uniform areas, but are not limited thereto. In some embodiments, each light-emitting region (EMA) of each subpixel (SPXn) may have different areas depending on the color or wavelength of light emitted from the light-emitting element (ED) placed in the corresponding subpixel.

[0046] Each subpixel (SPXn) may further include a sub-region (SA) placed in a non-emissive region. The sub-region (SA) of the corresponding subpixel (SPXn) may be placed on the lower side, which is the other side of the first direction (DR1) of the emitting region (EMA). The emitting region (EMA) and the sub-region (SA) are arranged alternately along the first direction (DR1), and the sub-region (SA) may be placed between the emitting regions (EMA) of different subpixels (SPXn) that are spaced apart in the first direction (DR1). For example, the emitting region (EMA) and the sub-region (SA) may be arranged alternately with each other in the first direction (DR1), and each of the emitting region (EMA) and the sub-region (SA) may be repeatedly arranged in the second direction (DR2). However, this is not limited thereto, and the emitting regions (EMA) and sub-regions (SA) in a plurality of pixels (PX) may have an arrangement different from that of FIG. 2.

[0047] In the sub-region (SA), light is not emitted because no light-emitting element (ED) is placed, but some of the electrodes (RME) placed in each sub-pixel (SPXn) may be placed therein. The electrodes (RME) placed in different sub-pixels (SPXn) may be placed separated from each other in the separation section (ROP) of the sub-region (SA).

[0048] The wiring and circuit elements of the circuit layer can be connected to the first to third subpixels (SPX1, SPX2, SPX3), respectively. However, the wiring and circuit elements are not arranged to correspond to the area occupied by each subpixel (SPXn) or light-emitting region (EMA), but can be arranged within a single pixel (PX) regardless of the position of the light-emitting region (EMA).

[0049] The lower bank layer (LBN) may be arranged to surround a plurality of subpixels (SPXn), a light-emitting region (EMA), and a sub-region (SA). The lower bank layer (LBN) may be arranged at the boundary of subpixels (SPXn) adjacent in a first direction (DR1) and a second direction (DR2), and may also be arranged at the boundary of a light-emitting region (EMA) and a sub-region (SA). The subpixels (SPXn), light-emitting region (EMA), and sub-region (SA) of the display device (10) may be regions separated by the arrangement of the lower bank layer (LBN). The spacing between the plurality of subpixels (SPXn), light-emitting regions (EMA), and sub-regions (SA) may vary depending on the width of the lower bank layer (LBN).

[0050] The lower bank layer (LBN) may be arranged in a grid pattern across the entire front of the display area (DPA), including portions extending in the first direction (DR1) and the second direction (DR2) in the plane. The lower bank layer (LBN) may be arranged across the boundaries of each subpixel (SPXn) to distinguish neighboring subpixels (SPXn). Additionally, the lower bank layer (LBN) may be arranged to surround the light-emitting area (EMA) and sub-area (SA) arranged for each subpixel (SPXn) to distinguish them.

[0051] FIG. 3 is a cross-sectional view taken along the line N1-N1' of FIG. 2. FIG. 4 is a cross-sectional view taken along the line N2-N2' of FIG. 2. FIG. 3 illustrates a cross-section across both ends of a light-emitting element (ED) placed in a first subpixel (SPX1) and electrode contact holes (CTD, CTS), and FIG. 4 illustrates a cross-section across both ends of a light-emitting element (ED) placed in a first subpixel (SPXn) and contact portions (CT1, CT2).

[0052] Referring to FIG. 3 and FIG. 4 in conjunction with FIG. 2, the display device (10) may include a first substrate (SUB) and a semiconductor layer, a plurality of conductive layers, and a plurality of insulating layers disposed on the first substrate (SUB). The semiconductor layer, the conductive layer, and the insulating layers may each constitute a circuit layer and a display element layer of the display device (10).

[0053] The first substrate (SUB) may be an insulating substrate. The first substrate (SUB) may be made of an insulating material such as glass, quartz, or a polymer resin. Additionally, the first substrate (SUB) may be a rigid substrate, but may also be a flexible substrate capable of bending, folding, rolling, etc. The first substrate (SUB) includes a display area (DPA) and a non-display area (NDA) surrounding it, and the display area (DPA) may include a light-emitting area (EMA) and a sub-area (SA) which is a part of the non-light-emitting area.

[0054] The first conductive layer may be disposed on the first substrate (SUB). The first conductive layer includes a lower metal layer (BML), and the lower metal layer (BML) is disposed to overlap with the active layer (ACT1) of the first transistor (T1). The lower metal layer (BML) may perform the function of preventing light from being incident on the active layer (ACT1) of the first transistor, or electrically connecting to the first active layer (ACT1) to stabilize the electrical characteristics of the first transistor (T1). However, the lower metal layer (BML) may be omitted.

[0055] A buffer layer (BL) can be disposed on a lower metal layer (BML) and a first substrate (SUB). The buffer layer (BL) is formed on the first substrate (SUB) to protect the transistors of the pixel (PX) from moisture penetrating through the first substrate (SUB), which is susceptible to moisture permeability, and can perform a surface planarization function.

[0056] The semiconductor layer is disposed on the buffer layer (BL). The semiconductor layer may include a first active layer (ACT1) of the first transistor (T1) and a second active layer (ACT2) of the second transistor (T2). The first active layer (ACT1) and the second active layer (ACT2) may be disposed to partially overlap with the first gate electrode (G1) and the second gate electrode (G2) of the second conductive layer, respectively, which will be described later.

[0057] The semiconductor layer may include polycrystalline silicon, single-crystal silicon, oxide semiconductors, etc. In another embodiment, the semiconductor layer may include polycrystalline silicon. The oxide semiconductor may be an oxide semiconductor containing indium (In). For example, the oxide semiconductor may be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), and indium gallium zinc tin oxide (IGZTO).

[0058] In the drawing, one first transistor (T1) and one second transistor (T2) are shown arranged in a subpixel (SPXn) of the display device (10), but the display device (10) is not limited thereto and may include a larger number of transistors.

[0059] The first gate insulating layer (GI) is placed on the semiconductor layer and the buffer layer (BL). The first gate insulating layer (GI) can serve as the gate insulating film for each transistor (T1, T2).

[0060] The second conductive layer is disposed on the first gate insulating layer (GI). The second conductive layer may include a first gate electrode (G1) of the first transistor (T1) and a second gate electrode (G2) of the second transistor (T2). The first gate electrode (G1) may be disposed to overlap the channel region of the first active layer (ACT1) in the third direction (DR3), which is the thickness direction, and the second gate electrode (G2) may be disposed to overlap the channel region of the second active layer (ACT2) in the third direction (DR3), which is the thickness direction. Although not shown in the drawing, the second conductive layer may further include one electrode of the storage capacitor.

[0061] The first interlayer insulating layer (IL1) is disposed on the second conductive layer. The first interlayer insulating layer (IL1) functions as an insulating film between the second conductive layer and other layers disposed thereon, and can protect the second conductive layer.

[0062] A third conductive layer is disposed on the first interlayer insulating layer (IL1). The third conductive layer may include a first voltage line (VL1) and a second voltage line (VL2) disposed in a display area (DPA), a first conductive pattern (CDP1), and source electrodes (S1, S2) and drain electrodes (D1, D2) of each transistor (T1, T2). Although not shown in the drawing, the third conductive layer may further include other electrodes of a storage capacitor.

[0063] A high potential voltage (or a first power supply voltage) delivered to the first electrode (RME1) can be applied to the first voltage line (VL1), and a low potential voltage (or a second power supply voltage) delivered to the second electrode (RME2) can be applied to the second voltage line (VL2). A portion of the first voltage line (VL1) can contact the first active layer (ACT1) of the first transistor (T1) through a contact hole penetrating the first interlayer insulating layer (IL1) and the first gate insulating layer (GI). The first voltage line (VL1) can serve as the first drain electrode (D1) of the first transistor (T1). The second voltage line (VL2) can be directly connected to the second electrode (RME2) described later.

[0064] The first conductive pattern (CDP) can be in contact with the first active layer (ACT1) of the first transistor (T1) through a contact hole penetrating the first interlayer insulating layer (IL1) and the first gate insulating layer (GI). The first conductive pattern (CDP) can be in contact with the lower metal layer (BML) through another contact hole. The first conductive pattern (CDP) can serve as the first source electrode (S1) of the first transistor (T1). Additionally, the first conductive pattern (CDP) can be connected to the first electrode (RME1) or the first connection electrode (CNE1) described later. The first transistor (T1) can transmit the first power supply voltage applied from the first voltage wiring (VL1) to the first electrode (RME1) or the first connection electrode (CNE1).

[0065] The second source electrode (S2) and the second drain electrode (D2) can each contact the second active layer (ACT2) of the second transistor (T2) through a contact hole penetrating the first interlayer insulating layer (IL1) and the first gate insulating layer (GI).

[0066] The first protective layer (PV1) is disposed on the third conductive layer. The first protective layer (PV1) functions as an insulating film between the third conductive layer and other layers and can protect the third conductive layer.

[0067] The above-described buffer layer (BL), first gate insulating layer (GI), first interlayer insulating layer (IL1), and first protective layer (PV1) may be composed of a plurality of inorganic layers stacked alternately. For example, the buffer layer (BL), first gate insulating layer (GI), first interlayer insulating layer (IL1), and first protective layer (PV1) may be silicon oxide (SiO₂). x ), Silicon Nitride (SiN x ), Silicon Oxynitride (SiO₂ x N y It may be formed into a double layer in which an inorganic layer comprising at least one of ) is stacked, or a multilayer in which the same is stacked alternately. However, it is not limited thereto, and the buffer layer (BL), the first gate insulating layer (GI), the first interlayer insulating layer (IL1), and the first protective layer (PV1) may be formed into a single inorganic layer including the insulating material described above. In addition, in some embodiments, the first interlayer insulating layer (IL1) may be made of an organic insulating material such as polyimide (PI).

[0068] The second conductive layer and the third conductive layer may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, they are not limited thereto.

[0069] A via layer (VIA) is disposed on a third conductive layer in a display area (DPA). The via layer (VIA) may comprise an organic insulating material, such as polyimide (PI), to compensate for the step difference caused by the underlying conductive layers and to form a flat upper surface. However, in some embodiments, the via layer (VIA) may be omitted.

[0070] Bank patterns (BP1, BP2), a plurality of electrodes (RME; RME1, RME2), a lower bank layer (LBN), a plurality of light-emitting elements (ED), and a plurality of connecting electrodes (CNE; CNE1, CNE2) are disposed on the via layer (VIA) as display element layers. Additionally, a plurality of insulating layers (PAS1, PAS2, PAS3) may be disposed on the via layer (VIA).

[0071] Multiple bank patterns (BP1, BP2) can be placed in the light-emitting region (EMA) of each subpixel (SPXn). The bank patterns (BP1, BP2) may have a shape that has a certain width in the second direction (DR2) and extends in the first direction (DR1).

[0072] For example, bank patterns (BP1, BP2) may include a first bank pattern (BP1) and a second bank pattern (BP2) spaced apart from each other in a second direction (DR2) within the light-emitting region (EMA) of each subpixel (SPXn). The first bank pattern (BP1) may be positioned on the left side, which is one side of the second direction (DR2) from the center of the light-emitting region (EMA), and the second bank patterns (BP2) may be spaced apart from the first bank pattern (BP1) and positioned on the right side, which is the other side of the second direction (DR2) from the center of the light-emitting region (EMA). The first bank pattern (BP1) and the second bank pattern (BP2) may be alternately positioned along the second direction (DR2) and may be arranged in an island pattern in the display region (DPA). A plurality of light-emitting elements (ED) may be positioned between the first bank pattern (BP1) and the second bank pattern (BP2).

[0073] The first bank pattern (BP1) and the second bank pattern (BP2) have the same length in the first direction (DR1), but may be smaller than the length in the first direction (DR1) of the light-emitting region (EMA) surrounded by the lower bank layer (LBN). The first bank pattern (BP1) and the second bank pattern (BP2) may be spaced apart from the portion of the lower bank layer (LBN) that extends in the second direction (DR2). However, they are not limited thereto, and the bank patterns (BP1, BP2) may be integrated with the lower bank layer (LBN) or partially overlap with the portion of the lower bank layer (LBN) that extends in the second direction (DR2). In this case, the length in the first direction (DR1) of the bank patterns (BP1, BP2) may be equal to or greater than the length in the first direction (DR1) of the light-emitting region (EMA) surrounded by the lower bank layer (LBN).

[0074] The first bank pattern (BP1) and the second bank pattern (BP2) may have the same width in the second direction (DR2). However, they are not limited thereto and may have different widths. For example, one bank pattern may have a larger width than the other bank pattern, and the bank pattern with the larger width may be placed across the light-emitting regions (EMA) of other subpixels (SPXn) adjacent in the second direction (DR2). In this case, the portion of the bank pattern placed across multiple light-emitting regions (EMA) that extends in the first direction (DR1) of the lower bank layer (LBN) may overlap with the second bank pattern (BP2) in the thickness direction. In the drawing, it is illustrated that two bank patterns (BP1, BP2) are placed with the same width for each subpixel (SPXn), but this is not limited thereto. The number and shape of the bank patterns (BP1, BP2) may vary depending on the number or arrangement structure of the electrodes (RME).

[0075] Multiple bank patterns (BP1, BP2) may be disposed on a via layer (VIA). For example, bank patterns (BP1, BP2) may be disposed directly on the via layer (VIA) and may have a structure in which at least a portion protrudes with respect to the upper surface of the via layer (VIA). The protruding portion of the bank patterns (BP1, BP2) may have inclined or curved sides, and light emitted from the light-emitting element (ED) may be reflected from the electrode (RME) disposed on the bank patterns (BP1, BP2) and emitted in the direction of the upper side of the via layer (VIA). Unlike as illustrated in the drawings, the bank patterns (BP1, BP2) may have the shape of a semicircle or semi-ellipse with a curved outer surface in a cross-sectional view. The bank patterns (BP1, BP2) may include an organic insulating material such as polyimide (PI), but are not limited thereto.

[0076] Multiple electrodes (RME; RME1, RME2) are arranged in a shape extending in one direction for each subpixel (SPXn). The multiple electrodes (RME1, RME2) may extend in a first direction (DR1) and be placed in the light-emitting region (EMA) and sub-region (SA) of the subpixel (SPXn), and may be spaced apart from each other in a second direction (DR2). The multiple electrodes (RME) may be electrically connected to the light-emitting element (ED) described later, but are not limited thereto and may not be electrically connected to the light-emitting element (ED).

[0077] The display device (10) may include a first electrode (RME1) and a second electrode (RME2) disposed in each subpixel (SPXn). The first electrode (RME1) is disposed to the left of the center of the light-emitting region (EMA), and the second electrode (RME2) is disposed to the right of the center of the light-emitting region (EMA) by being spaced apart from the first electrode (RME1) in a second direction (DR2). The first electrode (RME1) may be disposed on a first bank pattern (BP1), and the second electrode (RME2) may be disposed on a second bank pattern (BP2). The first electrode (RME1) and the second electrode (RME2) may be partially disposed in the corresponding subpixel (SPXn) and sub-region (SA) beyond the lower bank layer (LBN). The first electrode (RME1) and the second electrode (RME2) of different subpixels (SPXn) can be spaced apart from each other based on a separation portion (ROP) located within a sub-region (SA) of one subpixel (SPXn).

[0078] In the drawing, it is illustrated that each subpixel (SPXn) has two electrodes (RME) extending in a first direction (DR1), but is not limited thereto. For example, the display device (10) may have a larger number of electrodes (RME) arranged in one subpixel (SPXn), or the electrodes (RME) may be partially bent and have different widths depending on the position.

[0079] The first electrode (RME1) and the second electrode (RME2) may be disposed on at least the inclined side of the bank pattern (BP1, BP2). In one embodiment, the width of the plurality of electrodes (RME) measured in the second direction (DR2) may be smaller than the width of the bank pattern (BP1, BP2) measured in the second direction (DR2), and the spacing between the first electrode (RME1) and the second electrode (RME2) in the second direction (DR2) may be narrower than the spacing between the bank patterns (BP1, BP2). The first electrode (RME1) and the second electrode (RME2) may be disposed on the same plane as at least some regions are disposed directly on the via layer (VIA).

[0080] A light-emitting element (ED) placed between bank patterns (BP1, BP2) emits light in both end directions, and the emitted light can be directed toward an electrode (RME) placed on the bank patterns (BP1, BP2). Each electrode (RME) may have a structure in which a portion placed on the bank patterns (BP1, BP2) can reflect the light emitted from the light-emitting element (ED). The first electrode (RME1) and the second electrode (RME2) are placed to cover at least one side of the bank patterns (BP1, BP2) so as to reflect the light emitted from the light-emitting element (ED).

[0081] Each electrode (RME) can directly contact the third conductive layer through electrode contact holes (CTD, CTS) in the portion overlapping with the lower bank layer (LBN) between the light-emitting region (EMA) and the sub-region (SA). The first electrode contact hole (CTD) may be formed in the area where the lower bank layer (LBN) and the first electrode (RME1) overlap, and the second electrode contact hole (CTS) may be formed in the area where the lower bank layer (LBN) and the second electrode (RME2) overlap. The first electrode (RME1) can contact the first conductive pattern (CDP) through the first electrode contact hole (CTD) penetrating the via layer (VIA) and the first protective layer (PV1). The second electrode (RME2) can contact the second voltage wiring (VL2) through the second electrode contact hole (CTS) penetrating the via layer (VIA) and the first protective layer (PV1). The first electrode (RME1) may be electrically connected to the first transistor (T1) through the first conductive pattern (CDP) to apply the first power supply voltage, and the second electrode (RME2) may be electrically connected to the second voltage wiring (VL2) to apply the second power supply voltage. However, it is not limited thereto. In other embodiments, each electrode (RME1, RME2) may not be electrically connected to the voltage wiring (VL1, VL2) of the third conductive layer, and the connecting electrode (CNE) described below may be directly connected to the third conductive layer.

[0082] Multiple electrodes (RMEs) may include a highly reflective conductive material. For example, the electrodes (RMEs) may include a metal such as silver (Ag), copper (Cu), aluminum (Al), an alloy such as aluminum (Al), nickel (Ni), lanthanum (La), or a structure in which a metal layer such as titanium (Ti), molybdenum (Mo), and niobium (Nb) is stacked with said alloy. In some embodiments, the electrodes (RMEs) may be composed of a double layer or a multilayer structure in which an alloy containing aluminum (Al) and at least one metal layer consisting of titanium (Ti), molybdenum (Mo), and niobium (Nb) are stacked.

[0083] Each electrode (RME) may further include a transparent conductive material, without being limited thereto. For example, each electrode (RME) may include a material such as ITO, IZO, ITZO, etc. In some embodiments, each electrode (RME) may have a structure in which a transparent conductive material and a highly reflective metal layer are each stacked one or more times, or may be formed as a single layer including these. For example, each electrode (RME) may have a stacked structure such as ITO / Ag / ITO / , ITO / Ag / IZO, or ITO / Ag / ITZO / IZO. The electrodes (RME) are electrically connected to a light-emitting element (ED) and may reflect some of the light emitted from the light-emitting element (ED) toward the upper direction of the first substrate (SUB).

[0084] The first insulating layer (PAS1) is disposed on the front surface of the display area (DPA) and can be disposed on a via layer (VIA) and a plurality of electrodes (RME). The first insulating layer (PAS1) can protect the plurality of electrodes (RME) while simultaneously insulating different electrodes (RME) from each other. In particular, the first insulating layer (PAS1) is disposed to cover the electrodes (RME) before the lower bank layer (LBN) is formed, thereby preventing the electrodes (RME) from being damaged during the process of forming the lower bank layer (LBN). Additionally, the first insulating layer (PAS1) can prevent the light-emitting element (ED) disposed thereon from being damaged by direct contact with other components.

[0085] In an exemplary embodiment, the first insulating layer (PAS1) may have a step formed such that a portion of its upper surface is recessed between electrodes (RME) spaced apart in the second direction (DR2). A light-emitting element (ED) is disposed on the upper surface of the first insulating layer (PAS1) where the step is formed, and a space may be formed between the light-emitting element (ED) and the first insulating layer (PAS1).

[0086] A lower bank layer (LBN) may be disposed on a first insulating layer (PAS1). The lower bank layer (LBN) includes a portion extending in a first direction (DR1) and a second direction (DR2) and may surround each subpixel (SPXn). The lower bank layer (LBN) may surround and distinguish the light-emitting region (EMA) and sub-region (SA) of each subpixel (SPXn), and may surround the outermost edge of the display region (DPA) and distinguish the display region (DPA) from the non-display region (NDA). The lower bank layer (LBN) is disposed across the entire display region (DPA) to form a grid pattern, and the area where the lower bank layer (LBN) opens in the display region (DPA) may be the light-emitting region (EMA) and the sub-region (SA).

[0087] The lower bank layer (LBN) may have a certain height similar to the bank pattern (BP1, BP2). In some embodiments, the height of the upper surface of the lower bank layer (LBN) may be higher than that of the bank pattern (BP1, BP2), and its thickness may be equal to or greater than that of the bank pattern (BP1, BP2). The lower bank layer (LBN) can prevent ink from overflowing into adjacent subpixels (SPXn) during the inkjet printing process in the manufacturing process of the display device (10). The lower bank layer (LBN) may include an organic insulating material such as polyimide, similar to the bank pattern (BP1, BP2).

[0088] A plurality of light-emitting elements (EDs) may be placed in a light-emitting region (EMA). The light-emitting elements (EDs) may be placed between bank patterns (BP1, BP2) and arranged spaced apart from each other in a first direction (DR1). In one embodiment, the plurality of light-emitting elements (EDs) may have a shape that extends in one direction, and both ends may be placed on different electrodes (RMEs). The length of the light-emitting elements (EDs) may be longer than the spacing between the electrodes (RMEs) spaced apart in a second direction (DR2). The light-emitting elements (EDs) may generally be arranged such that their extended direction is perpendicular to the first direction (DR1) in which the electrodes (RMEs) extend. However, they are not limited thereto, and the extended direction of the light-emitting elements (EDs) may be arranged to face the second direction (DR2) or a direction inclined obliquely thereto.

[0089] A plurality of light-emitting elements (EDs) may be disposed on a first insulating layer (PAS1). The light-emitting elements (EDs) may have a shape that extends in one direction and may be disposed such that the extended one direction is parallel to the upper surface of the first substrate (SUB). As described below, the light-emitting elements (EDs) may include a plurality of semiconductor layers disposed along the extended one direction, and the plurality of semiconductor layers may be sequentially disposed along a direction parallel to the upper surface of the first substrate (SUB). However, not limited thereto, if the light-emitting elements (EDs) have a different structure, the plurality of semiconductor layers may be disposed in a direction perpendicular to the first substrate (SUB).

[0090] The light-emitting elements (EDs) placed in each subpixel (SPXn) can emit light of different wavelengths depending on the material of the semiconductor layer described above. However, not limited thereto, the light-emitting elements (EDs) placed in each subpixel (SPXn) may include a semiconductor layer of the same material and emit light of the same color.

[0091] The light-emitting elements (EDs) can be electrically connected to the conductive layers under the electrode (RME) and via layer (VIA) by contacting the connecting electrodes (CNE: CNE1, CNE2), and can emit light of a specific wavelength range when an electrical signal is applied.

[0092] A second insulating layer (PAS2) may be disposed on a plurality of light-emitting elements (ED), a first insulating layer (PAS1), and a lower bank layer (LBN). The second insulating layer (PAS2) includes a pattern portion that extends in a first direction (DR1) between bank patterns (BP1, BP2) and is disposed on a plurality of light-emitting elements (ED). The pattern portion is disposed to partially cover the outer surface of the light-emitting element (ED), and may not cover both sides or both ends of the light-emitting element (ED). The pattern portion may form a linear or island pattern within each subpixel (SPXn) in a planar view. The pattern portion of the second insulating layer (PAS2) can protect the light-emitting element (ED) and, at the same time, fix the light-emitting elements (ED) during the manufacturing process of the display device (10). Additionally, the second insulating layer (PAS2) may be disposed to fill the space between the light-emitting element (ED) and the second insulating layer (PAS2) below it. Additionally, a portion of the second insulating layer (PAS2) may be placed on the upper part of the lower bank layer (LBN) and in the sub-regions (SA).

[0093] A plurality of connecting electrodes (CNE; CNE1, CNE2) may be disposed on a plurality of electrodes (RME) and bank patterns (BP1, BP2). Each of the plurality of connecting electrodes (CNE) may have a shape extending in one direction and may be disposed spaced apart from each other. Each connecting electrode (CNE) may be in contact with a light-emitting element (ED) and electrically connected to a third conductive layer.

[0094] A plurality of connecting electrodes (CNE) may include a first connecting electrode (CNE1) and a second connecting electrode (CNE2) disposed in each subpixel (SPXn). The first connecting electrode (CNE1) may have a shape extending in a first direction (DR1) and may be disposed on a first electrode (RME1) or a first bank pattern (BP1). The first connecting electrode (CNE1) may partially overlap with the first electrode (RME1) and may be disposed from the light-emitting region (EMA) beyond the lower bank layer (LBN) to a sub-region (SA). The second connecting electrode (CNE2) may have a shape extending in a first direction (DR1) and may be disposed on a second electrode (RME2) or a second bank pattern (BP2). The second connecting electrode (CNE2) may partially overlap with the second electrode (RME2) and may be disposed from the light-emitting region (EMA) beyond the lower bank layer (LBN) to a sub-region (SA). The first connecting electrode (CNE1) and the second connecting electrode (CNE2) each come into contact with light-emitting elements (ED) and can be electrically connected to electrodes (RME) or the conductive layer underneath.

[0095] For example, the first connecting electrode (CNE1) and the second connecting electrode (CNE2) are each disposed on the side of the second insulating layer (PAS2) and can come into contact with light-emitting elements (EDs). The first connecting electrode (CNE1) partially overlaps with the first electrode (RME1) and can come into contact with one end of the light-emitting elements (EDs). The second connecting electrode (CNE2) partially overlaps with the second electrode (RME2) and can come into contact with the other end of the light-emitting elements (EDs). A plurality of connecting electrodes (CNEs) are disposed across the light-emitting region (EMA) and the sub-region (SA). The connecting electrodes (CNEs) can come into contact with the light-emitting elements (EDs) in the portion disposed in the light-emitting region (EMA) and can be electrically connected to the third conductive layer in the portion disposed in the sub-region (SA).

[0096] According to one embodiment, the display device (10) may have each connecting electrode (CNE) in contact with an electrode (RME) through contact portions (CT1, CT2) disposed in a sub-region (SA). The first connecting electrode (CNE1) may be in contact with the first electrode (RME1) through a first contact portion (CT1) that penetrates the first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) in the sub-region (SA). The second connecting electrode (CNE2) may be in contact with the second electrode (RME2) through a second contact portion (CT2) that penetrates the first insulating layer (PAS1) and the second insulating layer (PAS2) in the sub-region (SA). Each connecting electrode (CNE) may be electrically connected to the third conductive layer through each electrode (RME). The first connecting electrode (CNE1) is electrically connected to the first transistor (T1) so that the first power supply voltage is applied, and the second connecting electrode (CNE2) is electrically connected to the second voltage wiring (VL2) so that the second power supply voltage can be applied. Each connecting electrode (CNE) can contact the light-emitting element (ED) in the light-emitting region (EMA) to transmit the power supply voltage to the light-emitting element (ED).

[0097] However, it is not limited thereto. In some embodiments, a plurality of connecting electrodes (CNE) may be in direct contact with the third conductive layer, or may be electrically connected to the third conductive layer through patterns other than the electrodes (RME).

[0098] Connecting electrodes (CNEs) may include a conductive material. For example, they may include ITO, IZO, ITZO, aluminum (Al), etc. As an example, the connecting electrode (CNE) may include a transparent conductive material, and light emitted from the light-emitting element (ED) may pass through the connecting electrode (CNE) and be emitted.

[0099] A third insulating layer (PAS3) is disposed on the second connecting electrode (CNE2) and the second insulating layer (PAS2). The third insulating layer (PAS3) is disposed entirely on the second insulating layer (PAS2) to cover the second connecting electrode (CNE2), and the first connecting electrode (CNE1) may be disposed on the third insulating layer (PAS3). The third insulating layer (PAS3) may be disposed entirely on the via layer (VIA), except for the area where the second connecting electrode (CNE2) is disposed. The third insulating layer (PAS3) may insulate the first connecting electrode (CNE1) from the second connecting electrode (CNE2) so that they do not come into direct contact with each other.

[0100] Although not illustrated in the drawings, other insulating layers may be disposed on the third insulating layer (PAS3) and the first connecting electrode (CNE1). The insulating layers may function to protect the members disposed on the first substrate (SUB) from the external environment.

[0101] The first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) described above may each comprise an inorganic insulating material or an organic insulating material. For example, the first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) may each comprise an inorganic insulating material, or the first insulating layer (PAS1) and the third insulating layer (PAS3) may comprise an inorganic insulating material, while the second insulating layer (PAS2) may comprise an organic insulating material. The first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) may each, or at least one of them, be formed in a structure in which a plurality of insulating layers are stacked alternately or repeatedly. In an exemplary embodiment, the first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) may each be silicon oxide (SiO₂). x ), silicon nitride (SiN x ), and silicon oxynitride (SiO₂ x N yIt may be any one of the following. The first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) may be made of the same material, some of which may be made of the same material and some of which may be made of different material, or each of which may be made of different material.

[0102] FIG. 5 is a schematic diagram of a light-emitting element according to one embodiment.

[0103] Referring to FIG. 5, the light-emitting element (ED) may be a light-emitting diode, and specifically, the light-emitting element (ED) may be an inorganic light-emitting diode made of inorganic material having a size in the nanometer to micrometer range. The light-emitting element (ED) may be aligned between two electrodes that form polarity when an electric field is formed in a specific direction between the two electrodes facing each other.

[0104] A light-emitting element (ED) according to one embodiment may have a shape that extends in one direction. The light-emitting element (ED) may have a shape such as a cylinder, a rod, a wire, or a tube. However, the shape of the light-emitting element (ED) is not limited thereto, and the light-emitting element (ED) may have various shapes, such as a polygonal prism shape like a cube, a rectangular prism, or a hexagonal prism, or a shape that extends in one direction but has a partially inclined outer surface.

[0105] The light-emitting element (ED) may include a semiconductor layer doped with any conductivity type (e.g., p-type or n-type) dopant. The semiconductor layer may emit light of a specific wavelength range when an electrical signal applied from an external power source is transmitted. The light-emitting element (ED) may include a first semiconductor layer (31), a second semiconductor layer (32), a light-emitting layer (36), an electrode layer (37), and an insulating film (38).

[0106] The first semiconductor layer (31) may be an n-type semiconductor. The first semiconductor layer (31) may include a semiconductor material having the chemical formula AlxGayIn1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the first semiconductor layer (31) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with an n-type dopant. The n-type dopant doped in the first semiconductor layer (31) may be Si, Ge, Sn, etc.

[0107] The second semiconductor layer (32) is disposed on the first semiconductor layer (31) with the light-emitting layer (36) in between. The second semiconductor layer (32) may be a p-type semiconductor, and the second semiconductor layer (32) may include a semiconductor material having the chemical formula AlxGayIn1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the second semiconductor layer (32) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant. The p-type dopant doped in the second semiconductor layer (32) may be Mg, Zn, Ca, Ba, etc.

[0108] Meanwhile, the drawing shows the first semiconductor layer (31) and the second semiconductor layer (32) as being composed of a single layer, but is not limited thereto. Depending on the material of the light-emitting layer (36), the first semiconductor layer (31) and the second semiconductor layer (32) may further include a greater number of layers, such as a clad layer or a TSBR (Tensile strain barrier reducing) layer. For example, the light-emitting device (ED) may further include other semiconductor layers disposed between the first semiconductor layer (31) and the light-emitting layer (36), or between the second semiconductor layer (32) and the light-emitting layer (36). The semiconductor layer disposed between the first semiconductor layer (31) and the light-emitting layer (36) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, InN and SLs doped with an n-type dopant, and the semiconductor layer disposed between the second semiconductor layer (32) and the light-emitting layer (36) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN and InN doped with a p-type dopant.

[0109] The light-emitting layer (36) is disposed between the first semiconductor layer (31) and the second semiconductor layer (32). The light-emitting layer (36) may include a material having a single or multiple quantum well structure. If the light-emitting layer (36) includes a material having a multiple quantum well structure, it may have a structure in which a barrier layer and a well layer are alternately stacked. The light-emitting layer (36) can emit light by the coupling of electron-hole pairs according to an electrical signal applied through the first semiconductor layer (31) and the second semiconductor layer (32). The light-emitting layer (36) may include materials such as AlGaN, AlGaInN, and InGaN. In particular, if the light-emitting layer (36) has a structure in which a barrier layer and a well layer are alternately stacked in a multiple quantum well structure, the barrier layer may include a material such as AlGaN or AlGaInN, and the well layer may include a material such as GaN, InGaN, or AlInN.

[0110] The light-emitting layer (36) may have a structure in which semiconductor materials with large band gap energy and semiconductor materials with small band gap energy are alternately stacked, and may include different group 3 to group 5 semiconductor materials depending on the wavelength range of the light emitted. The light emitted by the light-emitting layer (36) is not limited to light in the blue wavelength range, and may emit light in the red or green wavelength range depending on the case.

[0111] The electrode layer (37) may be an ohmic connection electrode. However, it is not limited thereto and may be a Schottky connection electrode. The light-emitting element (ED) may include at least one electrode layer (37). The light-emitting element (ED) may include one or more electrode layers (37), but is not limited thereto and the electrode layer (37) may be omitted.

[0112] The electrode layer (37) can reduce the resistance between the light-emitting element (ED) and the electrode or connecting electrode when the light-emitting element (ED) in the display device (10) is electrically connected to the electrode or connecting electrode. The electrode layer (37) may include a conductive metal. For example, the electrode layer (37) may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), ITO, IZO, and ITZO.

[0113] The insulating film (38) is arranged to surround the outer surface of the plurality of semiconductor layers and electrode layers described above. For example, the insulating film (38) may be arranged to surround the outer surface of at least the light-emitting layer (36), but may be formed so that both ends in the longitudinal direction of the light-emitting element (ED) are exposed. Additionally, the insulating film (38) may be formed with a rounded upper surface in cross-section in an area adjacent to at least one end of the light-emitting element (ED).

[0114] The insulating film (38) is made of materials having insulating properties, for example, silicon oxide (SiO₂). x ), silicon nitride (SiNx ), silicon oxynitride (SiO₂ x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x It may include ) etc. In the drawing, the insulating film (38) is exemplified as being formed as a single layer, but is not limited thereto, and in some embodiments, the insulating film (38) may be formed as a multilayer structure in which a plurality of layers are stacked.

[0115] The insulating film (38) can perform the function of protecting the semiconductor layers and electrode layers of the light-emitting element (ED). The insulating film (38) can prevent an electrical short circuit that may occur in the light-emitting layer (36) when in direct contact with the electrode through which an electrical signal is transmitted to the light-emitting element (ED). In addition, the insulating film (38) can prevent a decrease in the light-emitting efficiency of the light-emitting element (ED).

[0116] Additionally, the outer surface of the insulating film (38) may be surface-treated. The light-emitting element (ED) may be sprayed onto the electrode and aligned in a dispersed state within a predetermined ink. Here, in order for the light-emitting element (ED) to remain dispersed without aggregating with other adjacent light-emitting elements (ED) within the ink, the surface of the insulating film (38) may be treated to be hydrophobic or hydrophilic.

[0117] According to one embodiment, the display device (10) may further include a color control structure ('TPL', 'WCL1', 'WCL2' of FIG. 6) and a color filter layer ('CFL1', 'CFL2', 'CFL3' of FIG. 6) disposed on light-emitting elements (EDs). Light emitted from the light-emitting elements (EDs) may be emitted through the color control structure (TPL, WCL1, WCL2) and the color filter layer (CFL1, CFL2, CFL3), and even if the same type of light-emitting elements (EDs) are disposed for each subpixel (SPXn), the color of the emitted light may differ for each subpixel (SPXn).

[0118] FIG. 6 is a cross-sectional view of a display device according to one embodiment.

[0119] Referring to FIG. 6, the display device (10) may include light-emitting elements (ED) disposed on a first substrate (SUB), and a color control structure (TPL, WCL1, WCL2) and a color filter layer (CFL1, CFL2, CFL3) disposed thereon. Additionally, the display device (10) may further include a plurality of layers disposed between the color control structures (TPL, WCL1, WCL2) and the color filter layers (CFL1, CFL2, CFL3). Below, the layers disposed on the light-emitting elements (ED) of the display device (10) will be described.

[0120] The fourth insulating layer (PAS4) may be disposed on the third insulating layer (PAS3), the connecting electrodes (CNE1, CNE2), and the lower bank layer (LBN). The fourth insulating layer (PAS4) may protect the layers disposed on the first substrate (SUB). However, the fourth insulating layer (PAS4) may be omitted.

[0121] A first bank (BNL1), a color control structure (TPL, WCL1, WCL2), a light-blocking member (BM), and a color filter layer (CFL1, CFL2, CFL3) may be disposed on the fourth insulating layer (PAS4). Additionally, a plurality of capping layers (CPL1, CPL2) and a low-refractive index layer (LRL) may be disposed between the color control structure (TPL, WCL1, WCL2) and the color filter layer (CFL1, CFL2, CFL3), and an overcoat layer (OC) may be disposed on the color filter layer (CFL1, CFL2, CFL3).

[0122] The display device (10) may include a plurality of light-emitting regions (TA1, TA2, TA3) in which light is emitted by arranging color filter layers (CFL1, CFL2, CFL3), and a light-blocking region (BA) in which light is not emitted between the light-emitting regions (TA1, TA2, TA3). The light-emitting regions (TA1, TA2, TA3) may be located corresponding to a part of the light-emitting region (EMA) of each subpixel (SPXn), and the light-blocking region (BA) may be an area other than the light-emitting regions (TA1, TA2, TA3). As described below, the light-emitting regions (TA1, TA2, TA3) and the light-blocking region (BA) may be separated by a light-blocking member (BM).

[0123] The first bank (BNL1) may be arranged to overlap with the lower bank layer (LBN) on the fourth insulating layer (PAS4). The first bank (BNL1) may be arranged in a grid pattern including portions extending in the first direction (DR1) and the second direction (DR2). The first bank (BNL1) may surround portions where light-emitting regions (EMA) or light-emitting elements (ED) are arranged. The first bank (BNL1) may form a region where color control structures (TPL, WCL1, WCL2) are arranged.

[0124] Color control structures (TPL, WCL1, WCL2) may be placed within the area surrounded by the first bank (BNL1) on the fourth insulating layer (PAS4). The color control structures (TPL, WCL1, WCL2) may be placed in the light-transmitting areas (TA1, TA2, TA3) surrounded by the first bank (BNL1) to form an island-shaped pattern in the display area (DPA). However, not limited thereto, the color control structures (TPL, WCL1, WCL2) may each extend in one direction and be placed across a plurality of subpixels (SPXn) to form a linear pattern.

[0125] In an embodiment in which the light-emitting element (ED) of each subpixel (SPXn) emits blue light of a third color, the color control structure (TPL, WCL1, WCL2) may include a first wavelength conversion layer (WCL1) disposed in the first subpixel (SPX1) corresponding to the first light-emitting region (TA1), a second wavelength conversion layer (WCL2) disposed in the second subpixel (SPX2) corresponding to the second light-emitting region (TA2), and a light-emitting layer (TPL) disposed in the third subpixel (SPX3) corresponding to the third light-emitting region (TA3).

[0126] The first wavelength conversion layer (WCL1) may include a first base resin (BRS1) and a first wavelength conversion material (WCP1) disposed within the first base resin (BRS1). The second wavelength conversion layer (WCL2) may include a second base resin (BRS2) and a second wavelength conversion material (WCP2) disposed within the second base resin (BRS2). The first wavelength conversion layer (WCL1) and the second wavelength conversion layer (WCL2) convert and transmit the wavelength of the third color blue light incident from the light-emitting element (ED). The first wavelength conversion layer (WCL1) and the second wavelength conversion layer (WCL2) further include a scatterer (SCP) contained in each base resin, and the scatterer (SCP) can increase the wavelength conversion efficiency.

[0127] The light-transmitting layer (TPL) may include a third base resin (BRS3) and a scatterer (SCP) disposed within the third base resin (BSR3). The light-transmitting layer (TPL) transmits the third color blue light incident from the light-emitting element (ED) while maintaining its wavelength. The scatterer (SCP) of the light-transmitting layer (TPL) may serve to regulate the emission path of light emitted through the light-transmitting layer (TPL). The light-transmitting layer (TPL) may not contain a wavelength conversion material.

[0128] The scattering body (SCP) may be a metal oxide particle or an organic particle. Examples of the metal oxide may include titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), or tin oxide (SnO2), and examples of the organic particle material may include acrylic resin or urethane resin.

[0129] The first to third base resins (BRS1, BRS2, ​​BRS3) may include a transparent organic material. For example, the first to third base resins (BRS1, BRS2, ​​BRS3) may be composed of an epoxy resin, an acrylic resin, a cardo resin, or an imide resin. The first to third base resins (BRS1, BRS2, ​​BRS3) may all be composed of the same material, but are not limited thereto.

[0130] The first wavelength conversion material (WCP1) may be a material that converts third-color blue light into first-color red light, and the second wavelength conversion material (WCP2) may be a material that converts third-color blue light into second-color green light. The first wavelength conversion material (WCP1) and the second wavelength conversion material (WCP2) may be quantum dots, quantum rods, phosphors, etc. The quantum dots may include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI nanocrystals, or a combination thereof.

[0131] In some embodiments, the color control structures (TPL, WCL1, WCL2) may be formed through an inkjet printing process or a photoresist process. The color control structures (TPL, WCL1, WCL2) may be formed through a drying or exposure and development process after the material constituting them is sprayed or applied within the area surrounded by the first bank (BNL1). For example, in an embodiment where the color control structures (TPL, WCL1, WCL2) are formed by an inkjet printing process, the upper surface of each layer of the color control structures (TPL, WCL1, WCL2) may be formed curved in the drawings so that the edge portion adjacent to the first bank (BNL1) is higher than the center. However, it is not limited thereto. In an embodiment where the color control structure (TPL, WCL1, WCL2) is formed by a photoresist process, the upper surface of each layer of the color control structure (TPL, WCL1, WCL2) may be formed flat so that the edge portion adjacent to the first bank (BNL1) is parallel to the upper surface of the first bank (BNL1), or, unlike the drawing, the center of the color control structure (TPL, WCL1, WCL2) may be formed higher.

[0132] The light-emitting element (ED) of each subpixel (SPXn) can emit the same third color of blue light, and the light emitted from each subpixel (SPXn) can be of different colors. For example, light emitted from the light-emitting element (ED) placed in the first subpixel (SPX1) is incident on the first wavelength conversion layer (WCL1), light emitted from the light-emitting element (ED) placed in the second subpixel (SPX2) is incident on the second wavelength conversion layer (WCL2), and light emitted from the light-emitting element (ED) placed in the third subpixel (SPX3) is incident on the light-transmitting layer (TPL). The light incident on the first wavelength conversion layer (WCL1) is converted into red light, the light incident on the second wavelength conversion layer (WCL2) is converted into green light, and the light incident on the light-transmitting layer (TPL) can be transmitted as the same blue light without wavelength conversion. Even if each subpixel (SPXn) includes light-emitting elements (ED) that emit light of the same color, it can emit light of different colors depending on the arrangement of the color control structures (TPL, WCL1, WCL2) placed above it.

[0133] The first capping layer (CPL1) may be disposed on a plurality of color control structures (TPL, WCL1, WCL2) and a first bank (BNL1). The first capping layer (CPL1) can prevent impurities, such as moisture or air, from penetrating from the outside and damaging or contaminating the color control structures (TPL, WCL1, WCL2). The first capping layer (CPL1) may include an inorganic insulating material.

[0134] A low refractive index layer (LRL) can be placed on a first capping layer (CPL1). The low refractive index layer (LRL) is an optical layer that recycles light passing through color control structures (TPL, WCL1, WCL2) and can improve the light emission efficiency and color purity of the display device (10). The low refractive index layer (LRL) can be made of an organic material having a low refractive index and can compensate for the step difference formed by the color control structures (TPL, WCL1, WCL2) and the first bank (BNL1).

[0135] The second capping layer (CPL2) is placed on the low-refractive index layer (LRL) and can prevent impurities, such as moisture or air, from penetrating from the outside and damaging or contaminating the low-refractive index layer (LRL). The second capping layer (CPL2) may include an inorganic insulating material similar to the first capping layer (CPL1).

[0136] A light-blocking member (BM) may be placed on a second capping layer (CPL2). The light-blocking member (BM) may be formed in a grid pattern to partially expose one side of the second capping layer (CPL2). In a display device (10), the light-blocking member (BM) may be placed to cover sub-regions (SA) of each sub-pixel (SPXn) in addition to the lower bank layers (LBN) and the first bank (BNL1) in a plan view. The area where the light-blocking member (BM) is not placed is a light-transmitting area (TA1, TA2, TA3) where a color filter layer (CFL1, CFL2, CFL3) is placed and light is emitted, and the area where the light-blocking member (BM) is placed may be a light-blocking area (BA) where the emission of light is blocked.

[0137] The light-blocking member (BM) may be composed of an organic material capable of absorbing light. By absorbing external light, the light-blocking member (BM) can reduce color distortion caused by external light reflection. For example, the light-blocking member (BM) may be composed of a material used as a black matrix of a display device (10) and may absorb all wavelengths of visible light.

[0138] Meanwhile, in some embodiments, the display device (10) may omit the light-blocking member (BM) and replace it with a material that absorbs light of a specific wavelength among visible light wavelengths and transmits light of another specific wavelength. The light-blocking member (BM) may be replaced with a color pattern containing the same material as at least one of the color filter layers (CFL1, CFL2, CFL3). For example, a color pattern containing the material of one of the color filter layers may be placed in the area where the light-blocking member (BM) is placed, or a structure in which a plurality of color patterns are stacked may be provided.

[0139] A plurality of color filter layers (CFL1, CFL2, CFL3) may be disposed on one side of the second capping layer (CPL2). Each of the plurality of color filter layers (CFL1, CFL2, CFL3) may be disposed on the second capping layer (CPL2) in a region where the light-blocking member (BM) is open. Different color filter layers (CFL1, CFL2, CFL3) may be spaced apart from each other with the light-blocking member (BM) in between, but are not limited thereto. In some embodiments, a portion of the color filter layers (CFL1, CFL2, CFL3) may be disposed on the light-blocking member (BM) and spaced apart from each other on the light-blocking member (BM), and in another embodiment, the color filter layers (CFL1, CFL2, CFL3) may partially overlap each other.

[0140] The color filter layers (CFL1, CFL2, CFL3) may include a first color filter layer (CFL1) disposed in a first subpixel (SPX1), a second color filter layer (CFL2) disposed in a second subpixel (SPX2), and a third color filter layer (CFL3) disposed in a third subpixel (SPX3). The color filter layers (CFL1, CFL2, CFL3) may be formed as a linear pattern disposed in a plurality of light-transmitting regions (TA1, TA2, TA3) or a plurality of light-emitting regions (EMA). However, they are not limited thereto. The color filter layers (CFL1, CFL2, CFL3) may be disposed corresponding to each light-transmitting region (TA1, TA2, TA3) and may form an island-shaped pattern.

[0141] The color filter layers (CFL1, CFL2, CFL3) may include a colorant, such as a dye or pigment, that absorbs light of a wavelength other than that of a specific wavelength. The color filter layers (CFL1, CFL2, CFL3) are arranged for each subpixel (SPXn) and may transmit only a portion of the light incident from the corresponding subpixel (SPXn) to the color filter layers (CFL1, CFL2, CFL3). In each subpixel (SPXn) of the display device (10), only the light transmitted by the color filter layers (CFL1, CFL2, CFL3) may be selectively displayed. In an exemplary embodiment, the first color filter layer (CFL1) may be a red color filter layer, the second color filter layer (CFL2) may be a green color filter layer, and the third color filter layer (CFL3) may be a blue color filter layer. Lights emitted from the light-emitting element (ED) can pass through the color control structure (TPL, WCL1, WCL2) and be emitted through the color filter layer (CFL1, CFL2, CFL3).

[0142] The overcoat layer (OC) can be placed on the color filter layers (CFL1, CFL2, CFL3) and the light-blocking member (BM). The overcoat layer (OC) is placed across the entire front surface of the display area (DPA), and a portion may also be placed in the non-display area (NDA). The overcoat layer (OC) may include an organic insulating material to protect the members placed in the display area (DPA) from the outside.

[0143] A display device (10) according to one embodiment includes a color control structure (TPL, WCL1, WCL2) and a color filter layer (CFL1, CFL2, CFL3) disposed above light-emitting elements (ED), so that even if light-emitting elements (ED) of the same type are disposed for each subpixel (SPXn), different colors of light can be displayed.

[0144] For example, a light-emitting element (ED) placed in a first subpixel (SPX1) emits blue light of a third color, and said light can pass through a fourth insulating layer (PAS4) and be incident on a first wavelength conversion layer (WCL1). The first base resin (BRS1) of the first wavelength conversion layer (WCL1) is made of a transparent material, and some of said light can pass through the first base resin (BRS1) and be incident on a first capping layer (CPL1) placed above it. However, at least some of said light is incident on a scatterer (SCP) and a first wavelength conversion material (WCP1) placed within the first base resin (BRS1), and said light can be scattered and its wavelength converted to red light and be incident on the first capping layer (CPL1). Lights incident on the first capping layer (CPL1) pass through the low-refractive index layer (LRL) and the second capping layer (CPL2) and are incident on the first color filter layer (CFL1), and the first color filter layer (CFL1) can block the transmission of light other than red light. Accordingly, red light can be emitted from the first subpixel (SPX1).

[0145] Similarly, light emitted from a light-emitting element (ED) placed in a second subpixel (SPX2) can pass through a fourth insulating layer (PAS4), a second wavelength conversion layer (WCL2), a first capping layer (CPL1), a low-refractive index layer (LRL), a second capping layer (CPL2), and a second color filter layer (CFL2) and be emitted as green light.

[0146] The light-emitting element (ED) placed in the third subpixel (SPX3) emits blue light of the third color and can pass through the fourth insulating layer (PAS4) and be incident on the light-transmitting layer. The third base resin (BRS3) of the light-transmitting layer (TPL) is made of a transparent material, and some of the light can pass through the third base resin (BRS3) and be incident on the first capping layer (CPL1) placed above it. The light incident on the first capping layer (CPL1) passes through the low-refractive index layer (LRL) and the second capping layer (CPL2) and is incident on the third color filter layer (CFL3), and the third color filter layer (CFL3) can block the transmission of light other than blue light. Accordingly, blue light can be emitted from the third subpixel (SPX3).

[0147] FIG. 7 is a schematic diagram showing banks arranged in a display area and a non-display area of ​​a display device according to one embodiment. FIG. 8 is a cross-sectional view taken along the line A1-A1' of FIG. 7. FIG. 9 is a cross-sectional view taken along the line A2-A2' of FIG. 7. FIG. 7 illustrates a planar arrangement of a plurality of banks (BNL1, BNL2, BNL3) arranged in a display area (DPA) and a non-display area (NDA) of a display device (10).

[0148] FIGS. 8 and 9 illustrate cross-sections of a portion of the display area (DPA) and a non-display area (NDA) at the outer edge of a display device (10), each cut in the second direction (DR2). FIG. 8 illustrates the left outer edge, which is one side of the second direction (DR2) of the outer edge of the display device (10), and FIG. 9 illustrates the right outer edge, which is the other side of the second direction (DR2) of the outer edge of the display device (10). In FIGS. 8 and 9, a plurality of conductive layers and semiconductor layers of the display area (DPA) are simplified and illustrated as a circuit layer (CCL), and electrodes (RME), light-emitting elements (ED), and connecting electrodes (CNE), etc., disposed in each sub-pixel (SPXn) are simplified and illustrated as a light-emitting element layer (EDL). The description of these structures is the same as described above with reference to FIGS. 2 to 4.

[0149] Referring to FIG. 7 through 9 in conjunction with FIG. 6, the display device (10) may include a first bank (BNL1) comprising a portion disposed on the outer edge of a display area (DPA), a first valley portion (VA1) disposed in a non-display area (NDA) and disposed to surround the display area (DPA), a second bank (BNL2), and a third bank (BNL3).

[0150] The first bank (BNL1) may extend in the first direction (DR1) and the second direction (DR2) from the display area (DPA). For example, the first bank (BNL1) may be positioned to surround a portion where multiple pixels (PX) are arranged at the outer edge of the display area (DPA). Although only the portion of the first bank (BNL1) positioned at the outermost edge of the display area (DPA) is illustrated in FIG. 7, the first bank (BNL1) may be positioned to extend across the display area (DPA) in the first direction (DR1) or the second direction (DR2), and may also be positioned at the boundaries of each sub-pixel (SPXn). The first bank (BNL1) can distinguish between the display area (DPA) and the non-display area (NDA), and also distinguish between different sub-pixels (SPXn).

[0151] In the non-display area (NDA), a second bank (BNL2) and a third bank (BNL3) may be arranged to surround the display area (DPA) while being spaced apart from the first bank (BNL1). The second bank (BNL2) may be arranged at a certain distance from the first bank (BNL1), and the third bank (BNL3) may be arranged at a certain distance from the second bank (BNL2). That is, the display area (DPA) may be arranged inside the area surrounded by the second bank (BNL2), and the second bank (BNL2) may be arranged inside the third bank (BNL3).

[0152] As described above, the display device (10) may have a structure in which a plurality of layers are sequentially stacked on a first substrate (SUB). Some layers of the display device (10) are made of an organic material and may be formed through a process in which the organic material is directly sprayed onto the first substrate (SUB). Since the organic material has fluidity and can flow, the organic material sprayed onto the display area (DPA) may overflow into the non-display area (NDA). The second bank (BNL2) and the third bank (BNL3) can prevent the organic material from overflowing beyond the non-display area (NDA) to the outside.

[0153] A display device (10) according to one embodiment may include a first valley portion (VA1) disposed between a first bank (BNL1) and a second bank (BNL2) in a non-display area (NDA). While the second bank (BNL2) and the first bank (BNL1) have a shape protruding in an upward direction, the first valley portion (VA1) may be formed by partially sinking the lower layer. The first valley portion (VA1) can form intaglio and relief patterns together with the second bank (BNL2) and the first bank (BNL1) to prevent organic material sprayed onto the display area (DPA) from overflowing into the non-display area (NDA).

[0154] A light-emitting element layer (EDL) comprising a plurality of electrodes (RME), light-emitting elements (ED), and connecting electrodes (CNE) is disposed in the display area (DPA). The light-emitting element layer (EDL) is disposed on a via layer (VIA) in the display area (DPA), and a plurality of insulating layers (PAS_S) disposed across the display area (DPA) and the non-display area (NDA) may be disposed on the via layer (VIA). Although not explicitly shown in the drawing, the plurality of insulating layers (PAS_S) may include a first insulating layer (PAS1) disposed below the light-emitting element (ED), a second insulating layer (PAS2) disposed above the light-emitting element (ED), and a third insulating layer (PAS3). Some of the plurality of insulating layers (PAS_S) may be sequentially stacked on the via layer (VIA) in the non-display area (NDA).

[0155] A fourth insulating layer (PAS4) may also cover the light-emitting element layer (EDL) and be disposed across the display area (DPA) and the non-display area (NDA). The fourth insulating layer (PAS4) may be disposed on the light-emitting element layer (EDL) in the display area (DPA) and directly disposed on other insulating layers (PAS_S) in the non-display area (NDA).

[0156] Additionally, as a sealing structure disposed on the color control structure (WCL1, WCL2, TPL), the first capping layer (CPL1) and the second capping layer (CPL2) may also be disposed extending to the non-display area (NDA). A portion of the first capping layer (CPL1) may be disposed directly on the fourth insulating layer (PAS4), and another portion may be disposed directly on the first bank (BNL1), the second bank (BNL2), and the third bank (BNL3). The second capping layer (CPL2) is disposed on the first capping layer (CPL1) with the low-refractive index layer (LRL) in between. Unlike the display area (DPA), the low-refractive index layer (LRL) does not extend across the entire front of the non-display area (NDA), so a portion of the second capping layer (CPL2) may be disposed directly on the first capping layer (CPL1).

[0157] As described above, the low-refractive index layer (LRL) is made of an organic material and can be placed across the entire front surface of the display area (DPA). During the process of applying the organic material onto the first capping layer (CPL1), the organic material may overflow into the non-display area (NDA) beyond the first bank (BNL1) placed at the outermost part of the display area (DPA). In particular, the display device (10) may include a first substrate (SUB1) and a plurality of layers may be formed on top of it through a continuous process. During this process, the organic material that overflows into the undesirable area of ​​the non-display area (NDA) may remain as foreign matter in a subsequent process. A display device (10) according to one embodiment may include structures with intaglio and embossed pattern shapes placed in the non-display area (NDA) to prevent the organic material that overflows into the non-display area (NDA) from spreading further into the undesirable area.

[0158] The display device (10) may include a first valley portion (VA1), a second bank (BNL2), and a third bank (BNL3) disposed in a non-display area (NDA). The first valley portion (VA1) may have an intaglio pattern shape that is sunken into the lower surface relative to the upper surface of the via layer (VIA), and the second bank (BNL2) and the third bank (BNL3) may have a relief pattern shape that is protruded upward relative to the upper surface of the via layer (VIA).

[0159] The first valley portion (VA1) may surround the display area (DPA) on the plan view and be spaced apart from the first bank (BNL1). The first valley portion (VA1) may have a first width (W1) and penetrate the first via layer (VIA1), and some layers placed on the via layer (VIA) may be placed inside the first valley portion (VA1). For example, among a plurality of insulating layers (PAS_S) placed directly on the via layer (VIA), the first insulating layer (PAS1) placed below the light-emitting elements (ED) may be placed inside the first valley portion (VA1) and may also come into direct contact with the inner side wall of the first valley portion (VA1) of the via layer (VIA). A fourth insulating layer (PAS4) disposed on a plurality of insulating layers (PAS_S) in a non-display area (NDA), and a first capping layer (CPL1) with a portion directly disposed on the fourth insulating layer (PAS4) may also have a portion disposed inside the first valley portion (VA1). The plurality of insulating layers (PAS_S), the fourth insulating layer (PAS4), and the first capping layer (CPL1) may include an inorganic insulating material, and they may be disposed along the step formed by the first valley portion (VA1) in the via layer (VIA). As an inorganic insulating material such as the plurality of insulating layers (PAS_S), the fourth insulating layer (PAS4), and the first capping layer (CPL1) is disposed within the first valley portion (VA1), external moisture may be prevented from penetrating the circuit layer (CCL) exposed by the first valley portion (VA1).

[0160] The low refractive index layer (LRL) is placed on the first capping layer (CPL1), and a portion of it may be placed in the non-display area (NDA) beyond the first bank (BNL1). The low refractive index layer (LRL) may also be placed on the first valley portion (VA1), and a portion of it may be placed to fill the step formed by the first valley portion (VA1). In the process of forming the low refractive index layer (LRL), the organic material forming the low refractive index layer (LRL) may flow beyond the display area (DPA) into the non-display area (NDA) and fill the step formed by the first valley portion (VA1), and the first valley portion (VA1) may prevent the organic material from overflowing excessively. The low refractive index layer (LRL) may be placed up to the second bank (BNL2) while filling the first valley portion (VA1).

[0161] The second bank (BNL2) and the third bank (BNL3) are spaced apart from each other and can surround and be spaced apart from the first valley portion (VA1). Based on the first bank (BNL1), the first valley portion (VA1), the second bank (BNL2), and the third bank (BNL3) can be sequentially spaced apart along the direction toward the outer edge of the non-display area (NDA). Unlike the first valley portion (VA1), the second bank (BNL2) and the third bank (BNL3) may be placed directly on the fourth insulating layer (PAS4) and have a shape that protrudes in an upward direction. Since the second bank (BNL2) and the third bank (BNL3) have a raised pattern shape, the low-refractive index layer (LRL) can be prevented from overflowing to the outer edge of the non-display area (NDA).

[0162] According to one embodiment, the widths of the second bank (BNL2) and the third bank (BNL3) may be the same as each other, and the first width (W1) of the first valley portion (VA1) may be larger than the second width (W2) on the cross-sectional view of the second bank (BNL2) and the third bank (BNL3). The second bank (BNL2) and the third bank (BNL3) may be formed in the same process after forming the light-emitting element layer (EDL) and the fourth insulating layer (PAS4) in the display area (DPA). The second bank (BNL2) and the third bank (BNL3) may have the same shape and material, differing only in their position relative to each other, and in particular, the width (W2) on the cross-sectional view may be the same as each other.

[0163] The first valley (VA1) may be positioned closer to the display area (DPA) than the second bank (BNL2) and the third bank (BNL3) and may be a primary structure that prevents the overflow of the low-refractive index layer (LRL). The first valley (VA1) may have a relatively larger width than the second bank (BNL2) and the third bank (BNL3) to prevent the organic material of the low-refractive index layer (LRL) from overflowing as much as possible. The second bank (BNL2) and the third bank (BNL3) may have a relatively smaller width than the first valley (VA1), but by having a certain width and a shape of an embossed pattern, the organic material may be prevented from overflowing beyond the first valley (VA1) to the outermost edge of the non-display area (NDA).

[0164] Meanwhile, the first bank (BNL1) can also be formed in the same process as the second bank (BNL2) and the third bank (BNL3). The first bank (BNL1) may overlap with the lower bank layer (LBN) and be placed directly on the fourth insulating layer (PAS4), and may be arranged in a grid pattern on the inner side while surrounding the inner side from the outermost part of the display area (DPA). However, according to one embodiment, the third width (W3), which is the width in the cross-sectional view of the first bank (BNL1), may be equal to or smaller than the second width (W2) of the second bank (BNL2). The first bank (BNL1) can form a space in which color control structures (TPL, WCL1, WCL2) are arranged while distinguishing adjacent subpixels (SPXn) in the display area (DPA). The second bank (BNL2) and the third bank (BNL3) are structures for preventing overflow of the low-refractive index layer (LRL), and their use may differ from that of the first bank (BNL1). That is, the first bank (BNL1), the second bank (BNL2), and the third bank (BNL3) are formed in the same process as they are placed directly on the fourth insulating layer (PAS4), but their widths may differ depending on their function. As structures for preventing overflow of organic material, the second bank (BNL2) and the third bank (BNL3), which are placed in the non-display area (NDA), may have a width equal to or greater than that of the first bank (BNL1).

[0165] The overcoat layer (OC) is positioned to cover the color filter layer (CFL) and the light-blocking member (BM) in the display area (DPA), and a portion may also be positioned in the non-display area (NDA). Similar to the low-refractive index layer (LRL), the overcoat layer (OC) may also be made of an organic material, and an overflow problem may occur on the color filter layers (CFL) and the second capping layer (CPL2). A display device (10) according to one embodiment may further include color dams (CBN1, CBN2) positioned on the second bank (BNL2) and the third bank (BNL3) as a structure to prevent overflow of the overcoat layer (OC).

[0166] A plurality of color dams (CBN1, CBN2) may be placed on the second bank (BNL2) and the third bank (BNL3), respectively. A plurality of color dams (CBN1, CBN2) may be placed on either the second bank (BNL2) or the third bank (BNL3), respectively, on the left outer edge and the right outer edge, which are both sides of the second direction (DR2) of the outer edge of the display device (10). For example, a plurality of color dams (CBN1, CBN2) may include a plurality of first color dams (CBN1) placed on the second bank (BNL2) and the third bank (BNL3) of the left outer edge (shown in FIG. 8) of the display device (10), and a plurality of second color dams (CBN2) placed on the second bank (BNL2) and the third bank (BNL3) of the right outer edge (shown in FIG. 9) of the display device (10). Color dams (CBN1, CBN2) adjacent to each other at one outer side of the display device (10) are spaced apart from each other in a second direction (DR2), and each color dam (CBN1, CBN2) may be arranged to extend in a first direction (DR1) on a second bank (BNL2) or a third bank (BNL3). Multiple color dams (CBN1, CBN2) may form a linear pattern in a non-display area (NDA).

[0167] Similar to how the second bank (BNL2) and the third bank (BNL3) each prevent the low-refractive index layer (LRL) placed below the second capping layer (CPL2) from overflowing in the non-display area (NDA), the color dams (CBN1, CBN2) can prevent the overcoat layer (OC) placed above the second capping layer (CPL2) from overflowing in the non-display area (NDA). The color dams (CBN1, CBN2) are each placed directly on the second capping layer (CPL2) and may have a raised pattern with a protruding shape having a certain thickness and a certain width.

[0168] In one embodiment, the first color dam (CBN1) and the second color dam (CBN2) may each have a width measured in the second direction (DR2) that is smaller than the second width (W2) of the second bank (BNL2), and their thickness may also be smaller than that of the second bank (BNL2). The plurality of color dams (CBN1, CBN2) may have a size to prevent the material made of organic material among the layers disposed on the second capping layer (CPL2) from overflowing. The second bank (BNL2) and the third bank (BNL3) disposed below the second capping layer (CPL2) are structures to prevent the overflow of the low-refractive index layer (LRL) and the overcoat layer (OC), whereas the plurality of color dams (CBN1, CBN2) may have a relatively small size as structures to prevent the overflow of the overcoat layer (OC).

[0169] According to one embodiment, the color dam (CBN1, CBN2) may be formed in the same process by including the same material as some of the color filter layers (CFL1, CFL2, CFL3). Since the color dam (CBN1, CBN2) and the color filter layers (CFL1, CFL2, CFL3) are each placed directly on the second capping layer (CPL2), they may be formed in the same process if they include the same material. However, the color dam (CBN1, CBN2) and the color filter layers (CFL1, CFL2, CFL3) may be placed in different areas and may perform different roles, and their planar arrangements may differ. For example, the color filter layers (CFL1, CFL2, CFL3) may be placed in the light-transmitting areas (TA1, TA2, TA3) of the display device (10) and formed in a linear or island pattern, and the color dam (CBN1, CBN2) may be placed in the non-display area (NDA) and formed in a linear pattern.

[0170] According to one embodiment, a first color dam (CBN1) disposed on the left outer edge of a display device (10) may include a different material from a second color dam (CBN2) disposed on the right outer edge. The first color dam (CBN1) may include the same material as the first color filter layer (CFL1), and the second color dam (CBN2) may include the same material as the third color filter layer (CFL3). The display device (10) may have a pixel (PX) comprising a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3), which may be sequentially arranged in a second direction (DR2). In the display area (DPA) of the display device (10), a plurality of pixels (PX) are arranged in a first direction (DR1) and a second direction (DR2), and a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3) may also be repeatedly arranged in the first direction (DR1) and the second direction (DR2). When the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) placed in the display area (DPA) are arranged in equal numbers and are repeatedly arranged in the second direction (DR2), the subpixel (SPXn) placed closest to the left non-display area (NDA) of the display area (DPA) may be the first subpixel (SPX1), and the subpixel (SPXn) placed closest to the right non-display area (NDA) may be the third subpixel (SPX3). Accordingly, a first color filter layer (CFL1) may be disposed on a subpixel (SPXn) disposed closest to the left non-display area (NDA) of the display area (DPA), and a third color filter layer (CFL3) may be disposed on a subpixel (SPXn) disposed closest to the right non-display area (NDA).

[0171] As described above, a plurality of color dams (CBN1, CBN2) may be carried out in the same process by including the same material as any one of the color filter layers (CFL1, CFL2, CFL3). The first color dam (CBN1) placed on the left outer edge may include the same material as the color filter layer placed closest thereto, for example, the first color filter layer (CFL1), and the second color dam (CBN2) placed on the right outer edge may include the same material as the color filter layer placed closest thereto, for example, the third color filter layer (CFL3).

[0172] FIG. 10 is a schematic diagram showing the arrangement of a color filter layer and a color dam of a display device according to one embodiment.

[0173] Referring to FIG. 10 in conjunction with FIGS. 7 to 9, the display device (10) may have a display area (DPA) that includes a plurality of areas (AA1, AA2, AA3) and a non-display area (NDA) that includes a plurality of dam areas (DMA1, DMA2). For example, the display device (10) may include a first dam area (DMA1) located on the left side, which is one side of the second direction (DR2), and a second dam area (DMA2) located on the right side, which is the other side of the second direction (DR2), among the non-display areas (NDA). The display area (DPA) may include a plurality of areas (AA1, AA2, AA3) separated along an area where identical color filter layers (CFL1, CFL2, CFL3) are repeatedly arranged, a first area (AA1) and a second area (AA2) arranged at the outermost edge of the second direction (DR2) of the display area (DPA), and a plurality of third areas (AA3) which are inner areas between the first area (AA1) and the second area (AA2). A plurality of color filter layers (CFL1, CFL2, CFL3) may be arranged in each of the first area (AA1), the second area (AA2), and the third area (AA3), and different color dams (CBN1, CBN2) may be arranged in each of the first dam area (DMA1) and the second dam area (DMA2).

[0174] In each of the first region (AA1), the second region (AA2), and the third region (AA3), a first color filter layer (CFL1), a second color filter layer (CFL2), and a third color filter layer (CFL3) may be sequentially arranged in the second direction (DR2). Different regions (AA1, AA2, AA3) may be regions distinguished according to the regions where the repeatedly arranged color filter layers (CFL1, CFL2, CFL3) are arranged. Each region (AA1, AA2, AA3) is a region where a pair of the first color filter layer (CFL1), the second color filter layer (CFL2), and the third color filter layer (CFL3) are arranged, wherein the first region (AA1) and the second region (AA2) are regions arranged at the outermost edge of the second direction (DR2) of the display region (DPA), and the third region (AA3) may be regions arranged on the inner side.

[0175] The first dam area (DMA1) may be placed in the left non-display area (NDA) and adjacent to the first area (AA1) of the display area (DPA). The color filter layer placed on the left side of the first area (AA1) is the first color filter layer (CFL1), and the first color dams (CBN1) placed in the first dam area (DMA1) may each contain the same material as the first color filter layer (CFL1). The second dam area (DMA2) may be placed in the right non-display area (NDA) and adjacent to the second area (AA2) of the display area (DPA). The color filter layer placed on the right side of the second area (AA2) is the third color filter layer (CFL3), and the second color dams (CBN2) placed in the second dam area (DMA2) may each contain the same material as the third color filter layer (CFL3). In the manufacturing process of the display device (10), the first color dams (CBN1) placed in the first dam area (DMA1) are formed in the same process as the first color filter layer (CFL1) placed in the first area (AA1), and the second color dams (CBN2) placed in the second dam area (DMA2) can be formed in the same process as the third color filter layer (CFL3) placed in the second area (AA2).

[0176] In an exemplary embodiment, a plurality of color filter layers (CFL1, CFL2, CFL3) and color dams (CBN1, CBN2) can each be formed by a patterning process using a mask. Since the plurality of color filter layers (CFL1, CFL2, CFL3) and color dams (CBN1, CBN2) contain different materials, they can be formed through different mask processes. For example, a display device (10) can first form the first color filter layers (CFL1), then form the second color filter layers (CFL2) in another process, and then form the third color filter layers (CFL3) in yet another process.

[0177] Additionally, each color filter layer (CFL1, CFL2, CFL3) may be formed in a plurality of processes rather than a single process on the front of the display device (10). Some of the first color filter layers (CFL1) placed in the plurality of regions (AA1, AA2, AA3) of the display area (DPA) may be formed in different processes. The first color filter layers (CFL1) placed in the first region (AA1) and some of the second region (AA2) may be formed in different processes from the first color filter layers (CFL1) placed in other parts of the second region (AA2), and the first color filter layers (CFL1) placed in another second region (AA2) and the third region (AA3), respectively. Similarly, the second color filter layers (CFL2) and the third color filter layers (CFL3) placed in the plurality of regions (AA1, AA2, AA3) may be formed in different mask processes, respectively.

[0178] According to one embodiment, a plurality of color dams (CBN1, CBN2) may be formed together with the corresponding color filter layers (CFL1, CFL2, CFL3) in a mask process for forming the color filter layers (CFL1, CFL2, CFL3) located in the outermost region of the display area (DPA), among a plurality of mask processes for forming the color filter layers (CFL1, CFL2, CFL3). For example, the first color dam (CBN1) may be formed together with the first color filter layer (CFL1) in a mask process for forming the first color filter layer (CFL1) located in the first region (AA1), and the second color dam (CBN2) may be formed together with the third color filter layer (CFL3) in a mask process for forming the third color filter layer (CFL3) located in the second region (AA2).

[0179] FIG. 11 is a schematic diagram illustrating an area where a mask process is performed for forming a first color filter layer and a first color dam of a display device according to one embodiment. FIG. 12 is a schematic diagram illustrating an area where a mask process is performed for forming a second color filter layer of a display device according to one embodiment. FIG. 13 is a schematic diagram illustrating an area where a mask process is performed for forming a third color filter layer and a second color dam of a display device according to one embodiment.

[0180] Referring to FIGS. 11 to 13, a display device (10) may perform a plurality of mask processes to form different color filter layers (CFL1, CFL2, CFL3). In some of the processes for forming each color filter layer (CFL1, CFL2, CFL3), color dams (CBN1, CBN2) of dam regions (DMA1, DMA2) may be formed together with the color filter layers (CFL1, CFL2, CFL3).

[0181] A plurality of mask processes for forming a first color filter layer (CFL1) may be performed across a first dam area (DMA1) and a display area (DPA). In the plurality of mask processes, the first mask process may be performed on a first mask area (MLR1) that includes a portion of the first dam area (DMA1) and the first area (AA1). In the first mask process, the first color dams (CBN1) of the first dam area (DMA1) and the first color filter layer (CFL1) of the first area (AA1) may be formed simultaneously. Subsequent second to fourth mask processes may be performed on a second mask area (MLR2), a third mask area (MLR3), and a fourth mask area (MLR4), respectively, that include the areas where the first color filter layer (CFL1) of the other areas (AA2, AA3) excluding the first area (AA1) in the display area (DPA) is placed.

[0182] Similarly, a plurality of mask processes for forming a third color filter layer (CFL3) may be performed across a second dam area (DMA2) and a display area (DPA). In the plurality of mask processes, a fourth mask process may be performed on a fourth mask area (MLB4) that includes a portion of the second dam area (DMA2) and the second area (AA2). In the fourth mask process, the second color dams (CBN2) of the second dam area (DMA2) and the third color filter layer (CFL3) of the second area (AA2) may be formed simultaneously. The preceding first to third mask processes may be performed on a first mask area (MLB1), a second mask area (MLB2), and a third mask area (MLB3), respectively, that include the area where the third color filter layer (CFL3) of the other areas (AA1, AA3) excluding the second area (AA2) in the display area (DPA) is placed.

[0183] On the other hand, the mask process for forming the second color filter layer (CFL2) may be performed only on the display area (DPA). In the mask process, the first to third mask processes may be performed respectively on the first mask area (MLG1), the second mask area (MLG2), and the third mask area (MLG3), which include the area where the second color filter layer (CFL2) of the first area (AA1) to the third area (AA3) is placed.

[0184] In one embodiment, the mask regions where each mask process is performed may have the same area. For example, the first to fourth mask regions (MLR1, MLR2, MLR3, MLR4) where mask processes for forming the first color filter layer (CFL1) are performed may have the same width. The first to fourth mask regions (MLR1, MLR2, MLR3, MLR4) may each have a width that divides the first dam region (DMA1) and the display region (DPA) into equal intervals. Similarly, the first to fourth mask regions (MLB1, MLB2, MLB3, MLB4) where mask processes for forming the third color filter layer (CFL3) are performed may also have the same width. The first to fourth mask regions (MLB1, MLB2, MLB3, MLB4) may each have a width that divides the second dam region (DMA2) and the display region (DPA) into equal intervals. On the other hand, the first to third mask regions (MLG1, MLG2, MLG3) in which mask processes for forming the second color filter layer (CFL2) are performed may have a width that divides the display region (DPA) into equal intervals.

[0185] As described above, a plurality of color filter layers (CFL1, CFL2, CFL3) are repeatedly arranged in each region (AA1, AA2, AA3) of the display area (DPA), and mask processes for forming them can be performed on mask regions having the same width using mask layers having the same width. In addition to forming color filter layers (CFL1, CFL2, CFL3) in the display area (DPA), in order to form color dams (CBN1, CBN2) containing the same material as the color filter layers (CFL1, CFL2, CFL3) in the dam regions (DMA1, DMA2), it may be necessary to design the mask regions where each mask process is performed and the mask layers.

[0186] In the display device (10), color dams (CBN1, CBN2) placed in the first dam area (DMA1) and the second dam area (DMA2) can be formed in a process for forming different color filter layers (CFL1, CFL2, CFL3). To form different color dams (CBN1, CBN2), the process for forming the first color filter layer (CFL1) and the third color filter layer (CFL3) may involve one additional mask process than the process for forming the second color filter layer (CFL2). The display device (10) according to one embodiment can form color filter layers (CFL1, CFL2, CFL3) and color dams (CBN1, CBN2) by adding a minimum number of mask processes, thereby reducing the number of manufacturing processes.

[0187] Hereinafter, other embodiments of the display device (10) will be described with reference to other drawings.

[0188] FIG. 14 is a cross-sectional view of a display device according to another embodiment. FIG. 15 is a cross-sectional view showing the outer portion of the display device of FIG. 14.

[0189] Referring to FIGS. 14 and 15, a display device (10_1) according to one embodiment may further include a flattening layer (PNL) disposed on a second capping layer (CPL2). This embodiment differs from the embodiment of FIGS. 6 and 8 in that the display device (10_1) further includes a flattening layer (PNL). Hereinafter, descriptions of duplicate content will be omitted, and the explanation will focus on the differences.

[0190] The flattening layer (PNL) can be placed across the entire front of the display area (DPA) and non-display area (NDA) on the second capping layer (CPL2). The flattening layer (PNL) overlaps with the color control structures (TPL, WCL1, WCL2) in the display area (DPA) and can also be placed on the second bank (BNL2) and the third bank (BNL3) in the non-display area (NDA). The light-blocking members (BM), a plurality of color filter layers (CFL1, CFL2, CFL3), and color dams (CBN1, CBN2) can each be placed directly on the flattening layer (PNL).

[0191] The planarization layer (PNL), in addition to a plurality of capping layers (CPL1, CPL2) and a low-refractive index layer (LRL), protects the members disposed on the first substrate (SUB) and can partially compensate for the step difference caused by them. In particular, the planarization layer (PNL) compensates for the step difference formed by the color control structures (TPL, WCL1, WCL2) and the first bank (BNL1) below it in the display area (DPA), so that the light-blocking members (BM) and color filter layers (CFL1, CFL2, CFL3) disposed thereon can be formed on a flat surface.

[0192] FIG. 16 is a cross-sectional view showing the outer portion of a display device according to another embodiment.

[0193] Referring to FIG. 16, a display device (10_2) according to one embodiment may further include third color dams (CBN3) respectively disposed on first color dams (CBN1). This embodiment differs from the embodiment of FIG. 15 in that the display device (10_2) further includes a third color dam (CBN3) covering the first color dam (CBN1). Hereinafter, descriptions of redundant content will be omitted, and the explanation will focus on the differences.

[0194] A third color dam (CBN3) may be placed on a first color dam (CBN1). A third color dam (CBN3) may be placed on the left outer edge of the display device (10), or on the second bank (BNL2) and the third bank (BNL3) in the first dam area (DMA1). Although not shown in the drawing, a third color dam (CBN3) may also be placed extending in the first direction (DR1) from the first dam area (DMA1), and adjacent third color dams (CBN3) may be spaced apart from each other in the second direction (DR2).

[0195] The third color dam (CBN3) is formed to have a wider width than the first color dam (CBN1) so as to completely cover the outer surface of the first color dam (CBN1). However, it is not limited thereto. The third color dam (CBN3) may have the same width as the first color dam (CBN1) or a smaller width, and the third color dam (CBN3) may be placed only on the upper surface of the first color dam (CBN1). In this case, the side of the first color dam (CBN1) may be exposed.

[0196] According to one embodiment, the third color dam (CBN3) may include the same material as the second color filter layer (CFL2). Similar to the first color dam (CBN1), the third color dam (CBN3) may be formed together with the second color filter layer (CFL2) placed in the first region (AA1) during the process of forming the second color filter layer.

[0197] The second color dam (CBN2) may include a blue colorant, made of the same material as the third color filter layer (CFL3). The second color dam (CBN2) containing the blue colorant can reduce reflected light caused by external light by absorbing a portion of the reflected light from light incident from the outside. Similarly, the first color dam (CBN1) and the third color dam (CBN3) may each include a red colorant and a green colorant, made of the same material as the first color filter layer (CFL1) and the second color filter layer (CFL2), respectively. The first color dam (CBN1) and the third color dam (CBN3) may be stacked in the thickness direction to absorb a portion of reflected light caused by light incident from the outside, similar to the second color dam (CBN2) containing the blue colorant, thereby reducing reflected light caused by external light.

[0198] FIG. 17 is a schematic diagram showing the arrangement of a color filter layer and a color dam of a display device according to another embodiment. FIG. 18 and FIG. 19 are cross-sectional views showing the outer periphery of the display device of FIG. 17.

[0199] Referring to FIGS. 17 to 19, a display device (10_3) according to one embodiment may have a first color dam (CBN1) that includes the same material as the third color filter layer (CFL3), and a second color dam (CBN2) that includes the same material as the first color filter layer (CFL1). This embodiment differs from the embodiment of FIGS. 8 to 13 in that the first color dam (CBN1) and the second color dam (CBN2) include opposite materials. Hereinafter, descriptions of redundant content will be omitted and the explanation will focus on the differences.

[0200] In the embodiments of FIGS. 8 to 13, the first color dam (CBN1) may include the same material as the closest first color filter layer (CFL1) among the color filter layers (CFL1, CFL2, CFL3) of the first region (AA1), and the second color dam (CBN2) may include the same material as the closest third color filter layer (CFL3) among the color filter layers (CFL1, CFL2, CFL3) of the second region (AA2). However, this is not limited thereto, and if the first color dam (CBN1) and the second color dam (CBN2) include different materials, it is irrelevant whether they include the same material as which color filter layer (CFL1, CFL2, CFL3).

[0201] For example, the first color dam (CBN1) may include the same material as the third color filter layer (CFL3) that is most spaced out among the color filter layers (CFL1, CFL2, CFL3) of the first region (AA1), and the second color dam (CBN2) may include the same material as the first color filter layer (CFL1) that is most spaced out among the color filter layers (CFL1, CFL2, CFL3) of the second region (AA2). In the mask process for forming each color filter layer (CFL1, CFL2, CFL3) of the present embodiment, each mask region where the repeated process is performed may have the same width as each other, and color dams (CBN1, CBN2) can be formed to prevent overflow of organic material by adding a minimum number of processes. A detailed explanation thereof is the same as described above.

[0202] FIG. 20 is a cross-sectional view of a display device according to another embodiment. FIG. 21 is a cross-sectional view showing the outer portion of the display device of FIG. 20.

[0203] Referring to FIGS. 20 and 21, in one embodiment, a display device (10_4) may have a light-blocking member (BM) omitted and a plurality of color patterns (CP1, CP2, CP3) arranged therein. This embodiment differs from the embodiment of FIG. 14 in that the light-blocking member (BM) is replaced by color patterns (CP1, CP2, CP3).

[0204] The color patterns (CP1, CP2, CP3) can be formed as a grid pattern substantially identical to the light-blocking member (BM) of FIG. 14. However, the color patterns (CP1, CP2, CP3) may be formed by including the same material as the color filter layers (CFL1, CFL2, CFL3) and being integrated with them. Different color patterns (CP1, CP2, CP3) are stacked and arranged in the light-blocking area (BA), and the transmission of light can be blocked in the area where they are stacked.

[0205] The first color pattern (CP1) may be placed in a light-blocking area (BA) and may include the same material as the first color filter layer (CFL1). The first color pattern (CP1) may be placed directly on the second capping layer (CPL2) in the light-blocking area (BA), and may be integrated with the first color filter layer (CFL1) in the light-blocking area (BA) adjacent to the first light-emitting area (TA1) of the first subpixel (SPX1).

[0206] The second color pattern (CP2) may be placed in the light-blocking area (BA) and may contain the same material as the second color filter layer (CFL2). The second color pattern (CP2) may be placed directly on the first color pattern (CP1) in the light-blocking area (BA) and may be integrated with the second color filter layer (CFL2) in the light-blocking area (BA) adjacent to the second light-emitting area (TA2) of the second subpixel (SPX2). Similarly, the third color pattern (CP3) may be placed in the light-blocking area (BA) and may contain the same material as the third color filter layer (CFL3). The third color pattern (CP3) may be placed directly on the second color pattern (CP2) in the light-blocking area (BA) and may be integrated with the third color filter layer (CFL3) in the light-blocking area (BA) adjacent to the third light-emitting area (TA3) of the third subpixel (SPX3).

[0207] In the display device (10_4), the first color pattern (CP1), the second color pattern (CP2), and the third color pattern (CP3) may each be arranged to overlap with at least one of the color filter layers (CFL1, CFL2, CFL3) containing different color materials in an area overlapping with the first bank (BNL1). For example, the first color pattern (CP1) may be arranged to overlap with the second color filter layer (CFL2) and the third color filter layer (CFL3), the second color pattern (CP2) may be arranged to overlap with the first color filter layer (CFL1) and the third color filter layer (CFL3), and the third color pattern (CP3) may be arranged to overlap with the first color filter layer (CFL1) and the second color filter layer (CFL2). The area overlapping with the first bank (BNL1) can perform the function of a light-blocking member (BM) by overlapping color patterns (CP1, CP2, CP3) containing different colors and color filter layers (CFL1, CFL2, CFL3) with each other.

[0208] Each of the first color dams (CBN1) is formed in the same process as the first color pattern (CP1) and may have the same shape. The first color dams (CBN1) may have substantially the same shape as the first color pattern (CP1) placed between the second color filter layer (CFL2) and the third color filter layer (CFL3). Each of the second color dams (CBN2) is formed in the same process as the third color pattern (CP3) and may have the same shape. The second color dams (CBN2) may have substantially the same shape as the third color pattern (CP3) placed on the second color pattern (CP2).

[0209] The display device (10_4) according to the present embodiment has a structure in which a plurality of color patterns (CP1, CP2, CP3) are stacked and performs the same role as a light-blocking member (BM), thereby preventing color mixing between adjacent regions by means of a material containing different colors. In addition, since the color patterns (CP1, CP2, CP3) contain the same material as the color filter layers (CFL1, CFL2, CFL3), the external light or reflected light transmitted through the light-blocking region (BA) may have a specific color wavelength band. The eye color sensitivity perceived by the user's eyes varies depending on the color of the light, and in particular, light in the blue wavelength band may be perceived by the user less sensitively than light in the green wavelength band and light in the red wavelength band. In the light-blocking area (BA), the light-blocking member (BM) is omitted and color patterns (CP1, CP2, CP3) are arranged, thereby blocking the transmission of light and allowing the user to perceive reflected light relatively less sensitively, and absorbing a portion of the light entering from outside the display device (10) to reduce reflected light caused by external light.

[0210] FIGS. 22 and FIGS. 23 are cross-sectional views showing the outer periphery of a display device according to another embodiment.

[0211] Referring to FIG. 22, a display device (10_5) according to one embodiment may further include a plurality of bank partitions (BMW) disposed between a first bank (BNL1) and a first valley portion (VA1). The plurality of bank partitions (BMW) are structures that form an embossed pattern and can prevent the organic material of the low-refractive index layer (LRL) from overflowing together with the first bank (BNL1), the first valley portion (VA1), the second bank (BNL2), and the third bank (BNL3). This embodiment differs from the embodiment of FIG. 14 and FIG. 15 in that it further includes a plurality of bank partitions (BMW) disposed in a non-display area (NDA). Hereinafter, redundant descriptions will be omitted and the explanation will focus on the differences.

[0212] Multiple bank bulkheads (BMW) may be placed between the first bank (BNL1) and the first valley section (VA1). The first valley section (VA1) may be placed closer to the second bank (BNL2) than to the first bank (BNL1), and multiple bank bulkheads (BMW) may be placed between them to more effectively prevent the overflow of organic material.

[0213] Although not illustrated in the drawing, bank bulkheads (BMW) may be arranged to surround the first bank (BNL1) and spaced apart from it, similar to the second bank (BNL2). Different bank bulkheads (BMW) may be spaced apart from each other, and the bank bulkheads (BMW) placed on the outside may surround the bank bulkheads (BMW) placed on the inside.

[0214] Multiple bank partitions (BMW) can be formed in the same process as the second bank (BNL2). Multiple bank partitions (BMW) are placed directly on the fourth insulating layer (PAS4), and the first capping layer (CPL1) can be placed directly on the multiple bank partitions (BMW). Multiple bank partitions (BMW) are placed in the non-display area (NDA) between the first bank (BNL1) and the first valley (VA1), and can partially overlap with the light-blocking member (BM). Multiple bank partitions (BMW) can have a raised pattern shape protruding upward on the via layer (VIA) and can prevent organic materials of the low-refractive index layer (LRL) from overflowing together with the first valley (VA1).

[0215] Multiple bank bulkheads (BMW) may have a smaller width than other banks (BNL1, BNL2, BNL3). Bank bulkheads (BMW) may be placed in a relatively narrow area between the first valley section (VA1) and the first bank (BNL1). Bank bulkheads (BMW) are formed in the same process as the second bank (BNL2), but their size may be adjusted according to the space of the display device (10_5).

[0216] Referring to FIG. 23, a display device (10_6) according to one embodiment may have a first bank (BNL1), a second bank (BNL2), and a third bank (BNL3), each comprising a plurality of layers (BNL_L, BNL_U). The first bank (BNL1), the second bank (BNL2), and the third bank (BNL3) may each comprise a base layer (BNL_L) and an upper layer (BNL_U) disposed on the base layer (BNL_L). Unlike the embodiments of FIG. 8 and 9, in this embodiment, a plurality of color control structures (TPL, WCL1, WCL2) are formed by a photoresist process, and a plurality of banks (BNL1, BNL2, BNL3) may have a relatively low height.

[0217] The base layer (BNL_L) of the first bank (BNL1), the second bank (BNL2), and the third bank (BNL3) may be placed directly on the fourth insulating layer (PAS4), and the upper layer (BNL_U) may be placed directly on the base layer (BNL_L). The upper layer (BNL_U) may be formed to have a width greater than that of the base layer (BNL_L) so as to completely cover the outer surface of the base layer (BNL_L). However, it is not limited thereto. The upper layer (BNL_U) may have the same width as or a smaller width than the base layer (BNL_L), and the upper layer (BNL_U) may be placed only on the upper surface of the base layer (BNL_L). In this case, the side of the base layer (BNL_L) may be exposed.

[0218] In one embodiment, the display device (10_6) may have a structure in which color control structures (TPL, WCL1, WCL2) are formed by a photoresist process, and the first bank (BNL1), the second bank (BNL2), and the third bank (BNL3) have a stacked structure in which a base layer (BNL_L) and an upper layer (BNL_U) are stacked. Unlike the embodiments of FIGS. 8 and 9, the first bank (BNL1), the second bank (BNL2), and the third bank (BNL3) may have a relatively low height, and each layer of the color control structures (TPL, WCL1, WCL2) may have a flat upper surface. The upper surface of the color control structures (TPL, WCL1, WCL2) may be formed parallel to the upper surface of the first bank (BNL1).

[0219] FIG. 24 is a plan view showing one subpixel of a display device according to another embodiment. FIG. 25 is a cross-sectional view taken along the line N3-N3' of FIG. 24. FIG. 26 is a cross-sectional view taken along the line N4-N4' of FIG. 24.

[0220] FIG. 24 illustrates the planar arrangement of electrodes (RME; RME1, RME2, RME3, RME4), bank patterns (BP1, BP2, BP3), a lower bank layer (LBN), a plurality of light-emitting elements (ED), and connecting electrodes (CNE; CNE1, CNE2, CNE3, CNE4, CNE5) placed on one pixel (PX) of a display device (10). FIG. 25 illustrates a cross-section across both ends of light-emitting elements (ED; ED1, ED2, ED3, ED4) placed on different electrodes (RME), and FIG. 26 illustrates a cross-section across a plurality of contact portions (CT1, CT2, CT3, CT4).

[0221] Referring to FIGS. 24 to 26, a display device (10) according to one embodiment may include a larger number of electrodes (RME; RME1, RME2, RME3, RME4), bank patterns (BP1, BP2, BP3), light-emitting elements (ED; ED1, ED2, ED3, ED4), and connecting electrodes (CNE; CNE1, CNE2, CNE3, CNE4, CNE5). The display device (10) according to this embodiment differs from the embodiment of FIG. 4 in that it includes a larger number of electrodes and light-emitting elements per subpixel (SPXn). Hereinafter, redundant content will be omitted and the differences will be explained in detail.

[0222] Bank patterns (BP1, BP2, BP3) may further include a third bank pattern (BP3) positioned between the first bank pattern (BP1) and the second bank pattern (BP2). The first bank pattern (BP1) may be positioned to the left of the center of the light-emitting region (EMA), the second bank pattern (BP2) may be positioned to the right of the center of the light-emitting region (EMA), and the third bank pattern (BP3) may be positioned at the center of the light-emitting region (EMA). The third bank pattern (BP3) may have a width measured in the second direction (DR2) greater than that of the first bank pattern (BP1) and the second bank pattern (BP2). The spacing in the second direction (DR2) between each bank pattern (BP1, BP2, BP3) may be greater than the spacing between each electrode (RME). The first bank pattern (BP1) may be positioned to partially overlap with the first electrode (RME1), and the second bank pattern (BP2) may be positioned to partially overlap with the fourth electrode (RME4). The third bank pattern (BP3) may be positioned to partially overlap with the second electrode (RME2) and the third electrode (RME3). Each electrode (RME) may be positioned such that at least a portion does not overlap with the bank patterns (BP1, BP2, BP3).

[0223] A plurality of electrodes (RME) disposed for each subpixel (SPXn) may further include a third electrode (RME3) and a fourth electrode (RME4) in addition to the first electrode (RME1) and the second electrode (RME2).

[0224] The third electrode (RME3) is positioned between the first electrode (RME1) and the second electrode (RME2), and the fourth electrode (RME4) can be positioned spaced apart from the third electrode (RME3) in the second direction (DR2) with the second electrode (RME2) in between. Multiple electrodes (RME) can be sequentially positioned from the left to the right of the sub-pixel (SPXn) as the first electrode (RME1), the third electrode (RME3), the second electrode (RME2), and the fourth electrode (RME4). Each electrode (RME) can be spaced apart from each other in the second direction (DR2) and face each other. Multiple electrodes (RME) can be spaced apart from the electrodes (RME) of other sub-pixels (SPXn) adjacent in the first direction (DR1) at the separation portion (ROP) of the sub-region (SA).

[0225] Among the plurality of electrodes (RME), the first electrode (RME1) and the second electrode (RME2) each contact the lower first conductive pattern (CDP1) and the second voltage wiring (VL2) through electrode contact holes (CTD, CTS) placed below the lower bank layer (LBN), whereas the third electrode (RME3) and the fourth electrode (RME4) may not.

[0226] The first insulating layer (PAS1) may be arranged in a structure similar to the embodiments described above. The first insulating layer (PAS1) is placed over the entire display area (DPA) and may cover a plurality of electrodes (RME) and bank patterns (BP1, BP2, BP3).

[0227] A plurality of light-emitting elements (EDs) may be placed between bank patterns (BP1, BP2, BP3) or on different electrodes (RME). Some of the light-emitting elements (EDs) may be placed between the first bank pattern (BP1) and the third bank pattern (BP3), and some of the others may be placed between the third bank pattern (BP3) and the second bank pattern (BP2). According to one embodiment, the light-emitting elements (EDs) may include a first light-emitting element (ED1) and a third light-emitting element (ED3) placed between the first bank pattern (BP1) and the third bank pattern (BP3), and a second light-emitting element (ED2) and a fourth light-emitting element (ED4) placed between the third bank pattern (BP3) and the second bank pattern (BP2). The first light-emitting element (ED1) and the third light-emitting element (ED3) may be disposed on the first electrode (RME1) and the third electrode (RME3), respectively, and the second light-emitting element (ED2) and the fourth light-emitting element (ED4) may be disposed on the second electrode (RME2) and the fourth electrode (RME4), respectively. The first light-emitting element (ED1) and the second light-emitting element (ED2) may be disposed on the lower side of the light-emitting region (EMA) of the corresponding sub-pixel (SPXn) or adjacent to the sub-region (SA), and the third light-emitting element (ED3) and the fourth light-emitting element (ED4) may be disposed adjacent to the upper side of the light-emitting region (EMA) of the corresponding sub-pixel (SPXn).

[0228] However, each light-emitting element (ED) is not distinguished according to its position in the light-emitting region (EMA), but may be distinguished according to its connection relationship with the connecting electrode (CNE) described below. Depending on the arrangement structure of the connecting electrodes (CNE), the connecting electrodes (CNE) that each light-emitting element (ED) contacts at both ends may differ, and the light-emitting elements (ED) may be distinguished according to the type of connecting electrode (CNE) they contact.

[0229] A plurality of connecting electrodes (CNE) may further include a first connecting electrode (CNE1) disposed on a first electrode (RME1) and a second connecting electrode (CNE2) disposed on a second electrode (RME2), in addition to a third connecting electrode (CNE3), a fourth connecting electrode (CNE4), and a fifth connecting electrode (CNE5) disposed across a plurality of electrodes (RME).

[0230] Unlike the embodiments of FIGS. 4 to 6, the first connecting electrode (CNE1) and the second connecting electrode (CNE2) may each have a relatively short length extended in the first direction (DR1). The first connecting electrode (CNE1) and the second connecting electrode (CNE2) may be positioned below the center of the light-emitting region (EMA). The first connecting electrode (CNE1) and the second connecting electrode (CNE2) are positioned across the light-emitting region (EMA) and the sub-region (SA) of the corresponding sub-pixel (SPXn), and may make direct contact with the electrode (RME) through contact portions (CT1, CT2) formed in the sub-region (SA), respectively. The first connecting electrode (CNE1) can be in direct contact with the first electrode (RME1) through a first contact portion (CT1) that penetrates the first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) in the sub-region (SA), and the second connecting electrode (CNE2) can be in contact with the second electrode (RME2) through a second contact portion (CT2) that penetrates the first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) in the sub-region (SA).

[0231] The third connecting electrode (CNE3) may include a first extension portion (CN_E1) ​​disposed on the third electrode (RME3), a second extension portion (CN_E2) disposed on the first electrode (RME1), and a first connecting portion (CN_B1) connecting the first extension portion (CN_E1) ​​and the second extension portion (CN_E2). The first extension portion (CN_E1) ​​may be spaced apart from the first connecting electrode (CNE1) in a second direction (DR2), and the second extension portion (CN_E2) may be spaced apart from the first connecting electrode (CNE1) in a first direction (DR1). The first extension portion (CN_E1) ​​may be disposed on the lower side of the light-emitting region (EMA) of the corresponding subpixel (SPXn), and the second extension portion (CN_E2) may be disposed on the upper side of the light-emitting region (EMA). The first extension (CN_E1) ​​and the second extension (CN_E2) may be positioned within the light-emitting region (EMA). The first connection (CN_B1) may be positioned across the first electrode (RME1) and the third electrode (RME3) at the center of the light-emitting region (EMA). The third connection electrode (CNE3) generally has a shape extended in the first direction (DR1), but may have a shape that is bent in the second direction (DR2) and then extended back in the first direction (DR1).

[0232] The fourth connecting electrode (CNE4) may include a third extension part (CN_E3) disposed on the fourth electrode (RME4), a fourth extension part (CN_E4) disposed on the second electrode (RME2), and a second connecting part (CN_B2) connecting the third extension part (CN_E3) and the fourth extension part (CN_E4). The third extension part (CN_E3) may be spaced apart from the second connecting electrode (CNE2) in a second direction (DR2), and the fourth extension part (CN_E4) may be spaced apart from the second connecting electrode (CNE2) in a first direction (DR1). The third extension part (CN_E3) may be disposed on the lower side of the light-emitting region (EMA) of the corresponding subpixel (SPXn), and the fourth extension part (CN_E4) may be disposed on the upper side of the light-emitting region (EMA). The third extension (CN_E3) and the fourth extension (CN_E4) may be positioned within the light-emitting region (EMA). The second connection (CN_B2) may be positioned adjacent to the center of the light-emitting region (EMA) and across the second electrode (RME2) and the fourth electrode (RME4). The fourth connection electrode (CNE4) generally has a shape extended in the first direction (DR1), but may have a shape that is bent in the second direction (DR2) and then extended back in the first direction (DR1).

[0233] The fifth connecting electrode (CNE5) may include a fifth extension (CN_E5) disposed on the third electrode (RME3), a sixth extension (CN_E6) disposed on the fourth electrode (RME4), and a third connecting part (CN_B3) connecting the fifth extension (CN_E5) and the sixth extension (CN_E6). The fifth extension (CN_E5) may be spaced apart from the second extension (CN_E2) of the third connecting electrode (CNE3) in the second direction (DR2), and the sixth extension (CN_E6) may be spaced apart from the fourth extension (CN_E4) of the fourth connecting electrode (CNE4) in the second direction (DR2). The fifth extension (CN_E5) and the sixth extension (CN_E6) are each positioned above the light-emitting region (EMA), and the third connection (CN_B3) can be positioned across the third electrode (RME3), the second electrode (RME2), and the fourth electrode (RME4). The fifth connection electrode (CNE5) can be positioned in a shape that surrounds the fourth extension (CN_E4) of the fourth connection electrode (CNE4) in the plan view.

[0234] The third connecting electrode (CNE3) can be in direct contact with the third electrode (RME3) through a third contact portion (CT3) that penetrates the first insulating layer (PAS1) and the second insulating layer (PAS2) in the sub-region (SA), and the fourth connecting electrode (CNE4) can be in contact with the fourth electrode (RME4) through a fourth contact portion (CT4) that penetrates the first insulating layer (PAS1) and the second insulating layer (PAS2) in the sub-region (SA).

[0235] However, it is not limited thereto. In some embodiments, some of the connecting electrodes (CNE) of the display device (10) may be directly connected to the third conductive layer. For example, the first connecting electrode (CNE1) and the second connecting electrode (CNE2), which are first type connecting electrodes, may each be directly connected to the third conductive layer and may not be electrically connected to the electrode (RME). The second type connecting electrode and the third type connecting electrode may also not be electrically connected to the electrode (RME) and may be connected only to the light-emitting elements (ED).

[0236] The first connecting electrode (CNE1) and the second connecting electrode (CNE2) are each first-type connecting electrodes connected to electrodes (RME1, RME2) directly connected to the third conductive layer, and the third connecting electrode (CNE3) and the fourth connecting electrode (CNE4) are second-type connecting electrodes connected to electrodes (RME3, RME4) not connected to the third conductive layer, and the fifth connecting electrode (CNE5) may be a third-type connecting electrode not connected to the electrode (RME). The fifth connecting electrode (CNE5) is not connected to the electrode (RME) but contacts the light-emitting elements (ED) and can form an electrical connection circuit of the light-emitting elements (ED) together with other connecting electrodes (CNE).

[0237] The third connecting electrode (CNE3) and the fourth connecting electrode (CNE4), which are second-type connecting electrodes, are connecting electrodes in which the electrode extensions extending in the first direction (DR1) are not aligned with each other in the second direction (DR2), and the fifth connecting electrode (CNE5), which is a third-type connecting electrode, may be a connecting electrode in which the electrode extensions extending in the first direction (DR1) are aligned with each other in the second direction (DR2). The third connecting electrode (CNE3) and the fourth connecting electrode (CNE4) extend in the first direction (DR1) but have a bent shape, and the fifth connecting electrode (CNE5) may have a shape that surrounds a part of another connecting electrode.

[0238] Corresponding to the arrangement structure of the connecting electrodes (CNE), a plurality of light-emitting elements (ED) can be classified into different light-emitting elements (ED) depending on the connecting electrode (CNE) to which both ends contact. A first light-emitting element (ED1) and a second light-emitting element (ED2) may have their first end contacting a first type connecting electrode and their second end contacting a second type connecting electrode. The first light-emitting element (ED1) may contact the first connecting electrode (CNE1) and the third connecting electrode (CNE3), and the second light-emitting element (ED2) may contact the second connecting electrode (CNE2) and the fourth connecting electrode (CNE4). A third light-emitting element (ED3) and a fourth light-emitting element (ED4) may have their first end contacting a second type connecting electrode and their second end contacting a third type connecting electrode. The third light-emitting element (ED3) can be in contact with the third connecting electrode (CNE3) and the fifth connecting electrode (CNE5), and the fourth light-emitting element (ED4) can be in contact with the fourth connecting electrode (CNE4) and the fifth connecting electrode (CNE5).

[0239] A plurality of light-emitting elements (EDs) can be connected in series with each other through a plurality of connecting electrodes (CNE). The display device (10) according to the present embodiment includes a larger number of light-emitting elements (EDs) for each subpixel (SPXn) and can configure their serial connection, thereby further increasing the amount of light emitted per unit area.

[0240] FIG. 27 is a plan view showing one subpixel of a display device according to another embodiment. FIG. 28 is a cross-sectional view taken along the line N5-N5' of FIG. 27. FIG. 29 is a cross-sectional view taken along the line N6-N6' of FIG. 27. FIG. 30 is a cross-sectional view taken along the line N7-N7' of FIG. 27.

[0241] FIG. 27 illustrates the planar arrangement of electrodes (RME; RME1, RME2), bank patterns (BP1, BP2), a lower bank layer (LBN), a plurality of light-emitting elements (ED), and connecting electrodes (CNE; CNE1, CNE2, CNE3) placed on a pixel (PX) of a display device (10). FIG. 28 illustrates a cross-section across both ends of light-emitting elements (ED; ED1, ED2) placed on different electrodes (RME). FIG. 29 and FIG. 30 illustrate cross-sections across a plurality of electrode contact holes (CTD, CTS, CTA) and contact portions (CT1, CT2).

[0242] Referring to FIGS. 27 to 30, the structure of the electrode (RME), the connecting electrode (CNE), and the bank pattern (BP1, BP2) of the display device (10) according to one embodiment may differ from the embodiments described above. Hereinafter, details that overlap with the embodiments described above will be omitted, and the differences will be explained in detail.

[0243] Multiple bank patterns (BP1, BP2) have a shape extended in a first direction (DR1), but the widths measured in a second direction (DR2) may differ from each other, and any one bank pattern (BP1, BP2) may be placed across adjacent subpixels (SPXn) in the second direction (DR2). For example, bank patterns (BP1, BP2) may include a first bank pattern (BP1) placed within the light-emitting region (EMA) of each subpixel (SPXn), and a second bank pattern (BP2) placed across the light-emitting region (EMA) of different subpixels (SPXn).

[0244] The first bank pattern (BP1) is positioned at the center of the light-emitting region (EMA), and the second bank patterns (BP2) are positioned spaced apart from the first bank pattern (BP1). The first bank pattern (BP1) and the second bank pattern (BP2) can be positioned alternately along the second direction (DR2). Light-emitting elements (EDs) can be positioned between the first bank pattern (BP1) and the second bank pattern (BP2).

[0245] The first bank pattern (BP1) and the second bank pattern (BP2) have the same length in the first direction (DR1), but the width measured in the second direction (DR2) may be different. The portion of the lower bank layer (LBN) extended in the first direction (DR1) may overlap with the second bank pattern (BP2) in the thickness direction. The first bank pattern (BP1) may be arranged to overlap with the first electrode (RME1), and the second bank pattern (BP2) may be arranged to overlap with the electrode branch portions (RM_B1, RM_B2) of the second electrode (RME2) and the lower bank layer (LBN).

[0246] The first bank pattern (BP1) and the second bank pattern (BP2) have the same length in the first direction (DR1), but the width measured in the second direction (DR2) may be different. The portion of the lower bank layer (LBN) extended in the first direction (DR1) may overlap with the second bank pattern (BP2) in the thickness direction. The bank patterns (BP1, BP2) may be arranged as an island pattern on the front of the display area (DPA).

[0247] A plurality of electrodes (RME) include a first electrode (RME1) positioned at the center of each subpixel (SPXn) and a second electrode (RME2) positioned across different subpixels (SPXn). The first electrode (RME1) and the second electrode (RME2) generally have a shape extending in a first direction (DR1), but the shape of the portion positioned in the light-emitting region (EMA) may differ from each other.

[0248] The first electrode (RME1) is positioned at the center of the subpixel (SPXn), and the portion positioned in the light-emitting region (EMA) may be positioned on the first bank pattern (BP1). The first electrode (RME1) may extend from the sub-region (SA) in the first direction (DR1) and extend to the sub-region (SA) of another subpixel (SPXn). The first electrode (RME1) may have a shape in which the width measured in the second direction (DR2) varies depending on the position, and at least the portion overlapping with the first bank pattern (BP1) in the light-emitting region (EMA) may have a width greater than that of the first bank pattern (BP1).

[0249] The second electrode (RME2) may include a portion extending in the first direction (DR1) and portions branched out near the light-emitting region (EMA). In one embodiment, the second electrode (RME2) may include an electrode stem portion (RM_S) extending in the first direction (DR1) and a plurality of electrode branch portions (RM_B1, RM_B2) branched from the electrode stem portion (RM_S), bent into the second direction (DR2), and then extended back into the first direction (DR1). The electrode stem portion (RM_S) may be positioned to overlap with the portion extending in the first direction (DR1) of the lower bank layer (LBN) and may be positioned on one side of the second direction (DR2) of the sub-region (SA). The electrode branch portions (RM_B1, RM_B2) are branched from the electrode stem portion (RM_S) located in the portion extending in the first direction (DR1) and the portion extending in the second direction (DR2) of the lower bank layer (LBN), and can be folded toward both sides of the second direction (DR2). The electrode branch portions (RM_B1, RM_B2) are arranged across the light-emitting region (EMA) in the first direction (DR1), and can be folded again to be integrated and connected to the electrode stem portion (RM_S). That is, the electrode branch portions (RM_B1, RM_B2) of the second electrode (RME2) can be branched from the upper side and then connected to each other again from the lower side, based on the light-emitting region (EMA) of one subpixel (SPXn).

[0250] The second electrode (RME2) may include a first electrode branch (RM_B1) positioned to the left of the first electrode (RME1) and a second electrode branch (RM_B2) positioned to the right of the first electrode (RME1). The electrode branch (RM_B1, RM_B2) included in one second electrode (RME2) are each positioned in the light-emitting region (EMA) of subpixels (SPXn) adjacent to the second direction (DR2), and the electrode branch (RM_B1, RM_B2) of different second electrodes (RME2) may be positioned in one subpixel (SPXn). The first electrode branch (RM_B1) of the second electrode (RME2) may be positioned to the left of the first electrode (RME1), and the second electrode branch (RM_B2) of another second electrode (RME2) may be positioned to the right of the first electrode (RME1).

[0251] Each electrode branch (RM_B1, RM_B2) of the second electrode (RME2) may overlap with one side of the second bank pattern (BP2). The first electrode branch (RM_B1) may partially overlap with the second bank pattern (BP2) positioned to the left of the first bank pattern (BP1), and the second electrode branch (RM_B2) may partially overlap with the second bank pattern (BP2) positioned to the right of the first bank pattern (BP1). The first electrode (RME1) may be spaced apart from the different electrode branches (RM_B1, RM_B2) of the second electrode (RME2) on both sides, and the gap between the first electrode (RME1) and each electrode branch (RM_B1, RM_B2) may be smaller than the gap between the different bank patterns (BP1, BP2).

[0252] The width measured in the second direction (DR2) of the first electrode (RME1) may be larger than the width of the electrode stem portion (RM_S) and electrode branch portions (RM_B1, RM_B2) of the second electrode (RME2). The first electrode (RME1) has a width greater than that of the first bank pattern (BP1) and overlaps with both sides, whereas the second electrode (RME2) is formed with a relatively smaller width so that the electrode branch portions (RM_B1, RM_B2) overlap with only one side of the second bank pattern (BP2).

[0253] The first electrode (RME1) can contact the first conductive pattern (CDP) of the third conductive layer through the first electrode contact hole (CTD) in the portion that overlaps with the portion extended in the second direction (DR2) of the lower bank layer (LBN). The second electrode (RME2) can contact the second voltage wiring (VL2) of the third conductive layer through the second electrode contact hole (CTS) in the electrode stem portion (RM_S). The first electrode (RME1) is positioned so that the portion placed in the sub-region (SA) overlaps with the first contact portion (CT1), and the second electrode (RME2) includes the portion protruding in the second direction (DR2) from the electrode stem portion (RM_S) and the portion placed in the sub-region (SA), and can overlap with the second contact portion (CT2) in the protruding portion.

[0254] Among the first electrode (RME1) and the second electrode (RME2), the first electrode (RME1) is positioned up to the separation portions (ROP1, ROP2) of the sub-region (SA), whereas the second electrode (RME2) may not be separated from the sub-region (SA). A single second electrode (RME2) may have a shape that extends in a first direction (DR1) including a plurality of electrode stem portions (RM_S) and electrode branch portions (RM_B1, RM_B2) and is branched near the light-emitting region (EMA) of each sub-pixel (SPXn). The first electrode (RME1) may be positioned between the separation portions (ROP1, ROP2) placed in different sub-regions (SA1, SA2) of each sub-pixel (SPXn) and may be positioned across the light-emitting region (EMA).

[0255] According to one embodiment, the display device (10) may include a wiring connection electrode (EP) disposed in the first sub-region (SA1) among a plurality of sub-regions (SA1, SA2) of each sub-pixel (SPXn) and disposed between the first electrodes (RME1) of different sub-pixels (SPXn). The wiring connection electrode (EP) may not be disposed in the second sub-region (SA) of the sub-pixel (SPXn), and the first electrodes (RME1) of other sub-pixels (SPXn) adjacent in the first direction (DR1) may be spaced apart from each other. Among the plurality of sub-pixels (SPXn), the sub-pixel (SPXn) illustrated in FIG. 27 may have the first sub-region (SA1) where the wiring connection electrode (EP) is disposed placed above the light-emitting region (EMA) and the second sub-region (SA2) placed below the light-emitting region (EMA). On the other hand, for a subpixel (SPXn) of FIG. 27 and a subpixel (SPXn) adjacent to the first direction (DR1), a first sub-region (SA1) in which a wiring connection electrode (EP) is placed may be positioned below the light-emitting region (EMA), and a second sub-region (SA2) may be positioned above the light-emitting region (EMA).

[0256] A first electrode (RME1) may be spaced apart from a wiring connection electrode (EP) in a first sub-region (SA1) with a first separation part (ROP1) in between. Two first separation parts (ROP1) may be arranged in one first sub-region (SA1), and the wiring connection electrode (EP) may be spaced apart from a first electrode (RME1) placed in a corresponding sub-pixel (SPXn) with a lower first separation part (ROP1) in between, and spaced apart from a first electrode (RME1) placed in another sub-pixel (SPXn) with an upper first separation part (ROP1) in between. A second separation part (ROP2) may be arranged in a second sub-region (SA2), and different first electrodes (RME1) may be spaced apart in a first direction (DR1).

[0257] In one embodiment, the wiring connection electrode (EP) can be connected to the first voltage wiring (VL1) of the third conductive layer through a third electrode contact hole (CTA) penetrating the via layer (VIA). The first electrode (RME1) is formed in a state connected to the wiring connection electrode (EP), and an electrical signal applied to place light-emitting elements (EDs) can be applied from the first voltage wiring (VL1) to the first electrode (RME1) through the wiring connection electrode (EP). In the process of placing the light-emitting elements (EDs), a signal is applied to the first voltage wiring (VL1) and the second voltage wiring (VL2), and these can be transmitted to the first electrode (RME1) and the second electrode (RME2), respectively.

[0258] Meanwhile, the second electrode contact hole (CTS) may have a different relative arrangement with respect to the third electrode contact hole (CTA) described later. The second electrode contact hole (CTS) may be placed in the portion surrounding the second sub-region (SA2) of the lower bank layer (LBN), and the third electrode contact hole (CTA) may be placed in the first sub-region (SA1). This may be because the second electrode contact hole (CTS) and the third electrode contact hole (CTA) each expose the upper surfaces of different voltage lines (VL1, VL2), and the positions of each electrode contact hole may be determined accordingly.

[0259] The lower bank layer (LBN) may surround a light-emitting region (EMA) and a plurality of sub-regions (SA1, SA2) similar to the embodiment described above. However, in an embodiment in which the display device (10) includes sub-regions (SA1, SA2) that are distinct from each other, the regions surrounded by the lower bank layer (LBN) may be distinct from each other. The lower bank layer (LBN) is identical to the embodiment described above except that it surrounds different sub-regions (SA1, SA2).

[0260] A plurality of light-emitting elements (ED) may be placed on different electrodes (RME) between different bank patterns (BP1, BP2). A light-emitting element (ED) may include a first light-emitting element (ED1) with both ends placed on the second electrode branch (RM_B2) of the first electrode (RME1) and the second electrode (RME2), and a second light-emitting element (ED2) with both ends placed on the first electrode branch (RM_B1) of the first electrode (RME1) and the other second electrode (RME2). The first light-emitting elements (ED1) may be placed to the right of the first electrode (RME1), and the second light-emitting elements (ED2) may be placed to the left of the first electrode (RME1). First light-emitting elements (ED1) are disposed on the first electrode (RME1) and the second electrode (RME2), and second light-emitting elements (ED2) can be disposed on the first electrode (RME1) and the second electrode (RME2).

[0261] A plurality of connecting electrodes (CNE; CNE1, CNE2, CNE3) may include a first connecting electrode (CNE1), a second connecting electrode (CNE2), and a third connecting electrode (CNE3).

[0262] The first connecting electrode (CNE1) may have a shape extending in the first direction (DR1) and may be disposed on the first electrode (RME1). The portion of the first connecting electrode (CNE1) disposed on the first bank pattern (BP1) overlaps with the first electrode (RME1) and may extend from therein in the first direction (DR1) to the first sub-region (SA1) located above the light-emitting region (EMA), beyond the lower bank layer (LBN). The first connecting electrode (CNE1) may contact the first electrode (RME1) through the first contact portion (CT1) in the first sub-region (SA1).

[0263] The second connecting electrode (CNE2) may have a shape extending in the first direction (DR1) and may be disposed on the second electrode (RME2). The portion of the second connecting electrode (CNE2) disposed on the second bank pattern (BP2) overlaps with the second electrode (RME2) and may extend from therein in the first direction (DR1) to the first sub-region (SA1) located above the light-emitting region (EMA), beyond the lower bank layer (LBN). The second connecting electrode (CNE2) may contact the second electrode (RME2) through the second contact portion (CT2) in the first sub-region (SA1).

[0264] Meanwhile, in the subpixel (SPXn) of FIG. 27 and the subpixel (SPXn) adjacent to the first direction (DR1), the first connecting electrode (CNE1) and the second connecting electrode (CNE2) can contact the first electrode (RME1) and the second electrode (RME2), respectively, through contact portions (CT1, CT2) placed in the second sub-region (SA2).

[0265] The third connecting electrode (CNE3) may include extensions (CN_E1, CN_E2) extending in a first direction (DR1), and a first connecting portion (CN_B1) connecting the extensions (CN_E1, CN_E2). The first extension (CN_E1) ​​is positioned on the second electrode branch (RM_B2) of the second electrode (RME2) and faces the first connecting electrode (CNE1) within the light-emitting region (EMA), and the second extension (CN_E2) is positioned on the first electrode (RME1) and faces the second connecting electrode (CNE2) within the light-emitting region (EMA). The first connecting portion (CN_B1) may extend in a second direction (DR2) on a lower bank layer (LBN) positioned below the light-emitting region (EMA) to connect the first extension (CN_E1) ​​and the second extension (CN_E2). The third connecting electrode (CNE3) is placed on the light-emitting region (EMA) and the lower bank layer (LBN) and may not be directly connected to the electrode (RME). The second electrode branch (RM_B2) placed below the first extension (CN_E1) ​​is electrically connected to the second voltage wiring (VL2), but the second power supply voltage applied to the second electrode branch (RM_B2) may not be transmitted to the third connecting electrode (CNE3).

[0266] FIG. 31 is a cross-sectional view of a display device according to another embodiment. FIG. 32 is a cross-sectional view showing the outer portion of the display device of FIG. 31.

[0267] Referring to FIGS. 31 and 32, a display device (10_7) according to one embodiment may include an organic light-emitting element, unlike the display device (10) described above with reference to FIGS. 2 to 6. In the display device (10_6), bank patterns (BP1, BP2), a plurality of electrodes (RME), light-emitting elements (ED), and connecting electrodes (CNE) disposed on a via layer (VIA) may be replaced with other layers or electrodes. Hereinafter, details overlapping with the embodiments of FIGS. 2 to 6 will be omitted, and the explanation will focus on the differences.

[0268] The display device (10_6) may include a plurality of anode electrodes (AE1, AE2, AE3), a pixel defining film (150), an organic layer (OL), and a cathode electrode (CE) disposed on a via layer (VIA). Additionally, the display device (10_6) may include an encapsulation layer (170) disposed on the cathode electrode (CE).

[0269] A plurality of anode electrodes (AE1, AE2, AE3) may be disposed on a via layer (VIA). The first anode electrode (AE1) may be disposed in the first subpixel (SPX1), the second anode electrode (AE2) may be disposed in the second subpixel (SPX2), and the third anode electrode (AE3) may be disposed in the third subpixel (SPX3).

[0270] In some embodiments, the widths or areas of the first anode electrode (AE1), the second anode electrode (AE2), and the third anode electrode (AE3) may differ from one another. For example, the width of the first anode electrode (AE1) may be greater than the width of the second anode electrode (AE2), and the width of the second anode electrode (AE2) may be smaller than the width of the first anode electrode (AE1) but larger than the width of the third anode electrode (AE3). Alternatively, the area of ​​the first anode electrode (AE1) may be larger than the area of ​​the second anode electrode (AE2), and the area of ​​the second anode electrode (AE2) may be smaller than the area of ​​the first anode electrode (AE1) but larger than the area of ​​the third anode electrode (AE3). However, this is not limited thereto, and the area of ​​the first anode electrode (AE1) may be smaller than the area of ​​the second anode electrode (AE2), and the area of ​​the third anode electrode (AE3) may be larger than the area of ​​the second anode electrode (AE2) and the area of ​​the first anode electrode (AE1). Alternatively, depending on the case, the width or area of ​​the first anode electrode (AE1), the second anode electrode (AE2), and the third anode electrode (AE3) may be substantially the same.

[0271] The first anode electrode (AE1), the second anode electrode (AE2), and the third anode electrode (AE3) may comprise a material with high reflectivity. For example, the first anode electrode (AE1), the second anode electrode (AE2), and the third anode electrode (AE3) may be metal layers comprising metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, and Cr. In other embodiments, the first anode electrode (AE1), the second anode electrode (AE2), and the third anode electrode (AE3) may further comprise a metal oxide layer stacked on the metal layer. In exemplary embodiments, the first anode electrode (AE1), the second anode electrode (AE2), and the third anode electrode (AE3) may have a double-layer structure such as ITO / Ag, Ag / ITO, ITO / Mg, ITO / MgF, or a multilayer structure such as ITO / Ag / ITO.

[0272] A pixel defining film (150) may be disposed on a first anode electrode (AE1), a second anode electrode (AE2), and a third anode electrode (AE3). The pixel defining film (150) may include an opening that exposes the first anode electrode (AE1), an opening that exposes the second anode electrode (AE2), and an opening that exposes the third anode electrode (AE3).

[0273] In some embodiments, the pixel defining film (150) may include an organic insulating material such as an acrylic resin (polyacrylates resin), an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ethers resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0274] The organic layer (OL) may be disposed on the first anode electrode (AE1), the second anode electrode (AE2), and the third anode electrode (AE3). In some embodiments, the organic layer (OL) may have the shape of a continuous film formed across a plurality of subpixels (SPXn) and their boundaries.

[0275] A cathode electrode (CE) may be disposed on an organic layer (OL). In some embodiments, the cathode electrode (CE) may be semipermeable or permeable. When the cathode electrode (CE) is semipermeable, the cathode electrode (CE) may comprise Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, or compounds or mixtures thereof, for example, a mixture of Ag and Mg. Additionally, when the thickness of the cathode electrode (CE) is tens to hundreds of angstroms, the cathode electrode (CE) may be semipermeable.

[0276] When the cathode electrode (CE) is permeable, the cathode electrode (CE) may include a transparent conductive oxide (TCO). For example, the cathode electrode (CE) may include WxOx (tungsten oxide), TiO2 (titanium oxide), ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), MgO (magnesium oxide), etc.

[0277] A first anode electrode (AE1), an organic layer (OL), and a cathode electrode (CE) may form a first organic light-emitting diode (ED1), a second anode electrode (AE2), an organic layer (OL), and a cathode electrode (CE) may form a second organic light-emitting diode (ED2), and a third anode electrode (AE3), an organic layer (OL), and a cathode electrode (CE) may form a third organic light-emitting diode (ED3). Light emitted from each organic light-emitting diode (ED1, ED2, ED3) may be incident on a color control structure (TPL, WCL1, WCL2) above it.

[0278] The encapsulation layer (170) can be positioned to cover the third insulating layer (PAS3) and the connecting electrodes (CNE1, CNE2) on the light-emitting elements (ED). The encapsulation layer (170) is positioned over the entire surface of the first substrate (SUB) and can completely cover the members positioned on the first substrate (SUB).

[0279] The encapsulation layer (170) may include a first encapsulation layer (171), a second encapsulation layer (173), and a third encapsulation layer (175) sequentially stacked on the third insulating layer (PAS3). The first encapsulation layer (171) and the third encapsulation layer (175) may include an inorganic insulating material, and the second encapsulation layer (173) may include an organic insulating material. For example, the first encapsulation layer (171) and the third encapsulation layer (175) may each include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, silicon oxynitride (SiO₂). x N yIt may include at least one of ), lithium fluoride, etc. The second encapsulation layer (173) may include at least one of acrylic resin, methacrylate resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, and perylene resin. However, the structure and material of the encapsulation layer (170) are not limited to those described above, and the laminated structure or material may be varied in many ways.

[0280] The first bank (BNL1) and color control structures (TPL, WCL1, WCL2) may each be disposed on the encapsulation layer (170). The first bank (BNL1) may be disposed on the encapsulation layer (170) so as to overlap with the pixel definition film (150), and the color control structures (TPL, WCL1, WCL2) may be disposed on the encapsulation layer (170) within the area surrounded by the first bank (BNL1). Capping layers (CPL1, CPL2), a low-refractive index layer (LRL), a planarization layer (PNL), a light-blocking member (BM), a color filter layer (CFL), and an overcoat layer (OC) may be disposed on the first bank (BNL1) and color control structures (TPL, WCL1, WCL2) in the same manner as described above.

[0281] In an embodiment in which the display device (10_6) includes organic light-emitting elements (ED1, ED2, ED3), the second bank (BNL2) and the third bank (BNL3) of the non-display area (NDA) may each be directly disposed on the third encapsulation layer (175) of the encapsulation layer (170). The first encapsulation layer (171) may be directly disposed on the inner side wall of the first valley portion (VA1) disposed between the first bank (BNL1) and the second bank (BNL2), and the step difference caused by the first valley portion (VA1) may be filled by the second encapsulation layer (173). Additionally, some of the first capping layer (CPL1) may be directly disposed on the third encapsulation layer (175) of the encapsulation layer (170). However, it is not limited thereto.

[0282] FIG. 33 is a cross-sectional view showing the outer portion of a display device according to another embodiment.

[0283] Referring to FIG. 33, a display device (10_8) according to one embodiment may further include an upper cover layer (UCL) disposed on an overcoat layer (OC). The upper cover layer (UCL) may be disposed on the top layer of the display device (10_8) to protect the display device (10_8) from external impact or to perform an optical function for light emitted from the display device (10_8) or incident from the outside. For example, the upper cover layer (UCL) may be an optical film that prevents a decrease in visibility due to external light reflection. In an embodiment where the upper cover layer (UCL) is an optical film, the upper cover layer (UCL) may include an external shock delay film and a coating layer that protects it. The upper cover layer (UCL) may include a layer made of a cellulose resin such as triacetyl cellulose, a polyester resin, etc., but is not limited thereto.

[0284] The upper cover layer (UCL) may be placed on the overcoat layer (OC) and the display device (10_8) may be placed on the display area (DPA) and the non-display area (NDA). The upper cover layer (UCL) may have an area similar to the first substrate (SUB) in the plan view and may completely cover the display area (DPA) and the non-display area (NDA) as shown in the drawing. However, it is not limited thereto, and the upper cover layer (UCL) may cover only the display area (DPA) or cover only a part of the display area (DPA) and the non-display area (NDA).

[0285] In an embodiment where the upper cover layer (UCL) is positioned to completely cover the non-display area (NDA), a space may be formed at the bottom of the upper cover layer (UCL). The portion where the second bank (BNL2) and the third bank (BNL3) are positioned at the outermost edge of the display device (10_8) may be lower in height than the overcoat layer (OC), and a space may be formed between the upper cover layer (UCL) and the second bank (BNL2) and the third bank (BNL3). The space may be filled with a filling material, but is not limited thereto. An air layer may be formed in the space at the bottom of the upper cover layer (UCL) without being filled with a filling material.

[0286] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0287] 10: Display device SUB: Substrate RME: Electrode VIA: Via layer PAS1, PAS2, PAS3: First to third insulating layers BP1, BP2: Bank Pattern ED: Light-emitting element CNE: Connecting electrode BNL1, BNL2, BNL3: Bank TPL: Light-transmitting layer WCL1, WCL2: Wavelength conversion layer BM: Light-blocking element CFL1, CFL2, CFL3: Color filter layer CBN1, CBN2, CBN3: Color Dam

Claims

Claim 1 A first substrate comprising a display area and a non-display area surrounding the display area; a plurality of subpixels comprising a plurality of light-emitting elements disposed on the first substrate in the display area; a first bank surrounding the subpixels in the display area; a plurality of color control structures disposed within the area surrounded by the first bank on the light-emitting elements of the plurality of subpixels; a plurality of color filter layers disposed on the color control structures; a second bank disposed spaced apart from the first bank and surrounding the display area in the non-display area; A display device comprising a plurality of color dams disposed on the second bank, wherein the color dams include a first color dam disposed on a portion disposed on the first side of the display area of ​​the second bank, and a second color dam disposed on a portion disposed on the second side opposite to the first side of the display area of ​​the second bank, wherein the first color dam and the second color dam comprise different materials, and further comprising a first capping layer disposed on the color control structures, the first bank and the second bank; a low-refractive index layer disposed on the first capping layer; and a second capping layer disposed on the low-refractive index layer, wherein the first color dam and the second color dam are disposed on the second capping layer. Claim 2 A display device according to claim 1, wherein the subpixel comprises a first subpixel and a second subpixel spaced apart from the first subpixel in one direction, the color control structure comprises a first wavelength conversion layer disposed on the first subpixel and a light-transmitting layer disposed on the second subpixel, and the color filter layer comprises a first color filter layer disposed on the first wavelength conversion layer and a second color filter layer disposed on the light-transmitting layer. Claim 3 A display device according to claim 2, wherein the first color dam and the second color dam are spaced apart in one direction with the display area in between, and the first color dam includes the same material as the first color filter layer and the second color dam includes the same material as the second color filter layer. Claim 4 A display device according to claim 3, wherein the subpixel further comprises a third subpixel disposed between the first subpixel and the second subpixel, the color control structure further comprises a second wavelength conversion layer disposed on the third subpixel, the color filter layer further comprises a third color filter layer disposed on the second wavelength conversion layer, and further comprises a third color dam disposed on the first color dam and comprising the same material as the third color filter layer. Claim 5 A display device according to claim 4, wherein the width of the third color dam is greater than the width of the first color dam, and the outer surface of the first color dam is covered by the third color dam. Claim 6 A display device according to claim 4, further comprising a plurality of color patterns arranged to overlap with the first bank, wherein the color patterns include a first color pattern comprising the same material as the first color filter layer, a second color pattern comprising the same material as the second color filter layer, and a third color pattern comprising the same material as the third color filter layer, wherein the first color pattern is arranged to overlap with the second color filter layer and the third color filter layer, respectively. Claim 7 A display device according to claim 2, wherein the first color dam and the second color dam are spaced apart in one direction with the display area in between, the first color dam includes the same material as the second color filter layer, and the second color dam includes the same material as the first color filter layer. Claim 8 delete Claim 9 A display device according to claim 1, further comprising a flattening layer disposed between the second capping layer and the color filter layer, wherein the first color dam and the second color dam are each directly disposed on the flattening layer on the second bank. Claim 10 A display device according to claim 9, further comprising: a light-blocking member disposed on the flattening layer and overlapping with the first bank; and an overcoat layer disposed on the light-blocking member and the color filter layer. Claim 11 A display device according to claim 1, comprising: a via layer disposed on the first substrate in the display area and the non-display area; a third bank disposed on the via layer and spaced apart from the second bank in the non-display area to surround the second bank; and a first valley portion disposed between the first bank and the second bank in the non-display area and penetrating the via layer. Claim 12 A display device according to claim 11, wherein the first color dams are arranged in plurality and each is placed on the portion on the first side of the display area among the second bank and the third bank, and the second color dams are arranged in plurality and each is placed on the portion on the second side of the display area among the second bank and the third bank. Claim 13 A display device according to claim 11, further comprising a plurality of bank partitions directly disposed on the via layer between the first bank and the first valley portion. Claim 14 A display device according to claim 1, wherein the first bank and the second bank each comprise a base layer and an upper layer disposed on the base layer, and the upper layer has a width greater than that of the base layer. Claim 15 A display device according to claim 1, wherein the subpixels include a plurality of electrodes that extend in one direction and are spaced apart from each other, and the plurality of light-emitting elements are disposed on the plurality of electrodes spaced apart from each other. Claim 16 In claim 1, the light-emitting element comprises a first electrode disposed on the first substrate, an organic layer disposed on the first electrode, and a second electrode disposed on the organic layer. Claim 17 A display area, and a non-display area surrounding the display area; a plurality of subpixels disposed in the display area and arranged in a first direction and a second direction intersecting the first direction, comprising a first electrode, a second electrode spaced apart from the first electrode, and a plurality of light-emitting elements having both ends placed on the first electrode and the second electrode; a first bank disposed extending in the display area in the first direction and the second direction and surrounding the subpixels; a plurality of color control structures disposed within the area surrounded by the first bank; a plurality of color filter layers disposed on the color control structures; a first valley portion disposed in the non-display area spaced apart from the first bank and surrounding the first bank; a second bank disposed in the non-display area spaced apart from the first valley portion and surrounding the first valley portion; a third bank disposed in the non-display area spaced apart from the second bank and surrounding the second bank; A display device comprising: a plurality of first color dams arranged extending in the first direction from a first dam area arranged on one side of the second direction of the display area among the non-display areas; and a plurality of second color dams arranged extending in the first direction from a second dam area arranged on the other side of the second direction of the display area among the non-display areas, wherein the first color dam and the second color dam include different materials. Claim 18 A display device according to claim 17, wherein the plurality of first color dams are arranged to overlap with the second bank and the third bank respectively placed in the first dam area, and the plurality of second color dams are arranged to overlap with the second bank and the third bank respectively placed in the second dam area. Claim 19 A display device according to claim 17, wherein the color filter layer comprises a plurality of first color filter layers, a plurality of second color filter layers spaced apart from each of the plurality of first color filter layers in the second direction, and a plurality of third color filter layers spaced apart from each of the plurality of second color filter layers in the second direction, wherein the first color filter layer, the second color filter layer, and the third color filter layer are each alternately arranged along the second direction, and the first color dam comprises the same material as the third color filter layer and the second color dam comprises the same material as the first color filter layer. Claim 20 A display device according to claim 19, further comprising a third color dam disposed on the second color dam and including the same material as the second color filter layer.

Images