Electronic device including host connector and memory device

Abstract

An electronic device comprising a host connector and a memory device is provided. The host connector includes a connector hole in which a memory connector is received, on which a connection terminal of the memory device is disposed, and a connector pin disposed within the connector hole and electrically connected to the connection terminal of the memory connector. The connector pin includes a first conductor portion comprising a conductor, a second conductor portion comprising a conductor and bent in a direction closer to the connection terminal from the first conductor portion when the memory connector is received in the connector hole, and a stub comprising an insulator and bent in a direction away from the connection terminal from the second conductor portion when the memory connector is received in the connector hole.

Description

Technology Field

[0001] The present invention relates to an electronic device comprising a host connector and a memory device. Background Technology

[0002] Memory devices, represented by SSDs (Solid State Drives), are widely used not only in traditional electronic devices such as desktop PCs, tablet PCs, and laptop PCs, but also in electronic devices related to mobility, such as automobiles, drones, and aircraft. Electronic devices can be exposed to various environments. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a host connector with improved signal integrity (SI) performance.

[0004] Another problem that the present invention aims to solve is to provide a memory device with improved SI performance.

[0005] Another problem that the present invention aims to solve is to provide an electronic device with improved SI performance.

[0006] The problems of the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0007] A host connector according to one embodiment for solving the above problem includes a connector hole in which a memory connector having a connection terminal of a memory device is accommodated, and a connector pin disposed within the connector hole and electrically connected to the connection terminal of the memory connector. The connector pin includes a first conductor portion comprising a conductor, a second conductor portion comprising a conductor and bent in a direction closer to the connection terminal from the first conductor portion when the memory connector is accommodated in the connector hole, and a stub comprising an insulator and bent in a direction further away from the connection terminal from the second conductor portion when the memory connector is accommodated in the connector hole.

[0008] A memory device according to one embodiment for solving the above other problems comprises a module board, a memory module including a memory connector disposed on one side of the module board and having a connection terminal disposed thereon and electrically connected to a host connector, a first enclosure disposed on the upper side of the memory module, and a second enclosure disposed on the lower side of the memory module, wherein the connection terminal includes a first region including an insulator and a second region including a conductor, and when the memory connector is electrically connected to the host connector, the first region is adjacent to the host connector compared to the second region.

[0009] An electronic device according to one embodiment for solving the above-mentioned other problem comprises a host connector including a connector pin and a memory connector including a connection terminal electrically connected to the connector pin of the host connector, wherein the connector pin includes a first conductor portion including a conductor, a second conductor portion including a conductor and bent in a direction approaching the connection terminal from the first conductor portion, and a stub including an insulator that is bent in a direction away from the connection terminal from the second conductor portion, and the connection terminal includes a first region including an insulator and a second region including a conductor, and the second conductor portion and the second region are electrically connected so that the host connector and the memory connector are electrically connected.

[0010] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0011] FIG. 1 is a block diagram of an electronic device according to some embodiments. FIG. 2 is a perspective view of a memory device of an electronic device according to some embodiments. Figure 3 is an exploded perspective view of the memory device shown in Figure 2. Figure 4 is a cross-sectional view of the memory device of Figure 2 cut along the first direction. Figure 5 is a plan view of a memory module included in the memory device of Figure 2. FIG. 6 is a partial perspective view of the memory connector of the memory device shown in FIG. 2. Figure 7 is an enlarged view of the connection terminal of Figure 6. FIG. 8 is a perspective view of a host connector of a host of an electronic device according to some embodiments. Figure 9 is a cross-sectional view of Figure 8. Figure 10 is an enlarged view of the connector pins of Figure 9. FIG. 11 is a perspective view showing the state in which a memory device is connected to a host. FIG. 12 is a perspective view showing the state of the memory device before it is connected to the host. FIG. 13 is a cross-sectional view showing the process of connecting a memory connector to a host connector. Figure 14 is a diagram illustrating the form in which connector pins and connection terminals are connected. FIGS. 15 and 16 are drawings for explaining the effects of a memory device according to some embodiments. Figure 17 is an enlarged view of the connection terminal of the memory connector. Figure 18 is a diagram illustrating the form in which connector pins and connection terminals are connected. Figure 19 is an enlarged view of the connector pins of the host connector. Figure 20 is an enlarged view of the connection terminal of the memory connector. Figure 21 is a diagram illustrating the form in which connector pins and connection terminals are connected. Figure 22 is an enlarged view of the connector pins of the host connector. FIG. 23 is a diagram illustrating the form in which connector pins and connection terminals are connected. Figure 24 is a diagram illustrating the form in which connector pins and connection terminals are connected. Figure 25 is a diagram illustrating the form in which connector pins and connection terminals are connected. Specific details for implementing the invention

[0012] Hereinafter, various embodiments of the present invention will be described with reference to the attached drawings.

[0013] FIG. 1 is a block diagram of an electronic device according to some embodiments.

[0014] Referring to FIG. 1, the memory system includes a host (20) and a memory device (10). The host (20) and the memory device (10) can communicate through a predetermined interface. The interface may be, for example, UFS (Universal Flash Storage), SAS (Serial Attached SCSI), SATA (Serial Advanced Technology Attachment), PCIe (Peripheral Component Interconnect Express), eMMC (embedded MultiMediaCard), FC (Fibre Channel), ATA (Advanced Technology Attachment), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), IEEE 1394 (Firewire), etc., but is not limited thereto.

[0015] The host (20) controls the overall operation of the memory device (10). The host (20) may include an application (21), a driver (22), a host controller (23), a buffer memory (26), and a host interface (24).

[0016] The application (21) can control the electronic device based on a set of instructions that can be used in the electronic device. The application (21) may support, for example, a SCSI (Small Computer System Interface) instruction set, but is not limited thereto.

[0017] The driver (22) can drive the memory device (10) connected to the host (20). Specifically, the driver (22) can receive a command to control the memory device (10) from an application (21), process the command using a host controller (23), and then provide the processing result to the application (21).

[0018] The application (21) and driver (22) may be implemented as software or firmware, but are not limited thereto.

[0019] The host controller (23) controls the overall operation within the host (20). For example, the host controller (23) can transmit data stored in the buffer memory to the memory device (10) via the host interface (24) in response to a write command received from the driver (22). Additionally, the host controller (23) can receive data from the memory device (10) via the host interface (24) in response to a read command received from the driver (22).

[0020] The buffer memory (26) can be used as the main memory of the host (20), or as a cache memory or temporary memory for temporarily storing data. Additionally, the buffer memory (26) can be used as a driving memory for running software such as an application (21) or a driver (22). The buffer memory (26) may include volatile memory, such as Dynamic Random Access Memory (DRAM), for example, but is not limited thereto.

[0021] The host interface (24) can exchange data with the memory device interface (14) of the memory device (10) through data lines (DIN, DOUT). The data lines (DIN, DOUT) can be connected between the host (20) and the memory device (10) by connecting the host connector and the memory device connector. A detailed description of the connection structure between the host connector and the memory device connector will be provided later.

[0022] The memory device (10) may include a memory device interface (14), a memory controller (13), and a memory (15). The memory device (10) may be connected to a host (20) through the memory device interface (14).

[0023] The memory controller (13) can perform operations to write, read, or erase data requested by the host (20) to the memory (15).

[0024] The buffer memory (16) may be used to temporarily store data to be stored in memory (15) or data read from memory (15). The buffer memory (16) may include, for example, volatile memory including Dynamic Random Access Memory (DRAM), but is not limited thereto.

[0025] The memory (15) may include non-volatile memory such as flash memory, magnetoresistive random access memory (MRAM), phase-change random access memory (PRAM), and ferroelectric random access memory (FeRAM). In the following embodiments, the memory device (10) is exemplified as a solid state drive (SSD) including flash memory, but applicable embodiments are not limited thereto.

[0026] The memory system described above may be embedded in or installed within various electronic devices. An electronic device is a device that includes electronic devices or electronic components, and examples include desktop PCs, tablet PCs, laptop PCs, netbook computers, workstations, servers, PDAs, mobile phones, smartphones, video phones, e-book readers, MP3 players, digital cameras, televisions, projectors, game consoles, navigation devices, robots, and global navigation satellite systems (GNSS), as well as medical devices, washing machines, refrigerators, etc. that include electronic devices. In addition, automobiles, drones, aircraft, ships, satellites, etc., may also be referred to as electronic devices insofar as they include electronic devices or electronic components.

[0027] FIG. 2 is a perspective view of a memory device of an electronic device according to some embodiment. FIG. 3 is an exploded perspective view of the memory device shown in FIG. 2. FIG. 4 is a cross-sectional view of the memory device of FIG. 2 taken along a first direction. FIG. 5 is a plan view of a memory module included in the memory device of FIG. 2. FIG. 6 is a partial perspective view of a memory connector of the memory device shown in FIG. 2. FIG. 7 is an enlarged view of the connection terminal of FIG. 6. FIG. 8 is a perspective view of a host connector of a host of an electronic device according to some embodiment. FIG. 9 is a cross-sectional view of FIG. 8. FIG. 10 is an enlarged view of the connector pin of FIG. 9.

[0028] Referring to FIG. 2, the exterior of the memory device (10) has a substantial rectangular shape. If the surface having the largest area in the rectangular prism is defined as the base, the memory device (10) may have a rectangular base.

[0029] In the drawing, the direction of the long side of the rectangular base is indicated as the first direction (X), the direction of the short side is indicated as the second direction (Y), and the direction of the thickness of the rectangular prism is indicated as the third direction (Z). The planes defined by the two directions may be referred to as the XY plane, the YZ plane, and the ZX plane, respectively. Based on these criteria, the base of the memory device (10) lies on the XY plane. Unless otherwise specifically stated in this specification, the planar shape or planar appearance of a specific member refers to the shape of the specific member lying on the XY plane.

[0030] The appearance of the memory device (10) may conform to a standardized or arbitrary form factor. The dimensions of the rectangular memory device (10) may also be changed according to various standards.

[0031] Referring to FIGS. 2 through 10, the memory device (10) includes a memory module (110) and an enclosure assembly (120) that houses the memory module (110). The enclosure assembly (120) can substantially define the exterior of the memory device (10). The memory module (110) may be covered by the enclosure assembly (120), except for a portion such as an area where a memory connector (MCN) is located.

[0032] Referring to FIGS. 2 to 10, the memory module (110) may include a module board (BDH), a memory connector (MCN) provided at least one end of the module board (BDH), and an electronic component (CHP) disposed on at least one surface of the module board (BDH).

[0033] The module board (BDH) may include one or more insulating layers and wiring layers. The module board (BDH) may include a printed circuit board.

[0034] The module board (BDH) may be formed in a plate-like shape. The module board (BDH) may generally be placed on an XY plane. The overall planar shape of the module board (BDH) may be similar to the planar shape of the memory device (10). For example, if the memory device (10) has a rectangular or similar appearance in plan view, the module board (BDH) may also have a rectangular or similar appearance.

[0035] The size of the planar module board (BDH) is smaller than the size of the memory device (10), but can be approximate.

[0036] In the plan view, the module board (BDH) occupies the central part of the memory device (10), and each side of the module board (BDH) may be located inward from each corresponding side of the memory device (10). Except for some sections, an enclosure assembly (120) is placed in the space between each side of the module board (BDH) and each side of the memory device (10) to prevent external exposure of the module board (BDH).

[0037] A memory connector (MCN) may be disposed on one end of the module board (BDH). Although the drawing illustrates a case where the memory connector (MCN) is connected to a first side (SS1) of the module board (BDH) and protrudes outward in a first direction (X) from the first side (SS1) of the module board (BDH), it is not limited thereto and may be disposed on other sides or on multiple sides.

[0038] The width of the second direction (Y) of the memory connector (MCN) may be smaller than the width of the second direction (Y) of the module board (BDH). Additionally, the memory connector (MCN) may be positioned spaced apart from the extension of the first long side (LS1) and / or the extension of the second long side (LS2) of the module board (BDH). The memory connector (MCN) may be positioned so as to be more oriented toward the first long side (LS1) than toward the second long side (LS2) overall. That is, the distance between the memory connector (MCN) and the extension of the first long side (LS1) of the module board (BDH) may be smaller than the distance between the memory connector (MCN) and the extension of the second long side (LS2) of the module board (BDH). However, it is not limited thereto, and the memory connector (MCN) may be positioned at an equal distance from the long sides of the module board (BDH).

[0039] The memory connector (MCN) is connected to the module board (BDH). The memory connector (MCN) may be provided as a separate component from the module board (BDH) and attached to the module board (BDH), or it may be provided integrally with the module board (BDH). If the memory connector (MCN) is provided integrally with the module board (BDH), the memory connector (MCN) may be provided in a protruding area of ​​the module board (BDH) that protrudes outwardly from a portion of the module board (BDH).

[0040] The memory connector (MCN) may include connection terminals (160). The connection terminals (160) may be spaced apart along the second direction (Y). The connection terminals (160) of the memory connector (MCN) may be connected to the connector pins (220) of the corresponding host connector (200). A detailed description of the connection between the memory connector (MCN) and the host connector (200) will be provided later.

[0041] The connection terminal (160) includes a first area (161) and a second area (162).

[0042] The first region (161) includes an insulator, and the insulator may be, for example, either a non-metal or a polymer.

[0043] The second region (162) includes a conductor, and the conductor may be a metal including, for example, cobalt (Co), tungsten (W) and / or copper (Cu).

[0044] In some embodiments, the first region (161) and the second region (162) may be bonded together using a predetermined adhesive material. Additionally, in some embodiments, the first region (161) and the second region (162) may be formed integrally using a die casting method in which a conductor and an insulator are injected into a mold shaped like the first region (161) and the second region (162).

[0045] In some embodiments, the length (c) of the first region (161) may be greater than the length (d) of the second region (162).

[0046] Additionally, in some embodiments, the ratio of the length (c) of the first region (161) to the length (d) of the second region (162) may be, for example, 3:2 to 4:1. Thus, when the ratio of the length (c) of the first region (161) to the length (d) of the second region (162) is 3:2 to 4:1, signal integrity can be improved while maintaining the reliability of the electrical connection between the connector pin (220) of the host connector (200) and the connection terminal (160) of the memory connector (MCN). This will be described later.

[0047] In addition, in some embodiments, the ratio of the total length (c+d) of the connection terminal (160) to the length (c) of the first region (161) may be, for example, 0.64 to 0.77. A detailed explanation regarding this will also be provided later.

[0048] The connection terminal (160) of the memory connector (MCN) can be connected to the wiring of the module board (BDH). When the memory connector (MCN) is provided integrally with the module board (BDH), the connection terminal (160) of the memory connector (MCN) can be formed on the same layer using the same material as the wiring of the module board (BDH). The connection terminal (160) may have the shape of a pad electrode that is wider than the wiring of the module board (BDH). The connection terminal (160) may be exposed to the outside without being covered by at least partially an insulating layer. The connection terminal (160) may be placed on the upper surface of the memory connector (MCN) or on the lower surface. In some cases, the connection terminal (160) may be placed on both the upper and lower surfaces of the memory connector (MCN). Furthermore, the memory connector (MCN) may include a plurality of layers separated in the thickness direction, and the connection terminal (160) may be placed on at least one surface of each layer.

[0049] The size, shape, location, and arrangement of connection terminals (160) of the memory connector (MCN) described above may conform to a set standard. For example, the size, shape, location, and arrangement of connection terminals (160) of the memory connector (MCN) may correspond to standards such as E1.S, M.2, NF2, etc.

[0050] An electronic component (CHP) is disposed on the upper and / or lower surface of the module board (BDH). The electronic component (CHP) can be manufactured as a chip separate from the module board (BDH) and mounted on the module board (BDH).

[0051] The electronic components (CHP) may include semiconductor components. The semiconductor components may include memory such as NAND flash memory or DRAM memory and a memory controller that controls the memory. The electronic components (CHP) may further include capacitor components. Each electronic component (CHP) may be connected to the wiring of the module board (BDH) to perform electrical operations. Multiple electronic components (CHP) may be spaced apart from each other.

[0052] Referring to FIGS. 2 through 10, the enclosure assembly (120) has a generally hollow rectangular shape. A memory module (110) is housed inside the enclosure assembly (120). The enclosure assembly (120) can serve as a housing.

[0053] At a location corresponding to the side of the memory device (10), the enclosure assembly (120) may include a connector opening (COP) that exposes a memory connector (MCN) in a first direction (X).

[0054] The enclosure assembly (120) may be provided by assembling multiple parts. Specifically, the enclosure assembly (120) may include a first enclosure (121) located at the top and a second enclosure (122) located at the bottom. The first enclosure (121) and the second enclosure (122) may be joined together to define a space that is at least partially sealed. A memory module (110) may be housed within the sealed space.

[0055] The first enclosure (121) and the second enclosure (122) may each be made of a metal such as stainless steel, aluminum (Al), copper (Cu), titanium (Ti), nickel (Ni), or an alloy containing these, or may be made of a polymer material, a carbon-based material, or a composite material in which these are combined.

[0056] The materials of the first enclosure (121) and the second enclosure (122) may be the same or different.

[0057] The first enclosure (121) and the second enclosure (122) may each include a bottom cover corresponding to the bottom surface of the enclosure assembly (120).

[0058] The first enclosure (121) may further include at least one clamping hole (CLH) penetrating the first main cover (CVU). The clamping hole (CLH) provides a space into which a hook (211) of the host connector (200) is inserted when connected to the host connector (200). The clamping hole (CLH) may be positioned adjacent to the first short side (SS1) of the first main cover (CVU).

[0059] The clamping hole (CLH) may be positioned overlapping with the memory connector (MCN). The clamping hole (CLH) may have a rectangular shape in which the second direction (Y) in the plan view is the longer side.

[0060] The number of clamping holes (CLH) may correspond to the number of hooks (211) of the host connector (200). If the host connector (200) includes two hooks (211), the number of clamping holes (CLH) may also be two.

[0061] Referring to FIGS. 2 to 10, the memory device (10) may have a sealed structure in which the memory module (110) is completely enclosed through the first enclosure (121) and the second enclosure (122), except for the side where the memory connector (MCN) is placed.

[0062] The side of the memory device (10) where the memory connector (MCN) is located can be substantially sealed by the host connector (200) described later.

[0063] The structure of the host connector (200) is described below.

[0064] Referring to FIGS. 2 through 10, the host (20) may include a host connector (200) and a system board (SBD).

[0065] The system board (SBD) may include a printed circuit board (PCB). The host connector (200) may be fixed to the system board (SBD). Although the drawing shows the host connector (200) being fixed to the system board (SBD) via screws, the method of fixation is not limited to that illustrated. The host connector (200) and the system board (SBD) may be electrically connected.

[0066] The host connector (200) may include a connector body (HB), a connector pin (220) installed within the connector body (HB), and a latch (210) installed on the upper surface of the connector body (HB).

[0067] A connector hole (COH) for accommodating a memory connector (MCN) is disposed within the connector body (HB).

[0068] The horizontal width of the connector hole (COH) is greater than or equal to the horizontal width of the memory connector (MCN) of the memory device (10), thereby providing space to accommodate the memory connector (MCN). A connector pin (220) may be placed inside the connector hole (COH) of the memory device (10). When the memory connector (MCN) of the memory device (10) is inserted into the connector hole (COH), the connection terminal (160) of the memory connector (MCN) and the connector pin (220) of the host connector (200) are electrically connected to each other, thereby interconnecting the memory device (10) and the host. For complete airtightness, at least some or all of the sides of the memory connector (MCN) inserted into the connector hole (COH) may come into contact with the inner wall of the connector hole (COH), but are not limited thereto.

[0069] The connector pin (220) may include a conductor. Such a conductor may include, for example, copper, tungsten, etc.

[0070] It may include a latch body (210_BD) and one or more hooks (211) disposed at the ends of the latch body (210_BD). The number and size of the hooks (211) may correspond to the number and size of the clamping holes (CLH) of the memory device (10).

[0071] The latch (210) can be coupled to the connector body (HB) by a joint (212). The joint (212) may include a spring. The spring has a restoring force so that even if the latch (210) is lifted up by an external force, it can be lowered back to its original position when the external force is removed.

[0072] FIG. 11 is a perspective view showing the state in which a memory device is connected to a host. FIG. 12 is a perspective view showing the state before the memory device is connected to the host. FIG. 13 are cross-sectional views showing the process of connecting a memory connector to a host connector. FIG. 14 is a drawing showing the form in which a connector pin and a connection terminal are connected. FIG. 15 and FIG. 16 are drawings for explaining the effects of a memory device according to some embodiments.

[0073] Referring to FIGS. 11 through 14, the latch (210) of the host connector (200) before being connected to the memory device (10) is positioned such that the latch body (210_BD) faces horizontally and the hook (211) faces downward. With respect to the memory device (10) being inserted, the hook (211) is positioned at a height lower than the first main cover (CVU) of the first enclosure (121).

[0074] To connect, the memory device (10) is pushed into the front of the host connector (200). At this time, the memory connector (MCN) is inserted into the connector hole (COH). Through this connection process, the connector pin (220) is electrically connected to the connection terminal (160).

[0075] In this embodiment, as described above, by making the ratio of the length (c) of the first region (161) of the connection terminal (160) and the length (d) of the second region (162) to be, for example, 3:2 to 4:1, signal integrity can be improved while maintaining the reliability of the electrical connection between the connector pin (220) and the connection terminal (160).

[0076] For example, as illustrated in FIG. 15, if the ratio of the length (c) of the first region (161) of the connection terminal (160) to the length (d) of the second region (162) is different from 3:2, for example, 1:4, the electrical connectivity between the connector pin (220) and the connection terminal (160) is good, but the length of the first region (161) made of an insulator becomes excessively short, and the signal integrity improvement effect may be reduced.

[0077] Conversely, as illustrated in FIG. 16, if the ratio of the length (c) of the first region (161) of the connection terminal (160) to the length (d) of the second region (162) is different from 4:1, for example, 5:1, the connector pin (220) may come into contact with the first region (161) of the connection terminal (160) which is made of an insulator, and the connection terminal (160) and the connector pin (220) may not be electrically connected.

[0078] According to this principle, in this embodiment, by maintaining the ratio of the total length (c+d) of the connection terminal (160) to the length (c) of the first region (161) to, for example, 0.64 to 0.77, signal integrity can be improved while maintaining the reliability of the electrical connection between the connector pin (220) and the connection terminal (160).

[0079] Hereinafter, electronic devices according to several other embodiments will be described with reference to FIGS. 17 to 20.

[0080] FIG. 17 is an enlarged view of the connection terminal of the memory connector. FIG. 18 is a diagram illustrating the configuration in which the connector pins and the connection terminal are connected. Below, the description of configurations identical to the previously described embodiment will be omitted, and the differences will be explained in detail.

[0081] Referring to FIG. 17, the connection terminal (160a) includes a first region (161a) and a second region (162a).

[0082] The first region (161a) includes an insulating terminal (IT) containing an insulator and a groove (HO) formed between the insulating terminal (IT) and the conductive terminal (ET). The second region (162a) may include a conductive terminal (ET) containing a conductor.

[0083] The conductor of the conductive terminal (ET) may be a metal including, for example, cobalt (Co), tungsten (W) and / or copper (Cu).

[0084] The insulator of the insulating terminal (IT) may be, for example, either a non-metal or a polymer.

[0085] In some embodiments, the ratio of the length (c) of the first region (161a) to the length (d) of the second region (162a) may be, for example, 3:2 to 4:1. Also, in some embodiments, the ratio of the total length (c+d) of the connection terminal (160a) to the length (c) of the first region (161a) may be, for example, 0.64 to 0.77.

[0086] Referring to FIG. 18, the connector pin (220) can be electrically connected to the connection terminal (160a). Specifically, when the connector pin (220) is electrically connected to the connection terminal (160a), as illustrated, the connector pin (220) can be spatially separated from the insulating terminal (IT) and electrically connected to the conductive terminal (ET).

[0087] In this embodiment as well, by making the ratio of the length (c) of the first region (161a) of the connection terminal (160a) and the length (d) of the second region (162a) to, for example, 3:2 to 4:1, signal integrity can be improved while maintaining electrical reliability between the connector pin (220) and the connection terminal (160a). As this has been sufficiently explained above, a redundant explanation is omitted.

[0088] Hereinafter, electronic devices according to several other embodiments will be described with reference to FIGS. 19 to 21.

[0089] FIG. 19 is an enlarged view of the connector pins of the host connector. FIG. 20 is an enlarged view of the connection terminals of the memory connector. FIG. 21 is a diagram showing the form in which the connector pins and connection terminals are connected.

[0090] Referring to FIG. 19, the connector pin (220a) includes a first conductor portion (220_1), a second conductor portion (220_2), and a stub (220_3).

[0091] The first conductor portion (220_1) includes a conductor. The second conductor portion (220_2) includes a conductor and is bent in a direction approaching the connection terminal (160b) from the first conductor portion (220_1). The stub (220_3) is bent in a direction away from the connection terminal (160b, shown in FIG. 20 and FIG. 21) from the second conductor portion (220_2) and includes an insulator.

[0092] The conductor may be a metal including, for example, cobalt (Co), tungsten (W) and / or copper (Cu).

[0093] The insulator can be, for example, either a nonmetal or a polymer.

[0094] In some embodiments, the second conductor part (220_2) and the stub (220_3) may be bonded to each other using a predetermined adhesive material. In addition, in some embodiments, the second conductor part (220_2) and the stub (220_3) may be formed integrally using a die casting method in which a conductor and an insulator are injected into a mold shaped like the second conductor part (220_2) and the stub (220_3).

[0095] In some embodiments, the sum (a) of the length of the first conductor part (220_1) and the length of the second conductor part (220_2) may be greater than the length (b) of the stub (220_3).

[0096] In addition, in some embodiments, the ratio of the sum (a) of the length of the first conductor part (220_1) and the length of the second conductor part (220_2) to the length (b) of the stub (220_3) may be 4:1.

[0097] Referring to FIG. 20, the connection terminal (160b) according to the present embodiment may not have a region containing an insulator, unlike the previously described embodiment. That is, the entire connection terminal (160b) according to the present embodiment may contain a conductor. The conductor may be a metal including, for example, cobalt (Co), tungsten (W), and / or copper (Cu).

[0098] Referring to FIG. 21, the connector pin (220a) can be electrically connected to the connection terminal (160b). Specifically, the second conductor portion (220_2) of the connector pin (220a) can be electrically connected to the connection terminal (160b). Through this, the first conductor portion (220_1) and the connection terminal (160b) can also be electrically connected.

[0099] In this embodiment, as described above, by making the ratio of the sum (a) of the length of the first conductor part (220_1) and the length of the second conductor part (220_2) to the length (b) of the stub (220_3) 4:1, signal integrity can be improved while maintaining the reliability of the electrical connection between the connection terminal (160b) and the connector pin (220a).

[0100] Specifically, if the ratio of the sum of the lengths of the first conductor part (220_1) and the second conductor part (220_2) (a) to the length of the stub (220_3) (b) is not 4:1, for example, 3:2, the proportion of the area occupied by the stub (220_3) in the connector pin (220a) becomes excessively large, and the conductor of the connector pin (220a) may not be electrically connected to the connection terminal (160b).

[0101] Conversely, if the ratio of the sum of the lengths of the first conductor part (220_1) and the second conductor part (220_2) (a) to the length of the stub (220_3) (b) is not 4:1, for example, 5:1, the ratio of the area occupied by the stub (220_3) in the connector pin (220a) becomes excessively small, and the effect of improving signal integrity may be reduced.

[0102] Hereinafter, electronic devices according to several other embodiments will be described with reference to FIGS. 22 and 23.

[0103] FIG. 22 is an enlarged view of the connector pins of the host connector. FIG. 23 is a diagram illustrating the configuration in which the connector pins and connection terminals are connected. Below, the description of configurations identical to the previously described embodiment will be omitted, and the differences will be explained in detail.

[0104] Referring to FIGS. 22 and 23, the connector pin (220b) includes a first conductor portion (220_1b), a second conductor portion (220_2b), a stub (220_3b), and a third conductor portion (220_4).

[0105] The first conductor portion (220_1b) includes a conductor. The second conductor portion (220_2b) includes a conductor and is bent in a direction approaching the connection terminal (160b) from the first conductor portion (220_1b). The stub (220_3b) is bent in a direction away from the connection terminal (160b, shown in FIG. 23) from the second conductor portion (220_2b) and includes an insulator. The third conductor portion (220_4) is bent in a direction away from the connection terminal (160b) from the stub (220_3b) and includes a conductor.

[0106] The conductor may be a metal including, for example, cobalt (Co), tungsten (W) and / or copper (Cu).

[0107] The insulator can be, for example, either a nonmetal or a polymer.

[0108] In some embodiments, the second conductor part (220_2b), the stub (220_3b), and the third conductor part (220_4) may be bonded together using a predetermined adhesive material. Additionally, in some embodiments, the second conductor part (220_2b), the stub (220_3b), and the third conductor part (220_4) may be formed integrally using a die casting method in which a conductor and an insulator are injected into a mold shaped like the second conductor part (220_2b), the stub (220_3b), and the third conductor part (220_4).

[0109] In some embodiments, the sum (x) of the length of the first conductor part (220_1b) and the length of the second conductor part (220_2b) may be greater than the sum (y) of the length of the stub (220_3b) and the length of the third conductor part (220_4).

[0110] In addition, in some embodiments, the ratio of the sum of the lengths of the first conductor part (220_1b) and the second conductor part (220_2b) (x) to the sum of the lengths of the stub (220_3b) and the third conductor part (220_4) (y) may be 4:1.

[0111] Referring to FIG. 23, as previously explained, by making the ratio of the sum of the lengths of the first conductor part (220_1b) and the second conductor part (220_2b) (x) and the sum of the lengths of the stub (220_3b) and the third conductor part (220_4) (y) 4:1, signal integrity can be improved while maintaining the reliability of the electrical connection between the connection terminal (160b) and the connector pin (220b). This has already been explained with reference to FIG. 21, so a redundant explanation is omitted.

[0112] Hereinafter, with reference to FIG. 24, an electronic device according to several other embodiments will be described.

[0113] FIG. 24 is a diagram illustrating the configuration in which connector pins and connection terminals are connected. Below, the description of the configuration identical to the previously described embodiment will be omitted, and the differences will be explained in detail.

[0114] When the connector pin (220a) according to the present embodiment is electrically connected to the connection terminal (160a), the insulating terminal (IT) is spatially separated and is electrically connected to the conductive terminal (ET).

[0115] In some embodiments, by making the ratio of the sum of the lengths of the first conductor portion (220_1) and the second conductor portion (220_2) of the connector pin (220a) (a) and the length (b) of the stub (220_3) 4:1, signal integrity can be improved while maintaining the reliability of the electrical connection between the connection terminal (160b) and the connector pin (220a). As this has been sufficiently explained above, a redundant explanation is omitted.

[0116] In addition, in some embodiments, the ratio of the length (c) of the first region (161a) of the connection terminal (160a) to the length (d) of the second region (162a) is, for example, 3:2 to 4:1, thereby improving signal integrity while maintaining electrical reliability between the connector pin (220a) and the connection terminal (160a). As this has been sufficiently explained above, a redundant explanation is omitted.

[0117] Also, in some embodiments, the ratio of the total length (c+d) of the connection terminal (160a) to the length (c) of the first region (161a) may be, for example, 0.64 to 0.77.

[0118] As described above, if the sum of the lengths of the first conductor portion (220_1) and the second conductor portion (220_2) of the connector pin (220a) (a) and the sum of the lengths of the stub (220_3) (b) is 4:1, and the ratio of the length of the first region (161a) of the connection terminal (160a) (c) and the length of the second region (162a) (d) is 3:2 to 4:1, or the ratio of the length of the first region (161a) (c) to the total length (c+d) of the connection terminal (160a) is 0.64 to 0.77, the connector pin (220a) and the connection terminal (160a) can improve signal integrity while maintaining the reliability of the electrical connection.

[0119] Hereinafter, with reference to FIG. 25, an electronic device according to several other embodiments will be described.

[0120] FIG. 25 is a diagram illustrating the configuration in which connector pins and connection terminals are connected. Below, the description of the configuration identical to the previously described embodiment will be omitted, and the differences will be explained in detail.

[0121] When the connector pin (220b) is electrically connected to the connection terminal (160a), the isolation terminal (IT) is spatially separated and is electrically connected to the conductive terminal (ET).

[0122] In some embodiments, by making the ratio of the sum of the lengths of the first conductor portion (220_1b) and the second conductor portion (220_2b) of the connector pin (220b) (x) and the sum of the lengths of the stub (220_3b) and the third conductor portion (220_4) (y) 4:1, signal integrity can be improved while maintaining the reliability of the electrical connection between the connection terminal (160a) and the connector pin (220b).

[0123] As described above, if the ratio of the sum of the lengths of the first conductor portion (220_1b) and the second conductor portion (220_2b) of the connector pin (220b) (x) and the sum of the lengths of the stub (220_3b) and the third conductor portion (220_4) (y) is 4:1, and the ratio of the length (c) of the first region (161a) of the connection terminal (160a) and the length (d) of the second region (162a) is 3:2 to 4:1, or the ratio of the length (d) of the first region (161a) to the total length (c+d) of the connection terminal (160a) is 0.64 to 0.77, the connector pin (220b) and the connection terminal (160a) can improve signal integrity while maintaining the reliability of the electrical connection.

[0124] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0125] 10: Memory device 20: Host 110: Memory module 160, 160a, 160b: Connection terminals 161, 161a: First region 162, 162a: Second region MCN: Memory Connector 200: Host Connector COH: Connector hole 220: Connector pin 220_1, 220_1b: First conductor part 220_2, 220_2b: Second conductor part 220_3, 220_3b: Stub 220_4: Third conductor

Claims

Claim 1 A host connector comprising: a connector hole for receiving a memory connector having a connection terminal of a memory device; and a connector pin disposed within the connector hole and electrically connected to the connection terminal of the memory connector, wherein the connector pin comprises: a first conductor portion which is a conductor; a second conductor portion which is a conductor and is bent in a direction approaching the connection terminal from the first conductor portion when the memory connector is received in the connector hole; and a stub which is an insulator and is bent in a direction away from the connection terminal from the second conductor portion when the memory connector is received in the connector hole. Claim 2 A host connector according to claim 1, wherein the sum of the length of the first conductor part and the length of the second conductor part is greater than the length of the stub. Claim 3 A host connector according to paragraph 2, wherein the ratio of the sum of the lengths of the first conductor part and the second conductor part to the length of the stub is 4:

1. Claim 4 A host connector according to claim 1, wherein the connector pin is bent in a direction away from the stub and the connection terminal, and further comprises a third conductor portion including the conductor, and the ratio of the sum of the lengths of the first conductor portion and the second conductor portion to the sum of the lengths of the stub and the third conductor portion is 4:

1. Claim 5 A memory device comprising: a module board and a memory connector disposed on one side of the module board and electrically connected to a host connector; a first enclosure disposed on the upper side of the memory module; and a second enclosure disposed on the lower side of the memory module, wherein the memory connector comprises a plurality of connection terminals arranged spaced apart from each other in a first direction on the upper surface of the module board and extending in a second direction intersecting the first direction, each of the plurality of connection terminals comprises a first region which is an insulator and a second region which is a conductor, and when the memory connector is electrically connected to the host connector, the first region is adjacent to the host connector compared to the second region. Claim 6 A memory device according to claim 5, wherein the length of the first region is greater than the length of the second region, and the ratio of the length of the first region to the length of the second region is 3:2 to 4:

1. Claim 7 A memory device according to claim 5, wherein the first region comprises an insulating terminal which is an insulator, the second region comprises a conductive terminal which is a conductor, and the first region comprises a groove formed between the insulating terminal and the conductive terminal. Claim 8 In claim 7, when the memory connector is electrically connected to the host connector, the connector pin of the host connector is spatially separated from the insulating terminal and electrically connected to the conductive terminal. Claim 9 An electronic device comprising: a host connector including connector pins; and a memory connector including a connection terminal electrically connected to the connector pins of the host connector, wherein the connector pins include a first conductor portion which is a conductor, a second conductor portion which is a conductor and is bent in a direction approaching the connection terminal from the first conductor portion, and a stub which is an insulator and is bent in a direction away from the connection terminal from the second conductor portion, and wherein the connection terminals include a first region which is an insulator and a second region which is a conductor, and wherein the second conductor portion and the second region are electrically connected so as to electrically connect the host connector and the memory connector. Claim 10 An electronic device according to claim 9, wherein the ratio of the length of the first region to the length of the connection terminal is 0.64 to 0.77.

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