Display substrate and display device

Abstract

The present disclosure provides a display substrate and a display device. The display substrate comprises: a base substrate, and a plurality of data lines and a plurality of sub-pixels arranged on the base substrate; each sub-pixel comprises a sub-pixel driving circuit and a light-emitting element; the sub-pixel driving circuit comprises a driving transistor and a data writing transistor, and the light-emitting element comprises a first electrode; a second pole of the driving transistor is coupled to the corresponding first electrode by means of a first connecting structure; a first pole of the data writing transistor is coupled to the corresponding data line by means of a second connecting structure; the first connecting structure and the second connecting structure are both located in a non-opening area of the sub-pixel; the orthographic projection of the first connecting structure on the base substrate and the orthographic projection of the second connecting structure on the base substrate are arranged in a first direction, and the orthographic projection of the second connecting structure on the base substrate and an opening area of the sub-pixel are arranged in a second direction, wherein the second direction intersects with the first direction.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, the application range of display products is becoming wider and wider, and display products with high resolution and high refresh rate are becoming more and more popular. However, medium and large-sized display products cannot fully realize the product function of high refresh rate due to the limitation of heavy load.

[0003] Summary of the Invention

[0004] An object of the present disclosure is to provide a display substrate and a display device.

[0005] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0006] A first aspect of the present disclosure provides a display substrate, comprising: a base substrate, and a plurality of data lines and a plurality of sub-pixels disposed on the base substrate; the sub-pixels comprising a sub-pixel driving circuit and a light-emitting element; the sub-pixel driving circuit comprising a driving transistor and a data writing transistor; and the light-emitting element comprising a first electrode;

[0007] The second electrode of the driving transistor is coupled to the corresponding first electrode through a first connection structure; the first electrode of the data writing transistor is coupled to the corresponding data line through a second connection structure;

[0008] The first connection structure and the second connection structure are both located in the non-opening area of ​​the sub-pixel, and the orthographic projection of the first connection structure on the base substrate and the orthographic projection of the second connection structure on the base substrate are arranged along a first direction;

[0009] The orthographic projection of the second connection structure on the base substrate and the opening area of ​​the sub-pixel are arranged along a second direction, and the second direction intersects with the first direction.

[0010] Optionally, the first connection structure includes: a second conductive connection portion, a first via structure, a fifth conductive connection portion and a second via structure;

[0011] The second conductive connection portion is coupled to the second electrode of the driving transistor, the second conductive connection portion is coupled to the fifth conductive connection portion through the first via structure, and the fifth conductive connection portion is coupled to the corresponding first electrode through the second via structure.

[0012] Optionally, the second connection structure includes: a fourth conductive connection portion and a third via structure; the fourth conductive connection portion is coupled to the first electrode of the data writing transistor, and the fourth conductive connection portion is coupled to the corresponding data line through the third via structure.

[0013] Optionally, the display substrate further includes a first organic layer and a second organic layer stacked in sequence in a direction away from the base substrate, the first via structure penetrates the first organic layer, and the second via structure penetrates the second organic layer;

[0014] The second conductive connection portion is located between the first organic layer and the base substrate, and the fifth conductive connection portion is located between the first organic layer and the second organic layer.

[0015] Optionally, the third via structure passes through the first organic layer, and the fourth conductive connection portion is located between the first organic layer and the base substrate.

[0016] Optionally, the display substrate further includes: a first passivation layer and a second passivation layer; the first passivation layer is located between the first organic layer and the second passivation layer, and the second passivation layer is located between the first passivation layer and the second organic layer;

[0017] The first via structure and the third via structure both penetrate the first passivation layer, and the second via structure penetrates the second passivation layer; the fifth conductive connection portion is located between the first passivation layer and the second passivation layer.

[0018] Optionally, the display substrate further includes: an auxiliary electrode, a third connection structure and a second electrode layer; the auxiliary electrode is coupled to the second electrode layer via the third connection structure;

[0019] The third connection structure is located in the non-opening area of ​​the sub-pixel, and an orthographic projection of the third connection structure on the base substrate and an orthographic projection of the first connection structure on the base substrate are arranged along a first direction.

[0020] Optionally, the display substrate further includes: an auxiliary electrode, a third connection structure and a second electrode layer; the auxiliary electrode is coupled to the second electrode layer via the third connection structure;

[0021] The third connection structure is located in the non-opening area of ​​the sub-pixel, and an orthographic projection of the third connection structure on the base substrate is at least partially offset from an orthographic projection of the first connection structure on the base substrate.

[0022] Optionally, the display substrate further includes a second organic layer and a pixel defining layer stacked in sequence in a direction away from the base substrate;

[0023] The third connection structure includes: a fourth via structure, a connection pattern, and a fifth via structure; the auxiliary electrode is located between the second organic layer and the base substrate, at least a portion of the second electrode layer is located on a side of the pixel defining layer facing away from the base substrate, at least a portion of the connection pattern is located between the second organic layer and the pixel defining layer, the fourth via structure penetrates the second organic layer, and the fifth via structure penetrates the pixel defining layer;

[0024] The connection pattern is coupled to the auxiliary electrode through the fourth via structure, and the connection pattern is coupled to the second electrode layer through the fifth via structure.

[0025] Optionally, the plurality of sub-pixels are divided into a plurality of repeating units distributed in an array, each repeating unit includes two sub-units arranged along a first direction, and each sub-unit includes a plurality of the sub-pixels arranged along the first direction;

[0026] The orthographic projection of the auxiliary electrode on the base substrate is located between the orthographic projections of the two sub-units on the base substrate.

[0027] Optionally, the display substrate further includes a power line and a power compensation line;

[0028] The sub-pixel driving circuit further includes a light emitting control transistor; a first electrode of the light emitting control transistor is coupled to the power compensation line, and a second electrode of the light emitting control transistor is coupled to the first electrode of the driving transistor;

[0029] The power compensation line is coupled to the power line through a sixth via structure, and the sixth via structure is located in a non-opening area of ​​the sub-pixel.

[0030] Optionally, the display substrate further includes a first organic layer, the power compensation line is located between the first organic layer and the base substrate, the power line is located on a side of the first organic layer facing away from the base substrate, and the sixth via structure passes through the first organic layer.

[0031] Optionally, the orthographic projection of the power line on the base substrate and the orthographic projection of the repeating unit on the base substrate are alternately arranged along the first direction.

[0032] Optionally, the display substrate further includes: a plurality of light emitting control lines, a power supply line, an initialization signal line, a reference signal line, a plurality of first scan lines, a plurality of second scan lines, a plurality of third scan lines and a plurality of partition control lines;

[0033] The sub-pixel driving circuit further includes: a compensation transistor, a reset transistor, a light emitting control transistor, a write control transistor and a storage capacitor;

[0034] The gate of the data writing transistor is coupled to the corresponding first scan line, and the second electrode of the data writing transistor is coupled to the first electrode of the write control transistor;

[0035] The second electrode of the write control transistor is coupled to the gate of the drive transistor, and the gate of the write control transistor is coupled to the corresponding partition control line;

[0036] The gate of the compensation transistor is coupled to the corresponding second scan line, the first electrode of the compensation transistor is coupled to the reference signal line, and the second electrode of the compensation transistor is coupled to the first electrode of the write control transistor;

[0037] The gate of the reset transistor is coupled to the corresponding third scan line, the first electrode of the reset transistor is coupled to the initialization signal line, and the second electrode of the reset transistor is coupled to the second electrode of the drive transistor;

[0038] The gate of the light emitting control transistor is coupled to the corresponding light emitting control line, the first electrode of the light emitting control transistor is coupled to the power line, and the second electrode of the light emitting control transistor is coupled to the first electrode of the driving transistor;

[0039] The first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the second electrode of the driving transistor.

[0040] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present disclosure provides a display device including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0042] FIG1 is a circuit diagram of a sub-pixel driving circuit provided by an embodiment of the present disclosure;

[0043] FIG2 is a schematic diagram of the circuit structure of a repeating unit provided in an embodiment of the present disclosure;

[0044] FIG3 is a schematic diagram of the resistance-capacitance equivalent of a partition control line provided by an embodiment of the present disclosure;

[0045] FIG4 is a driving timing diagram provided by an embodiment of the present disclosure;

[0046] FIG5 is a schematic diagram of the layout of the active layer and the first gate metal layer of the repeating unit provided in an embodiment of the present disclosure;

[0047] FIG6 is a schematic diagram of a layout in which a second gate metal layer is added on the basis of FIG5 ;

[0048] FIG7 is a schematic diagram of the layout of the second gate metal layer in FIG6 ;

[0049] FIG8 is a schematic diagram of a layout in which a first source / drain metal layer is added on the basis of FIG6 ;

[0050] FIG9 is a schematic diagram of the layout of via holes formed on the interlayer insulating layer in FIG8 ;

[0051] FIG10 is a schematic diagram of the layout of the first source and drain metal layer in FIG8 ;

[0052] FIG11 is a schematic diagram of a layout in which a second source / drain metal layer is added on the basis of FIG8 ;

[0053] FIG12 is a schematic diagram of the layout of via holes formed on the first organic layer in FIG11;

[0054] FIG13 is a schematic diagram of the layout of via holes formed on the first passivation layer in FIG11;

[0055] FIG14 is a schematic diagram of the layout of the second source / drain metal layer in FIG11 ;

[0056] FIG15 is a schematic diagram of a layout in which a first electrode layer is added on the basis of FIG11;

[0057] FIG16 is a schematic diagram of the layout of via holes formed on the second passivation layer in FIG15 ;

[0058] FIG17 is a schematic diagram of the layout of via holes formed on the second organic layer in FIG15 ;

[0059] FIG18 is a schematic diagram of the layout of the first electrode layer in FIG15 ;

[0060] FIG19 is a schematic diagram of a layout in which a first pixel defining layer is added to the layout in FIG15;

[0061] FIG20 is a schematic diagram of the layout of the first pixel definition layer in FIG19;

[0062] FIG21 is a schematic diagram of a layout with a second pixel defining layer opening added to FIG19;

[0063] FIG22 is a schematic diagram of the layout of the openings in the second pixel defining layer in FIG21;

[0064] FIG23 is a schematic diagram of a layout with a second pixel defining layer opening added to FIG19;

[0065] FIG24 is a schematic cross-sectional view along the A1A2 direction in FIG23 . DETAILED DESCRIPTION

[0066] In order to further illustrate the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0067] Because medium and large-sized display products are limited by heavy loads and cannot fully implement high refresh rate features, they require the addition of metal layers and thicker insulation layers for wiring to reduce the impact of these loads. Adding a thicker insulation layer requires the formation of deeper vias within the insulation layer, which can affect the flatness of the light-emitting functional layer, thereby reducing the aperture ratio of the display product and shortening its lifespan.

[0068] Referring to FIG. 1 , FIG. 2 , FIG. 5 , FIG. 23 and FIG. 24 , an embodiment of the present disclosure provides a display substrate, comprising: a base substrate, and a plurality of data lines DA and a plurality of sub-pixels disposed on the base substrate; the sub-pixels comprising a sub-pixel driving circuit and a light-emitting element EL; the sub-pixel driving circuit comprising a driving transistor DRT and a data writing transistor T1; the light-emitting element EL comprising a first electrode;

[0069] The second electrode of the driving transistor DRT is coupled to the corresponding first electrode through a first connection structure 81; the first electrode of the data writing transistor T1 is coupled to the corresponding data line DA through a second connection structure 82;

[0070] The first connection structure 81 and the second connection structure 82 are both located in the non-opening area 61 of the sub-pixel, and the orthographic projection of the first connection structure 81 on the base substrate and the orthographic projection of the second connection structure 82 on the base substrate are arranged along a first direction;

[0071] The orthographic projection of the second connection structure 82 on the base substrate and the opening area 60 of the sub-pixel are arranged along a second direction, and the second direction intersects with the first direction.

[0072] Exemplarily, the plurality of data lines DA are arranged along the first direction, and the data lines DA include at least a portion extending along the second direction. The plurality of sub-pixels are distributed in an array, and the plurality of sub-pixels are divided into a plurality of sub-pixel columns, and each sub-pixel included in each sub-pixel column is coupled to a corresponding data line DA.

[0073] Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element, and the sub-pixel driving circuit is coupled to a first electrode included in the light-emitting element, and is used to provide a driving signal to the first electrode of the light-emitting element to drive the light-emitting element to emit light.

[0074] Exemplarily, the data line DA and the first electrode are both located on the side of the sub-pixel driving circuit facing away from the base substrate. A thick insulating layer is provided between the data line DA and the first electrode of the data write transistor T1, and a thick insulating layer is also provided between the first electrode and the second electrode of the drive transistor DRT. Therefore, both the first connection structure 81 and the second connection structure 82 include relatively deep via structures.

[0075] According to the specific structure of the above-mentioned display substrate, in the display substrate provided by the embodiment of the present disclosure, by arranging the first connection structure 81 and the second connection structure 82 to be located in the non-opening area of ​​the sub-pixel, the first connection structure 81 and the second connection structure 82 are avoided from occupying the space of the opening area, thereby ensuring the aperture ratio of the display substrate and avoiding the first connection structure 81 and the second connection structure 82 from affecting the flatness of the light-emitting element.

[0076] Moreover, in the display substrate provided by the embodiment of the present disclosure, the orthographic projection of the first connection structure 81 on the base substrate is arranged along the first direction with the orthographic projection of the second connection structure 82 on the base substrate; the orthographic projection of the second connection structure 82 on the base substrate is arranged along the second direction with the opening area of ​​the sub-pixel; so that the first connection structure 81 and the second connection structure 82 are both located on the same side of the opening area along the second direction, and the first connection structure 81 and the second connection structure 82 occupy a smaller space in the second direction, which can centrally block the first connection structure 81 and the second connection structure 82, so that the size of the opening area in the second direction can be optimized, thereby effectively improving the aperture ratio of the display substrate and improving the service life of the display substrate.

[0077] As shown in FIG8 to FIG18 , FIG23 and FIG24 , in some embodiments, the first connection structure 81 includes: a second conductive connection portion 52 , a first via structure, a fifth conductive connection portion 55 and a second via structure;

[0078] The second conductive connection part 52 is coupled to the second electrode of the driving transistor DRT, the second conductive connection part 52 is coupled to the fifth conductive connection part 55 through the first via structure, and the fifth conductive connection part 55 is coupled to the corresponding first electrode (the first electrode layer 42 includes multiple first electrodes) through the second via structure.

[0079] Illustratively, the first via structure includes a seventeenth via Via17 and a twentieth via Via20. The second via structure includes a twenty-fourth via Via24 and a twenty-sixth via Via26. The second conductive connection portion 52 is made of the first source-drain metal layer of the display substrate, and the fifth conductive connection portion 55 is made of the second source-drain metal layer of the display substrate.

[0080] As shown in Figures 8 to 18, Figures 23 and 24, in some embodiments, the second connection structure 82 includes: a fourth conductive connection portion 54 and a third via structure; the fourth conductive connection portion 54 is coupled to the first electrode of the data writing transistor T1, and the fourth conductive connection portion 54 is coupled to the corresponding data line DA through the third via structure.

[0081] Exemplarily, the third via structure includes a sixteenth via Via 16 and a nineteenth via Via 19. The fourth conductive connection portion 54 is made of the first source-drain metal layer in the display substrate.

[0082] As shown in FIG24 , in some embodiments, the display substrate includes the following layers stacked sequentially on the base substrate 70 in a direction away from the base substrate 70: a buffer layer 71, an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer ILD, a first source / drain metal layer, a first organic layer Resin1, a first passivation layer PVX1, a second source / drain metal layer, a second passivation layer PVX2, a second organic layer Resin2, a first electrode layer 42, a first pixel defining layer PDL1, a second pixel defining layer PDL2, a light-emitting functional layer, a second electrode layer 43, and an encapsulation layer. The second electrode layer 43 receives a negative power supply signal VSS.

[0083] As shown in FIG8 to FIG18 , FIG23 and FIG24 , in some embodiments, the display substrate further includes a first organic layer and a second organic layer sequentially stacked in a direction away from the base substrate, the first via structure penetrates the first organic layer, and the second via structure penetrates the second organic layer;

[0084] The second conductive connection portion 52 is located between the first organic layer and the base substrate, and the fifth conductive connection portion 55 is located between the first organic layer and the second organic layer.

[0085] The first organic layer and the second organic layer are both relatively thick insulating layers, so the first and second via structures are both relatively deep via structures. The aforementioned arrangement of the first connection structure 81 in the non-opening region of the sub-pixel allows both the first and second via structures to be located in the non-opening region, preventing them from occupying space in the opening region, thereby ensuring the aperture ratio of the display substrate and preventing the first and second via structures from affecting the flatness of the light-emitting element.

[0086] As shown in FIG. 8 to FIG. 18 , FIG. 23 and FIG. 24 , in some embodiments, the third via structure passes through the first organic layer, and the fourth conductive connection portion 54 is located between the first organic layer and the base substrate.

[0087] The first organic layer is a relatively thick insulating layer, so the third via structure is a relatively deep via structure. The second connecting structure 82 is located in the non-opening area of ​​the sub-pixel, so that the third via structure is located in the non-opening area. This prevents the third via structure from occupying space in the opening area, thereby ensuring the aperture ratio of the display substrate and preventing the third via structure from affecting the flatness of the light-emitting element.

[0088] In the display substrate provided by the above embodiment, the orthographic projection of the first connecting structure 81 on the base substrate is arranged along the first direction with the orthographic projection of the second connecting structure 82 on the base substrate, and the orthographic projection of the second connecting structure 82 on the base substrate is arranged along the second direction with the opening area of ​​the sub-pixel; so that the orthographic projection of the first via structure on the base substrate, the orthographic projection of the second via structure on the base substrate, and the orthographic projection of the third via structure on the base substrate are all located on the same side of the opening area along the second direction, and the first via structure, the second via structure and the third via structure occupy a smaller space in the second direction, so that the size of the opening area in the second direction can be optimized, thereby effectively improving the aperture ratio of the display substrate and improving the service life of the display substrate.

[0089] As shown in FIG8 to FIG18, FIG23 and FIG24, in some embodiments, the display substrate further includes: a first passivation layer and a second passivation layer; the first passivation layer is located between the first organic layer and the second passivation layer, and the second passivation layer is located between the first passivation layer and the second organic layer;

[0090] The first via structure and the third via structure both penetrate the first passivation layer, and the second via structure penetrates the second passivation layer; the fifth conductive connection portion 55 is located between the first passivation layer and the second passivation layer.

[0091] In the display substrate provided in the above embodiment, the display substrate further includes a first passivation layer and a second passivation layer, and the fifth conductive connection portion 55 is located between the first passivation layer and the second passivation layer, which can better ensure the conductive performance of the fifth conductive connection portion 55.

[0092] As shown in FIG8 to FIG18 , FIG23 and FIG24 , in some embodiments, the display substrate further includes: an auxiliary electrode 40 , a third connection structure 83 and a second electrode layer 43 ; the auxiliary electrode 40 is coupled to the second electrode layer 43 via the third connection structure 83 ;

[0093] The third connection structure 83 is located in the non-opening area 61 of the sub-pixel, and the orthographic projection of the third connection structure 83 on the base substrate and the orthographic projection of the first connection structure 81 on the base substrate are arranged along a first direction.

[0094] Exemplarily, the display substrate includes a plurality of auxiliary electrodes 40 arranged along the first direction, and the auxiliary electrodes 40 include at least a portion extending along the second direction.

[0095] Illustratively, there is a thicker insulating layer between the auxiliary electrode 40 and the second electrode layer, and the third connection structure 83 includes a deeper via structure capable of penetrating the thicker insulating layer.

[0096] In the display substrate provided by the above embodiment, by arranging the third connection structure 83 in the non-opening area 61 of the sub-pixel, the third connection structure 83 is avoided from occupying the space of the opening area 60, thereby ensuring the aperture ratio of the display substrate and avoiding the third connection structure 83 from affecting the flatness of the light-emitting element.

[0097] Moreover, in the display substrate provided by the above embodiment, by setting the orthographic projection of the third connecting structure 83 on the base substrate, it is arranged along the first direction with the orthographic projection of the first connecting structure 81 on the base substrate, so that the first connecting structure 81 and the third connecting structure 83 are both located on the same side of the opening area 60 along the second direction, and the first connecting structure 81 and the third connecting structure 83 occupy a smaller space in the second direction, so that the size of the opening area 60 in the second direction can be optimized, thereby effectively improving the aperture ratio of the display substrate and improving the service life of the display substrate.

[0098] As shown in FIG8 to FIG18 , FIG23 and FIG24 , in some embodiments, the display substrate further includes: an auxiliary electrode 40 , a third connection structure 83 and a second electrode layer; the auxiliary electrode 40 is coupled to the second electrode layer 43 via the third connection structure 83 ;

[0099] The third connection structure 83 is located in the non-opening area of ​​the sub-pixel, and the orthographic projection of the third connection structure 83 on the base substrate is at least partially offset from the orthographic projection of the first connection structure 81 on the base substrate.

[0100] In the display substrate provided in the above embodiment, by setting the orthographic projection of the third connecting structure 83 on the base substrate to be at least partially staggered with the orthographic projection of the first connecting structure 81 on the base substrate, the layout space of the non-opening area can be better utilized, thereby reducing the layout difficulty of the first connecting structure 81 and the third connecting structure 83.

[0101] As shown in FIG8 to FIG18 , FIG23 and FIG24 , in some embodiments, the display substrate further includes a second organic layer and a pixel defining layer sequentially stacked in a direction away from the base substrate;

[0102] The third connection structure 83 includes: a fourth via structure, a connection pattern 41, and a fifth via structure; the auxiliary electrode 40 is located between the second organic layer and the base substrate; at least a portion of the second electrode layer is located on a side of the pixel defining layer facing away from the base substrate; at least a portion of the connection pattern 41 is located between the second organic layer and the pixel defining layer; the fourth via structure penetrates the second organic layer; and the fifth via structure penetrates the pixel defining layer.

[0103] The connection pattern 41 is coupled to the auxiliary electrode 40 through the fourth via structure, and the connection pattern 41 is coupled to the second electrode layer through the fifth via structure.

[0104] Exemplarily, the pixel defining layer includes a first pixel defining layer and a second pixel defining layer stacked together, with the first pixel defining layer positioned between the base substrate and the second pixel defining layer. At least a portion of the second electrode layer is positioned on a side of the second pixel defining layer facing away from the base substrate, and at least a portion of the connection pattern 41 is positioned between the second organic layer and the first pixel defining layer.

[0105] Exemplarily, the fourth via structure includes a twenty-fifth via Via25 and a twenty-seventh via Via27. The fifth via structure includes a twenty-eighth via Via28 and a twenty-ninth via Via29.

[0106] Exemplarily, the connection pattern 41 is arranged in the same layer as the first electrode layer 42. Exemplarily, the connection pattern 41 can be made of the same material as the first electrode layer, such as indium tin oxide material, or different materials can be used as long as the performance of the conductive connection is met.

[0107] In the display substrate provided by the above embodiment, the second electrode layer is coupled to the plurality of auxiliary electrodes 40 via the connection pattern 41 , thereby effectively reducing the voltage drop of the second electrode layer.

[0108] As shown in FIG. 21 , in some embodiments, the plurality of sub-pixels are divided into a plurality of repeating units distributed in an array, each repeating unit includes two sub-units arranged along a first direction, and each sub-unit includes a plurality of the sub-pixels arranged along the first direction;

[0109] The orthographic projection of the auxiliary electrode 40 on the base substrate is located between the orthographic projections of the two sub-units on the base substrate.

[0110] Exemplarily, the display substrate includes a plurality of repeating units arranged in an array and capable of being divided into a plurality of columns of repeating units arranged sequentially along the first direction, each column of repeating units including a plurality of repeating units arranged along the second direction. The repeating units include a plurality of sub-pixels arranged along the first direction. For example, the repeating units include six sub-pixels arranged along the first direction, each of which includes BRGBRG arranged along the first direction, where B represents a blue sub-pixel, R represents a red sub-pixel, and G represents a green sub-pixel. A group of BRG represents a sub-unit.

[0111] Exemplarily, the multiple sub-pixels included in the multiple repeating units are distributed in an array, and the multiple sub-pixels can be divided into multiple columns of sub-pixels, and the multiple columns of sub-pixels correspond one-to-one to the multiple data lines DA included in the display substrate.

[0112] The above arrangement of the orthographic projection of the auxiliary electrode 40 on the base substrate being located between the orthographic projections of the two sub-units on the base substrate better utilizes the layout drop and reduces the layout difficulty of the auxiliary electrode 40 .

[0113] As shown in FIG8 to FIG18 , FIG23 and FIG24 , in some embodiments, the display substrate further includes a power line VDD and a power compensation line 30 ;

[0114] The sub-pixel driving circuit further includes a light emitting control transistor T_em; a first electrode of the light emitting control transistor T_em is coupled to the power compensation line 30, and a second electrode of the light emitting control transistor T_em is coupled to a first electrode of the driving transistor DRT;

[0115] The power compensation line 30 is coupled to the power line VDD through a sixth via structure, and the sixth via structure is located in a non-opening area of ​​the sub-pixel.

[0116] Exemplarily, the plurality of power lines VDD are arranged along the first direction, the power lines VDD include at least a portion extending along the second direction, and along the first direction, the power lines VDD and the repeating unit columns are alternately arranged.

[0117] Exemplarily, the sixth via structure includes an eighteenth via Via18 and a twenty-first via Via21.

[0118] In some embodiments, the display substrate further includes a first organic layer, the power compensation line 30 is located between the first organic layer and the base substrate, the power line VDD is located on the side of the first organic layer facing away from the base substrate, and the sixth via structure passes through the first organic layer.

[0119] The sixth via structure is located in the non-opening area of ​​the sub-pixel, which prevents the sixth connection structure from occupying the space of the opening area, ensures the aperture ratio of the display substrate, and prevents the sixth connection structure from affecting the flatness of the light-emitting element.

[0120] In some embodiments, the orthographic projection of the power line VDD on the base substrate and the orthographic projection of the repeating unit on the base substrate are alternately arranged along the first direction.

[0121] As shown in FIG1 , FIG2 , FIG8 to FIG18 , FIG23 and FIG24 , in some embodiments, the display substrate further includes: a plurality of emission control lines EM, a power line VDD, an initialization signal line Vini, a reference signal line Vref, a plurality of first scan lines G1, a plurality of second scan lines G2, a plurality of third scan lines G3 and a plurality of partition control lines;

[0122] The sub-pixel driving circuit further includes: a compensation transistor T2, a reset transistor T3, a light emitting control transistor T_em, a write control transistor T_com and a storage capacitor Cst;

[0123] The gate of the data writing transistor T1 is coupled to the corresponding first scan line G1, and the second electrode of the data writing transistor T1 is coupled to the first electrode of the writing control transistor T_com;

[0124] A second electrode of the write control transistor T_com is coupled to the gate of the drive transistor DRT, and the gate of the write control transistor T_com is coupled to the corresponding partition control line;

[0125] The gate of the compensation transistor T2 is coupled to the corresponding second scan line G2, the first electrode of the compensation transistor T2 is coupled to the reference signal line Vref, and the second electrode of the compensation transistor T2 is coupled to the first electrode of the write control transistor T_com;

[0126] The gate of the reset transistor T3 is coupled to the corresponding third scan line G3, the first electrode of the reset transistor T3 is coupled to the initialization signal line Vini, and the second electrode of the reset transistor T3 is coupled to the second electrode of the drive transistor DRT;

[0127] The gate of the light emitting control transistor T_em is coupled to the corresponding light emitting control line EM, the first electrode of the light emitting control transistor T_em is coupled to the power line VDD, and the second electrode of the light emitting control transistor T_em is coupled to the first electrode of the driving transistor DRT;

[0128] A first plate Cst1 of the storage capacitor Cst is coupled to the gate of the driving transistor DRT, and a second plate Cst2 of the storage capacitor Cst is coupled to the second electrode of the driving transistor DRT.

[0129] Exemplarily, the initialization signal line Vini includes a plurality of first initial portions 21 and a plurality of second initial portions 22, the plurality of first initial portions 21 are arranged along the second direction, the plurality of second initial portions 22 are arranged along the first direction, the first initial portion 21 includes at least a portion extending along the first direction, the second initial portion 22 includes at least a portion extending along the second direction, the first initial portion 21 is coupled to each of the second initial portions 22, respectively, so that the initialization signal line Vini forms a grid structure, thereby effectively reducing the voltage drop of the initialization signal line Vini.

[0130] As shown in FIG. 5 , illustratively, the active layer is used to form a channel portion, a first electrode, and a second electrode included in each of the transistors.

[0131] As shown in FIG. 5 , illustratively, the first gate metal layer is used to form the gate of each of the transistors, the first branch line 111 and the second initial portion 22 .

[0132] As shown in FIG. 7 , illustratively, the second gate metal layer is used for the second substrate of the storage capacitor Cst.

[0133] As shown in Figure 10, illustratively, the first source-drain metal layer is used to form some conductive connection portions, the reference signal line Vref, the first scan line G1, the second scan line G2, the third scan line G3, the light-emitting control line EM, and the first initial portion 21. The reference signal line Vref, the second scan line G2, the first scan line G1, the second branch line 112, the light-emitting control line EM, the power compensation line 30, the third scan line G3, and the first initial portion 21 coupled to the same repeating unit are arranged sequentially along the second direction.

[0134] Exemplarily, the reference signal line Vref, the first scan line G1, the second scan line G2, the third scan line G3 and the light emitting control line EM each include at least a portion extending along the first direction.

[0135] As shown in Figure 14 , the second source / drain metal layer is illustratively used to form the power line VDD, the data line DA, several conductive connectors, and an auxiliary electrode 40. Using the second source / drain metal layer to form signal lines effectively reduces the load on these lines, providing technical support for medium- and large-sized display products. Exemplarily, the auxiliary electrode 40 includes at least a portion extending along the second direction. The auxiliary electrode 40 is coupled to the second electrode layer via a connection pattern 41 made of indium tin oxide, effectively reducing the voltage drop across the second electrode layer.

[0136] Since there is a first organic layer and a first passivation layer between the first source-drain metal layer and the second source-drain metal layer, the first source-drain metal layer and the second source-drain metal layer are far apart. This can effectively reduce the parasitic capacitance between the first source-drain metal layer and the second source-drain metal layer, thereby meeting the load requirements of medium and large-sized display products and providing support for high refresh rates.

[0137] As shown in FIG1 , illustratively, the sub-pixel driving circuit includes: a data writing transistor T1 , a writing control transistor T_com, a driving transistor DRT, a compensation transistor T2 , a reset transistor T3 , a light emitting control transistor T_em, a storage capacitor Cst and an intrinsic capacitor C1 of the light emitting element EL.

[0138] As shown in Figure 9, a via hole formed in the interlayer insulating layer is shown. As shown in Figures 5 to 10, the gate of the compensation transistor T2 is coupled to the corresponding second scan line G2 through the second via hole Via2, and the first electrode of the compensation transistor T2 is coupled to the reference signal line Vref through the first via hole Via1.

[0139] The gate of the data writing transistor T1 is coupled to the corresponding first scan line G1 through the third via hole Via3 , and the first electrode of the data writing transistor T1 is coupled to the fourth conductive connection portion 54 through the ninth via hole Via9 .

[0140] The gate of the write control transistor T_com is coupled to the partition control line G_com through the fourth via Via4, the second electrode of the write control transistor T_com is coupled to the first conductive connection part 51 through the fifth via Via5, and the first conductive connection part 51 is coupled to the gate of the driving transistor DRT through the sixth via Via6. The gate of the driving transistor DRT is reused as the first plate Cst1 of the storage capacitor Cst.

[0141] The second electrode of the drive transistor DRT is coupled to the second conductive connection portion 52 through a seventh via Via7. The second conductive connection portion 52 is coupled to the second plate Cst2 of the storage capacitor Cst through an eighth via Via8. The second plate Cst2 of the storage capacitor Cst is coupled to the third conductive connection portion 53 through a tenth via Via10. The third conductive connection portion 53 is coupled to the second electrode of the reset transistor T3 through a fifteenth via Via15.

[0142] The gate of the light emitting control transistor T_em is coupled to the corresponding light emitting control line EM through an eleventh via hole Via11 , and the first electrode of the light emitting control transistor T_em is coupled to the power line VDD through a twelfth via hole Via12 .

[0143] The gate of the reset transistor T3 is coupled to the third scan line G3 through the fourteenth via hole Via14 , and the first electrode of the reset transistor T3 is coupled to the first initial portion 21 through the thirteenth via hole Via13 .

[0144] The first branch line 111 is coupled to the second branch line 112 through the twenty-second via Via22. The first initial portion 21 is coupled to the second initial portion 22 through the twenty-third via Via23.

[0145] As shown in Figure 12, a via hole formed on the first organic layer is shown. As shown in Figure 13, a via hole formed on the first passivation layer is shown.

[0146] As shown in Figures 11 to 14, the second conductive connection portion 52 is sequentially coupled to the fifth conductive connection portion 55 through the seventeenth via Via17 and the twentieth via Via20. The fourth conductive connection portion 54 is sequentially coupled to the data line DA through the sixteenth via Via16 and the nineteenth via Via19. The power compensation line 30 is once coupled to the power line VDD through the eighteenth via Via18 and the twenty-first via Via21.

[0147] As shown in Figure 16, a via hole formed on the second passivation layer is shown. As shown in Figure 17, a via hole formed on the second organic layer is shown.

[0148] As shown in Figures 15 to 22, the fifth conductive connection portion 55 is sequentially coupled to the corresponding first electrode in the first electrode layer 42 through the twenty-fourth via Via24 and the twenty-sixth via Via26. The auxiliary electrode 40 is sequentially coupled to the connection pattern 41 through the twenty-fifth via Via25 and the twenty-seventh via Via27. The connection pattern 41 is sequentially coupled to the second electrode layer through the twenty-eighth via Via28 and the twenty-ninth via Via29.

[0149] As shown in FIG. 23 , an opening region 60 of a sub-pixel and a non-opening region 61 located near the opening region 60 are schematically illustrated.

[0150] As shown in FIG. 1 , in some embodiments, the data writing transistor T1 , the compensation transistor T2 , and the reset transistor T3 all include a dual-gate structure, which can effectively reduce leakage current.

[0151] As shown in FIG. 1 , in some embodiments, the write control transistor T_com includes a single-gate structure.

[0152] Since the data write transistor T1 is connected between the data line DA and the write control transistor T_com, when the write control transistor T_com is turned off, the leakage path of the data write transistor T1 can be closed. The write control transistor T_com adopts a single-gate structure design, which is conducive to saving layout area.

[0153] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0154] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0155] Exemplarily, the display device includes an organic light emitting diode display device, but is not limited thereto.

[0156] In the display substrate provided by the above embodiment, by arranging the first connection structure and the second connection structure to be located in the non-opening area of ​​the sub-pixel, the first connection structure and the second connection structure are avoided from occupying the space of the opening area, thereby ensuring the aperture ratio of the display substrate and avoiding the first connection structure and the second connection structure from affecting the flatness of the light-emitting element.

[0157] Moreover, in the display substrate provided by the above embodiment, the orthographic projection of the first connection structure on the base substrate is arranged to be arranged along the first direction with the orthographic projection of the second connection structure on the base substrate; the orthographic projection of the second connection structure on the base substrate is arranged along the second direction with the opening area of ​​the sub-pixel; so that the first connection structure and the second connection structure are both located on the same side of the opening area along the second direction, and the first connection structure and the second connection structure occupy a smaller space in the second direction, so that the size of the opening area in the second direction can be optimized, thereby effectively improving the aperture ratio of the display substrate and improving the service life of the display substrate.

[0158] The display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0159] Referring to FIG. 1 , FIG. 2 , FIG. 3 , FIG. 5 , and FIG. 21 , an embodiment of the present disclosure provides a display substrate, comprising: a base substrate, and a plurality of repeating units and a plurality of data lines DA disposed on the base substrate, wherein the plurality of repeating units are divided into a plurality of columns of repeating units;

[0160] Each repeating unit includes a plurality of sub-pixels, each sub-pixel including a sub-pixel driving circuit, wherein the sub-pixel driving circuit includes a data writing transistor T1, a writing control transistor T_com, and a driving transistor DRT; a first electrode of the data writing transistor T1 is coupled to the corresponding data line DA, a second electrode of the data writing transistor T1 is coupled to the first electrode of the writing control transistor T_com, and a second electrode of the writing control transistor T_com is coupled to the gate of the driving transistor DRT;

[0161] The display substrate further includes: a plurality of control areas (such as control areas 1 to control areas X) and a plurality of partition control lines G_com; the control area includes at least one column of repeating units; the partition control lines G_com are respectively coupled to the gates of the write control transistors T_com included in each repeating unit column in the corresponding control area.

[0162] Exemplarily, the display substrate includes a plurality of repeating units arranged in an array. The repeating units include a plurality of sub-pixels arranged along a first direction. For example, the repeating unit includes six sub-pixels arranged along the first direction. The six sub-pixels include BRGBRG arranged along the first direction, where B represents a blue sub-pixel, R represents a red sub-pixel, and G represents a green sub-pixel.

[0163] Exemplarily, the multiple sub-pixels included in the multiple repeating units are distributed in an array, and the multiple sub-pixels can be divided into multiple columns of sub-pixels, and the multiple columns of sub-pixels correspond one-to-one to the multiple data lines DA included in the display substrate.

[0164] Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element EL. The sub-pixel driving circuit is coupled to the light-emitting element EL and is configured to provide a driving signal to the light-emitting element EL to drive the light-emitting element EL to emit light.

[0165] Exemplarily, the sub-pixel driving circuit includes a data writing transistor T1, a writing control transistor T_com and a driving transistor DRT; the first electrode of the data writing transistor T1 is coupled to the corresponding data line DA, the second electrode of the data writing transistor T1 is coupled to the first electrode of the writing control transistor T_com, and the second electrode of the writing control transistor T_com is coupled to the gate of the driving transistor DRT; when the data writing transistor T1 and the writing control transistor T_com are both turned on, the data signal transmitted by the data line DA can be written into the gate of the driving transistor DRT; when one of the data writing transistor T1 and the writing control transistor T_com is turned off, the data signal cannot be transmitted to the gate of the driving transistor DRT.

[0166] Exemplarily, the display substrate further includes a plurality of control regions and a plurality of partition control lines G_com, wherein the plurality of control regions correspond one-to-one to the plurality of partition control lines G_com. The partition control lines G_com are respectively coupled to the gates of the write control transistors T_com included in each repeating unit column in the corresponding control region, and are used to control the conduction or cutoff of the write control transistors T_com included in each repeating unit column in the corresponding control region.

[0167] Based on the specific structure of the display substrate described above, the display substrate provided in the embodiments of the present disclosure includes multiple control regions, each of which includes at least one column of repeating units. The partition control lines G_com are respectively coupled to the gates of the write control transistors T_com included in each repeating unit column in the corresponding control region. Each partition control line G_com can control whether all write control transistors T_com in the corresponding control region are conductive, thereby controlling whether the region achieves a high refresh rate.

[0168] In more detail, as shown in FIG. 3 and FIG. 4 , it is taken as an example that the display substrate includes X control areas.

[0169] During the Nth frame display period: the first partition control line G_com <1> and the Mth partition control line G_com <m>The transmitted control signals are all at the effective level VGH, and the corresponding first partition control line G_com <1> All write control transistors T_com included in the corresponding first control area are turned on, and the Mth partition control line G_com <m>All write control transistors T_com included in the corresponding M-th control area are turned on, which can ensure that the first control area and the M-th control area are areas where normal refresh can be achieved. When the display substrate is scanned line by line, high refresh operation can be achieved in the first control area and the M-th control area. <h>The transmitted control signal is a non-valid level VGL, and the corresponding Hth partition control line G_com <h>All write control transistors T_com included in the corresponding Hth control area are turned off. When the display substrate is scanned row by row, the Hth control area cannot achieve high refresh rate operation, so the Hth control area is not refreshed in the Nth frame, and its display image is not updated in the Nth frame. The saved data is provided to the high refresh rate area, achieving the effect of zoned high refresh rate. It is worth noting that M and H are both positive integers greater than 1 and less than X.

[0170] During the blanking period, the partition selection is performed for the N+1 frame by controlling the level of the control signal transmitted by the partition control line G_com. It is worth noting that the blanking period is located at the beginning or end of the display period of each frame.

[0171] During the N+1 frame display period: the first partition control line G_com <1> and the Hth partition control line G_com <h>The transmitted control signals are all at the effective level VGH, and the corresponding first partition control line G_com <1> All the write control transistors T_com included in the corresponding first control area are turned on, and the Hth partition control line G_com <h>All write control transistors T_com included in the corresponding H-th control area are turned on, which can ensure that the first control area and the H-th control area are areas where normal refresh can be achieved. When the display substrate is scanned line by line, high refresh operation can be achieved in the first control area and the H-th control area. <m>The transmitted control signal is a non-valid level VGL, and the corresponding Mth partition control line G_com <m>All the write control transistors T_com included in the corresponding Mth control area are turned off. When the display substrate is scanned line by line, the Mth control area cannot implement high refresh operation, so that the Mth control area is not refreshed in the Mth frame, and its display screen is not updated in the Mth frame. The saved data is provided to the high refresh area to achieve the effect of partitioned high refresh.

[0172] It is worth noting that, considering that the load of the partition control line G_com is relatively large, the control signal transmitted by the partition control line G_com may be adjusted immediately when the Nth frame ends and the blanking period begins.

[0173] In the display substrate provided by the embodiment of the present disclosure, by providing the control area and the partition control line G_com, a large-size display substrate can also well realize the high refresh rate function of the display substrate.

[0174] It should be noted that the numbers in the brackets in Figure 4 represent the row numbers, such as: G1 <1> Represents the first scan line of the first row, G2 <1> Represents the second scan line of the first row, G3 <1> Represents the third scan line of the first row, EM <1> Represents the first row of light-emitting control lines.

[0175] As shown in FIG3 , FIG5 , FIG8 , FIG11 , FIG15 , FIG19 and FIG21 , in some embodiments, the partition control line G_com includes: a control bus 10 and at least one control branch line 11 ;

[0176] The control branch line 11 is coupled to the gate of each write control transistor T_com included in a corresponding column of repeating units in the corresponding control region. The control bus 10 is coupled to the at least one control branch line 11 .

[0177] Exemplarily, the control branch lines 11 included in the partition control line G_com correspond one-to-one with the repeating unit columns included in its corresponding control region. The control branch lines 11 are respectively coupled to the gates of the write control transistors T_com included in a corresponding column of repeating units in the corresponding control region to control the conduction or cutoff of the write control transistors T_com included in the corresponding column of repeating units.

[0178] For example, in the same partition control line G_com, the control bus 10 and each control branch line 11 are coupled separately. For example, in the same partition control line G_com, the control bus 10 and each control branch line 11 form an integrated structure.

[0179] Exemplarily, the display substrate also includes a driver chip, and the control bus 10 and the driver chip are located on the same side of the display substrate. The control bus 10 is coupled to the driver chip, receives the control signal provided by the driver chip, and transmits the received control signal to each control branch 11 coupled thereto, thereby controlling whether the write control transistor T_com in the corresponding control area is turned on.

[0180] In the display substrate provided by the above embodiment, by setting the partition control line G_com to include the control bus 10 and the control branch line 11, not only can the transmission of the control signal be better realized, but also the layout difficulty of the partition control line G_com can be reduced, thereby ensuring the reliability of the coupling between the partition control line G_com and the gate of the write control transistor T_com.

[0181] As shown in Figures 3, 5, 8, 11, 15, 19 and 21, in some embodiments, the control branch 11 includes: a first branch 111 and multiple second branches 112; the second branch 112 includes at least a portion extending along the first direction, and the multiple second branches 112 are arranged along the second direction; the first branch 111 includes at least a portion extending along the second direction, the first branch 111 is coupled to the multiple second branches 112 respectively, and the first branch 111 is coupled to the control bus 10; the first direction intersects with the second direction; the second branch 112 is respectively coupled to the gates of each write control transistor T_com included in the corresponding repeating unit.

[0182] Exemplarily, the first direction includes a horizontal direction, and the second direction includes a vertical direction.

[0183] Exemplarily, in the control region, the control branch line 11 corresponds one-to-one with the columns of repeating units, and the multiple second branches 112 included in the control branch line 11 correspond one-to-one with the multiple repeating units included in the corresponding repeating unit columns. The repeating units include multiple sub-pixels arranged along the first direction, each sub-pixel including a sub-pixel driving circuit, and the sub-pixel driving circuit includes a write control transistor T_com. The second branch line 112 is respectively coupled to the gate of each write control transistor T_com included in the corresponding repeating unit. Exemplarily, the second branch line 112 is respectively coupled to the gates of six write control transistors T_com included in the corresponding repeating unit to control the conduction and cutoff of the six write control transistors T_com.

[0184] Exemplarily, the first branch line 111 included in the control branch line 11 is located in the middle region of the corresponding repeating unit column. That is, in the repeating unit column corresponding to the first branch line 111, the number of sub-pixels located on both sides of the first branch line 111 along the first direction is the same. For example, along the first direction, the number of sub-pixels located on the left and right sides of the corresponding first branch line 111 in the repeating unit is both three.

[0185] Exemplarily, in the same control branch line 11, the orthographic projection of the first branch line 111 on the substrate substrate and the orthographic projection of each second branch line 112 on the substrate substrate respectively form an overlapping area, and the first branch line 111 is coupled to the corresponding second branch line 112 through a via in the corresponding overlapping area.

[0186] In the display substrate provided in the above embodiment, the control branch line 11 is provided to include: a first branch line 111 and multiple second branches 112; this not only enables better transmission of control signals, but also reduces the difficulty of layout of the control branch line 11, thereby ensuring reliability of coupling between the control branch line 11 and the gate of the write control transistor T_com.

[0187] In some embodiments, in the same control area, adjacent second branches 112 along the first direction are coupled.

[0188] For example, in the same control area, the second branches 112 located in the same row along the first direction are sequentially connected. For example, in the same control area, the second branches 112 located in the same row along the first direction form an integrated structure.

[0189] Exemplarily, in adjacent control areas, the second branches 112 adjacent to each other along the first direction are disconnected.

[0190] In the display substrate provided by the above embodiment, the second branches 112 adjacent to each other along the first direction are arranged in the same control area and coupled, so that in the same control area, the control branches 11 can form a grid structure, which is beneficial to reducing the overall load of the partition control line G_com and reducing the voltage drop of the partition control line G_com.

[0191] In some embodiments, in the same control area, the second branches 112 adjacent to each other along the first direction are independent of each other.

[0192] As shown in FIG11 , in some embodiments, the display substrate further includes a plurality of power lines VDD, and the orthographic projection of the second branch line 112 on the base substrate does not overlap with the orthographic projection of the power line VDD on the base substrate.

[0193] Exemplarily, the plurality of power lines VDD are arranged along the first direction, the power lines VDD include at least a portion extending along the second direction, and along the first direction, the power lines VDD and the repeating unit columns are alternately arranged.

[0194] Exemplarily, the display substrate further includes a plurality of power compensation lines 30, which are arranged along the second direction and include at least a portion extending along the first direction. The power compensation lines 30 are respectively coupled to the plurality of power lines VDD, and the power compensation lines 30 and the power lines VDD together form a grid structure to reduce a voltage drop across the power line VDD.

[0195] Exemplarily, an orthographic projection of the power compensation line 30 on the substrate and an orthographic projection of the power line VDD on the substrate have an overlapping area, and the power compensation line 30 and the power line VDD are coupled through a via in the overlapping area.

[0196] In the display substrate provided by the above embodiment, the second branches 112 adjacent to each other along the first direction are set to be independent of each other, and the orthographic projection of the second branch 112 on the base substrate does not overlap with the orthographic projection of the power line VDD on the base substrate, so that the control branch 11 is formed into a non-grid structure and can avoid the power line VDD. This not only reduces the risk of short circuit between the control branch 11 and the power line VDD, but also reduces the parasitic capacitance formed between the control branch 11 and the power line VDD.

[0197] As shown in FIG11 , in some embodiments, the orthographic projection of the data line DA on the base substrate and the orthographic projection of the second branch line 112 on the base substrate have a first overlapping region, and the areas of the first overlapping regions formed by the data lines DA are the same.

[0198] Exemplarily, the data lines DA and the sub-pixel columns in the display substrate are alternately arranged along the first direction. The data lines DA include at least a portion extending along the second direction.

[0199] Exemplarily, the data lines DA and the second branch lines 112 are provided in different layers, and the total area of ​​the first overlapping regions formed between each of the data lines DA and the plurality of second branch lines 112 is the same.

[0200] In the display substrate provided in the above embodiment, by setting the total area of ​​the first overlapping regions formed between each of the data lines DA and the plurality of second branches 112 to be the same, the loads of the data lines DA connected to the sub-pixels of various colors in the display substrate are made the same, thereby better ensuring the uniformity of the display image of the display substrate.

[0201] In some embodiments, the first branch line 111 is made of a first gate metal layer in a display substrate, and the second branch line 112 is made of a first source / drain metal layer in a display substrate.

[0202] As shown in FIG24 , in some embodiments, the display substrate includes the following layers, stacked sequentially on the base substrate 70 in a direction away from the base substrate 70: a buffer layer 71, an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer ILD, a first source / drain metal layer, a first organic layer Resin1, a first passivation layer PVX1, a second source / drain metal layer, a second passivation layer PVX2, a second organic layer Resin2, a first electrode layer 42, a first pixel defining layer PDL1, a second pixel defining layer PDL2, a light-emitting functional layer, a second electrode layer 43, and an encapsulation layer. FIG24 also illustrates a first connection structure 81, a second connection structure 82, and a third connection structure 83. The second electrode layer 43 receives a negative power supply signal VSS.

[0203] In the display substrate provided in the above embodiment, by setting the first branch line 111 to be made of the first gate metal layer, the first branch line 111 can be formed in the same patterning process as other structures in the display substrate made of the first gate metal layer, thereby effectively simplifying the manufacturing process of the display substrate.

[0204] In the display substrate provided in the above embodiment, by setting the second branch line 112 to be made of the first source-drain metal layer, the second branch line 112 can be formed in the same patterning process as other structures in the display substrate made of the first source-drain metal layer, thereby effectively simplifying the manufacturing process flow of the display substrate.

[0205] In the display substrate provided in the above embodiment, by configuring the partition control line G_com to include the control bus 10 and the control branch line 11, and configuring the control branch line 11 to include the first branch line 111 and the plurality of second branch lines 112, the partition control line G_com is designed to be connected in parallel within the control region, resulting in a low equivalent resistance. Furthermore, the first branch line 111 is fabricated using the first gate metal layer of the display substrate, which has a relatively high sheet resistance and a relatively low impact on parasitic resistance. Furthermore, the first branch line 111 is fabricated using the first gate metal layer of the display substrate, while the second branch line 112 is fabricated using the first source / drain metal layer of the display substrate. This effectively reduces the parasitic capacitance formed between the partition control line G_com and structures fabricated using the second source / drain metal layer, thereby optimizing the load on the partition control line G_com and achieving optimized partition control.

[0206] As shown in FIG1 , FIG5 , FIG6 , FIG7 , FIG11 , FIG15 , FIG19 and FIG21 , in some embodiments, the display substrate further includes: a plurality of first scan lines G1 , a plurality of second scan lines G2 , a plurality of third scan lines G3 , a plurality of emission control lines EM , a power line VDD , a reference signal line Vref and an initialization signal line Vini ;

[0207] The sub-pixel driving circuit further includes: a compensation transistor T2, a reset transistor T3, a light emitting control transistor T_em and a storage capacitor Cst;

[0208] The gate of the data writing transistor T1 is coupled to the corresponding first scan line G1;

[0209] The gate of the compensation transistor T2 is coupled to the corresponding second scan line G2, the first electrode of the compensation transistor T2 is coupled to the reference signal line Vref, and the second electrode of the compensation transistor T2 is coupled to the first electrode of the write control transistor T_com;

[0210] The gate of the reset transistor T3 is coupled to the corresponding third scan line G3, the first electrode of the reset transistor T3 is coupled to the initialization signal line Vini, and the second electrode of the reset transistor T3 is coupled to the second electrode of the drive transistor DRT;

[0211] The gate of the light emitting control transistor T_em is coupled to the corresponding light emitting control line EM, the first electrode of the light emitting control transistor T_em is coupled to the power line VDD, and the second electrode of the light emitting control transistor T_em is coupled to the first electrode of the driving transistor DRT;

[0212] A first plate Cst1 of the storage capacitor Cst is coupled to the gate of the driving transistor DRT, and a second plate Cst2 of the storage capacitor Cst is coupled to the second electrode of the driving transistor DRT.

[0213] Exemplarily, the initialization signal line Vini includes a plurality of first initial portions 21 and a plurality of second initial portions 22, the plurality of first initial portions 21 are arranged along the second direction, the plurality of second initial portions 22 are arranged along the first direction, the first initial portion 21 includes at least a portion extending along the first direction, the second initial portion 22 includes at least a portion extending along the second direction, the first initial portion 21 is coupled to each of the second initial portions 22, respectively, so that the initialization signal line Vini forms a grid structure, thereby effectively reducing the voltage drop of the initialization signal line Vini.

[0214] As shown in FIG. 5 , illustratively, the active layer is used to form a channel portion, a first electrode, and a second electrode included in each of the transistors.

[0215] As shown in FIG. 5 , illustratively, the first gate metal layer is used to form the gate of each of the transistors, the first branch line 111 and the second initial portion 22 .

[0216] As shown in FIG. 7 , illustratively, the second gate metal layer is used for the second substrate of the storage capacitor Cst.

[0217] As shown in Figure 10, illustratively, the first source-drain metal layer is used to form some conductive connection portions, the reference signal line Vref, the first scan line G1, the second scan line G2, the third scan line G3, the light-emitting control line EM, and the first initial portion 21. The reference signal line Vref, the second scan line G2, the first scan line G1, the second branch line 112, the light-emitting control line EM, the power compensation line 30, the third scan line G3, and the first initial portion 21 coupled to the same repeating unit are arranged sequentially along the second direction.

[0218] Exemplarily, the reference signal line Vref, the first scan line G1, the second scan line G2, the third scan line G3 and the light emitting control line EM each include at least a portion extending along the first direction.

[0219] As shown in FIG14 , the second source-drain metal layer is illustratively used to form the power line VDD, the data line DA, some conductive connection portions, and the auxiliary electrode 40. Exemplarily, the auxiliary electrode 40 includes at least a portion extending along the second direction. The auxiliary electrode 40 is coupled to the second electrode layer via a connection pattern 41 made of indium tin oxide, thereby effectively reducing the voltage drop across the second electrode layer.

[0220] As shown in FIG1 , illustratively, the sub-pixel driving circuit includes: a data writing transistor T1 , a writing control transistor T_com, a driving transistor DRT, a compensation transistor T2 , a reset transistor T3 , a light emitting control transistor T_em, a storage capacitor Cst and an intrinsic capacitor C1 of the light emitting element EL.

[0221] As shown in Figure 9, a via hole formed in the interlayer insulating layer is shown. As shown in Figures 5 to 10, the gate of the compensation transistor T2 is coupled to the corresponding second scan line G2 through the second via hole Via2, and the first electrode of the compensation transistor T2 is coupled to the reference signal line Vref through the first via hole Via1.

[0222] The gate of the data writing transistor T1 is coupled to the corresponding first scan line G1 through the third via hole Via3 , and the first electrode of the data writing transistor T1 is coupled to the fourth conductive connection portion 54 through the ninth via hole Via9 .

[0223] The gate of the write control transistor T_com is coupled to the partition control line G_com through the fourth via Via4, the second electrode of the write control transistor T_com is coupled to the first conductive connection part 51 through the fifth via Via5, and the first conductive connection part 51 is coupled to the gate of the driving transistor DRT through the sixth via Via6. The gate of the driving transistor DRT is reused as the first plate Cst1 of the storage capacitor Cst.

[0224] The second electrode of the drive transistor DRT is coupled to the second conductive connection portion 52 through a seventh via Via7. The second conductive connection portion 52 is coupled to the second plate Cst2 of the storage capacitor Cst through an eighth via Via8. The second plate Cst2 of the storage capacitor Cst is coupled to the third conductive connection portion 53 through a tenth via Via10. The third conductive connection portion 53 is coupled to the second electrode of the reset transistor T3 through a fifteenth via Via15.

[0225] The gate of the light emitting control transistor T_em is coupled to the corresponding light emitting control line EM through an eleventh via hole Via11 , and the first electrode of the light emitting control transistor T_em is coupled to the power line VDD through a twelfth via hole Via12 .

[0226] The gate of the reset transistor T3 is coupled to the third scan line G3 through the fourteenth via hole Via14 , and the first electrode of the reset transistor T3 is coupled to the first initial portion 21 through the thirteenth via hole Via13 .

[0227] The first branch line 111 is coupled to the second branch line 112 through the twenty-second via Via22. The first initial portion 21 is coupled to the second initial portion 22 through the twenty-third via Via23.

[0228] As shown in Figure 12, a via hole formed on the first organic layer is shown. As shown in Figure 13, a via hole formed on the first passivation layer is shown.

[0229] As shown in Figures 11 to 14, the second conductive connection portion 52 is sequentially coupled to the fifth conductive connection portion 55 through the seventeenth via Via17 and the twentieth via Via20. The fourth conductive connection portion 54 is sequentially coupled to the data line DA through the sixteenth via Via16 and the nineteenth via Via19. The power compensation line 30 is once coupled to the power line VDD through the eighteenth via Via18 and the twenty-first via Via21.

[0230] As shown in Figure 16, a via hole formed on the second passivation layer is shown. As shown in Figure 17, a via hole formed on the second organic layer is shown.

[0231] As shown in Figures 15 to 22, the fifth conductive connection portion 55 is sequentially coupled to the corresponding first electrode in the first electrode layer 42 through the twenty-fourth via Via24 and the twenty-sixth via Via26. The auxiliary electrode 40 is sequentially coupled to the connection pattern 41 through the twenty-fifth via Via25 and the twenty-seventh via Via27. The connection pattern 41 is sequentially coupled to the second electrode layer through the twenty-eighth via Via28 and the twenty-ninth via Via29.

[0232] As shown in FIG. 23 , an opening region 60 of a pixel and a non-opening region 61 located near the opening region 60 are schematically illustrated.

[0233] As shown in FIG. 1 , in some embodiments, the data writing transistor T1 , the compensation transistor T2 , and the reset transistor T3 all include a dual-gate structure, which can effectively reduce leakage current.

[0234] As shown in FIG. 1 , in some embodiments, the write control transistor T_com includes a single-gate structure.

[0235] Since the data write transistor T1 is connected between the data line DA and the write control transistor T_com, when the write control transistor T_com is turned off, the leakage path of the data write transistor T1 can be closed. The write control transistor T_com adopts a single-gate structure design, which is conducive to saving layout area.

[0236] The present disclosure also provides a method for driving a display substrate, which is used to drive the display substrate provided by the above embodiment. The method includes:

[0237] During an N-th frame display period, partition control signals transmitted by at least some of the plurality of partition control lines G_com in the display substrate are at an effective level, and write control transistors T_com coupled to at least some of the partition control lines G_com are turned on, thereby performing row-by-row scanning on the plurality of sub-pixels and implementing row-by-row writing of data signals.

[0238] During the N+1 frame display period, the levels of the partition control signals transmitted by the multiple partition control lines G_com change, causing the write control transistor T_com coupled to the partition control line G_com that transmits the partition control signal of the valid level to be turned on, and the multiple sub-pixels are scanned row by row to realize the writing of data signals row by row.

[0239] Take the display substrate including X control areas as an example.

[0240] For example, in the Nth frame display period, the first partition control line G_com in the display substrate <1> and the Mth partition control line G_com <m>The transmitted control signals are all at the effective level VGH, and the corresponding first partition control line G_com <1> All write control transistors T_com included in the corresponding first control area are turned on, and the Mth partition control line G_com <m>All the write control transistors T_com included in the corresponding M-th control area are turned on, which can ensure that the first control area and the M-th control area are areas where normal refresh can be achieved. When the display substrate is scanned line by line, high refresh operation can be achieved in the first control area and the M-th control area. In the N+1 frame display period, the levels of the partition control signals transmitted by the multiple partition control lines G_com change, so that the first partition control line G_com <1> and the Hth partition control line G_com <h>The transmitted control signals are all at the effective level VGH, and the corresponding first partition control line G_com <1> All the write control transistors T_com included in the corresponding first control area are turned on, and the Hth partition control line G_com <h>All write control transistors T_com included in the corresponding Hth control area are turned on, which can ensure that the first control area and the Hth control area are areas where normal refresh can be achieved. When the display substrate is scanned line by line, high refresh operations can be achieved in the first control area and the Hth control area.

[0241] When scanning the display substrate row by row to write data signals, the sub-pixel driving circuits in every two rows or every four rows can be controlled to simultaneously perform resetting and compensation according to actual needs.

[0242] When the driving method provided in the embodiment of the present disclosure is used to drive the display substrate, each partition control line G_com can be used to control whether all the write control transistors T_com in the corresponding control area are turned on, so as to achieve the effect of controlling whether the area achieves a high refresh frequency, so that a large-size display substrate can also well achieve the high refresh rate function of the display substrate.

[0243] In some embodiments, the driving method further includes:

[0244] A blanking period is located at the beginning or end of each frame display period; during the blanking period, the levels of the partition control signals transmitted by the plurality of partition control lines are adjusted.

[0245] Exemplarily, at the end of the Nth frame and when entering the blanking period of the N+1th frame, the control signal transmitted by the partition control line G_com is immediately adjusted.

[0246] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0247] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0248] Exemplarily, the display device includes an organic light emitting diode display device, but is not limited thereto.

[0249] The display substrate provided in the above embodiment includes multiple control areas, each of which includes at least one column of repeating units. The partition control lines are respectively coupled to the gates of the write control transistors included in each repeating unit column in the corresponding control area. Each partition control line can control whether all write control transistors in the corresponding control area are turned on, thereby achieving the effect of controlling whether the area achieves a high refresh rate. In the display substrate provided in the above embodiment, by providing the control areas and partition control lines, the high refresh rate function of the display substrate can also be well achieved in large-scale display substrates.

[0250] The display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0251] It should be noted that the signal line extends along a certain direction means that: the signal line includes a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along a certain direction, and the length of the main part extended along the certain direction is greater than the length of the secondary part extended along other directions.

[0252] It should be noted that in the embodiments of the present disclosure, "the same layer" may refer to film layers on the same structural layer. Alternatively, for example, the film layers on the same layer may be formed using the same film-forming process to form a specific pattern, and then patterned using the same mask through a single patterning process to form the layer structure. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0253] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0254] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0255] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" and the like mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0256] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0257] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0258] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.< / h> < / h> < / m> < / m> < / m> < / m> < / h> < / h> < / h> < / h> < / m> < / m>

Claims

1. A display substrate, comprising: A base substrate, and a plurality of data lines and a plurality of sub-pixels disposed on the base substrate; The sub-pixel includes a sub-pixel driving circuit and a light-emitting element; The sub-pixel driving circuit includes a driving transistor and a data writing transistor, and the light emitting element includes a first electrode; The second electrode of the driving transistor is coupled to the corresponding first electrode through a first connection structure; the first electrode of the data writing transistor is coupled to the corresponding data line through a second connection structure; The first connection structure and the second connection structure are both located in the non-opening area of ​​the sub-pixel, and the orthographic projection of the first connection structure on the base substrate and the orthographic projection of the second connection structure on the base substrate are arranged along a first direction; The orthographic projection of the second connection structure on the base substrate is arranged along a second direction with the opening area of ​​the sub-pixel, and the second direction intersects with the first direction.

2. The display substrate according to claim 1, wherein: The first connection structure includes: a second conductive connection portion, a first via structure, a fifth conductive connection portion and a second via structure; The second conductive connection portion is coupled to the second electrode of the driving transistor, the second conductive connection portion is coupled to the fifth conductive connection portion through the first via structure, and the fifth conductive connection portion is coupled to the corresponding first electrode through the second via structure.

3. The display substrate according to claim 2, wherein: The second connection structure includes: a fourth conductive connection portion and a third via structure; the fourth conductive connection portion is coupled to the first electrode of the data writing transistor, and the fourth conductive connection portion is coupled to the corresponding data line through the third via structure.

4. The display substrate according to claim 3, wherein: The display substrate further includes a first organic layer and a second organic layer stacked in sequence in a direction away from the base substrate, the first via structure penetrates the first organic layer, and the second via structure penetrates the second organic layer; The second conductive connection portion is located between the first organic layer and the base substrate, and the fifth conductive connection portion is located between the first organic layer and the second organic layer.

5. The display substrate according to claim 4, wherein: The third via structure penetrates the first organic layer, and the fourth conductive connection portion is located between the first organic layer and the base substrate.

6. The display substrate according to claim 5, wherein: The display substrate further includes: a first passivation layer and a second passivation layer; the first passivation layer is located between the first organic layer and the second passivation layer, and the second passivation layer is located between the first passivation layer and the second organic layer; The first via structure and the third via structure both penetrate the first passivation layer, and the second via structure penetrates the second passivation layer; the fifth conductive connection portion is located between the first passivation layer and the second passivation layer.

7. The display substrate according to claim 1, wherein: The display substrate further includes: an auxiliary electrode, a third connection structure and a second electrode layer; the auxiliary electrode is coupled to the second electrode layer through the third connection structure; The third connection structure is located in the non-opening area of ​​the sub-pixel, and the orthographic projection of the third connection structure on the base substrate is arranged along a first direction with the orthographic projection of the first connection structure on the base substrate.

8. The display substrate according to claim 1, wherein: The display substrate further includes: an auxiliary electrode, a third connection structure and a second electrode layer; the auxiliary electrode is coupled to the second electrode layer through the third connection structure; The third connection structure is located in the non-opening area of ​​the sub-pixel, and the orthographic projection of the third connection structure on the base substrate is at least partially offset from the orthographic projection of the first connection structure on the base substrate.

9. The display substrate according to claim 7 or 8, wherein: The display substrate further comprises a second organic layer and a pixel defining layer which are sequentially stacked in a direction away from the base substrate; The third connection structure includes: a fourth via structure, a connection pattern and a fifth via structure; the auxiliary electrode is located between the second organic layer and the base substrate, at least a portion of the second electrode layer is located on a side of the pixel defining layer facing away from the base substrate, at least a portion of the connection pattern is located between the second organic layer and the pixel defining layer, the fourth via structure penetrates the second organic layer, and the fifth via structure penetrates the pixel defining layer; The connection pattern is coupled to the auxiliary electrode through the fourth via structure, and the connection pattern is coupled to the second electrode layer through the fifth via structure.

10. The display substrate according to claim 9, wherein: The plurality of sub-pixels are divided into a plurality of repeating units distributed in an array, each repeating unit includes two sub-units arranged along a first direction, and each sub-unit includes a plurality of the sub-pixels arranged along the first direction; The orthographic projection of the auxiliary electrode on the base substrate is located between the orthographic projections of the two sub-units on the base substrate.

11. The display substrate according to claim 10, wherein: The display substrate also includes a power line and a power compensation line; The sub-pixel driving circuit further includes a light emitting control transistor; a first electrode of the light emitting control transistor is coupled to the power supply compensation line, and a second electrode of the light emitting control transistor is coupled to a first electrode of the driving transistor; The power compensation line is coupled to the power line through a sixth via structure, and the sixth via structure is located in a non-opening area of ​​the sub-pixel.

12. The display substrate according to claim 11, wherein: The display substrate further includes a first organic layer, the power compensation line is located between the first organic layer and the base substrate, the power line is located on a side of the first organic layer facing away from the base substrate, and the sixth via structure penetrates the first organic layer.

13. The display substrate according to claim 11, wherein: The orthographic projection of the power line on the base substrate and the orthographic projection of the repeating unit on the base substrate are alternately arranged along the first direction.

14. The display substrate according to claim 1, wherein: The display substrate further includes: a plurality of light emitting control lines, a power supply line, an initialization signal line, a reference signal line, a plurality of first scanning lines, a plurality of second scanning lines, a plurality of third scanning lines and a plurality of partition control lines; The sub-pixel driving circuit further includes: a compensation transistor, a reset transistor, a light emitting control transistor, a write control transistor and a storage capacitor; The gate of the data writing transistor is coupled to the corresponding first scanning line, and the second electrode of the data writing transistor is coupled to the first electrode of the writing control transistor; The second electrode of the write control transistor is coupled to the gate of the drive transistor, and the gate of the write control transistor is coupled to the corresponding partition control line; The gate of the compensation transistor is coupled to the corresponding second scan line, the first electrode of the compensation transistor is coupled to the reference signal line, and the second electrode of the compensation transistor is coupled to the first electrode of the write control transistor; The gate of the reset transistor is coupled to the corresponding third scan line, the first electrode of the reset transistor is coupled to the initialization signal line, and the second electrode of the reset transistor is coupled to the second electrode of the drive transistor; The gate of the light emitting control transistor is coupled to the corresponding light emitting control line, the first electrode of the light emitting control transistor is coupled to the power line, and the second electrode of the light emitting control transistor is coupled to the first electrode of the driving transistor; The first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the second electrode of the driving transistor.

15. A display device comprising the display substrate according to any one of claims 1 to 14.

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