Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a plurality of repeating units (100); a repeating unit (100) comprises a display area (110) and a light-transmissive area (120); the display area (110) comprises a plurality of sub-pixels; a sub-pixel comprises a pixel driving circuit and a light emitting device; the pixel driving circuit comprises a first electrode plate (11), and the light emitting device comprises a first electrode (61); the display substrate comprises a plurality of conductive layers; the first electrode plate (11), an electrode plate connection electrode (50), and a first electrode (61) are arranged in different conductive layers; the first electrode plate (11) is connected to the electrode plate connection electrode (50) by means of a first electrode plate via hole (BV), and the first electrode (61) is connected to the electrode plate connection electrode (50) by means of a second electrode plate via hole (YV); the second electrode plate via hole (YV) is arranged on the side of the first electrode plate via hole (BV) close to the light-transmissive area (120).

Description

Display substrate and manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) are active light-emitting display devices. They offer advantages such as active illumination, ultra-thinness, wide viewing angles, high brightness, high contrast, low power consumption, extremely fast response times, lightweight design, customizable form factors, and flexible displays. They are becoming a highly promising next-generation display technology. Active Matrix (AM) OLEDs are current-driven devices that use independent thin film transistors (TFTs) to control each sub-pixel, allowing each sub-pixel to emit light continuously and independently.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, an embodiment of the present disclosure provides a display substrate, which in an exemplary embodiment includes multiple repeating units, at least one repeating unit includes a display area and a light-transmitting area located on at least one side of the display area, the display area is configured to display an image, and the light-transmitting area is configured to transmit light; the display area includes multiple sub-pixels, at least one sub-pixel includes a pixel driving circuit and a light-emitting device, the pixel driving circuit includes at least a storage capacitor, the storage capacitor includes at least a first plate, the light-emitting device includes at least a first electrode, and the first electrode is connected to the first plate through a plate connecting electrode; in a direction perpendicular to the display substrate, the display substrate includes at least multiple conductive layers arranged on a base, the first plate, the plate connecting electrode and the first electrode are arranged in different conductive layers, the first plate is connected to the plate connecting electrode through a first plate via, and the first electrode is connected to the plate connecting electrode through a second plate via, and in at least one sub-pixel, the second plate via is arranged on the side of the first plate via close to the light-transmitting area.

[0006] In an exemplary embodiment, the display area further includes a first power line, which is configured to provide a first power signal to the pixel driving circuit, and the first power line is arranged on a side of the display area close to the light-transmitting area; the first plate via is arranged on a side of the first power line away from the light-transmitting area, and the second plate via is arranged on a side of the first power line close to the light-transmitting area, and the orthographic projection of the plate connecting electrode on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate.

[0007] In an exemplary embodiment, the display area further includes a second power line, which is configured to provide a second power signal to the light-emitting device, and the second power line is arranged on a side of the display area close to the light-transmitting area; the first plate via is arranged on a side of the second power line away from the light-transmitting area, and the second plate via is arranged on a side of the second power line close to the light-transmitting area, and the orthographic projection of the plate connecting electrode on the substrate at least partially overlaps with the orthographic projection of the second power line on the substrate.

[0008] In an exemplary embodiment, the light-transmitting area further includes at least one first auxiliary electrode and at least one second auxiliary electrode, the second auxiliary electrode is connected to the first auxiliary electrode through an auxiliary electrode via, and the first auxiliary electrode is connected to the second power line; there is a first distance between an edge of the second plate via away from the second power line and an edge of the second power line close to the second plate via, and there is a second distance between an edge of at least one auxiliary electrode via away from the second power line and an edge of the second power line close to the auxiliary electrode via, and the first distance is less than the second distance.

[0009] In an exemplary embodiment, an orthographic projection area of ​​the auxiliary electrode via hole on the substrate is larger than an orthographic projection area of ​​the second plate via hole on the substrate.

[0010] In an exemplary embodiment, an orthographic projection area of ​​the second plate via on the substrate is larger than an orthographic projection area of ​​the first plate via on the substrate.

[0011] In an exemplary embodiment, the multiple conductive layers include at least a first conductive layer arranged on the substrate, a second conductive layer arranged on a side of the first conductive layer away from the substrate, and a third conductive layer arranged on a side of the second conductive layer away from the substrate, the first electrode is arranged in the first conductive layer, the electrode connecting electrode is arranged in the second conductive layer, and the first electrode is arranged in the third conductive layer.

[0012] In an exemplary embodiment, the display substrate further includes a first insulating layer, a second insulating layer, and a third insulating layer, the first insulating layer being arranged on a side of the first conductive layer away from the substrate, the second insulating layer being arranged on a side of the first insulating layer away from the substrate, the second conductive layer being arranged on a side of the second insulating layer away from the substrate, the third insulating layer being arranged on a side of the second conductive layer away from the substrate, and the third conductive layer being arranged on a side of the third insulating layer away from the substrate; the first electrode via is arranged in the first insulating layer and the second insulating layer, and the second electrode via is arranged in the third insulating layer.

[0013] In an exemplary embodiment, in at least one sub-pixel, the storage capacitor further includes a second plate, an orthographic projection of the second plate on the substrate at least partially overlaps with an orthographic projection of the first plate on the substrate, and the second plate is arranged on the same layer as the plate connecting electrode.

[0014] In an exemplary embodiment, in at least one sub-pixel, a plate groove is provided on the second plate, and the orthographic projection of the first plate via hole on the substrate is located within the range of the orthographic projection of the plate groove on the substrate.

[0015] In an exemplary embodiment, in at least one sub-pixel, the plate connecting electrode includes at least a first sub-connecting electrode and a second sub-connecting electrode, the first end of the first sub-connecting electrode is connected to the first plate through the first plate via, the second end of the first sub-connecting electrode extends toward the direction close to the light-transmitting area and is connected to the second sub-connecting electrode, and the first electrode is connected to the second sub-connecting electrode through the second plate via.

[0016] In an exemplary embodiment, in at least one sub-pixel, the first sub-connecting electrode and the second sub-connecting electrode are provided in the same layer and are connected to each other as an integral structure.

[0017] In an exemplary embodiment, in at least one sub-pixel, the first electrode includes at least a first sub-electrode, a second sub-electrode and a sub-connecting electrode, the first sub-electrode and the second sub-electrode are isolated from each other, the sub-connecting electrode is in a "C" shape, the first end of the sub-connecting electrode is connected to the first sub-electrode, the second end of the sub-connecting electrode is connected to the second sub-electrode, and the area between the first end and the second end is connected to the plate connecting electrode through the second plate via.

[0018] In an exemplary embodiment, in at least one sub-pixel, the first sub-electrode, the second sub-electrode, and the sub-connecting electrode are provided in the same layer and are interconnected as an integral structure.

[0019] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the first sub-electrode on the substrate does not overlap with the orthographic projection of the first electrode via on the substrate, and the orthographic projection of the second sub-electrode on the substrate does not overlap with the orthographic projection of the first electrode via on the substrate.

[0020] In an exemplary embodiment, in at least one sub-pixel, the display area further includes a second electrode disposed on a side of the first electrode away from the substrate, the second electrode includes a third sub-electrode and a fourth sub-electrode disposed in isolation, the orthographic projection of the third sub-electrode on the substrate at least partially overlaps with the orthographic projection of the first sub-electrode on the substrate, the third sub-electrode overlaps with the first sub-electrode, the orthographic projection of the fourth sub-electrode on the substrate at least partially overlaps with the orthographic projection of the second sub-electrode on the substrate, the fourth sub-electrode overlaps with the second sub-electrode, the orthographic projection of the third sub-electrode on the substrate does not overlap with the orthographic projection of the first electrode plate via on the substrate, and the orthographic projection of the fourth sub-electrode on the substrate does not overlap with the orthographic projection of the first electrode plate via on the substrate.

[0021] In an exemplary embodiment, the display substrate further includes a pixel definition layer disposed on a side of the second electrode away from the substrate, and in at least one sub-pixel, a first pixel opening and a second pixel opening are disposed on the pixel definition layer, the first pixel opening exposing the third sub-electrode, the second pixel opening exposing the fourth sub-electrode, the orthographic projection of the first pixel opening on the substrate does not overlap with the orthographic projection of the first electrode plate via on the substrate, and the orthographic projection of the second pixel opening on the substrate does not overlap with the orthographic projection of the first electrode plate via on the substrate.

[0022] In an exemplary embodiment, in the light-transmitting area, a light-transmitting opening is provided on the pixel definition layer, and an orthographic projection of the light-transmitting opening on the substrate does not overlap with an orthographic projection of the second plate via on the substrate.

[0023] On the other hand, an embodiment of the present disclosure further provides a display device, comprising the aforementioned display substrate.

[0024] In yet another aspect, embodiments of the present disclosure further provide a method for preparing a display substrate, the display substrate comprising a plurality of repeating units, at least one repeating unit comprising a display area and a light-transmitting area located on at least one side of the display area, the display area being configured to display an image, and the light-transmitting area being configured to transmit light; the display area comprising a plurality of sub-pixels, at least one sub-pixel comprising a pixel driving circuit and a light-emitting device, the pixel driving circuit comprising at least a storage capacitor, the storage capacitor comprising at least a first plate, the light-emitting device comprising at least a first electrode, the first electrode being connected to the first plate via a plate connecting electrode; the preparation method comprising:

[0025] Multiple conductive layers are formed on the substrate, the first plate, the plate connecting electrode and the first electrode are arranged in different conductive layers, the first plate is connected to the plate connecting electrode through a first plate via, the first electrode is connected to the plate connecting electrode through a second plate via, and in at least one sub-pixel, the second plate via is arranged on a side of the first plate via close to the light-transmitting area.

[0026] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0028] FIG1 is a schematic structural diagram of a display device;

[0029] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0030] FIG3 is a schematic diagram showing the arrangement of sub-pixels in a substrate according to an exemplary embodiment of the present disclosure;

[0031] FIG4 is an equivalent circuit diagram of a pixel driving circuit in a display unit according to an exemplary embodiment of the present disclosure;

[0032] FIG5 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0033] FIG6 is a cross-sectional view taken along line AA in FIG5 ;

[0034] FIG7 is a schematic diagram of an embodiment of the present disclosure after forming a first conductive layer pattern;

[0035] 8A and 8B are schematic diagrams of a semiconductor layer pattern formed according to an embodiment of the present disclosure;

[0036] FIG9 is a schematic diagram of an embodiment of the present disclosure after forming a second insulating layer pattern;

[0037] 10A and 10B are schematic diagrams of an embodiment of the present disclosure after forming a second conductive layer pattern;

[0038] FIG11 is a schematic diagram of an embodiment of the present disclosure after forming patterns of a third insulating layer and a planar layer;

[0039] 12A and 12B are schematic diagrams of an embodiment of the present disclosure after forming a third conductive layer pattern;

[0040] 13A and 13B are schematic diagrams of an embodiment of the present disclosure after forming a fourth conductive layer pattern;

[0041] FIG. 14 is a schematic diagram of an embodiment of the present disclosure after forming a pixel definition layer pattern.

[0042] Explanation of Reference Numerals: 10—substrate; 11—first plate; 12—second plate; 13—second gate electrode; 21—first active layer; 22—second active layer; 23—third active layer; 30—scanning signal line; 30-1—double line segment; 30-2—single line segment; 31—first auxiliary power line; 32—second auxiliary power line; 33—first power connection line; 34—second power connection line; 35—first auxiliary electrode; 36—second auxiliary electrode; 37—third auxiliary electrode; 41—first connection electrode; 42—second connection electrode; 43—third connection electrode; 44—fourth connection electrode; 45—fifth connection electrode; 46—sixth connection electrode; 50—plate connection electrode; 50-1—first sub-connection electrode; 50-2—second sub-connection electrode; 51—first power line; 52—second power line; 53—Data signal line; 54—Compensation signal line; 61—First electrode; 61-1—First sub-electrode; 61-2—Second sub-electrode; 61-3—Sub-connecting electrode; 62—Second electrode; 62-1—Third sub-electrode; 62-2—Fourth sub-electrode; 71—First insulating layer; 72—Second insulating layer; 73—Third insulating layer; 74—Planning layer; 75—Pixel definition layer; 100—Repeating unit; 110—Display area; 120—Light-transmitting area. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0044] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0045] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0046] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0047] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0048] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0049] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0050] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0051] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0052] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0053] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0054] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0055] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the OLED display device may include a timing controller, a data driver, a scan driver, and a pixel array. The timing controller is respectively connected to the data driver and the scan driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The pixel array may include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line and a corresponding scan signal line. i and j may be natural numbers. At least one sub-pixel Pxij may include at least a circuit unit and a display unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to the scan signal line and the data signal line. The display unit may include at least a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the circuit unit. Sub-pixel Pxij may refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and the j-th data signal line. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver. The data driver can generate data voltages to be provided to data signal lines 530, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines 530 to Dn in units of pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next-level circuit under the control of a clock signal. m can be a natural number. In an exemplary embodiment, the pixel array can be provided on a display substrate.

[0056] With the continuous development of display technology, OLED technology is increasingly being used in transparent displays. Transparent display is an important personalized display field in display technology. It refers to the display of images in a transparent state. Viewers can not only see the image in the display device, but also the scene behind the display device, which can realize virtual reality (VR), augmented reality (AR) and 3D display functions. Transparent display devices using OLED technology usually divide each sub-pixel into a display area and a light-transmitting area. The display area is equipped with pixel driving circuits and light-emitting devices to realize image display, and the light-transmitting area allows light to pass through.

[0057] FIG2 is a schematic diagram of a planar structure of a display substrate. As shown in FIG2 , in an exemplary embodiment, the display substrate may include a plurality of regularly arranged repeating units 100, and at least one repeating unit 100 may include a display area 110 and a light-transmitting area 120. The display area 110 may include a plurality of sub-pixels, and at least one sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, and the light-emitting unit may include at least a light-emitting device. The light-emitting device of the light-emitting unit is connected to the pixel driving circuit of the corresponding circuit unit, and the display area 110 is configured to display an image. The light-transmitting area 120 may be located on at least one side of the display area 110 in the repeating unit 100. The light-transmitting area 120 is configured to transmit light, so that the repeating unit 100 can realize image display in a transparent state, i.e., transparent display. In an exemplary embodiment, the repeating unit is the basic unit that constitutes the display substrate. The display substrate is formed by repeating and continuously arranging it along at least one direction, i.e., the display substrate is spliced ​​by a plurality of repeating units.

[0058] An exemplary embodiment of the present disclosure provides a display substrate, comprising a plurality of repeating units, at least one repeating unit comprising a display area and a light-transmitting area located on at least one side of the display area, the display area being configured to display an image, and the light-transmitting area being configured to transmit light; the display area comprising a plurality of sub-pixels, at least one sub-pixel comprising a pixel driving circuit and a light-emitting device, the pixel driving circuit comprising at least a storage capacitor, the storage capacitor comprising at least a first plate, the light-emitting device comprising at least a first electrode, the first electrode being connected to the first plate via a plate connecting electrode; in a direction perpendicular to the display substrate, the display substrate comprises at least a plurality of conductive layers arranged on a base, the first plate, the plate connecting electrode, and the first electrode being arranged in different conductive layers, the first plate being connected to the plate connecting electrode via a first plate via, the first electrode being connected to the plate connecting electrode via a second plate via, and in at least one sub-pixel, the second plate via being arranged on a side of the first plate via close to the light-transmitting area.

[0059] In an exemplary embodiment, the display area further includes a first power line, which is configured to provide a first power signal to the pixel driving circuit, and the first power line is arranged on a side of the display area close to the light-transmitting area; the first plate via is arranged on a side of the first power line away from the light-transmitting area, and the second plate via is arranged on a side of the first power line close to the light-transmitting area, and the orthographic projection of the plate connecting electrode on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate.

[0060] In an exemplary embodiment, the display area further includes a second power line, which is configured to provide a second power signal to the light-emitting device, and the second power line is arranged on a side of the display area close to the light-transmitting area; the first plate via is arranged on a side of the second power line away from the light-transmitting area, and the second plate via is arranged on a side of the second power line close to the light-transmitting area, and the orthographic projection of the plate connecting electrode on the substrate at least partially overlaps with the orthographic projection of the second power line on the substrate.

[0061] In an exemplary embodiment, the display substrate further includes at least one first auxiliary electrode and at least one second auxiliary electrode, the first auxiliary electrode and the second auxiliary electrode are arranged in the light-transmitting area, the light-emitting device further includes a third electrode, the third electrode is connected to the second auxiliary electrode, the second auxiliary electrode is connected to the first auxiliary electrode through an auxiliary electrode via, and the first auxiliary electrode is connected to the second power line; there is a first distance between an edge of the second plate via away from the second power line and an edge of the second power line close to the second plate via, and there is a second distance between an edge of at least one auxiliary electrode via away from the second power line and an edge of the second power line close to the auxiliary electrode via, and the first distance is less than the second distance.

[0062] In an exemplary embodiment, an orthographic projection area of ​​the auxiliary electrode via hole on the substrate is larger than an orthographic projection area of ​​the second plate via hole on the substrate.

[0063] In an exemplary embodiment, an orthographic projection area of ​​the second plate via on the substrate is larger than an orthographic projection area of ​​the first plate via on the substrate.

[0064] In an exemplary embodiment, the multiple conductive layers include at least a first conductive layer arranged on the substrate, a second conductive layer arranged on a side of the first conductive layer away from the substrate, and a third conductive layer arranged on a side of the second conductive layer away from the substrate, the first electrode is arranged in the first conductive layer, the electrode connecting electrode is arranged in the second conductive layer, and the first electrode is arranged in the third conductive layer.

[0065] In an exemplary embodiment, the display substrate further includes a first insulating layer, a second insulating layer, and a third insulating layer, the first insulating layer being arranged on a side of the first conductive layer away from the substrate, the second insulating layer being arranged on a side of the first insulating layer away from the substrate, the second conductive layer being arranged on a side of the second insulating layer away from the substrate, the third insulating layer being arranged on a side of the second conductive layer away from the substrate, and the third conductive layer being arranged on a side of the third insulating layer away from the substrate; the first electrode via is arranged in the first insulating layer and the second insulating layer, and the second electrode via is arranged in the third insulating layer.

[0066] The display substrate of the present disclosure is described below by way of some exemplary embodiments.

[0067] In an exemplary embodiment, the display substrate may include a plurality of regularly arranged repeating units parallel to the display substrate, with at least one repeating unit including a display area and a light-transmitting area. The display area is configured to display an image, and the light-transmitting area is configured to transmit light, thereby achieving a transparent display. In a direction perpendicular to the display substrate, the display substrate may include at least a driving circuit layer disposed on a base and a light-emitting structure layer disposed on a side of the driving circuit layer away from the base. In at least one repeating unit, the driving circuit layer in the display area may include a plurality of circuit units, and the light-emitting structure layer in the display area may include a plurality of light-emitting units. The circuit units may include at least pixel driving circuits, and the light-emitting units may include at least light-emitting devices, which are connected to the pixel driving circuits of corresponding circuit units.

[0068] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0069] In the exemplary embodiment of the present disclosure, the position of the circuit unit's orthographic projection on the substrate corresponds one-to-one to the position of the light-emitting unit's orthographic projection on the substrate. The circuit unit and the light-emitting unit constitute a sub-pixel. Therefore, in the following content, sub-pixels are uniformly used to refer to the circuit unit and the light-emitting unit.

[0070] Figure 3 is a schematic diagram of the arrangement of subpixels in a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a repeating unit. As shown in Figure 3, the repeating unit may include a display area 110 and a light-transmitting area 120. The display area 110 may be located on one side of the light-transmitting area 120 in a first direction X. In an exemplary embodiment, the display area 110 may include four subpixels: a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4. The four subpixels may be arranged in a square to effectively increase the aperture ratio and the area of ​​the light-transmitting area.

[0071] In an exemplary embodiment, the second subpixel P2 may be disposed on one side of the first subpixel P1 in the first direction X, the third subpixel P3 may be disposed on one side of the first subpixel P1 in the second direction Y, and the fourth subpixel P4 may be disposed on one side of the third subpixel P3 in the first direction X. A plurality of subpixels sequentially disposed along the first direction X may be referred to as a pixel row, and a plurality of subpixels sequentially disposed along the second direction Y may be referred to as a pixel column. The first direction X intersects the second direction Y.

[0072] In an exemplary embodiment, the first subpixel P1 may be a white subpixel (W) that emits white light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, the third subpixel P3 may be a red subpixel (R) that emits red light, and the fourth subpixel P4 may be a green subpixel (G) that emits green light. In some possible embodiments, the arrangement of WRBG can be adjusted according to actual needs and is not specifically limited in this disclosure.

[0073] In an exemplary embodiment, each sub-pixel may include at least a pixel driving circuit and a light emitting device, and the light emitting device is connected to the pixel driving circuit.

[0074] Figure 4 is an equivalent circuit diagram of a pixel driving circuit in a display unit according to an exemplary embodiment of the present disclosure. As shown in Figure 4, at least one display unit may include four pixel driving circuits, which may be arranged in a square configuration and may have a 3T1C structure.

[0075] In an exemplary embodiment, at least one pixel driving circuit may include three transistors (a first transistor T1, a second transistor T2, and a third transistor T3) and a storage capacitor C, and the pixel driving circuit is respectively connected to the scanning signal line 30, the first power line 51, the data signal line 53, and the compensation signal line 54.

[0076] In an exemplary embodiment, the pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first end of the storage capacitor C, respectively. The second node N2 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second end of the storage capacitor C, respectively.

[0077] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , a second end of the storage capacitor C is connected to the second node N2 , and the storage capacitor C is used to store the potential of the gate electrode of the second transistor T2 .

[0078] In an exemplary embodiment, the first transistor T1 may function as a data writing transistor, the second transistor T2 may function as a driving transistor, and the third transistor T3 may function as a compensation transistor.

[0079] In the exemplary embodiment, a gate electrode of the first transistor T1 is connected to the scan signal line 30, a first electrode of the first transistor T1 is connected to the data signal line 53, and a second electrode of the first transistor T1 is connected to the first node N1. When a turn-on signal is applied to the scan signal line 30, the first transistor T1 inputs a data signal of the data signal line 53 to the gate electrode of the second transistor T2.

[0080] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the first node N1, a first electrode of the second transistor T2 is connected to the first power line 51, and a second electrode of the second transistor T2 is connected to the second node N2. The second transistor T2 generates a corresponding current at its second electrode under the control of the data signal received at its gate electrode.

[0081] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the scan signal line 30, a first electrode of the third transistor T3 is connected to the compensation signal line 54, and a second electrode of the third transistor T3 is connected to the second node N2. When a turn-on signal is applied to the scan signal line 30, the third transistor T3 extracts the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing to compensate for the threshold voltage Vth.

[0082] In an exemplary embodiment, in the pixel driving circuit of at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 30 .

[0083] In an exemplary embodiment, in two pixel driving circuits of at least one pixel row, the gate electrodes of the two first transistors T1 and the gate electrodes of the two third transistors T3 are connected to the same scan signal line 30 .

[0084] In an exemplary embodiment, in the four pixel driving circuits of at least one repeating unit, the gate electrodes of the four first transistors T1 and the gate electrodes of the four third transistors T3 are connected to the same scan signal line 30 .

[0085] In an exemplary embodiment, the light-emitting device EL may be an OLED, including a stacked first electrode, an organic light-emitting layer, and a second electrode, or a QLED, including a stacked first electrode, a quantum dot light-emitting layer, and a second electrode. The first electrode of the light-emitting device EL is connected to the second node N2, and the second electrode of the light-emitting device EL is connected to the second power line 52. The light-emitting device EL emits light of a corresponding brightness in response to the current flowing through the second electrode of the second transistor T2. In an exemplary embodiment, the first electrode may be an anode, and the second electrode may be a cathode; alternatively, the first electrode may be a cathode, and the second electrode may be an anode.

[0086] In an exemplary embodiment, the signal of the first power line 51 is a continuously provided high-level signal, and the signal of the second power line 52 is a continuously provided low-level signal.

[0087] In an exemplary embodiment, the first to third transistors T1 to T3 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first to third transistors T1 to T3 may include P-type transistors and N-type transistors.

[0088] In an exemplary embodiment, the first transistor T1 to the third transistor T3 may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, can leverage the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0089] Figure 5 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a repeating unit. In an exemplary embodiment, the display substrate may include a plurality of regularly arranged repeating units, at least one of which may include a display area 110 and a light-transmitting area 120 located on at least one side of the display area 110. The display area 110 is configured to display an image, and the light-transmitting area 120 is configured to transmit light. The display area 110 may include a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4 arranged in a square manner. The second subpixel P2 may be arranged on one side of the first subpixel P1 in the first direction X, the third subpixel P3 may be arranged on one side of the first subpixel P1 in the second direction Y, and the fourth subpixel P4 may be arranged on one side of the third subpixel P3 in the first direction X, where the first direction X intersects the second direction Y. At least one subpixel may include a pixel driving circuit and a light-emitting device, and the light-emitting device is connected to the pixel driving circuit.

[0090] As shown in FIG5 , in an exemplary embodiment, in at least one sub-pixel, the pixel driving circuit may include at least a storage capacitor, which may include at least a first plate 11 and a second plate 12, wherein the orthographic projection of the second plate 12 on the display substrate plane at least partially overlaps with the orthographic projection of the first plate 11 on the display substrate plane. The light-emitting device may include at least a first electrode 61, which may be connected to the first plate 11 via a plate connecting electrode 50.

[0091] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a plurality of conductive layers arranged on a base, the first plate 11, the plate connecting electrode 50, and the first electrode 61 may be arranged in different conductive layers, the plate connecting electrode 50 may be connected to the first plate 11 through a first plate via BV, and the first electrode 61 may be connected to the plate connecting electrode 50 through a second plate via YV. In at least one sub-pixel, the second plate via YV may be arranged on a side of the first plate via BV close to the light-transmitting region 120, that is, the second plate via YV is arranged in a region closer to the light-transmitting region 120 than the first plate via BV.

[0092] In an exemplary embodiment, an orthographic projection area of ​​the second plate via YV on the substrate may be larger than an orthographic projection area of ​​the first plate via BV on the substrate.

[0093] In an exemplary embodiment, the multiple conductive layers of the display substrate may include at least a first conductive layer disposed on the substrate, a second conductive layer disposed on a side of the first conductive layer away from the substrate, and a third conductive layer disposed on a side of the second conductive layer away from the substrate. The first electrode 11 may be disposed in the first conductive layer, the electrode connecting electrode 50 may be disposed in the second conductive layer, and the first electrode 61 may be disposed in the third conductive layer.

[0094] In an exemplary embodiment, the second electrode 12 and the electrode connecting electrode 50 may be provided in the same layer and formed simultaneously through the same patterning process.

[0095] In an exemplary embodiment, a plate groove 12-1 may be provided on one side of the second plate 12 close to the light-transmitting area 120, and the plate groove 12-1 is configured to accommodate the first plate via BV. The orthographic projection of the first plate via BV on the substrate may be located within the range of the orthographic projection of the plate groove 12-1 on the substrate.

[0096] In an exemplary embodiment, in at least one sub-pixel, the plate connecting electrode 50 may include at least a first sub-connecting electrode 50-1 and a second sub-connecting electrode 50-2, the first sub-connecting electrode 50-1 may be in the shape of a strip extending along the first direction X, the second sub-connecting electrode 50-2 may be in the shape of a block, the first end of the first sub-connecting electrode 50-1 is connected to the first plate 11 through the first plate via BV, the second end of the first sub-connecting electrode 50-1 extends toward the direction close to the light-transmitting area 120 and is connected to the second sub-connecting electrode 50-2, and the second sub-connecting electrode 50-2 is connected to the first electrode 61 through the second plate via YV.

[0097] In an exemplary embodiment, the first sub-connection electrode 50 - 1 and the second sub-connection electrode 50 - 2 may be provided in the same layer, formed simultaneously through the same patterning process, and be an integrated structure connected to each other.

[0098] In an exemplary embodiment, in at least one sub-pixel, the first electrode 61 may include at least a first sub-electrode 61-1, a second sub-electrode 61-2 and a sub-connecting electrode 61-3, the first sub-electrode 61-1 and the second sub-electrode 61-2 are arranged in isolation, the sub-connecting electrode 61-3 may be shaped like a "C", the first end of the sub-connecting electrode 61-3 is connected to the first sub-electrode 61-1, the second end of the sub-connecting electrode 61-3 is connected to the second sub-electrode 61-2, and the area between the first end of the sub-connecting electrode 61-3 and the second end of the sub-connecting electrode 61-3 extends to the rear in a direction close to the light-transmitting area 120, and is connected to the second sub-connecting electrode 50-2 through the second electrode via YV.

[0099] In an exemplary embodiment, in at least one sub-pixel, the first sub-electrode 61-1, the second sub-electrode 61-2 and the sub-connecting electrode 61-3 may be provided in the same layer, formed simultaneously through the same patterning process, and be an interconnected integral structure.

[0100] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the first sub-electrode 61-1 on the substrate does not overlap with the orthographic projection of the first plate via BV on the substrate, and the orthographic projection of the second sub-electrode 61-2 on the substrate does not overlap with the orthographic projection of the first plate via BV on the substrate.

[0101] FIG6 is a cross-sectional view taken along line AA in FIG5 . As shown in FIG6 , the display substrate may further include a first insulating layer 71, a second insulating layer 72, a third insulating layer 73, and a semiconductor layer. The first insulating layer 71 may be disposed on a side of the first electrode 11 away from the substrate 10, the semiconductor layer may be disposed on a side of the first insulating layer 71 away from the substrate 10, the second insulating layer 72 may be disposed on a side of the semiconductor layer away from the substrate 10, the second electrode 12 and the electrode connecting electrode 50 may be disposed on a side of the second insulating layer 72 away from the substrate 10, the third insulating layer 73 may be disposed on a side of the second electrode 12 and the electrode connecting electrode 50 away from the substrate 10, and the sub-connecting electrode 61-3 in the first electrode 61 may be disposed on a side of the third insulating layer 73 away from the substrate.

[0102] In an exemplary embodiment, the first plate via BV may be provided in the first insulating layer 71 and the second insulating layer 72, and the first plate via BV passes through the first insulating layer 71 and the second insulating layer 72. The second plate via YV may be provided in the third insulating layer 73, and the second plate via YV passes through the third insulating layer 73.

[0103] In an exemplary embodiment, the display substrate may further include a planarization layer 74 and a pixel definition layer 75 .

[0104] In an exemplary embodiment, the flat layer 74 can be arranged on the side of the third insulating layer 73 away from the substrate, the first sub-electrode 61-1 and the second sub-electrode 61-2 in the first electrode 61 can be arranged on the side of the flat layer 74 away from the substrate, a flat opening TV1 is opened on the flat layer 74 located in the light-transmitting area, the flat layer within the flat opening TV1 is removed, the second electrode via YV and the sub-connecting electrode 61-3 are arranged within the area of ​​the flat opening TV1, and the orthographic projection of the second electrode via YV on the substrate is located within the range of the orthographic projection of the flat opening TV1 on the substrate.

[0105] In an exemplary embodiment, the pixel definition layer 75 can be disposed on a side of the first electrode 61 away from the substrate. The pixel definition layer 75 located in the display area is provided with a first pixel opening and a second pixel opening, and the orthographic projections of the first pixel opening and the second pixel opening on the substrate do not overlap with the orthographic projection of the first plate via BV on the substrate. The pixel definition layer 75 located in the light-transmitting area is provided with a light-transmitting opening TV2. The pixel definition layer within the light-transmitting opening TV2 is removed. The second plate via YV and the sub-connecting electrode 61-3 are disposed outside the area of ​​the light-transmitting opening TV2, and the orthographic projection of the second plate via YV on the substrate does not overlap with the orthographic projection of the light-transmitting opening TV2 on the substrate.

[0106] As shown in Figures 5 and 6, at least one repeating unit may include one scan signal line 30, one first power line 51, one second power line 52, four data signal lines 53, and one compensation signal line 54. The scan signal line 30 may be in the shape of a line with a main portion extending along the first direction X. The first power line 51, the second power line 52, the data signal line 53, and the compensation signal line 54 may be in the shape of a line with a main portion extending along the second direction Y, and may be arranged in the display area 110. In an exemplary embodiment, the first power line 51, two data signal lines 53, the compensation signal line 54, two data signal lines 53, and the second power line 52 may be arranged in sequence along the first direction X. In at least one repeating unit, the first power line 51 can be located on one side of the display area 110 in the first direction X, the second power line 52 can be located on the other side of the display area 110 in the first direction X, the compensation signal line 54 can be located between the first power line 51 and the second power line 52, two of the four data signal lines 53 can be located between the first power line 51 and the compensation signal line 54, and the other two of the four data signal lines 53 can be located between the second power line 52 and the compensation signal line 54.

[0107] In an exemplary embodiment, the positions of the first power line 51 and the second power line 52 can be substantially mirror-symmetrical with respect to the compensation signal line 54, and the two data signal lines 53 located on the opposite side of the first direction X of the compensation signal line 54 and the two data signal lines 53 located on the side of the first direction X of the compensation signal line 54 can be substantially mirror-symmetrical with respect to the compensation signal line 54.

[0108] In an exemplary embodiment, one scan signal line 30 may define two adjacent pixel rows, one compensation signal line 54 may define two adjacent pixel columns, and the scan signal line 30 and the compensation signal line 54 define four sub-pixels.

[0109] In an exemplary embodiment, in at least one sub-pixel, the pixel driving circuit can be connected to the scan signal line 30, the first power line 51, the data signal line 53 and the compensation signal line 54, respectively, the light-emitting device is connected to the second power line 52, the scan signal line 30 is configured to provide a scan signal to the pixel driving circuit, the first power line 51 is configured to provide a first power signal to the pixel driving circuit, the data signal line 53 is configured to provide a data signal to the pixel driving circuit, the compensation signal line 54 is configured to provide a compensation signal to the pixel driving circuit, and the second power line 52 is configured to provide a second power signal to the third electrode of the light-emitting device.

[0110] In an exemplary embodiment, the first power line 51 , the second power line 52 , the data signal line 53 , and the compensation signal line 54 may be disposed in the same layer as the first electrode plate 11 and may be simultaneously formed through the same patterning process.

[0111] In an exemplary embodiment, the scan signal line 30 may be disposed in the same layer as the plate connection electrode 50 and may be simultaneously formed through the same patterning process.

[0112] In an exemplary embodiment, the pixel driving circuit may further include a first transistor as a data writing transistor, a second transistor as a driving transistor, and a third transistor as a compensation transistor, and in at least one repeating unit, the gate electrodes of the four first transistors and the gate electrodes of the four third transistors are connected to the same scan signal line 30.

[0113] In an exemplary embodiment, the first light-transmitting area 120-1 can be arranged on a side of the display area 110 in the opposite direction of the first direction X, the first power line 51 can be arranged on a side of the display area 110 close to the first light-transmitting area 120-1, and the plate connecting electrode 50 can cross the first power line 51 and be connected to the first plate 11 and the first electrode 61 respectively.

[0114] In an exemplary embodiment, the first plate via BV can be arranged on a side of the first power line 51 away from the first light-transmitting area 120-1, and the second plate via YV can be arranged on a side of the first power line 51 close to the first light-transmitting area 120-1, and the orthographic projection of the plate connecting electrode 50 on the substrate at least partially overlaps with the orthographic projection of the first power line 51 on the substrate.

[0115] In an exemplary embodiment, the second light-transmitting area 120-2 can be set on one side of the display area 110 in the first direction X, the second power line 52 can be set on one side of the display area 110 close to the second light-transmitting area 120-2, and the plate connecting electrode 50 can cross the second power line 52 and be connected to the first plate 11 and the first electrode 61 respectively.

[0116] In an exemplary embodiment, the first plate via BV can be arranged on a side of the second power line 52 away from the second light-transmitting area 120-2, and the second plate via YV can be arranged on a side of the second power line 52 close to the second light-transmitting area 120-2, and the orthographic projection of the plate connecting electrode 50 on the substrate at least partially overlaps with the orthographic projection of the first power line 51 on the substrate.

[0117] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0118] In an exemplary embodiment, taking four sub-pixels (first sub-pixel P1, second sub-pixel P2, third sub-pixel P3 and fourth sub-pixel P4) of a repeating unit as an example, the preparation process of the display substrate of the exemplary embodiment of the present disclosure may include the following operations.

[0119] (1) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern includes: depositing a first conductive film on a substrate, patterning the first conductive film through a patterning process, and forming a first conductive layer pattern on the substrate, as shown in FIG7 . In an exemplary embodiment, the first conductive layer may be referred to as a light shielding layer (SHL).

[0120] In an exemplary embodiment, the first conductive layer of each sub-pixel in the display substrate may include at least a first electrode plate 11 .

[0121] In an exemplary embodiment, the shape of the first electrode plate 11 can be rectangular, and the corners of the rectangle can be chamfered. The first electrode plate 11 can serve as the lower electrode plate of the storage capacitor (the second end of the storage capacitor), and the first electrode plate 11 is configured to form a storage capacitor with the subsequently formed second electrode plate.

[0122] In an exemplary embodiment, the first electrode plate 11 is further configured to shield the second transistor from light, reduce the intensity of light irradiating the second transistor, reduce leakage current of the second transistor, and thereby reduce the effect of light on the characteristics of the second transistor.

[0123] In an exemplary embodiment, the position and shape of the first electrode plate 11 in the first subpixel P1 and the position and shape of the first electrode plate 11 in the third subpixel P3 may be substantially mirror-symmetrical with respect to a horizontal reference line, the position and shape of the first electrode plate 11 in the second subpixel P2 and the position and shape of the first electrode plate 11 in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to the horizontal reference line, the position and shape of the first electrode plate 11 in the first subpixel P1 and the position and shape of the first electrode plate 11 in the second subpixel P2 may be substantially mirror-symmetrical with respect to a vertical reference line, the position and shape of the first electrode plate 11 in the third subpixel P3 and the position and shape of the first electrode plate 11 in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a vertical reference line, the horizontal reference line may be a straight line extending along the first direction X and bisecting the display area in the second direction Y, and the vertical reference line may be a straight line extending along the second direction Y and bisecting the display area in the first direction X.

[0124] In an exemplary embodiment, the first conductive layer of each repeating unit in the display substrate may further include at least one first power line 51 , one second power line 52 , four data signal lines 53 , and one compensation signal line 54 .

[0125] In an exemplary embodiment, the shapes of the first power line 51, the second power line 52, the data signal line 53 and the compensation signal line 54 can be straight lines or broken lines with the main part extending along the second direction Y. The first power line 51 can be located on the side opposite to the first direction X of the repeating unit, the second power line 52 can be located on the side of the repeating unit in the first direction X, the compensation signal line 54 can be located between the two first power lines 51, the first data signal line 53 of the four data signal lines 53 can be located on the side of the first power line 51 close to the compensation signal line 54, the second data signal line 53 of the four data signal lines 53 can be located on the side of the compensation signal line 54 close to the first power line 51, the third data signal line 53 of the four data signal lines 53 can be located on the side of the compensation signal line 54 close to the second power line 52, and the fourth data signal line 53 of the four data signal lines 53 can be located on the side of the second power line 52 close to the compensation signal line 54.

[0126] In an exemplary embodiment, the first power line 51 and the compensation signal line 54 may define a first pixel column, and the first data signal line 53 and the second data signal line 53 may be disposed in the first pixel column and located on both sides of the first electrode plate 11 in the first direction X. The second power line 52 and the compensation signal line 54 may define a second pixel column, and the third data signal line 53 and the fourth data signal line 53 may be disposed in the second pixel column and located on both sides of the first electrode plate 11 in the first direction X.

[0127] In an exemplary embodiment, the positions of the first power line 51 and the second power line 52 can be substantially mirror-symmetrical with respect to a vertical reference line, and the positions of the two data signal lines 53 located on the opposite side of the first direction X of the compensation signal line 54 and the positions of the two data signal lines 53 located on the side of the first direction X of the compensation signal line 54 can be substantially mirror-symmetrical with respect to the vertical reference line.

[0128] In an exemplary embodiment, in an exemplary embodiment, the first power line 51, the second power line 52, the data signal line 53 and the compensation signal line 54 can be straight lines or broken lines of equal width, or straight lines or broken lines of unequal width. The use of straight lines or broken lines of variable width can not only facilitate the layout of the pixel structure, but also reduce parasitic capacitance.

[0129] After this patterning process, the first electrode 11 , the first power line 51 , the second power line 52 , the data signal line 53 and the compensation signal line 54 are formed in the display area 110 , and the light-transmitting area 120 has no corresponding film layer.

[0130] (2) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a first insulating layer covering the first conductive layer, and a semiconductor layer disposed on the first insulating layer, as shown in FIG8A and FIG8B , where FIG8B is a schematic diagram of the semiconductor layer in FIG8A .

[0131] In an exemplary embodiment, the semiconductor layer of each sub-pixel in the display substrate may include at least a first active layer 21, a second active layer 22, and a third active layer 23, the first active layer 21 serving as an active layer of the first transistor T1, the second active layer 22 serving as an active layer of the second transistor T2, and the third active layer 23 serving as an active layer of the third transistor T3.

[0132] In an exemplary embodiment, for the first subpixel P1 and the second subpixel P2, the first active layer 21 and the third active layer 23 can be disposed on one side of the first electrode plate 11 of the subpixel in the second direction Y, and the second active layer 22 can be disposed in an end region of the first electrode plate 11 of the subpixel away from the first active layer 21 and the third active layer 23. The orthographic projection of the second active layer 22 on the substrate is within the range of the orthographic projection of the first electrode plate 11 of the subpixel on the substrate. This allows the first electrode plate 11, acting as a shielding layer, to shield the channel region of the second transistor T2, preventing light from affecting the channel and ensuring the electrical performance of the second transistor T2. The third active layer 23 of the first subpixel P1 can be disposed on one side of the first active layer 21 of the subpixel in the first direction X, and the third active layer 23 of the second subpixel P2 can be disposed on a side of the first active layer 21 of the subpixel opposite to the first direction X.

[0133] In an exemplary embodiment, for the third subpixel P3 and the fourth subpixel P4, the first active layer 21 and the third active layer 23 can be disposed on the side of the first electrode plate 11 of the subpixel opposite to the second direction Y, and the second active layer 22 can be disposed in the end region of the first electrode plate 11 of the subpixel away from the first active layer 21 and the third active layer 23. The orthographic projection of the second active layer 22 on the substrate is within the orthographic projection of the first electrode plate 11 of the subpixel on the substrate. This allows the first electrode plate 11, acting as a shielding layer, to shield the channel region of the second transistor T2, preventing light from affecting the channel and ensuring the electrical performance of the second transistor T2. The third active layer 23 of the third subpixel P3 can be disposed on the side of the first active layer 21 of the subpixel opposite to the first direction X, and the third active layer 23 of the fourth subpixel P4 can be disposed on the side of the first active layer 21 of the subpixel in the first direction X.

[0134] In an exemplary embodiment, the third active layer 23 of the first subpixel P1 and the third active layer 23 of the third subpixel P3 may be interconnected as a single unitary structure, and the third active layer 23 of the second subpixel P2 and the third active layer 23 of the fourth subpixel P4 may be interconnected as a single unitary structure. That is, the third active layers 23 of two subpixels in adjacent pixel rows are interconnected as a single unitary structure. By providing a shared source electrode for the second transistors of two adjacent subpixels in a pixel column, the present disclosure not only saves space but also reduces the number of via connection structures, simplifying the manufacturing process.

[0135] In an exemplary embodiment, the first active layer 21 and the third active layer 23 may be in an I-shape, and the second active layer 22 may be in a block shape (eg, rectangular), with chamfered corners of the block shape.

[0136] In the exemplary embodiment, the orthographic projection of the first active layer 21 on the substrate does not overlap with the orthographic projection of the first electrode plate 11 on the substrate, and the orthographic projection of the third active layer 23 on the substrate does not overlap with the orthographic projection of the first electrode plate 11 on the substrate. By providing a non-overlapping region between the first active layer 21 and the first electrode plate 11, and between the third active layer 23 and the first electrode plate 11, the present disclosure facilitates designing the channel width-to-length ratios of the first and third transistors according to relevant requirements.

[0137] In an exemplary embodiment, the position and shape of the first active layer 21 and the third active layer 23 in the first subpixel P1 and the position and shape of the first active layer 21 and the third active layer 23 in the second subpixel P2 may be substantially mirror-symmetrical with respect to a vertical reference line, the position and shape of the first active layer 21 and the third active layer 23 in the third subpixel P3 and the position and shape of the first active layer 21 and the third active layer 23 in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a vertical reference line, and the position of the second active layer 22 in the first subpixel P1 and the position and shape of the first active layer 22 in the second subpixel P2 may be substantially mirror-symmetrical with respect to a vertical reference line. The position of the second active layer 22 can be basically mirror-symmetrical with respect to the vertical reference line, the position of the second active layer 22 in the third subpixel P3 and the position of the second active layer 22 in the fourth subpixel P4 can be basically mirror-symmetrical with respect to the vertical reference line, the position of the second active layer 22 in the first subpixel P1 and the position of the second active layer 22 in the third subpixel P3 can be basically mirror-symmetrical with respect to the horizontal reference line, and the position of the second active layer 22 in the second subpixel P2 and the position of the second active layer 22 in the fourth subpixel P4 can be basically mirror-symmetrical with respect to the horizontal reference line.

[0138] In example embodiments, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.

[0139] In exemplary embodiments, the semiconductor layer may be formed of a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, an oxide containing indium, gallium, and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0140] In an exemplary embodiment, after this patterning process, a semiconductor layer pattern is formed in the display region 110 , and the film layer in the light-transmitting region 120 includes a first insulating layer.

[0141] (3) Forming a second insulating layer pattern. In an exemplary embodiment, forming the second insulating layer pattern may include: depositing a second insulating film on the substrate having the aforementioned pattern formed thereon, patterning the second insulating film through a patterning process to form a second insulating layer pattern covering the semiconductor layer, wherein the second insulating layer is provided with a plurality of vias, as shown in FIG. 9 .

[0142] In an exemplary embodiment, the multiple via holes of each sub-pixel in the display substrate may include at least: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8, a ninth via hole V9 and a tenth via hole V10.

[0143] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the second insulating layer in the first via hole V1 is etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed first connecting electrode to the first region of the first active layer through the via hole.

[0144] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer on the substrate, the second insulating layer in the second via hole V2 is etched away to expose the surface of the second region of the first active layer, and the second via hole V2 is configured to connect a subsequently formed second connecting electrode to the second region of the first active layer through the via hole.

[0145] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the orthographic projection of the first region of the second active layer on the substrate. The second insulating layer within the third via hole V3 is etched away, exposing the surface of the first region of the second active layer. The third via hole V3 is configured to connect a subsequently formed third connection electrode to the first region of the second active layer through the via hole. In an exemplary embodiment, some sub-pixels may have multiple third via holes V3 to increase connection reliability.

[0146] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the orthographic projection of the second region of the second active layer on the substrate. The second insulating layer within the fourth via hole V4 is etched away, exposing the surface of the second region of the second active layer. The fourth via hole V4 is configured to connect a subsequently formed fourth connection electrode to the second region of the second active layer through the via hole. In an exemplary embodiment, some sub-pixels may have multiple fourth via holes V4 to increase connection reliability.

[0147] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the orthographic projection of the first region of the third active layer on the substrate. The second insulating layer within the fifth via hole V5 is etched away, exposing the surface of the first region of the third active layer. The fifth via hole V5 is configured to connect a subsequently formed fifth connecting electrode to the first region of the third active layer through the via hole. In an exemplary embodiment, because the third active layers 23 of two adjacent sub-pixels in the second direction Y in a pixel column are interconnected and integrally structured, the two sub-pixels share the first region of the third active layer, and thus, the two sub-pixels share one fifth via hole V5.

[0148] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second region of the third active layer on the substrate, the second insulating layer in the sixth via hole V6 is etched away to expose the surface of the second region of the third active layer, and the sixth via hole V6 is configured to connect a subsequently formed sixth connecting electrode to the second region of the third active layer through the via hole.

[0149] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first electrode plate 11 on the substrate, and is arranged in the end area of ​​the first electrode plate 11 of each sub-pixel away from the second active layer 22. The second insulating layer and the first insulating layer in the seventh via hole V7 are etched away to expose the surface of the first electrode plate 11. The seventh via hole V7 is configured to connect the subsequently formed fourth connecting electrode to the first electrode plate 11 through the via hole.

[0150] In an exemplary embodiment, the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the first electrode plate 11 on the substrate, and is arranged in the end area of ​​the first electrode plate 11 of each sub-pixel close to the third active layer 23. The second insulating layer and the first insulating layer in the eighth via hole V8 are etched away to expose the surface of the first electrode plate 11. The eighth via hole V8 is configured to connect the subsequently formed sixth connecting electrode to the first electrode plate 11 through the via hole.

[0151] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the first electrode plate 11 on the substrate, and is arranged in the end area of ​​the first electrode plate 11 of each sub-pixel away from the compensation signal line 54. The second insulating layer and the first insulating layer in the ninth via hole V9 are etched away to expose the surface of the first electrode plate 11. The ninth via hole V9 is configured to connect the subsequently formed electrode connecting electrode to the first electrode plate 11 through the via hole.

[0152] In the exemplary embodiment, the ninth via hole V9 serves as the first plate via hole of the present disclosure. For the light-transmitting region 120 located on the opposite side of the first power line 51 in the first direction X, the ninth via hole V9 is disposed on the side of the first power line 51 away from the light-transmitting region 120. For the light-transmitting region 120 located on the opposite side of the second power line 52 in the first direction X, the ninth via hole V9 is disposed on the side of the second power line 52 away from the light-transmitting region 120.

[0153] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the data signal line 53 on the substrate, the second insulating layer and the first insulating layer in the tenth via hole V10 are etched away to expose the surface of the data signal line 53, and the tenth via hole V10 is configured to connect the subsequently formed first connecting electrode to the data signal line 53 through the via hole.

[0154] In an exemplary embodiment, the at least one repeating unit may further include an eleventh via hole V11 , a twelfth via hole V12 , and a thirteenth via hole V13 .

[0155] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the compensation signal line 54 on the substrate, the second insulating layer and the first insulating layer in the eleventh via hole V11 are etched away to expose the surface of the compensation signal line 54, and the eleventh via hole V11 is configured to connect the subsequently formed fifth connecting electrode to the compensation signal line 54 through the via hole.

[0156] In an exemplary embodiment, a twelfth via hole V12 may be provided in the first subpixel P1 and the third subpixel P3. The orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the first power line 51 on the substrate. The second insulating layer and the first insulating layer within the twelfth via hole V12 are etched away, exposing the surface of the first power line 51. The twelfth via hole V12 is configured to connect a subsequently formed first auxiliary power line to the first power line 51 through the via hole. In an exemplary embodiment, there may be multiple twelfth via holes V12, and the multiple twelfth via holes V12 may be arranged sequentially along the second direction Y to increase connection reliability.

[0157] In an exemplary embodiment, a thirteenth via hole V13 may be provided in the second subpixel P2 and the fourth subpixel P4. The orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the second power line 52 on the substrate. The second insulating layer and the first insulating layer within the thirteenth via hole V13 are etched away, exposing the surface of the second power line 52. The thirteenth via hole V13 is configured to connect a subsequently formed second auxiliary power line to the second power line 52 through the via hole. In an exemplary embodiment, there may be multiple thirteenth via holes V13, and the multiple thirteenth via holes V13 may be arranged sequentially along the first direction X and the second direction Y to increase connection reliability.

[0158] In an exemplary embodiment, the patterning process may use a half tone mask process.

[0159] In an exemplary embodiment, during the process of forming the second insulating layer pattern, a dry etching process may be used to form a plurality of via holes, and the semiconductor layer exposed within the via holes may be subjected to a primary conductorization process. During the primary conductorization process, the edge portion of the semiconductor layer covered by the second insulating layer near the via hole is also conductorized, that is, the semiconductor layer subjected to the primary conductorization extends away from the via hole.

[0160] After this patterning process, the film layer of the light-transmitting region 120 includes a first insulating layer and a second insulating layer.

[0161] (4) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film through a patterning process, and forming a second conductive layer pattern on the second insulating layer, as shown in FIG. 10A and FIG. 10B , where FIG. 10B is a schematic diagram of the second conductive layer in FIG. 10A . In an exemplary embodiment, the second conductive layer may be referred to as a gate metal layer (GATE).

[0162] In an exemplary embodiment, the second conductive layer in at least one repeating unit may include at least a scan signal line 30 , a first power auxiliary line 31 , a second power auxiliary line 32 , a first power connection line 33 , a second power connection line 34 , and a first auxiliary electrode 35 .

[0163] In an exemplary embodiment, the shape of the scanning signal line 30 can be a line extending along the first direction X, and can be arranged in the middle of the repeating unit in the second direction Y, that is, between the first sub-pixel P1 and the second sub-pixel P2 and the third sub-pixel P3 and the fourth sub-pixel P4. The area where the scanning signal line 30 overlaps with the multiple first active layers can serve as the gate electrodes of the multiple first transistors T1, and the area where the scanning signal line 30 overlaps with the multiple third active layers can serve as the gate electrodes of the multiple third transistors T3, so that the scanning signal line 30 can control the conduction or disconnection of the first transistor T1 and the third transistor T3.

[0164] In an exemplary embodiment, along the first direction X, the scan signal line 30 may include a double line segment 30-1 and a single line segment 30-2 connected in sequence. The double line segment 30-1 may be located in the display area 110, and the single line segment 30-2 may be located in the light-transmitting area 120. That is, the display area 110 is provided with two signal lines, while the light-transmitting area 120 is provided with only one signal line.

[0165] In an exemplary embodiment, the double line segment 30-1 of the display area 110 may include a first sub-line 30a and a second sub-line 30b extending along a first direction X. The first sub-line 30a and the second sub-line 30b are arranged along a second direction Y. The second sub-line 30b may be disposed on one side of the first sub-line 30a in the second direction Y. The first sub-line 30a may be connected to the pixel driving circuits of two sub-pixels in a first pixel row, respectively, and the second sub-line 30b may be connected to the pixel driving circuits of two sub-pixels in a second pixel row, respectively. This enables connection between the double line segment 30-1 and multiple pixel driving circuits in a repeating unit.

[0166] In an exemplary embodiment, the orthographic projection of the first sub-line 30a on the substrate at least partially overlaps with the orthographic projections of the first active layer 21 and the third active layer 23 in the first sub-pixel P1 and the second sub-pixel P2 on the substrate, respectively. The overlapping regions serve as the gate electrodes of the first transistor T1 and the third transistor T3, respectively. That is, the first sub-line 30a is simultaneously connected to the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 in the first sub-pixel P1 and the second sub-pixel P2. The orthographic projection of the second sub-line 30b on the substrate at least partially overlaps with the orthographic projections of the first active layer 21 and the third active layer 23 in the third sub-pixel P3 and the fourth sub-pixel P4 on the substrate, respectively. The overlapping regions serve as the gate electrodes of the first transistor T1 and the third transistor T3, respectively. That is, the second sub-line 30b is simultaneously connected to the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 in the third sub-pixel P3 and the fourth sub-pixel P4. In this way, the double line segment 30 - 1 transmitting the same scan signal can simultaneously control the on or off of all first transistors T1 and all third transistors T3 in the four sub-pixels of the repeating unit.

[0167] In an exemplary embodiment, the double line segment 30-1 of the display area 110 may further include a third sub-line 30c and a fourth sub-line 30d. The third sub-line 30c may be connected to the ends of the first sub-line 30a and the second sub-line 30b in the opposite direction of the first direction X, respectively. The fourth sub-line 30d may be connected to the ends of the first sub-line 30a and the second sub-line 30b in the first direction X, respectively. Thus, the third sub-line 30c, the first sub-line 30a, the fourth sub-line 30d, and the second sub-line 30b are sequentially connected to form a ring structure. In an exemplary embodiment, the ring shape may be a rectangular ring or a polygonal ring.

[0168] In an exemplary embodiment, the third sub-line 30c can be connected to the single line segment 30-2 of the light-transmitting area 120 in the opposite direction of the first direction X of the display area 110, and the fourth sub-line 30d can be connected to the single line segment 30-2 of the light-transmitting area 120 in the first direction X of the display area 110. The double line segment 30-1 of the display area 110 and the single line segment 30-2 of the light-transmitting area 120 constitute a continuous scanning signal line 30 extending along the first direction X.

[0169] In an exemplary embodiment, for multiple repeating units arranged sequentially in the first direction X, the double line segment 30-1 and the single line segment 30-2 in each repeating unit can be an integrated structure connected to each other, and the multiple double line segments 30-1 and the multiple single line segments 30-2 in the multiple repeating units can be an integrated structure connected to each other.

[0170] In an exemplary embodiment, in at least one sub-pixel, one scan signal line 30 can simultaneously control the turning on or off of the first transistor T1 and the third transistor T3 in the sub-pixel.

[0171] In an exemplary embodiment, in at least one pixel row, one scan signal line 30 can simultaneously control the turning on or off of all first transistors T1 and all third transistors T3 in the pixel row.

[0172] In an exemplary embodiment, in at least one repeating unit, one scan signal line 30 can simultaneously control the turning on or off of all first transistors T1 and all third transistors T3 in the repeating unit.

[0173] In an exemplary embodiment, in at least one repeating unit, the orthographic projection of the third active layer of the integrated structure in two sub-pixels of adjacent pixel rows on the substrate at least partially overlaps with the orthographic projection of the ring structure of the scan signal line 30 on the substrate.

[0174] In an exemplary embodiment, the orthographic projections of the first via hole V1 , the fifth via hole V5 , the tenth via hole V10 , and the eleventh via hole V11 on the substrate may be located within the range of the orthographic projection of the region surrounded by the ring structure of the scan signal line 30 on the substrate.

[0175] In an exemplary embodiment, the position and shape of the double line segment 30-1 in the first subpixel P1 and the position and shape of the double line segment 30-1 in the second subpixel P2 can be substantially mirror-symmetrical with respect to a vertical reference line, the position and shape of the double line segment 30-1 in the third subpixel P3 and the position and shape of the double line segment 30-1 in the fourth subpixel P4 can be substantially mirror-symmetrical with respect to a vertical reference line, the position and shape of the double line segment 30-1 in the first subpixel P1 and the position and shape of the double line segment 30-1 in the third subpixel P3 can be substantially mirror-symmetrical with respect to a horizontal reference line, and the position and shape of the double line segment 30-1 in the second subpixel P2 and the position and shape of the double line segment 30-1 in the fourth subpixel P4 can be substantially mirror-symmetrical with respect to a horizontal reference line.

[0176] In an exemplary embodiment, the first auxiliary power line 31 can be in the shape of a strip extending along the second direction Y. It can be provided in the first subpixel P1 and the third subpixel P3, respectively, on the side of the second electrode plate 12 opposite the first direction X. The first auxiliary power line 31 is connected to the first power line 51 through a plurality of twelfth vias V12. The first auxiliary power line 31 and the first power line 51 form a double-layer routing structure, which not only ensures the reliability of power signal transmission but also effectively reduces the resistance of the first power line, effectively reducing the voltage drop of the first power signal, and improving the display effect. In an exemplary embodiment, there can be multiple first auxiliary power lines 31 in the first subpixel P1 and the third subpixel P3, and the multiple first auxiliary power lines 31 can be spaced apart along the second direction Y.

[0177] In an exemplary embodiment, the second auxiliary power line 32 can be in the shape of a strip extending along the second direction Y. It can be provided in the second subpixel P2 and the fourth subpixel P4, respectively, on one side of the second electrode plate 12 in the first direction X. The second auxiliary power line 32 is connected to the second power line 52 through a plurality of thirteenth vias V13. The second auxiliary power line 32 and the second power line 52 form a double-layer routing structure, which not only ensures the reliability of power signal transmission but also effectively reduces the resistance of the second power line, effectively reduces the voltage drop of the second power signal, and improves the display effect. In an exemplary embodiment, there can be multiple second auxiliary power lines 32 in the second subpixel P2 and the fourth subpixel P4, and the multiple second auxiliary power lines 32 can be spaced apart along the second direction Y.

[0178] In an exemplary embodiment, the first power connection line 33 may be in the shape of a strip extending along the first direction X. The main portion of the first power connection line 33 may be disposed in each of the first subpixel P1 and the third subpixel P3, and may be located on the side of the first electrode plate 11 of each subpixel away from the scan signal line 30. In the first subpixel P1, the first end of the first power connection line 33 is connected to the first auxiliary power line 31 in the first subpixel P1, and the second end of the first power connection line 33 extends along the first direction X to the second subpixel P2. The first auxiliary power line 31 is configured to connect to the third connection electrodes in the first subpixel P1 and the second subpixel P2, respectively. In the third subpixel P3, the first end of the first power connection line 33 is connected to the first auxiliary power line 31 in the third subpixel P3, and the second end of the first power connection line 33 extends along the first direction X to the fourth subpixel P4. The first auxiliary power line 31 is configured to connect to the third connection electrodes in the third subpixel P3 and the fourth subpixel P4, respectively.

[0179] In an exemplary embodiment, the first power connection line 33 can realize a one-to-four structure of the first power lines in a repeating unit, saving the number of signal lines, reducing the occupied space, having a simple structure and a reasonable layout, making full use of the layout space, improving space utilization, and facilitating improving resolution and transparency.

[0180] In an exemplary embodiment, in the overlapping area between the first power connection line 33 and the compensation signal line 54, a strip-shaped opening (through hole) extending along the first direction X may be provided on the first power connection line 33, so that the area forms a ring structure to reduce the overlapping area between the first power connection line 33 and the data signal line 53 and the compensation signal line 54, reduce the parasitic capacitance between the signal lines, and improve the display effect.

[0181] In an exemplary embodiment, the first power connection line 33 and the at least one first power auxiliary line 31 in the first sub-pixel P1 can be an integrated structure connected to each other, and the first power connection line 33 and the at least one first power auxiliary line 31 in the third sub-pixel P3 can be an integrated structure connected to each other.

[0182] In an exemplary embodiment, the second power connection line 34 and the first auxiliary electrode 35 can be disposed in the light-transmitting region 120 of the repeating unit. The second power connection line 34 can be in the shape of a strip extending along the first direction X. The first end of the second power connection line 34 is connected to the second power auxiliary line 32, and the second end of the second power connection line 34 extends toward the light-transmitting region 120 and is connected to the first auxiliary electrode 35. The first auxiliary electrode 35 can be in the shape of a block (e.g., a rectangle) and is configured to connect to a subsequently formed second auxiliary electrode. Since the second auxiliary electrode is configured to connect to a subsequently formed third electrode, the second power line 52 can be connected to the third electrode.

[0183] In an exemplary embodiment, three second power connection lines 34 and first auxiliary electrodes 35 may be provided in the light-transmitting area 120 on one side of the first direction X of the second sub-pixel P2, and two second power connection lines 34 and first auxiliary electrodes 35 may be provided in the light-transmitting area 120 on one side of the first direction X of the fourth sub-pixel P4.

[0184] In an exemplary embodiment, the extension lengths of the plurality of second power connection lines 34 in the first direction X may be the same or different, and the areas of the plurality of first auxiliary electrodes 35 may be the same or different.

[0185] In an exemplary embodiment, the second power auxiliary line 32 and the first auxiliary electrode 35 connected by the second power connection line 34 may be an integral structure connected to each other.

[0186] In an exemplary embodiment, taking into account the voltage drop (IR Drop) problem existing in large-size transparent displays, the embodiment of the present disclosure specifically sets a second power line for transmitting a low-voltage signal in each repeating unit. The second power line is connected to the third electrode in the subsequently formed light-emitting structure layer through an auxiliary electrode, which can effectively reduce the voltage drop of the second power signal, effectively solve the voltage drop problem existing in large-size transparent displays, and ensure display uniformity.

[0187] In an exemplary embodiment, the position and shape of the first power auxiliary line 31 and the first power connection line 33 in the first subpixel P1 and the position and shape of the first power auxiliary line 31 and the first power connection line 33 in the third subpixel P3 may be substantially mirror-symmetrical with respect to a horizontal reference line, and the position and shape of the second power auxiliary line 32 in the second subpixel P2 and the position and shape of the second power auxiliary line 32 in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a horizontal reference line. The position of the first power auxiliary line 31 in the first subpixel P1 and the position of the second power auxiliary line 32 in the second subpixel P2 may be substantially mirror-symmetrical with respect to a vertical reference line, and the position of the first power auxiliary line 31 in the third subpixel P3 and the position of the second power auxiliary line 32 in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a vertical reference line.

[0188] In an exemplary embodiment, the second conductive layer of each sub-pixel in the display substrate may include at least a second plate 12, a second gate electrode 13, a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, a sixth connection electrode 46 and a plate connection electrode 50.

[0189] In an exemplary embodiment, the shape of the second electrode plate 12 can be rectangular, and the corners of the rectangle can be chamfered, protruded or opened. It can be set at the position of each sub-pixel near the scanning signal line 30. The positive projection of the second electrode plate 12 on the substrate at least partially overlaps with the positive projection of the first electrode plate 11 on the substrate. The second electrode plate 12 can serve as the upper plate of the storage capacitor (the first end of the storage capacitor), and the first electrode plate 11 and the second electrode plate 12 form a storage capacitor of the pixel driving circuit.

[0190] In an exemplary embodiment, the second gate electrode 13 may be in the shape of a strip extending along the second direction Y, and may be located on the side of the second electrode plate 12 of the sub-pixel away from the scanning signal line 30. The first end of the second gate electrode 13 is connected to the second electrode plate 12 of the sub-pixel, and the second end of the second gate electrode 13 extends in a direction away from the scanning signal line 30. The orthographic projection of the second gate electrode 13 on the substrate at least partially overlaps with the orthographic projection of the second active layer 22 on the substrate. The second gate electrode 13 may serve as the gate electrode of the second transistor T2, and may control the conduction or disconnection of the second transistor T2.

[0191] In an exemplary embodiment, the second plate 12 and the second gate electrode 13 in each sub-pixel may be an integral structure connected to each other.

[0192] In an exemplary embodiment, the first connection electrode 41 may be in a block shape (e.g., a rectangle). A first end of the first connection electrode 41 is connected to the first region of the first active layer via a first via hole V1, and a second end of the first connection electrode 41 is connected to the data signal line 53 via a tenth via hole V10. In an exemplary embodiment, the first connection electrode 41 may serve as the first electrode of the first transistor T1, enabling the data signal line 53 to write a data signal to the first electrode of the first transistor T1.

[0193] In an exemplary embodiment, the four data signal lines 53 may include a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line. The first data signal line may be located on one side of the first power line 51 in the first direction X and may be connected to the first region of the first active layer in the first subpixel P1 through a first via hole V1. The second data signal line may be located on one side of the compensation signal line 54 in the opposite direction of the first direction X and may be connected to the first region of the first active layer in the third subpixel P3 through a first via hole V1. The third data signal line may be located on one side of the compensation signal line 54 in the first direction X and may be connected to the first region of the first active layer in the fourth subpixel P4 through a first via hole V1. The fourth data signal line may be located on one side of the second power line 52 in the opposite direction of the first direction X and may be connected to the first region of the first active layer in the second subpixel P2 through a first via hole V1.

[0194] In an exemplary embodiment, the second connection electrode 42 may be in a block shape (e.g., a rectangle), with a first end of the second connection electrode 42 connected to the second region of the first active layer via a second via hole V2, and a second end of the second connection electrode 42 connected to the second electrode plate 12. In an exemplary embodiment, the second connection electrode 42 may serve as the second electrode of the first transistor T1, such that the second electrode of the first transistor T1 and the second electrode plate 12 have the same potential.

[0195] In an exemplary embodiment, the second connection electrode 42 and the second electrode plate 12 may be an integral structure connected to each other.

[0196] In an exemplary embodiment, since the second gate electrode 13 is connected to the second electrode plate 12 and the second electrode of the first transistor T1 is connected to the second electrode plate 12, the second electrode of the first transistor T1, the gate electrode of the second transistor T2 and the second electrode plate 12 have the same potential, forming the first node N1 of the pixel driving circuit.

[0197] In an exemplary embodiment, the third connection electrode 43 may be in the shape of a strip extending along the second direction Y. A first end of the third connection electrode 43 is connected to the first region of the second active layer via a third via hole V3, and a second end of the third connection electrode 43 is connected to the first power connection line 33. In an exemplary embodiment, the third connection electrode 43 may serve as the first electrode of the second transistor T2. Because the first power connection line 33 is connected to the first auxiliary power line 31, and the first auxiliary power line 31 is connected to the first power line 51, the first power line 51 can write the first power signal to the first electrode of the second transistor T2.

[0198] In an exemplary embodiment, the third connection electrode 43 of the first subpixel P1, the third connection electrode 43 of the second subpixel P2, and the connected first power connection line 33 may be connected to each other as an integral structure. The third connection electrode 43 of the third subpixel P3, the third connection electrode 43 of the fourth subpixel P4, and the connected first power connection line 33 may be connected to each other as an integral structure.

[0199] In an exemplary embodiment, the fourth connection electrode 44 may be in the shape of a strip extending along the second direction Y. A first end of the fourth connection electrode 44 is connected to the second region of the second active layer via a fourth via hole V4, and a second end of the fourth connection electrode 44 is connected to the first electrode plate 11 via a seventh via hole V7. In an exemplary embodiment, the fourth connection electrode 44 may serve as the second electrode of the second transistor T2, such that the second electrode of the second transistor T2 and the first electrode plate 11 have the same potential.

[0200] In an exemplary embodiment, the fifth connection electrode 45 may be in the shape of a strip extending along the first direction X. A first end of the fifth connection electrode 45 is connected to the first region of the third active layer via a fifth via hole V5, and a second end of the fifth connection electrode 45 is connected to the compensation signal line 54 via an eleventh via hole V11. In an exemplary embodiment, the fifth connection electrode 45 may serve as the first electrode of the third transistor T1, enabling the compensation signal line 54 to write the compensation signal into the first electrode of the third transistor T1.

[0201] In an exemplary embodiment, since the third active layers 23 of two adjacent sub-pixels in the second direction Y in one pixel column are connected as an integral structure, the two sub-pixels share the first region of the third active layer, and thus the two sub-pixels share one fifth connection electrode 45 .

[0202] In an exemplary embodiment, the fifth connection electrodes 45 of two pixel columns may be interconnected and integrally formed. These fifth connection electrodes 45 of the two pixel columns constitute a compensation connection line. That is, four pixel drive circuits within a display area 110 share a single compensation connection line, achieving a one-to-four compensation signal line structure within a repeating unit. By designing the compensation signal lines as a one-to-four structure, the display substrate of the present disclosure reduces the number of signal lines and occupies less space. This results in a simple structure and a rational layout, fully utilizing the layout space, improving space efficiency, and facilitating enhanced resolution and transparency.

[0203] In an exemplary embodiment, since the compensation signal line 54 is arranged between the first pixel column and the second pixel column, the compensation signal line 54 is connected to the third transistors T3 in the first pixel column and the second pixel column respectively through the fifth connecting electrode 45, and the third transistor T3 of the first pixel column and the third transistor T3 of the second pixel column are symmetrically arranged with respect to the compensation signal line 54. Therefore, this symmetrical structure can ensure that the RC delay of the compensation signal written into the third transistor T3 is substantially the same, thereby ensuring display uniformity.

[0204] In an exemplary embodiment, the orthographic projections of the first and fifth connection electrodes 41 and 45 in the repeating unit on the substrate may be located within the range of the orthographic projection of the region surrounded by the ring structure of the scan signal line 30 on the substrate.

[0205] In an exemplary embodiment, the sixth connection electrode 46 may be in the shape of a strip extending along the second direction Y. A first end of the sixth connection electrode 46 is connected to the second region of the third active layer via a sixth via hole V6, and a second end of the sixth connection electrode 46 is connected to the first electrode plate 11 via an eighth via hole V8. In an exemplary embodiment, the sixth connection electrode 46 may serve as the second electrode of the third transistor T3, such that the second electrode of the third transistor T3 and the first electrode plate 11 have the same potential.

[0206] In an exemplary embodiment, the fourth connection electrode 44 and the sixth connection electrode 46 allow the second electrode of the second transistor T2 , the second electrode of the third transistor T3 , and the first electrode plate 11 to have the same potential, forming a second node N2 of the pixel driving circuit.

[0207] In an exemplary embodiment, the shape of the plate connecting electrode 50 can be a strip shape extending along the first direction X, the first end of the plate connecting electrode 50 is connected to the first plate 11 through the ninth via V9, and the second end of the plate connecting electrode 50 extends in a direction away from the compensation signal line 54, and the second end of the plate connecting electrode 50 is configured to be connected to the first electrode formed subsequently.

[0208] In an exemplary embodiment, the plate connection electrode 50 in the first subpixel P1 and the third subpixel P3 crosses the first power line 51 disposed on one side of the display area 110, and the orthographic projection of the plate connection electrode 50 on the substrate at least partially overlaps with the orthographic projection of the first power line 51 on the substrate.

[0209] In an exemplary embodiment, the plate connection electrode 50 in the second subpixel P2 and the fourth subpixel P4 crosses the second power line 52 disposed on one side of the display area 110 , and the orthographic projection of the plate connection electrode 50 on the substrate at least partially overlaps with the orthographic projection of the second power line 52 on the substrate.

[0210] In an exemplary embodiment, the plate connection electrode 50 may include at least a first sub-connection electrode 50-1 and a second sub-connection electrode 50-2 that are connected to each other. The first sub-connection electrode 50-1 may be in the shape of a strip extending along the first direction X, and the second sub-connection electrode 50-2 may be in the shape of a block (e.g., a rectangle). In an exemplary embodiment, a first end of the first sub-connection electrode 50-1 is connected to the first plate 11 through a ninth via hole V9. A second end of the first sub-connection electrode 50-1 crosses the first power line 51 or the second power line 52 in a direction away from the first plate 11 and is then connected to the second sub-connection electrode 50-2. The second sub-connection electrode 50-2 is configured to be connected to a first electrode formed subsequently.

[0211] In an exemplary embodiment, the first sub-connection electrode 50 - 1 and the second sub-connection electrode 50 - 2 may be provided in the same layer and be an integral structure connected to each other.

[0212] In an exemplary embodiment, a plate groove 12-1 may be provided on the side of the second plate 12 close to the light-transmitting area 120 (away from the compensation signal line 54), and the shape of the plate groove 12-1 may be block-shaped (such as a rectangle), and the ninth via V9 may be accommodated in the plate groove 12-1. The orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the plate groove 12-1 on the substrate, and the first end of the first sub-connecting electrode 50-1 is also provided in the plate groove 12-1.

[0213] In an exemplary embodiment, for the second electrode 12, the second gate electrode 13, the first to sixth connecting electrodes 41 to 46, and the electrode connecting electrode 50, the position of each pattern in the first sub-pixel P1 and the position of each pattern in the third sub-pixel P3 can be substantially mirror-symmetrical with respect to the horizontal reference line, the position of each pattern in the second sub-pixel P2 and the position of each pattern in the fourth sub-pixel P4 can be substantially mirror-symmetrical with respect to the horizontal reference line, the position of each pattern in the first sub-pixel P1 and the position of each pattern in the second sub-pixel P2 can be substantially mirror-symmetrical with respect to the vertical reference line, and the position of each pattern in the third sub-pixel P3 and the position of each pattern in the fourth sub-pixel P4 can be substantially mirror-symmetrical with respect to the vertical reference line.

[0214] In an exemplary embodiment, a distance is provided between the end of each connecting electrode connected to the semiconductor layer and the edge of the corresponding via hole, that is, the connecting electrode does not completely cover the via hole.

[0215] In an exemplary embodiment, in the process of forming the second conductive layer pattern, a wet etching process is first used to form the second conductive layer pattern, and then a self-alignment process using the second conductive layer as a mask is used to etch the second insulating layer in the area outside the second conductive layer using a dry etching process. While etching away the second insulating layer, the exposed semiconductor layer is subjected to a second conductorization.

[0216] In an exemplary embodiment, during the second conductorization process, the edge portion of the semiconductor layer covered by the second conductive layer is also conductorized, that is, the semiconductor layer that is conductorized for the second time extends toward the area that was conductorized for the first time, forming a double conductorization area in the overlapping area of ​​the first conductorization area and the second conductorization area, thereby ensuring a reliable connection between the second conductive layer and the semiconductor layer.

[0217] After this patterning process, the film layer of the light-transmitting region 120 may include a first insulating layer, a second insulating layer, and a single line segment disposed on the second insulating layer.

[0218] (5) Forming a third insulating layer and a planar layer pattern. In an exemplary embodiment, forming the third insulating layer and the planar layer pattern may include: first depositing a third insulating film on the substrate on which the aforementioned pattern is formed, then coating a planar film, patterning the third insulating film and the planar film through a patterning process to form a third insulating layer covering the second conductive layer and a planar layer pattern disposed on the third insulating layer, wherein the planar layer is provided with a flat opening, and the third insulating layer is provided with a plurality of vias, as shown in FIG. 11 .

[0219] In an exemplary embodiment, the planar layer covers the display area 110 and the area where the single line segment is located in the light-transmitting area 120. The planar opening TV1 may be located outside the single line segment in the light-transmitting area 120. The planar film in the planar opening TV1 is removed to expose the third insulating layer.

[0220] In an exemplary embodiment, the shape of the flat opening TV1 can be rectangular, the corners of the rectangle can be provided with grooves or chamfers, and the first auxiliary electrode 35 in each sub-pixel and the second sub-connecting electrode 50-2 in the plate connecting electrode 50 can be located within the range of the flat opening TV1.

[0221] In an exemplary embodiment, the plurality of via holes of at least one repeating unit may include at least four twenty-first via holes V21 and six twenty-second via holes V22 .

[0222] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the second sub-connection electrode 50-2 in the plate connecting electrode 50 on the substrate, the third insulating layer in the twenty-first via hole V21 is etched away to expose the surface of the second sub-connection electrode 50-2, and the twenty-first via hole V21 is configured to connect the subsequently formed first electrode to the second sub-connection electrode 50-2 through the via hole.

[0223] In an exemplary embodiment, the twenty-first via hole V21 serves as the second plate via hole of the present disclosure, and the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the flat opening TV1 on the substrate.

[0224] In an exemplary embodiment, an orthographic projection area of ​​the twenty-first via hole V21 on the substrate may be greater than an orthographic projection area of ​​the ninth via hole V9 on the substrate.

[0225] In an exemplary embodiment, the twenty-second via hole V22 can be arranged in the light-transmitting area 120, and the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the first auxiliary electrode 35 on the substrate. The third insulating layer in the twenty-second via hole V22 is etched away to expose the surface of the first auxiliary electrode 35, and the twenty-second via hole V22 is configured to connect the subsequently formed second auxiliary electrode to the first auxiliary electrode 35 through the via hole.

[0226] In an exemplary embodiment, the twenty-second via hole V22 serves as the auxiliary electrode via hole of the present disclosure, and the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the flat opening TV1 on the substrate.

[0227] In an exemplary embodiment, the orthographic projection area of ​​the twenty-second via hole V22 (ie, the auxiliary electrode via hole) on the substrate may be larger than the orthographic projection area of ​​the twenty-first via hole V21 (ie, the second plate via hole) on the substrate.

[0228] In an exemplary embodiment, a first distance L1 is provided between an edge of the twenty-first via V21 away from the second power line 52 and an edge of the second power line 52 close to the twenty-first via V21, and a second distance L2 is provided between an edge of at least one twenty-second via V22 away from the second power line 52 and an edge of the second power line 52 close to the twenty-second via V22. The first distance L1 may be smaller than the second distance L2.

[0229] In an exemplary embodiment, the patterning process may use a half tone mask process.

[0230] After this patterning process, the main film layers of the light-transmitting region 120 include a first insulating layer, a second insulating layer, and a third insulating layer.

[0231] (6) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film through a patterning process to form a third conductive layer pattern, as shown in FIG12A and FIG12B , where FIG12B is a schematic diagram of the third conductive layer in FIG12A .

[0232] In an exemplary embodiment, the third conductive layer of each sub-pixel in the display substrate may include at least a first electrode 61. The first electrode 61 may include a first sub-electrode 61-1, a second sub-electrode 61-2, and a sub-connecting electrode 61-3. In an exemplary embodiment, the first electrode 61 may serve as one electrode of the anode of the light-emitting device.

[0233] In an exemplary embodiment, on the flat layer of the display area 110, the first sub-electrode 61-1 and the second sub-electrode 61-2 are arranged in isolation, the shapes of the first sub-electrode 61-1 and the second sub-electrode 61-2 can be rectangular, and the first sub-electrode 61-1 and the second sub-electrode 61-2 can be arranged in sequence along the second direction Y.

[0234] In an exemplary embodiment, the main portion of the sub-connecting electrode 61-3 may be disposed on the third insulating layer. The sub-connecting electrode 61-3 may be shaped like a "C," with a first end connected to the first sub-electrode 61-1, a second end connected to the second sub-electrode 61-2, and an area between the first and second ends connected to the second sub-connecting electrode 50-2 of the plate-connecting electrodes via a twenty-first via hole V21. In an exemplary embodiment, the sub-connecting electrode 61-3 interconnects the first sub-electrode 61-1 and the second sub-electrode 61-2. Because the sub-connecting electrode 61-3 is connected to the plate-connecting electrode 50, and the plate-connecting electrode 50 is connected to the first plate 11, the first electrode 61 and the first plate 11 of the storage capacitor have the same potential.

[0235] In an exemplary embodiment, when a bright spot defect occurs on the display substrate, the sub-connecting electrode 61-3 can be cut off by laser cutting, so that one of the first sub-electrode 61-1 and the second sub-electrode 61-2 is connected to the first electrode plate 11 and the other is floating, thereby repairing the bright spot defect.

[0236] In an exemplary embodiment, the twenty-first via hole V21 serves as the second plate via hole of the present invention. The orthographic projection of the twenty-first via hole V21 on the substrate does not overlap with the orthographic projections of the first sub-electrode 61-1 and the second sub-electrode 61-2 on the substrate. This not only improves the success rate of repairing bright spot defects and avoids the impact of the repair on the pixel driving circuit, but also ensures the flatness of the first electrode, improves the light output quality of the light-emitting device, and improves the display effect.

[0237] In an exemplary embodiment, the four first electrodes 61 in a repeating unit can be arranged in a square, with the upper left first electrode 61 connected to the pixel driving circuit in the first subpixel P1, the upper right first electrode 61 connected to the pixel driving circuit in the second subpixel P2, the lower left first electrode 61 connected to the pixel driving circuit in the third subpixel P3, and the lower right first electrode 61 connected to the pixel driving circuit in the fourth subpixel P4. In some possible implementations, the arrangement of the first electrodes can be adjusted according to actual needs and is not specifically limited in this disclosure.

[0238] In an exemplary embodiment, the first sub-electrode 61 - 1 , the second sub-electrode 61 - 2 , and the sub-connection electrode 61 - 3 of each sub-pixel may be an integral structure connected to each other.

[0239] In an exemplary embodiment, the third conductive layer of at least one repeating unit may further include a second auxiliary electrode 36. A plurality of second auxiliary electrodes 36 may be disposed in the light-transmitting region 120 on one side of the second subpixel P2 and the fourth subpixel P4 in the first direction X. The second auxiliary electrodes 36 may be rectangular in shape, with the orthographic projection of the second auxiliary electrode 36 on the substrate at least partially overlapping with the orthographic projection of the first auxiliary electrode 35 on the substrate. The second auxiliary electrodes 36 may be connected to the first auxiliary electrode 35 via a twenty-second via hole V22. The second auxiliary electrodes 36 are configured to be connected to a subsequently formed third auxiliary electrode.

[0240] In an exemplary embodiment, the third conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0241] After this patterning process, the main film layer of the light-transmitting area 120 remains unchanged.

[0242] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film through a patterning process to form a fourth conductive layer pattern, as shown in FIG13A and FIG13B , where FIG13B is a schematic diagram of the fourth conductive layer in FIG13A .

[0243] In an exemplary embodiment, the fourth conductive layer of each sub-pixel in the display substrate may include at least a second electrode 62. In an exemplary embodiment, the second electrode 62 may serve as another electrode of an anode of the light emitting device.

[0244] In an exemplary embodiment, the second electrode 62 may be disposed on the first sub-electrode 61-1 and the second sub-electrode 61-2 in the first electrode 61 of the display area 110. The second electrode 62 in at least one sub-pixel may include a third sub-electrode 62-1 and a fourth sub-electrode 62-2 that are separated from each other. The third sub-electrode 62-1 and the fourth sub-electrode 62-2 may be rectangular in shape and may be sequentially disposed along the second direction Y.

[0245] In the exemplary embodiment, the orthographic projection of the third sub-electrode 62-1 on the substrate at least partially overlaps with the orthographic projection of the first sub-electrode 61-1 on the substrate, and the third sub-electrode 62-1 directly overlaps with the first sub-electrode 61-1. The orthographic projection of the fourth sub-electrode 62-2 on the substrate at least partially overlaps with the orthographic projection of the second sub-electrode 61-2 on the substrate, and the fourth sub-electrode 62-2 directly overlaps with the second sub-electrode 61-2.

[0246] In an exemplary embodiment, the fourth conductive layer of at least one repeating unit may further include a third auxiliary electrode 37. A plurality of third auxiliary electrodes 37 may be disposed in the light-transmitting region 120 on one side of the second subpixel P2 and the fourth subpixel P4 in the first direction X. The third auxiliary electrodes 37 may be rectangular in shape and may be disposed on the second auxiliary electrode 36. The orthographic projection of the third auxiliary electrode 37 on the substrate at least partially overlaps with the orthographic projection of the second auxiliary electrode 36 on the substrate, and the third auxiliary electrode 37 directly overlaps the second auxiliary electrode 36. In an exemplary embodiment, the third auxiliary electrode 37 is configured to connect to a subsequently formed third electrode.

[0247] In an exemplary embodiment, the third auxiliary electrode 37 can adopt an isolation column (RIB) structure, and the cross-sectional shape of the third auxiliary electrode 37 can be an inverted trapezoid, so that the subsequently formed organic light-emitting layer can be disconnected at the side edge of the third auxiliary electrode 37 to form an isolated and isolated organic light-emitting block, which effectively avoids the interference of the organic light-emitting block on the outgoing light, improves the quality of the outgoing light, and is conducive to improving the display quality.

[0248] In an exemplary embodiment, the stacked first auxiliary electrode 35 , the second auxiliary electrode 36 , and the third auxiliary electrode 37 constitute auxiliary electrodes.

[0249] In an exemplary embodiment, the fourth conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0250] After this patterning process, the main film layer of the light-transmitting area 120 remains unchanged.

[0251] (8) Forming a pixel definition layer. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on the substrate having the aforementioned pattern formed thereon, and patterning the pixel definition film through a patterning process to form a pixel definition layer, as shown in FIG. 14 .

[0252] In an exemplary embodiment, in at least one repeating unit, a main portion of the pixel definition layer covers the display area 110 , and at least a first pixel opening K1 , a second pixel opening K2 , and a light-transmitting opening TV2 are provided on the pixel definition layer.

[0253] In an exemplary embodiment, a first pixel opening K1 and a second pixel opening K2 may be provided in each sub-pixel. The orthographic projection of the first pixel opening K1 on the substrate is within the range of the orthographic projection of the third sub-electrode 62-1 of the second electrode 62 on the substrate. The pixel definition film within the first pixel opening K1 is removed, exposing a portion of the surface of the third sub-electrode 62-1. The orthographic projection of the second pixel opening K2 on the substrate is within the range of the orthographic projection of the fourth sub-electrode 62-2 of the second electrode 62 on the substrate. The pixel definition film within the second pixel opening K2 is removed, exposing a portion of the surface of the fourth sub-electrode 62-2.

[0254] In an exemplary embodiment, in a plane parallel to the substrate, the shapes of the first pixel opening K1 and the second pixel opening K2 may be similar to the shapes of the sub-electrodes, and in a plane perpendicular to the substrate, the cross-sectional shapes of the first pixel opening K1 and the second pixel opening K2 may be rectangular or inverted trapezoidal, etc.

[0255] In an exemplary embodiment, the pixel definition film within the light-transmitting opening TV2 is removed to form the light-transmitting region 120. A shielding groove may be provided on a side of the light-transmitting opening TV2 close to the display region 110, and the second plate via hole YV and the sub-connecting electrode 61-3 may be provided in the shielding groove so that the pixel definition layer can shield the second plate via hole YV and the sub-connecting electrode 61-3.

[0256] In an exemplary embodiment, the orthographic projection of the second plate via hole YV on the substrate does not overlap with the orthographic projection of the light-transmitting opening TV2 on the substrate.

[0257] In an exemplary embodiment, the orthographic projections of the plurality of third auxiliary electrodes 37 on the substrate are located within the range of the orthographic projections of the light-transmitting opening TV2 on the substrate.

[0258] In an exemplary embodiment, the pixel definition layer may be made of polyimide, acryl, polyethylene terephthalate, or the like.

[0259] (9) Forming an organic light-emitting layer and a third electrode pattern. In an exemplary embodiment, forming the organic light-emitting layer and the third electrode pattern may include: first forming an organic light-emitting layer pattern in the display area 110, wherein the organic light-emitting layer is connected to the third sub-electrode and the fourth sub-electrode through the first pixel opening K1 and the second pixel opening K2, respectively. Subsequently, a third electrode is formed, wherein the third electrode is connected to the organic light-emitting layer in the display area 110, and the third electrode is connected to the third auxiliary electrode in the light-transmitting area 120 through the auxiliary electrode opening K3. Since the third auxiliary electrode is connected to the second power line, the connection between the third electrode and the second power line is achieved. In an exemplary embodiment, the third electrode may be the cathode of the light-emitting device.

[0260] In an exemplary embodiment, the organic light-emitting layer may include an emission layer (EML), and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the organic light-emitting layer may be formed using a fine metal mask (FMM) or open mask evaporation, or using an inkjet process.

[0261] In an exemplary embodiment, the preparation process of the display substrate may further include forming an encapsulation structure layer pattern. The formation of the encapsulation structure layer pattern may include: first depositing a first inorganic thin film using an open mask to form a first encapsulation layer. Subsequently, inkjet printing an organic material on the first encapsulation layer using an inkjet printing process, and after curing into a film, forming a second encapsulation layer. Subsequently, an open mask is used to deposit a second inorganic thin film to form a third encapsulation layer, and the first encapsulation layer, the second encapsulation layer and the third encapsulation layer constitute an encapsulation structure layer. The first encapsulation layer and the third encapsulation layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), silicon carbonitride (SiCN) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer. The second encapsulation layer can be made of a resin material to form a laminated structure of inorganic material / organic material / inorganic material. The organic material layer is arranged between the two inorganic material layers to ensure that external water vapor cannot enter the light-emitting structure layer.

[0262] In an exemplary embodiment, the preparation process of the display substrate may further include forming film layers such as a color filter layer and a black matrix. The black matrix has a plurality of opening areas arranged in a matrix, and the color filter layer is filled in the opening areas. This disclosure does not limit this.

[0263] At this point, the preparation of the display substrate according to the exemplary embodiment of the present disclosure is completed.

[0264] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0265] In an exemplary embodiment, the first conductive layer and the second conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, and the third insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The planar layer can be made of an organic material, such as a resin.

[0266] From the structure and preparation process of the display substrate described above, it can be seen that the display substrate provided by the embodiment of the present disclosure achieves a matching of high aperture ratio and high transmittance through the optimized design of the layout, using the plate connection electrode to connect to the first electrode and the first plate respectively, and the second plate via is arranged on the side of the first plate via close to the light-transmitting area, thereby achieving a matching of high aperture ratio and high transmittance. In the embodiment of the present disclosure, the first plate of the storage capacitor is arranged in the first conductive layer, the plate connection electrode is arranged in the second conductive layer, and the first electrode of the light-emitting device is arranged in the third conductive layer. The plate connection electrode is connected to the first plate through the first plate via, and the first electrode is connected to the plate connection electrode through the second plate via, thereby achieving a connection between the light-emitting device and the pixel driving circuit. In the embodiment of the present disclosure, by arranging the first plate via on the side of the first power line or the second power line away from the light-transmitting area and the second plate via on the side of the first power line or the second power line close to the light-transmitting area, the second plate via does not affect the arrangement of the first electrode or the flatness of the first electrode, thereby increasing the area of ​​the first electrode and the pixel opening, effectively improving the pixel aperture ratio of the display area. The embodiment of the present disclosure arranges the second electrode plate via on the side of the first power line or the second power line close to the light-transmitting area, and uses the electrode connecting electrode and the second electrode plate via to change the light-transmitting area into an irregular shape, thereby reducing the diffraction effect of the light-transmitting area and effectively improving the transmittance of the light-transmitting area.

[0267] The embodiment of the present disclosure arranges structures such as the first power line, the data signal line, and the compensation signal line in the first conductive layer, and arranges structures such as the scanning signal line in the second conductive layer, thereby not only reducing one conductive layer, but also reducing the patterning process of the transfer via and the patterning process of the transfer conductive layer, so that the preparation process of the display substrate only requires eight patterning processes, reducing the number of patterning processes, effectively improving production efficiency, effectively reducing production costs, and maximizing product yield.

[0268] The disclosed embodiment adopts a 3T1C pixel driving circuit with one scanning signal line, where one scanning signal line is connected to the first transistor and the third transistor in the pixel driving circuit. By reducing the number of scanning signal lines, not only can the structure of the pixel driving circuit be simplified and the occupied area of ​​the pixel driving circuit be reduced, which is conducive to achieving high-resolution display, but the number of corresponding gate driving circuits (GOA) and clock signal lines (CLK) can also be reduced exponentially, effectively reducing the occupied area of ​​the gate driving circuit and the clock signal line, which is conducive to achieving a narrow frame and improving product advantages.

[0269] The first conductive layer of the embodiment of the present disclosure adopts longitudinal wiring, and the second conductive layer adopts transverse wiring. A single-line structure is set in the light-transmitting area, and a double-line structure is set in the display area. This not only ensures that the scanning signal line drives all pixel driving circuits in the repeated area, but also realizes the dual-channel function, which can repair the signal lines at all positions, realizes the repair of full signal short circuit defects, and effectively improves the product yield.

[0270] The present disclosure exemplarily sets a one-to-four structure for the first power line and a one-to-four structure for the compensation signal line, thereby saving the number of signal lines and reducing the occupied space. It has a simple structure and a reasonable layout, fully utilizing the layout space, improving space utilization, and facilitating improved resolution.

[0271] The exemplary embodiments of the present disclosure can effectively increase the pixel aperture ratio and improve the display effect by adopting a first power line structure with a non-mesh structure.

[0272] The embodiment of the present disclosure sets two sub-electrodes in a sub-pixel, and the two sub-electrodes are connected by a sub-connecting electrode. This not only improves the success rate of repairing bright spot defects, avoids the impact of the repair on the pixel driving circuit, and does not cause other defects, but also has a high repair success rate. It can also ensure the flatness of the first electrode, improve the light output quality of the light-emitting device, and improve the display effect.

[0273] The embodiment of the present disclosure provides a second power line and an auxiliary electrode, and the second power line is connected to the third electrode of the light-emitting device through the auxiliary electrode, which can effectively reduce the voltage drop of the power signal and ensure display uniformity.

[0274] The preparation process of the exemplary embodiment of the present disclosure is well compatible with the existing preparation process, and the process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield rate.

[0275] The structure and preparation process described above are merely exemplary. In exemplary embodiments, the corresponding structure may be modified and patterning processes may be added or reduced as needed. For example, forming the third insulating layer and the planarization layer pattern may utilize two patterning processes, resulting in a display substrate preparation process requiring nine patterning processes. This is not a limitation of the present disclosure.

[0276] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0277] The present disclosure also provides a method for preparing a display substrate to prepare the display substrate provided in the above embodiment. In an exemplary embodiment, the display substrate includes a plurality of repeating units, at least one repeating unit including a display area and a light-transmitting area located on at least one side of the display area, the display area being configured to display an image, and the light-transmitting area being configured to transmit light; the display area including a plurality of sub-pixels, at least one sub-pixel including a pixel driving circuit and a light-emitting device, the pixel driving circuit including at least a storage capacitor, the storage capacitor including at least a first plate, the light-emitting device including at least a first electrode, the first electrode being connected to the first plate via a plate connecting electrode; the preparation method may include:

[0278] Multiple conductive layers are formed on the substrate, the first plate, the plate connecting electrode and the first electrode are arranged in different conductive layers, the first plate is connected to the plate connecting electrode through a first plate via, the first electrode is connected to the plate connecting electrode through a second plate via, and in at least one sub-pixel, the second plate via is arranged on a side of the first plate via close to the light-transmitting area.

[0279] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0280] While the embodiments disclosed herein are as described above, it should be noted that the above embodiments are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a plurality of repeating units, at least one repeating unit comprising a display area and a light-transmitting area located on at least one side of the display area, the display area being configured to display an image, and the light-transmitting area being configured to transmit light; the display area comprising a plurality of sub-pixels, at least one sub-pixel comprising a pixel driving circuit and a light-emitting device, the pixel driving circuit comprising at least a storage capacitor, the storage capacitor comprising at least a first plate, the light-emitting device comprising at least a first electrode, the first electrode being connected to the first plate via a plate connecting electrode; in a direction perpendicular to the display substrate, the display substrate comprises at least a plurality of conductive layers arranged on a base, the first plate, the plate connecting electrode and the first electrode being arranged in different conductive layers, the first plate being connected to the plate connecting electrode via a first plate via, the first electrode being connected to the plate connecting electrode via a second plate via, and in at least one sub-pixel, the second plate via being arranged on a side of the first plate via close to the light-transmitting area.

2. The display substrate according to claim 1, wherein The display area also includes a first power line, which is configured to provide a first power signal to the pixel driving circuit, and the first power line is arranged on a side of the display area close to the light-transmitting area; the first electrode via is arranged on a side of the first power line away from the light-transmitting area, and the second electrode via is arranged on a side of the first power line close to the light-transmitting area, and the orthographic projection of the electrode connecting electrode on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate.

3. The display substrate according to claim 1, wherein The display area also includes a second power line, which is configured to provide a second power signal to the light-emitting device, and the second power line is arranged on a side of the display area close to the light-transmitting area; the first plate via is arranged on a side of the second power line away from the light-transmitting area, and the second plate via is arranged on a side of the second power line close to the light-transmitting area, and the orthographic projection of the plate connecting electrode on the substrate at least partially overlaps with the orthographic projection of the second power line on the substrate.

4. The display substrate according to claim 3, wherein: The light-transmitting area also includes at least one first auxiliary electrode and at least one second auxiliary electrode, the second auxiliary electrode is connected to the first auxiliary electrode through an auxiliary electrode via, and the first auxiliary electrode is connected to the second power line; there is a first distance between the edge of the second plate via away from the second power line and the edge of the second power line close to the second plate via, and there is a second distance between the edge of at least one auxiliary electrode via away from the second power line and the edge of the second power line close to the auxiliary electrode via, and the first distance is smaller than the second distance.

5. The display substrate according to claim 4, wherein: The area of the orthographic projection of the auxiliary electrode via hole on the substrate is larger than the area of the orthographic projection of the second electrode plate via hole on the substrate.

6. The display substrate according to any one of claims 1 to 5, wherein: The area of the orthographic projection of the second electrode plate via hole on the substrate is larger than the area of the orthographic projection of the first electrode plate via hole on the substrate.

7. The display substrate according to any one of claims 1 to 5, wherein: The multiple conductive layers include at least a first conductive layer arranged on the substrate, a second conductive layer arranged on a side of the first conductive layer away from the substrate, and a third conductive layer arranged on a side of the second conductive layer away from the substrate, the first electrode is arranged in the first conductive layer, the electrode connecting electrode is arranged in the second conductive layer, and the first electrode is arranged in the third conductive layer.

8. The display substrate according to claim 7, wherein: The display substrate also includes a first insulating layer, a second insulating layer and a third insulating layer, the first insulating layer is arranged on a side of the first conductive layer away from the substrate, the second insulating layer is arranged on a side of the first insulating layer away from the substrate, the second conductive layer is arranged on a side of the second insulating layer away from the substrate, the third insulating layer is arranged on a side of the second conductive layer away from the substrate, and the third conductive layer is arranged on a side of the third insulating layer away from the substrate; the first electrode via is arranged in the first insulating layer and the second insulating layer, and the second electrode via is arranged in the third insulating layer.

9. The display substrate according to any one of claims 1 to 5, wherein: In at least one sub-pixel, the storage capacitor further includes a second electrode plate, the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate, and the second electrode plate and the electrode connecting electrode are arranged in the same layer.

10. The display substrate according to claim 9, wherein: In at least one sub-pixel, a plate groove is provided on the second plate, and the orthographic projection of the first plate via hole on the substrate is located within the range of the orthographic projection of the plate groove on the substrate.

11. The display substrate according to any one of claims 1 to 5, wherein: In at least one sub-pixel, the plate connecting electrode includes at least a first sub-connecting electrode and a second sub-connecting electrode, the first end of the first sub-connecting electrode is connected to the first plate through the first plate via, the second end of the first sub-connecting electrode extends toward the direction close to the light-transmitting area and is connected to the second sub-connecting electrode, and the first electrode is connected to the second sub-connecting electrode through the second plate via.

12. The display substrate according to claim 11, wherein: In at least one sub-pixel, the first sub-connecting electrode and the second sub-connecting electrode are provided in the same layer and are interconnected as an integral structure.

13. The display substrate according to any one of claims 1 to 5, wherein: In at least one sub-pixel, the first electrode includes at least a first sub-electrode, a second sub-electrode and a sub-connecting electrode, the first sub-electrode and the second sub-electrode are isolated from each other, the sub-connecting electrode is in a "C" shape, the first end of the sub-connecting electrode is connected to the first sub-electrode, the second end of the sub-connecting electrode is connected to the second sub-electrode, and the area between the first end and the second end is connected to the plate connecting electrode through the second plate via.

14. The display substrate according to claim 13, wherein: In at least one sub-pixel, the first sub-electrode, the second sub-electrode and the sub-connecting electrode are arranged in the same layer and are an integrated structure connected to each other.

15. The display substrate according to claim 13, wherein: In at least one sub-pixel, the orthographic projection of the first sub-electrode on the substrate does not overlap with the orthographic projection of the first electrode via on the substrate, and the orthographic projection of the second sub-electrode on the substrate does not overlap with the orthographic projection of the first electrode via on the substrate.

16. The display substrate according to claim 13, wherein: In at least one sub-pixel, the display area further includes a second electrode arranged on a side of the first electrode away from the substrate, the second electrode includes a third sub-electrode and a fourth sub-electrode arranged in isolation, the orthographic projection of the third sub-electrode on the substrate at least partially overlaps with the orthographic projection of the first sub-electrode on the substrate, the third sub-electrode overlaps with the first sub-electrode, the orthographic projection of the fourth sub-electrode on the substrate at least partially overlaps with the orthographic projection of the second sub-electrode on the substrate, the fourth sub-electrode overlaps with the second sub-electrode, the orthographic projection of the third sub-electrode on the substrate does not overlap with the orthographic projection of the first electrode plate via on the substrate, and the orthographic projection of the fourth sub-electrode on the substrate does not overlap with the orthographic projection of the first electrode plate via on the substrate.

17. The display substrate according to claim 16, wherein: The display substrate also includes a pixel definition layer arranged on the side of the second electrode away from the substrate. In at least one sub-pixel, a first pixel opening and a second pixel opening are provided on the pixel definition layer, the first pixel opening exposes the third sub-electrode, and the second pixel opening exposes the fourth sub-electrode. The orthographic projection of the first pixel opening on the substrate does not overlap with the orthographic projection of the first electrode plate via on the substrate, and the orthographic projection of the second pixel opening on the substrate does not overlap with the orthographic projection of the first electrode plate via on the substrate.

18. The display substrate according to claim 17, wherein: In the light-transmitting area, a light-transmitting opening is provided on the pixel definition layer, and an orthographic projection of the light-transmitting opening on the substrate does not overlap with an orthographic projection of the second electrode plate via on the substrate.

19. A display device comprising the display substrate according to any one of claims 1 to 18.

20. A method for preparing a display substrate, the display substrate comprising a plurality of repeating units, at least one repeating unit comprising a display area and a light-transmitting area located on at least one side of the display area, the display area being configured to display an image, and the light-transmitting area being configured to transmit light; the display area comprising a plurality of sub-pixels, at least one sub-pixel comprising a pixel driving circuit and a light-emitting device, the pixel driving circuit comprising at least a storage capacitor, the storage capacitor comprising at least a first plate, the light-emitting device comprising at least a first electrode, the first electrode being connected to the first plate via a plate connecting electrode; the preparation method comprising: Multiple conductive layers are formed on the substrate, the first plate, the plate connecting electrode and the first electrode are arranged in different conductive layers, the first plate is connected to the plate connecting electrode through a first plate via, the first electrode is connected to the plate connecting electrode through a second plate via, and in at least one sub-pixel, the second plate via is arranged on a side of the first plate via close to the light-transmitting area.

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