Display panel

Abstract

The present application provides a display panel. The display panel comprises an array substrate, a planarization layer, a first electrode layer, a spacing layer, a pixel define layer, a light-emitting layer, and a second electrode layer. The spacing layer comprises spacing parts arranged between every two adjacent first electrodes of the first electrode layer, and each spacing part comprises a recess having an opening direction away from the array substrate and protrusions extending towards the center of the recess. The maximum depth of each recess is greater than or equal to the sum of the thicknesses of a first light-emitting sub-layer and a charge generation layer of the light-emitting layer, and the first light-emitting sub-layer and the charge generation layer are disconnected at the spacing parts. According to the display panel provided in the present application, the problem of unexpected lighting of pixels can be mitigated.

Description

Display panel Technical Field

[0001] The present application relates to the field of display, and in particular to a display panel. Background Art

[0002] Organic Light Emitting Diode (OLED) is widely used in the display field due to its excellent properties such as self-luminescence, high contrast, wide viewing angle, low power consumption, and bendability. It is used in displays of electronic devices such as mobile phones, computers, and televisions.

[0003] In order to further reduce power consumption and achieve high brightness, the light-emitting structure in the OLED display panel will be set to a structure in which multiple light-emitting layers are superimposed, and a common functional layer is set between adjacent light-emitting layers to connect them, forming a tandem OLED (Tandem OLED).

[0004] However, due to the demand for high resolution, the pixel pitch of the display panel is designed to be very small, resulting in the distance between adjacent light-emitting structures in the display panel being very close. At the same time, the common functional layers continuously arranged in the series-connected OLED have strong conductivity. Therefore, lateral leakage current is prone to occur in the common functional layers, making it impossible to completely turn off the pixels that should be turned off during display, resulting in the problem of stealth lighting, which seriously affects the display quality of the display panel. SUMMARY OF THE INVENTION

[0005] The embodiments of the present application provide a display panel that can improve the pixel brightness problem and enhance the display quality of the display panel.

[0006] The embodiment of the present application provides a display panel, which includes: an array substrate; a flat layer, which is arranged on the array substrate; a first electrode layer, which is arranged on a surface of the flat layer away from the array substrate, the first electrode layer including a plurality of first electrodes arranged at intervals; a spacer layer, which is arranged on a surface of the flat layer away from the array substrate, the spacer layer including a plurality of spacers arranged between two adjacent first electrodes, the spacers including grooves with openings away from the array substrate and protrusions extending toward the centers of the grooves; a pixel definition layer, which is arranged on surfaces of the first electrode layer and the spacer layer away from the array substrate, the pixel definition layer including a plurality of spacers arranged between adjacent first electrodes, the spacers including grooves with openings away from the array substrate and protrusions extending toward the centers of the grooves; and a pixel definition layer. A first opening and a second opening are provided on a surface of the pixel definition layer away from the flat layer, the first opening exposes at least a portion of the corresponding first electrode, and the second opening is connected to the corresponding groove; a light-emitting layer is provided on a surface of the pixel definition layer away from the array substrate, the light-emitting layer includes a first light-emitting sublayer, a charge generation layer and a second light-emitting sublayer stacked in sequence; a second electrode layer is provided on a surface of the light-emitting layer away from the array substrate; wherein the maximum depth of the groove is greater than or equal to the sum of the thicknesses of the first light-emitting sublayer and the charge generation layer, and in the light-emitting layer, at least the first light-emitting sublayer and the charge generation layer are disconnected at the spacer.

[0007] In one embodiment of the present application, the maximum depth of the groove is less than or equal to the thickness of the light-emitting layer.

[0008] In one embodiment of the present application, the second electrode layer is not disconnected at the spacing portion.

[0009] In one embodiment of the present application, the spacing layer includes a first spacing sublayer and a second spacing sublayer, the first spacing sublayer is arranged on a surface of the second spacing sublayer away from the flat layer, the first spacing sublayer includes a plurality of third openings arranged corresponding to the spacing portions, the second spacing sublayer includes a plurality of fourth openings arranged corresponding to the spacing portions, the groove includes the third opening and the fourth opening, and the third opening and the fourth opening are connected.

[0010] In one embodiment of the present application, the thickness of the second spacer sublayer is 0.05 micrometers to 0.4 micrometers.

[0011] In one embodiment of the present application, an opening size of the fourth opening close to one end of the first spacer sub-layer is smaller than an opening size of the third opening.

[0012] In one embodiment of the present application, an etching rate of the first spacer sub-layer is lower than an etching rate of the second spacer sub-layer.

[0013] In one embodiment of the present application, the angle between the line connecting the two end points of the side wall of the third opening of the first spacer sublayer and a surface of the first spacer sublayer close to the array substrate is a first angle, and the angle between the line connecting the two end points of the side wall of the fourth opening of the second spacer sublayer and a surface of the second spacer sublayer close to the array substrate is a second angle, and the first angle is greater than the second angle.

[0014] In one embodiment of the present application, the spacing layer also includes a third spacing sublayer, which is arranged between the second spacing sublayer and the flat layer; the third spacing sublayer includes a plurality of sub-grooves arranged corresponding to the spacing parts, and the grooves include the sub-grooves, and the openings of the sub-grooves are arranged toward the second spacing sublayer and are connected to the corresponding fourth opening.

[0015] In one embodiment of the present application, the sidewall of the fourth opening of the second spacer sublayer includes a first arc surface, the sub-groove of the third spacer sublayer includes a second arc surface, and the curvature radius of the second arc surface is greater than the curvature radius of the first arc surface.

[0016] In one embodiment of the present application, the second arc surface is continuous with the first arc surface adjacent to the second arc surface.

[0017] In one embodiment of the present application, an etching rate of the third spacer sub-layer is lower than an etching rate of the second spacer sub-layer.

[0018] In one embodiment of the present application, the angle between the line connecting the two end points of the side wall of the third opening of the first spacer sublayer and a surface of the first spacer sublayer close to the array substrate is a first angle, the angle between the line connecting the two end points of the side wall of the fourth opening of the second spacer sublayer and a surface of the second spacer sublayer close to the array substrate is a second angle, and the angle between the line connecting the two end points of the side wall of the sub-groove of the third spacer sublayer and a surface of the third spacer sublayer close to the array substrate is a third angle, the first angle is greater than the second angle, and the second angle is greater than the third angle.

[0019] In one embodiment of the present application, the thickness of the third spacer sublayer is greater than 3 nanometers.

[0020] In one embodiment of the present application, a distance between an edge of the protrusion of the first spacer sublayer facing the center of the groove and an edge of the fourth opening close to one end of the first spacer sublayer is greater than or equal to 1 micron.

[0021] In one embodiment of the present application, the thickness of the first spacer sublayer is in a range of 0.01 micrometers to 0.1 micrometers.

[0022] In an embodiment of the present application, the spacer surrounds the corresponding first electrode.

[0023] In one embodiment of the present application, the spacer is entirely surrounded by a circumference of the first electrode.

[0024] In one embodiment of the present application, the spacer is partially surrounded by a circumference of the first electrode.

[0025] In one embodiment of the present application, two second openings are provided between two adjacent first openings, two spacers are provided between two adjacent first electrodes, and one second opening is connected to the groove of a corresponding spacer. Beneficial effects

[0026] In the display panel provided in the embodiment of the present application, a spacer is provided between two adjacent first electrodes, the spacer includes a groove with an opening direction away from the array substrate and a protrusion extending toward the center of the groove, the maximum depth of the groove is greater than or equal to the sum of the thicknesses of the first light-emitting sublayer and the charge generation layer, and in the light-emitting layer, at least the first light-emitting sublayer and the charge generation layer are disconnected at the spacer, thereby isolating the conduction path of the lateral leakage current between pixels, improving the crosstalk problem between pixels caused by the lateral leakage current in the display panel, thereby improving the pixel stealing problem, and improving the display quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG1 is a schematic diagram of a first cross-sectional structure of a display panel provided in an embodiment of the present application.

[0028] FIG2 is a schematic diagram of the structure of the light-emitting layer of the display panel provided in an embodiment of the present application.

[0029] FIG3 is a schematic diagram of a second cross-sectional structure of a display panel provided in an embodiment of the present application.

[0030] FIG. 4 is a schematic diagram of the structure of a spacer layer of the display panel shown in FIG. 1 .

[0031] FIG. 5 is a top view of the display panel shown in FIG. 1 .

[0032] FIG6 is a schematic diagram of a third cross-sectional structure of a display panel provided in an embodiment of the present application.

[0033] FIG. 7 is a top view of the display panel shown in FIG. 6 .

[0034] FIG8 is a flow chart of a method for manufacturing a display panel provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0035] To make the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0036] In this disclosure, unless otherwise specified, directional terms such as "upper" and "lower" generally refer to the upper and lower parts of a device in actual use or operation. Directional terms such as "inner" and "outer" refer to the inner and outer parts relative to the outline of each component. In the description of this disclosure, "plurality" means at least two, such as two or three, unless otherwise specifically defined. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the technical features being referred to.

[0037] 1 , a display panel 100 provided in one embodiment of the present application includes an array substrate 10 , a planar layer 20 , a first electrode layer 30 , a spacer layer 40 , a pixel definition layer 50 , a light emitting layer 60 and a second electrode layer 70 .

[0038] Specifically, the planar layer 20 is disposed on the array substrate 10 to provide a flat surface for the subsequent arrangement of the first electrode layer 30. The material of the planar layer 20 can be an organic material with a low dielectric constant, such as polyimide.

[0039] The first electrode layer 30 is disposed on a surface of the planar layer 20 away from the array substrate 10. The first electrode layer 30 includes a plurality of first electrodes 31 spaced apart from each other. The first electrode 31 may be an anode and may be selected from a material with a high work function to improve hole injection efficiency, such as gold, platinum, titanium, silver, indium tin oxide (ITO), zinc tin oxide (IZO), or a transparent conductive polymer (such as polyaniline).

[0040] The spacer layer 40 is disposed on a surface of the planar layer 20 that is away from the array substrate 10. The spacer layer 40 includes a plurality of spacers 41 disposed between adjacent first electrodes 31. The spacers 41 include grooves 411 opening away from the array substrate 10 and protrusions 412 extending toward the center of the grooves 411. Due to the obstruction provided by the protrusions 412, when the light-emitting layer 60 is subsequently formed, no light-emitting layer 60 will be deposited in the area within the grooves 411, which is a perpendicular projection of the protrusions 412 on the array substrate 10. This makes it easier to disconnect the light-emitting layer 60 at the spacers 41.

[0041] The pixel definition layer 50 is arranged on a surface of the first electrode layer 30 and the spacer layer 40 away from the array substrate 10. The surface of the pixel definition layer 50 away from the flat layer 30 is provided with a first opening 51 and a second opening 52. The first opening 51 exposes at least a portion of the corresponding first electrode 31, and the second opening 52 is connected to the corresponding groove 411. The material of the pixel definition layer 50 can be hexamethyldisiloxane, epoxy resin or polyimide, and can also be other silicone adhesive materials with a transmittance of more than 90%, or other organic adhesive materials with a transmittance greater than 80% and slightly higher bending strength. In addition, a support column PS is also provided on the pixel definition layer 50. The support column PS is used to support the mask plate during the evaporation process. In order not to affect the opening of the second opening 52, the second opening 52 is arranged away from the support column PS.

[0042] The light-emitting layer 60 is disposed on a surface of the pixel definition layer 50 facing away from the array substrate 10. Referring to Figure 2 , the light-emitting layer 60 comprises a first light-emitting sublayer 61, a charge generation layer 62, and a second light-emitting sublayer 63, stacked in sequence. The first and second light-emitting sublayers 61 and 62 are used to generate light and may include layers such as an electron injection layer, an electron transport layer, an organic light-emitting material layer, a hole transport layer, and a hole injection layer. The charge generation layer 62, disposed between the first and second light-emitting sublayers 61 and 62, connects the first and second light-emitting layers 521 and 523 to form a tandem OLED device, thereby reducing power consumption and improving brightness. The charge generation layer 62 can be formed by open mask evaporation. The charge generation layer 62 typically comprises an organic material with a high carrier transport rate and is doped with an active metal such as lithium or ytterbium. This material exhibits strong electrical conductivity, enabling efficient conduction between the first and second light-emitting sublayers 61 and 62, but also tends to generate lateral current.

[0043] The second electrode layer 70 is disposed on a surface of the light-emitting layer 60 that is distal from the array substrate 10. It forms an electric field with the first electrode layer 30, driving the light-emitting layer 60 to emit light. The second electrode layer 70 can serve as a cathode and can be selected from a material with a low work function to facilitate electron injection, such as silver (Ag), aluminum (Al), lithium (Li), magnesium (Mg), ytterbium (Yb), calcium (Ca), or indium (In). It can also be an alloy of the aforementioned metals, such as magnesium-silver alloy (Mg / Ag) or lithium-aluminum alloy (Li / Al). The second electrode layer 70 can be continuous (uninterrupted) at the spacer 41. Specifically, the continuous configuration of the second electrode layer 70 reduces its resistance, facilitates current transfer within the second electrode layer, improves the response of the display panel 100, and thereby enhances the display quality of the display panel 100.

[0044] Specifically, the maximum depth of the groove 411 is greater than or equal to the sum of the thicknesses of the first light-emitting sublayer 61 and the charge generation layer 62. In the light-emitting layer 60, at least the first light-emitting sublayer 61 and the charge generation layer 62 are disconnected at the spacer 41. This arrangement cuts off the lateral conduction path of the current in the charge generation layer 62, thereby improving the crosstalk problem between pixels caused by lateral leakage current in the display panel 100, thereby alleviating the problem of pixel stealing and enhancing the display quality of the display panel 100.

[0045] The maximum depth of the groove 411 can be less than or equal to the thickness of the light-emitting layer 60. With this arrangement, after the light-emitting layer 60 is formed, the step difference at the spacer 41 on the surface of the light-emitting layer 60 away from the array substrate 10 does not interrupt the subsequently formed second electrode layer 70, thereby ensuring the continuity of the subsequently formed second electrode layer 70 and improving the display effect of the display panel 100.

[0046] Continuing with Figure 1 , the display panel 100 further includes an encapsulation layer 80 disposed on a surface of the second electrode layer 70 distal from the array substrate 10 to prevent external moisture from penetrating into the display panel 100. The encapsulation layer 80 may include alternating organic and inorganic layers. The organic layer may be made of, for example, polyethylene terephthalate, polyimide, polycarbonate (PC), epoxy resin, polyethylene (PE), or polyacrylate (PA). The inorganic layer may be made of, for example, silicon nitride, aluminum oxide, silicon oxide, or titanium oxide.

[0047] 3 , the array substrate 10 may include a base 11 and a buffer layer 12 , an active layer 13 , a first insulating layer 14 , a first metal layer 15 , a second insulating layer 16 , a second metal layer 17 , a third insulating layer 18 , and a third metal layer 19 sequentially disposed on the base 11 .

[0048] Substrate 11 is used to support the various layers of structure disposed thereon. Substrate 11 can be a rigid substrate such as a glass substrate, or a flexible substrate. Flexible substrate materials include, but are not limited to, polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), and polyetherimide (PEI). Substrate 11 can include a multi-layered structure. Specifically, substrate 11 can include a first flexible substrate, an intermediate layer, and a second flexible substrate stacked in sequence. The first and second flexible substrates can be formed of polyimide, and the intermediate layer can be formed of an inorganic material such as silicon nitride or silicon oxide.

[0049] The buffer layer 12 is provided on the substrate 11 to prevent impurities and water vapor from penetrating from the substrate 11 and to provide a flat surface for the film layer formed subsequently. The buffer layer 12 includes inorganic insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride. In order to further enhance the effect of blocking impurities, water vapor, and flattening, a barrier layer may be provided between the buffer layer 12 and the substrate 11. The buffer layer 12 includes inorganic insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride. Specifically, the barrier layer may include a plurality of sub-layer structures, wherein the sub-layer close to the substrate 11 is formed of silicon oxide to enhance the bonding performance between the barrier layer and the substrate 11, and the sub-layer close to the buffer layer 12 is formed of silicon nitride to enhance the bonding performance between the barrier layer and the buffer layer 12.

[0050] The active layer 13 is disposed on the buffer layer 12. The material of the active layer 13 can be a metal oxide semiconductor such as polycrystalline silicon (P-Si) or indium gallium zinc oxide (IGZO). To reduce the impact of light on the active layer 13, a light shielding layer can be disposed above or below the buffer layer 12. The light shielding layer and the vertical projection of the active layer 13 on the array substrate 10 overlap, thereby reducing light exposure to the active layer 13 and ensuring the performance stability of the array substrate 10.

[0051] The first insulating layer 14 is disposed on the active layer 13 . The material of the first insulating layer 14 may be silicon nitride, silicon oxide, or a stacked structure of silicon nitride and silicon oxide.

[0052] The first metal layer 15 is disposed on the first insulating layer 14 and can be patterned to form a first gate. The material of the first metal layer 15 may include molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), or alloys thereof. The first metal layer 15 may include a single-layer or multi-layer metal structure.

[0053] The second insulating layer 16 is disposed on the first metal layer 15 . The material of the second insulating layer 16 may be silicon nitride, silicon oxide, or a stacked structure of silicon nitride and silicon oxide.

[0054] A second metal layer 17 is disposed on the second insulating layer 16 and can be patterned to form a second gate. Specifically, the second metal layer 17 is disposed opposite the first metal layer 15, forming a dual-gate structure. The material of the second metal layer 17 may include molybdenum, aluminum, platinum, palladium, silver, magnesium, gold, nickel, neodymium, iridium, chromium, titanium, tantalum, tungsten, copper, or alloys thereof. The second metal layer 17 may comprise a single layer or a multilayer metal structure.

[0055] The third insulating layer 18 is disposed on the second metal layer 17 . The material of the third insulating layer 18 may be silicon nitride, silicon oxide, or a stacked structure of silicon nitride and silicon oxide.

[0056] The third metal layer 19 is disposed on the third insulating layer 18 and can be patterned to form a source metal layer and a drain metal layer spaced apart. Specifically, the third metal layer 19 is connected to the active layer 13 via a through hole, thereby forming a thin film transistor together with the first metal layer 15, the second metal layer 17, and the third metal layer 19 and the active layer 13. The material of the third metal layer 19 can include molybdenum, aluminum, platinum, palladium, silver, magnesium, gold, nickel, neodymium, iridium, chromium, titanium, tantalum, tungsten, copper, or alloys thereof. The third metal layer 19 can include a single layer or a multilayer metal structure.

[0057] Continuing with Figure 3 , the planarization layer 20 disposed on the array substrate 10 may include a first planarization layer 21 and a second planarization layer 22 to further enhance surface flatness and provide a smoother surface for the subsequently formed first electrode layer 30. When the planarization layer 20 comprises a multi-layer structure, a contact metal layer CM may be further disposed between the first electrode 31 and the third metal layer 19 . The first electrode 31 is connected to the contact metal layer CM, which in turn is connected to the third metal layer 19 . This facilitates wiring connections between the multi-layer film structures.

[0058] Referring to Figure 4 , the spacer layer 40 includes a first spacer sublayer 42 and a second spacer sublayer 43. The first spacer sublayer 41 is disposed on a surface of the second spacer sublayer 43 away from the planar layer 20. The first spacer sublayer 42 includes a plurality of third openings 421 corresponding to the spacers 41, and the second spacer sublayer 43 includes a plurality of fourth openings 431 corresponding to the spacers 41. The third openings 421 and the fourth openings 431 are connected, and the opening size of the fourth openings 431 near the end of the first spacer sublayer 42 is smaller than the opening size of the third openings 421. This arrangement allows the first spacer sublayer 42 to have a protrusion 412 extending toward the center of the groove 411. This can block the deposition of the light-emitting layer 60 during the subsequent formation of the light-emitting layer 60, thereby enhancing the spacing effect of the spacer 41 on the light-emitting layer 60.

[0059] The recess 411 may include a third opening 421 and a fourth opening 431, and the etching rate of the first spacer sublayer 42 may be lower than the etching rate of the second spacer sublayer 43. This configuration allows for a single etching process, and allows more material of the second spacer sublayer 43 to be removed than material of the first spacer sublayer 42 in the same etching process. This facilitates the formation of the protrusion 412 extending toward the center of the recess 411, simplifies the process for forming the spacer layer 40, and reduces the process difficulty.

[0060] Specifically, the material of the first spacer sublayer 42 can be silicon nitride, and the material of the second spacer sublayer 43 can be silicon oxide. Since the etching rate of silicon nitride is lower than that of silicon oxide, the third opening 421 and the fourth opening 431 can be formed by wet etching. The third opening 421 and the fourth opening 431 are connected to form the groove 411. By utilizing the isotropy of the wet etching process, more material of the second spacer sublayer 43 is etched away than that of the first spacer sublayer 42 in a single etching process, ultimately forming a protrusion 412 extending toward the center of the groove 411. This greatly simplifies the process of forming the spacer layer 40 and reduces the process difficulty. In addition, the etching uniformity of inorganic materials such as silicon nitride and silicon oxide is significantly better than that of organic materials. The materials of the first spacer sublayer 42 and the second spacer sublayer 43 are selected from silicon nitride and silicon oxide, respectively, so that the spacer layer 40 has a more detailed and uniform spacing morphology, thereby further improving the isolation effect of the spacer layer 40 on the light-emitting layer 60 and the overall reliability of the display panel 100. The thickness of the second spacer sublayer 43 can be adjusted according to the specific thickness of the light-emitting layer 60 , so that the light-emitting layer 60 can be disconnected at the spacer 41 . The specific thickness of the second spacer sublayer 43 can be 0.05 μm to 0.4 μm.

[0061] The angle formed between the line connecting the two end points of the sidewall of the third opening 421 of the first spacer sublayer 42 and the surface of the first spacer sublayer 42 close to the array substrate 10 is a first angle a. The angle formed between the line connecting the two end points of the sidewall of the fourth opening 431 of the second spacer sublayer 43 and the surface of the second spacer sublayer 43 close to the array substrate 10 is a second angle b. The first angle a can be greater than the second angle b. This arrangement further enhances the spacing effect of the first spacer sublayer 42 on the light-emitting layer 60, thereby further enhancing the lateral current blocking effect of the spacer layer 40.

[0062] The spacer layer 40 may also include a third spacer sublayer 44, which is disposed between the second spacer sublayer 43 and the planar layer 20. The third spacer sublayer 44 includes a plurality of sub-grooves 441 corresponding to the spacer portion 41, with the openings of the sub-grooves 441 facing the second spacer sublayer 43 and communicating with the corresponding fourth opening 431. The groove 411 includes a third opening 421, a fourth opening 431, and sub-grooves 441. The provision of the third spacer sublayer 44 can reduce the adverse effects of over-etching on the flatness of the planar layer 20, thereby improving the flatness of the subsequently formed film layer and enhancing the reliability and display effect of the display panel 100. At the same time, the blocking effect of the third spacer sublayer 44 also increases the adjustment range of the etching time, thereby making it easier to adjust the depth of the lateral etching of the first spacer sublayer 42 and the second spacer sublayer 43, thereby ensuring the spacing effect of the spacer layer 40 on the light-emitting layer 60.

[0063] The sidewalls of the fourth opening 431 of the second spacer sub-layer 43 may include a first curved surface 432, and the sub-groove 441 of the third spacer sub-layer 44 may include a second curved surface 442. The radius of curvature of the second curved surface 442 is greater than the radius of curvature of the first curved surface 432. This configuration can provide a smaller step difference at the third spacer sub-layer 44. Therefore, after the light-emitting layer 60 is formed, the step difference at the spacer 41 on the surface of the light-emitting layer 60 away from the array substrate 10 is further reduced. This facilitates the continuity of the subsequently formed second electrode layer 70 at the spacer 41, thereby improving the display effect of the display panel 100.

[0064] The second curved surface 442 can be continuous with the adjacent first curved surface 432. This configuration can minimize the step difference between the third spacer sublayer 44 and the second spacer sublayer 43. Therefore, after the light-emitting layer 60 is formed, the step difference at the spacer 41 on the surface of the light-emitting layer 60 away from the array substrate 10 is further reduced, thereby facilitating the continuity of the subsequently formed second electrode layer 70 at the spacer 41, thereby improving the display effect of the display panel 100.

[0065] The etching rate of the third spacer sublayer 44 can be lower than that of the second spacer sublayer 43. This configuration allows for a single etching process, with less material of the third spacer sublayer 44 removed in the same etching process than that of the second spacer sublayer 43. This simplifies the process and reduces complexity. It also facilitates making the radius of curvature of the second curved surface 442 greater than that of the first curved surface 432, thereby reducing the step difference at the spacer 41 on the surface of the light-emitting layer 60 facing away from the array substrate 10. Furthermore, the third spacer sublayer 44, with its lower etching rate, is more suitable as an etch stop, further reducing the adverse effects of overetching on the flatness of the planar layer 20. Specifically, the second spacer sublayer 43 can be made of silicon oxide, and the third spacer sublayer 44 can be made of silicon nitride or silicon oxynitride. The thickness of the third spacer sublayer 44 can be greater than 3 nanometers. To further improve film uniformity, the thickness of the third spacer sublayer 44 is preferably greater than 20 nanometers.

[0066] The angle formed between the line connecting the two end points of the sidewall of the third opening 421 of the first spacer sublayer 42 and the surface of the first spacer sublayer 42 near the array substrate 10 is a first angle a. The angle formed between the line connecting the two end points of the sidewall of the fourth opening 431 of the second spacer sublayer 43 and the surface of the second spacer sublayer 43 near the array substrate 10 is a second angle b. The angle formed between the line connecting the two end points of the sidewall of the sub-recess 441 of the third spacer sublayer 44 and the surface of the third spacer sublayer 44 near the array substrate 10 is a third angle c. The first angle a can be greater than the second angle b, and the second angle b is greater than the third angle c. This configuration further enhances the spacing effect of the first spacer sublayer 42 on the subsequently formed light-emitting layer 60, thereby further enhancing the spacer layer 40's ability to block lateral current in the light-emitting layer 60.

[0067] The distance between the edge of the protrusion 412 of the first spacer sublayer 42, which faces the center of the groove 411, and the edge of the fourth opening 431 near one end of the first spacer sublayer 42 can be greater than or equal to 1 micron. This arrangement can reduce the impact of process precision errors. Even if the specific position of the groove 411 shifts slightly due to process precision errors, it will not affect the formation of the protrusion 412, thereby further ensuring the spacing effect of the spacer 41. To balance the spacing effect and the thinness of the display panel 100, the thickness of the first spacer sublayer 42 can be 0.01 micron to 0.1 micron.

[0068] The spacer 41 may surround the corresponding first electrode 31. Referring to FIG5 , the display panel 100 includes a first sub-pixel A1, a second sub-pixel A2, and a third sub-pixel A3. The first sub-pixel A1, the second sub-pixel A2, and the third sub-pixel A3 are disposed in the first opening 51. The first sub-pixel A1, the second sub-pixel A2, and the third sub-pixel A3 include a first electrode 31, a light-emitting layer 60, and a second electrode layer 70 that are sequentially stacked. In other words, the spacer 41 may be disposed around the first sub-pixel A1, the second sub-pixel A2, or the third sub-pixel A3. With such an arrangement, the spacer 41 may isolate the lateral current in the charge generation layer between a sub-pixel of the display panel and other adjacent sub-pixels, thereby improving the crosstalk problem between the sub-pixels, thereby improving the problem of sub-pixels being too bright during display, and enhancing the display quality of the display panel 100. The spacer 41 is disposed in accordance with the specific pixel arrangement structure, ensuring that the spacer 41 is disposed around the sub-pixels. Specifically, the spacer 41 can be completely surrounded by the circumference of the first electrode 31, that is, the spacer 41 arranged on the circumference of the first electrode 31 is continuously arranged; the spacer 41 can also be partially surrounded by the circumference of the first electrode 31, that is, the spacer 41 arranged on the circumference of the first electrode 31 is intermittently arranged with gaps.

[0069] Referring to Figures 6 and 7 , a second cross-sectional schematic diagram of the display panel 100 provided in an embodiment of the present application differs from the cross-sectional schematic diagram of the display panel 100 shown in Figure 1 in that two second openings 52 are provided between two adjacent first openings 51, two spacers 41 are provided between two adjacent first electrodes 31, and a second opening 52 communicates with a groove 411 of a corresponding spacer 41. The provision of multiple spacers 41 between two adjacent first electrodes 31 further enhances the spacing effect of the spacer layer 40 on the light-emitting layer 60, thereby further improving the spacer layer 40's ability to block lateral current in the light-emitting layer 60.

[0070] The display panel 100 provided in the above embodiment can be applied to various display devices to improve their display quality, including but not limited to smart watches, mobile phones, tablet computers, and laptop computers.

[0071] Referring to FIG. 8 , an embodiment of the present application further provides a method for manufacturing a display panel, comprising the following steps:

[0072] S1: forming a planar layer on the array substrate.

[0073] Specifically, the material of the planar layer may be an organic material with a low dielectric constant, such as polyimide. In order to provide a smoother surface for the subsequently formed film layer, the planar layer may include a first planar layer and a second planar layer.

[0074] S2: forming a first electrode layer on a surface of the planar layer away from the array substrate, wherein the first electrode layer includes a plurality of first electrodes arranged at intervals.

[0075] The material of the first electrode can be selected from, for example, gold, platinum, titanium, silver, indium tin oxide, zinc tin oxide, or a transparent conductive polymer (such as polyaniline). Specifically, a layer of the first electrode material can be formed on the flat layer, and then patterned to form a plurality of first electrodes spaced apart.

[0076] S3: forming an inorganic layer between two adjacent first electrodes.

[0077] Specifically, a layer of inorganic layer material may be deposited on the planar layer by using a chemical vapor deposition (CVD) process, and then the inorganic layer disposed between adjacent first electrodes may be formed by a patterning process.

[0078] S4: forming a pixel definition layer on the planar layer, the first electrode, and a surface of the inorganic layer away from the array substrate.

[0079] The material of the pixel definition layer can be hexamethyldisiloxane, epoxy resin or polyimide, or other silicone adhesive materials with a transmittance of more than 90%, or other organic adhesive materials with a transmittance greater than 80% and slightly higher bending strength.

[0080] S5: forming a first opening and a second opening on a surface of the pixel definition layer away from the planar layer, wherein the first opening exposes at least a portion of the corresponding first electrode, and the second opening exposes at least a portion of the corresponding inorganic layer.

[0081] Specifically, a half tone mask (HTM) process can be used to open a first opening in the pixel definition layer at the position of the first electrode to expose at least a portion of the corresponding first electrode; and open a second opening in the pixel definition layer at the position of the inorganic layer to expose at least a portion of the corresponding inorganic layer.

[0082] S6: forming a spacer layer in the inorganic layer exposed by the second opening, wherein the spacer layer includes a plurality of spacers arranged between two adjacent first electrodes, and the spacers include a groove with an opening direction away from the array substrate and a protrusion extending toward the center of the groove.

[0083] The spacer layer may include a first spacer sublayer, a second spacer sublayer, and a third spacer sublayer stacked in sequence. Correspondingly, the inorganic layer includes a first inorganic layer, a second inorganic layer, and a third inorganic layer stacked in sequence, and the first spacer sublayer, the second spacer sublayer, and the third spacer sublayer are respectively formed by a patterning process of the first inorganic layer, the second inorganic layer, and the third inorganic layer. The first spacer sublayer has a protrusion relative to the second spacer sublayer in the direction toward the center of the groove. When the light-emitting layer is subsequently formed, due to the obstruction of the protrusion, the light-emitting layer will not be deposited in the area of ​​the vertical projection of the array substrate where the protrusion falls into the groove, thereby facilitating the disconnection of the light-emitting layer at the spacer layer. The conduction of the lateral current in the light-emitting layer, especially the charge generation layer, is blocked at the spacer layer, thereby improving the crosstalk problem between pixels caused by the lateral leakage current.

[0084] Specifically, the etching rate of the first inorganic layer can be lower than the etching rate of the second inorganic layer. For example, the material of the first inorganic layer is silicon nitride, and the material of the second inorganic layer is silicon oxide. Therefore, the first and second inorganic layers can be etched by wet etching to form the groove. The isotropy of the wet etching process is utilized to remove more material of the second inorganic layer than that of the first inorganic layer in the same etching process, ultimately forming a protrusion of the first spacer sublayer relative to the second spacer sublayer in the direction toward the center of the groove, thereby simplifying the spacer layer formation process and reducing the process difficulty.

[0085] The third spacer sublayer is arranged between the second spacer sublayer and the flat layer. The etching rate of the third spacer sublayer can be lower than the etching rate of the second spacer sublayer. For example, the material of the second spacer sublayer is silicon oxide, and the material of the third spacer sublayer is silicon nitride or silicon oxynitride. The third spacer sublayer acts as an etching barrier layer to reduce the adverse effects of over-etching on the flatness of the flat layer when etching the first inorganic layer and the second inorganic layer. Therefore, the provision of the third spacer sublayer can improve the flatness of the subsequently formed film layer, and improve the reliability and display effect of the display panel. At the same time, the blocking of the third spacer sublayer also increases the adjustment range of the etching time, which is more conducive to adjusting the depth of lateral etching for the first spacer sublayer and the second spacer sublayer, and ensuring the spacing effect of the spacer layer on the light-emitting layer.

[0086] S7: A light-emitting layer is formed on a surface of the flat layer, the first electrode layer, and the spacer layer away from the array substrate, wherein the light-emitting layer includes a first light-emitting sublayer, a charge generating layer, and a second light-emitting sublayer stacked in sequence, wherein the sum of the thicknesses of the first light-emitting sublayer and the charge generating layer is less than or equal to the maximum depth of the groove of the spacer layer, and in the light-emitting layer, at least the first light-emitting sublayer and the charge generating layer are disconnected at the spacer layer.

[0087] Specifically, the first and second luminescent sublayers may include layers such as an electron injection layer, an electron transport layer, an organic light-emitting material layer, a hole transport layer, and a hole injection layer. The charge generation layer may be formed by open mask evaporation and is disposed between the first and second luminescent sublayers to connect the first and second luminescent sublayers, forming a tandem OLED device to achieve the effect of reducing power consumption and improving brightness. Specifically, the charge generation layer comprises an organic material with a high carrier transport rate and is doped with an active metal such as lithium or ytterbium, thereby having strong electrical conductivity, enabling efficient conduction between multiple stacked organic light-emitting layers, but also easily generating lateral conduction current. Since the sum of the thicknesses of the first luminescent sublayer and the charge generation layer is less than or equal to the maximum depth of the groove of the spacer layer, in the luminescent layer, at least the first luminescent sublayer and the charge generation layer are disconnected at the spacer layer, cutting off the conduction path of the lateral leakage current, thereby improving the crosstalk problem between pixels caused by the lateral leakage current, improving the pixel stealing problem, and improving the display quality of the display panel.

[0088] S8: forming a second electrode layer on a surface of the light emitting layer away from the array substrate.

[0089] The second electrode layer can be made of a material with a low work function to facilitate electron injection, such as silver (Ag), aluminum (Al), lithium (Li), magnesium (Mg), ytterbium (Yb), calcium (Ca), indium (In), or alloys of the aforementioned metals, such as magnesium-silver alloy (Mg / Ag) and lithium-aluminum alloy (Li / Al). The second electrode layer can be continuous (or uninterrupted) at the gaps to reduce its resistance, facilitate current transfer within the second electrode layer, improve the display panel's response, and ultimately enhance the display quality.

[0090] The display panel provided in the embodiments of the present application is introduced in detail above. The description of the above embodiments is only used to help understand the method and core concept of the present application, and should not be understood as limiting the scope of protection of the present application.

Claims

1. A display panel, characterized in that: The display panel comprises: An array substrate; a planar layer, wherein the planar layer is disposed on the array substrate; A first electrode layer is disposed on a surface of the planar layer away from the array substrate, the first electrode layer comprising a plurality of first electrodes disposed at intervals; a spacer layer, arranged on a surface of the flat layer away from the array substrate, the spacer layer comprising a plurality of spacers arranged between two adjacent first electrodes, the spacers comprising a groove with an opening direction away from the array substrate and a protrusion extending toward the center of the groove; A pixel definition layer is provided on a surface of the first electrode layer and the spacer layer away from the array substrate, and a first opening and a second opening are provided on a surface of the pixel definition layer away from the planar layer, wherein the first opening exposes at least a portion of the corresponding first electrode, and the second opening is connected to the corresponding groove; A light-emitting layer is arranged on a surface of the pixel definition layer away from the array substrate, and the light-emitting layer includes a first light-emitting sublayer, a charge generation layer and a second light-emitting sublayer which are stacked in sequence; A second electrode layer is disposed on a surface of the light emitting layer away from the array substrate; The maximum depth of the groove is greater than or equal to the sum of the thicknesses of the first light-emitting sublayer and the charge generation layer, and in the light-emitting layer, at least the first light-emitting sublayer and the charge generation layer are disconnected at the spacing portion.

2. The display panel according to claim 1, characterized in that: The maximum depth of the groove is less than or equal to the thickness of the light emitting layer.

3. The display panel according to claim 2, characterized in that: The second electrode layer is not disconnected at the spacing portion.

4. The display panel according to claim 1, characterized in that: The spacing layer includes a first spacing sublayer and a second spacing sublayer, the first spacing sublayer is arranged on a surface of the second spacing sublayer away from the flat layer, the first spacing sublayer includes a plurality of third openings arranged corresponding to the spacing parts, the second spacing sublayer includes a plurality of fourth openings arranged corresponding to the spacing parts, the groove includes the third opening and the fourth opening, and the third opening is connected to the fourth opening.

5. The display panel according to claim 4, characterized in that: The thickness of the second spacer sublayer is 0.05 micrometer to 0.4 micrometer.

6. The display panel according to claim 4, characterized in that: An opening size of the fourth opening close to one end of the first spacer sublayer is smaller than an opening size of the third opening.

7. The display panel according to claim 4, characterized in that: An etching rate of the first spacer sublayer is lower than an etching rate of the second spacer sublayer.

8. The display panel according to claim 4, characterized in that: An angle between a line connecting the two end points of the side wall of the third opening of the first spacer sublayer and a surface of the first spacer sublayer close to the array substrate is a first angle, and an angle between a line connecting the two end points of the side wall of the fourth opening of the second spacer sublayer and a surface of the second spacer sublayer close to the array substrate is a second angle, and the first angle is greater than the second angle.

9. The display panel according to claim 4, characterized in that: The spacer layer further includes a third spacer sublayer, and the third spacer sublayer is disposed between the second spacer sublayer and the planar layer; The third spacer sub-layer includes a plurality of sub-grooves arranged corresponding to the spacer portions, the groove includes the sub-grooves, and the openings of the sub-grooves are arranged toward the second spacer sub-layer and communicate with the corresponding fourth openings.

10. The display panel according to claim 9, characterized in that: The sidewall of the fourth opening of the second spacer sub-layer includes a first curved surface, and the sub-groove of the third spacer sub-layer includes a second curved surface, and a curvature radius of the second curved surface is greater than a curvature radius of the first curved surface.

11. The display panel according to claim 10, characterized in that: The second arc surface is continuous with the first arc surface adjacent to the second arc surface.

12. The display panel according to claim 9, characterized in that: An etching rate of the third spacer sublayer is lower than an etching rate of the second spacer sublayer.

13. The display panel according to claim 9, characterized in that: The angle between the line connecting the two end points of the side wall of the third opening of the first spacer sublayer and a surface of the first spacer sublayer close to the array substrate is a first angle, the angle between the line connecting the two end points of the side wall of the fourth opening of the second spacer sublayer and a surface of the second spacer sublayer close to the array substrate is a second angle, the angle between the line connecting the two end points of the side wall of the sub-groove of the third spacer sublayer and a surface of the third spacer sublayer close to the array substrate is a third angle, the first angle is greater than the second angle, and the second angle is greater than the third angle.

14. The display panel according to claim 9, characterized in that: The thickness of the third spacer sublayer is greater than 3 nanometers.

15. The display panel according to claim 4, characterized in that: A distance between an edge of the protrusion of the first spacer sublayer facing the center of the groove and an edge of the fourth opening close to one end of the first spacer sublayer is greater than or equal to 1 micrometer.

16. The display panel according to claim 4, characterized in that: The thickness of the first spacer sublayer is in the range of 0.01 micrometer to 0.1 micrometer.

17. The display panel according to claim 1, characterized in that: The spacer surrounds the corresponding first electrode.

18. The display panel according to claim 17, characterized in that: The partition part entirely surrounds the circumference of the first electrode.

19. The display panel according to claim 17, characterized in that: The spacer partially surrounds the circumference of the first electrode.

20. The display panel according to claim 1, characterized in that: Two second openings are arranged between two adjacent first openings, two spacers are arranged between two adjacent first electrodes, and one of the second openings is communicated with the groove of a corresponding one of the spacers.

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