Drive circuit, drive method, drive module, and display apparatus

Abstract

A drive circuit, a drive method, a drive module, and a display apparatus. The drive circuit comprises a first output circuit (11), a second output circuit (12) and a first output node control circuit (13), wherein under the control of the electric potential of a first output node NO1, the first output circuit (11) controls the connection or disconnection between a drive signal output end GT and a first voltage end V1; under the control of the electric potential of a second output node NO2, the second output circuit (12) controls the connection or disconnection between the drive signal output end GT and an output signal end S1; and under the control of a first output control signal, the first output node control circuit (13) controls the connection or disconnection between the first output node NO1 and a second voltage end V2. The present drive circuit can control a drive signal output end to output a drive signal normally within a holding time period, and can thus reduce the power consumption.

Description

Driving circuit, driving method, driving module and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving circuit, a driving method, a driving module, and a display device. Background Art

[0002] When the relevant display products are working and performing low-frequency display, the display cycle includes a refresh frame and a hold frame. In the hold frame, when the clock signal and input signal are stopped, the drive signal output from the drive signal output end will have steps and the output will be abnormal.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a driving circuit, comprising a first output circuit, a second output circuit, and a first output node control circuit;

[0005] The control terminal of the first output circuit is electrically connected to the first output node. The first output circuit is also electrically connected to the first voltage terminal and the drive signal output terminal, respectively, and is used to control the connection or disconnection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first output node;

[0006] The control terminal of the second output circuit is electrically connected to the second output node. The second output circuit is also electrically connected to the output signal terminal and the drive signal output terminal, respectively, and is used to control the connection or disconnection between the drive signal output terminal and the output signal terminal under the control of the potential of the second output node;

[0007] The first output node control circuit is electrically connected to the first output control terminal, the second voltage terminal and the first output node respectively, and is used to control the connection or disconnection between the first output node and the second voltage terminal under the control of a first output control signal provided by the first output control terminal.

[0008] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a second output node control circuit;

[0009] The second output node control circuit is electrically connected to the second output control terminal, the third voltage terminal and the second output node respectively, and is used to control the connection or disconnection between the second output node and the third voltage terminal under the control of a second output control signal provided by the second output control terminal.

[0010] Optionally, the first output node control circuit includes a first transistor;

[0011] The gate of the first transistor is electrically connected to the first output control terminal, the first electrode of the first transistor is electrically connected to the second voltage terminal, and the second electrode of the first transistor is electrically connected to the first output node.

[0012] Optionally, the second output node control circuit includes a second transistor;

[0013] The gate of the second transistor is electrically connected to the second output control terminal, the first electrode of the second transistor is electrically connected to the third voltage terminal, and the second electrode of the second transistor is electrically connected to the second output node.

[0014] Optionally, the first output control terminal and the second output control terminal are the same output control terminal; or,

[0015] The first output control end and the second output control end are different output control ends.

[0016] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a second node control circuit and an on-off control circuit;

[0017] The second node control circuit is electrically connected to the second node and is used to control the potential of the second node;

[0018] The on-off control circuit is electrically connected to the fourth voltage terminal, the second node and the second output node respectively, and is used to control the connection or disconnection between the second node and the second output node under the control of a fourth voltage signal provided by the fourth voltage terminal.

[0019] Optionally, the on-off control circuit includes an on-off control transistor;

[0020] The gate of the on-off control transistor is electrically connected to the fourth voltage terminal, the first electrode of the on-off control transistor is electrically connected to the second node, and the second electrode of the on-off control transistor is electrically connected to the second output node;

[0021] The on-off control transistor is an n-type transistor, and the fourth voltage terminal is a high voltage terminal; or, the on-off control transistor is a p-type transistor, and the fourth voltage terminal is a low voltage terminal.

[0022] Optionally, the driving circuit further includes a first on-off control circuit;

[0023] The first output node is electrically connected to the control terminal of the first output circuit through a first on-off control circuit;

[0024] The first on-off control circuit is used to control the connection between the first output node and the control terminal of the first output circuit during at least a part of the holding time period included in the display cycle.

[0025] Optionally, the driving circuit further includes a second on-off control circuit;

[0026] The second output node is electrically connected to the control terminal of the second output circuit through a second on-off control circuit;

[0027] The second on-off control circuit is used to control the connection between the second output node and the control terminal of the second output circuit during at least a part of the holding time period included in the display cycle.

[0028] Optionally, the second node control circuit is electrically connected to the first clock signal terminal and the first input terminal respectively, and is used to control the connection or disconnection between the second node and the first input terminal under the control of the first clock signal provided by the first clock signal terminal.

[0029] Optionally, the second node control circuit is also electrically connected to the first output node, the first voltage terminal and the second clock signal terminal, respectively, and is used to control the connection between the second node and the first voltage terminal under the control of the potential of the first output node and the second clock signal provided by the second clock signal terminal.

[0030] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a first output control circuit;

[0031] The first output control circuit is electrically connected to the first clock signal terminal, the fifth voltage terminal, the first output node, the second clock signal terminal and the first voltage terminal, respectively, and is used to control the connection between the first output node and the fifth voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the connection between the first output node and the first voltage terminal under the control of the second clock signal provided by the second clock signal terminal.

[0032] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a first output control circuit;

[0033] The first output control circuit is electrically connected to the first clock signal terminal, the fifth voltage terminal, the first output node and the second node, respectively, and is used to control the connection between the first output node and the fifth voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and write the first clock signal into the first output node under the control of the potential of the second node.

[0034] Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes a first energy storage circuit and a second energy storage circuit;

[0035] The first energy storage circuit is electrically connected to the first output node and the first voltage terminal respectively, and is used to store electrical energy;

[0036] The second energy storage circuit is electrically connected to the second output node and the driving signal output terminal respectively, and is used for storing electric energy.

[0037] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a first control circuit;

[0038] The first control circuit includes a third node control circuit, a fourth node control circuit and a first node control circuit;

[0039] The third node control circuit is electrically connected to the third node, the third clock signal terminal, the fifth voltage terminal, and the second output node, respectively, and is configured to control communication between the third node and the fifth voltage terminal under the control of a third clock signal provided by the third clock signal terminal, write the third clock signal into the third node under the control of the potential of the second output node, and maintain the potential of the third node;

[0040] The fourth node control circuit is electrically connected to the third node, the fourth clock signal terminal and the fourth node respectively, and is configured to write the fourth clock signal provided by the fourth clock signal terminal into the fourth node under the control of the potential of the third node;

[0041] The first node control circuit is electrically connected to the fourth clock signal terminal, the fourth node, the first output node, the second output node and the first voltage terminal, respectively, and is used to control the connection between the fourth node and the first output node under the control of the fourth clock signal, and to control the connection between the first output node and the first voltage terminal under the control of the potential of the second output node.

[0042] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a second output control circuit;

[0043] The second output control circuit is electrically connected to the second output node, the third clock signal terminal and the second input terminal respectively, and is used to control the connection between the second output node and the second input terminal under the control of the third clock signal provided by the third clock signal terminal.

[0044] In a second aspect, an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned driving circuit, wherein a display period includes a refresh period and a hold period; the driving method includes:

[0045] During a refresh period, the first output node control circuit controls the first output node to be disconnected from the second voltage terminal under the control of a first output control signal provided by the first output control terminal;

[0046] During at least part of the holding time period, the first output node control circuit controls the connection between the first output node and the second voltage terminal under the control of the first output control signal provided by the first output control terminal, so that the first output circuit controls the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first output node.

[0047] Optionally, the driving circuit further includes a second output node control circuit; and the driving method includes:

[0048] During a refresh period, the second output node control circuit controls the second output node to be disconnected from the third voltage terminal under the control of a second output control signal provided by the second output control terminal;

[0049] During at least part of the holding time period, the second output node control circuit, under the control of a second output control signal provided by the second output control terminal, controls the connection between the second output node and the third voltage terminal, so that the second output circuit, under the control of the potential of the second output node, controls the disconnection between the drive signal output terminal and the output signal terminal.

[0050] Optionally, the driving circuit further includes a first output control circuit; the first output control circuit is electrically connected to the first clock signal terminal, and the driving circuit further includes a second node control circuit and an on-off control circuit; the second node control circuit is electrically connected to the first clock signal terminal, and the output signal terminal is a second clock signal terminal;

[0051] The frequency of the first clock signal provided by the first clock signal terminal and the frequency of the second clock signal provided by the second clock signal terminal are equal to the frequency of the data voltage provided to the data line during the display period.

[0052] Optionally, the first output control end and the second output control end are different output ends;

[0053] During the holding time period, the first output node control circuit controls the time for the first output node and the second voltage terminal to be connected to each other for a first time, and the second output node control circuit controls the time for the second output node and the third voltage terminal to be connected to each other for a second time, and the first time is greater than the second time.

[0054] Optionally, the first output control signal is a square wave signal, and the second output control signal is a square wave signal;

[0055] The frequency of the first output control signal is greater than the display refresh frequency, and the frequency of the second output control signal is greater than the display refresh frequency.

[0056] Optionally, during the refresh time period, the first output control signal is a first control voltage signal, and the second output control signal is a second control voltage signal;

[0057] During the holding period, the first output control signal is a third control voltage signal, and the second output control signal is a fourth control voltage signal;

[0058] The first control voltage signal is different from the third control voltage signal, and the second control voltage signal is different from the fourth control voltage signal.

[0059] Optionally, the first control voltage signal, the second control voltage signal, the third control voltage signal and the fourth control voltage signal are all DC voltage signals.

[0060] Optionally, the first control voltage signal is a DC voltage signal, and the second control voltage signal is a square wave voltage signal;

[0061] The third control voltage signal is a DC voltage signal, and the fourth DC voltage signal is a square wave voltage signal.

[0062] Optionally, the driving method described in at least one embodiment of the present disclosure further includes:

[0063] During the holding period, supply of clock signals to the clock signal terminals is stopped, and supply of input signals to the input terminals is stopped.

[0064] In a third aspect, an embodiment of the present disclosure provides a driving module comprising multiple levels of the above-mentioned driving circuits.

[0065] In a fourth aspect, embodiments of the present disclosure provide a driving method, applied to the aforementioned driving module, wherein the driving module includes an odd-stage driving circuit and an even-stage driving circuit; the driving circuit includes a first output node control circuit and a second output node control circuit; the display period includes a hold period; and the driving method includes:

[0066] During the holding period, supplying clock signals and input signals to the odd-numbered stage driving circuits is stopped;

[0067] During at least part of the time included in the holding period, in the odd-numbered stage driving circuit, the first output node control circuit controls the first output node to be connected to the second voltage terminal, so that the first output circuit controls the driving signal output terminal to be connected to the first voltage terminal; and the second output node control circuit controls the second output node to be connected to the third voltage terminal, so that the second output circuit controls the driving signal output terminal to be disconnected from the output signal terminal under the control of the potential of the second output node;

[0068] During the holding period, the clock signal and the input signal are normally supplied to the even-numbered stage driving circuits.

[0069] In a fifth aspect, embodiments of the present disclosure provide a driving method, applied to the aforementioned driving module, wherein the driving module includes an odd-stage driving circuit and an even-stage driving circuit; the driving circuit includes a first output node control circuit and a second output node control circuit; the display period includes a hold period; and the driving method includes:

[0070] During the holding period, supplying clock signals and input signals to the even-numbered stage driving circuits is stopped;

[0071] During at least part of the time included in the holding period, in the even-numbered stage driving circuit, the first output node control circuit controls the first output node to be connected to the second voltage terminal, so that the first output circuit controls the driving signal output terminal to be connected to the first voltage terminal; and the second output node control circuit controls the second output node to be connected to the third voltage terminal, so that the second output circuit controls the driving signal output terminal to be disconnected from the output signal terminal under the control of the potential of the second output node;

[0072] During the holding period, the clock signal and the input signal are normally supplied to the odd-numbered stage driving circuits.

[0073] In a sixth aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned driving module. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] FIG1 is a structural diagram of a driving circuit according to an embodiment of the present disclosure;

[0075] FIG2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0076] FIG3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0077] FIG4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0078] FIG5 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0079] FIG6 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0080] FIG7 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG6 during a refresh period;

[0081] FIG8 is a timing diagram of the operation of at least one embodiment of the driving circuit shown in FIG6 during a display period;

[0082] 9 is a timing diagram of the operation of the driving circuit when the clock signal and the first input signal are stopped during the holding period when the related art is adopted;

[0083] FIG10 is a timing diagram of the operation of at least one embodiment of the driving circuit shown in FIG6 during a display period;

[0084] FIG11 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0085] FIG12 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0086] FIG13 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0087] FIG14 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG13 during a refresh period;

[0088] FIG15 is a timing diagram illustrating the operation of at least one embodiment of the driving circuit shown in FIG13 during a display period;

[0089] 16 is a timing diagram of the operation of the driving circuit when the clock signal and the second input signal are stopped during the holding period FB when the related art is adopted;

[0090] FIG17 is a timing diagram illustrating the operation of at least one embodiment of the driving circuit shown in FIG13 during a display period;

[0091] FIG18 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0092] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0093] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0094] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0095] As shown in FIG1 , the driving circuit according to the embodiment of the present disclosure includes a first output circuit 11 , a second output circuit 12 and a first output node control circuit 13 ;

[0096] The control terminal of the first output circuit 11 is electrically connected to the first output node NO1. The first output circuit 11 is also electrically connected to the first voltage terminal V1 and the drive signal output terminal GT, respectively, and is used to control the connection or disconnection between the drive signal output terminal GT and the first voltage terminal V1 under the control of the potential of the first output node NO1;

[0097] The control terminal of the second output circuit 12 is electrically connected to the second output node NO2. The second output circuit is also electrically connected to the output signal terminal S1 and the drive signal output terminal GT, respectively, and is used to control the connection or disconnection between the drive signal output terminal GT and the output signal terminal S1 under the control of the potential of the second output node NO2;

[0098] The first output node control circuit 13 is electrically connected to the first output control terminal Tx1, the second voltage terminal V2 and the first output node NO1 respectively, and is used to control the connection or disconnection between the first output node NO1 and the second voltage terminal V2 under the control of the first output control signal provided by the first output control terminal Tx1.

[0099] When the embodiment of the driving circuit shown in Figure 1 of the present disclosure is working, during low-frequency display, the display cycle may include a refresh time period and a hold time period. During the hold time period, the clock signal terminal may be controlled to stop providing the corresponding clock signal, and the first output node NO1 may be controlled to be connected to the second voltage terminal V2 under the control of the first output control signal provided by the first output control terminal Tx1 of the first output node control circuit 13. The first output circuit 11 may be controlled to be connected to the driving signal output terminal GT and the first voltage terminal V1 under the control of the potential of the first output node NO1, thereby controlling the driving signal output terminal GT to normally output the driving signal, and at the same time reducing power consumption.

[0100] Optionally, the first voltage terminal V1 may be a low voltage terminal, the output signal terminal S1 may be a second clock signal terminal or a high voltage terminal, and the second voltage terminal V2 may be a high voltage terminal, but is not limited thereto.

[0101] In a specific implementation, the second voltage terminal V2 can also be the first high voltage terminal or the second high voltage terminal. The value of the second voltage terminal V2 only needs to satisfy the requirement that when the first output node NO1 is connected to the second voltage terminal V2, the first output circuit 11 can control the connection between the drive signal output terminal GT and the first voltage terminal V1.

[0102] The driving circuit according to at least one embodiment of the present disclosure further includes a second output node control circuit;

[0103] The second output node control circuit is electrically connected to the second output control terminal, the third voltage terminal and the second output node respectively, and is used to control the connection or disconnection between the second output node and the third voltage terminal under the control of a second output control signal provided by the second output control terminal.

[0104] In a specific implementation, the driving circuit may further include a second output node control circuit. The second output node control circuit controls the connection or disconnection between the second output node and the third voltage terminal under the control of a second output control signal.

[0105] Optionally, the third voltage end may be a low voltage end, but is not limited thereto.

[0106] In actual operation, the third voltage terminal can also be the first low voltage terminal or the second low voltage terminal. It only needs to ensure that when the second output node control terminal circuit controls the connection between the second output node and the third voltage terminal, the second output circuit can control the disconnection between the drive signal output terminal and the output signal terminal.

[0107] As shown in FIG2 , based on at least one embodiment of the driving circuit shown in FIG1 , the driving circuit according to at least one embodiment of the present disclosure further includes a second output node control circuit 21 ;

[0108] The second output node control circuit 21 is electrically connected to the second output control terminal Tx2, the third voltage terminal V3 and the second output node NO2, respectively, and is used to control the connection or disconnection between the second output node NO2 and the third voltage terminal V3 under the control of the second output control signal provided by the second output control terminal Tx2.

[0109] When at least one embodiment of the driving circuit of the present disclosure as shown in Figure 2 is in operation, during the holding time period included in the display cycle, the second output node control circuit 21 can control the second output node NO2 to be connected to the third voltage terminal V3 under the control of the second output control signal, so as to control the second output circuit 12 to be disconnected from the driving signal output terminal GT and the output signal terminal S1 under the control of the potential of the second output node NO2, so as to control the driving signal output terminal GT to normally output the driving signal while saving power consumption.

[0110] When at least one embodiment of the driving circuit of the present disclosure as shown in Figure 2 is working, during the refresh time period included in the display cycle, each clock signal terminal normally provides a clock signal, and the first output node control circuit 13 controls the first output node NO1 and the second voltage terminal V2 to be disconnected under the control of the first output control signal, and the second output node control circuit 21 controls the second output node NO2 and the third voltage terminal V3 to be disconnected under the control of the second output control signal, so that the driving circuit can work normally.

[0111] In at least one embodiment of the driving circuit shown in FIG. 2 , Tx1 and Tx2 may be the same output control terminal, or Tx1 and Tx2 may be different output control terminals.

[0112] Optionally, the first output node control circuit includes a first transistor;

[0113] The gate of the first transistor is electrically connected to the first output control terminal, the first electrode of the first transistor is electrically connected to the second voltage terminal, and the second electrode of the first transistor is electrically connected to the first output node.

[0114] Optionally, the second output node control circuit includes a second transistor;

[0115] The gate of the second transistor is electrically connected to the second output control terminal, the first electrode of the second transistor is electrically connected to the third voltage terminal, and the second electrode of the second transistor is electrically connected to the second output node.

[0116] In at least one embodiment of the present disclosure, the first output control terminal and the second output control terminal are the same output control terminal; or,

[0117] The first output control end and the second output control end are different output control ends.

[0118] The driving circuit according to at least one embodiment of the present disclosure further includes a second node control circuit and an on-off control circuit;

[0119] The second node control circuit is electrically connected to the second node and is used to control the potential of the second node;

[0120] The on-off control circuit is electrically connected to the fourth voltage terminal, the second node and the second output node respectively, and is used to control the connection or disconnection between the second node and the second output node under the control of a fourth voltage signal provided by the fourth voltage terminal.

[0121] In a specific implementation, the driving circuit may further include a second node control circuit and an on-off control circuit; the second node control circuit controls the potential of the second node; the on-off control circuit controls the connection or disconnection between the second node and the second output node under the control of a fourth voltage signal provided by the fourth voltage terminal.

[0122] As shown in FIG3 , based on at least one embodiment of the driving circuit shown in FIG2 , the driving circuit further includes a second node control circuit 31 and an on-off control circuit 32 ;

[0123] The second node control circuit 31 is electrically connected to the second node N2 and is used to control the potential of the second node N2;

[0124] The on-off control circuit 32 is electrically connected to the fourth voltage terminal V4, the second node N2 and the second output node NO2 respectively, and is used to control the connection or disconnection between the second node N2 and the second output node NO2 under the control of the fourth voltage signal provided by the fourth voltage terminal V4.

[0125] Optionally, when the transistor included in the on-off control circuit 32 is an n-type transistor, the fourth voltage terminal V4 can be a high voltage terminal; or, when the transistor included in the on-off control circuit 32 is a p-type transistor, the fourth voltage terminal is a low voltage terminal.

[0126] Optionally, the on-off control circuit includes an on-off control transistor;

[0127] The gate of the on-off control transistor is electrically connected to the fourth voltage terminal, the first electrode of the on-off control transistor is electrically connected to the second node, and the second electrode of the on-off control transistor is electrically connected to the second output node;

[0128] The on-off control transistor is an n-type transistor, and the fourth voltage terminal is a high voltage terminal; or, the on-off control transistor is a p-type transistor, and the fourth voltage terminal is a low voltage terminal.

[0129] Optionally, the second node control circuit is electrically connected to the first clock signal terminal and the first input terminal respectively, and is used to control the connection or disconnection between the second node and the first input terminal under the control of the first clock signal provided by the first clock signal terminal.

[0130] In a specific implementation, the second node control circuit can control the connection or disconnection between the second node and the first input terminal under the control of the first clock signal.

[0131] In at least one embodiment of the present disclosure, the second node control circuit is also electrically connected to the first output node, the first voltage terminal and the second clock signal terminal, respectively, and is used to control the connection between the second node and the first voltage terminal under the control of the potential of the first output node and the second clock signal provided by the second clock signal terminal.

[0132] In a specific implementation, the second node control circuit may further control the connection between the second node and the first voltage terminal under the control of the potential of the first output node and the second clock signal.

[0133] In at least one embodiment of the present disclosure, the driving circuit described in at least one embodiment of the present disclosure further includes a first output control circuit;

[0134] The first output control circuit is electrically connected to the first clock signal terminal, the fifth voltage terminal, the first output node, the second clock signal terminal and the first voltage terminal, respectively, and is used to control the connection between the first output node and the fifth voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the connection between the first output node and the first voltage terminal under the control of the second clock signal provided by the second clock signal terminal.

[0135] In a specific implementation, the driving circuit according to at least one embodiment of the present disclosure further includes a first output control circuit;

[0136] The first output control circuit can control the connection between the first output node and the fifth voltage terminal under the control of the first clock signal, and control the connection between the first output node and the first voltage terminal under the control of the second clock signal.

[0137] In at least one embodiment of the present disclosure, the first output control circuit is electrically connected to the first clock signal terminal, the fifth voltage terminal, the first output node and the second node, respectively, and is used to control the connection between the first output node and the fifth voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and write the first clock signal into the first output node under the control of the potential of the second node.

[0138] In a specific implementation, the first output control circuit can control the connection between the first output node and the fifth voltage terminal under the control of the first clock signal, and write the first clock signal into the first output node under the control of the potential of the second node.

[0139] Optionally, the fifth voltage terminal may be a high voltage terminal, but is not limited thereto.

[0140] The driving circuit according to at least one embodiment of the present disclosure further includes a first energy storage circuit and a second energy storage circuit;

[0141] The first energy storage circuit is electrically connected to the first output node and the first voltage terminal respectively, and is used to store electrical energy;

[0142] The second energy storage circuit is electrically connected to the second output node and the driving signal output terminal respectively, and is used for storing electric energy.

[0143] Optionally, the driving circuit may further include a first energy storage circuit and a second energy storage circuit, the first energy storage circuit is used to maintain the potential of the first output node, and the second energy storage circuit can be used to control the potential of the second output node.

[0144] As shown in FIG4 , based on at least one embodiment of the driving circuit shown in FIG3 , the driving circuit according to at least one embodiment of the present disclosure further includes a second energy storage circuit 52 and a first output control circuit 41 ;

[0145] The second node control circuit 31 is electrically connected to the first clock signal terminal GCK and the first input terminal GSTV, and is used to control the connection or disconnection between the second node N2 and the first input terminal GSTV under the control of the first clock signal provided by the first clock signal terminal GCK;

[0146] The first output control circuit 41 is electrically connected to the first clock signal terminal GCK, the fifth voltage terminal V5, the first output node NO1, the second clock signal terminal GCB, and the first voltage terminal V1, respectively, and is configured to control the communication between the first output node NO1 and the fifth voltage terminal V5 under the control of the first clock signal provided by the first clock signal terminal GCK, and control the communication between the first output node NO1 and the first voltage terminal V1 under the control of the second clock signal provided by the second clock signal terminal GCB;

[0147] The second energy storage circuit 52 is electrically connected to the second output node NO2 and the driving signal output terminal GT, respectively, and is used for storing electrical energy.

[0148] Optionally, the fifth voltage terminal may be a high voltage terminal, and the first voltage terminal may be a low voltage terminal.

[0149] As shown in FIG5 , based on at least one embodiment of the driving circuit shown in FIG3 , the driving circuit according to at least one embodiment of the present disclosure further includes a first output control circuit 41 ;

[0150] The second node control circuit 31 is electrically connected to the first clock signal terminal GCK and the first input terminal GSTV, and is used to control the connection or disconnection between the second node N2 and the first input terminal GSTV under the control of the first clock signal provided by the first clock signal terminal GCK;

[0151] The second node control circuit 31 is further electrically connected to the first output node NO1, the first voltage terminal V1, and the second clock signal terminal GCB, respectively, and is configured to control the connection between the second node N2 and the first voltage terminal V1 under the control of the potential of the first output node NO1 and the second clock signal provided by the second clock signal terminal GCB;

[0152] The first output control circuit 41 is electrically connected to the first clock signal terminal GCK, the fifth voltage terminal V5, the first output node NO1, and the second node N2, respectively, and is configured to control the communication between the first output node NO1 and the fifth voltage terminal V5 under the control of the first clock signal provided by the first clock signal terminal GCK, and write the first clock signal into the first output node NO1 under the control of the potential of the second node N2;

[0153] The driving circuit according to at least one embodiment of the present disclosure further includes a first energy storage circuit 51 and a second energy storage circuit 52;

[0154] The first energy storage circuit 51 is electrically connected to the first output node NO1 and the first voltage terminal V1 respectively, and is used to store electrical energy;

[0155] The second energy storage circuit 52 is electrically connected to the second output node NO2 and the driving signal output terminal GT, respectively, and is used for storing electrical energy.

[0156] As shown in FIG6 , based on at least one embodiment of the driving circuit shown in FIG4 ,

[0157] The first output node control circuit includes a first transistor T1;

[0158] The gate of the first transistor T1 is electrically connected to the first output control terminal Tx1, the source of the first transistor T1 is electrically connected to the high voltage terminal VGH, and the drain of the first transistor T1 is electrically connected to the first output node NO1;

[0159] The second output node control circuit includes a second transistor T2;

[0160] The gate of the second transistor T2 is electrically connected to the second output control terminal Tx2, the source of the second transistor T2 is electrically connected to the low voltage terminal VGL, and the drain of the second transistor T2 is electrically connected to the second output node NO2;

[0161] The first output control circuit includes a third transistor T3 and a fourth transistor T4;

[0162] The gate of the third transistor T3 is electrically connected to the first clock signal terminal GCK, the source of the third transistor T3 is electrically connected to the high voltage terminal VGH, and the drain of the third transistor T3 is electrically connected to the first output node NO1;

[0163] The gate of the fourth transistor T4 is electrically connected to the second clock signal terminal GCB, the source of the fourth transistor T4 is electrically connected to the low voltage terminal VGL, and the drain of the fourth transistor T4 is electrically connected to the first output node NO1;

[0164] The on-off control circuit includes a fifth transistor T5;

[0165] The gate of the fifth transistor T5 is electrically connected to the high voltage terminal VGH, the source of the fifth transistor T5 is electrically connected to the second node N2, and the drain of the fifth transistor T5 is electrically connected to the second output node NO;

[0166] The second node control circuit includes a sixth transistor T6;

[0167] The gate of the sixth transistor T6 is electrically connected to the first clock signal terminal GCK, the first electrode of the sixth transistor T6 is electrically connected to the first input terminal GSTV, and the second electrode of the sixth transistor T6 is electrically connected to the second node N2;

[0168] The first output circuit includes a first output transistor TO1;

[0169] The gate of the first output transistor TO1 is electrically connected to the first output node NO1, the source of the first output transistor TO1 is electrically connected to the low voltage terminal VGL, and the drain of the first output transistor TO1 is electrically connected to the driving signal output terminal GT;

[0170] The second output circuit includes a second output transistor TO2;

[0171] The gate of the second output transistor TO2 is electrically connected to the second output node NO2, the source of the second output transistor TO2 is electrically connected to the second clock signal terminal GCB, and the drain of the second output transistor TO2 is electrically connected to the drive signal output terminal GT;

[0172] The second energy storage circuit includes a second capacitor C2;

[0173] A first end of the second capacitor C2 is electrically connected to the second output node NO2 , and a second end of the second capacitor C2 is electrically connected to the driving signal output terminal GT.

[0174] In at least one embodiment of the driving circuit shown in FIG. 6 , all transistors are n-type transistors, but the present invention is not limited thereto.

[0175] In at least one embodiment of the driving circuit shown in FIG. 6 , Tx1 and Tx2 may be the same output control terminal, or Tx1 and Tx2 may be different output control terminals.

[0176] At least one embodiment of the driving circuit shown in Figure 6 of the present disclosure adopts T1 controlled by Tx1 and T2 controlled by Tx2, so that during low-frequency display, the driving signal can be output normally during the holding frame (i.e., the holding time period) even if the clock signal and input signal are not provided, thereby saving power consumption.

[0177] At least one embodiment of the driving circuit shown in FIG6 , when in operation, during low-frequency display, a display cycle may include a refresh period and a hold period;

[0178] During the refresh period, GCK and GCB normally output corresponding clock signals, GSTV provides corresponding input signals, Tx1 and Tx2 provide low voltage signals, T1 and T2 are turned off, and the driving circuit normally outputs driving signals;

[0179] During the hold time period, GCK and GCB stop providing clock signals, GSTV stops providing corresponding input signals, and Tx1 and Tx2 can both provide high voltage signals to control T1 and T2 to turn on, so that TO1 is turned on and TO2 is turned off, and GT continues to output low voltage signals. In this way, power consumption can be reduced during the hold time period while ensuring the stable output of the drive signal output terminal GT.

[0180] In at least one embodiment of the driving circuit shown in FIG6 , during operation, during the hold period, the first output control signal provided by Tx1 and the second output control signal provided by Tx2 may also be square wave voltage signals. In this case, the frequency of the first output control signal and the frequency of the second output control signal may be set to be higher than the display refresh frequency to optimize TFT (thin film transistor) bias leakage.

[0181] At this time, when the potential of the first output control signal is a high voltage, T1 can be turned on, and when the potential of the first output control signal is a low voltage, T1 can be turned off;

[0182] When the potential of the second output control signal is a high voltage, T2 may be turned on, and when the potential of the second output control signal is a low voltage, T2 may be turned off.

[0183] In at least one embodiment of the driving circuit shown in FIG6 , when in operation, the first output control terminal Tx1 and the second output control terminal Tx2 may be different output control terminals. Since the leakage paths and leakage amounts of TO1 and TO2 are different, the on-time of T1 may be greater than the on-time of T2 during the holding period.

[0184] When at least one embodiment of the driving circuit shown in FIG6 is in operation, during low-frequency display, the frequency of the first clock signal and the frequency of the second clock signal may be equal to the frequency of the data voltage provided to the data line during the display period to save power consumption.

[0185] FIG. 7 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 6 during a refresh period.

[0186] FIG. 8 is a timing diagram illustrating the operation of at least one embodiment of the driving circuit shown in FIG. 6 during a display period.

[0187] As shown in FIG8 , the display cycle includes a refresh period FS and a hold period FB;

[0188] During the refresh period FS, GSTV normally outputs the first input signal, GCK normally outputs the first clock signal, GCB normally outputs the second clock signal, and Tx outputs a low voltage signal;

[0189] During the holding period FB, GSTV stops outputting the first input signal, GCK stops outputting the clock signal, GCB stops outputting the clock signal, and Tx outputs a high voltage signal.

[0190] Figure 9 is a timing diagram of the operation of the drive circuit when the clock signal and the first input signal are stopped during the hold period when using the related art. As shown in Figure 9, during the hold period FB, the potential of the drive signal provided by GT has an upward step, resulting in an abnormal output.

[0191] FIG. 10 is a timing diagram illustrating the operation of at least one embodiment of the driving circuit shown in FIG. 6 during a display period.

[0192] As can be seen from FIG. 10 , by adopting at least one embodiment of the driving circuit shown in FIG. 6 , the driving signal provided by GT is normal during the holding period.

[0193] As shown in FIG11 , based on at least one embodiment of the driving circuit shown in FIG5 , the first output node control circuit includes a first transistor T1;

[0194] The gate of the first transistor T1 is electrically connected to the first output control terminal Tx1, the source of the first transistor T1 is electrically connected to the high voltage terminal VGH, and the drain of the first transistor T1 is electrically connected to the first output node NO1;

[0195] The second output node control circuit includes a second transistor T2;

[0196] The gate of the second transistor T2 is electrically connected to the second output control terminal Tx2, the source of the second transistor T2 is electrically connected to the low voltage terminal VGL, and the drain of the second transistor T2 is electrically connected to the second output node NO2;

[0197] The first output control circuit includes a third transistor T3 and a fourth transistor T4;

[0198] The gate of the third transistor T3 is electrically connected to the first clock signal terminal GCK, the source of the third transistor T3 is electrically connected to the high voltage terminal VGH, and the drain of the third transistor T3 is electrically connected to the first output node NO1;

[0199] The gate of the fourth transistor T4 is electrically connected to the second node N2, the source of the fourth transistor T4 is electrically connected to the first clock signal terminal GCK, and the drain of the fourth transistor T4 is electrically connected to the first output node NO1;

[0200] The on-off control circuit includes a fifth transistor T5;

[0201] The gate of the fifth transistor T5 is electrically connected to the high voltage terminal VGH, the source of the fifth transistor T5 is electrically connected to the second node N2, and the drain of the fifth transistor T5 is electrically connected to the second output node NO;

[0202] The second node control circuit includes a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8;

[0203] The gate of the sixth transistor T6 is electrically connected to the first clock signal terminal GCK, the first electrode of the sixth transistor T6 is electrically connected to the first input terminal GSTV, and the second electrode of the sixth transistor T6 is electrically connected to the second node N2;

[0204] The gate of the seventh transistor T7 is electrically connected to the first output node NO1, the source of the seventh transistor T7 is electrically connected to the low voltage terminal VGL, and the drain of the seventh transistor T7 is electrically connected to the source of the eighth transistor T8;

[0205] The gate of the eighth transistor T8 is electrically connected to the second clock signal terminal GCB, and the drain of the eighth transistor T8 is electrically connected to the second node N2;

[0206] The first output circuit includes a first output transistor TO1;

[0207] The gate of the first output transistor TO1 is electrically connected to the first output node NO1, the source of the first output transistor TO1 is electrically connected to the low voltage terminal VGL, and the drain of the first output transistor TO1 is electrically connected to the driving signal output terminal GT;

[0208] The second output circuit includes a second output transistor TO2;

[0209] The gate of the second output transistor TO2 is electrically connected to the second output node NO2, the source of the second output transistor TO2 is electrically connected to the second clock signal terminal GCB, and the drain of the second output transistor TO2 is electrically connected to the drive signal output terminal GT;

[0210] The first energy storage circuit includes a first capacitor C1; the second energy storage circuit includes a second capacitor C2;

[0211] A first terminal of C1 is electrically connected to the first output node NO1, and a second terminal of C1 is electrically connected to the low voltage terminal VGL;

[0212] A first end of C2 is electrically connected to the second output node NO2 , and a second end of C2 is electrically connected to the driving signal output terminal GT.

[0213] In at least one embodiment of the driving circuit shown in FIG. 11 , all transistors may be n-type transistors, but the present invention is not limited thereto.

[0214] In at least one embodiment of the driving circuit shown in FIG. 11 , Tx1 and Tx2 may be the same output control terminal, or Tx1 and Tx2 may be different output control terminals.

[0215] At least one embodiment of the driving circuit shown in Figure 11 of the present disclosure adopts T1 controlled by Tx1 and T2 controlled by Tx2, so that during low-frequency display, the driving signal can be output normally during the holding frame (i.e., the holding time period) even if the clock signal and input signal are not provided, thereby saving power consumption.

[0216] At least one embodiment of the driving circuit shown in FIG11 of the present disclosure, when in operation, during low-frequency display, a display cycle may include a refresh period and a hold period;

[0217] During the refresh period, GCK and GCB normally output corresponding clock signals, GSTV provides corresponding input signals, Tx1 and Tx2 provide low voltage signals, T1 and T2 are turned off, and the driving circuit normally outputs driving signals;

[0218] During the hold time period, GCK and GCB stop providing clock signals, GSTV stops providing corresponding input signals, and Tx1 and Tx2 can both provide high voltage signals to control T1 and T2 to turn on, so that TO1 is turned on and TO2 is turned off, and GT continues to output low voltage signals. In this way, power consumption can be reduced during the hold time period while ensuring the stable output of the drive signal output terminal GT.

[0219] In at least one embodiment of the driving circuit shown in FIG11 , during operation, during the hold period, the first output control signal provided by Tx1 and the second output control signal provided by Tx2 may also be square wave voltage signals. In this case, the frequency of the first output control signal and the second output control signal may be set to be higher than the display refresh frequency to optimize TFT bias leakage.

[0220] At this time, when the potential of the first output control signal is a high voltage, T1 can be turned on, and when the potential of the first output control signal is a low voltage, T1 can be turned off;

[0221] When the potential of the second output control signal is a high voltage, T2 may be turned on, and when the potential of the second output control signal is a low voltage, T2 may be turned off.

[0222] In at least one embodiment of the driving circuit shown in FIG11 , when in operation, the first output control terminal Tx1 and the second output control terminal Tx2 may be different output control terminals. Since the leakage paths and leakage amounts of TO1 and TO2 are different, the on-time of T1 may be greater than the on-time of T2 during the holding period.

[0223] When at least one embodiment of the driving circuit shown in FIG11 is in operation, during low-frequency display, the frequency of the first clock signal and the frequency of the second clock signal may be equal to the frequency of the data voltage provided to the data line during the display period to save power consumption.

[0224] In at least one embodiment of the present disclosure, the driving circuit may further include a first control circuit;

[0225] The first control circuit includes a third node control circuit, a fourth node control circuit and a first node control circuit;

[0226] The third node control circuit is electrically connected to the third node, the third clock signal terminal, the fifth voltage terminal, and the second output node, respectively, and is configured to control communication between the third node and the fifth voltage terminal under the control of a third clock signal provided by the third clock signal terminal, write the third clock signal into the third node under the control of the potential of the second output node, and maintain the potential of the third node;

[0227] The fourth node control circuit is electrically connected to the third node, the fourth clock signal terminal and the fourth node respectively, and is configured to write the fourth clock signal provided by the fourth clock signal terminal into the fourth node under the control of the potential of the third node;

[0228] The first node control circuit is electrically connected to the fourth clock signal terminal, the fourth node, the first output node, the second output node and the first voltage terminal, respectively, and is used to control the connection between the fourth node and the first output node under the control of the fourth clock signal, and to control the connection between the first output node and the first voltage terminal under the control of the potential of the second output node.

[0229] In a specific implementation, the first control circuit may include a third node control circuit, a fourth node control circuit and a first node control circuit; the third node control circuit controls the connection between the second output node and the fifth voltage terminal under the control of a third clock signal, writes the third clock signal into the third node under the control of the potential of the second output node, and is used to maintain the potential of the third node; the fourth node control circuit writes the fourth clock signal into the fourth node under the control of the potential of the third node; the first node control circuit controls the connection between the fourth node and the first output node under the control of the fourth clock signal, and controls the connection between the first output node and the first voltage terminal under the control of the potential of the second output node.

[0230] Optionally, the fifth voltage terminal may be a high voltage terminal, but is not limited thereto.

[0231] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a second output control circuit;

[0232] The second output control circuit is electrically connected to the second output node, the third clock signal terminal and the second input terminal respectively, and is used to control the connection between the second output node and the second input terminal under the control of the third clock signal provided by the third clock signal terminal.

[0233] In a specific implementation, the second output control circuit may further control the connection between the second output node and the second input terminal under the control of a third clock signal.

[0234] As shown in FIG12 , based on at least one embodiment of the driving circuit shown in FIG2 , the driving circuit according to at least one embodiment of the present disclosure further includes a first control circuit and a second output control circuit 42 ;

[0235] The first control circuit includes a third node control circuit 121, a fourth node control circuit 122 and a first node control circuit 123;

[0236] The third node control circuit 121 is electrically connected to the third node N3, the third clock signal terminal ECK, the fifth voltage terminal V5, and the second output node NO2, respectively, and is configured to control communication between the third node N3 and the fifth voltage terminal V5 under the control of a third clock signal provided by the third clock signal terminal ECK, write the third clock signal into the third node N3 under the control of the potential of the second output node NO2, and maintain the potential of the third node N3;

[0237] The fourth node control circuit 122 is electrically connected to the third node N3, the fourth clock signal terminal ECB, and the fourth node N4, respectively, and is configured to write the fourth clock signal provided by the fourth clock signal terminal ECB into the fourth node N4 under the control of the potential of the third node N3;

[0238] The first node control circuit 123 is electrically connected to the fourth clock signal terminal ECB, the fourth node N4, the first output node NO1, the second output node NO2, and the first voltage terminal V1, respectively, and is configured to control the fourth node N4 to be connected to the first output node NO1 under the control of the fourth clock signal, and to control the first output node NO1 to be connected to the first voltage terminal V1 under the control of the potential of the second output node NO2;

[0239] The second output control circuit 42 is electrically connected to the second output node NO2, the third clock signal terminal ECK and the second input terminal ESTV, respectively, and is used to control the communication between the second output node NO2 and the second input terminal ESTV under the control of the third clock signal provided by the third clock signal terminal ECK;

[0240] The driving circuit further includes a first energy storage circuit 51 and a second energy storage circuit 52;

[0241] The first energy storage circuit 51 is electrically connected to the first output node NO1 and the first voltage terminal V1 respectively, and is used to store electrical energy;

[0242] The second energy storage circuit 52 is electrically connected to the second output node NO2 and the driving signal output terminal GT, respectively, and is used for storing electrical energy.

[0243] As shown in FIG13 , based on at least one embodiment of the driving circuit shown in FIG12 , the first output node control circuit includes a first transistor T1 ;

[0244] The gate of the first transistor T1 is electrically connected to the first output control terminal Tx1, the source of the first transistor T1 is electrically connected to the high voltage terminal VGH, and the drain of the first transistor T1 is electrically connected to the first output node NO1;

[0245] The second output node control circuit includes a second transistor T2;

[0246] The gate of the second transistor T2 is electrically connected to the second output control terminal Tx2, the source of the second transistor T2 is electrically connected to the low voltage terminal VGL, and the drain of the second transistor T2 is electrically connected to the second output node NO2;

[0247] The third node control circuit includes a ninth transistor T9, a tenth transistor T10 and a storage capacitor Cst;

[0248] The gate of the ninth transistor T9 is electrically connected to the third clock signal terminal ECK, the source of the ninth transistor T9 is electrically connected to the high voltage terminal VGH, and the drain of the ninth transistor T9 is electrically connected to the third node N3;

[0249] The gate of the tenth transistor T10 is electrically connected to the second output node NO2, the source of the tenth transistor T10 is electrically connected to the third clock signal terminal, and the drain of the tenth transistor T10 is electrically connected to the third node N3;

[0250] A first terminal of Cst is electrically connected to the third node N3, and a second terminal of Cst is electrically connected to the high voltage terminal VGH;

[0251] The fourth node control circuit includes an eleventh transistor T11;

[0252] The gate of the eleventh transistor T11 is electrically connected to the third node N3, the source of the eleventh transistor T11 is electrically connected to the fourth clock signal terminal ECB, and the drain of the eleventh transistor T11 is electrically connected to the fourth node N4;

[0253] The first node control circuit includes a twelfth transistor T12 and a thirteenth transistor T13;

[0254] The gate of T12 is electrically connected to the fourth clock signal terminal ECB, the source of T12 is electrically connected to the fourth node N4, and the drain of T12 is electrically connected to the first output node NO1;

[0255] The gate of T13 is electrically connected to the second output node NO2, the source of T13 is electrically connected to the low voltage terminal VGL, and the drain of T13 is electrically connected to the first output node NO1;

[0256] The second output control circuit includes a fourteenth transistor T14;

[0257] The gate of the fourteenth transistor T14 is electrically connected to the third clock signal terminal ECK, the source of T14 is electrically connected to the second input terminal ESTV, and the drain of T14 is electrically connected to the second output node NO2;

[0258] The first output circuit includes a first output transistor TO1;

[0259] The gate of the first output transistor TO1 is electrically connected to the first output node NO1, the source of the first output transistor TO1 is electrically connected to the low voltage terminal VGL, and the drain of the first output transistor TO1 is electrically connected to the driving signal output terminal GT;

[0260] The second output circuit includes a second output transistor TO2;

[0261] The gate of the second output transistor TO2 is electrically connected to the second output node NO2, the source of the second output transistor TO2 is electrically connected to the second clock signal terminal GCB, and the drain of the second output transistor TO2 is electrically connected to the drive signal output terminal GT;

[0262] The first energy storage circuit includes a first capacitor C1; the second energy storage circuit includes a second capacitor C2;

[0263] A first terminal of C1 is electrically connected to the first output node NO1, and a second terminal of C1 is electrically connected to the low voltage terminal VGL;

[0264] A first end of C2 is electrically connected to the second output node NO2 , and a second end of C2 is electrically connected to the driving signal output terminal GT.

[0265] At least one embodiment of the driving circuit shown in FIG. 13 can be used to provide a light-emitting control signal, that is, the driving signal output terminal GT can be used to output the light-emitting control signal.

[0266] Fig. 14 is an operation timing diagram of at least one embodiment of the driving circuit shown in Fig. 13 during a refresh period. During the refresh period, Tx1 and Tx2 provide low voltage signals, and both T1 and T2 are turned off.

[0267] In FIG14 , the first stage of the refresh period is marked t1, the second stage of the refresh period is marked t2, the third stage of the refresh period is marked t3, and the fourth stage of the refresh period is marked t4;

[0268] In the first stage t1, T14 is turned on, the potential of NO2 is high voltage, T13 is turned on, and the potential of NO1 is low voltage;

[0269] In the second stage t2, T10 is turned on, the potential of N3 is low, and the potentials of NO1 and NO2 are kept at the original potentials through the capacitors;

[0270] In the third stage t3, T14 is turned on, the potential of NO2 is low voltage, the potential of N3 is high voltage, and the potential of NO1 remains low voltage;

[0271] In the fourth stage t4, T11 and T12 are turned on, the potential of NO1 is high, and the potential of NO2 is maintained at a low voltage.

[0272] FIG. 15 is a timing diagram illustrating the operation of at least one embodiment of the driving circuit shown in FIG. 13 during a display period.

[0273] As shown in FIG15 , when at least one embodiment of the driving circuit shown in FIG13 is in operation, a display cycle includes a refresh period FS and a hold period FB;

[0274] During the refresh period FS, ESTV normally provides the second input signal, ECK normally provides the third clock signal, ECB normally provides the fourth clock signal, Tx1 and Tx2 both provide low voltage signals, and T1 and T2 are turned off;

[0275] During the holding period FB, ESTV stops providing the second input signal, ECK stops providing the third clock signal, ECB stops providing the fourth clock signal, Tx1 and Tx2 both provide high voltage signals, T1 and T2 are turned on, TO1 is turned on, and TO2 is turned off.

[0276] Figure 16 shows the operating timing of the drive circuit when the clock signal and the second input signal are stopped during the hold period FB, using the related art. As shown in Figure 16, during the hold period, the potential of the drive signal provided by GT has an upward step, resulting in an abnormal output.

[0277] FIG. 17 is a timing diagram illustrating the operation of at least one embodiment of the driving circuit shown in FIG. 13 during a display period.

[0278] As can be seen from FIG. 17 , by adopting at least one embodiment of the driving circuit shown in FIG. 13 , during the holding period FB, the driving signal provided by GT is normal.

[0279] In at least one embodiment of the present disclosure, the driving circuit may further include a first on-off control circuit;

[0280] The first output node is electrically connected to the control terminal of the first output circuit through a first on-off control circuit;

[0281] The first on-off control circuit is used to control the connection between the first output node and the control terminal of the first output circuit during at least a part of the holding time period included in the display cycle.

[0282] In a specific implementation, the driving circuit described in at least one embodiment of the present disclosure may further include a first on-off control circuit, which controls the connection between the first output node and the control end of the first output circuit during at least part of the holding time period.

[0283] In at least one embodiment of the present disclosure, the driving circuit may further include a second on-off control circuit; the second output node is electrically connected to a control terminal of the second output circuit via the second on-off control circuit;

[0284] The second on-off control circuit is used to control the connection between the second output node and the control terminal of the second output circuit during at least a part of the holding time period included in the display cycle.

[0285] In a specific implementation, the driving circuit described in at least one embodiment of the present disclosure may further include a second on-off control circuit, which controls the connection between the second output node and the control end of the second output circuit during at least part of the holding time period.

[0286] As shown in FIG18 , based on at least one embodiment of the driving circuit shown in FIG2 , the driving circuit may further include a first on-off control circuit 171 and a second on-off control circuit 172 ;

[0287] The first output node NO1 is electrically connected to the control terminal of the first output circuit 11 through the first on-off control circuit 171;

[0288] The first on-off control circuit 171 is used to control the connection between the first output node NO1 and the control terminal of the first output circuit 11 during at least part of the holding time period included in the display cycle;

[0289] The second output node NO2 is electrically connected to the control terminal of the second output circuit 12 through the second on-off control circuit 172;

[0290] The second on-off control circuit 172 is configured to control the connection between the second output node NO2 and the control terminal of the second output circuit 12 during at least a portion of a holding period included in a display cycle.

[0291] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned driving circuit, wherein the display cycle includes a refresh period and a hold period; the driving method includes:

[0292] During a refresh period, the first output node control circuit controls the first output node to be disconnected from the second voltage terminal under the control of a first output control signal provided by the first output control terminal;

[0293] During at least part of the holding time period, the first output node control circuit controls the connection between the first output node and the second voltage terminal under the control of the first output control signal provided by the first output control terminal, so that the first output circuit controls the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first output node.

[0294] In at least one embodiment of the present disclosure, the driving circuit further includes a second output node control circuit; and the driving method includes:

[0295] During a refresh period, the second output node control circuit controls the second output node to be disconnected from the third voltage terminal under the control of a second output control signal provided by the second output control terminal;

[0296] During at least part of the holding time period, the second output node control circuit, under the control of a second output control signal provided by the second output control terminal, controls the connection between the second output node and the third voltage terminal, so that the second output circuit, under the control of the potential of the second output node, controls the disconnection between the drive signal output terminal and the output signal terminal.

[0297] In at least one embodiment of the present disclosure, the driving circuit further includes a first output control circuit; the first output control circuit is electrically connected to the first clock signal terminal, and the driving circuit further includes a second node control circuit and an on-off control circuit; the second node control circuit is electrically connected to the first clock signal terminal, and the output signal terminal is a second clock signal terminal;

[0298] The frequency of the first clock signal provided by the first clock signal terminal and the frequency of the second clock signal provided by the second clock signal terminal are equal to the frequency of the data voltage provided to the data line during the display period to reduce power consumption.

[0299] Optionally, the first output control end and the second output control end are different output ends;

[0300] During the holding time period, the first output node control circuit controls the time for the first output node and the second voltage terminal to be connected to each other for a first time, and the second output node control circuit controls the time for the second output node and the third voltage terminal to be connected to each other for a second time, and the first time is greater than the second time.

[0301] Optionally, the first output control signal is a square wave signal, and the second output control signal is a square wave signal;

[0302] The frequency of the first output control signal is greater than the display refresh frequency, and the frequency of the second output control signal is greater than the display refresh frequency, which are used to optimize TFT bias leakage.

[0303] In at least one embodiment of the present disclosure, during the refresh period, the first output control signal is a first control voltage signal, and the second output control signal is a second control voltage signal;

[0304] During the holding period, the first output control signal is a third control voltage signal, and the second output control signal is a fourth control voltage signal;

[0305] The first control voltage signal is different from the third control voltage signal, and the second control voltage signal is different from the fourth control voltage signal.

[0306] Optionally, the first control voltage signal, the second control voltage signal, the third control voltage signal and the fourth control voltage signal are all DC voltage signals.

[0307] For example, the first control voltage signal and the third control voltage signal may be low voltage signals, and the second control voltage signal and the fourth control voltage signal may be high voltage signals, but the present invention is not limited thereto.

[0308] Optionally, the first control voltage signal is a DC voltage signal, and the second control voltage signal is a square wave voltage signal;

[0309] The third control voltage signal is a DC voltage signal, and the fourth DC voltage signal is a square wave voltage signal.

[0310] For example, the first control voltage signal and the third control voltage signal may be low voltage signals, and the second control voltage signal and the fourth control voltage signal may be square wave voltage signals, but the present invention is not limited thereto.

[0311] The driving method according to at least one embodiment of the present disclosure further includes:

[0312] During the holding period, supply of clock signals to the clock signal terminals and supply of input signals to the input terminals are stopped, so as to reduce power consumption.

[0313] The driving module described in the embodiment of the present disclosure includes multiple stages of the above-mentioned driving circuits.

[0314] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned driving module, wherein the driving module includes an odd-stage driving circuit and an even-stage driving circuit; the driving circuit includes a first output node control circuit and a second output node control circuit; the display cycle includes a holding period; and the driving method includes:

[0315] During the holding period, supplying clock signals and input signals to the odd-numbered stage driving circuits is stopped;

[0316] During at least part of the time included in the holding period, in the odd-numbered stage driving circuit, the first output node control circuit controls the first output node to be connected to the second voltage terminal, so that the first output circuit controls the driving signal output terminal to be connected to the first voltage terminal; and the second output node control circuit controls the second output node to be connected to the third voltage terminal, so that the second output circuit controls the driving signal output terminal to be disconnected from the output signal terminal under the control of the potential of the second output node;

[0317] During the holding period, the clock signal and the input signal are normally supplied to the even-numbered stage driving circuits.

[0318] In a specific implementation, output control signals can be provided to the odd-stage driving circuit and the even-stage driving circuit respectively. During the holding period, the clock signal and input signal can be stopped from being provided to the odd-stage driving circuit, while the clock signal and input signal can be provided normally to the even-stage driving circuit.

[0319] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned driving module, wherein the driving module includes an odd-stage driving circuit and an even-stage driving circuit; the driving circuit includes a first output node control circuit and a second output node control circuit; the display cycle includes a holding period; and the driving method includes:

[0320] During the holding period, supplying clock signals and input signals to the even-numbered stage driving circuits is stopped;

[0321] During at least part of the time included in the holding period, in the even-numbered stage driving circuit, the first output node control circuit controls the first output node to be connected to the second voltage terminal, so that the first output circuit controls the driving signal output terminal to be connected to the first voltage terminal; and the second output node control circuit controls the second output node to be connected to the third voltage terminal, so that the second output circuit controls the driving signal output terminal to be disconnected from the output signal terminal under the control of the potential of the second output node;

[0322] During the holding period, the clock signal and the input signal are normally supplied to the odd-numbered stage driving circuits.

[0323] In specific implementation, output control signals can be provided separately for odd-numbered driving circuits and even-numbered driving circuits. During the holding period, clock signals and input signals can be stopped from being provided to the even-numbered driving circuits, while clock signals and input signals can be provided normally to the odd-numbered driving circuits.

[0324] The display device described in the embodiment of the present disclosure includes the above-mentioned driving module.

[0325] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A driving circuit comprising a first output circuit, a second output circuit and a first output node control circuit; The control end of the first output circuit is electrically connected to the first output node, and the first output circuit is also electrically connected to the first voltage end and the drive signal output end respectively, and is used to control the connection or disconnection between the drive signal output end and the first voltage end under the control of the potential of the first output node; The control end of the second output circuit is electrically connected to the second output node, and the second output circuit is also electrically connected to the output signal end and the drive signal output end respectively, and is used to control the connection or disconnection between the drive signal output end and the output signal end under the control of the potential of the second output node; The first output node control circuit is electrically connected to the first output control terminal, the second voltage terminal and the first output node respectively, and is used to control the connection or disconnection between the first output node and the second voltage terminal under the control of a first output control signal provided by the first output control terminal.

2. The driving circuit according to claim 1, wherein: Also included is a second output node control circuit; The second output node control circuit is electrically connected to the second output control terminal, the third voltage terminal and the second output node respectively, and is used to control the connection or disconnection between the second output node and the third voltage terminal under the control of a second output control signal provided by the second output control terminal.

3. The driving circuit according to claim 1, wherein: The first output node control circuit includes a first transistor; The gate of the first transistor is electrically connected to the first output control terminal, the first electrode of the first transistor is electrically connected to the second voltage terminal, and the second electrode of the first transistor is electrically connected to the first output node.

4. The driving circuit according to claim 2, wherein: The second output node control circuit includes a second transistor; A gate of the second transistor is electrically connected to the second output control terminal, a first electrode of the second transistor is electrically connected to the third voltage terminal, and a second electrode of the second transistor is electrically connected to the second output node.

5. The driving circuit according to claim 2, wherein: The first output control terminal and the second output control terminal are the same output control terminal; or, The first output control terminal and the second output control terminal are different output control terminals.

6. The driving circuit according to claim 2, wherein: Also includes a second node control circuit and an on-off control circuit; The second node control circuit is electrically connected to the second node and is used to control the potential of the second node; The on-off control circuit is electrically connected to the fourth voltage terminal, the second node and the second output node respectively, and is used to control the connection or disconnection between the second node and the second output node under the control of a fourth voltage signal provided by the fourth voltage terminal.

7. The driving circuit according to claim 6, wherein: The on-off control circuit includes an on-off control transistor; The gate of the on-off control transistor is electrically connected to the fourth voltage terminal, the first electrode of the on-off control transistor is electrically connected to the second node, and the second electrode of the on-off control transistor is electrically connected to the second output node; The on-off control transistor is an n-type transistor, and the fourth voltage terminal is a high voltage terminal; or, the on-off control transistor is a p-type transistor, and the fourth voltage terminal is a low voltage terminal.

8. The driving circuit according to claim 1, wherein: The driving circuit also includes a first on-off control circuit; The first output node is electrically connected to the control end of the first output circuit through a first on-off control circuit; The first on-off control circuit is used to control the connection between the first output node and the control terminal of the first output circuit during at least a part of the holding time period included in the display cycle.

9. The driving circuit according to claim 2, wherein: The driving circuit also includes a second on-off control circuit; The second output node is electrically connected to the control end of the second output circuit through a second on-off control circuit; The second on-off control circuit is used to control the connection between the second output node and the control terminal of the second output circuit during at least a part of the holding time period included in the display cycle.

10. The driving circuit according to claim 6, wherein: The second node control circuit is electrically connected to the first clock signal terminal and the first input terminal respectively, and is used to control the connection or disconnection between the second node and the first input terminal under the control of the first clock signal provided by the first clock signal terminal.

11. The driving circuit according to claim 10, wherein: The second node control circuit is also electrically connected to the first output node, the first voltage terminal and the second clock signal terminal, respectively, and is used to control the connection between the second node and the first voltage terminal under the control of the potential of the first output node and the second clock signal provided by the second clock signal terminal.

12. The driving circuit according to claim 1, wherein: Also included is a first output control circuit; The first output control circuit is electrically connected to the first clock signal terminal, the fifth voltage terminal, the first output node, the second clock signal terminal and the first voltage terminal, respectively, and is used to control the connection between the first output node and the fifth voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the connection between the first output node and the first voltage terminal under the control of the second clock signal provided by the second clock signal terminal.

13. The driving circuit according to claim 6, wherein: Also included is a first output control circuit; The first output control circuit is electrically connected to the first clock signal terminal, the fifth voltage terminal, the first output node and the second node, respectively, and is used to control the connection between the first output node and the fifth voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and write the first clock signal into the first output node under the control of the potential of the second node.

14. The driving circuit according to claim 13, wherein: Also includes a first energy storage circuit and a second energy storage circuit; The first energy storage circuit is electrically connected to the first output node and the first voltage terminal respectively, and is used to store electric energy; The second energy storage circuit is electrically connected to the second output node and the driving signal output terminal respectively, and is used for storing electric energy.

15. The driving circuit according to claim 1, wherein: Also includes a first control circuit; The first control circuit includes a third node control circuit, a fourth node control circuit and a first node control circuit; The third node control circuit is electrically connected to the third node, the third clock signal terminal, the fifth voltage terminal and the second output node respectively, and is used to control the third node under the control of the third clock signal provided by the third clock signal terminal. connected to the fifth voltage terminal, and under the control of the potential of the second output node, writes the third clock signal into the third node and is used to maintain the potential of the third node; The fourth node control circuit is electrically connected to the third node, the fourth clock signal terminal and the fourth node respectively, and is used to write the fourth clock signal provided by the fourth clock signal terminal into the fourth node under the control of the potential of the third node; The first node control circuit is electrically connected to the fourth clock signal terminal, the fourth node, the first output node, the second output node and the first voltage terminal, respectively, and is used to control the connection between the fourth node and the first output node under the control of the fourth clock signal, and to control the connection between the first output node and the first voltage terminal under the control of the potential of the second output node.

16. The driving circuit according to claim 2, wherein: Also comprising a second output control circuit; The second output control circuit is electrically connected to the second output node, the third clock signal terminal and the second input terminal respectively, and is used to control the connection between the second output node and the second input terminal under the control of the third clock signal provided by the third clock signal terminal.

17. A driving method, applied to the driving circuit according to any one of claims 1 to 16, wherein a display period includes a refresh period and a hold period; the driving method comprises: In a refresh period, the first output node control circuit controls the first output node to be disconnected from the second voltage terminal under the control of a first output control signal provided by the first output control terminal; During at least part of the holding time period, the first output node control circuit controls the connection between the first output node and the second voltage terminal under the control of the first output control signal provided by the first output control terminal, so that the first output circuit controls the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first output node.

18. The driving method according to claim 17, wherein: The driving circuit further includes a second output node control circuit; and the driving method includes: In the refresh time period, the second output node control circuit controls the second output node to be disconnected from the third voltage terminal under the control of the second output control signal provided by the second output control terminal; During at least part of the holding time period, the second output node control circuit, under the control of a second output control signal provided by the second output control terminal, controls the connection between the second output node and the third voltage terminal, so that the second output circuit, under the control of the potential of the second output node, controls the disconnection between the drive signal output terminal and the output signal terminal.

19. The driving method according to claim 18, wherein: The driving circuit further includes a first output control circuit; the first output control circuit is electrically connected to the first clock signal terminal, and the driving circuit further includes a second node control circuit and an on-off control circuit; the second node control circuit is electrically connected to the first clock signal terminal, and the output signal terminal is a second clock signal terminal; The frequency of the first clock signal provided by the first clock signal terminal and the frequency of the second clock signal provided by the second clock signal terminal are equal to the frequency of the data voltage provided to the data line in the display period.

20. The driving method according to claim 18, wherein: The first output control terminal and the second output control terminal are different output terminals; In the holding time period, the first output node control circuit controls the time for which the first output node and the second voltage terminal are connected to each other as a first time, and the second output node control circuit controls the time for which the second output node and the third voltage terminal are connected to each other as a second time, and the first time is greater than the second time.

21. The driving method according to claim 18, wherein: The first output control signal is a square wave signal, and the second output control signal is a square wave signal; The frequency of the first output control signal is greater than the display refresh frequency, and the frequency of the second output control signal is greater than the display refresh frequency.

22. The driving method according to claim 18, wherein: In the refresh time period, the first output control signal is a first control voltage signal, and the second output control signal is a second control voltage signal; In the holding period, the first output control signal is a third control voltage signal, and the second output control signal is a fourth control voltage signal; The first control voltage signal is different from the third control voltage signal, and the second control voltage signal is different from the fourth control voltage signal.

23. The driving method according to claim 22, wherein: The first control voltage signal, the second control voltage signal, the third control voltage signal and the fourth control voltage signal are all DC voltage signals.

24. The driving method according to claim 22, wherein: The first control voltage signal is a DC voltage signal, and the second control voltage signal is a square wave voltage signal; The third control voltage signal is a DC voltage signal, and the fourth DC voltage signal is a square wave voltage signal.

25. The driving method according to any one of claims 17 to 24, wherein: Also includes: In the holding time period, supplying clock signals to each clock signal terminal is stopped, and supplying input signals to each input terminal is stopped.

26. A driving module comprising a plurality of driving circuits according to any one of claims 1 to 16.

27. A driving method, applied to the driving module according to claim 26, wherein the driving module comprises an odd-numbered driving circuit and an even-numbered driving circuit; the driving circuit comprises a first output node control circuit and a second output node control circuit; The display cycle includes a holding period; the driving method includes: In the holding period, the clock signal and the input signal are stopped from being provided to the odd-numbered stage driving circuits; During at least part of the time included in the holding period, in the odd-numbered driving circuit, the first output node control circuit controls the first output node to be connected to the second voltage terminal, so that the first output circuit controls the driving signal output terminal to be connected to the first voltage terminal; the second output node control circuit controls the second output node to be connected to the third voltage terminal, so that the second output circuit controls the driving signal output terminal to be disconnected from the output signal terminal under the control of the potential of the second output node; During the holding period, the clock signal and the input signal are normally supplied to the even-numbered stage driving circuits.

28. A driving method, applied to the driving module according to claim 26, wherein the driving module comprises an odd-numbered driving circuit and an even-numbered driving circuit; The driving circuit includes a first output node control circuit and a second output node control circuit; The display cycle includes a holding period; the driving method includes: In the holding period, the clock signal and the input signal are stopped from being provided to the even-numbered stage driving circuits; During at least part of the time included in the holding period, in the even-numbered stage driving circuit, the first output node control circuit controls the first output node to be connected to the second voltage terminal, so that the first output circuit controls the driving signal output terminal to be connected to the first voltage terminal; the second output node control circuit controls the second output node to be connected to the third voltage terminal, so that the second output circuit controls the driving signal output terminal to be disconnected from the output signal terminal under the control of the potential of the second output node; During the holding period, the clock signal and the input signal are normally supplied to the odd-numbered stage driving circuits.

29. A display device comprising the driving module according to claim 26.

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