Display substrate and display apparatus

Abstract

A display substrate, comprising: a first display area (A1) and a second display area (A2). The first display area (A1) comprises a first sub-area (A11), and a second sub-area (A12a, A12b) located on at least one side of the first sub-area (A11) close to the second display area (A2). The first sub-area (A11) comprises a plurality of display island areas (A111), and first light-transmitting areas (A112) located between adjacent display island areas (A111). The display island areas (A111) comprise a plurality of first pixel circuits (11) and a plurality of first light-emitting elements (15), the orthographic projections of the first light-emitting elements (15) at least partially overlapping the orthographic projections of the connected first pixel circuits (11) on a substrate (60). The second sub-area (A12a, A12b) comprises a plurality of second light-emitting elements (16). The second display area (A2) comprises a plurality of second pixel circuits (12) provided on the substrate (60). At least one second pixel circuit (12) is connected to at least one second light-emitting element (16) by means of a conductive connection line (53).

Description

Display substrate and display device Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide a display substrate and a display device.

[0006] In one aspect, this embodiment provides a display substrate, comprising: a first display area and a second display area located at least on one side of the first display area; the first display area comprising: a first sub-area and a second sub-area located on at least one side of the first sub-area proximal to the second display area; the first sub-area comprising: a plurality of display islands and a first light-transmitting area located between adjacent display islands. The display islands comprise: a plurality of first pixel circuits and a plurality of first light-emitting elements disposed on a substrate; the plurality of first pixel circuits and the plurality of first light-emitting elements are electrically connected; the orthographic projections of the first light-emitting elements and the first pixel circuits to which they are connected on the substrate at least partially overlap. The second sub-area comprises: a plurality of second light-emitting elements disposed on the substrate. The second display area comprises at least: a plurality of second pixel circuits disposed on the substrate; at least one of the plurality of second pixel circuits is electrically connected to at least one of the plurality of second light-emitting elements via a conductive connection line; the spacing between the orthographic projection of the second light-emitting element on the substrate and the orthographic projection of the second pixel circuit to which the second light-emitting element is connected on the substrate is greater than zero.

[0007] In some exemplary embodiments, the plurality of first pixel circuits in the display island regions are connected to a plurality of first signal lines extending along a first direction and a plurality of second signal lines extending along a second direction. Within the first sub-region, the plurality of first signal lines of adjacent display island regions in the first direction are connected via a plurality of first island region connecting lines, and the plurality of second signal lines of adjacent display island regions in the second direction are connected via a plurality of second island region connecting lines; the first direction intersects the second direction.

[0008] In some exemplary embodiments, the conductive connection line includes at least one routing layer, the plurality of first island area connection lines, the plurality of second island area connection lines and the at least one routing layer of the conductive connection line are in the same layer structure and are made of transparent conductive material.

[0009] In some exemplary embodiments, the plurality of first island area connection lines, the plurality of second island area connection lines, and the conductive connection lines are all made of metal materials.

[0010] In some exemplary embodiments, the plurality of first island area connection lines and the plurality of second island area connection lines are made of metal materials, and the conductive connection lines are made of transparent conductive materials.

[0011] In some example embodiments, the plurality of first pixel circuits in the display island area are connected to the same first power line.

[0012] In some exemplary embodiments, the plurality of first pixel circuits in the display island region are connected to the same first initial signal line and the same second initial signal line. Within the display island region, the first initial signal line, the second initial signal line, and the first power line extend in the same direction, and the first power line is located between the first initial signal line and the second initial signal line.

[0013] In some exemplary embodiments, the plurality of first pixel circuits in the display island region are connected to the same light emitting control line, and an extending direction of the light emitting control line intersects an extending direction of the first power line.

[0014] In some exemplary embodiments, the display island area includes four first pixel circuits arranged in a 2×2 array, and active layers of the four first pixel circuits are symmetrically arranged about a first center line of the four first pixel circuits in a first direction.

[0015] In some exemplary embodiments, the display island region includes three first pixel circuits, and the three first pixel circuits are sequentially arranged along a first direction.

[0016] In some exemplary embodiments, the display substrate further comprises: a light-shielding layer located on a side of the first and second pixel circuits closer to the substrate; the light-shielding layer and the orthographic projection of the first light-transmitting area on the substrate do not overlap. The light-shielding layer comprises at least: a first light-shielding block located in the display island area; the orthographic projection of the first light-shielding block on the substrate covering the plurality of first pixel circuits in the display island area and the orthographic projections of signal lines connected to the plurality of first pixel circuits on the substrate.

[0017] In some exemplary embodiments, the first light shielding blocks of adjacent display island regions are interconnected as an integral structure.

[0018] In some exemplary embodiments, the first light shielding blocks of adjacent display island regions are independently provided.

[0019] In some exemplary embodiments, an edge of the first light-shielding block close to the first light-transmitting area is an arc-shaped edge.

[0020] In some exemplary embodiments, the display substrate further comprises: a light-emitting structure layer located on a side of the plurality of first pixel circuits and the plurality of second pixel circuits away from the substrate, the light-emitting structure layer comprising a cathode layer, wherein the cathode layer and the orthographic projection of the substrate on the first light-transmitting area do not overlap. The cathode layer comprises at least cathodes of the plurality of first light-emitting elements. The cathodes of the plurality of first light-emitting elements in the display island area are interconnected as an integrated structure, and the orthographic projection of the cathodes of the plurality of first light-emitting elements in the display island area on the substrate covers the orthographic projection of the plurality of first pixel circuits in the display island area and the orthographic projection of the substrate on the signal lines connected to the plurality of first pixel circuits.

[0021] In some exemplary embodiments, the cathode layer further includes: cathodes of the plurality of second light-emitting elements; and the cathodes of the plurality of first light-emitting elements in the first sub-region and the cathodes of the plurality of second light-emitting elements in the second sub-region are connected to form a grid.

[0022] In some exemplary embodiments, the display substrate further includes: a light-shielding pixel definition layer located on a side of the cathode layer close to the substrate, the light-shielding pixel definition layer being located at least in the first sub-region, and the orthographic projection of the cathode layer on the substrate covering the orthographic projection of the light-shielding pixel definition layer on the substrate.

[0023] In some exemplary embodiments, the display substrate further comprises: a light-shielding layer located on a side of the first and second pixel circuits proximal to the substrate; the light-shielding layer and the first light-transmitting region do not overlap with each other on an orthographic projection of the substrate. The light-shielding layer comprises at least: a plurality of light-shielding strips located in the display island region; the orthographic projection of each light-shielding strip on the substrate covers the orthographic projection of the channel region of the active layer of at least one transistor in the first pixel circuit on the substrate. The orthographic projection of the cathodes of the plurality of first light-emitting elements in the display island region on the substrate covers the orthographic projection of the plurality of light-shielding strips in the display island region on the substrate.

[0024] In some exemplary embodiments, light transmittance of the first display region is greater than light transmittance of the second display region, and a light emitting element density of the second display region is the same as a light emitting element density of the first display region.

[0025] In some exemplary embodiments, the first display area is in the shape of a long strip extending along a first direction, and the second sub-area is located between the first sub-area and the second display area in the first direction.

[0026] In some exemplary embodiments, the display island area includes: at least one first light-emitting unit, the first light-emitting unit including: a plurality of adjacent first light-emitting elements. The second sub-area includes: a plurality of second light-emitting units, the second light-emitting unit including: a plurality of adjacent second light-emitting elements. The number of first light-emitting elements in the first light-emitting unit is the same as the number of second light-emitting elements in the second light-emitting unit; at least three first light-emitting elements in the first light-emitting unit are configured to emit light of different colors, and at least three second light-emitting elements in the second light-emitting unit are configured to emit light of different colors. In the adjacent area of ​​the first sub-area and the second sub-area, along the first direction, the minimum distance between the first light-emitting unit and the second light-emitting unit is less than the distance between adjacent first light-emitting units and greater than the distance between adjacent second light-emitting units.

[0027] On the other hand, this embodiment provides a display device, comprising the display substrate as described above, and a sensor located on a non-display surface side of the display substrate, wherein the orthographic projection of the sensor on the display substrate at least partially overlaps with the first display area of ​​the display substrate.

[0028] In another aspect, this embodiment provides a display substrate, comprising: a first display area and a second display area located at least to one side of the first display area. The first display area comprises: a first sub-area and a second sub-area located at least to one side of the first sub-area proximal to the second display area. The first sub-area comprises: a plurality of first pixel circuits and a plurality of first light-emitting elements disposed on a substrate. The plurality of first pixel circuits and the plurality of first light-emitting elements are electrically connected, and the orthographic projections of the substrate on the first light-emitting elements at least partially overlap with the first pixel circuits to which they are connected. The second sub-area comprises: a plurality of second light-emitting elements disposed on the substrate. The second display area comprises: at least: a plurality of second pixel circuits disposed on the substrate. At least one of the plurality of second pixel circuits is electrically connected to at least one of the plurality of second light-emitting elements via a conductive connection line, and the spacing between the second light-emitting element and the orthographic projection of the substrate on the second light-emitting element is greater than zero. For first and second light-emitting elements emitting the same color light within the first display area, along a first direction, the distance between adjacent first light-emitting elements emitting the same color light within the first sub-area is greater than the distance between adjacent second light-emitting elements emitting the same color light within the second sub-area.

[0029] In some exemplary embodiments, along the first direction, the distance between adjacent first light-emitting elements emitting the same color light in the first sub-region is 1.5 times to 2 times the distance between adjacent first light-emitting elements emitting the same color light in the second sub-region.

[0030] In some exemplary embodiments, the first sub-area includes: a plurality of display island areas and a first light-transmitting area located between adjacent display island areas. The display island area includes at least: a first light-emitting unit, the first light-emitting unit including: a plurality of adjacent first light-emitting elements. The second sub-area includes at least: a plurality of second light-emitting units, the second light-emitting unit including: a plurality of adjacent second light-emitting elements. The number of first light-emitting elements in the first light-emitting unit is the same as the number of second light-emitting elements in the second light-emitting unit; at least three first light-emitting elements in the first light-emitting unit are configured to emit light of different colors, and at least three second light-emitting elements in the second light-emitting unit are configured to emit light of different colors. In the adjacent area of ​​the first sub-area and the second sub-area, along the first direction, the minimum distance between the first light-emitting unit and the second light-emitting unit is less than the distance between adjacent first light-emitting units, and greater than the distance between adjacent second light-emitting units.

[0031] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0032] Summary of the Figures

[0033] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0034] 1A, 1B, and 1C are schematic diagrams of a display substrate according to at least one embodiment of the present disclosure;

[0035] FIG2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0036] FIG3 is a partial schematic diagram of a display area according to at least one embodiment of the present disclosure;

[0037] FIG4 is a partial schematic diagram of a first display area according to at least one embodiment of the present disclosure;

[0038] FIG5 is a partial schematic diagram of a display island area according to at least one embodiment of the present disclosure;

[0039] FIG6A is a partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0040] FIG6B is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0041] FIG6C is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0042] FIG6D is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0043] 7 is a schematic diagram of a first semiconductor layer in a display island region according to at least one embodiment of the present disclosure;

[0044] FIG8A is a schematic diagram of a display island region after forming a first conductive layer in at least one embodiment of the present disclosure;

[0045] FIG8B is a schematic diagram of the first conductive layer in FIG8A ;

[0046] FIG9A is a schematic diagram of a display island region after forming a second conductive layer in at least one embodiment of the present disclosure;

[0047] FIG9B is a schematic diagram of the second conductive layer in FIG9A ;

[0048] FIG10A is a schematic diagram of a display island region after forming a second semiconductor layer in at least one embodiment of the present disclosure;

[0049] FIG10B is a schematic diagram of the first semiconductor layer and the second semiconductor layer in FIG10A ;

[0050] FIG11A is a schematic diagram of a display island region after a third conductive layer is formed in at least one embodiment of the present disclosure;

[0051] FIG11B is a schematic diagram of the third conductive layer in FIG11A ;

[0052] FIG12 is a schematic diagram of a display island region after a fifth insulating layer is formed in at least one embodiment of the present disclosure;

[0053] FIG13A is a schematic diagram of a display island region after a fourth conductive layer is formed in at least one embodiment of the present disclosure;

[0054] FIG13B is a schematic diagram of the fourth conductive layer in FIG13A;

[0055] FIG14 is a schematic diagram of a display island region after a sixth insulating layer is formed in at least one embodiment of the present disclosure;

[0056] FIG15A is a schematic diagram of a display island region after a fifth conductive layer is formed in at least one embodiment of the present disclosure;

[0057] FIG15B is a schematic diagram of the fifth conductive layer in FIG15A;

[0058] FIG16 is a partial schematic diagram of a light shielding layer in a first sub-region according to at least one embodiment of the present disclosure;

[0059] FIG17 is another partial schematic diagram of the light shielding layer in the first sub-region according to at least one embodiment of the present disclosure;

[0060] FIG18 is a partial top view of the first sub-area according to at least one embodiment of the present disclosure;

[0061] FIG19 is another partial schematic diagram of the display area according to at least one embodiment of the present disclosure;

[0062] FIG20 is a schematic top view of a display island region according to at least one embodiment of the present disclosure;

[0063] FIG21 is a schematic diagram of the first semiconductor layer in FIG20;

[0064] FIG22 is a schematic diagram of the first semiconductor layer and the first conductive layer in FIG20 ;

[0065] FIG23 is a schematic diagram of the first semiconductor layer, the first conductive layer, and the second conductive layer in FIG20 ;

[0066] FIG24 is a schematic diagram of the first semiconductor layer, the first conductive layer, the second conductive layer, and the second semiconductor layer in FIG20 ;

[0067] FIG25 is a schematic diagram of the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer and the third conductive layer in FIG20 ;

[0068] FIG26 is a schematic diagram of via holes formed in the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, the third conductive layer, and the fifth insulating layer in FIG20 ;

[0069] FIG27A is a schematic diagram of the display island region after the fourth conductive layer is formed in FIG20;

[0070] FIG27B is a schematic diagram of the fourth conductive layer in FIG27A ;

[0071] FIG28 is another partial schematic diagram of the light shielding layer in the first sub-region according to at least one embodiment of the present disclosure;

[0072] FIG29 is a partial schematic diagram of a display island region according to at least one embodiment of the present disclosure;

[0073] FIG30 is a schematic diagram of a cathode layer in a first display area according to at least one embodiment of the present disclosure;

[0074] FIG31 is another partial schematic diagram of a display area according to at least one embodiment of the present disclosure;

[0075] FIG32 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0076] FIG33 is another partial schematic diagram of the display area according to at least one embodiment of the present disclosure;

[0077] FIG34 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0078] Details

[0079] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0080] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0081] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0082] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0083] In this specification, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connected," and "coupled" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meanings of these terms in this disclosure based on the specific circumstances.

[0084] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0085] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0086] In this specification, the first electrode can be referred to as the drain and the second electrode as the source, or vice versa. The functions of "source" and "drain" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0087] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0088] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0089] The term "light transmittance" in this disclosure refers to the ability of light to pass through a medium, and is the percentage of the luminous flux passing through a transparent or translucent body to the incident luminous flux.

[0090] In this disclosure, the terms "approximately" and "substantially" are used without strict boundaries, allowing for process and measurement errors. In this disclosure, "same" can include both identical and substantially the same. "Substantially the same" means that the values ​​differ by less than 10%.

[0091] In this disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In this disclosure, "A extends along direction B" means "the main portion of A extends along direction B."

[0092] With the continuous development of display technology, cameras are usually installed on display devices to meet the needs of shooting or face recognition. In order to maximize the screen-to-body ratio, technologies such as bangs screen, water drop screen, and hollowing out in the screen have appeared one after another. These technologies are achieved by making holes in part of the display area and placing a camera below the hole area to reduce the area occupied by the camera, thereby increasing the screen-to-body ratio. However, the above technologies require digging out part of the display area, which will cause part of the display image to be unable to be displayed, and the screen-to-body ratio cannot be further increased. In order to avoid punching holes in the display area and to make a true full screen possible while ensuring the practicality of the display substrate, the pixel circuit external method or the pixel circuit internal method is usually adopted in the camera area under the screen.

[0093] The external pixel circuit method involves placing the pixel circuits connected to the light-emitting elements in the under-screen camera area within the normal display area. By separating the light-emitting elements and pixel circuits, the light transmittance of the under-screen camera area is improved. Since the under-screen camera area lacks pixel circuits, it lacks any other light-shielding layers besides the anodes of the light-emitting elements, resulting in higher light transmittance. However, with this method, the pixel circuits and light-emitting elements must be electrically connected via conductive wires. Limited by the space available for these wires, the size (e.g., aperture) of the under-screen camera area of ​​the display substrate using the external pixel circuit method is limited. For example, the external pixel circuit method is not suitable for under-screen camera areas with long, runway-shaped apertures. Furthermore, increasing the aperture of the under-screen camera area typically requires additional masking processes for the conductive wires, increasing costs. Furthermore, the conductive wires are typically made of transparent conductive materials such as indium tin oxide (ITO). Due to the high sheet resistance of ITO, the longer conductive wires carry a heavy load, which can easily affect the brightness of the light-emitting elements in the under-screen camera area, reducing the brightness of the under-screen camera area and causing display artifacts such as vertical mura.

[0094] The built-in pixel circuit method involves placing a light-emitting element and the pixel circuit connected to it in the under-screen camera area. Compared to the external pixel circuit method, the built-in method eliminates the need for long conductive wires to connect the pixel circuit and light-emitting element in the under-screen camera area, thus avoiding display issues in the under-screen camera area caused by these wires. Furthermore, the built-in method places no restrictions on the size of the under-screen camera area and can support under-screen camera areas with large apertures. However, in display substrates using the built-in pixel circuit method, the anode of the light-emitting element in the under-screen camera area cannot completely block the pixel circuit, thus affecting the light transmittance of the under-screen camera area.

[0095] This embodiment provides a display substrate and a display device, which can support increasing the size of the under-screen camera area while ensuring the light transmittance of the under-screen camera area.

[0096] This embodiment provides a display substrate, comprising: a first display area and a second display area located at least to one side of the first display area. The first display area comprises: a first sub-area and a second sub-area located at least to one side of the first sub-area proximal to the second display area. The first sub-area comprises: a plurality of display islands and a first light-transmitting area located between adjacent display islands. The display islands comprise: a plurality of first pixel circuits and a plurality of first light-emitting elements disposed on a substrate. The plurality of first pixel circuits and the plurality of first light-emitting elements are electrically connected; the orthographic projections of the first light-emitting elements and the first pixel circuits to which they are connected on the substrate at least partially overlap. The second sub-area comprises: a plurality of second light-emitting elements disposed on the substrate. The second display area comprises: at least a plurality of second pixel circuits disposed on the substrate. At least one of the plurality of second pixel circuits is electrically connected to at least one of the plurality of second light-emitting elements via a conductive connecting line. The spacing between the orthographic projection of the second light-emitting element on the substrate and the orthographic projection of the second pixel circuit to which the second light-emitting element is connected on the substrate is greater than zero. In other words, the orthographic projections of the second light-emitting element and the second pixel circuit to which it is connected on the substrate do not overlap.

[0097] The display substrate provided in this embodiment utilizes a combination of external and internal pixel circuits to ensure light transmittance in the first display area and support increased size. For example, this example can meet the design requirements of an under-screen camera area with a long hole runway design.

[0098] In some exemplary embodiments, a plurality of first pixel circuits in a display island area are connected to a plurality of first signal lines extending along a first direction and a plurality of second signal lines extending along a second direction. Within a first sub-area, a plurality of first signal lines of adjacent display island areas in the first direction are connected via a plurality of first island area connecting lines, and a plurality of second signal lines of adjacent display island areas in the second direction are connected via a plurality of second island area connecting lines. The first direction and the second direction may intersect, for example, the first direction may be perpendicular to the second direction. In this example, signal transmission along the first direction between first pixel circuits in adjacent display island areas is achieved through first island area connecting lines, and signal transmission along the second direction between first pixel circuits in adjacent display island areas is achieved through second island area connecting lines, thereby ensuring signal transmission in the first and second directions between adjacent display island areas.

[0099] In some exemplary embodiments, the conductive connecting lines include at least one routing layer, and the plurality of first island connecting lines, the plurality of second island connecting lines, and at least one routing layer of the conductive connecting lines may be co-layered and made of a transparent conductive material. In some examples, the conductive connecting lines may include a routing layer, and the plurality of first island connecting lines, the plurality of second island connecting lines, and the routing layer may be co-layered and made of a transparent conductive material. In this example, by placing the plurality of first island connecting lines, the plurality of second island connecting lines, and the conductive connecting lines in the same transparent conductive layer, the number of transparent conductive layers can be reduced, which helps reduce costs. However, this embodiment is not limited to this. In other examples, the conductive connecting lines may include multiple routing layers made of transparent conductive material, and the plurality of first island connecting lines and the plurality of second island connecting lines may be co-layered with one of the routing layers; alternatively, a portion of the first island connecting lines and a portion of the second island connecting lines may be co-layered with one of the routing layers, while another portion of the first island connecting lines and another portion of the second island connecting lines may be co-layered with another routing layer. In this example, a plurality of first island area connecting lines and a plurality of second island area connecting lines are made of transparent conductive material, which can help improve the light transmittance of the first display area.

[0100] In some exemplary embodiments, the plurality of first island area connection lines, the plurality of second island area connection lines, and the conductive connection lines can all be made of metal. In some examples, the plurality of first island area connection lines, the plurality of second island area connection lines, and the conductive connection lines can be located in different metal layers, or can be located in the same metal layer. In this example, by disposing the plurality of first island area connection lines, the plurality of second island area connection lines, and the conductive connection lines in the metal conductive layer, the number of transparent conductive layers can be reduced, which helps to reduce costs.

[0101] In some exemplary embodiments, the plurality of first island area connection lines and the plurality of second island area connection lines may be made of metal material, and the conductive connection lines may be made of transparent conductive material. In some examples, the first island area connection lines and the first signal lines transmitting the same signal may be an integrated structure connected to each other, and the second island area connection lines and the second signal lines transmitting the same signal may be an integrated structure connected to each other. In other examples, the first island area connection lines and the first signal lines transmitting the same signal may be located in different metal conductive layers. In other examples, the second island area connection lines and the second signal lines transmitting the same signal may be located in different metal conductive layers. In this example, by setting the plurality of first island area connection lines and the plurality of second island area connection lines in the metal conductive layer and setting the conductive connection lines in the transparent conductive layer, the opening process of the first sub-area can be reduced.

[0102] In some exemplary embodiments, a plurality of first pixel circuits in the display island region may be connected to the same first power line. This example can reduce wiring in the display island region.

[0103] In some exemplary embodiments, multiple first pixel circuits in a display island region may be connected to the same first initial signal line and the same second initial signal line. Within the display island region, the first initial signal line, the second initial signal line, and the first power line extend in the same direction, and the first power line is located between the first initial signal line and the second initial signal line. This embodiment can reduce wiring in the display island region and reduce the crossing of signal lines.

[0104] In some exemplary embodiments, multiple first pixel circuits in the display island region may be connected to the same emission control line, with the emission control line extending in a direction that intersects the direction of the first power line. For example, the emission control line may include multiple emission control segments located on different conductive layers, and the emission control signal is transmitted through the connection of the multiple emission control segments. This embodiment can reduce wiring in the display island region and reduce the crossing of signal lines.

[0105] In some exemplary embodiments, the display island area may include four first pixel circuits, which may be arranged in a 2×2 array, and the active layers of the four first pixel circuits may be symmetrically arranged about a first midline of the four first pixel circuits in the first direction. The arrangement of this example is conducive to optimizing the layout of the first pixel circuits and increasing the area of ​​the first light-transmitting area. In other examples, the display island area may include three first pixel circuits, which are arranged sequentially along the first direction. By reducing the number of first pixel circuits in the display island area, this example can reduce the number of signal lines, thereby facilitating an increase in the area of ​​the first light-transmitting area.

[0106] In some exemplary embodiments, the display substrate may further include: a light-shielding layer located on a side of the first pixel circuit and the second pixel circuit close to the substrate. The light-shielding layer does not overlap with the orthographic projection of the first light-transmitting area on the substrate. The light-shielding layer includes at least: a first light-shielding block located in the display island area; the orthographic projection of the first light-shielding block on the substrate can cover the orthographic projection of the plurality of first pixel circuits in the display island area and the signal lines connected to the plurality of first pixel circuits on the substrate. In some examples, the first light-shielding blocks of adjacent display island areas are interconnected as an integral structure. In other examples, the first light-shielding blocks of adjacent display island areas can be independently provided. This example can help prevent diffraction by providing a light-shielding layer to shield the first pixel circuit and signal lines in the display island area. In some examples, the edge of the first light-shielding block close to the first light-transmitting area can be roughly arc-shaped. In this example, the edge of the first light-shielding block close to the first light-transmitting area can be roughly the same shape as the outer edge of the signal line in the display island area, thereby helping to increase the area of ​​the first light-transmitting area.

[0107] In some exemplary embodiments, the display substrate may further include: a light-emitting structure layer located on a side away from the substrate where the multiple first pixel circuits and the multiple second pixel circuits are located, and the light-emitting structure layer may include a cathode layer, and the cathode layer does not overlap with the orthographic projection of the first light-transmitting area on the substrate. The cathode layer may at least include: cathodes of multiple first light-emitting elements. The cathodes of the multiple first light-emitting elements in the display island area are an integrated structure connected to each other, and the orthographic projection of the cathodes of the multiple first light-emitting elements in the display island area on the substrate covers the multiple first pixel circuits in the display island area and the orthographic projection of the signal lines connected to the multiple first pixel circuits on the substrate. This example implements shielding of the first pixel circuits and signal lines in the display island area by graphically designing the cathode layer, which can help prevent diffraction.

[0108] The solution of this embodiment is illustrated below through some examples.

[0109] Figures 1A, 1B, and 1C are schematic diagrams of a display substrate according to at least one embodiment of the present disclosure. In some examples, the display substrate may include: a display area AA and a peripheral area (not shown) located outside the display area AA. The display area AA of the display substrate may include at least: a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. For example, as shown in Figure 1A, the second display area A2 may surround the first display area A1. The peripheral area may surround the second display area A2. However, this embodiment is not limited to this.

[0110] In some examples, the first display area A1 may be a light-transmitting display area, which may be used as an under-screen camera (FDC, Full Display With Camera) area or a face recognition function area (Face ID) under the screen. The second display area A2 may be referred to as a normal display area. The light transmittance of the first display area A1 may be greater than the light transmittance of the second display area A2. For example, the orthographic projection of a sensor (such as a camera or other hardware) on the display substrate may be located within the first display area A1 of the display substrate. In some examples, as shown in Figures 1A and 1B, the first display area A1 may be rectangular, and the size of the orthographic projection of a single sensor on the display substrate may be less than or equal to the size of the inscribed circle of the first display area A1, and the first display area A1 may cover the orthographic projection of multiple sensors on the display substrate. However, this embodiment is not limited to this. In other examples, as shown in Figure 1C, the first display area A1 may be circular, and the size of the orthographic projection of a single sensor on the display substrate may be less than or equal to the size of the first display area A1.

[0111] In some examples, as shown in FIG1A , the first display area A1 may be located in the top center of the display area AA. The second display area A2 may surround the first display area A1. However, this embodiment is not limited to this. For example, the second display area A2 may surround at least one side of the first display area A1. For example, as shown in FIG1B and FIG1C , the first display area A1 may be located in the upper left corner of the display area AA. In other examples, the first display area A1 may be located in other locations such as the lower left corner, lower right corner, or upper right corner of the display area AA.

[0112] In some examples, as shown in Figures 1A and 1B, the display area AA can be a rectangle, such as a rounded rectangle. The first display area A1 can be a rectangle, for example, it can be roughly a long strip extending along the first direction X. The length of the first display area A1 along the first direction X can be greater than the length along the second direction Y. The first direction X intersects the second direction Y, for example, the first direction X can be perpendicular to the second direction Y. However, this embodiment is not limited to this. For example, as shown in Figure 1C, the first display area A1 can be a circle. In other examples, the first display area A1 can be a semicircle, a pentagon, or other shapes.

[0113] In some examples, the display area AA may be provided with a plurality of sub-pixels. At least one sub-pixel may include a pixel circuit and a light-emitting element. The pixel circuit may be configured to drive the connected light-emitting element. For example, the pixel circuit may be configured to provide a driving current to drive the light-emitting element to emit light. The pixel circuit may include a plurality of transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0114] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, which may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The light-emitting color of the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0115] FIG2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit of this example may have a 7T1C structure and may include seven transistors (e.g., first to seventh transistors T1 to T7) and one capacitor (e.g., storage capacitor C). The pixel circuit may be electrically connected to a first scan line GL1, a second scan line GL2, a third scan line GL3, a fourth scan line GL4, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a data line DL, and a first power line VDD.

[0116] In some examples, the first transistor T1 may also be referred to as a first reset transistor, the second transistor T2 may also be referred to as a threshold compensation transistor, the third transistor T3 may also be referred to as a driving transistor, the fourth transistor T4 may also be referred to as a data writing transistor, the fifth transistor T5 may also be referred to as a first emission control transistor, the sixth transistor T6 may also be referred to as a second emission control transistor, and the seventh transistor T7 may also be referred to as a second reset transistor. The light-emitting device EL may be an organic electroluminescent diode (OLED), including a stacked first electrode (e.g., an anode), an organic light-emitting layer, and a second electrode (e.g., a cathode).

[0117] In some examples, the third transistor T3 to the seventh transistor T7 may be first-type transistors, for example, P-type transistors; and the first transistor T1 and the second transistor T2 may be second-type transistors, for example, N-type transistors. However, this embodiment is not limited to this. In other examples, the first transistor T1 to the seventh transistor T7 may all be P-type transistors, or may all be N-type transistors.

[0118] In some examples, the first type of transistor of the pixel circuit (for example, including the third transistor T3 to the seventh transistor T7) can be a low-temperature polysilicon thin film transistor, and the second type of transistor of the pixel circuit (for example, including the first transistor T1 and the second transistor T2) can be an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, while oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0119] In some examples, the first end of the storage capacitor C is connected to the first node N1, that is, the first end of the storage capacitor C is connected to the control electrode of the third transistor T3, and the second end of the storage capacitor C is connected to the first power line VDD.

[0120] In some examples, a gate electrode of the first transistor T1 is connected to the third scan line GL3, a first electrode of the first transistor T1 is connected to the first initialization signal line INIT1, and a second electrode of the first transistor T1 is connected to the first node N1. When an on-level scan signal is applied to the third scan line GL3, the first transistor T1 transmits a first initialization voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.

[0121] In some examples, the gate electrode of the second transistor T2 is connected to the fourth scan line GL4, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the first node N1. When an on-level scan signal is applied to the fourth scan line GL4, the second transistor T2 connects the gate electrode of the third transistor T3 to the second electrode.

[0122] In some examples, the gate of the third transistor T3 is connected to the first node N1, that is, the gate of the third transistor T3 is connected to the first end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a drive transistor (DTFT). The third transistor T3 determines the amount of drive current flowing between the first power line VDD and the second power line VSS based on the potential difference between the gate and the first electrode. The first power line VDD can be configured to transmit a first voltage signal, and the second power line VSS can be configured to transmit a second voltage signal. The first voltage signal can be greater than the second voltage signal.

[0123] In some examples, a gate electrode of the fourth transistor T4 is connected to the first scan line GL1, a first electrode of the fourth transistor T4 is connected to the data line DL, and a second electrode of the fourth transistor T4 is connected to the second node N2. The fourth transistor T4 can be referred to as a data write transistor. When an on-level scan signal is applied to the first scan line GL1, the fourth transistor T4 inputs a data voltage of the data line DL to the pixel circuit.

[0124] In some examples, the gate of the fifth transistor T5 is connected to the emission control line EML, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The gate of the sixth transistor T6 is connected to the emission control line EML, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When an on-level light-emitting signal is applied to the light-emitting control line EML, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power line VDD and the second power line VSS, causing the light-emitting device to emit light.

[0125] In some examples, a gate electrode of the seventh transistor T7 is connected to the second scan line GL2, a first electrode of the seventh transistor T7 is connected to the second initialization signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4. When an on-level scan signal is applied to the second scan line GL2, the seventh transistor T7 transmits a second initialization voltage to the first electrode of the light-emitting device to initialize or release the charge accumulated in the first electrode of the light-emitting device.

[0126] In some examples, the second electrode of the light-emitting device EL is connected to a second power line VSS, the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a high-level signal. The first scan line GL1 is a scan line in the pixel circuit of the current display row, and the second scan line GL2 can be a scan line in the pixel circuit of the previous display row. That is, for the nth display row, the first scan line GL1 is GL(n), and the second scan line GL2 is GL(n-1). The second scan line GL2 of the current display row and the first scan line GL1 in the pixel circuit of the previous display row can be the same signal line, thereby reducing the number of signal lines of the display panel and achieving a narrow bezel of the display panel.

[0127] In some examples, as shown in FIG2 , the first node N1 can be connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2, the gate of the third transistor T3, and the first end of the storage capacitor C, respectively. The second node N2 can be connected to the second electrode of the fifth transistor T5, the second electrode of the fourth transistor T4, and the first electrode of the third transistor T3, respectively. The third node N3 can be connected to the second electrode of the third transistor T3, the first electrode of the second transistor T2, and the first electrode of the sixth transistor T6, respectively. The fourth node N4 can be connected to the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7, and the first electrode of the light-emitting device EL, respectively.

[0128] In other examples, the pixel circuit of this embodiment may be an 8T1C structure, which may include eight transistors (e.g., a first transistor to an eighth transistor) and a capacitor. The eighth transistor may also be referred to as a third reset transistor. The gate of the eighth transistor may be connected to the second scan line, the first electrode of the eighth transistor may be connected to the third initial signal line, and the second electrode of the eighth transistor may be connected to the second node. When the conduction level scan signal is applied to the second scan line, the eighth transistor may transfer the third initialization voltage provided by the third initial signal line to the second node to initialize the second node. Among them, the eighth transistor may be a first type transistor, for example, a P-type transistor. The description of the first transistor to the seventh transistor and the capacitor of the pixel circuit can refer to the corresponding description of Figure 2, so it will not be repeated here.

[0129] In some examples, the operation process of the pixel circuit of this example may include the following stages: Here, the first transistor T1 and the second transistor T2 are N-type transistors, and the third transistor T3 to the seventh transistor T7 are P-type transistors.

[0130] The first phase is called the reset phase. The signals on the first scan line GL1, the third scan line GL3, and the emission control line EML are high-level signals, while the signals on the second scan line GL2 and the fourth scan line GL4 are low-level signals. The signal on the third scan line GL3 is high, turning on the first transistor T1. The signal on the first initial signal line INIT1 is supplied to the first node N1, initializing the storage capacitor C and clearing the existing data voltage in the storage capacitor C. The signal on the second scan line GL2 is low, turning on the seventh transistor T7. Turning on the seventh transistor T7 allows the initial voltage on the second initial signal line INIT2 to be supplied to the first electrode of the light-emitting device EL, initializing (resetting) the first electrode of the light-emitting device EL and clearing the pre-stored voltage therein, completing initialization. The signals on the first scan line GL1 and the emission control line EML are high-level signals, turning off the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. The signal on the fourth scan line GL4 is low, turning off the second transistor T2. During this phase, the light-emitting device EL does not emit light.

[0131] The second stage is called the data writing stage or the threshold compensation stage. The signals of the first scan line GL1 and the third scan line GL3 are low-level signals, the signals of the second scan line GL2, the fourth scan line GL4 and the emission control line EML are high-level signals, and the data line DL outputs the data voltage.

[0132] During this phase, since the first end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The signal on the first scan line GL1 is a low level signal, turning on the fourth transistor T4. The signal on the fourth scan line GL4 is a high level signal, turning on the second transistor T2. The second and fourth transistors T2 and T4 are turned on, allowing the data voltage output by the data line DL to be supplied to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data line DL and the threshold voltage of the third transistor T3 is then charged into the storage capacitor C. The voltage at the first end (first node N1) of the storage capacitor C is Vd - |Vth|, where Vd is the data voltage output by the data line DL and Vth is the threshold voltage of the third transistor T3. The signal on the second scan line GL2 is a high level signal, turning off the seventh transistor T7. The signal on the third scan line GL3 is a low level signal, turning off the first transistor T1. The signal on the emission control line EML is a high level signal, turning off the fifth and sixth transistors T5 and T6.

[0133] The third phase is called the light-emitting phase. The signal on the emission control line EML is low, the signals on the first and second scan lines GL1 and GL2 are high, and the signals on the third and fourth scan lines GL3 and GL4 are low. The low signal on the emission control line EML turns on the fifth and sixth transistors T5 and T6. The power supply voltage from the first power line VDD provides a driving voltage to the first electrode of the light-emitting device EL through the turned-on fifth, third, and sixth transistors T5, T3, and T6, driving the light-emitting device EL to emit light.

[0134] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is: I=K×(Vgs-Vth) 2 =K×[(Vdd-Vd+|Vth|)-Vth] 2 =K×[Vdd-Vd] 2 ;

[0135] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting device EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data line DL, and Vdd is the power supply voltage output by the first power line VDD.

[0136] From the above equation, it can be seen that the current flowing through the light emitting element is independent of the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can better compensate for the threshold voltage of the third transistor T3.

[0137] Figure 3 is a partial schematic diagram of a display area according to at least one embodiment of the present disclosure. Figure 4 is a partial schematic diagram of a first display area according to at least one embodiment of the present disclosure.

[0138] In some examples, as shown in FIG3 , the first display area A1 may include a first sub-area A11 and two second sub-areas A12a and A12b. The second sub-areas A12a and A12b may be located on opposite sides of the first sub-area A11 near the second display area A2. The first sub-area A11 may be located between the two second sub-areas A12a and A12b in the first direction X. The second sub-area A12a may be located between the first sub-area A11 and the second display area A2 on the left, and the second sub-area A12b may be located between the first sub-area A11 and the second display area A2 on the right. In the second direction Y, the first sub-area A11 and the second sub-areas A12a and A12b may be directly adjacent to the second display area A2. However, this embodiment is not limited to this. In other examples, the second sub-area may be located on one side or on opposite sides of the first sub-area in the second direction Y; alternatively, the second sub-area may be located between the first sub-area and the second display area in both the first direction X and the second direction Y.

[0139] In some examples, the area of ​​the first sub-area A11 may occupy one-third to two-thirds of the total area of ​​the first display area A1. For example, the areas of the first sub-area A11, the second sub-area A12a, and the second sub-area A12b may be approximately the same; the area of ​​the first sub-area A11 may occupy one-third of the total area of ​​the first display area A1, the area of ​​the second sub-area A12a may occupy one-third of the total area of ​​the first display area A1, and the area of ​​the second sub-area A12b may occupy one-third of the total area of ​​the first display area A1. However, this embodiment is not limited to this. In other examples, the area of ​​the first sub-area A11 may be greater than the area of ​​a single second sub-area, or the area of ​​the first sub-area may be greater than or equal to the total area of ​​multiple second sub-areas.

[0140] In some examples, the first sub-area A11 may include: a plurality of display island areas A111 arranged in an array. Each display island area A111 may be configured to display an image. The plurality of display island areas A111 may be arranged in an array along a first direction X and a second direction Y. The plurality of display island areas A111 arranged along the first direction X may be referred to as a row of display island areas, and the plurality of display island areas A111 arranged along the second direction Y may be referred to as a column of display island areas. FIG3 illustrates two columns and three rows of display island areas within the first sub-area A11 as an example. This embodiment does not limit the number of display island areas A111 within the first sub-area A11.

[0141] In some examples, in a plane parallel to the display substrate, the shapes of multiple display island areas A111 can be roughly the same. For example, the display island area A111 can be roughly elliptical, or can be other shapes without right-angled sides, so as to set a sufficient light-emitting area to ensure the display effect. The display island area A111 can have smooth edges, thereby reducing the diffraction effect of light to help improve the shooting effect. A first light-transmitting area can be provided between adjacent display island areas A111, and the first light-transmitting area can be configured to provide a light transmission space. For example, the multiple first light-transmitting areas of the first sub-area A11 can be interconnected. However, this embodiment is not limited to this. In other examples, the multiple first light-transmitting areas of the first sub-area A11 can be independent of each other and not connected.

[0142] In some examples, as shown in Figures 3 and 4, the display island area A111 may include: a plurality of first pixel circuits 11 and a plurality of first light-emitting elements 15 (for example, four first pixel circuits 11 and four first light-emitting elements 15). At least one first pixel circuit 11 is electrically connected to at least one first light-emitting element 15, and at least one first pixel circuit 11 can be configured to drive the at least one first light-emitting element 15 connected thereto to emit light. The first light-emitting element 15 and the orthographic projection of the connected first pixel circuit 11 on the substrate may at least partially overlap. For example, a plurality of first pixel circuits 11 and a plurality of first light-emitting elements 15 can be electrically connected in a one-to-one correspondence. However, this embodiment is not limited to this. In other examples, a first pixel circuit 11 can be connected to a plurality of first light-emitting elements 15 and configured to drive the plurality of first light-emitting elements 15 connected thereto to emit light.

[0143] In some examples, one display island A111 may be provided with one first pixel unit, one first pixel unit may include four first sub-pixels, and each first sub-pixel may include one first pixel circuit 11 and one first light-emitting element 15. In other examples, one first pixel unit may include three first sub-pixels. This embodiment is not limited to this.

[0144] In some examples, the second sub-areas A12a and A12b may include: a plurality of second light-emitting elements 16. FIG3 illustrates two columns of second light-emitting elements 16 within the second sub-areas A12a and A12b as an example. This embodiment is not limited to this. For example, each second sub-area may include at least one column of second light-emitting elements.

[0145] In some examples, the second display area A2 may include: a plurality of second pixel circuits 12, a plurality of third pixel circuits 13 and a plurality of third light-emitting elements (not shown). At least one second pixel circuit 12 may be electrically connected to at least one second light-emitting element 16 in the second sub-area A12a or A12b through a conductive connecting line 53, and configured to drive the at least one second light-emitting element 16 connected thereto to emit light. The second light-emitting element 16 may not overlap with the orthographic projection of the connected second pixel circuit 12 on the substrate. For example, the plurality of second pixel circuits 12 of the second display area A2 and the plurality of second light-emitting elements 16 of the second sub-areas A12a and A12b may be electrically connected in a one-to-one correspondence. However, this embodiment is not limited to this. In other examples, the second pixel circuit 12 and the second light-emitting element 16 may be in a one-to-many relationship.

[0146] In some examples, the conductive connection line 53 may extend at least along the first direction X. The conductive connection line 53 may be made of a transparent conductive material, such as indium tin oxide (ITO), or a metal material, which is not limited in this embodiment.

[0147] In some examples, at least one third pixel circuit 13 of the second display area A2 is electrically connected to at least one third light-emitting element and is configured to drive the at least one third light-emitting element connected thereto to emit light. The orthographic projection of the third light-emitting element and the connected third pixel circuit 13 on the substrate may at least partially overlap. For example, the plurality of third pixel circuits 13 and the plurality of third light-emitting elements of the second display area A2 may be electrically connected in a one-to-one correspondence. However, this embodiment is not limited to this. In other examples, the third pixel circuit 13 and the third light-emitting element may be in a one-to-many relationship.

[0148] In some examples, within the second display area A2, a plurality of second pixel circuits 12 may be arranged between a plurality of third pixel circuits 13. For example, in the first direction X, a second pixel circuit 12 may be provided for every two third pixel circuits 13. However, this embodiment is not limited to this. In other examples, a second pixel circuit 12 may be provided for every four third pixel circuits 13.

[0149] In some examples, since only the second light-emitting elements 16 are provided in the second sub-areas A12a and A12b without pixel circuits, the gaps between adjacent second light-emitting elements 16 can form a second light-transmitting area, which helps improve the light transmittance of the first display area A1. For example, the second light-transmitting area in the second sub-areas A12a and A12b can be connected to the first light-transmitting area in the first sub-area A11. However, this embodiment is not limited to this.

[0150] In some examples, the arrangement of the second light-emitting elements 16 in the second sub-areas A12a and A12b can be the same as the arrangement of the third light-emitting elements in the second display area A2, so that the display effects at the intersection of the second sub-areas A12a and A12b and the second display area A2 can be consistent. The arrangement of the second light-emitting elements 16 in the second sub-areas A12a and A12b can be different from the arrangement of the first light-emitting elements 15 in the first sub-area A11. For example, the first light-emitting elements 15 in the first sub-area A11 can be arranged in an island shape to increase the area of ​​the first light-transmitting area.

[0151] In some examples, the light-emitting areas of the second light-emitting element 16 and the third light-emitting element emitting light of the same color can be approximately the same. The light-emitting area of ​​the second light-emitting element 16 emitting light of the same color can be larger than the light-emitting area of ​​the first light-emitting element 15. In this example, the light-emitting area of ​​a light-emitting element can refer to the overlapping area of ​​the anode of the light-emitting element exposed by the pixel definition layer and the organic light-emitting layer and cathode. The configuration of this example can help ensure the consistency of the display effect at the intersection of the first display area A1 and the second display area A2, and help improve the light transmittance of the first display area A1.

[0152] In some examples, the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13 within the display area AA can all be connected to a plurality of first signal lines 54 extending along the first direction X and a plurality of second signal lines 55 extending along the second direction Y. For example, the plurality of first signal lines 54 can include: a first scan line, a second scan line, a third scan line, a fourth scan line, and a light-emitting control line; and the plurality of second signal lines 55 can include: a first power line, a data line, a first initial signal line, and a second initial signal line. This embodiment is not limited to this. In other examples, the first initial signal line and the second initial signal line can be arranged to extend along the first direction X.

[0153] In some examples, within the first sub-area A11, multiple first signal lines 54 of adjacent display islands A111 in the first direction X can be connected by multiple first island connection lines 51; multiple second signal lines 55 of adjacent display islands A111 in the second direction Y can be connected by multiple second island connection lines 52. In some examples, multiple first island connection lines 51 can be located in the first routing area between adjacent display islands A111, and multiple second island connection lines 52 can be located in the second routing area between adjacent display islands A111. For example, taking the example of routing lines made of metal materials in the first routing area and the second routing area, the first light-transmitting area of ​​the first display area A1 can be independently set, and a first light-transmitting area can be formed by four display islands A111 arranged in a 2×2 array, two first routing areas adjacent along the second direction Y, and two second routing areas adjacent along the first direction X. This embodiment is not limited to this. In other examples, the first routing area and the second routing area may be provided with routings made of transparent conductive material, so that the first routing area and the second routing area can connect to the adjacent first light-transmitting area, thereby improving the light transmittance of the first display area.

[0154] In some examples, the multiple first signal lines 54 connected to the third pixel circuit 13 of the second display area A2 can directly pass through the second sub-areas A12a and A12b to extend to connect to the first pixel circuit 11 in the first sub-area A11. The multiple second signal lines 55 connected to the third pixel circuit 13 of the second display area A2 can directly extend to the first sub-area A11 and connect to the first pixel circuit 11 of the first sub-area A11. However, this embodiment is not limited to this. In other examples, the multiple first signal lines 54 connected to the third pixel circuit 13 of the second display area A2 can be connected to the first pixel circuit 11 of the first sub-area A11 through multiple first island area connecting lines 51 provided in the second sub-areas A12a and A12b. In other examples, the multiple second signal lines 55 connected to the third pixel circuit 13 of the second display area A2 can be connected to the first pixel circuit 11 of the first sub-area A11 through multiple second island area connecting lines 52.

[0155] In some examples, the multiple first island area connection lines 51 and the multiple second island area connection lines 52 can be made of a transparent conductive material. For example, the multiple first island area connection lines 51, the multiple second island area connection lines 52, and the conductive connection lines 53 can be a co-layer structure. In this example, by providing a transparent conductive layer to arrange the multiple first island area connection lines 51, the multiple second island area connection lines 52, and the conductive connection lines 53, the number of transparent conductive layers can be reduced, which is conducive to reducing costs. However, this embodiment is not limited to this. In other examples, the multiple first island area connection lines 51 and the multiple second island area connection lines 52 can be made of a metal material.

[0156] In some examples, the light-emitting element density of the second display area A2 can be substantially the same as the light-emitting element density of the second sub-area A12a (or A12b). The light-emitting element density of the first sub-area A11 can be substantially the same as the light-emitting element density of the second sub-area A12a (or A12b). The arrangement of this example is conducive to display uniformity of the display area. The light-emitting element density in this example can refer to the number of light-emitting elements arranged per unit area.

[0157] In this example, the first sub-area A11 of the first display area A1 adopts a built-in pixel circuit method, and the second sub-areas A12a and A12b adopt an external pixel circuit method. This can improve the low transmittance that exists when only the built-in pixel circuit method is used, and the limited size of the first display area that exists when only the external pixel circuit method is used, thereby ensuring the light transmittance of the first display area A1 and supporting the increase in the size of the first display area A1.

[0158] Figure 5 is a partial schematic diagram of the display island area of ​​at least one embodiment of the present disclosure. In some examples, the display island area may include four first pixel circuits (for example, including first pixel circuits 11a, 11b, 11c and 11d), and four first light-emitting elements (for example, including first light-emitting elements 15a, 15b, 15c and 15d). The four first pixel circuits 11a, 11b, 11c and 11d can be arranged in a 2×2 array. The first pixel circuit 11a can be connected to the first light-emitting element 15a, the first pixel circuit 11b can be connected to the first light-emitting element 15b, the first pixel circuit 11c can be connected to the first light-emitting element 15c, and the first pixel circuit 11d can be connected to the first light-emitting element 11d. For example, the first light-emitting element 15a can be configured to emit red light, the first light-emitting element 15c can be configured to emit blue light, and the first light-emitting elements 15b and 15d can be configured to emit green light. The first light-emitting element 15a emitting red light and the first light-emitting element 15c emitting blue light can be arranged in the same column along the second direction Y, the first light-emitting elements 15b and 15d emitting green light can be arranged in the same column along the second direction Y, the first light-emitting element 15a emitting red light and the first light-emitting element 15b emitting green light can be arranged in the same row, and the first light-emitting element 15c emitting blue light and the first light-emitting element 15d emitting green light can be arranged in the same row.

[0159] In some examples, the four first pixel circuits can be connected to a plurality of first signal lines 54 extending along the first direction X, and the plurality of first signal lines 54 can be connected to a plurality of first island area connection lines 51, thereby enabling signal transmission within the first sub-area A1 along the first direction X. The four first pixel circuits can be connected to a plurality of second signal lines (e.g., including the first power line 41 and the data lines 50a and 50b) extending along the second direction Y, and the plurality of second signal lines can be connected to a plurality of second island area connection lines 52, thereby enabling signal transmission within the first sub-area A1 along the second direction Y. For example, the four first pixel circuits in the display island area can be connected to the same first power line 41, thereby reducing signal line crossing and facilitating wiring design of the display island area.

[0160] In some examples, the plurality of first signal lines and the plurality of first island area connection lines 51 may be located in different film layers, and the plurality of second signal lines and the plurality of second island area connection lines may be located in different film layers. For example, the plurality of first signal lines and the plurality of second signal lines may be made of metal materials, and the plurality of first island area connection lines 51 and the plurality of second island area connection lines may be made of transparent conductive materials. This embodiment is not limited to this.

[0161] Figure 6A is a partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 6A , in a direction perpendicular to the display substrate, the display substrate may include: a substrate 60, and a circuit structure layer, a conductive connection layer, and a light-emitting structure layer disposed on the substrate 60. The light-emitting structure layer may be located on a side of the circuit structure layer away from the substrate 60, and the conductive connection layer may be located between the circuit structure layer and the light-emitting structure layer. The circuit structure layer of the first display area A1 may include: a plurality of first pixel circuits 11; the light-emitting structure layer of the first display area A1 may include: a plurality of first light-emitting elements 15 and a plurality of second light-emitting elements 16. The circuit structure layer of the second display area A2 may include at least: a plurality of second pixel circuits 12. Figure 6A illustrates a first pixel circuit 11 and a first light-emitting element 15 in the first sub-area A11 of the first display area A1, and a second light-emitting element 16 in the second sub-area A12a. A first-type transistor, a second-type transistor, and a storage capacitor in the first pixel circuit 11 are illustrated, as well as a first-type transistor and a storage capacitor in the second pixel circuit 12.

[0162] In some examples, the circuit structure layer may include: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed on a substrate 60. A first insulating layer 611 may be disposed between the first semiconductor layer and the first conductive layer, a second insulating layer 612 may be disposed between the first conductive layer and the second conductive layer, a third insulating layer 613 may be disposed between the second conductive layer and the second semiconductor layer, a fourth insulating layer 614 may be disposed between the second semiconductor layer and the third conductive layer, a fifth insulating layer 615 may be disposed between the third conductive layer and the fourth conductive layer, a sixth insulating layer 616 may be disposed between the fourth conductive layer and the fifth conductive layer, and a seventh insulating layer 617 may be disposed on the side of the fifth conductive layer away from the substrate 60. In some examples, the first to fourth insulating layers 611 to 614 may be inorganic insulating layers; the fifth insulating layer 615 may be an inorganic insulating layer, an organic insulating layer, or a stacked structure of inorganic and organic insulating layers; and the sixth to seventh insulating layers 616 to 617 may be organic insulating layers. However, this embodiment is not limited to this.

[0163] In some examples, the conductive connection layer can be provided on the seventh insulating layer 617. For example, the conductive connection layer can be made of a transparent conductive material (e.g., ITO), and the conductive connection layer can also be referred to as a transparent conductive layer. As shown in Figure 6A, the conductive connection layer can include a plurality of conductive connection lines 53, a plurality of first island area connection lines 51, and a plurality of second island area connection lines 52. The conductive connection lines 53 can extend from the second display area A2 to the second sub-area A12a of the first display area A1, thereby electrically connecting the second light-emitting element 16 in the second sub-area A12a and the second pixel circuit 12 in the second display area A2. By providing a plurality of first island area connection lines 51, a plurality of second island area connection lines 52, and a plurality of conductive connection lines 53 in the same conductive layer, a transparent conductive film layer can be saved, which is conducive to reducing costs. However, this embodiment is not limited to this. In other examples, the display substrate may include a plurality of conductive connection layers made of a transparent conductive material, at least one conductive connection line may be located in one of the conductive connection layers, or at least one conductive connection line may include a plurality of routing layers located in different conductive connection layers.

[0164] In some examples, the light-emitting structure layer may include: an anode layer, a pixel definition layer 621, an organic light-emitting layer, and a cathode layer sequentially arranged on the seventh insulating layer 617. The anode layer may include at least: an anode 151 of the first light-emitting element 15, and an anode 161 of the second light-emitting element 16. In a direction perpendicular to the display substrate, the anode layer may include a first transparent conductive layer (for example, made of ITO material), a metal layer (for example, including silver), and a second transparent conductive layer (for example, made of ITO material) stacked together. The first transparent conductive layer of the anode layer may be connected to the conductive connection layer. For example, the first transparent conductive layer of the anode 161 of the second light-emitting element 16 may be an integral structure connected to the conductive connection line 53. The anode 161 of the second light-emitting element 16 may be connected to the second pixel circuit 12 via the conductive connection line 53, and the anode 151 of the first light-emitting element 15 may be connected to the first pixel circuit 11. However, this embodiment is not limited to this. In other examples, an organic insulating layer may be provided between the anode layer and the conductive connection layer, and the anode layer may be connected to the conductive connection layer via a via provided in the organic insulating layer.

[0165] In some examples, the pixel definition layer 621 may have multiple pixel openings, and the pixel openings may expose a portion of the surface of the anode layer. The organic light-emitting layer 152 of the first light-emitting element 15 may be in direct contact with the anode 151 through the pixel openings, and the cathode 153 of the first light-emitting element 15 may be in direct contact with the organic light-emitting layer 152. The organic light-emitting layer 162 of the second light-emitting element 16 may be in direct contact with the anode 161 through the pixel openings, and the cathode 163 of the second light-emitting element 16 may be in direct contact with the organic light-emitting layer 162. The organic light-emitting layer of the light-emitting element can emit light of a corresponding color when driven by the anode layer and the cathode layer.

[0166] In some examples, an encapsulation structure layer may be further provided on the side of the light-emitting structure layer away from the substrate 60. For example, the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer may be provided between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer. In some possible implementations, the display substrate may further include other film layers, such as a touch structure layer, a color filter layer, etc., which are not limited in this embodiment.

[0167] Figure 6B is another partial cross-sectional schematic diagram of the display substrate of at least one embodiment of the present disclosure. In some examples, as shown in Figure 6B, the conductive connection layer can be made of a transparent conductive material (for example, ITO), and the conductive connection layer can include a plurality of conductive connection lines 53. The plurality of first island area connection lines 51 and the plurality of second island area connection lines 52 can be made of metal materials, for example, they can be located in the fifth conductive layer. However, this embodiment is not limited to this. In other examples, the plurality of first island area connection lines and the plurality of second island area connection lines can be located in the fourth conductive layer. In other examples, the plurality of first island area connection lines and the plurality of second island area connection lines can be located in different film layers, for example, the first island area connection line can be an integrated structure interconnected with the first signal line to which it is connected, and the second island area connection line can be an integrated structure interconnected with the second signal line to which it is connected. The rest of the description of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0168] Figure 6C is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 6C , the conductive connecting line 53 can be made of a metal material and, for example, can be located in the fifth conductive layer. The plurality of first island area connecting lines 51 and the plurality of second island area connecting lines 52 can be made of a metal material and, for example, can be located in the fifth conductive layer. However, this embodiment is not limited to this. For example, the conductive connecting lines can be located in a different metal film layer than the first island area connecting lines and the second island area connecting lines. The remaining description of the display substrate of this example can be referred to the description of the aforementioned embodiment and will not be repeated here.

[0169] Figure 6D is another partial cross-sectional schematic diagram of the display substrate of at least one embodiment of the present disclosure. In some examples, as shown in Figure 6D, the pixel definition layer may include: a first pixel definition layer 621a located in the first display area A1 and a second pixel definition layer 621b located in the second display area A2. The first pixel definition layer 621a can also be called a light-shielding pixel definition layer, for example, it can be a black pixel definition layer. The first pixel definition layer 621a in the first light-transmitting area and the second light-transmitting area in the first display area A1 can be removed to ensure the light transmittance of the light-transmitting area. The first pixel definition layer 621a can at least cover the first pixel circuit in the display island area, the metal traces connected to the first pixel circuit, and the peripheral portion of the light-emitting area of ​​the second light-emitting element 16 in the second sub-area. In this example, by setting the first pixel definition layer in the first display area, the metal film layer can be effectively shielded and diffraction can be reduced.

[0170] In some examples, as shown in FIG6D , the cathode layer of the first display area A1 can be graphically designed. The cathode layers of the first light-transmitting area and the second light-transmitting area of ​​the first display area A1 can be removed to ensure the light transmittance of the light-transmitting area. The cathodes 153 of the multiple first light-emitting elements 15 in the display island area of ​​the first sub-area A11 can be an integrated structure connected to each other. The cathode 153 of the first light-emitting element 15 can be connected to the cathode 163 of the second light-emitting element 16. The positive projection of the cathode layer of the first display area A1 on the substrate 60 can cover the positive projection of the first pixel definition layer 621a on the substrate 60. This example can use a graphically designed cathode layer to achieve a shading effect, effectively block the metal film layer, and reduce diffraction. The rest of the description of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0171] The structure of the display substrate is explained below by taking the example of the preparation process of the display substrate as an example. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0172] The terms "A and B are arranged in the same layer" and "A and B are in the same layer structure" mentioned in the present disclosure mean that A and B are formed simultaneously through the same patterning process, or the surfaces of A and B close to the substrate are at substantially the same distance from the substrate, or the surfaces of A and B close to the substrate are in direct contact with the same film layer. The "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The "shape of A" mentioned in the present disclosure refers to the shape of the orthographic projection of A on the substrate.

[0173] In some examples, the preparation process of the display substrate may include the following operations. The circuit structure layer of a display island A111 of the first sub-area A11 of the first display area A1 is used as an example for illustration, and the film layer structure is described using the structure of the first transistor 21, the second transistor 22, the third transistor 23, the fourth transistor 24, the fifth transistor 25, the sixth transistor 26, the seventh transistor 27, and the storage capacitor of the first pixel circuit 11a within the display island A111 as an example.

[0174] (1) Provide a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass and quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNy, y>0) or silicon oxide (SiOx, x>0), etc., to improve the substrate's resistance to water and oxygen.

[0175] (2) Forming a first semiconductor layer. In some examples, a first semiconductor thin film is deposited on a substrate, and the first semiconductor thin film is patterned by a patterning process to form a first semiconductor layer disposed on the substrate. In some examples, the first semiconductor layer can be made of amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene.

[0176] FIG7 is a schematic diagram of the first semiconductor layer of the display island region according to at least one embodiment of the present disclosure. In some examples, as shown in FIG7 , the first semiconductor layer of the display island region may include: active layers of a plurality of first-type transistors (e.g., active layers 230 of the third transistor, active layers 240 of the fourth transistor, active layers 250 of the fifth transistor, active layers 260 of the sixth transistor, and active layers 270 of the seventh transistor) of four first pixel circuits (e.g., first pixel circuits 11a, 11b, 11c, and 11d) of the first pixel circuits.

[0177] In some examples, the active layers of the multiple first-type transistors in each first pixel circuit can be interconnected and integrated. The active layers of the multiple first-type transistors in different first pixel circuits can be independent of each other. The first semiconductor layer patterns of the four first pixel circuits can be arranged in a 2×2 array. The first semiconductor layer patterns of the four first pixel circuits can be substantially symmetrical about the first center line O1. The extension direction of the first center line O1 can be parallel to the second direction Y.

[0178] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region located between the first region and the second region. The material of the first semiconductor layer may include, for example, polysilicon. The channel region may not be doped with impurities and have semiconductor properties. The first region and the second region may be doped regions on both sides of the channel region, and are doped with impurities and therefore have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as wiring doped with impurities, which can be used to electrically connect the transistors. This embodiment is not limited to this.

[0179] In some examples, the first semiconductor layer pattern of the first pixel circuit 11a is used as an example for description. The active layer 240 of the fourth transistor of the first pixel circuit 11a can be located on a side of the active layer 230 of the third transistor in the opposite direction of the second direction Y, and the active layer 250 of the fifth transistor, the active layer 260 of the sixth transistor, and the active layer 270 of the seventh transistor can be located on a side of the active layer 230 of the third transistor in the second direction Y. The active layer 250 of the fifth transistor and the active layer 240 of the fourth transistor can be located on a side of the active layer 230 of the third transistor in the opposite direction of the first direction X, and the active layer 260 of the sixth transistor and the active layer 270 of the seventh transistor can be located on a side of the active layer 230 of the third transistor in the first direction X. The first region of the active layer 230 of the third transistor can simultaneously serve as the second region of the active layer 250 of the fifth transistor and the second region of the active layer 240 of the fourth transistor. The second region of the active layer 230 of the third transistor can simultaneously serve as the first region of the active layer 260 of the sixth transistor. The second region of the active layer 260 of the sixth transistor can simultaneously serve as the second region of the active layer 270 of the seventh transistor.

[0180] In some examples, the active layer 230 of the third transistor may be shaped approximately like an I, the active layer 240 of the fourth transistor may be shaped approximately like a U, and the active layer 250 of the fifth transistor, the active layer 260 of the sixth transistor, and the active layer 270 of the seventh transistor may be shaped approximately like an L. This embodiment is not limited to this.

[0181] (3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate forming the aforementioned structure, and the first conductive film is patterned by a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer. In some examples, the first conductive layer may also be referred to as a first gate metal layer, and the first insulating layer may also be referred to as a first gate insulating layer.

[0182] Figure 8A is a schematic diagram of a display island region after forming a first conductive layer in at least one embodiment of the present disclosure. Figure 8B is a schematic diagram of the first conductive layer in Figure 8A.

[0183] In some examples, as shown in Figures 8A and 8B, the first conductive layer of the display island area may include at least: the first electrodes of the storage capacitors of the four first pixel circuits (for example, the first electrode 281), the first scan lines 31a and 31b, the second scan lines 32a and 32b, the first light-emitting control segments 291a and 291b, and the second light-emitting control segments 292a and 292b.

[0184] In some examples, within the display island area, the first scan line 31b, the second scan line 32b, the first scan line 31a, and the second scan line 32a can be arranged sequentially along the second direction Y. The shapes of the first scan lines 31a and 31b, and the second scan lines 32a and 32b can be roughly zigzag lines extending along the first direction X. The first scan line 31a can bypass the first electrodes of the storage capacitors of the first pixel circuits 11a and 11b on the side opposite to the second direction Y, and the second scan line 32a can bypass the first electrodes of the storage capacitors of the first pixel circuits 11a and 11b on the side opposite to the second direction Y. The first scan line 31b can bypass the first electrodes of the storage capacitors of the first pixel circuits 11c and 11d on the side opposite to the second direction Y, and the second scan line 32b can bypass the first electrodes of the storage capacitors of the first pixel circuits 11c and 11d on the side opposite to the second direction Y.

[0185] In some examples, the overlapping region of the first scan line 31a with the active layer of the fourth transistor 24 of the first pixel circuit 11a can serve as the gate of the fourth transistor 24 of the first pixel circuit 11a, and the overlapping region of the first scan line 31b with the active layer of the fourth transistor of the first pixel circuit 11b can serve as the gate of the fourth transistor of the first pixel circuit 11b. The overlapping region of the first scan line 31b with the active layer of the fourth transistor of the first pixel circuit 11c can serve as the gate of the fourth transistor of the first pixel circuit 11c, and the overlapping region of the first scan line 31b with the active layer of the fourth transistor of the first pixel circuit 11d can serve as the gate of the fourth transistor of the first pixel circuit 11d. For example, the fourth transistor of the first pixel circuit can be a dual-gate transistor.

[0186] In some examples, the overlapping region of the second scan line 32a with the active layer of the seventh transistor 27 of the first pixel circuit 11a can serve as the gate of the seventh transistor 27 of the first pixel circuit 11a, and the overlapping region of the second scan line 32b with the active layer of the seventh transistor of the first pixel circuit 11b can serve as the gate of the seventh transistor of the first pixel circuit 11b. The overlapping region of the second scan line 32b with the active layer of the seventh transistor of the first pixel circuit 11c can serve as the gate of the seventh transistor of the first pixel circuit 11c, and the overlapping region of the second scan line 32b with the active layer of the seventh transistor of the first pixel circuit 11d can serve as the gate of the seventh transistor of the first pixel circuit 11d.

[0187] In some examples, the first light-emitting control segments 291a and 291b and the second light-emitting control segments 292a and 292b can be substantially linear and extend along the first direction X. The first light-emitting control segment 291a can be located on one side of the first electrode 281 of the storage capacitor of the first pixel circuits 11a and 11b in the second direction Y, and on a side of the second scan line 32a opposite to the second direction Y. The first light-emitting control segment 291b can be located on one side of the first electrode of the storage capacitor of the first pixel circuits 11c and 11d in the second direction Y, and on a side of the second scan line 32b opposite to the second direction Y. The second light-emitting control segment 292a can be located on one side of the first pixel circuit 11a opposite to the first direction X, and the second light-emitting control segment 292b can be located on one side of the first pixel circuit 11b in the first direction X. The second light-emitting control segments 292a and 292b can be aligned in the first direction X.

[0188] In some examples, the overlapping area of ​​the first light-emitting control segment 291a with the active layer of the fifth transistor 25 of the first pixel circuit 11a can serve as the gate of the fifth transistor 25 of the first pixel circuit 11a, the overlapping area with the active layer of the sixth transistor 26 of the first pixel circuit 11a can serve as the gate of the sixth transistor 26 of the first pixel circuit 11a, the overlapping area with the active layer of the fifth transistor of the first pixel circuit 11b can serve as the gate of the fifth transistor of the first pixel circuit 11b, and the overlapping area with the active layer of the sixth transistor of the first pixel circuit 11b can serve as the gate of the sixth transistor of the first pixel circuit 11b. The overlapping area of ​​the first light-emitting control segment 291b with the active layer of the fifth transistor of the first pixel circuit 11c can serve as the gate of the fifth transistor of the first pixel circuit 11c, the overlapping area with the active layer of the sixth transistor of the first pixel circuit 11c can serve as the gate of the sixth transistor of the first pixel circuit 11c, the overlapping area with the active layer of the fifth transistor of the first pixel circuit 11d can serve as the gate of the fifth transistor of the first pixel circuit 11d, and the overlapping area with the active layer of the sixth transistor of the first pixel circuit 11d can serve as the gate of the sixth transistor of the first pixel circuit 11d.

[0189] In some examples, the shape of the first electrode 281 of the storage capacitor of the first pixel circuit 11 a may be substantially rectangular. The first electrode 281 of the storage capacitor of the first pixel circuit 11 a may also serve as the gate of the third transistor 23 .

[0190] (4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate forming the aforementioned structure. The second conductive film is patterned by a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer. In some examples, the second conductive layer may also be referred to as a second gate metal layer, and the second insulating layer may also be referred to as a second gate insulating layer.

[0191] Figure 9A is a schematic diagram of a display island region after forming a second conductive layer in at least one embodiment of the present disclosure. Figure 9B is a schematic diagram of the second conductive layer in Figure 9A.

[0192] In some examples, as shown in Figures 9A and 9B, the second conductive layer of the display island area may include at least: first scanning auxiliary lines 35a and 35b, second scanning auxiliary lines 36a and 36b, second electrodes of the storage capacitors of the four first pixel circuits (for example, the second electrode 282), first initial connection segments 293a and 293b, and second initial connection segments 294a and 294b.

[0193] In some examples, the shape of the second electrode 282 of the storage capacitor of the first pixel circuit 11a can be roughly rectangular, for example, the rectangle can have rounded corners or chamfered corners. The second electrode 282 can have a hollow area 283, and the shape of the hollow area 283 can be roughly rectangular, for example, a rounded rectangle. The orthographic projection of the hollow area 283 on the substrate can be located within the orthographic projection range of the first electrode 281 on the substrate. The shapes of the second electrodes of the storage capacitors of the other first pixel circuits are similar, so they are not further described here.

[0194] In some examples, the second electrode 282 of the storage capacitor of the first pixel circuit 11a and the second electrode of the storage capacitor of the first pixel circuit 11b can be connected through a plate connection block 282-1. The shape of the plate connection block 282-1 can be roughly a strip extending along the first direction X. The length of the plate connection block 282-1 along the second direction Y can be less than the length of the second electrode 282 along the second direction Y. The second electrode 282 of the storage capacitor of the first pixel circuit 11a, the second electrode of the storage capacitor of the first pixel circuit 11b, and the plate connection block 282-1 can be an integrated structure connected to each other. The second electrode of the storage capacitor of the first pixel circuit 11c and the second electrode of the storage capacitor of the first pixel circuit 11d can be connected through another plate connection block. The second electrode of the storage capacitor of the first pixel circuit 11c, the second electrode of the storage capacitor of the first pixel circuit 11d, and the plate connection block can be an integrated structure connected to each other.

[0195] In some examples, the shape of the first scan auxiliary lines 35a and 35b can be roughly a zigzag shape extending along the first direction X. The orthographic projection of the first scan auxiliary line 35a on the substrate can be located between the orthographic projections of the first scan line 31a and the second scan line 32b on the substrate. The orthographic projection of the first scan auxiliary line 35b on the substrate can be located on the side opposite to the orthographic projection of the first scan line 31b on the substrate in the second direction Y. The orthographic projections of the first scan auxiliary lines 35a and 35b on the substrate can not overlap with the orthographic projections of the first semiconductor layers of the four first pixel circuits on the substrate. The first scan auxiliary line 35a can bypass the second electrodes of the storage capacitors of the first pixel circuits 11a and 11b on the side opposite to the second direction Y, and the first scan auxiliary line 35b can bypass the second electrodes of the storage capacitors of the first pixel circuits 11c and 11d on the side opposite to the second direction Y.

[0196] In some examples, the second scan auxiliary lines 36a and 36b can be shaped roughly like a zigzag line extending along the first direction X. The orthographic projection of the second scan auxiliary line 36a on the substrate can be located on one side of the orthographic projection of the first scan line 31a on the substrate along the second direction Y. The orthographic projection of the second scan auxiliary line 36b on the substrate can be located within the range of the orthographic projections of the second scan line 32b and the first scan line 31b on the substrate. The second scan auxiliary line 36a can bypass the second electrodes of the storage capacitors of the first pixel circuits 11a and 11b on the side opposite to the second direction Y, and the second scan auxiliary line 36b can bypass the second electrodes of the storage capacitors of the first pixel circuits 11c and 11d on the side opposite to the second direction Y.

[0197] In some examples, the first initial connection segments 293a and 293b may be shaped substantially like strips extending along the first direction X. The first initial connection segment 293a may be located on a side of the first scanning auxiliary line 35a opposite to the second direction Y. The first initial connection segment 293b may be located on a side of the first scanning auxiliary line 35b opposite to the second direction Y.

[0198] In some examples, the first initial connection section 293a may be provided with two first initial connection blocks 293-1a on a side close to the first scanning auxiliary line 35a, and the two first initial connection blocks 293-1a are arranged at intervals along the first direction X. The first initial connection section 293a and the two first initial connection blocks 293-1a may be an integrated structure connected to each other. The first initial connection section 293b may be provided with two first initial connection blocks 293-1b on a side close to the first scanning auxiliary line 35b, and the two first initial connection blocks 293-1b are arranged at intervals along the first direction X. The first initial connection section 293b and the two first initial connection blocks 293-1b may be an integrated structure connected to each other.

[0199] In some examples, the second initial connection segments 294 a and 294 b may be shaped substantially like strips extending along the first direction X. The second initial connection segment 294 a may be located on one side of the second scan line 32 a in the second direction Y. The second initial connection segment 294 b may be located on a side of the first initial connection segment 293 a in the opposite direction of the second direction Y.

[0200] In some examples, the second initial connection section 294a may be provided with two second initial connection blocks 294-1a on a side close to the second scan line 32a, and the two second initial connection blocks 294-1a are arranged at intervals along the first direction X. The second initial connection section 294a and the two second initial connection blocks 294-1a may be an integrated structure connected to each other. The second initial connection section 294b may be provided with two second initial connection blocks 294-1b on a side close to the second scan line 32b, and the two second initial connection blocks 294-1b are arranged at intervals along the first direction X. The second initial connection section 294b and the two second initial connection blocks 294-1b may be an integrated structure connected to each other.

[0201] (5) Forming a second semiconductor layer. In some examples, a third insulating film and a second semiconductor film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The second semiconductor film is patterned by a patterning process to form a third insulating layer and a second semiconductor layer disposed on the third insulating layer. In some examples, the material of the second semiconductor layer may include indium gallium zinc oxide (IGZO). In some examples, the third insulating layer may also be referred to as a third gate insulating layer.

[0202] Figure 10A is a schematic diagram of a display island region after forming a second semiconductor layer in at least one embodiment of the present disclosure. Figure 10B is a schematic diagram of the first semiconductor layer and the second semiconductor layer in Figure 10A.

[0203] In some examples, as shown in Figures 10A and 10B, the second semiconductor layer of the display island area may include at least: an active layer of multiple second-type transistors of four first pixel circuits (for example, an active layer 210 of the first transistor 21 of the first pixel circuit 11a and an active layer 220 of the second transistor 22).

[0204] In some examples, the active layers of the two second-type transistors of each first pixel circuit may be an interconnected integral structure. The active layers of the second-type transistors of different first pixel circuits may be independently provided.

[0205] In some examples, using the second semiconductor layer pattern of the first pixel circuit 11a as an example, the active layer 210 of the first transistor 21 and the active layer 220 of the second transistor 22 can be interconnected as an integrated structure. The second region of the active layer 210 of the first transistor 21 can also serve as the second region of the active layer 220 of the second transistor 22. The integrated structure of the active layer 210 of the first transistor 21 and the active layer 320 of the second transistor 22 can be located on a side of the active layer 230 of the third transistor opposite to the second direction Y, and on a side of the active layer 230 of the third transistor in the first direction X.

[0206] In some examples, the active layer 210 of the first transistor 21 and the active layer 220 of the second transistor 22 may be substantially in an I-shape, which is not limited in this embodiment.

[0207] In some examples, the second semiconductor layer patterns of the four first pixel circuits can be substantially symmetrical about the first center line O1. In this example, the active layers of the transistors of the four first pixel circuits in the display island region can be substantially symmetrical about the first center line O1, which can optimize the arrangement of the first pixel circuits and save space.

[0208] (6) Forming a third conductive layer. In some examples, a fourth insulating film and a third conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The third conductive film is patterned by a patterning process to form a fourth insulating layer and a third conductive layer disposed on the fourth insulating layer. In some examples, the third conductive layer may also be referred to as a third gate metal layer, and the fourth insulating layer may also be referred to as a fourth gate insulating layer.

[0209] Figure 11A is a schematic diagram of a display island region after forming a third conductive layer in at least one embodiment of the present disclosure. Figure 11B is a schematic diagram of the third conductive layer in Figure 11A.

[0210] In some examples, as shown in Figures 11A and 11B, the third conductive layer of the display island region may include at least third scan lines 33a and 33b, and fourth scan lines 34a and 34b. The third scan line 33b, the fourth scan line 34b, and the third scan line 33a and the fourth scan line 34b may be arranged sequentially along the second direction Y.

[0211] In some examples, the third scan lines 33a and 33b may be shaped substantially like a zigzag line extending along the first direction X. The orthographic projection of the third scan line 33a on the substrate may be located between the orthographic projections of the first scan line 31a and the second scan line 32b on the substrate. The orthographic projection of the third scan line 33a on the substrate may at least partially overlap with the orthographic projection of the first scan auxiliary line 35a on the substrate. For example, the orthographic projection of the third scan line 33a on the substrate may cover the orthographic projection of the first scan auxiliary line 35a on the substrate.

[0212] In some examples, the overlapping region of the third scan line 33a with the active layer 210 of the first transistor 21 of the first pixel circuit 11a can serve as the gate of the first transistor 21 of the first pixel circuit 11a, and the overlapping region of the third scan line 33a with the active layer of the first transistor of the first pixel circuit 11b can serve as the gate of the first transistor of the first pixel circuit 11b. The overlapping region of the first scan auxiliary line 35a with the active layer 210 of the first transistor 21 of the first pixel circuit 11a can serve as the bottom gate of the first transistor 21 of the first pixel circuit 11a, and the overlapping region of the first scan auxiliary line 35a with the active layer 210 of the first transistor of the first pixel circuit 11a can serve as the bottom gate of the first transistor of the first pixel circuit 11b.

[0213] In some examples, the orthographic projection of the third scan line 33b on the substrate may be located on a side of the first scan line 31b in the opposite direction of the second direction Y. The orthographic projection of the third scan line 33b on the substrate may at least partially overlap with the orthographic projection of the first scan auxiliary line 35b on the substrate. For example, the orthographic projection of the third scan line 33b on the substrate may cover the orthographic projection of the first scan auxiliary line 35b on the substrate.

[0214] In some examples, the overlapping region of the third scan line 33b with the active layer of the first transistor of the first pixel circuit 11c can serve as the gate of the first transistor of the first pixel circuit 11c, and the overlapping region of the third scan line 33b with the active layer of the first transistor of the first pixel circuit 11d can serve as the gate of the first transistor of the first pixel circuit 11d. The overlapping region of the first scan auxiliary line 35b with the active layer of the first transistor of the first pixel circuit 11c can serve as the bottom gate of the first transistor of the first pixel circuit 11c, and the overlapping region of the first scan auxiliary line 35b with the active layer of the first transistor of the first pixel circuit 11d can serve as the bottom gate of the first transistor of the first pixel circuit 11d.

[0215] In some examples, the fourth scan lines 34 a and 34 b may be shaped substantially like a zigzag line extending along the first direction X. The orthographic projection of the fourth scan line 34 a on the substrate may be located on one side of the orthographic projection of the first scan line 31 a on the substrate in the second direction Y. The orthographic projection of the fourth scan line 34 b on the substrate may be located between the orthographic projections of the second scan line 32 b and the first scan line 31 b on the substrate.

[0216] In some examples, the orthographic projection of the fourth scan line 34a on the substrate may at least partially overlap with the orthographic projection of the second scan assistance line 36a on the substrate. For example, the orthographic projection of the fourth scan line 34a on the substrate may cover the orthographic projection of the second scan assistance line 36a on the substrate. The orthographic projection of the fourth scan line 34b on the substrate may at least partially overlap with the orthographic projection of the second scan assistance line 36b on the substrate. For example, the orthographic projection of the fourth scan line 34b on the substrate may cover the orthographic projection of the second scan assistance line 36b on the substrate.

[0217] In some examples, the overlapping region of the fourth scan line 34a with the active layer 220 of the second transistor 22 of the first pixel circuit 11a can serve as the gate of the second transistor 22 of the first pixel circuit 11a, and the overlapping region of the fourth scan line 34a with the active layer of the second transistor of the first pixel circuit 11b can serve as the gate of the second transistor of the first pixel circuit 11b. The overlapping region of the second scan auxiliary line 36a with the active layer 220 of the second transistor 22 of the first pixel circuit 11a can serve as the bottom gate of the second transistor 22 of the first pixel circuit 11a, and the overlapping region of the second scan auxiliary line 36a with the active layer 220 of the second transistor of the first pixel circuit 11a can serve as the bottom gate of the second transistor of the first pixel circuit 11b.

[0218] In some examples, the overlapping region of the fourth scan line 34b with the active layer of the second transistor of the first pixel circuit 11c can serve as the gate of the second transistor of the first pixel circuit 11c, and the overlapping region of the fourth scan line 34b with the active layer of the second transistor of the first pixel circuit 11d can serve as the gate of the second transistor of the first pixel circuit 11d. The overlapping region of the second scan auxiliary line 36b with the active layer of the second transistor of the first pixel circuit 11c can serve as the bottom gate of the second transistor 22 of the first pixel circuit 11c, and the overlapping region of the second scan auxiliary line 36b with the active layer of the second transistor of the first pixel circuit 11d can serve as the bottom gate of the second transistor of the first pixel circuit 11d.

[0219] (7) Forming a fifth insulating layer. In some examples, a fifth insulating film is deposited on the substrate having the aforementioned pattern, and the fifth insulating film is patterned by a patterning process to form a fifth insulating layer. In some examples, the fifth insulating layer may also be referred to as a passivation layer. In other examples, the fifth insulating layer may be an organic insulating layer. This embodiment is not limited thereto.

[0220] Figure 12 is a schematic diagram of the display island region after the fifth insulating layer is formed in at least one embodiment of the present disclosure. In some examples, as shown in Figure 12, the fifth insulating layer of the display island region may be provided with a plurality of vias, such as first through fifth vias V1 through V5, sixth through eighth vias V6 through V8, ninth through thirteenth vias V9 through V13, and fifteenth through twenty-first vias V15 through V21.

[0221] In some examples, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the first through holes V1 to V5 can be removed to expose a portion of the surface of the first semiconductor layer. The fifth insulating layer and the fourth insulating layer within the sixth through holes V6 to V8 can be removed to expose a portion of the surface of the second semiconductor layer. The fifth insulating layer, the fourth insulating layer, and the third insulating layer within the ninth through holes V9 to V13 can be removed to expose a portion of the surface of the second conductive layer. The fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fifteenth through holes V15 to V21 can be removed to expose a portion of the surface of the first conductive layer.

[0222] (8) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate having the aforementioned pattern, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer on the fifth insulating layer. In some examples, the fourth conductive layer may also be referred to as a first source / drain metal layer.

[0223] FIG13A is a schematic diagram of a display island region after forming a fourth conductive layer in at least one embodiment of the present disclosure. FIG13B is a schematic diagram of the fourth conductive layer in FIG13A.

[0224] In some examples, as shown in Figures 13A and 13B, the fourth conductive layer of the display island area may include at least: a first power line 41, a first initial signal line 42, a second initial signal line 43, a third light-emitting control segment 44a and 44b, and a plurality of connecting electrodes (for example, a first connecting electrode 451 to a ninth connecting electrode 459).

[0225] In some examples, the shape of the first power line 41 can be roughly straight and extend along the second direction Y. The first power line 41 can be located between the first pixel circuits 11a and 11b, and between the first pixel circuits 11c and 11d. The first power line 41 can be connected to the plate connection block 282-1 through the twelfth via V12 to achieve connection with the second electrode of the storage capacitor of the first pixel circuits 11a and 11b. It can also be connected to another plate connection block through the thirteenth via V13 to achieve connection with the second electrode of the storage capacitor of the first pixel circuits 11c and 11d. In this example, the four first pixel circuits in the display island area can be connected to the same first power line 41, which can reduce wiring layout. The first power line 41 can realize the transmission of the first voltage signal along the second direction Y, and the second electrode of the storage capacitor of the first pixel circuit can realize the transmission of the first voltage signal along the first direction X, thereby forming a mesh structure for transmitting the first voltage signal within the display island area, which is beneficial to the uniformity of the transmission of the first voltage signal.

[0226] In some examples, the shape of the first initial signal line 42 can be roughly a broken line extending along the second direction Y. The first initial signal line 42 can be located on a side of the first power line 41 opposite to the first direction X. The first initial signal line 42 can be provided with a first initial bump 42-1 and a second initial bump 42-2 on a side close to the first power line 41. The shape of the first initial bump 42-1 and the second initial bump 42-2 can be roughly a strip extending along the first direction X. The first initial bump 42-1, the second initial bump 42-2, and the first initial signal line 42 can be an integrated structure connected to each other.

[0227] In some examples, the first initial bump 42-1 can be connected to the first initial connection block 293-1a via the eleventh via V11, achieving electrical connection to the first initial connection segment 293a. It can also be connected to the first region of the active layer of the first transistor of the first pixel circuit 11a via the eighth via V8. The second initial bump 42-2 can be electrically connected to the first initial connection segment 293b and the first region of the active layer of the first transistor of the first pixel circuit 11c. The seventh connection electrode 457 and the eighth connection electrode 458 can be substantially strip-shaped extending along the first direction X. The seventh connection electrode 457 can electrically connect the first initial connection segment 293a and the first region of the active layer of the first transistor of the first pixel circuit 11b. The eighth connection electrode 458 can electrically connect the first initial connection segment 293b and the first region of the active layer of the first transistor of the first pixel circuit 11d. In this example, the four first pixel circuits in the display island area can be connected to the same first initial signal line 42, which can reduce wiring layout. The first initial signal line 42 can realize the transmission of the first initial signal line along the second direction Y, and the first initial connection segments 293a and 293b can realize the transmission of the first initial signal along the first direction X, thereby forming a mesh structure for transmitting the first initial signal in the display island area, which is beneficial to the transmission uniformity of the first initial signal.

[0228] In some examples, the second initial signal line 43 may be shaped roughly like a broken line extending along the second direction Y. The second initial signal line 43 may be located on one side of the first power line 41 in the first direction X. The second initial signal line 43 may be provided with a third initial bump 43-1 and a fourth initial bump 43-2 on a side close to the first power line 41. The third initial bump 43-1 and the fourth initial bump 43-2 may be shaped roughly like a strip extending along the first direction X. The third initial bump 43-1, the fourth initial bump 44-2, and the second initial signal line 43 may be an integrated structure connected to each other.

[0229] In some examples, the third initial bump 43-1 can be connected to one of the second initial connection blocks 294-1a to achieve electrical connection with the second initial connection segment 294a and can also be connected to the first region of the active layer of the seventh transistor of the first pixel circuit 11b. The fourth initial bump 43-2 can be electrically connected to the second initial connection segment 294b and the first region of the active layer of the seventh transistor of the first pixel circuit 11d. The first connection electrode 451 and the ninth connection electrode 459 can be shaped as strips extending along the first direction X. The first connection electrode 451 can be connected to one of the second initial connection blocks 294-1a via the ninth via hole V9 to achieve electrical connection with the second initial connection segment 294a and can also be connected to the first region of the active layer of the seventh transistor of the first pixel circuit 11a via the first via hole V1. The ninth connection electrode 459 can be electrically connected to the second initial connection segment 294b and the first region of the active layer of the seventh transistor of the first pixel circuit 11c. In this example, the four first pixel circuits in the display island area can be connected to the same second initial signal line 43, which can reduce wiring layout. The second initial signal line 43 can realize the transmission of the second initial signal line along the second direction Y, and the second initial connection segments 294a and 294b can realize the transmission of the second initial signal along the first direction X, thereby forming a mesh structure for transmitting the second initial signal within the display island area, which is beneficial to the uniformity of the transmission of the second initial signal.

[0230] In some examples, the third light-emitting control segments 44 a and 44 b may be shaped substantially like a curve extending along the second direction Y. The third light-emitting control segment 44 a may be located on a side of the first initial signal line 42 in the opposite direction of the first direction X, and the third light-emitting control segment 44 b may be located on a side of the second initial signal line 43 in the first direction X.

[0231] In some examples, the third light-control segment 44a can be bent along one side in the opposite direction of the first direction X, and the third light-control segment 44b can be bent along one side in the first direction X. The third light-control segment 44a can be connected to one end of the first light-control segment 291a through a nineteenth via hole V19, can be connected to the second light-control segment 292a through a fifteenth via hole V15, and can be connected to one end of the first light-control segment 291b through a seventeenth via hole V17. The third light-control segment 44b can be connected to the other end of the first light-control segment 291a through a twentieth via hole V20, can be connected to the second light-control segment 292b through a sixteenth via hole V16, and can be connected to the other end of the first light-control segment 291b through an eighteenth via hole V18. In this example, the four first pixel circuits in the display island area can share a single light-emission control line. This light-emission control line can be divided into a first light-emission control segment, a second light-emission control segment, and a third light-emission control segment. Two first light-emission control segments can be connected to the four first pixel circuits, respectively, while two third light-emission control segments can electrically connect the first light-emission control segment and the second light-emission control segment. This arrangement of the light-emission control line in this example avoids signal routing crossover, facilitating wiring design in the display island area.

[0232] In some examples, the second connection electrode 452 may be shaped substantially like a strip extending along the second direction Y. The second connection electrode 452 may be connected to the first region of the active layer of the fifth transistor of the first pixel circuit 11 a through the third via hole V3, and may also be connected to the second electrode 282 of the storage capacitor of the first pixel circuit 11 a through the tenth via hole V10.

[0233] In some examples, the third connection electrode 453 may be substantially rectangular in shape. The third connection electrode 453 may be connected to the second region of the active layer of the sixth transistor of the first pixel circuit 11a through the second via hole V2. The third connection electrode 453 may be configured to connect to the anode connection electrode 460 formed subsequently.

[0234] In some examples, the fourth connection electrode 454 can be substantially rectangular in shape. The fourth connection electrode 454 can be connected to the first region of the active layer of the sixth transistor of the first pixel circuit 11a via a fourth via V4, and can also be connected to the first region of the active layer of the second transistor of the first pixel circuit 11a via a sixth via V6. The fourth connection electrode 454 can connect the second region of the active layer of the third transistor of the first pixel circuit 11a, the first region of the active layer of the second transistor, and the first region of the active layer of the sixth transistor, and can serve as a third node of the first pixel circuit 11a.

[0235] In some examples, the fifth connection electrode 455 can be shaped substantially like a strip extending along a third direction, which can intersect both the first direction X and the second direction Y. The fifth connection electrode 455 can be connected to the gate of the third transistor of the first pixel circuit 11a through a twenty-first via hole V21, and can also be connected to the first region of the active layer of the second transistor through a seventh via hole V7. The gate of the third transistor of the first pixel circuit 11a, the first plate of the storage capacitor, the first electrode of the second transistor, and the first electrode of the first transistor can be connected through the fifth connection electrode 455, and the fifth connection electrode 455 can serve as the first node of the first pixel circuit 11a.

[0236] In some examples, the sixth connection electrode 456 may be shaped substantially like a strip extending along the first direction X. The sixth connection electrode 456 may be connected to the first region of the active layer of the fourth transistor of the first pixel circuit 11 a through a fifth via hole V5. The sixth connection electrode 456 may be configured to be connected to a subsequently formed data line 50 a.

[0237] (9) Forming a sixth insulating layer. In some examples, a sixth insulating film is coated on the substrate having the aforementioned pattern, and the sixth insulating film is patterned by a patterning process to form a sixth insulating layer. In some examples, the sixth insulating layer may also be referred to as a planar layer.

[0238] Figure 14 is a schematic diagram of the display island region after the sixth insulating layer is formed in at least one embodiment of the present disclosure. In some examples, as shown in Figure 14 , the sixth insulating layer in the display island region may have multiple vias, such as a thirty-first via V31 and a thirty-second via V32. The sixth insulating layer within the thirty-first via V31 and the thirty-second via V32 may be removed to expose the surface of the fourth conductive layer.

[0239] (10) Forming a fifth conductive layer. In some examples, a fifth conductive film is deposited on the substrate having the aforementioned pattern, and the fifth conductive film is patterned by a patterning process to form a fifth conductive layer on the sixth insulating layer. In some examples, the fifth conductive layer may also be referred to as a second source / drain metal layer.

[0240] FIG15A is a schematic diagram of a display island region after forming a fifth conductive layer in at least one embodiment of the present disclosure. FIG15B is a schematic diagram of the fifth conductive layer in FIG15A.

[0241] In some examples, as shown in FIG. 15A and FIG. 15B , the fifth conductive layer of the display island region may include at least two data lines 50 a and 50 b and four anode connection electrodes (eg, anode connection electrode 460 ).

[0242] In some examples, the shape of the data lines 50a and 50b can be roughly straight lines extending along the second direction Y. The orthographic projection of the data line 50a on the substrate can be located on the side of the first initial signal line 42 away from the first power line 41. The data line 50a can be connected to the sixth connection electrode 456 through the thirty-second via V32 to achieve connection with the fourth transistor of the first pixel circuit 11a; the data line 50a can also be connected to the fourth transistor of the first pixel circuit 11c. The orthographic projection of the data line 50b on the substrate can be located on the side of the first power line 41 close to the second initial signal line 43. The data line 50b can be connected to the fourth transistors of the first pixel circuits 11b and 11d. In some examples, the first pixel circuits connected to the first light-emitting elements emitting red light and blue light can share a data line, which can save the number of wirings in the display island area.

[0243] In some examples, the anode connection electrode 460 can be connected to the third connection electrode 453 through the thirty-first via hole V31 to achieve connection with the sixth transistor of the first pixel circuit 11a. The anode connection electrode 460 can be configured to be connected to the anode of the first light emitting element.

[0244] (11) Forming a seventh insulating layer. In some examples, a seventh insulating film is coated on the substrate having the aforementioned pattern, and the seventh insulating film is patterned by a patterning process to form the seventh insulating layer. In some examples, the seventh insulating layer may also be referred to as a planar layer.

[0245] In some examples, the plurality of first island connection lines and the connected first signal lines may be an integrated structure connected to each other. For example, in the first direction X, the first scan lines 31a of adjacent display islands may be connected to each other as an integrated structure, the first scan lines 31b of adjacent display islands may be connected to each other as an integrated structure, the second scan lines 32a of adjacent display islands may be connected to each other as an integrated structure, the second scan lines 32b of adjacent display islands may be connected to each other as an integrated structure, the second light-emitting control segments 292a and 292b of adjacent display islands may be connected to each other as an integrated structure, the third scan lines 33a of adjacent display islands may be connected to each other as an integrated structure, the third scan lines 33b of adjacent display islands may be connected to each other as an integrated structure, the fourth scan lines 34a of adjacent display islands may be connected to each other as an integrated structure, the fourth scan lines 34b of adjacent display islands may be connected to each other as an integrated structure, the first scan auxiliary lines 35a of adjacent display islands may be connected to each other as an integrated structure, the first scan auxiliary lines 35b of adjacent display islands may be connected to each other as an integrated structure, the second scan auxiliary lines 36a of adjacent display islands may be connected to each other as an integrated structure, and the second scan auxiliary lines 36b of adjacent display islands may be connected to each other as an integrated structure. However, this embodiment is not limited to this. In other examples, first signal lines (eg, horizontal lines transmitting the same signal) of adjacent display islands in the first direction X may be connected via first island connection lines located in the fourth conductive layer or the fifth conductive layer.

[0246] In some examples, a plurality of second island area connection lines and the second signal lines connected thereto may be interconnected integral structures. For example, the data lines of adjacent display island areas in the second direction Y may be interconnected integral structures, the first power lines of adjacent display island areas may be interconnected integral structures, the first initial signal lines of adjacent display island areas may be interconnected integral structures, and the second initial signal lines of adjacent display island areas may be interconnected integral structures. However, this embodiment is not limited to this. In other examples, the second signal lines of adjacent display island areas in the second direction Y (for example, longitudinal traces transmitting the same signal) may be connected via second island area connection lines located in different conductive layers. For example, the second signal lines located in the fourth conductive layer (for example, including the first power line, the first initial signal line, and the second initial signal line) may be connected to the second island area connection lines located in the fifth conductive layer.

[0247] At this point, the circuit structure layer of the display substrate can be completed. The circuit structure layer of the display island area can include multiple first pixel circuits, and the circuit structure layer of the second sub-area can include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, and a seventh insulating layer stacked on the substrate. The circuit structure layer of the second display area can include multiple second pixel circuits and multiple third pixel circuits.

[0248] Subsequently, a conductive connection layer, a light-emitting structure layer, and an encapsulation structure layer can be sequentially prepared. The conductive connection layer can include multiple conductive connection lines. The conductive connection layer can be made of a transparent conductive material. The light-emitting structure layer can include: multiple first light-emitting elements located in the display island region, multiple second light-emitting elements located in the second sub-region, and multiple third light-emitting elements located in the second display region. For example, the light-emitting structure layer can include: an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode layer.

[0249] In some examples, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer. The sixth insulating layer and the seventh insulating layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. However, this embodiment is not limited to this.

[0250] The structure of the display substrate and its fabrication process in this embodiment are merely illustrative. In some examples, the corresponding structure can be modified and patterning processes can be added or removed as needed. The fabrication process of this exemplary embodiment can be implemented using currently available manufacturing equipment and is well compatible with existing fabrication processes. The process is simple to implement, easy to implement, and offers high production efficiency, low production costs, and a high yield rate.

[0251] In some examples, the structures of the second and third pixel circuits in the second display area can be substantially the same as those of the first pixel circuit. The light-emitting areas of the third and second light-emitting elements emitting light of the same color can be substantially the same, and the light-emitting area of ​​the second light-emitting element emitting light of the same color can be larger than that of the first light-emitting element. The arrangement of the second light-emitting elements in the second sub-area can be substantially the same as that of the third light-emitting elements in the second display area. This arrangement can improve display uniformity at the interface between the first and second display areas.

[0252] The display substrate provided in this example divides the first display area into a first sub-area and a second sub-area. The first sub-area employs a design with a built-in first pixel circuit, while the second sub-area employs an external second pixel circuit. This achieves an optimal combination of light transmittance and size for the first display area, thereby improving the performance of the display substrate and user experience. For example, this example design can meet the light transmittance requirements of a first display area that is a long strip along a first direction.

[0253] Figure 16 is a partial schematic diagram of the light-shielding layer of the first sub-area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 16, the display substrate may include: a light-shielding layer (BSM, Bottom Shielding Metal) provided on the substrate. The light-shielding layer may be located on the side of the circuit structure layer close to the substrate. For example, the light-shielding layer may be located on the side of the first semiconductor layer close to the substrate, and an inorganic insulating layer may be provided between the first semiconductor layer and the light-shielding layer. The light-shielding layer may include: a plurality of first light-shielding blocks 100 located in the first sub-area. The plurality of first light-shielding blocks 100 in the first sub-area may be an integrated structure connected to each other. The light-shielding layer in the first sub-area may form a continuous pattern.

[0254] In some examples, the first island area connecting line and the second island area connecting line connected to the first pixel circuit of the display island area can be made of metal material. The orthographic projection of a single first light shielding block 100 in the first sub-area on the substrate can cover the four first pixel circuits in a display island area and the metal traces connected to the four first pixel circuits. The outline of the first light shielding block 100 can be roughly the same as the edge shape of the display island area. Four adjacent first light shielding blocks 100 can surround a first light-transmitting area A112.

[0255] In some examples, the edge of the first light-shielding block 100 adjacent to the first light-transmitting area A112 may be an arcuate edge, such that the first light-transmitting area A112 has an arcuate edge. For example, the arcuate edge of the first light-shielding block 100 may be recessed toward the display island area to increase the area of ​​the first light-transmitting area A112. Multiple first light-transmitting areas A112 in the first sub-area may be independently provided, and adjacent first light-transmitting areas A112 may be separated by the first light-shielding block 100.

[0256] In some examples, the edge of the first light-transmitting area A112 can be formed by connecting a plurality of continuous arc-shaped line segments. For example, the first light-transmitting area A112 can be roughly circular or elliptical. The first light-transmitting area A112 has no right-angled edges, which can reduce the diffraction effect of light. In some examples, at least part of the edge of the first light-transmitting area A112 can be wavy, broken line, or sawtooth-shaped. This embodiment does not limit the edge shape of the first light-transmitting area A112. For example, the edge shape of the first light-transmitting area can be determined based on the outer edge of the metal traces in the display island area, or based on the outer edge of the light-shielding layer of the display island area.

[0257] In this example, a light-shielding layer is provided, and the contour of the first light-shielding block of the light-shielding layer is substantially the same as the shape of the edge of the trace, which can help increase the area of ​​the first light-transmitting region and prevent diffraction.

[0258] Figure 17 is another partial schematic diagram of a light shielding layer in the first sub-region according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 17, the light shielding layer of the display substrate may include: a plurality of independently arranged first light shielding blocks 100 located in the first sub-region. The light shielding layer in the first sub-region may form a discontinuous pattern.

[0259] In some examples, the first signal lines and second signal lines connected to the first pixel circuits in the display island area can be made of metal, and the first island area connecting lines and the second island area connecting lines can be made of transparent conductive material. The orthographic projection of a single first light shielding block 100 on the substrate can cover the four first pixel circuits in a display island area and the metal traces connected to the four first pixel circuits. The orthographic projection of the light shielding layer on the substrate can overlap with the orthographic projections of multiple first island area connecting lines and multiple second island area connecting lines on the substrate.

[0260] The first light-transmitting areas between the display island areas of the first sub-area of ​​this example can be interconnected, thereby facilitating an increase in light transmittance of the first sub-area.

[0261] Figure 18 is a partial top view of the first sub-region of at least one embodiment of the present disclosure. Figure 18 illustrates a first light shielding block 100 in the first sub-region and a display island region covered by the first light shielding block 100. The plurality of first island region connecting lines and the plurality of second island region connecting lines can be made of transparent conductive material and located in the same conductive layer.

[0262] In some examples, as shown in Figure 18, the conductive connection layer of the display substrate may include: multiple first island area connection lines (for example, including first connection lines 511a and 511b, second connection lines 512a and 512b, third connection lines 513a and 513b, fourth connection lines 514a and 514b, fifth connection lines 515a and 515b, sixth connection lines 516a and 516b, seventh connection lines 517a and 517b, eighth connection lines 518a and 518b, and ninth connection lines 519a and 519b) and multiple second island area connection lines (for example, including eleventh connection lines 521a and 521b, twelfth connection lines 522a and 522b, thirteenth connection lines 523a and 523b, fourteenth connection lines 524a and 524b, and fifteenth connection lines 525a and 525b).

[0263] In some examples, the seventh insulating layer may have a plurality of vias that expose portions of the surfaces of the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer. The first connecting wires 511a and 511b to the ninth connecting wires 519a and 519b may extend substantially along the first direction X and be arranged sequentially along the second direction Y. The eleventh connecting wires 521a and 521b to the fifteenth connecting wires 525a and 525b may extend substantially along the second direction Y and be arranged sequentially along the first direction X.

[0264] In some examples, one end of the second scan line 32a located in the first conductive layer can be connected to the first connection line 511a, and the other end can be connected to the first connection line 511b. The second light-emitting control segment 292a located in the first conductive layer can be connected to the second connection line 512a, and the second light-emitting control segment 292b can be connected to the second connection line 512b. One end of the second scan auxiliary line 36a located in the second conductive layer and one end of the fourth scan line 34a located in the third conductive layer can be connected to the third connection line 513a, and the other end of the second scan auxiliary line 36a and the other end of the fourth scan line 34a can be connected to the third connection line 513b. The first scan line 31a located in the first conductive layer can have one end connected to the fourth connection line 514a, and the other end connected to the fourth connection line 514b. One end of the first scan auxiliary line 35a located in the second conductive layer and one end of the third scan line 33a located in the third conductive layer can be connected to the fifth connection line 515a, and the other end of the first scan auxiliary line 35a and the other end of the third scan line 33a can be connected to the fifth connection line 515b. One end of the second scan line 32b located in the first conductive layer can be connected to the sixth connection line 516a, and the other end can be connected to the sixth connection line 516b. One end of the second scan auxiliary line 36b located in the second conductive layer and one end of the fourth scan line 34b located in the third conductive layer can be connected to the seventh connection line 517a, and the other end of the second scan auxiliary line 36b and the other end of the fourth scan line 34b can be connected to the seventh connection line 517b. One end of the first scan line 31b located in the first conductive layer can be connected to the eighth connection line 518a, and the other end can be connected to the eighth connection line 518b. One end of the first scan auxiliary line 35b located on the second conductive layer and one end of the third scan line 33b located on the third conductive layer can be connected to the ninth connection line 519a, and the other end of the first scan auxiliary line 35b and the other end of the third scan line 33b can be connected to the ninth connection line 519b. In this example, nine first island area connection lines can be used to implement signal transmission in the first direction X for first pixel circuits in adjacent display island areas in the first direction X.

[0265] In some examples, one end of the data line 50a located in the fifth conductive layer can be connected to the eleventh connecting line 521a, and the other end can be connected to the eleventh connecting line 521b. One end of the first initial signal line 42 located in the fourth conductive layer can be connected to the twelfth connecting line 522a, and the other end can be connected to the twelfth connecting line 522b. One end of the first power line 41 located in the fourth conductive layer can be connected to the thirteenth connecting line 523a, and the other end can be connected to the thirteenth connecting line 523b. One end of the data line 50b located in the fifth conductive layer can be connected to the fourteenth connecting line 524a, and the other end can be connected to the fourteenth connecting line 524b. One end of the second initial signal line 43 located in the fourth conductive layer can be connected to the fifteenth connecting line 525a, and the other end can be connected to the fifteenth connecting line 525b. This example uses five second island area connecting lines to implement signal transmission in the second direction Y for first pixel circuits in adjacent display island areas in the second direction Y.

[0266] In some examples, the edge of the first light shielding block 100 can be roughly the same shape as the edge of the outer metal traces within the display island area. For example, the edge of the first light shielding block 100 can surround the edges of the second scan line 32a and the third scan line 33b. The first light shielding block 100 can cover the connection location between the first island area connecting line and the metal trace of the display island area, as well as the connection location between the second island area connecting line and the metal trace of the display island area. The first island area connecting line and the second island area connecting line between adjacent display island areas can have no overlap with the orthographic projection of the first light shielding block 100 on the substrate.

[0267] In this example, the light shielding layer is provided to shield the first pixel circuit and the metal wiring, thereby preventing diffraction. The remaining film layer structures of the display island region of this example can refer to the description of the previous embodiment, so they are not repeated here.

[0268] Figure 19 is another partial schematic diagram of the display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 19, a display island area A111 of the first sub-area A11 of the first display area A1 can be provided with a first pixel unit. Each first pixel unit can include three first sub-pixels, each of which can include a first pixel circuit 11 and a first light-emitting element 15. In other words, the display island area A111 can include three first pixel circuits 11 and three first light-emitting elements 15. The three first pixel circuits 11 and the three first light-emitting elements 15 can be electrically connected in a one-to-one correspondence. The three first pixel circuits 11 can be arranged sequentially along the first direction X. Two of the three first light-emitting elements 15 can be arranged in a row along the second direction Y, and the other first light-emitting element can be arranged to one side of the two first light-emitting elements along the first direction X. For example, a first light-emitting element emitting green light and a first light-emitting element emitting red light can be arranged in a row along the second direction Y, and a first light-emitting element emitting blue light can be arranged to one side of the first light-emitting element emitting green light and the first light-emitting element emitting red light in the opposite direction of the first direction X. This embodiment is not limited to this.

[0269] In some examples, the first island area connection line 51 and the second island area connection line 52 connecting the first pixel circuits of adjacent display island areas can be metal traces. The second light-emitting element 16 of the second sub-area A12a can be connected to the second pixel circuit 12 of the second display area A2 via a conductive connection line 53. For example, the conductive connection line 53 can be made of a transparent conductive material. However, this embodiment is not limited to this.

[0270] In this example, three first sub-pixels can be arranged in each display island area. Compared with arranging four first sub-pixels in the display island area, the aperture ratio and light-emitting element density of the first sub-area can be improved.

[0271] Figure 20 is a schematic top view of a display island region according to at least one embodiment of the present disclosure. Figure 20 illustrates a circuit structure layer of a display island region. In some examples, as shown in Figure 20 , the circuit structure layer of the display island region can be covered by the orthographic projection of a first light shielding block 100 located in the light shielding layer onto the substrate.

[0272] FIG21 is a schematic diagram of the first semiconductor layer in FIG20 . In some examples, as shown in FIG21 , the first semiconductor layer of the display island region may include: active layers of multiple first-type transistors (e.g., active layers 230 of the third transistor, 240 of the fourth transistor, 250 of the fifth transistor, 260 of the sixth transistor, and 270 of the seventh transistor of the first pixel circuit 11a ) of three first pixel circuits (e.g., first pixel circuits 11a , 11b , and 11c ). The first semiconductor layer patterns of the three first pixel circuits may be sequentially arranged along the first direction X.

[0273] FIG22 is a schematic diagram of the first semiconductor layer and the first conductive layer in FIG20. In some examples, as shown in FIG22, the first conductive layer of the display island region may include: first electrodes of storage capacitors of three first pixel circuits (e.g., first electrodes 281), a first scan line 31, a second scan line 32, and a light emitting control line 37.

[0274] In some examples, the first scan line 31, the second scan line 32, and the light-emitting control line 37 may be shaped like a zigzag line extending along the first direction X. The second scan line 32 and the light-emitting control line 37 may be located on one side of the first electrodes of the storage capacitors of the three first pixel circuits in the second direction Y, and the second scan line 32 may be located on one side of the light-emitting control line 37 in the second direction Y; the first scan line 31 may be located on a side opposite to the second direction Y of the first electrodes of the storage capacitors of the three first pixel circuits.

[0275] In some examples, the overlapping area of ​​the first scan line 31 and the active layer 240 of the fourth transistor 24 of the first pixel circuit 11a can serve as the gate of the fourth transistor 24 of the first pixel circuit 11a, the overlapping area with the active layer of the fourth transistor of the first pixel circuit 11b can serve as the gate of the fourth transistor of the first pixel circuit 11b, and the overlapping area with the active layer of the fourth transistor of the first pixel circuit 11c can serve as the gate of the fourth transistor of the first pixel circuit 11c.

[0276] In some examples, the overlapping area of ​​the light-emitting control line 37 and the active layer of the fifth transistor 25 of the first pixel circuit 11a can serve as the gate of the fifth transistor 25 of the first pixel circuit 11a, and the overlapping area with the active layer of the sixth transistor 26 of the first pixel circuit 11a can serve as the gate of the sixth transistor 26 of the first pixel circuit 11a; the overlapping area of ​​the light-emitting control line 37 and the active layer of the fifth transistor of the first pixel circuit 11b can serve as the gate of the fifth transistor of the first pixel circuit 11b, and the overlapping area with the active layer of the sixth transistor of the first pixel circuit 11b can serve as the gate of the sixth transistor of the first pixel circuit 11b; the overlapping area of ​​the light-emitting control line 37 and the active layer of the fifth transistor of the first pixel circuit 11c can serve as the gate of the fifth transistor of the first pixel circuit 11c, and the overlapping area with the active layer of the sixth transistor of the first pixel circuit 11c can serve as the gate of the sixth transistor of the first pixel circuit 11c.

[0277] In some examples, the overlapping area of ​​the second scan line 32 and the active layer of the seventh transistor 27 of the first pixel circuit 11a can serve as the gate of the seventh transistor 27 of the first pixel circuit 11a, the overlapping area with the active layer of the seventh transistor of the first pixel circuit 11b can serve as the gate of the seventh transistor of the first pixel circuit 11b, and the overlapping area with the active layer of the seventh transistor of the first pixel circuit 11c can serve as the gate of the seventh transistor of the first pixel circuit 11c.

[0278] Figure 23 is a schematic diagram of the first semiconductor layer, the first conductive layer, and the second conductive layer in Figure 20. In some examples, as shown in Figure 23, the second conductive layer of the display island area may include at least: a first scanning auxiliary line 35, a second scanning auxiliary line 36, the second electrodes of the storage capacitors of the three first pixel circuits (e.g., the second electrode 282), the first initial connection segment 293, and the second initial connection segment 294. In some examples, the second electrodes 282 of the storage capacitors of two adjacent first pixel circuits in the three first pixel circuits can be connected through a plate connection block 282-1. The second electrodes 282 of the storage capacitors of the three first pixel circuits and the plate connection block 282-1 can be an integrated structure connected to each other.

[0279] FIG24 is a schematic diagram of the first semiconductor layer, the first conductive layer, the second conductive layer, and the second semiconductor layer in FIG20. In some examples, as shown in FIG24, the second semiconductor layer in the display island region may include at least the active layers of the plurality of second-type transistors of the three first pixel circuits (e.g., the active layer 210 of the first transistor 21 and the active layer 220 of the second transistor 22 of the first pixel circuit 11a).

[0280] Figure 25 is a schematic diagram of the first semiconductor layer, first conductive layer, second conductive layer, second semiconductor layer, and third conductive layer in Figure 20 . In some examples, as shown in Figure 25 , the third conductive layer in the display island region may include at least a third scan line 33 and a fourth scan line 34. In some examples, the orthographic projection of the third scan line 33 onto the substrate may partially overlap with the orthographic projection of the first scan auxiliary line 35 onto the substrate. The orthographic projection of the fourth scan line 34 onto the substrate may partially overlap with the orthographic projection of the second scan auxiliary line 36 onto the substrate.

[0281] FIG26 is a schematic diagram of via holes defined in the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, the third conductive layer, and the fifth insulating layer in FIG20. In some examples, as shown in FIG26, the fifth insulating layer in the display island region may have multiple via holes defined therein, such as first to fifth via holes V1 to V5, sixth to eighth via holes V6 to V8, ninth to eleventh via holes V9 to V11, and a twenty-first via hole V21.

[0282] In some examples, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the first through holes V1 to V5 can be removed to expose a portion of the surface of the first semiconductor layer. The fifth insulating layer and the fourth insulating layer within the sixth through holes V6 to V8 can be removed to expose a portion of the surface of the second semiconductor layer. The fifth insulating layer, the fourth insulating layer, and the third insulating layer within the ninth through holes V9 to V11 can be removed to expose a portion of the surface of the second conductive layer. The fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the twenty-first through hole V21 can be removed to expose a portion of the surface of the first conductive layer.

[0283] FIG27A is a schematic diagram of the display island region after the fourth conductive layer is formed in FIG20 . FIG27B is a schematic diagram of the fourth conductive layer in FIG27A . In some examples, as shown in FIG27A and FIG27B , the fourth conductive layer of the display island region may include: a first power line 41, a first initial signal line 42, a second initial signal line 43, and a plurality of connection electrodes (e.g., including first to sixth connection electrodes 451 to 456, and eleventh to thirteenth connection electrodes 461 to 463). The first power line 41, the first initial signal line 42, and the second initial signal line 43 may be in the shape of a broken line extending substantially along the second direction Y. The first power line 41 may be located between the first initial signal line 42 and the second initial signal line 43.

[0284] In some examples, the first power line 41 may be provided with a power connection block 41-1 on a side close to the second initial signal line 43. The shape of the power connection block 41-1 may be roughly L-shaped. The first power line 41 and the power connection block 41-1 may be an integrated structure connected to each other. The power connection line 41-1 may be connected to the first area of ​​the active layer of the fifth transistor of the first pixel circuit 11b and the second electrode of the storage capacitor, thereby achieving electrical connection with the first power line 41. The first power line 41 can enable the first voltage signal to be transmitted along the second direction Y, and the integrated structure of the second electrodes of the storage capacitors of the three first pixel circuits can enable the first voltage signal to be transmitted along the first direction X, thereby forming a mesh structure for transmitting the first voltage signal within the display island area, which is beneficial to the transmission uniformity of the first voltage signal.

[0285] In some examples, a fifth initial bump 42-3 may be provided on a side of the first initial signal line 42 near the first power line 41. The fifth initial bump 42-3 may be substantially strip-shaped and extend along the first direction X. The fifth initial bump 42-3 and the first initial signal line 42 may be interconnected as a single, integrated structure. The fifth initial bump 42-3 may be connected to the first initial connection block via an eleventh via V11, electrically connecting to the first initial connection segment 293. The fifth initial bump 42-3 may also be connected to the first region of the active layer of the first transistor of the first pixel circuit 11a via an eighth via V8. The twelfth connection electrode 462 may electrically connect the first region of the active layer of the first transistor of the first pixel circuit 11b to the first initial connection segment 293. The thirteenth connection electrode 463 may electrically connect the first region of the active layer of the first transistor of the first pixel circuit 11c to the first initial connection segment 293. In this example, the three first pixel circuits in the display island region may be connected to the same first initial signal line 42, thereby reducing wiring layout. The first initial signal line 42 can realize the transmission of the first initial signal line along the second direction Y, and the first initial connection segment 293 can realize the transmission of the first initial signal along the first direction X, thereby forming a mesh structure for transmitting the first initial signal in the display island area, which is beneficial to the transmission uniformity of the first initial signal.

[0286] In some examples, the second initial signal line 43 can be connected to the first region of the active layer of the seventh transistor of the first pixel circuit 11c and the second initial connection segment 294. The first connection electrode 451 can be connected to a second initial connection block through the ninth via V9 to achieve electrical connection with the second initial connection segment 294. It can also be connected to the first region of the active layer of the seventh transistor of the first pixel circuit 11a through the first via V1. The eleventh connection electrode 461 can be electrically connected to the first region of the active layer of the seventh transistor of the first pixel circuit 11b and the second initial connection segment 294. In this example, the three first pixel circuits in the display island area can be connected to the same second initial signal line 43, which can reduce wiring layout. The second initial signal line 43 can realize the transmission of the second initial signal line along the second direction Y, and the second initial connection segment 294 can realize the transmission of the second initial signal along the first direction X, thereby forming a mesh structure for transmitting the second initial signal within the display island area, which is beneficial to the uniformity of the transmission of the second initial signal.

[0287] The description of the second connection electrode 452 to the sixth connection electrode 456 can refer to the description of the aforementioned embodiment, and thus will not be repeated here.

[0288] FIG20 is a schematic diagram of a display island region after forming a fifth conductive layer in at least one embodiment of the present disclosure. In some examples, as shown in FIG20 , the fifth conductive layer in the display island region may include at least three data lines 50c, 50d, and 50e, and three anode connection electrodes (e.g., anode connection electrode 470).

[0289] In some examples, the anode connection electrode 470 can be connected to the third connection electrode through a via hole opened in the sixth insulating layer, thereby achieving connection with the sixth transistor of the first pixel circuit 11 a.

[0290] In some examples, the three data lines 50c, 50d, and 50e may be substantially in the shape of a zigzag line extending along the second direction Y. The three data lines 50c, 50d, and 50e may be arranged along the first direction X. The orthographic projection of the data line 50c on the substrate may be located on a side of the first initial signal line 42 opposite to the first direction X, the orthographic projection of the data line 50d on the substrate may be located on a side of the first power line 41 opposite to the first direction X, and the orthographic projection of the data line 50e on the substrate may be located on a side of the second initial signal line 43 opposite to the first direction X.

[0291] In some examples, data line 50c can be connected to the fourth transistor of the first pixel circuit 11a through a via opened in the sixth insulating layer, data line 50d can be connected to the fourth transistor of the first pixel circuit 11b, and data line 11e can be connected to the fourth transistor of the first pixel circuit 11c.

[0292] In this example, the first signal lines (for example, including the first scan line 31, the second scan line 32, the third scan line 33, the fourth scan line 34, the first scan auxiliary line 35, the second scan auxiliary line 36 and the light-emitting control line 37) and the second signal lines (for example, including the data lines 50c, 50d and 50e, the first power line 51, the first initial signal line 42 and the second initial signal line 43) of the display island area are cross-designed, which can help increase the area of ​​the first light-transmitting area.

[0293] Figure 28 is another partial schematic diagram of the light shielding layer in the first sub-area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 28 , the light shielding layer can include multiple first light shielding blocks 100 located in the first sub-area. The multiple first light shielding blocks 100 can be interconnected and integrally formed. The light shielding layer in the first sub-area can form a continuous pattern.

[0294] In some examples, the first island area connection line and the second island area connection line connected to the first pixel circuit of the display island area can be made of metal material. The orthographic projection of a single first light shielding block 100 in the first sub-area on the substrate can cover the four first pixel circuits in a display island area and the metal traces connected to the four first pixel circuits. The edge of the first light shielding block 100 near the first light-transmitting area A112 can be an arc-shaped edge, so that the first light-transmitting area A112 has an arc-shaped edge. The edge profile of the first light shielding block 100 near the first light-transmitting area A112 can be substantially the same as the edge shape of the metal trace connected to the first pixel circuit.

[0295] In this example, three first pixel circuits are set in the display island area, and the first pixel circuits of adjacent display island areas are connected by seven metal traces extending along the first direction X. Compared with the case where four first pixel circuits are set in the display island area, this example can reduce the size of the position where the first light-shielding block 100 blocks the first island area connection line (for example, the length along the second direction Y) by reducing the horizontal connection traces, thereby facilitating increasing the area of ​​the first light-transmitting area.

[0296] Figure 29 is a partial schematic diagram of the display island area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 29, the light-shielding layer of the display substrate may include: a plurality of light-shielding strips 101 located in the display island area. The shape of the light-shielding strips 101 may be roughly rectangular strips. The orthographic projection of each light-shielding strip 101 on the substrate may cover the orthographic projection of the channel region of the active layer of at least one transistor of the first pixel circuit in the display island area on the substrate. For example, the orthographic projection of each light-shielding strip 101 on the substrate may cover the orthographic projection of the channel region of the active layer of a transistor of the first pixel circuit on the substrate. In some examples, multiple light-shielding strips 101 may be independently provided. However, this embodiment is not limited to this. In other examples, multiple light-shielding strips may be interconnected to form a mesh structure.

[0297] In some examples, as shown in FIG29 , the cathodes of the plurality of first light-emitting elements (e.g., three first light-emitting elements) in the display island area may be interconnected integral structures. For example, the plurality of first light-emitting elements in the display island area are interconnected to form an island cathode structure 600. The island cathode structure 600 may cover the three first pixel circuits in the display island area, the metal traces to which the three first pixel circuits are connected, and the orthographic projections of the plurality of light-shielding strips 101 in the display island area on the substrate. The edge of the island cathode structure 600 close to the first light-transmitting area may be an arc-shaped edge. The edge profile of the island cathode structure 600 may be roughly the same as the edge shape of the metal trace to which the first pixel circuit is connected. In some examples, the island cathode structure 600 may be made of a metal material. By providing a patterned cathode layer to shield the first pixel circuit and the metal trace in the display island area, it can help to increase the area of ​​the first light-transmitting area and prevent diffraction.

[0298] In some examples, a light-shielding pixel definition layer (such as the first pixel definition layer described above) may be provided on the side of the island cathode structure 600 close to the substrate. The orthographic projection of the light-shielding pixel definition layer on the substrate may cover the first island connection line and the second island connection made of metal material. The orthographic projection of the island cathode structure 600 on the substrate may cover the orthographic projection of the light-shielding pixel definition layer on the substrate. By providing a light-shielding pixel definition layer and a patterned cathode layer to shield the metal traces between adjacent display islands, it can help to increase the area of ​​the first light-transmitting area and prevent diffraction. The remaining description of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0299] Figure 30 is a schematic diagram of the cathode layer of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 30 , within the second sub-area A12a, the cathodes 163 of multiple second light-emitting elements can be interconnected. For example, the cathodes 163 of adjacent second light-emitting elements can be connected via a cathode connecting bar 163-1. The cathodes 163 of the second light-emitting elements and the cathode connecting bar 163-1 can be an integrated, interconnected structure.

[0300] In some examples, the cathode 163 of the second light-emitting element in the second sub-region A12a and the island cathode structure 600 in the first sub-region A11 can be interconnected and integrated. The cathodes of the first light-emitting element and the second light-emitting element in the first display region can be connected to form a grid, and the grid-shaped cathode layer can have multiple cathode grids. The area of ​​the cathode grid in the second sub-region A12a can be smaller than the area of ​​the cathode grid in the first sub-region A11. For example, the area of ​​the cathode grid in the first sub-region A11 can be approximately the area of ​​the first light-transmitting region, and the area of ​​the cathode grid in the second sub-region A12 can be approximately the area of ​​the second light-transmitting region.

[0301] This example, by providing a patterned cathode layer, can help increase the area of ​​the light-transmitting region of the first display region and prevent diffraction. The remaining description of the display substrate of this example can refer to the description of the previous embodiment, so it will not be repeated here.

[0302] Figure 31 is another partial schematic diagram of the display area of ​​at least one embodiment of the present disclosure. In some examples, the display area may include: a first display area A1 and a second display area A2. The first display area A1 may, for example, be located at an edge corner position of the display area (e.g., the upper left corner position). The first display area A1 may include: a first sub-area A11 and a second sub-area A12. The second sub-area A12 is located between the first sub-area A11 and the second display area A2 in the first direction X. For example, the area of ​​the first sub-area A11 may account for two-thirds of the total area of ​​the first display area A1, and the area of ​​the second sub-area A12 may account for one-third of the total area of ​​the first display area A1. However, this embodiment is not limited to this.

[0303] In some examples, the second light-emitting element 16 in the second sub-area A12 can be connected to the second pixel circuit 12 in the adjacent second display area A2 through the conductive connection line 53. The first pixel circuit 11 and the first light-emitting element 15 in the first sub-area A11 are connected and arranged in an island shape.

[0304] In this example, a second sub-area A12 is disposed on one side of the first sub-area A11 of the first display area A1. The first sub-area A11 utilizes an internal pixel circuit, while the second sub-area A12 utilizes an external pixel circuit. This provides a circuit drive design for when the first display area A1 is located at the edge of the display area, ensuring light transmittance in the first display area A1 and allowing for an increase in the size of the first display area A1. The remaining description of the display substrate of this example can be found in the previous embodiment and will not be repeated here.

[0305] Figure 32 is a partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 32, the first display area may include a first sub-area A11 and a second sub-area A12 adjacent to the first sub-area A11. The second sub-area A12 may be located on opposite sides of the first sub-area A11 in the first direction X and adjacent to one side of the first sub-area A11 in the second direction Y. The second display area may be located peripherally to the second sub-area A12. The first sub-area A11 includes a plurality of display islands and a first light-transmitting area located between adjacent display islands.

[0306] In some examples, as shown in FIG32 , the display island area of ​​the first sub-area A11 may include a plurality of first pixel circuits and a plurality of first light-emitting elements (e.g., three first pixel circuits and three first light-emitting elements 15a, 15b, and 15c) provided on the substrate. The display island area may include a first light-emitting unit 150, and the first light-emitting unit 150 may include a plurality of adjacent first light-emitting elements. For example, one display island area may include one first light-emitting unit 150, and a single first light-emitting unit 150 may include: adjacent first light-emitting elements 15a, 15b, and 15c that emit light of different colors. The first light-emitting element 15a may be configured to emit a first color light, the first light-emitting element 15b may be configured to emit a second color light, and the first light-emitting element 15c may be configured to emit a third color light. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light.

[0307] In some examples, as shown in FIG32 , the second sub-area A12 may include a plurality of second light-emitting units 160. Each second light-emitting unit 160 may include a plurality of adjacent second light-emitting elements. For example, a second light-emitting unit 160 may include three second light-emitting elements 16a, 16b, and 16c. The second light-emitting element 16a may be configured to emit a first color of light, the second light-emitting element 16b may be configured to emit a second color of light, and the second light-emitting element 16c may be configured to emit a third color of light.

[0308] In some examples, the number of first light-emitting elements in the first light-emitting unit 150 and the number of second light-emitting elements in the second light-emitting unit 160 can be the same, for example, they can both be three. The three first light-emitting elements in the first light-emitting unit 150 can be configured to emit light of different colors, and the three first light-emitting elements in the second light-emitting unit 160 can be configured to emit light of different colors. However, this embodiment is not limited to this. In other examples, the number of first light-emitting elements in the first light-emitting unit and the number of second light-emitting elements in the second light-emitting unit can both be four. The first light-emitting unit can, for example, include: a first light-emitting element that emits light of the first color, a first light-emitting element that emits light of the third color, and two first light-emitting elements that emit light of the second color; the second light-emitting unit can, for example, include: a second light-emitting element that emits light of the first color, a second light-emitting element that emits light of the third color, and two second light-emitting elements that emit light of the second color. For the example in which the first light-emitting unit includes four first light-emitting elements and the second light-emitting unit includes four second light-emitting elements, reference can be made to the corresponding embodiment of Figure 3, so it will not be repeated here.

[0309] In some examples, as shown in FIG32 , for first light-emitting elements and second light-emitting elements emitting light of the same color in the first display area, the distance between adjacent first light-emitting elements emitting light of the same color in the first sub-area A11 can be greater than the distance between adjacent second light-emitting elements emitting light of the same color in the second sub-area A12 along the first direction X. For example, the distance between adjacent first light-emitting elements emitting light of the same color in the first sub-area A11 along the first direction X is 1.5 to 2 times the distance between adjacent first light-emitting elements emitting light of the same color in the second sub-area A12.

[0310] Taking the first light-emitting element 15c and the second light-emitting element 16c emitting third color light as an example, in the first direction X, the distance between adjacent first light-emitting elements 15c emitting third color light in the first sub-area A11 is L1, and the distance between adjacent second light-emitting elements 16c emitting third color light in the second sub-area A12 is L2, where L1 is greater than L2. For example, L1 can be 1.5 to 2 times the value of L2, such as approximately 1.5 times, approximately 1.8 times, or approximately 2 times. This example is not limited to this.

[0311] In other examples, along the second direction, the distance between adjacent first light-emitting elements emitting light of the same color in the first sub-area may be greater than the distance between adjacent second light-emitting elements emitting light of the same color in the second sub-area. For example, along the second direction, the distance between adjacent first light-emitting elements emitting light of the same color in the first sub-area may be 1.5 to 2 times the distance between adjacent second light-emitting elements emitting light of the same color in the second sub-area.

[0312] In this example, by setting the spacing between the first light-emitting elements emitting the same color light in the first sub-area to be greater than the spacing between the second light-emitting elements emitting the same color light in the second sub-area, it is beneficial to increase the area of ​​the first light-transmitting area in the first sub-area, thereby improving the light transmittance of the first display area.

[0313] In some examples, as shown in FIG32 , in the adjacent area of ​​the first sub-area A11 and the second sub-area A12, along the first direction X, the minimum distance between the first light-emitting unit 150 and the second light-emitting unit 160 (for example, distance D2) can be smaller than the distance between adjacent first light-emitting units 150 (for example, distance D3), and larger than the distance between adjacent second light-emitting units 160 (for example, distance D1). In other words, D1 is smaller than D2, and D2 is smaller than D3. In this example, the distance between light-emitting units refers to the distance between adjacent light-emitting elements in adjacent light-emitting units. In this example, the distance between adjacent light-emitting units is adjusted in the order of the first sub-area, the adjacent area of ​​the first sub-area and the second sub-area, and the second sub-area, so that the distance between adjacent light-emitting units varies along the direction from the first sub-area to the second sub-area, which is beneficial to improving the display uniformity of the first display area.

[0314] The remaining structures of the display substrate of this example can be referred to the description of the aforementioned embodiment, and thus will not be described again here.

[0315] Figure 33 is a partial schematic diagram of a display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 33, the second display area A2 can be located around the second sub-area A12, away from the first sub-area A11. The second display area A2 can include at least: a plurality of third light-emitting elements (e.g., third light-emitting elements 17a, 17b, and 17c). For example, the third light-emitting element 17a can be configured to emit a first color of light, the third light-emitting element 17b can be configured to emit a second color of light, and the third light-emitting element 17c can be configured to emit a third color of light.

[0316] In some examples, as shown in Figure 33, the arrangement of the plurality of third light-emitting elements in the second display area A2 can be the same as the arrangement of the plurality of second light-emitting elements in the second sub-area A12. The light-emitting area of ​​the third light-emitting element emitting the same color light can be smaller than the light-emitting area of ​​the second light-emitting element. The light-emitting area of ​​the second light-emitting element emitting the same color light can be smaller than the light-emitting area of ​​the first light-emitting element. This example can help improve the display uniformity of the entire display area by setting the changes in the light-emitting areas of the first light-emitting element, the second light-emitting element, and the third light-emitting element. However, this embodiment is not limited to this. In other examples, the light-emitting areas of the third light-emitting element and the second light-emitting element emitting the same color light can be approximately the same, and the distance between adjacent third light-emitting elements emitting the same color light can be greater than the distance between adjacent second light-emitting elements emitting the same color light. This example improves the display uniformity of the entire display area by adjusting the distance between adjacent light-emitting elements emitting the same color light.

[0317] The remaining structures of the display substrate of this example can refer to the description of the aforementioned embodiment, so they will not be repeated here. Figure 34 is a schematic diagram of a display device of at least one embodiment of the present disclosure. As shown in Figure 34, this embodiment provides a display device, comprising: a display substrate 91 and a sensor 92 located on the light-emitting side of the light-emitting structure layer away from the display substrate 91. The sensor 92 can be located on the non-display surface side of the display substrate 91. The orthographic projection of the sensor 92 on the display substrate 91 may overlap with the first display area A1.

[0318] In some examples, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be a product having an image (including a static image or a dynamic image, wherein the dynamic image may be a video) display function. For example, the display device may be: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (such as business query equipment for e-government, banks, hospitals, power departments, etc.), a monitor, and the like. For another example, the display device may also be a microdisplay, a VR device or an AR device containing a microdisplay, and the like.

[0319] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of the present disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be noted that the above-mentioned embodiments or implementation methods are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents shown and described in detail herein. Various modifications, replacements or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. A display substrate, comprising: a first display area and a second display area located at at least one side of the first display area; The first display area includes: a first sub-area and a second sub-area located at least on one side of the first sub-area close to the second display area; the first sub-area includes: a plurality of display island areas and a first light-transmitting area located between adjacent display island areas; The display island area comprises: a plurality of first pixel circuits and a plurality of first light-emitting elements arranged on a substrate; the plurality of first pixel circuits and the plurality of first light-emitting elements are electrically connected; the first light-emitting elements and the connected first pixel circuits have at least a partial overlap of their orthographic projections on the substrate; The second sub-area includes: a plurality of second light-emitting elements disposed on the substrate; The second display area at least includes: a plurality of second pixel circuits arranged on the substrate; at least one second pixel circuit among the plurality of second pixel circuits is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements through a conductive connecting line; and a distance between an orthographic projection of the second light-emitting element on the substrate and an orthographic projection of the second pixel circuit connected to the second light-emitting element on the substrate is greater than 0.

2. The display substrate according to claim 1, wherein: The plurality of first pixel circuits in the display island area are connected to a plurality of first signal lines extending along a first direction and a plurality of second signal lines extending along a second direction; In the first sub-area, multiple first signal lines of adjacent display island areas in the first direction are connected by multiple first island area connecting lines, and multiple second signal lines of adjacent display island areas in the second direction are connected by multiple second island area connecting lines; the first direction intersects the second direction.

3. The display substrate according to claim 2, wherein: The conductive connection line includes at least one routing layer, and the plurality of first island area connection lines, the plurality of second island area connection lines and at least one routing layer of the conductive connection line are in the same layer structure and are made of transparent conductive material.

4. The display substrate according to claim 2, wherein: The plurality of first island area connection lines, the plurality of second island area connection lines and the conductive connection lines are all made of metal material.

5. The display substrate according to claim 2, wherein: The plurality of first island area connection lines and the plurality of second island area connection lines are made of metal material, and the conductive connection lines are made of transparent conductive material.

6. The display substrate according to any one of claims 1 to 5, wherein: The plurality of first pixel circuits in the display island area are connected to the same first power line.

7. The display substrate according to claim 6, wherein: The plurality of first pixel circuits in the display island area are connected to the same first initial signal line and the same second initial signal line; In the display island area, the first initial signal line, the second initial signal line and the first power line have the same extension direction, and the first power line is located between the first initial signal line and the second initial signal line.

8. The display substrate according to claim 6 or 7, wherein: The plurality of first pixel circuits in the display island area are connected to the same light emitting control line, and an extending direction of the light emitting control line intersects with an extending direction of the first power line.

9. The display substrate according to any one of claims 6 to 8, wherein: The display island area includes four first pixel circuits, which are arranged in a 2×2 array, and active layers of the four first pixel circuits are symmetrically arranged about a first midline of the four first pixel circuits in a first direction.

10. The display substrate according to any one of claims 6 to 8, wherein: The display island area includes three first pixel circuits, and the three first pixel circuits are arranged in sequence along a first direction.

11. The display substrate according to any one of claims 1 to 10, further comprising: A light shielding layer located on a side of the first pixel circuit and the second pixel circuit close to the substrate; The orthographic projections of the light shielding layer and the first light-transmitting area on the substrate do not overlap; The light shielding layer at least includes: a first light shielding block located in the display island area; The orthographic projection of the first light shielding block on the substrate covers the plurality of first pixel circuits in the display island area and the orthographic projection of the signal lines connected to the plurality of first pixel circuits on the substrate.

12. The display substrate according to claim 11, wherein: The first light shielding blocks of adjacent display island regions are interconnected as an integrated structure.

13. The display substrate according to claim 11, wherein: The first light shielding blocks of adjacent display island areas are independently arranged.

14. The display substrate according to any one of claims 11 to 13, wherein: The edge of the first light shielding block close to the first light-transmitting area is an arc-shaped edge.

15. The display substrate according to any one of claims 1 to 10, further comprising: a light emitting structure layer located on a side of the plurality of first pixel circuits and the plurality of second pixel circuits away from the substrate, the light emitting structure layer comprising a cathode layer, and the cathode layer and the orthographic projection of the first light-transmitting area on the substrate do not overlap; The cathode layer at least includes: cathodes of the plurality of first light-emitting elements; The cathodes of the multiple first light-emitting elements in the display island area are an integrated structure that is interconnected, and the integrated structure of the cathodes of the multiple first light-emitting elements in the display island area covers the multiple first pixel circuits in the display island area and the orthographic projection of the signal lines connected to the multiple first pixel circuits on the substrate.

16. The display substrate according to claim 15, wherein: The cathode layer further includes: cathodes of the plurality of second light emitting elements; the cathodes of the plurality of first light emitting elements in the first sub-region and the cathodes of the plurality of second light emitting elements in the second sub-region are connected to form a grid.

17. The display substrate according to claim 15 or 16, further comprising: A light-shielding pixel definition layer is located on the side of the cathode layer close to the substrate, the light-shielding pixel definition layer is at least located in the first sub-area, and the orthographic projection of the cathode layer on the substrate covers the orthographic projection of the light-shielding pixel definition layer on the substrate.

18. The display substrate according to any one of claims 15 to 17, further comprising: A light shielding layer located on a side of the first pixel circuit and the second pixel circuit close to the substrate; The orthographic projections of the light shielding layer and the first light-transmitting area on the substrate do not overlap; The light shielding layer at least comprises: a plurality of light shielding strips located in the display island area; the orthographic projection of each light shielding strip on the substrate covers the orthographic projection of the channel region of the active layer of at least one transistor of the first pixel circuit on the substrate; The orthographic projection of the integrated structure of cathodes of the plurality of first light-emitting elements in the display island region on the substrate covers the orthographic projection of the plurality of light-shielding strips in the display island region on the substrate.

19. The display substrate according to any one of claims 1 to 18, wherein: The light transmittance of the first display area is greater than the light transmittance of the second display area, and the density of light-emitting elements in the second display area is the same as the density of light-emitting elements in the first display area.

20. The display substrate according to any one of claims 1 to 19, wherein: The first display area is in the shape of a long strip extending along a first direction, and the second sub-area is located between the first sub-area and the second display area in the first direction.

21. The display substrate according to any one of claims 1 to 20, wherein: The display island area includes: at least one first light emitting unit, wherein the first light emitting unit includes: a plurality of adjacent first light emitting elements; The second sub-area includes: a plurality of second light-emitting units, the second light-emitting units include: a plurality of adjacent second light-emitting elements; the number of first light-emitting elements in the first light-emitting unit is the same as the number of second light-emitting elements in the second light-emitting unit; at least three first light-emitting elements in the first light-emitting unit are configured to emit light of different colors, The at least three second light-emitting elements in the second light-emitting unit are configured to emit light of different colors; In the adjacent area of ​​the first sub-area and the second sub-area, along the first direction, the minimum distance between the first light-emitting unit and the second light-emitting unit is smaller than the distance between adjacent first light-emitting units, and larger than the distance between adjacent second light-emitting units.

22. A display device, comprising a display substrate as claimed in any one of claims 1 to 21, and a sensor located on a non-display surface side of the display substrate, wherein an orthographic projection of the sensor on the display substrate at least partially overlaps with a first display area of ​​the display substrate.

23. A display substrate, comprising: a first display area and a second display area located at at least one side of the first display area; The first display area includes: a first sub-area and a second sub-area located at least on one side of the first sub-area close to the second display area; The first sub-area comprises: a plurality of first pixel circuits and a plurality of first light-emitting elements arranged on a substrate, the plurality of first pixel circuits and the plurality of first light-emitting elements being electrically connected, and the first light-emitting elements and the connected first pixel circuits at least partially overlap with each other in orthographic projection on the substrate; The second sub-area includes: a plurality of second light-emitting elements disposed on the substrate; The second display area at least includes: a plurality of second pixel circuits arranged on the substrate; at least one second pixel circuit among the plurality of second pixel circuits is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements through a conductive connection line, and a spacing between the second light-emitting element and the connected second pixel circuit and an orthographic projection of the substrate is greater than 0; For the first light-emitting elements and the second light-emitting elements emitting the same color light in the first display area, along the first direction, the distance between adjacent first light-emitting elements emitting the same color light in the first sub-area is greater than the distance between adjacent second light-emitting elements emitting the same color light in the second sub-area.

24. The display substrate according to claim 23, wherein: Along the first direction, the distance between adjacent first light emitting elements emitting light of the same color in the first sub-region is 1.5 times to 2 times the distance between adjacent first light emitting elements emitting light of the same color in the second sub-region.

25. The display substrate according to claim 23, wherein: The first sub-area includes: a plurality of display island areas and a first light-transmitting area located between adjacent display island areas; The display island area at least includes: a first light emitting unit, the first light emitting unit includes: a plurality of adjacent first light emitting elements; The second sub-area at least includes: a plurality of second light-emitting units, the second light-emitting units include: a plurality of adjacent second light-emitting elements; the number of first light-emitting elements in the first light-emitting unit is the same as the number of second light-emitting elements in the second light-emitting unit; at least three first light-emitting elements in the first light-emitting unit are configured to emit light of different colors, and at least three second light-emitting elements in the second light-emitting unit are configured to emit light of different colors; In the adjacent area of ​​the first sub-area and the second sub-area, along the first direction, the minimum distance between the first light-emitting unit and the second light-emitting unit is smaller than the distance between adjacent first light-emitting units, and larger than the distance between adjacent second light-emitting units.

Images