Display panel and display device

Abstract

A display panel and a display device. The display panel comprises driver modules (GA1, GA12, GA22) and a driver integrated circuit (GI), wherein the driver integrated circuit (GI) is configured to provide a driver control signal for driver circuits by means of GOA signal lines (L11, L21, L31, L011, L021, L031, L012, L022, L032); the GOA signal lines (L11, L21, L31, L011, L021, L031, L012, L022, L032) comprise first GOA signal lines (L11, L21, L31) arranged between a display area (A0) and the driver integrated circuit (GI); at least some of the driver circuits comprised in the driver modules (GA1, GA12, GA22) are arranged in the display area (A0); the at least some of the driver circuits that are comprised in the driver modules (GA1, GA12, GA22) and are arranged in the display area (A0) are electrically connected to the driver integrated circuit (GI) by means of the first GOA signal lines (L11, L21, L31), and are configured to receive the driver control signal from the driver integrated circuit (GI); and the first GOA signal lines (L11, L21, L31) extend in a first direction. The display panel further comprises data lines, which are configured to provide a data voltage for a pixel circuit, the extension direction of the data lines being approximately the same as the first direction. The display panel and the display device are used for realizing a narrow lower rounded-corner border and a small size of a lower pad area.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In recent years, the market and customers have placed numerous new demands on the appearance of displays, with a larger screen-to-body ratio and narrower bezels being among the most common and pressing. Displays with extremely narrow bezels are not only aesthetically pleasing but also more practical. Currently, various methods are available to reduce bezels, such as GIP (in-plane shift register) and FIP (in-plane fan-out signal line) technologies, which have been gradually incorporated into products.

[0003] Usually, the GOA (Gate On Array, a gate drive circuit arranged on an array substrate) module and its signal lines are placed on the left and right borders and corners outside the display area of ​​the display panel. The IC (driver integrated circuit) and FPC (flexible circuit board) located in the lower pad (pad) area input signals to the GOA module through complex winding. GIP technology can significantly reduce the width of the border by compressing the size of the pixel circuit and placing at least part of the GOA circuit under the anode layer of the display area. When the GOA circuit is placed near the center of the display area, how to efficiently and conveniently lead out the signal lines to connect the IC and FPC in the lower pad area becomes a problem. At the same time, the client requires that the size of the lower pad area be as small as possible to make more space for other structures of the whole machine to avoid interference.

[0004] Summary of the Invention

[0005] In one aspect, an embodiment of the present disclosure provides a display panel, comprising a display area and a pixel circuit disposed in the display area; the display panel further comprising a driving module and a driving integrated circuit; the driving module comprising a plurality of driving circuits, the driving circuits being configured to provide driving signals to the pixel circuits; the driving integrated circuit being configured to provide driving control signals to the driving circuits via GOA signal lines; the GOA signal lines comprising a first GOA signal line disposed between the display area and the driving integrated circuit;

[0006] At least part of the driving circuit included in the driving module is arranged in the display area;

[0007] At least part of the driving circuit included in the driving module and arranged in the display area is electrically connected to the driving integrated circuit through the first GOA signal line, and is used to receive a driving control signal from the driving integrated circuit;

[0008] The first GOA signal line extends along a first direction;

[0009] The display panel further includes a data line, and the data line is used to provide a data voltage for the pixel circuit; the extending direction of the data line is substantially the same as the first direction.

[0010] Optionally, at least part of the driving circuits included in the driving module is arranged in the middle of the display area, and at least part of the driving circuits are arranged along the first direction.

[0011] Optionally, the at least part of the driving circuit included in the driving module is a first driving circuit;

[0012] The plurality of driving circuits included in the driving module except the first driving circuit are second driving circuits;

[0013] The driving integrated circuit and the first GOA signal line are arranged on a first side of the display area;

[0014] The plurality of second driving circuits included in the driving circuit are arranged on the second side and / or the third side of the display area; the second side and the third side are opposite sides.

[0015] Optionally, the GOA signal line further includes a second GOA signal line extending along a second direction; the first direction intersects with the second direction;

[0016] The first GOA signal line is electrically connected to the second GOA signal line;

[0017] The second GOA signal line is electrically connected to the driver integrated circuit;

[0018] The second GOA signal line is used to receive and transmit a driving control signal from the driving integrated circuit.

[0019] Optionally, on the first side of the display area, a fan-out area, a bending area, a box test area, and an area for arranging the driver integrated circuit are sequentially arranged in a direction away from the display area;

[0020] The second GOA signal line is arranged between the bending area and the box testing area.

[0021] Optionally, at least part of the first GOA signal lines are directly electrically connected to the driver integrated circuit for receiving a driving control signal from the driver integrated circuit.

[0022] Optionally, the GOA signal line further includes a second GOA signal line extending along a second direction; the first direction intersects with the second direction;

[0023] A portion of the first GOA signal line is electrically connected to the second GOA signal line;

[0024] The second GOA signal line is directly electrically connected to the second driving circuit, and is used to provide a driving control signal to the second driving circuit.

[0025] Optionally, the first GOA signal line is electrically connected to a port located in the middle of the driver integrated circuit.

[0026] Optionally, the GOA signal line further includes a second GOA signal line, and the second GOA signal line extends along a second direction; the first direction intersects the second direction;

[0027] The first GOA signal line is directly connected to the second GOA signal line;

[0028] On the first side of the display area, a fan-out area, a bending area, a box test area, and an area for arranging the driver integrated circuit are sequentially arranged in a direction away from the display area;

[0029] The second GOA signal line is arranged in the fan-out area;

[0030] The second GOA signal line is electrically connected to the driver integrated circuit.

[0031] Optionally, a plurality of the second driving circuits are arranged on the second side and the third side of the display area;

[0032] The first end of the second GOA signal line is electrically connected to the second driving circuit provided on the second side of the display area and the first port of the driving integrated circuit respectively;

[0033] The second end of the second GOA signal line is electrically connected to a second driving circuit disposed on a third side of the display area and a second port of the driving integrated circuit, respectively.

[0034] Optionally, a plurality of second driving circuits are arranged on the second side of the display area; the first end of the second GOA signal line is electrically connected to the second driving circuit arranged on the second side of the display area and the first port of the driving integrated circuit respectively; or,

[0035] A plurality of the second driving circuits are arranged on a third side of the display area;

[0036] The second end of the second GOA signal line is electrically connected to a driving circuit disposed on a third side of the display area and a second port of the driving integrated circuit, respectively.

[0037] Optionally, the display panel described in at least one embodiment of the present disclosure further includes a circuit board;

[0038] The circuit board is arranged on a side of the driver integrated circuit away from the display area;

[0039] The circuit board is electrically connected to the first drive circuit and the second drive circuit respectively, and is used to provide DC voltage signals to the first drive circuit and the second drive circuit respectively.

[0040] Optionally, the circuit board is further electrically connected to the driver integrated circuit, and is used to provide a DC voltage signal to the driver integrated circuit;

[0041] The driving integrated circuit is used to generate a driving control signal according to the DC voltage signal, and provide the driving control signal to the first driving circuit and the second driving circuit.

[0042] Optionally, all driving circuits included in the driving module are arranged in the display area;

[0043] The first GOA signal line is directly electrically connected to the driver integrated circuit and is used to receive a driving control signal from the driver integrated circuit.

[0044] Optionally, the display panel described in at least one embodiment of the present disclosure further includes a voltage signal line;

[0045] The voltage signal line is electrically connected to the driving circuit and is used to provide a DC voltage signal to the driving circuit.

[0046] Optionally, the voltage signal line is electrically connected to the driver integrated circuit, and is used to provide a DC voltage signal to the driver integrated circuit;

[0047] The driving integrated circuit is used to generate a driving control signal according to the DC voltage signal, and provide the driving control signal to the driving circuit.

[0048] Optionally, the display panel according to at least one embodiment of the present disclosure further includes a circuit board disposed on the driving integrated circuit away from the display area;

[0049] The circuit board is electrically connected to the voltage signal line and is used to provide the DC voltage signal to the voltage signal line.

[0050] In a second aspect, an embodiment of the present disclosure further provides a display device comprising the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] FIG1A is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0052] FIG1B is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0053] FIG1C is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0054] FIG2 is a schematic diagram of various regions of a display panel;

[0055] FIG3A is a layout diagram of a portion of a lower pad region of a display panel according to at least one embodiment of the present disclosure;

[0056] FIG3B is a layout diagram of the first gate metal layer in FIG3A ;

[0057] FIG3C is a layout diagram of the second gate metal layer in FIG3A ;

[0058] FIG3D is a layout diagram of the first source / drain metal layer in FIG3A ;

[0059] FIG3E is a layout diagram of the second source / drain metal layer in FIG3A ;

[0060] FIG4A is a layout diagram of a first gate metal layer in at least one embodiment of the present disclosure;

[0061] FIG4B is a layout diagram of a second gate metal layer in at least one embodiment of the present disclosure;

[0062] FIG5A is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0063] FIG5B is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0064] FIG5C is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0065] FIG5D is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0066] FIG5E is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0067] FIG6A is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0068] FIG6B is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0069] FIG6C is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0070] FIG7A is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0071] FIG7B is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0072] FIG7C is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0073] FIG8A is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0074] FIG8B is a structural diagram of a display panel according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0075] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0076] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0077] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0078] The display panel according to the embodiment of the present disclosure includes a display area and a pixel circuit arranged in the display area; the display panel also includes a driving module and a driving integrated circuit; the driving module includes a plurality of driving circuits, the driving circuits are used to provide driving signals for the pixel circuits; the driving integrated circuit is used to provide driving control signals to the driving circuits via GOA signal lines; the GOA signal lines include a first GOA signal line arranged between the display area and the driving integrated circuit;

[0079] At least part of the driving circuit included in the driving module is arranged in the display area;

[0080] At least part of the driving circuit included in the driving module and arranged in the display area is electrically connected to the driving integrated circuit through the first GOA signal line, and is used to receive a driving control signal from the driving integrated circuit;

[0081] The first GOA signal line extends along a first direction;

[0082] The display panel further includes a data line, and the data line is used to provide a data voltage for the pixel circuit; the extending direction of the data line is substantially the same as the first direction.

[0083] During specific implementation, the first direction may be a vertical direction, but is not limited thereto.

[0084] In at least one embodiment of the present disclosure, the extending direction of the data line being substantially the same as the first direction may refer to:

[0085] The extending direction of the data line is the same as the first direction; or,

[0086] The angle between the extending direction of the data line and the first direction is less than 5 degrees;

[0087] But it is not limited to this.

[0088] In the relevant technologies, the market and customers have put forward many requirements for the appearance of displays, and narrower borders are one of the most common and urgent requirements. Displays with extremely narrow borders are not only beautiful but also more practical. Currently, there are many ways to narrow the borders. Under normal circumstances, the GOA (Gate On Array, a gate drive circuit arranged on an array substrate) circuit and its signal lines are placed on the left and right borders and corners outside the AA area (effective display area) of the OLED (organic light emitting diode) display. The driver integrated circuit and FPC (flexible circuit board) located on the lower side of the display panel input signals to the GOA circuit through leads, which is not conducive to achieving a narrow lower rounded border and a small lower pad (soldering pad) area size.

[0089] Based on the above problems, the embodiment of the present disclosure applies GIP technology to set at least part of the driving circuit included in the driving module in the display area (in the display area, at least part of the driving circuit included in the driving module is set below the anode layer), and electrically connect the at least part of the driving circuit to the driving integrated circuit through a first GOA signal line extending along a first direction, thereby reducing the space occupied by the GOA signal line, achieving a narrower lower rounded corner frame, and a smaller size of the lower pad area, which not only improves the screen-to-body ratio, but also reserves space to provide more solutions for the overall design. In at least one embodiment of the present disclosure, at least part of the driving circuit included in the driving module is set in the middle of the display area, but is not limited to this; in actual operation, at least part of the driving circuit can also be located on the left half and / or right half of the display panel;

[0090] At least part of the driving circuits are arranged along a first direction.

[0091] In a specific implementation, when at least part of the driving circuit is arranged in the middle of the display area, only one driving circuit can be set corresponding to each row of pixel circuits. The driving circuit is electrically connected to the middle of a row of scan lines to provide a scanning signal for the scan lines, which is beneficial to reducing the number of driving circuits used and thereby reducing the number of connection lines between the driving circuits and the driving integrated circuits.

[0092] In at least one embodiment of the present disclosure, the at least part of the driving circuit included in the driving module is a first driving circuit;

[0093] The plurality of driving circuits included in the driving module except the first driving circuit are second driving circuits;

[0094] The driving integrated circuit and the first GOA signal line are arranged on a first side of the display area;

[0095] The plurality of second driving circuits included in the driving circuit are arranged on the second side and / or the third side of the display area; the second side and the third side are opposite sides.

[0096] In a specific implementation, the first driving circuit included in the driving module is arranged in the display area, and the second driving circuit included in the driving module is arranged on the second side and / or the third side of the display area, and the second side and the third side are opposite sides; for example, the first side can be the lower side, the second side can be the left side, and the third side can be the right side.

[0097] In at least one embodiment of the present disclosure, the first driving circuit may be one of a driving circuit for providing an N-type driving signal, a driving circuit for providing a P-type driving signal, and a driving circuit for providing a light-emitting control signal, but is not limited thereto.

[0098] The driver integrated circuit may provide corresponding driving control signals to the first driver circuit and the second driver circuit respectively. For example, the driving control signals may include a clock signal, a start signal, a frame start signal, etc.

[0099] The driving integrated circuit may also provide a driving control signal to the first driving circuit and the second driving circuit simultaneously. For example, the driving control signal may be a strobe signal; the strobe signal may be used to control the display of sub-areas.

[0100] In at least one embodiment of the present disclosure, the GOA signal line further includes a second GOA signal line extending along a second direction; the first direction intersects the second direction;

[0101] The first GOA signal line is electrically connected to the second GOA signal line;

[0102] The second GOA signal line is electrically connected to the driver integrated circuit;

[0103] The second GOA signal line is used to receive and transmit a driving control signal from the driving integrated circuit.

[0104] In a specific implementation, the GOA signal line may further include a second GOA signal line extending along a second direction, where the second direction may be, for example, a horizontal direction, but is not limited thereto; the second GOA signal line receives and transmits a driving control signal from the driving integrated circuit.

[0105] Optionally, the driving control signal may be, for example, a clock signal, a start signal, or other signal used to control the operation of the driving circuit.

[0106] The display panel according to at least one embodiment of the present disclosure may further include a circuit board;

[0107] The circuit board is arranged on a side of the driver integrated circuit away from the display area;

[0108] The circuit board is electrically connected to the first drive circuit and the second drive circuit respectively, and is used to provide DC voltage signals to the first drive circuit and the second drive circuit respectively.

[0109] In a specific implementation, the driver integrated circuit and the circuit board can both be arranged in the lower pad area of ​​the display panel, the lower pad area can be arranged on the lower side of the display area, and the circuit board can be arranged on the side of the driver integrated circuit away from the display area; the circuit board can be used to provide a DC voltage signal for the first driver circuit and the second driver circuit, and the DC voltage signal can, for example, include a high voltage signal and a low voltage signal, but is not limited to this.

[0110] In at least one embodiment of the present disclosure, the circuit board is further electrically connected to the driver integrated circuit, and is used to provide a DC voltage signal to the driver integrated circuit;

[0111] The driving integrated circuit is used to generate a driving control signal according to the DC voltage signal, and provide the driving control signal to the first driving circuit and the second driving circuit.

[0112] In a specific implementation, the circuit board may further provide a DC voltage signal to the driver integrated circuit, and the driver integrated circuit generates a driving control signal according to the DC voltage signal.

[0113] As shown in FIG1A , the display panel is labeled P1, the display area is labeled A0, the first driving module is labeled GA1, and the first driving module GA1 includes a multi-stage first driving circuit, the first second driving module GA12 is labeled GA12, and the first second driving module GA12 includes a multi-stage second driving circuit, the second second driving module GA22 is labeled GA22, and the second second driving module GA22 includes a multi-stage second driving circuit;

[0114] GA1 is set in the middle of the display area A0, GA12 and GA22 are set in the peripheral area, GA12 is set on the left side of the display area A0, and GA22 is set on the right side of the display area A0;

[0115] GA1 is electrically connected to the driving integrated circuit GI through a first first GOA signal line L11 extending in the vertical direction and a first second GOA signal line L12 extending in the horizontal direction;

[0116] GA1 is electrically connected to the driving integrated circuit GI through a second first GOA signal line L21 extending in the vertical direction and a second second GOA signal line L22 extending in the horizontal direction;

[0117] GA1 is electrically connected to the driving integrated circuit GI through a third first GOA signal line L31 extending in the vertical direction and a third second GOA signal line L32 extending in the horizontal direction;

[0118] The first first GOA signal line L11 and the first second GOA signal line L12 may be used to provide a clock signal;

[0119] The second first GOA signal line L21 and the second second GOA signal line L22 may be used to provide a start signal;

[0120] The third first GOA signal line L31 and the third second GOA signal line L32 may be used to provide a strobe signal;

[0121] The driving integrated circuit GI is arranged at the lower side of the display area A0;

[0122] L11 is electrically connected to L12, L21 is electrically connected to L22, and L31 is electrically connected to L32;

[0123] L12 is electrically connected to the port of the driver integrated circuit GI near the left end, and L12 is electrically connected to the port of the driver integrated circuit GI near the right end; L22 is electrically connected to the port of the driver integrated circuit GI near the left end, and L22 is electrically connected to the port of the driver integrated circuit GI near the right end; L32 is electrically connected to the port of the driver integrated circuit GI near the left end, and L32 is electrically connected to the port of the driver integrated circuit GI near the right end;

[0124] The first second driving module GA12 is electrically connected to the third second GOA signal line L32, and the second second driving module GA22 is electrically connected to the third second GOA signal line L32. The first second driving module GA12 and the second second driving module GA22 receive the selection signal through the third second GOA signal line L32.

[0125] In at least one embodiment of the present disclosure, the display panel may be a local frequency conversion display panel, and GA1, GA12, and GA22 may share a strobe signal, but the present invention is not limited thereto.

[0126] As shown in FIG1A , the line labeled L011 is the first first signal line, the line labeled L021 is the second first signal line, and the line labeled L031 is the third first signal line;

[0127] The line labeled L012 is the first second signal line, the line labeled L022 is the second second signal line, and the line labeled L032 is the third second signal line;

[0128] L011, L021, L031, L012, L022 and L032 can all be GOA signal lines;

[0129] GA12 is electrically connected to L32 via L031, and GA22 is electrically connected to L32 via L032;

[0130] GA12 can receive a clock signal from the driver integrated circuit GI through L011, and GA12 can receive a start signal from the driver integrated circuit GI through L021;

[0131] GA22 may receive a clock signal from the driving integrated circuit GI through L012 , and GA22 may receive a start signal from the driving integrated circuit GI through L022 .

[0132] FIG1B is a schematic diagram based on FIG1A , without labeling the signal lines.

[0133] In a specific implementation, the number of GOA signal lines between GA1 and the driving integrated circuit GI is not limited to three, and can be greater than three;

[0134] The number of GOA signal lines between GA12 and the driver integrated circuit GI is not limited to three and can be greater than three;

[0135] The number of GOA signal lines between the GA22 and the driving integrated circuit GI is not limited to three, and can be greater than three.

[0136] In at least one embodiment of the display panel shown in Figures 1A and 1B, GA1 is set in the display area A0, and GA1 is electrically connected to the driving integrated circuit GI through L11, L21 and L31 extending in the vertical direction, thereby reducing the space occupied by the GOA signal line and achieving a narrower lower rounded border and a smaller lower pad area size.

[0137] In at least one embodiment shown in FIG. 1A and FIG. 1B , the second GOA signal line L2 may be disposed between the bending area and the box test area.

[0138] In at least one embodiment shown in FIG. 1A and FIG. 1B of the present disclosure, the first driving module GA1 is placed in the middle of the display area A0, the first second driving module GA12 is arranged at the left frame of the display panel, and the second second driving module GA22 is arranged at the right frame of the display panel. The first driving module GA1 placed in the middle of the display area A0 is electrically connected to the driving integrated circuit GI via a first GOA signal line extending in the vertical direction and a second GOA signal line extending in the horizontal direction between the bending area and the box test area, from a port near the left end of the driving integrated circuit GI and a port near the right end of the driving integrated circuit GI, receiving a driving control signal from the driving integrated circuit GI, without having to change the driving integrated circuit GI to facilitate design changes. At least one embodiment of the display panel shown in FIG. 1A and FIG. 1B of the present disclosure can reduce the space occupied by the GOA signal line in the lower corner frame, fully utilize the space in the lower pad area, reduce the size of the lower pad area, and thus improve the screen-to-body ratio. In at least one embodiment of the display panel shown in FIG. 1 of the present disclosure, the GOA signal line uses a film layer that does not interfere with other units in the current area as much as possible. For example, the second GOA signal line can be formed in the second source / drain metal layer, but is not limited thereto.

[0139] In at least one embodiment shown in FIG. 1A and FIG. 1B of the present disclosure, the second GOA signal line may also be electrically connected to a port provided at the left end portion of the driver integrated circuit GI and a port provided at the right end portion of the driver integrated circuit GI, but is not limited thereto.

[0140] As shown in FIG1C , based on at least one embodiment of the display panel shown in FIG1B , the display panel according to at least one embodiment of the present disclosure may further include a circuit board F1 ;

[0141] The circuit board F1 is disposed on a side of the driver integrated circuit GI away from the display area A0;

[0142] The circuit board F1 is electrically connected to the first driving module GA1, the first second driving module GA12, and the second second driving module GA22, respectively, and is used to provide DC voltage signals to the first driving module GA1, the first second driving module GA12, and the second second driving module GA22, respectively. For example, the DC voltage signals provided by the circuit board F1 to each driving module may include a high voltage signal VGH, a first low voltage signal LVGL, and a second low voltage signal VGL, but are not limited thereto.

[0143] The circuit board F1 is further electrically connected to the driver integrated circuit GI and is configured to provide a DC voltage signal to the driver integrated circuit GI. For example, the DC voltage signal provided by the circuit board F1 to the driver integrated circuit GI may include, but is not limited to, at least one of a high voltage signal VGH, a first low voltage signal LVGL, a second low voltage signal VGL, a high level signal VDD, and a low level signal VSS.

[0144] The driving integrated circuit GI is configured to generate a driving control signal according to the DC voltage signal, and provide the driving control signal to the first driving circuit and the second driving circuit.

[0145] In a specific implementation, the driving integrated circuit GI may also be used to provide data voltages for data lines disposed in the display area;

[0146] The circuit board F1 is used to provide a DC voltage signal to the driving integrated circuit GI, so that the driving integrated circuit GI generates a driving control signal according to the DC voltage signal;

[0147] The circuit board F1 is used to provide a DC voltage signal to each driving module, so that each driving module generates a driving signal according to the DC voltage signal.

[0148] In FIG1C , the line labeled L14 is the first DC signal transmission line, the line labeled L24 is the second DC signal transmission line, the line labeled L15 is the third DC signal transmission line, and the line labeled L25 is the fourth DC signal transmission line;

[0149] The circuit board F1 provides a DC voltage signal to GA12 through L14, provides a DC voltage signal to GA22 through L24, and provides a DC voltage signal to GI through L15 and L25.

[0150] In FIG. 1C , the voltage signal line for transmitting the DC voltage signal between the circuit board F1 and the first driving module GA1 is not shown.

[0151] Optionally, on the first side of the display area, a fan-out area, a bending area, a box test area, and an area for arranging the driver integrated circuit are sequentially arranged in a direction away from the display area;

[0152] The second GOA signal line is arranged between the bending area and the box testing area.

[0153] In a specific implementation, a fan-out region, a bending region, a box test region, and a region for arranging the driver integrated circuit may be sequentially arranged on a first side of the display area, along a direction away from the display area. The second GOA signal line may be arranged between the bending region and the box test region. Optionally, the first side may be a bottom side, but is not limited thereto.

[0154] As shown in FIG2 , the area labeled A0 is the display area, the area labeled F0 is the fan-out area, the area labeled B1 is the bending area, the area labeled C1 is the box test area, and the area labeled CP is where the driver integrated circuit is set;

[0155] On the lower side of the display area A0, along the direction away from the display area A0, a fan-out area F0, a bending area B1, a box test area C1 and an area CP for arranging the driver integrated circuit are sequentially arranged.

[0156] FIG. 3A is a layout diagram of a portion of a lower pad region of a display panel according to at least one embodiment of the present disclosure.

[0157] In FIG3A , the area labeled A1 is a portion of the signal line area where the second GOA signal line is set, the area labeled C11 is a portion of the box test area, and the area labeled CP1 is a portion of the area where the driver integrated circuit is set.

[0158] Figure 3B is a layout diagram of the first gate metal layer in Figure 3A, Figure 3C is a layout diagram of the second gate metal layer in Figure 3A, Figure 3D is a layout diagram of the first source and drain metal layer in Figure 3A, and Figure 3E is a layout diagram of the second source and drain metal layer in Figure 3A.

[0159] In FIG3E , the region labeled A1 is where part of the second GOA signal line is set. Part of the second GOA signal line is set within A1, and the second GOA signal line is formed in the second source and drain metal layer.

[0160] As shown in FIG3A , FIG3D and FIG3E , the second GOA signal line formed in the second source-drain metal layer is electrically connected to the adapter line formed in the first source-drain metal layer and extending in the vertical direction;

[0161] As shown in FIG3A to FIG3E , the connecting wire formed on the first source-drain metal layer is electrically connected to the connecting wire formed on the second gate metal layer and extending in the horizontal direction;

[0162] As shown in FIG. 3A to FIG. 3E , the connecting wire formed on the second gate metal layer and the connecting wire formed on the first gate metal layer are electrically connected to the driver integrated circuit.

[0163] FIG4A is a layout diagram of a first gate metal layer in at least one embodiment of the present disclosure, and FIG4B is a layout diagram of a second gate metal layer in at least one embodiment of the present disclosure.

[0164] Compared with FIG3B , in at least one embodiment shown in FIG4A , a plurality of transverse signal lines are reduced, and the signal lines may be GOA signal lines disposed between the driving module and the driving integrated circuit GI in the peripheral area;

[0165] Compared with FIG3C , in at least one embodiment shown in FIG4B , multiple rows of horizontal signal lines are reduced. The signal lines may be GOA signal lines disposed between the driving module and the driving integrated circuit GI in the peripheral area.

[0166] In at least one embodiment of the present disclosure, GA1 is disposed in the display area, and GA1 receives a GOA control signal from the driver integrated circuit GI through a vertical GOA signal line, so that the number of GOA signal lines between the driver module disposed in the peripheral area and the driver integrated circuit GI can be reduced.

[0167] In at least one embodiment of the present disclosure, at least part of the first GOA signal lines are directly electrically connected to the driver integrated circuit for receiving a driving control signal from the driver integrated circuit.

[0168] In a specific implementation, at least part of the first GOA signal lines may be directly electrically connected to a driver integrated circuit to receive a driving control signal from the driver integrated circuit.

[0169] In at least one embodiment of the present disclosure, the GOA signal line further includes a second GOA signal line extending along a second direction; the first direction intersects the second direction;

[0170] A portion of the first GOA signal line is electrically connected to the second GOA signal line.

[0171] In a specific implementation, the GOA signal line may further include a second GOA signal line extending along a second direction. The second direction may be, for example, a horizontal direction, but is not limited thereto.

[0172] In at least one embodiment of the present disclosure, the first GOA signal line can be electrically connected to a port located in the middle of the driver integrated circuit to shorten the length of the connecting line of the first GOA signal line, reduce the length of the winding of the first GOA signal line, and reduce the load of the first GOA signal line.

[0173] As shown in FIG5A , the display panel is labeled P1, the display area is labeled A0, the first driving module is labeled GA1, and the first driving module GA1 includes a multi-stage first driving circuit, the first second driving module is labeled GA12, and the first second driving module includes a multi-stage second driving circuit, and the second second driving module GA22 includes a multi-stage second driving circuit;

[0174] GA1 is set in the middle of the display area A0, GA12 and GA22 are set in the peripheral area, GA12 is set on the left side of the display area A0, and GA22 is set on the right side of the display area A0;

[0175] GA1 is electrically connected to a port located in the middle of the driver integrated circuit GI via a first first GOA signal line L11 extending in a vertical direction. GA1 receives a clock signal from the driver integrated circuit GI via L11.

[0176] GA1 is electrically connected to a port located in the middle of the driver integrated circuit GI via a second first GOA signal line L21 extending in the vertical direction; GA1 receives a start signal from the driver integrated circuit GI via L21;

[0177] GA1 is electrically connected to a port located in the middle of the driver integrated circuit GI through a third first GOA signal line L31 extending in the vertical direction. GA1 receives a strobe signal from the driver integrated circuit GI through L31.

[0178] L31 is electrically connected to a second GOA signal line L2 extending in the horizontal direction, and L2 is electrically connected to GA12 and GA22 respectively, for providing a strobe signal to GA12 and GA22;

[0179] GA12, GA22 and GA1 share the same selection signal.

[0180] As shown in FIG5A , the line labeled L011 is the first first signal line, the line labeled L021 is the second first signal line, and the line labeled L031 is the third first signal line;

[0181] The line labeled L012 is the first second signal line, the line labeled L022 is the second second signal line, and the line labeled L032 is the third second signal line;

[0182] L011, L021, L031, L012, L022 and L032 can all be GOA signal lines;

[0183] GA12 is electrically connected to L2 via L031, and GA22 is electrically connected to L2 via L032;

[0184] GA12 can receive a clock signal from the driver integrated circuit GI through L011, and GA12 can receive a start signal from the driver integrated circuit GI through L021;

[0185] GA22 may receive a clock signal from the driving integrated circuit GI through L012 , and GA22 may receive a start signal from the driving integrated circuit GI through L022 .

[0186] In at least one embodiment shown in FIG5A , the driving integrated circuit GI is disposed below the display area A0 ;

[0187] The first driving module GA1 arranged in the display area is directly electrically connected to the driving integrated circuit GI through L11, L21 and L31 extending in the vertical direction, thereby reducing the winding length of the GOA signal line and reducing the load on the GOA signal line. At least one embodiment of the display panel shown in Figure 5A can reduce the space occupied by the GOA signal line in the lower corner frame, reduce the size of the lower pad area, and make full use of the space in the middle section of the driving integrated circuit GI, further shortening the width of the driving integrated circuit GI and the size of the lower pad area.

[0188] In at least one embodiment of the display panel shown in FIG. 5A , the GOA signal lines are preferably formed using a film layer that does not interfere with other units in the current area. The design of other units may also be modified to match the GOA signal lines.

[0189] In at least one embodiment shown in FIG. 5A , the second GOA signal line L2 may be disposed between the bending area and the box test area, but the present invention is not limited thereto.

[0190] Compared with at least one embodiment shown in FIG. 1A , in at least one embodiment shown in FIG. 5A , only one second GOA signal line extending in the horizontal direction is provided, thereby reducing the number of second GOA signal lines provided in the lower pad area and reducing the size of the lower pad area.

[0191] FIG5B is a schematic diagram based on FIG5A , without labeling the signal lines.

[0192] In a specific implementation, the number of GOA signal lines between GA1 and the driving integrated circuit GI is not limited to three, and can be greater than three;

[0193] The number of GOA signal lines between GA12 and the driver integrated circuit GI is not limited to three and can be greater than three;

[0194] The number of GOA signal lines between the GA22 and the driving integrated circuit GI is not limited to three, and can be greater than three.

[0195] As shown in FIG5C , the display panel according to at least one embodiment of the present disclosure may further include a circuit board F1;

[0196] The circuit board F1 is disposed on a side of the driving integrated circuit GI away from the display area A0;

[0197] The circuit board F1 is electrically connected to the first driving module GA1, the first second driving module GA12 and the second second driving module GA22, respectively, for providing DC voltage signals to the first driving module GA1, the first second driving module GA12 and the second second driving module GA22;

[0198] The circuit board F1 is also electrically connected to the driver integrated circuit GI, and is used to provide a DC voltage signal to the driver integrated circuit GI;

[0199] The driving integrated circuit GI is configured to generate a driving control signal according to the DC voltage signal, and provide the driving control signal to the first driving module GA1 , the first second driving module GA12 , and the second second driving module GA22 .

[0200] In FIG5C , the line labeled L14 is the first DC signal transmission line, the line labeled L24 is the second DC signal transmission line, the line labeled L15 is the third DC signal transmission line, and the line labeled L25 is the fourth DC signal transmission line;

[0201] The circuit board F1 provides a DC voltage signal to GA12 through L14, provides a DC voltage signal to GA22 through L24, and provides a DC voltage signal to GI through L15 and L25.

[0202] In FIG5C , the voltage signal lines for transmitting DC voltage signals between the circuit board F1 and the first driver module GA1 are not shown. As shown in FIG6A , the display panel is labeled P1, the display area is labeled A0, the first driver module is labeled GA1, and the first driver module GA1 includes multiple first driver circuits. The first second driver module is labeled GA12, and the first second driver module includes multiple second driver circuits. The second second driver module is labeled GA22, and the second second driver module GA22 includes multiple second driver circuits.

[0203] GA1 is set in the middle of the display area A0, GA12 and GA22 are set in the peripheral area, GA12 is set on the left side of the display area A0, and GA22 is set on the right side of the display area A0;

[0204] GA1 is electrically connected to a port located in the middle of the driver integrated circuit GI via a first first GOA signal line L11 extending in a vertical direction. GA1 receives a clock signal from the driver integrated circuit GI via L11.

[0205] GA1 is electrically connected to a port located in the middle of the driver integrated circuit GI via a second first GOA signal line L21 extending in the vertical direction; GA1 receives a start signal from the driver integrated circuit GI via L21;

[0206] GA1 is electrically connected to a port provided in the middle of the driving integrated circuit GI through a third first GOA signal line L31 extending in the vertical direction, and GA1 receives a strobe signal from the driving integrated circuit GI through L31.

[0207] Optionally, the second driving module may be disposed on the left and / or right side of the display area A0.

[0208] As shown in FIG5D , the display panel is labeled P1, the display area is labeled A0, the first driving module is labeled GA1, and the first driving module GA1 includes a multi-stage first driving circuit. The first second driving module is labeled GA12, and the first second driving module includes a multi-stage second driving circuit.

[0209] GA1 is set in the middle of the display area A0, GA12 is set in the peripheral area, and GA12 is set on the left side of the display area A0;

[0210] GA1 is electrically connected to a port located in the middle of the driver integrated circuit GI via a first first GOA signal line L11 extending in a vertical direction. GA1 receives a clock signal from the driver integrated circuit GI via L11.

[0211] GA1 is electrically connected to a port located in the middle of the driver integrated circuit GI via a second first GOA signal line L21 extending in the vertical direction; GA1 receives a start signal from the driver integrated circuit GI via L21;

[0212] GA1 is electrically connected to a port located in the middle of the driver integrated circuit GI through a third first GOA signal line L31 extending in the vertical direction. GA1 receives a strobe signal from the driver integrated circuit GI through L31.

[0213] L31 is electrically connected to the second GOA signal line L2 extending in the horizontal direction, L2 is electrically connected to GA12, and is used to provide a strobe signal for GA12 and GA22;

[0214] GA12 and GA1 share the same selection signal.

[0215] As shown in FIG5D , the line labeled L011 is the first first signal line, the line labeled L021 is the second first signal line, and the line labeled L031 is the third first signal line;

[0216] L011, L021 and L031 can all be GOA signal lines;

[0217] GA12 is electrically connected to L2 through L031;

[0218] GA12 may receive a clock signal from the driving integrated circuit GI through L011 , and GA12 may receive a start signal from the driving integrated circuit GI through L021 .

[0219] In at least one embodiment shown in FIG5D , the driving integrated circuit GI is disposed below the display area A0;

[0220] The first driving module GA1 arranged in the display area is directly electrically connected to the driving integrated circuit GI through L11, L21 and L31 extending in the vertical direction, thereby reducing the winding length of the GOA signal line and reducing the load on the GOA signal line. At least one embodiment of the display panel shown in Figure 5D can reduce the space occupied by the GOA signal line in the lower corner frame, reduce the size of the lower pad area, and make full use of the space in the middle section of the driving integrated circuit GI, further shortening the width of the driving integrated circuit GI and the size of the lower pad area.

[0221] As shown in FIG5E , the display panel is labeled P1, the display area is labeled A0, the first driving module is labeled GA1, and the first driving module GA1 includes a multi-stage first driving circuit. The second driving module GA22 includes a multi-stage second driving circuit.

[0222] GA1 is set in the middle of the display area A0, GA22 is set in the peripheral area, and GA22 is set on the right side of the display area A0;

[0223] GA1 is electrically connected to a port located in the middle of the driver integrated circuit GI via a first first GOA signal line L11 extending in a vertical direction. GA1 receives a clock signal from the driver integrated circuit GI via L11.

[0224] GA1 is electrically connected to a port located in the middle of the driver integrated circuit GI via a second first GOA signal line L21 extending in the vertical direction; GA1 receives a start signal from the driver integrated circuit GI via L21;

[0225] GA1 is electrically connected to a port located in the middle of the driver integrated circuit GI through a third first GOA signal line L31 extending in the vertical direction. GA1 receives a strobe signal from the driver integrated circuit GI through L31.

[0226] L31 is electrically connected to the second GOA signal line L2 extending in the horizontal direction, L2 is electrically connected to GA22, and is used to provide a strobe signal to GA22;

[0227] GA22 and GA1 share the same selection signal.

[0228] As shown in FIG5E , the line labeled L012 is the first second signal line, the line labeled L022 is the second second signal line, and the line labeled L032 is the third second signal line;

[0229] L012, L022 and L032 can all be GOA signal lines;

[0230] GA22 is electrically connected to L2 through L032;

[0231] GA22 may receive a clock signal from the driving integrated circuit GI through L012 , and GA22 may receive a start signal from the driving integrated circuit GI through L022 .

[0232] In at least one embodiment shown in FIG5E , the driving integrated circuit GI is disposed below the display area A0;

[0233] The first driving module GA1 arranged in the display area is directly electrically connected to the driving integrated circuit GI through L11, L21 and L31 extending in the vertical direction, thereby reducing the winding length of the GOA signal line and reducing the load on the GOA signal line. At least one embodiment of the display panel shown in Figure 5E can reduce the space occupied by the GOA signal line in the lower corner frame, reduce the size of the lower pad area, and make full use of the space in the middle section of the driving integrated circuit GI, further shortening the width of the driving integrated circuit GI and the size of the lower pad area.

[0234] As shown in FIG6A , the line labeled L011 is the first first signal line, the line labeled L021 is the second first signal line, and the line labeled L031 is the third first signal line;

[0235] The line labeled L012 is the first second signal line, the line labeled L022 is the second second signal line, and the line labeled L032 is the third second signal line;

[0236] L011, L021, L031, L012, L022 and L032 can all be GOA signal lines;

[0237] GA12 can receive a clock signal from the driver integrated circuit GI through L011, and a start signal from the driver integrated circuit GI through L021; GA12 can receive a strobe signal from the driver integrated circuit GI through L031;

[0238] GA22 can receive a clock signal from the driving integrated circuit GI through L012 , and can receive a start signal from the driving integrated circuit GI through L022 ; GA22 can receive a strobe signal from the driving integrated circuit GI through L032 .

[0239] In at least one embodiment shown in FIG. 6A , GA1 and GA12 are not electrically connected to the same GOA signal line, GA1 and GA22 are not electrically connected to the same GOA signal line, GA1 receives a selection signal through L31, GA12 receives a selection signal through L031, and GA22 receives a selection signal through L032.

[0240] In at least one embodiment shown in FIG6A , the driver integrated circuit GI is disposed below the display area A0 ;

[0241] The first driving module GA1 arranged in the display area is directly electrically connected to the driving integrated circuit GI through L11, L21 and L31 extending in the vertical direction, thereby reducing the winding length of the GOA signal line and reducing the load on the GOA signal line. At least one embodiment of the display panel shown in Figure 6A can reduce the space occupied by the GOA signal line in the lower corner frame, reduce the size of the lower pad area, and make full use of the space in the middle section of the driving integrated circuit GI, further shortening the width of the driving integrated circuit GI and the size of the lower pad area.

[0242] In at least one embodiment of the display panel shown in FIG. 6A , the GOA signal lines are preferably formed using a film layer that does not interfere with other units in the current area. The design of other units may also be modified to match the GOA signal lines.

[0243] In at least one embodiment shown in FIG. 6A , the second GOA signal line L2 may be disposed between the bending area and the box test area, but the present invention is not limited thereto.

[0244] Compared with at least one embodiment shown in FIG. 1A , in at least one embodiment shown in FIG. 6A , no second GOA signal line extending in the horizontal direction is provided, thereby reducing the number of second GOA signal lines provided in the lower pad region and reducing the size of the lower pad region.

[0245] FIG6B is a schematic diagram based on FIG6A , without labeling the signal lines.

[0246] In a specific implementation, the number of GOA signal lines between GA1 and the driving integrated circuit GI is not limited to three, and can be greater than three;

[0247] The number of GOA signal lines between GA12 and the driver integrated circuit GI is not limited to three and can be greater than three;

[0248] The number of GOA signal lines between the GA22 and the driving integrated circuit GI is not limited to three, and can be greater than three.

[0249] As shown in FIG6C , the display panel according to at least one embodiment of the present disclosure may further include a circuit board F1;

[0250] The circuit board F1 is disposed on a side of the driver integrated circuit GI away from the display area A0;

[0251] The circuit board F1 is electrically connected to the first driving module GA1, the first second driving module GA12 and the second second driving module GA22, respectively, for providing DC voltage signals to the first driving module GA1, the first second driving module GA12 and the second second driving module GA22;

[0252] The circuit board F1 is also electrically connected to the driver integrated circuit GI, and is used to provide a DC voltage signal to the driver integrated circuit GI;

[0253] The driving integrated circuit GI is configured to generate a driving control signal according to the DC voltage signal, and provide the driving control signal to the first driving module GA1 , the first second driving module GA12 , and the second second driving module GA22 .

[0254] In FIG6C , the line labeled L14 is the first DC signal transmission line, the line labeled L24 is the second DC signal transmission line, the line labeled L15 is the third DC signal transmission line, and the line labeled L25 is the fourth DC signal transmission line;

[0255] The circuit board F1 provides a DC voltage signal to GA12 through L14, provides a DC voltage signal to GA22 through L24, and provides a DC voltage signal to GI through L15 and L25.

[0256] In FIG. 6C , the voltage signal line for transmitting the DC voltage signal between the circuit board F1 and the first driving module GA1 is not shown.

[0257] In at least one embodiment of the present disclosure, the GOA signal line further includes a second GOA signal line, and the second GOA signal line extends along a second direction; the first direction intersects the second direction;

[0258] The first GOA signal line is directly connected to the second GOA signal line;

[0259] On the first side of the display area, a fan-out area, a bending area, a box test area, and an area for arranging the driver integrated circuit are sequentially arranged in a direction away from the display area;

[0260] The second GOA signal line is arranged in the fan-out area;

[0261] The second GOA signal line is electrically connected to the driver integrated circuit.

[0262] As shown in FIG7A , the display panel is labeled P1, the display area is labeled A0, the first driving module is labeled GA1, and the first driving module GA1 includes a multi-stage first driving circuit, the first second driving module GA12 is labeled GA12, and the first second driving module GA12 includes a multi-stage second driving circuit, and the second second driving module GA22 is labeled GA22, and the second second driving module GA22 includes a multi-stage second driving circuit;

[0263] GA1 is set in the middle of the display area A0, GA12 and GA22 are set in the peripheral area, GA12 is set on the left side of the display area A0, and GA22 is set on the right side of the display area A0;

[0264] GA1 is electrically connected to the driving integrated circuit GI through a first first GOA signal line L11 extending in the vertical direction and a first second GOA signal line L12 extending in the horizontal direction;

[0265] GA1 is electrically connected to the driving integrated circuit GI through a second first GOA signal line L21 extending in the vertical direction and a second second GOA signal line L22 extending in the horizontal direction;

[0266] GA1 is electrically connected to the driving integrated circuit GI through a third first GOA signal line L11 extending in the vertical direction and a third second GOA signal line L12 extending in the horizontal direction;

[0267] GA1 is directly electrically connected to L11, and L11 is directly electrically connected to L12; GA1 is directly electrically connected to L21, and L21 is directly electrically connected to L22; GA1 is directly electrically connected to L31, and L31 is directly electrically connected to L32;

[0268] GA1 receives a clock signal from the driver integrated circuit GI through L11 and L12, a start signal from the driver integrated circuit GI through L21 and L22, and a strobe signal from the driver integrated circuit GI through L31 and L32.

[0269] The driving integrated circuit GI is arranged at the lower side of the display area A0;

[0270] L11, L21, and L31 are all located in the fan-out area;

[0271] L12, L22 and L32 are all set in the fan-out area to avoid setting the GOA signal line in the lower pad area, saving space in the lower frame, and facilitating the realization of a narrow lower rounded frame and a small lower pad (solder pad) area size.

[0272] As shown in FIG7A , the line labeled L011 is the first first signal line, the line labeled L021 is the second first signal line, and the line labeled L031 is the third first signal line;

[0273] The line labeled L012 is the first second signal line, the line labeled L022 is the second second signal line, and the line labeled L032 is the third second signal line;

[0274] L011, L021, L031, L012, L022 and L032 can all be GOA signal lines;

[0275] GA12 is electrically connected to L2 via L031, and GA22 is electrically connected to L2 via L032;

[0276] GA12 can receive a clock signal from the driver integrated circuit GI through L011, and GA12 can receive a start signal from the driver integrated circuit GI through L021;

[0277] GA22 may receive a clock signal from the driving integrated circuit GI through L012 , and GA22 may receive a start signal from the driving integrated circuit GI through L022 .

[0278] In at least one embodiment of the display panel shown in FIG. 7A , the GOA signal lines are preferably formed using a film layer that does not interfere with other units in the current area. The design of other units may also be modified to match the GOA signal lines.

[0279] In at least one embodiment of the display panel shown in FIG. 7A ,

[0280] Each second GOA signal line is electrically connected to a port close to the left end of the driving integrated circuit GI, and each second GOA signal line is electrically connected to a port close to the right end of the driving integrated circuit GI.

[0281] In at least one embodiment of the display panel shown in FIG7A , a GOA signal line is disposed above the bend region. The GOA signal line can be fabricated using film layers that do not interfere with the fan-out region, high-voltage lines, and low-voltage lines, such as a BSM layer or a third gate metal layer. At least one embodiment of the display panel shown in FIG7A of the present disclosure can implement the design of the GOA signal line without modifying the design of the lower pad region, thereby reducing the width of the lower corner bezel of the display panel and eliminating the need for a driver integrated circuit (GI) to assist in design changes.

[0282] In a specific implementation, the film layer associated with the fan-out area may include a first gate metal layer and a second gate metal layer, the film layer associated with the high voltage line and the low voltage line may include a first source-drain metal layer and a second source-drain metal layer, and the GOA signal line may be made of a film layer other than the first gate metal layer, the second gate metal layer, the first source-drain metal layer and the second source-drain metal layer.

[0283] FIG. 7B is a schematic diagram based on FIG. 7A , without labeling the signal lines.

[0284] In a specific implementation, the number of GOA signal lines between GA1 and the driving integrated circuit GI is not limited to three, and can be greater than three;

[0285] The number of GOA signal lines between GA12 and the driver integrated circuit GI is not limited to three and can be greater than three;

[0286] The number of GOA signal lines between the GA22 and the driving integrated circuit GI is not limited to three, and can be greater than three.

[0287] As shown in FIG7C , the display panel according to at least one embodiment of the present disclosure may further include a circuit board F1;

[0288] The circuit board F1 is disposed on a side of the driving integrated circuit GI away from the display area A0;

[0289] The circuit board F1 is electrically connected to the first driving module GA1, the first second driving module GA12 and the second second driving module GA22, respectively, for providing DC voltage signals to the first driving module GA1, the first second driving module GA12 and the second second driving module GA22;

[0290] The circuit board F1 is also electrically connected to the driver integrated circuit GI, and is used to provide a DC voltage signal to the driver integrated circuit GI;

[0291] The driving integrated circuit GI is configured to generate a driving control signal according to the DC voltage signal, and provide the driving control signal to the first driving module GA1 , the first second driving module GA12 , and the second second driving module GA22 .

[0292] In FIG7C , the line labeled L14 is the first DC signal transmission line, the line labeled L24 is the second DC signal transmission line, the line labeled L15 is the third DC signal transmission line, and the line labeled L25 is the fourth DC signal transmission line;

[0293] The circuit board F1 provides a DC voltage signal to GA12 through L14, provides a DC voltage signal to GA22 through L24, and provides a DC voltage signal to GI through L15 and L25.

[0294] In FIG. 7C , the voltage signal line for transmitting the DC voltage signal between the circuit board F1 and the first driving module GA1 is not shown;

[0295] The driving integrated circuit GI and the circuit board F1 are both disposed in the lower pad area.

[0296] Optionally, a plurality of the second driving circuits are arranged on the second side and the third side of the display area;

[0297] The first end of the second GOA signal line is electrically connected to the first port of the driver integrated circuit;

[0298] The second end of the second GOA signal line is electrically connected to the second port of the driver integrated circuit.

[0299] In a specific implementation, the first end of the second GOA signal line may be the left end of the second GOA signal line, and the second end of the second GOA signal line may be the right end of the second GOA signal line;

[0300] The left end portion of the second GOA signal line may be electrically connected to the first port of the driver integrated circuit;

[0301] The right end of the second GOA signal line may be electrically connected to the second port of the driver integrated circuit;

[0302] The first port of the driver integrated circuit may be a port close to the left end of the driver integrated circuit, or the first port of the driver integrated circuit may be a port provided at the left end of the driver integrated circuit;

[0303] The second port of the driver integrated circuit may be a port close to a right end portion of the driver integrated circuit, or the second port of the driver integrated circuit may be a port provided at the right end portion of the driver integrated circuit.

[0304] In at least one embodiment of the present disclosure, all driving circuits included in the driving module are arranged in the display area;

[0305] The first GOA signal line is directly electrically connected to the driver integrated circuit and is used to receive a driving control signal from the driver integrated circuit.

[0306] In a specific implementation, all driving circuits included in the driving module can be arranged in the display area and below the anode layer to fully reduce the left and right borders of the display panel, thereby facilitating the realization of the left border.

[0307] The display panel according to at least one embodiment of the present disclosure further includes a voltage signal line;

[0308] The voltage signal line is electrically connected to the driving circuit and is used to provide a DC voltage signal to the driving circuit.

[0309] In a specific implementation, the display panel may include a voltage signal line, and the voltage signal line provides a DC voltage signal to a driving circuit located in the display area.

[0310] In at least one embodiment of the present disclosure, the voltage signal line is electrically connected to the driver integrated circuit and is used to provide a DC voltage signal to the driver integrated circuit;

[0311] The driving integrated circuit is used to generate a driving control signal according to the DC voltage signal, and provide the driving control signal to the driving circuit.

[0312] During specific implementation, the voltage signal line may also provide a DC voltage signal for the driver integrated circuit.

[0313] The display panel according to at least one embodiment of the present disclosure further includes a circuit board disposed at a position above the driver integrated circuit and away from the display area;

[0314] The circuit board is electrically connected to the voltage signal line and is used to provide the DC voltage signal to the voltage signal line.

[0315] In a specific implementation, the display panel may further include a circuit board disposed below the driver integrated circuit, and the circuit board provides the DC voltage signal to the voltage signal line.

[0316] As shown in FIG8A , the display panel is labeled P1, the display area is labeled A0, and the first driving module is labeled GA1. The first driving circuit in the first driving module GA1 is all the driving circuits included in the driving module in the display panel.

[0317] GA1 is located in the middle of the display area A0;

[0318] GA1 is electrically connected to the driver integrated circuit GI through a first first GOA signal line L11 extending in a vertical direction; the first first GOA signal line L11 is directly electrically connected to a port provided in the middle of the driver integrated circuit GI;

[0319] GA1 is electrically connected to the driver integrated circuit GI via a second first GOA signal line L21 extending in the vertical direction; the second first GOA signal line L21 is directly electrically connected to a port provided in the middle of the driver integrated circuit GI;

[0320] GA1 is electrically connected to the driver integrated circuit GI via a third first GOA signal line L31 extending in a vertical direction; the third first GOA signal line L31 is directly electrically connected to a port disposed in the middle of the driver integrated circuit GI.

[0321] Optionally, the GOA control signal may include a clock signal, a start signal and a selection signal.

[0322] The driving integrated circuit GI provides a clock signal to the first driving module GA1 through the first first GOA signal line L11;

[0323] The driving integrated circuit GI provides a start signal to the first driving module GA1 through the second first GOA signal line L21;

[0324] The driving integrated circuit GI provides a gate signal to the first driving module GA1 through the third first GOA signal line L31.

[0325] As shown in FIG8B , the display panel according to at least one embodiment of the present disclosure may further include a circuit board F1;

[0326] The circuit board F1 is disposed on a side of the driver integrated circuit GI away from the display area A0;

[0327] In FIG8B , the line labeled L14 is the first DC signal transmission line, the line labeled L24 is the second DC signal transmission line, the line labeled L15 is the third DC signal transmission line, and the line labeled L25 is the fourth DC signal transmission line;

[0328] The circuit board F1 provides a DC voltage signal to GA12 through L14, provides a DC voltage signal to GA22 through L24, and provides a DC voltage signal to GI through L15 and L25.

[0329] In at least one embodiment shown in FIG. 8B , the driving integrated circuit GI is configured to generate a driving control signal according to the DC voltage signal and provide the driving control signal to the first driving module GA1 ;

[0330] The driving integrated circuit GI and the circuit board F1 are both disposed in the lower pad area.

[0331] At least one embodiment of the driving circuit shown in Figures 8A and 8B of the present disclosure places all driving circuits in the middle position of the display area A0 and is set below the anode layer. The GOA signal line is changed to be introduced from the upper middle section of the driving integrated circuit GI, making full use of the space in the middle section of the driving integrated circuit GI. At least one embodiment of the driving circuit shown in Figures 8A and 8B of the present disclosure can reduce the size of the lower pad area and the winding length of the GOA signal line, so that the load of each GOA signal line is minimized and there is no difference. The GOA signal line tries to use a film layer that does not interfere with other units in the current area, and the design of other units can also be modified to match the GOA signal line.

[0332] The display device described in the embodiment of the present disclosure includes the above-mentioned display panel.

[0333] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A display panel, comprising a display area and a pixel circuit arranged in the display area; the display panel further comprising a driving module and a driving integrated circuit; the driving module comprising a plurality of driving circuits, the driving circuit being used to provide a driving signal for the pixel circuit; the driving integrated circuit being used to provide a driving control signal for the driving circuit through a GOA signal line; the GOA signal line comprising a first GOA signal line arranged between the display area and the driving integrated circuit; At least part of the driving circuit included in the driving module is arranged in the display area; At least part of the driving circuit included in the driving module and arranged in the display area is electrically connected to the driving integrated circuit through the first GOA signal line, and is used to receive a driving control signal from the driving integrated circuit; The first GOA signal line extends along a first direction; The display panel further includes a data line, and the data line is used to provide a data voltage for the pixel circuit; the extending direction of the data line is substantially the same as the first direction.

2. The display panel according to claim 1, wherein: At least part of the driving circuits included in the driving module are arranged in the middle of the display area, and at least part of the driving circuits are arranged along a first direction.

3. The display panel according to claim 1, wherein: At least part of the driving circuit included in the driving module is a first driving circuit; The plurality of driving circuits included in the driving module except the first driving circuit are second driving circuits; The driving integrated circuit and the first GOA signal line are arranged on a first side of the display area; The plurality of second driving circuits included in the driving circuit are arranged on the second side and / or the third side of the display area; the second side and the third side are opposite sides.

4. The display panel according to claim 3, wherein: The GOA signal line further includes a second GOA signal line extending along a second direction; the first direction intersects with the second direction; The first GOA signal line is electrically connected to the second GOA signal line; The second GOA signal line is electrically connected to the driver integrated circuit; The second GOA signal line is used to receive and transmit a driving control signal from the driving integrated circuit.

5. The display panel according to claim 4, wherein: On the first side of the display area, a fan-out area, a bending area, a box test area, and an area for arranging the driver integrated circuit are sequentially arranged in a direction away from the display area; The second GOA signal line is arranged between the bending area and the box test area.

6. The display panel according to claim 3, wherein: At least part of the first GOA signal lines are directly electrically connected to the driver integrated circuit for receiving a driving control signal from the driver integrated circuit.

7. The display panel according to claim 6, wherein: The GOA signal line further includes a second GOA signal line extending along a second direction; the first direction intersects with the second direction; A portion of the first GOA signal line is electrically connected to the second GOA signal line; The second GOA signal line is directly electrically connected to the second driving circuit, and is used to provide a driving control signal to the second driving circuit.

8. The display panel according to any one of claims 1 to 7, wherein: The first GOA signal line is electrically connected to a port located in the middle of the driving integrated circuit.

9. The display panel according to claim 3, wherein: The GOA signal line further includes a second GOA signal line, and the second GOA signal line extends along a second direction; the first direction intersects with the second direction; The first GOA signal line is directly connected to the second GOA signal line; On the first side of the display area, a fan-out area, a bending area, a box test area, and an area for arranging the driver integrated circuit are sequentially arranged in a direction away from the display area; The second GOA signal line is arranged in the fan-out area; The second GOA signal line is electrically connected to the driving integrated circuit.

10. The display panel according to claim 4, 7 or 9, wherein: A plurality of the second driving circuits are arranged on the second side and the third side of the display area; The first end of the second GOA signal line is electrically connected to a second driving circuit disposed on a second side of the display area and a first port of the driving integrated circuit respectively; The second end of the second GOA signal line is electrically connected to a second driving circuit disposed on a third side of the display area and a second port of the driving integrated circuit, respectively.

11. The display panel according to claim 4, 7 or 9, wherein: A plurality of the second driving circuits are arranged on the second side of the display area; the first end of the second GOA signal line is electrically connected to the second driving circuit arranged on the second side of the display area and the first port of the driving integrated circuit respectively; or, A plurality of the second driving circuits are arranged on a third side of the display area; The second end of the second GOA signal line is electrically connected to a driving circuit disposed on a third side of the display area and a second port of the driving integrated circuit, respectively.

12. The display panel according to any one of claims 3 to 7, wherein: Also includes circuit boards; The circuit board is arranged on a side of the driving integrated circuit away from the display area; The circuit board is electrically connected to the first drive circuit and the second drive circuit respectively, and is used to provide a DC voltage signal to the first drive circuit and the second drive circuit respectively.

13. The display panel according to claim 12, wherein: The circuit board is also electrically connected to the driver integrated circuit and is used to provide a DC voltage signal to the driver integrated circuit; The driving integrated circuit is used to generate a driving control signal according to the DC voltage signal, and provide the driving control signal to the first driving circuit and the second driving circuit.

14. The display panel according to claim 1, wherein: All driving circuits included in the driving module are arranged in the display area; The first GOA signal line is directly electrically connected to the driver integrated circuit and is used to receive a driving control signal from the driver integrated circuit.

15. The display panel according to claim 14, wherein: Also includes voltage signal lines; The voltage signal line is electrically connected to the driving circuit and is used to provide a DC voltage signal to the driving circuit.

16. The display panel according to claim 15, wherein: The voltage signal line is electrically connected to the driver integrated circuit and is used to provide a DC voltage signal to the driver integrated circuit; The driving integrated circuit is used to generate a driving control signal according to the DC voltage signal, and provide the driving control signal to the driving circuit.

17. The display panel according to claim 16, wherein: It also includes a circuit board arranged on the driving integrated circuit away from the display area; The circuit board is electrically connected to the voltage signal line and is used to provide the DC voltage signal to the voltage signal line.

18. A display device comprising the display panel according to any one of claims 1 to 17.

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