Data providing circuit, display substrate, panel, driving method, and display apparatus

Abstract

A data providing circuit, a display substrate, a panel, a driving method, and a display apparatus. The data providing circuit comprises a multiplexing circuit (41) and a reset circuit (42), N being an integer greater than 1, wherein the multiplexing circuit (41) writes a data voltage into an nth data line under the control of an nth multiplexing control signal, n being a positive integer less than or equal to N; and under the control of a first multiplexing control signal, the reset circuit (42) is controlled so as to write an initial voltage (Vint) into data lines other than a first data line among N data lines. The reset circuit (42) is controlled by means of a first multiplexing control end (MUX1) among N multiplexing control ends, so as to write the initial voltage (Vint) into the data lines other than the first data line among the N data lines; and by means of a combination of the multiplexing circuit (41) and the reset circuit (42), the problem of the previous row of data voltages on a data line affecting the writing of the next row of data voltages on the data line is solved.

Description

Data providing circuit, display substrate, panel, driving method and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a data providing circuit, a display substrate, a panel, a driving method, and a display device. Background Art

[0002] In related technologies, mainstream LED (light-emitting diode) backplanes rely on splicing processes to increase their size, so signal lines need to be compressed into a layout to achieve seamless splicing. The number of data lines will affect the width of the seam, so time-sharing multiplexing is generally used to reduce the number of data lines. High PPI (pixel circuit) displays also often use time-sharing multiplexing to reduce the number of data voltage supply terminals of the source driver.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a data providing circuit, characterized in that it includes a multiplexing circuit and a reset circuit; N is an integer greater than 1;

[0005] The multiplexing circuit is electrically connected to the data voltage supply terminal, N multiplexing control terminals and N data lines respectively, and is used to write the data voltage provided by the data voltage supply terminal into the nth data line under the control of the nth multiplexing control signal provided by the nth multiplexing control terminal; n is a positive integer less than or equal to N;

[0006] The reset circuit is electrically connected to the first multiplexing control terminal, the initial voltage line and the data lines other than the first data line among the N data lines, respectively, and is used to control the initial voltage provided by the initial voltage line to be written into the data lines other than the first data line among the N data lines under the control of the first multiplexing control signal provided by the first multiplexing control terminal.

[0007] Optionally, the reset circuit includes M reset sub-circuits; M is equal to N-1; m is a positive integer less than or equal to M;

[0008] The control end of the mth reset subcircuit is electrically connected to the first multiplexing control end, the first end of the mth reset subcircuit is electrically connected to the initial voltage line, and the second end of the mth reset subcircuit is electrically connected to the (m+1)th data line;

[0009] The mth reset sub-circuit is configured to write the initial voltage provided by the initial voltage line into the (m+1)th data line under the control of the first multiplexing control signal provided by the first multiplexing control terminal.

[0010] Optionally, the multiplexing circuit includes N multiplexing sub-circuits;

[0011] The control terminal of the nth multiplexing subcircuit is electrically connected to the nth multiplexing control terminal, the first terminal of the nth multiplexing subcircuit is electrically connected to the data voltage supply terminal, and the second terminal of the nth multiplexing subcircuit is electrically connected to the nth data line;

[0012] The nth multiplexing sub-circuit is configured to write the data voltage provided by the data voltage providing end into the nth data line under the control of the nth multiplexing control signal provided by the nth multiplexing control end.

[0013] In a second aspect, an embodiment of the present disclosure provides a display substrate, comprising a base and the above-mentioned data providing circuit disposed on the base.

[0014] Optionally, the reset circuit in the data providing circuit includes M reset sub-circuits; M is equal to N-1; m is a positive integer less than or equal to M;

[0015] A control terminal of the mth reset sub-circuit is electrically connected to the first multiplexing control terminal, a first terminal of the mth reset sub-circuit is electrically connected to the initial voltage line, and a second terminal of the mth reset sub-circuit is electrically connected to the (m+1)th data line; the mth reset sub-circuit is configured to write an initial voltage provided by the initial voltage line to the (m+1)th data line under the control of a first multiplexing control signal provided by the first multiplexing control terminal;

[0016] The first end of a reset sub-circuit in the M reset sub-circuits is multiplexed as the first end of another reset sub-circuit in the M multiplexing sub-circuits.

[0017] Optionally, the multiplexing circuit in the data providing circuit includes N multiplexing sub-circuits;

[0018] a control terminal of the nth multiplexing sub-circuit electrically connected to the nth multiplexing control terminal, a first terminal of the nth multiplexing sub-circuit electrically connected to the data voltage supply terminal, and a second terminal of the nth multiplexing sub-circuit electrically connected to the nth data line; the nth multiplexing sub-circuit is configured to write the data voltage provided by the data voltage supply terminal into the nth data line under the control of an nth multiplexing control signal provided by the nth multiplexing control terminal;

[0019] The second end of the nth multiplexing subcircuit is multiplexed as the second end of the n-1th reset subcircuit. Optionally, the mth reset subcircuit includes an mth reset transistor;

[0020] The gate of the mth reset transistor is electrically connected to the first multiplexing control terminal, the first electrode of the mth reset transistor is electrically connected to the initial voltage line, and the second electrode of the mth reset transistor is electrically connected to the (m+1)th data line;

[0021] A first electrode of one of the M reset transistors is multiplexed as a first electrode of another reset transistor in the M multiplexing transistors.

[0022] Optionally, the nth multiplexing sub-circuit includes an nth multiplexing transistor;

[0023] The gate of the nth multiplexing transistor is electrically connected to the nth multiplexing control terminal, the first electrode of the nth multiplexing transistor is electrically connected to the data voltage supply terminal, and the second electrode of the nth multiplexing transistor is electrically connected to the nth data line;

[0024] The second electrode of the nth multiplexing transistor is multiplexed as the second electrode of the (n-1)th reset transistor.

[0025] Optionally, N is equal to 3 and M is equal to 2;

[0026] The first electrode of the first reset transistor is multiplexed as the first electrode of the second reset transistor;

[0027] The first electrode of the first reset transistor is multiplexed as the second electrode of the second multiplexing transistor, and the second electrode of the second reset transistor is multiplexed as the second electrode of the third multiplexing transistor.

[0028] Optional, N equals 5, M equals 4;

[0029] The first electrode of the first reset transistor is multiplexed as the first electrode of the second reset transistor, and the first electrode of the third reset transistor is multiplexed as the first electrode of the fourth reset transistor;

[0030] The first pole of the first reset transistor is multiplexed as the second pole of the second multiplexing transistor, and the second pole of the second reset transistor is multiplexed as the second pole of the third multiplexing transistor; the first pole of the third reset transistor is multiplexed as the second pole of the fourth multiplexing transistor, and the second pole of the fourth reset transistor is multiplexed as the second pole of the fifth multiplexing transistor.

[0031] In a third aspect, an embodiment of the present disclosure provides a display panel comprising the above-mentioned display substrate.

[0032] In a fourth aspect, an embodiment of the present disclosure provides a display panel comprising the above-mentioned data providing circuit.

[0033] Optionally, the display panel according to at least one embodiment of the present disclosure further includes a plurality of rows and columns of pixel circuits arranged in the display area;

[0034] The pixel circuit includes a light emitting element, a driving circuit and a writing control circuit;

[0035] The driving circuit is used to control the generation of a driving current for driving the light-emitting element under the control of the potential of the control terminal;

[0036] The write control circuit is electrically connected to the scan line, the data line and the first end of the drive circuit respectively, and is used to write the data voltage provided by the data line into the first end of the drive circuit under the control of the scan signal provided by the scan line.

[0037] In a fifth aspect, an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned display panel, wherein a display cycle includes a data writing phase; the data writing phase includes N writing time periods;

[0038] The driving method includes:

[0039] In a first writing time period, the reset circuit controls, under the control of the first multiplexing control signal, an initial voltage provided by the initial voltage line to be written into data lines other than the first data line among the N data lines;

[0040] In the nth writing time period, the multiplexing circuit writes the data voltage provided by the data voltage supply terminal into the nth data line under the control of the nth multiplexing control signal;

[0041] N is an integer greater than 1, and n is a positive integer less than or equal to N.

[0042] Optionally, the display panel further includes a plurality of rows and columns of pixel circuits arranged in the display area; the pixel circuits include light-emitting elements, a driving circuit, and a writing control circuit; and the driving method further includes:

[0043] In the data writing phase, the writing control circuit writes the data voltage provided by the data line into the first end of the driving circuit under the control of the scanning signal.

[0044] Optionally, the start time of the data writing phase is the same as the start time of the first writing time period.

[0045] Optionally, the display cycle also includes a pre-write stage, which is arranged before the data write stage, and the pre-write stage is adjacent to the data write stage. The driving method includes: in the pre-write stage, the reset circuit controls the initial voltage provided by the initial voltage line to be written into the N data lines except the first data line under the control of the first multiplexing control signal, and the multiplexing circuit controls the data voltage provided by the data voltage supply end to be written into the first data line under the control of the first multiplexing control signal.

[0046] Optionally, the driving method described in at least one embodiment of the present disclosure further includes:

[0047] In the ath writing time period, the data voltage provided by the data voltage supply terminal is controlled to be Va+ΔVa; a is an integer less than or equal to N and greater than 1;

[0048] ΔVa is equal to (Va-Vth-V0)×(e-(t1-t0a) / RC)-e -(t1 / RC) );

[0049] Wherein, Vth is the threshold voltage of the driving transistor included in the driving circuit, and Va is the data voltage to be written into the ath data line in the ath writing time period;

[0050] t1 is the duration of the data writing phase, and t0a is equal to (a-1)×(t2+t3);

[0051] Among them, t2 is the duration of each write time period, t3 is the interval between two adjacent write time periods, R is the resistance value of the resistor on the data line, C is the capacitance value of the coupling capacitor on the data line, and V0 is the voltage on the data line after the reset circuit, under the control of the first multiplexing control signal, controls the initial voltage provided by the initial voltage line to be written into the data lines other than the first data line among the N data lines.

[0052] In a sixth aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] FIG1 is a structural diagram of a related data providing circuit;

[0054] FIG2 is a circuit diagram of at least one embodiment of a pixel circuit in at least one embodiment of the present disclosure;

[0055] FIG3 is a driving timing diagram of at least one embodiment of the pixel circuit shown in FIG2 ;

[0056] FIG4 is a structural diagram of a data providing circuit according to an embodiment of the present disclosure;

[0057] FIG5 is a circuit diagram of a data providing circuit according to at least one embodiment of the present disclosure;

[0058] FIG6 is a circuit diagram of a data providing circuit according to at least one embodiment of the present disclosure;

[0059] FIG7 is a circuit diagram of a data providing circuit according to at least one embodiment of the present disclosure;

[0060] FIG8 is a circuit diagram of a verification simulation module;

[0061] FIG9 is a timing diagram of the operation of the verification simulation module shown in FIG8 ;

[0062] FIG10 is a circuit diagram of a verification simulation module;

[0063] FIG11 is a working timing diagram of the verification simulation module shown in FIG10 ;

[0064] FIG12 is a layout diagram of a data providing circuit according to at least one embodiment of the present disclosure;

[0065] FIG13 is a layout diagram of the semiconductor layer in FIG12;

[0066] FIG14 is a layout diagram of the gate metal layer in FIG12;

[0067] FIG15 is a layout diagram of the source / drain metal layer in FIG12 ;

[0068] FIG16 is a layout diagram of a data providing circuit according to at least one embodiment of the present disclosure;

[0069] FIG17 is a layout diagram of the semiconductor layer in FIG16;

[0070] FIG18 is a layout diagram of the gate metal layer in FIG16 ;

[0071] FIG19 is a layout diagram of the source / drain metal layer in FIG16 ;

[0072] FIG20 is a structural diagram of at least one embodiment of a pixel circuit;

[0073] FIG21 is an operation timing diagram of at least one embodiment of the data providing circuit shown in FIG7 ;

[0074] FIG22 is an operation timing diagram of at least one embodiment of the data providing circuit shown in FIG7 ;

[0075] FIG23 is an operation timing diagram of at least one embodiment of the data providing circuit shown in FIG7 ;

[0076] FIG. 24 is a timing diagram of the operation of the verification simulation module shown in FIG. 10 after the compensation method in at least one embodiment of the present disclosure is implemented. DETAILED DESCRIPTION

[0077] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0078] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0079] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0080] The data providing circuit described in the embodiment of the present disclosure includes a multiplexing circuit and a reset circuit; N is an integer greater than 1;

[0081] The multiplexing circuit is electrically connected to the data voltage supply terminal, N multiplexing control terminals and N data lines respectively, and is used to write the data voltage provided by the data voltage supply terminal into the nth data line under the control of the nth multiplexing control signal provided by the nth multiplexing control terminal; n is a positive integer less than or equal to N;

[0082] The reset circuit is electrically connected to the first multiplexing control terminal, the initial voltage line and the data lines other than the first data line among the N data lines, respectively, and is used to control the initial voltage provided by the initial voltage line to be written into the data lines other than the first data line among the N data lines under the control of the first multiplexing control signal provided by the first multiplexing control terminal.

[0083] An embodiment of the present disclosure provides a data providing circuit, which controls a reset circuit through the first multiplexing control terminal among N multiplexing control terminals to write an initial voltage into data lines other than the first data line among the N data lines. By combining the multiplexing circuit and the reset circuit, the problem of the influence of the previous row of data voltage on the writing of the next row of data voltage on the data line is solved.

[0084] In at least one embodiment of the present disclosure, the first data line may be any one of the N data lines. The first data line is not necessarily the first data line in a column from left to right included in the display panel, and the first data line is not necessarily the first data line in a column from left to right among the N data lines.

[0085] In at least one embodiment of the present disclosure, the first data line is described as a first column data line. However, in actual operation, the first data line may be any one of the N data lines.

[0086] In related technologies, mainstream LED (light-emitting diode) backplanes rely on splicing processes to increase their size, so signal lines need to be compressed into a layout to achieve seamless splicing. The number of data lines will affect the width of the seam, so time-sharing multiplexing is generally used to reduce the number of data lines. High PPI (pixel circuit) displays also often use time-sharing multiplexing to reduce the number of data voltage supply terminals of the source driver.

[0087] As shown in FIG1 , in the relevant data providing circuit, one data voltage providing terminal provides data voltages for two columns of data lines;

[0088] In FIG1 , the terminal labeled D1 is a first data voltage supply terminal, and the terminal labeled D2 is a second data voltage supply terminal;

[0089] The data line labeled DL1 is the first column, the data line labeled DL2 is the second column, the data line labeled DL3 is the third column, and the data line labeled DL4 is the fourth column;

[0090] The pixel circuit labeled PM1 is the M-th row and the first column, the pixel circuit labeled PM2 is the M-th row and the second column, the pixel circuit labeled PM3 is the M-th row and the third column, and the pixel circuit labeled PM4 is the M-th row and the fourth column;

[0091] The pixel circuit labeled PM-11 is the pixel circuit in the first column of the M-1th row, the pixel circuit labeled PM-12 is the pixel circuit in the second column of the M-1th row, the pixel circuit labeled PM-13 is the pixel circuit in the third column of the M-1th row, and the pixel circuit labeled PM-14 is the pixel circuit in the fourth column of the M-1th row.

[0092] M is an integer greater than 1.

[0093] In at least one embodiment of the present disclosure, the first column data line DL1, the second column data line DL2, the third column data line DL3 and the fourth column data line DL4 are any four adjacent data lines included in the display panel, but are not necessarily the first four columns of data lines included in the display panel;

[0094] Moreover, the first column of data lines DL1 is not necessarily the first column of data lines from left to right among the four data lines, the second column of data lines DL2 is not necessarily the second column of data lines from left to right among the four data lines, the third column of data lines DL3 is not necessarily the third column of data lines from left to right among the four data lines, and the fourth column of data lines DL4 is not necessarily the fourth column of data lines from left to right among the four data lines.

[0095] In FIG1 , the transistor labeled TM1 is a first multiplexing transistor, the transistor labeled TM2 is a second multiplexing transistor, the transistor labeled TM3 is a third multiplexing transistor, and the transistor labeled TM4 is a fourth multiplexing transistor;

[0096] The gate of TM1 is electrically connected to the first multiplexing control terminal MUX1, the source of TM1 is electrically connected to the first data voltage supply terminal D1, and the drain of TM1 is electrically connected to the first column data line DL1;

[0097] The gate of TM2 is electrically connected to the second multiplexing control terminal MUX2, the source of TM2 is electrically connected to the first data voltage supply terminal D1, and the drain of TM2 is electrically connected to the second column data line DL2;

[0098] The gate of TM3 is electrically connected to the first multiplexing control terminal MUX1, the source of TM3 is electrically connected to the second data voltage supply terminal D2, and the drain of TM3 is electrically connected to the third column data line DL3;

[0099] A gate of TM4 is electrically connected to the second multiplexing control terminal MUX2 , a source of TM4 is electrically connected to the second data voltage supply terminal D2 , and a drain of TM4 is electrically connected to the fourth column data line DL4 .

[0100] In FIG. 1 , TM1 , TM2 , TM3 , and TM4 are all p-type transistors, but the present invention is not limited thereto.

[0101] FIG. 2 is a circuit diagram of at least one embodiment of a pixel circuit in at least one embodiment of the present disclosure.

[0102] As shown in FIG2 , at least one embodiment of the pixel circuit includes a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a storage capacitor Cst, and an organic light emitting diode OL;

[0103] The gate of T1 is electrically connected to the reset line RST, the source of T1 is connected to the reset signal Vi, and the drain of T1 is electrically connected to the gate of T3;

[0104] The gate of T2 is electrically connected to the scan line GL, the source of T2 is electrically connected to the source of T3, and the drain of T2 is electrically connected to the drain of T8;

[0105] The drain of T3 is electrically connected to the source of T6;

[0106] The gate of T4 is electrically connected to the light emitting control line EM, the source of T4 is electrically connected to the high voltage terminal VDD, and the drain of T4 is electrically connected to the source of T3;

[0107] The gate of T5 is electrically connected to the scan line GL, the source of T5 is electrically connected to the gate of T3, and the drain of T5 is electrically connected to the drain of T3;

[0108] The gate of T6 is electrically connected to the light emitting control line EM, the source of T6 is electrically connected to the drain of T3, the drain of T6 is electrically connected to the anode of OL, and the cathode of OL is electrically connected to the low voltage terminal VSS;

[0109] The gate of T7 is electrically connected to the reset line RST, the source of T7 is connected to the reset voltage Vi, and the drain of T7 is electrically connected to the anode of OL;

[0110] The gate of T8 is electrically connected to the multiplexing control terminal MUX, and the source of T8 is electrically connected to the data voltage supply terminal D0.

[0111] In at least one embodiment of the pixel circuit shown in FIG. 2 , all transistors are p-type transistors, but the present invention is not limited thereto.

[0112] In FIG3 , the terminal labeled MUX1 is a first multiplexing control terminal, and the terminal labeled MUX2 is a second multiplexing control terminal.

[0113] According to the driving timing in FIG. 3 , at least one embodiment of the pixel circuit shown in FIG. 2 is in operation, when the gate of T8 in FIG. 2 is electrically connected to the second multiplexing control terminal MUX2,

[0114] After the scan line GL is turned on and the data writing of the M-1th row is completed, the data writing of the Mth row begins. After the pixel circuit is initialized, MUX2 in Figure 2 is turned on. At this time, before MUX2 is turned on, the gate of T3 in Figure 2 will be written with the data voltage of the M-1th row, thereby causing the data voltage of the Mth row to be incorrectly written. It is also noted that the above-mentioned effect occurs when the data voltage of the M-1th row is higher than the data voltage of the Mth row. If the data voltage of the M-1th row is the high data voltage VDH and the data voltage of the Mth row is the low data voltage VDL, the potential of the gate of T3 will first be written with VDH+Vth. Therefore, the gate-source voltage of T3 written into the pixel circuit of the Mth row will become VDH+Vth-(VDL+Vth). In other words, the gate-source voltage of the pixel circuit of the Mth row will become VDH-VGL. This gate-source voltage is greater than 0. At this time, T3 in the pixel circuit of the Mth row is turned off, and the data voltage VDL of the Mth row to be written into the pixel circuit of the Mth row cannot be properly written.

[0115] In the related art, the scan line and the multiplexing control terminal are opened in time-sharing mode. However, in at least one embodiment of the present disclosure, when the scan line is opened, at least two rows of data voltages are written in sequence, saving time. Therefore, at least one embodiment of the present disclosure is suitable for high-frequency display products.

[0116] As shown in FIG4 , the data providing circuit according to the embodiment of the present disclosure includes a multiplexing circuit 41 and a reset circuit 42 ; N is an integer greater than 1;

[0117] The multiplexing circuit 41 is electrically connected to the first data voltage supply terminal D1, the first multiplexing control terminal MUX1, the second multiplexing control terminal MUX2, the third multiplexing control terminal MUX3, the first column data line DL1, the second column data line DL2, and the third column data line DL3, respectively, and is configured to write the data voltage provided by the first data voltage supply terminal D1 into the first column data line DL1 under the control of a first multiplexing control signal provided by the first multiplexing control terminal MUX1, write the data voltage provided by the first data voltage supply terminal D1 into the second column data line DL2 under the control of a second multiplexing control signal provided by the second multiplexing control terminal MUX2, and write the data voltage provided by the first data voltage supply terminal D1 into the third column data line DL3 under the control of a third multiplexing control signal provided by the third multiplexing control terminal MUX3;

[0118] The reset circuit 42 is electrically connected to the first multiplexing control terminal MUX1, the initial voltage line, the second column data line DL2 and the third column data line DL3, respectively, and is used to control the initial voltage Vint provided by the initial voltage line to be written into the second column data line DL2 and the third column data line DL3 under the control of the first multiplexing control signal provided by the first multiplexing control terminal MUX1.

[0119] The data providing circuit described in the embodiment of the present disclosure can solve the problem of mutual interference of data voltages between adjacent row pixel circuits when the scan line and the multiplexing control terminal are turned on at the same time. When the multiplexing circuit 41 writes the data voltage provided by the first data voltage providing terminal D1 into the first column data line DL1 under the control of the first multiplexing control signal, the reset circuit 42 controls the initial voltage Vint to be written into the second column data line DL2 and the third column data line DL3 under the control of the first multiplexing control signal, and resets the second column data line DL2 and the third column data line DL3 to solve the problem of the influence of the previous row data voltage on the data line on the writing of the data voltage of the next row on the data line; and, compared with the scan line being turned on after all the multiplexing control terminals are turned off, the flexibility of the driving timing is increased, and the influence of the capacitance between adjacent data line layers can also be reduced.

[0120] Optionally, the reset circuit includes M reset sub-circuits; M is equal to N-1; m is a positive integer less than or equal to M;

[0121] The control end of the mth reset subcircuit is electrically connected to the first multiplexing control end, the first end of the mth reset subcircuit is electrically connected to the initial voltage line, and the second end of the mth reset subcircuit is electrically connected to the (m+1)th data line;

[0122] The mth reset sub-circuit is configured to write the initial voltage provided by the initial voltage line into the (m+1)th data line under the control of the first multiplexing control signal provided by the first multiplexing control terminal.

[0123] Optionally, the mth reset subcircuit may include an mth reset transistor;

[0124] The gate of the mth reset transistor is electrically connected to the first multiplexing control terminal, the first electrode of the mth reset transistor is electrically connected to the initial voltage line, and the second electrode of the mth reset transistor is electrically connected to the (m+1)th data line.

[0125] Optionally, the M reset transistors are all p-type transistors; or, the M reset transistors are all n-type transistors, but the present invention is not limited thereto. In a specific implementation, the reset transistors can be p-type transistors or n-type transistors, and the type of the reset transistor varies according to the timing of the multiplexing control signal connected to its gate.

[0126] In at least one embodiment of the present disclosure, the mth reset subcircuit may also include at least two reset transistors connected in series, and gates of the at least two reset transistors may be electrically connected to the first multiplexing control terminal.

[0127] For example, when the mth reset subcircuit includes two reset transistors connected in series,

[0128] A gate of a first reset transistor included in the mth reset subcircuit may be electrically connected to the first multiplexing control terminal, a first electrode of the first reset transistor included in the mth reset subcircuit may be electrically connected to the initial voltage line, and a second electrode of the first reset transistor included in the mth reset subcircuit may be electrically connected to a first electrode of a second reset transistor included in the mth reset subcircuit;

[0129] The gate of the second reset transistor included in the mth reset subcircuit can be electrically connected to the first multiplexing control terminal, and the second electrode of the second reset transistor included in the mth reset subcircuit can be electrically connected to the m+1th data line. In at least one embodiment of the present disclosure, the multiplexing circuit includes N multiplexing subcircuits;

[0130] The control terminal of the nth multiplexing subcircuit is electrically connected to the nth multiplexing control terminal, the first terminal of the nth multiplexing subcircuit is electrically connected to the data voltage supply terminal, and the second terminal of the nth multiplexing subcircuit is electrically connected to the nth data line;

[0131] The nth multiplexing sub-circuit is configured to write the data voltage provided by the data voltage providing end into the nth data line under the control of the nth multiplexing control signal provided by the nth multiplexing control end.

[0132] Optionally, the nth multiplexing sub-circuit may include an nth multiplexing transistor;

[0133] The gate of the nth multiplexing transistor is electrically connected to the nth multiplexing control terminal, the first electrode of the nth multiplexing transistor is electrically connected to the data voltage supply terminal, and the second electrode of the nth multiplexing transistor is electrically connected to the nth data line.

[0134] In at least one embodiment of the present disclosure, the nth multiplexing sub-circuit may include at least two multiplexing transistors connected in series, and gates of the at least two multiplexing transistors are both electrically connected to the nth multiplexing control terminal.

[0135] For example, when the nth multiplexing sub-circuit includes two multiplexing transistors connected in series,

[0136] A gate of a first multiplexing transistor included in the nth multiplexing sub-circuit may be electrically connected to an nth multiplexing control terminal, a first electrode of a first multiplexing transistor included in the nth multiplexing sub-circuit may be electrically connected to the data voltage supply terminal, and a second electrode of the first multiplexing transistor included in the nth multiplexing sub-circuit may be electrically connected to a second multiplexing transistor included in the nth multiplexing sub-circuit;

[0137] The gate of the second multiplexing transistor included in the nth multiplexing sub-circuit may be electrically connected to the nth multiplexing control terminal, and the second electrode of the second multiplexing transistor included in the nth multiplexing sub-circuit may be electrically connected to the nth data line.

[0138] In FIG5 , the pixel circuit labeled PM1 is the pixel circuit in the first column of the M-th row, the pixel circuit labeled PM2 is the pixel circuit in the second column of the M-th row, and the pixel circuit labeled PM3 is the pixel circuit in the third column of the M-th row;

[0139] The pixel circuit labeled PM-11 is the pixel circuit in the first column of the M-1th row, the pixel circuit labeled PM-12 is the pixel circuit in the second column of the M-1th row, and the pixel circuit labeled PM-13 is the pixel circuit in the third column of the M-1th row;

[0140] PM1 and PM-11 are both electrically connected to the first column data line DL1, PM2 and PM-12 are both electrically connected to the second column data line DL2, and PM3 and PM-13 are both electrically connected to the third column data line DL3;

[0141] M is an integer greater than 1.

[0142] As shown in FIG5, based on the embodiment of the data providing circuit shown in FIG4,

[0143] The multiplexing circuit includes a first multiplexing transistor TM1, a second multiplexing transistor TM2 and a third multiplexing transistor TM3;

[0144] The reset circuit includes a first reset transistor TR1 and a second reset transistor TR2;

[0145] The gate of TM1 is electrically connected to the first multiplexing control terminal MUX1, the source of TM1 is electrically connected to the first data voltage supply terminal D1, and the drain of TM1 is electrically connected to the first column data line DL1;

[0146] The gate of TM2 is electrically connected to the second multiplexing control terminal MUX2, the source of TM2 is electrically connected to the first data voltage supply terminal D1, and the drain of TM2 is electrically connected to the second column data line DL2;

[0147] The gate of TM3 is electrically connected to the third multiplexing control terminal MUX3, the source of TM3 is electrically connected to the first data voltage supply terminal D1, and the drain of TM3 is electrically connected to the third column data line DL3;

[0148] The gate of TR1 is electrically connected to the first multiplexing control terminal MUX1, the source of TR1 is connected to the initial voltage Vint, and the drain of TR1 is electrically connected to the second column data line DL2;

[0149] The gate of TR2 is electrically connected to the first multiplexing control terminal MUX1 , the source of TR2 is connected to the initial voltage Vint, and the drain of TR2 is electrically connected to the third column data line DL3 .

[0150] In at least one embodiment shown in FIG. 5 , TM1 , TM2 , TM3 , TR1 , and TR2 are all p-type transistors, but the present invention is not limited thereto.

[0151] In at least one embodiment shown in FIG. 5 , N is taken as 3 as an example for description.

[0152] The display substrate described in the embodiment of the present disclosure includes a base and the above-mentioned data providing circuit arranged on the base.

[0153] In at least one embodiment of the present disclosure, the reset circuit in the data providing circuit may include M reset sub-circuits; M is equal to N-1; m is a positive integer less than or equal to M;

[0154] A control terminal of the mth reset sub-circuit is electrically connected to the first multiplexing control terminal, a first terminal of the mth reset sub-circuit is electrically connected to the initial voltage line, and a second terminal of the mth reset sub-circuit is electrically connected to the (m+1)th data line; the mth reset sub-circuit is configured to write an initial voltage provided by the initial voltage line to the (m+1)th data line under the control of a first multiplexing control signal provided by the first multiplexing control terminal;

[0155] The first end of a reset sub-circuit in the M reset sub-circuits can be multiplexed as the first end of another reset sub-circuit in the M multiplexing sub-circuits.

[0156] In at least one embodiment of the present disclosure, the multiplexing circuit in the data providing circuit includes N multiplexing sub-circuits;

[0157] a control terminal of the nth multiplexing sub-circuit electrically connected to the nth multiplexing control terminal, a first terminal of the nth multiplexing sub-circuit electrically connected to the data voltage supply terminal, and a second terminal of the nth multiplexing sub-circuit electrically connected to the nth data line; the nth multiplexing sub-circuit is configured to write the data voltage provided by the data voltage supply terminal into the nth data line under the control of an nth multiplexing control signal provided by the nth multiplexing control terminal;

[0158] The second end of the nth multiplexing sub-circuit is multiplexed as the second end of the (n-1)th reset sub-circuit.

[0159] As shown in FIG6 , the pixel circuit labeled PM1 is the pixel circuit in the first column of the M-th row, and the pixel circuit labeled PM2 is the pixel circuit in the second column of the M-th row;

[0160] The pixel circuit labeled PM-11 is the pixel circuit in the first column of the M-1th row, and the pixel circuit labeled PM-12 is the pixel circuit in the second column of the M-1th row;

[0161] PM-11 includes a first first transistor T11, a first second transistor T12, a first driving transistor T13, a first fourth transistor T14, a first fifth transistor T15, a first sixth transistor T16, a first seventh transistor T17, a first storage capacitor Cst1 and a first organic light emitting diode O1;

[0162] PM-12 includes a second first transistor T21, a second second transistor T22, a second driving transistor T23, a second fourth transistor T24, a second fifth transistor T25, a second sixth transistor T26, a second seventh transistor T27, a second storage capacitor Cst2 and a second organic light emitting diode O2;

[0163] PM1 includes a third first transistor T31, a third second transistor T32, a third driving transistor T33, a third fourth transistor T34, a third fifth transistor T35, a third sixth transistor T36, a third seventh transistor T37, a third storage capacitor Cst3, and a third organic light emitting diode O3;

[0164] PM2 includes a fourth first transistor T41, a fourth second transistor T42, a fourth driving transistor T43, a fourth fourth transistor T44, a fourth fifth transistor T45, a fourth sixth transistor T46, a fourth seventh transistor T47, a fourth storage capacitor Cst4 and a fourth organic light emitting diode O4;

[0165] In FIG6 , the first column data line is labeled DL1 , the second column data line is labeled DL2 , and the first data voltage supply terminal is labeled D1 ;

[0166] The terminal labeled VDD is a high voltage terminal, the terminal labeled EM(M-1) is the light emitting control line in the M-1th row, and the terminal labeled EM(M) is the light emitting control line in the Mth row;

[0167] The scan line labeled GLM-1 is the M-1th row, and the scan line labeled GLM is the Mth row;

[0168] The line labeled RST(M-1) is the reset line of the M-1th row, and the line labeled RST(M) is the reset line of the Mth row;

[0169] The one labeled Vi is the reset voltage, the one labeled VDD is the high voltage end, the one labeled VSS is the low voltage end, and the one labeled Vint is the initial voltage.

[0170] In at least one embodiment shown in FIG6 , N is equal to 2;

[0171] At least one embodiment of the data providing circuit includes a first multiplexing transistor TM1, a second multiplexing transistor TM2 and a first reset transistor TR1;

[0172] The gate of TM1 is electrically connected to the first multiplexing control terminal MUX1, the source of TM1 is electrically connected to the first data voltage supply terminal D1, and the drain of TM1 is electrically connected to the first column data line DL1;

[0173] The gate of TM2 is electrically connected to the second multiplexing control terminal MUX2, the source of TM2 is electrically connected to the first data voltage supply terminal D1, and the drain of TM2 is electrically connected to the second column data line DL2;

[0174] The gate of TR1 is electrically connected to the first multiplexing control terminal MUX1, the source of TR1 is connected to the initial voltage Vint, and the drain of TR1 is electrically connected to the second column data line DL2;

[0175] When MUX1 provides a low voltage signal, TM1 and TR1 are turned on, and the data voltage provided by the first data voltage supply terminal D1 is written into the first column data line DL1, and the initial voltage Vint is written into the second column data line DL2;

[0176] When MUX2 provides a low voltage signal, TM2 is turned on to write the data voltage provided by the first data voltage supply terminal D1 into the second column data line DL2.

[0177] In at least one embodiment shown in FIG. 6 , Vi and Vint may be the same; or, Vi and Vint may be different.

[0178] In at least one embodiment of the present disclosure, when T3 in the pixel circuit is a p-type transistor, Vint may be a relatively low value so that the difference between Vint and the data voltage is less than the threshold voltage of T3;

[0179] When T3 in the pixel circuit is an n-type transistor, Vint may be a relatively high value, so that the difference between Vint and the data voltage is greater than the threshold voltage of T3.

[0180] As shown in FIG7 , the pixel circuit labeled PM1 is the pixel circuit in the first column of the M-th row, the pixel circuit labeled PM2 is the pixel circuit in the second column of the M-th row; and the pixel circuit labeled PM3 is the pixel circuit in the third column of the M-th row;

[0181] The pixel circuit labeled PM-11 is the pixel circuit in the first column of the M-1th row; the pixel circuit labeled PM-12 is the pixel circuit in the second column of the M-1th row; and the pixel circuit labeled PM-13 is the pixel circuit in the third column of the M-1th row.

[0182] PM-11 includes a first first transistor T11, a first second transistor T12, a first driving transistor T13, a first fourth transistor T14, a first fifth transistor T15, a first sixth transistor T16, a first seventh transistor T17, a first storage capacitor Cst1 and a first organic light emitting diode O1;

[0183] PM-12 includes a second first transistor T21, a second second transistor T22, a second driving transistor T23, a second fourth transistor T24, a second fifth transistor T25, a second sixth transistor T26, a second seventh transistor T27, a second storage capacitor Cst2 and a second organic light emitting diode O2;

[0184] PM-13 includes a fifth first transistor T51, a fifth second transistor T52, a fifth driving transistor T53, a fifth fourth transistor T54, a fifth fifth transistor T55, a fifth sixth transistor T56, a fifth seventh transistor T57, a fifth storage capacitor Cst5 and a fifth organic light emitting diode O5;

[0185] PM1 includes a third first transistor T31, a third second transistor T32, a third driving transistor T33, a third fourth transistor T34, a third fifth transistor T35, a third sixth transistor T36, a third seventh transistor T37, a third storage capacitor Cst3, and a third organic light emitting diode O3;

[0186] PM2 includes a fourth first transistor T41, a fourth second transistor T42, a fourth driving transistor T43, a fourth fourth transistor T44, a fourth fifth transistor T45, a fourth sixth transistor T46, a fourth seventh transistor T47, a fourth storage capacitor Cst4 and a fourth organic light emitting diode O4;

[0187] PM3 includes a sixth first transistor T61, a sixth second transistor T62, a sixth driving transistor T63, a sixth fourth transistor T64, a sixth fifth transistor T65, a sixth sixth transistor T66, a sixth seventh transistor T67, a sixth storage capacitor Cst6 and a sixth organic light emitting diode O6;

[0188] In FIG7 , the data line labeled DL1 is the first column, the data line labeled DL2 is the second column, the data line labeled DL3 is the third column, and the first data voltage supply terminal labeled D1 is;

[0189] The terminal labeled VDD is a high voltage terminal, the terminal labeled EM(M-1) is the light emitting control line in the M-1th row, and the terminal labeled EM(M) is the light emitting control line in the Mth row;

[0190] The scan line labeled GLM-1 is the M-1th row, and the scan line labeled GLM is the Mth row;

[0191] The line labeled RST(M-1) is the reset line of the M-1th row, and the line labeled RST(M) is the reset line of the Mth row;

[0192] The voltage labeled Vi is the reset voltage, the voltage labeled VSS is the low voltage terminal, and the voltage labeled Vint is the initial voltage.

[0193] In at least one embodiment shown in FIG. 7 , N is equal to 3;

[0194] At least one embodiment of the data providing circuit includes a first multiplexing transistor TM1, a second multiplexing transistor TM2, a third multiplexing transistor TM3, a first reset transistor TR1 and a second reset transistor TR2;

[0195] The gate of TM1 is electrically connected to the first multiplexing control terminal MUX1, the source of TM1 is electrically connected to the first data voltage supply terminal D1, and the drain of TM1 is electrically connected to the first column data line DL1;

[0196] The gate of TM2 is electrically connected to the second multiplexing control terminal MUX2, the source of TM2 is electrically connected to the first data voltage supply terminal D1, and the drain of TM2 is electrically connected to the second column data line DL2;

[0197] The gate of TM3 is electrically connected to the third multiplexing control terminal MUX3, the source of TM3 is electrically connected to the first data voltage supply terminal D1, and the drain of TM3 is electrically connected to the third column data line DL3;

[0198] The gate of TR1 is electrically connected to the first multiplexing control terminal MUX1, the source of TR1 is connected to the initial voltage Vint, and the drain of TR1 is electrically connected to the second column data line DL2;

[0199] The gate of TR2 is electrically connected to the first multiplexing control terminal MUX1, the source of TR2 is connected to the initial voltage Vint, and the drain of TR2 is electrically connected to the third column data line DL3;

[0200] When MUX1 provides a low voltage signal, TM1, TR1 and TR2 are turned on, and the data voltage provided by the first data voltage supply terminal D1 is written into the first column data line DL1, and the initial voltage Vint is written into the second column data line DL2 and the third column data line DL3.

[0201] In at least one embodiment shown in FIG. 7 , Vi and Vint may be the same; or, Vi and Vint may be different.

[0202] In at least one embodiment of the present disclosure, when T3 in the pixel circuit is a p-type transistor, Vint may be a relatively low value so that the difference between Vint and the data voltage is less than the threshold voltage of T3;

[0203] When T3 in the pixel circuit is an n-type transistor, Vint may be a relatively high value, so that the difference between Vint and the data voltage is greater than the threshold voltage of T3.

[0204] The following takes N equal to 3 as an example to illustrate the process of verifying the technical solution of the embodiment of the present disclosure.

[0205] As shown in Figure 8, a verification simulation module is designed;

[0206] The verification simulation module includes a first driving circuit 81, a second driving circuit 82, a third driving circuit 83, a first load circuit 801, a second load circuit 802, a third load circuit 803, a first analog data line DLM1, a second analog data line DLM2, a third analog data line DLM3, a data providing circuit 80 and a verification module;

[0207] The first driving circuit 81 includes a first driving transistor T13, a first second transistor T12, a first first transistor T11, a first fifth transistor T15 and a first storage capacitor Cst1;

[0208] The second driving circuit 82 includes a second driving transistor T23, a second second transistor T22, a second first transistor T21, a second fifth transistor T25 and a second storage capacitor Cst2;

[0209] The third driving circuit 83 includes a third driving transistor T33, a third second transistor T32, a third first transistor T31, a third fifth transistor T35 and a third storage capacitor Cst3;

[0210] The data providing circuit 80 includes a first multiplexing transistor TM1, a second multiplexing transistor TM2 and a third multiplexing transistor TM3;

[0211] The gate of TM1 is electrically connected to the first multiplexing control terminal MUX1, the source of TM1 is electrically connected to the first data voltage supply terminal D1, and the drain of TM1 is electrically connected to T12 and the first load circuit 801 respectively;

[0212] The gate of TM2 is electrically connected to the second multiplexing control terminal MUX2, the source of TM2 is electrically connected to the first data voltage supply terminal D1, and the drain of TM2 is electrically connected to T22 and the second load circuit 802 respectively;

[0213] The gate of TM3 is electrically connected to the third multiplexing control terminal MUX3, the source of TM3 is electrically connected to the first data voltage supply terminal D1, and the drain of TM3 is electrically connected to T32 and the third load circuit 803 respectively;

[0214] The first load circuit 801 simulates the coupling capacitance and resistance on the first column data line, the second load circuit 802 simulates the coupling capacitance and resistance on the second column data line, and the third load circuit 803 simulates the coupling capacitance and resistance on the third column data line.

[0215] DLM1 is electrically connected to T12 via a first load circuit 801 , DLM2 is electrically connected to T22 via a second load circuit 802 , and DLM3 is electrically connected to T32 via a third load circuit 803 .

[0216] In FIG8 , RST is a reset line, GL is a scan line, VDD is a high voltage terminal, and Vi is a reset voltage.

[0217] In FIG8 , the gate of T13 is the first gate monitoring point g1, the gate of T23 is the second gate monitoring point g2, the gate of T33 is the third gate monitoring point g3, a first data line monitoring point is provided on DLM1, a second data line monitoring point is provided on DLM2, and a third data line monitoring point is provided on DLM3;

[0218] When simulating and verifying the verification simulation module in Figure 8, the verification module controls the provision of data voltage, scan signal, reset signal, and detects the potential of each monitoring point. First, the first data voltage supply terminal D1 will input three pulses of 8V voltage (for low grayscale display), and g1, g2, and g3 will all be charged with a voltage of approximately 7.1V. The data voltage on DL1, the data voltage on DL2, and the data voltage on DL3 will eventually maintain a voltage of approximately 7V. Immediately after RST is turned on and the potential of the gate of each driving transistor is reset by the reset voltage Vi, the first data voltage supply terminal D1 inputs a 3V voltage (for high grayscale display). Due to the 7V voltage retained by the capacitor on the data line, except for MUX1, which is turned on at the same time as the signal on the scan line, that is, the potential of g1 is written to the normal voltage of 2.5V, the potential of g2 and the potential of g3 are respectively approximately 6.3V, which means that a write abnormality problem occurs.

[0219] FIG9 is a working timing diagram of the verification simulation module shown in FIG8 .

[0220] In FIG9 , Vg1 is the potential of g1 , Vg2 is the potential of g2 , and Vg3 is the potential of g3 .

[0221] As shown in Figure 10, a verification simulation module is designed;

[0222] The verification simulation module includes a first driving circuit 81, a second driving circuit 82, a third driving circuit 83, a first load circuit 801, a second load circuit 802, a third load circuit 803, a first analog data line DLM1, a second analog data line DLM2, a third analog data line DLM3, a data providing circuit 80 and a verification module;

[0223] The first driving circuit 81 includes a first driving transistor T13, a first second transistor T12, a first first transistor T11, a first fifth transistor T15 and a first storage capacitor Cst1;

[0224] The second driving circuit 82 includes a second driving transistor T23, a second second transistor T22, a second first transistor T21, a second fifth transistor T25 and a second storage capacitor Cst2;

[0225] The third driving circuit 83 includes a third driving transistor T33, a third second transistor T32, a third first transistor T31, a third fifth transistor T35 and a third storage capacitor Cst3;

[0226] The data providing circuit 80 includes a first multiplexing transistor TM1, a second multiplexing transistor TM2, a third multiplexing transistor TM3, a first reset transistor TR1 and a second reset transistor TR2;

[0227] The gate of TM1 is electrically connected to the first multiplexing control terminal MUX1, the source of TM1 is electrically connected to the first data voltage supply terminal D1, and the drain of TM1 is electrically connected to T12 and the first load circuit 801 respectively;

[0228] The gate of TM2 is electrically connected to the second multiplexing control terminal MUX2, the source of TM2 is electrically connected to the first data voltage supply terminal D1, and the drain of TM2 is electrically connected to T22 and the second load circuit 802 respectively;

[0229] The gate of TM3 is electrically connected to the third multiplexing control terminal MUX3, the source of TM3 is electrically connected to the first data voltage supply terminal D1, and the drain of TM3 is electrically connected to T32 and the third load circuit 803 respectively;

[0230] The gate of TR1 is electrically connected to the first multiplexing control terminal MUX1, the source of TR1 is connected to the initial voltage Vint, and the drain of TR1 is electrically connected to the second load circuit 802;

[0231] The gate of TR2 is electrically connected to the first multiplexing control terminal MUX1, the source of TR1 is connected to the initial voltage Vint, and the drain of TR1 is electrically connected to the third load circuit 803;

[0232] The first load circuit 801 simulates the coupling capacitance and resistance on the first column data line, the second load circuit 802 simulates the coupling capacitance and resistance on the second column data line, and the third load circuit 803 simulates the coupling capacitance and resistance on the third column data line.

[0233] DLM1 is electrically connected to T12 via a first load circuit 801 , DLM2 is electrically connected to T22 via a second load circuit 802 , and DLM3 is electrically connected to T32 via a third load circuit 803 .

[0234] In FIG10 , RST is a reset line, GL is a scan line, VDD is a high voltage terminal, and Vi is a reset voltage.

[0235] In FIG10 , the gate of T13 is the first gate monitoring point g1, the gate of T23 is the second gate monitoring point g2, the gate of T33 is the third gate monitoring point g3, a first data line monitoring point is provided on DLM1, a second data line monitoring point is provided on DLM2, and a third data line monitoring point is provided on DLM3;

[0236] When performing simulation verification on the verification simulation module in FIG10 , the verification module controls the provision of data voltage, scan signal, reset signal, and detects the potential of each monitoring point.

[0237] First, the first data voltage supply terminal D1 will input three pulses of 8V voltage (as a low grayscale display), g1, g2 and g3 will all be charged with a voltage of about 7.1V, and the data voltage on DL1, the data voltage on DL2 and the data voltage on DL3 will eventually maintain a voltage of about 7V; then RST is turned on, and the potential of the gate of each driving transistor is reset by the reset voltage Vi, and the first data voltage supply terminal D1 inputs a 3V voltage (as a high grayscale display). When MUX1 provides a valid first multiplexing control signal, TM1, TR1 and TR2 are turned on at the same time, and Vint simultaneously resets the 7.1V voltage stored in the coupling capacitor on DL2 and the 7.1V voltage stored in the coupling capacitor on DL3. Therefore, when the MUX2 and MUX3 start signals arrive, the 3V data voltage is written. According to the simulation structure, g1 writes a 2.53V voltage, g2 writes a 2.44V voltage, and g3 writes a 2.26V voltage.

[0238] FIG11 is a working timing diagram of the verification simulation module shown in FIG10 .

[0239] Taking N equal to 3 as an example, in the design of a data providing circuit, taking the channel width-to-length ratio of each multiplexing transistor as 100 / 5 as an example, the minimum line width of the data line is 5μm, the minimum spacing between data lines is 3μm, the first multiplexing transistor TM1, the first reset transistor TR1, and the second reset transistor TR2 share a common gate. When the first multiplexing control terminal MUX1 is turned on and the signal arrives, DL2 and DL3 are reset through TR1 and TR2. Among them, when TR2 resets DL3, it needs to use a via structure and a scan line as a cross-line and pass through DL2. The above connection method is relatively conventional, which not only takes up a large layout area, but also requires the introduction of a via jumper, increasing the resistance. Based on this, the embodiment of the present disclosure proposes a new layout structure.

[0240] Optionally, the reset circuit in the data providing circuit may include M reset transistors; M is equal to N-1; m is a positive integer less than or equal to M;

[0241] The gate of the mth reset transistor is electrically connected to the first multiplexing control terminal, the first electrode of the mth reset transistor is electrically connected to the initial voltage line, and the second electrode of the mth reset transistor is electrically connected to the (m+1)th data line;

[0242] A first electrode of one of the M reset transistors is multiplexed as a first electrode of another reset transistor in the M multiplexing transistors.

[0243] In at least one embodiment of the present disclosure, the multiplexing circuit in the data providing circuit may include N multiplexing transistors;

[0244] The gate of the nth multiplexing transistor is electrically connected to the nth multiplexing control terminal, the first electrode of the nth multiplexing transistor is electrically connected to the data voltage supply terminal, and the second electrode of the nth multiplexing transistor is electrically connected to the nth data line;

[0245] The second electrode of the nth multiplexing transistor is multiplexed as the second electrode of the (n-1)th reset transistor.

[0246] Optionally, N is equal to 3 and M is equal to 2;

[0247] The first electrode of the first reset transistor is multiplexed as the first electrode of the second reset transistor;

[0248] The first electrode of the first reset transistor is multiplexed as the second electrode of the second multiplexing transistor, and the second electrode of the second reset transistor is multiplexed as the second electrode of the third multiplexing transistor.

[0249] In FIG12 , taking N equal to 3 and M equal to 2 as an example, the data providing circuit includes a first multiplexing transistor TM1 , a second multiplexing transistor TM2 , a third multiplexing transistor TM3 , a first reset transistor TR1 , and a second reset transistor TR2 ;

[0250] As shown in Figures 12 to 15, TM1 is set on the far left;

[0251] The second pole of TM2 is multiplexed as the second pole of TR1; the orthographic projection of the second column data line DL2 on the substrate at least partially overlaps with the orthographic projection of the second pole of TM2 on the substrate;

[0252] The first pole of TR1 is reused as the first pole of TR2. The first poles of TR1 and TR2 are both electrically connected to the initial voltage line IL. The orthographic projection of the initial voltage line IL on the substrate at least partially overlaps with the orthographic projection of the first pole of TR1 on the substrate.

[0253] The second pole of TM3 is multiplexed as the second pole of TR2; the orthographic projection of the third column data line DL3 on the base substrate at least partially overlaps with the orthographic projection of the second pole of TM3 on the base substrate.

[0254] In at least one embodiment of the layout diagram shown in FIG12 , the channel width-to-length ratio of each transistor may be 100 / 5, the minimum line width of the data line may be 5 μm, and the minimum spacing between the data lines may be 3 μm;

[0255] The second terminal DM2 of TM2 is multiplexed as the second terminal of TR1, the first terminal SR1 of TR1 is multiplexed as the first terminal of TR2, and the second terminal DM3 of TM3 is multiplexed as the second terminal of TR2. TR1 and TR2 share the initial voltage line IL, so that only one initial voltage line IL can reset the data supply circuit. This also avoids the use of vias and cross-wires, reducing loading. Calculations show that the layout shown in Figure 12 reduces the layout area by 23.2% compared to related layouts.

[0256] In FIG12 , the data line labeled DL1 is the first column, the data line labeled DL2 is the second column, and the data line labeled DL3 is the third column.

[0257] FIG13 is a layout diagram of the semiconductor layer in FIG12 , FIG14 is a layout diagram of the gate metal layer in FIG12 , and FIG15 is a layout diagram of the source / drain metal layer in FIG12 .

[0258] In FIG13 , reference numeral A1 is a first active pattern, and reference numeral A2 is a second active pattern.

[0259] In FIG. 15 , the terminal labeled D11 is the first first data voltage supply terminal, the terminal labeled D21 is the second first data voltage supply terminal, and the terminal labeled D31 is the third first data voltage supply terminal.

[0260] Optional, N equals 5, M equals 4;

[0261] The first electrode of the first reset transistor is multiplexed as the first electrode of the second reset transistor, and the first electrode of the third reset transistor is multiplexed as the first electrode of the fourth reset transistor;

[0262] The first pole of the first reset transistor is multiplexed as the second pole of the second multiplexing transistor, and the second pole of the second reset transistor is multiplexed as the second pole of the third multiplexing transistor; the first pole of the third reset transistor is multiplexed as the second pole of the fourth multiplexing transistor, and the second pole of the fourth reset transistor is multiplexed as the second pole of the fifth multiplexing transistor.

[0263] In FIG16 , taking N equal to 5 and M equal to 4 as an example, the data providing circuit includes a first multiplexing transistor TM1, a second multiplexing transistor TM2, a third multiplexing transistor TM3, a fifth multiplexing transistor TM4, a fifth multiplexing transistor TM5, a first reset transistor TR1, a second reset transistor TR2, and a third reset transistor TR3;

[0264] As shown in Figures 16 to 19, TM1 is set on the far left;

[0265] The second pole DM2 of TM2 is multiplexed as the second pole of TR1; the orthographic projection of the second column data line DL2 on the base substrate at least partially overlaps with the orthographic projection of the second pole of TM2 on the base substrate;

[0266] The first pole SR1 of TR1 is reused as the first pole of TR2. The first poles of TR1 and TR2 are both electrically connected to the first initial voltage line IL1. The orthographic projection of the first initial voltage line IL1 on the substrate at least partially overlaps with the orthographic projection of the first pole of TR1 on the substrate.

[0267] The second pole DM3 of TM3 is multiplexed as the second pole of TR2; the orthographic projection of the third column data line DL3 on the base substrate at least partially overlaps with the orthographic projection of the second pole of TM3 on the base substrate.

[0268] The first electrode SR3 of TR3 is reused as the first electrode of TR4. The first electrodes of TR1 and TR2 are both electrically connected to the second initial voltage line IL2. The orthographic projection of the second initial voltage line IL2 on the substrate at least partially overlaps with the orthographic projection of the first electrode of TR3 on the substrate.

[0269] The second pole of TR2 is multiplexed as the second pole of TM3;

[0270] The first pole SR3 of TR3 is multiplexed as the second pole of TM4;

[0271] The second pole DR4 of TR4 is multiplexed as the second pole of TM5.

[0272] FIG17 is a layout diagram of the semiconductor layer in FIG16 , FIG18 is a layout diagram of the gate metal layer in FIG16 , and FIG19 is a layout diagram of the source / drain metal layer in FIG16 .

[0273] In FIG17 , A1 is a first active pattern, A2 is a second active pattern, and A3 is a third active pattern.

[0274] In FIG19 , D11 is a first first data voltage supply terminal, D21 is a second first data voltage supply terminal, D31 is a third first data voltage supply terminal, D41 is a fourth first data voltage supply terminal, and D51 is a fifth first data voltage supply terminal.

[0275] In Figure 16, the line labeled IL1 is the first initial voltage line, the line labeled IL2 is the second initial voltage line, the line labeled DL1 is the first column data line, the line labeled DL2 is the second column data line, the line labeled DL3 is the third column data line, the line labeled DL4 is the fourth column data line, and the line labeled DL5 is the fifth data line.

[0276] In at least one embodiment of the layout diagram shown in FIG16 , the channel width-to-length ratio of each transistor may be 100 / 5, the minimum line width of the data line may be 5 μm, and the minimum spacing between the data lines may be 3 μm;

[0277] The second pole of TM2 is multiplexed as the second pole of TR1; the first pole of TR1 is multiplexed as the first pole of TR2; the second pole of TM3 is multiplexed as the second pole of TR2; the first pole of TR3 is multiplexed as the first pole of TR4; the second pole of TR2 is multiplexed as the second pole of TM3; and the first pole of TR3 is multiplexed as the second pole of TM4. Furthermore, TR1 and TR2 share the first initial voltage line IL1, so that only one first initial voltage line IL1 can provide reset for DL2 and DL3. TR3 and TR4 share the second initial voltage line, so that only one second initial voltage line IL2 can provide reset for DL4 and DL5. This also avoids the use of vias across the lines, reducing loading. Calculations show that the layout shown in Figure 16 has a smaller area than the related layout.

[0278] The display panel described in the embodiment of the present disclosure includes the above-mentioned display substrate.

[0279] The display panel described in the embodiment of the present disclosure includes the above-mentioned data providing circuit.

[0280] The display panel according to at least one embodiment of the present disclosure further includes a plurality of rows and columns of pixel circuits arranged in the display area;

[0281] The pixel circuit includes a light-emitting element, a driving circuit (T3) and a writing control circuit (T2);

[0282] The driving circuit is used to control the generation of a driving current for driving the light-emitting element under the control of the potential of the control terminal;

[0283] The write control circuit is electrically connected to the scan line, the data line and the first end of the drive circuit respectively, and is used to write the data voltage provided by the data line into the first end of the drive circuit under the control of the scan signal provided by the scan line.

[0284] As shown in FIG20 , at least one embodiment of the pixel circuit may include a light emitting element EL, a driving circuit 201 and a writing control circuit 202 ;

[0285] The driving circuit 201 is used to control the generation of a driving current for driving the light emitting element EL under the control of the potential of its control terminal;

[0286] The write control circuit 202 is electrically connected to the scan line GL, the data line DL and the first end of the driving circuit 201 respectively, and is used to write the data voltage provided by the data line DL into the first end of the driving circuit 201 under the control of the scan signal provided by the scan line GL.

[0287] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned display panel, wherein the display cycle includes a data writing phase; the data writing phase includes N writing time periods;

[0288] The driving method includes:

[0289] In a first writing time period, the reset circuit controls, under the control of a first multiplexing control signal, the initial voltage provided by the initial voltage line to be written into data lines other than the first data line among the N data lines;

[0290] In the nth writing time period, the multiplexing circuit writes the data voltage provided by the data voltage supply terminal into the nth data line under the control of the nth multiplexing control signal;

[0291] N is an integer greater than 1, and n is a positive integer less than or equal to N.

[0292] In a specific implementation, the data writing stage may include N writing time periods. In the nth writing time period, the multiplexing circuit writes the data provided by the data voltage providing end into the nth data line. In the first writing time period, the reset circuit, under the control of the first multiplexing control signal, controls the initial voltage provided by the initial voltage line to be written into the data lines other than the first data line among the N data lines.

[0293] Optionally, the display panel further includes a plurality of rows and columns of pixel circuits arranged in the display area; the pixel circuits include light-emitting elements, a driving circuit, and a writing control circuit; and the driving method further includes:

[0294] In the data writing phase, the writing control circuit writes the data voltage provided by the data line into the first end of the driving circuit under the control of the scanning signal.

[0295] In at least one embodiment of the present disclosure, in the data writing phase, the write control circuit writes the data voltage on the data line into the first terminal of the driving circuit.

[0296] Optionally, the start time of the data writing phase is the same as the start time of the first writing time period.

[0297] In at least one embodiment of the present disclosure, the display cycle also includes a pre-write stage, which is arranged before the data write stage, and the pre-write stage is adjacent to the data write stage. The driving method includes: in the pre-write stage, the reset circuit controls the initial voltage provided by the initial voltage line to be written into the N data lines except the first data line under the control of the first multiplexing control signal, and the multiplexing circuit controls the data voltage provided by the data voltage supply end to be written into the first data line under the control of the first multiplexing control signal.

[0298] In a specific implementation, the first multiplexing control terminal is opened at the same time as the scan line, or the first multiplexing control terminal is opened before the scan line, so as to prevent the voltage signal remaining on the first data line in the previous display cycle from affecting the potential of the gate of the driving transistor in the pixel circuit corresponding to the first column.

[0299] As shown in FIG21 , when at least one embodiment shown in FIG7 is in operation, the phase labeled S1 is the M-1th row reset phase, the phase labeled S2 is the M-1th row data write phase, and the phase labeled S3 is the M-1th row light emitting phase;

[0300] The time when the scan line GLM-1 starts to provide a low voltage in the M-1th row is the same as the time when MUX1 starts to provide a low voltage.

[0301] As shown in FIG22 , when at least one embodiment shown in FIG7 is in operation, the phase labeled S1 is the M-1th row reset phase, the phase labeled S2 is the M-1th row data write phase, and the phase labeled S3 is the M-1th row light emitting phase;

[0302] The time when MUX1 starts to provide a low voltage before the scan line GLM-1 in the M-1th row starts to provide a low voltage;

[0303] In FIG. 22 , the phase labeled S0 is the pre-writing phase.

[0304] As shown in FIG21, at least one embodiment shown in FIG7 is in operation.

[0305] In the reset phase S1 of the M-1th row, RST(M-1) provides a low voltage signal, T11, T17, T21, T27, T51, and T57 are turned on, and Vi resets the potential of the gate of T13, the potential of the gate of T23, the potential of the gate of T53, the potential of the anode of O1, the potential of the gate of O2, and the potential of the gate of O5; in at least one embodiment of the present disclosure, Vi and Vint may be the same;

[0306] In the M-1th row data writing phase S2, GLM-1 provides a low voltage signal, T12, T22 and T52 are turned on, and T15, T25 and T55 are turned on;

[0307] In the M-1th row data writing phase S2, MUX1, MUX2, and MUX3 are turned on in sequence, that is, S2 includes a first time period, a second time period, and a third time period set in sequence; in the first time period, MUX1 provides a low voltage signal, and MUX2 and MUX3 provide a high voltage signal; in the second time period, MUX2 provides a low voltage signal, and MUX1 and MUX3 provide a high voltage signal; in the third time period, MUX3 provides a low voltage signal, and MUX1 and MUX2 provide a high voltage signal;

[0308] In the first time period, MUX1 provides a low voltage signal, TM1 is turned on, D1 provides the first data voltage to DL1, and provides the compensated first data voltage to the gate of T13 through T12, T13 and T15, TR1 and TR2 are turned on, and DL2 and DL3 are reset through Vint;

[0309] In the second time period, MUX2 provides a low voltage signal, TM2 is turned on, D1 provides the second data voltage to DL2, and provides the compensated second data voltage to the gate of T23 through T22, T23 and T25;

[0310] In the third time period, MUX3 provides a low voltage signal, TM3 is turned on, D1 provides the third data voltage to DL3, and provides the compensated third data voltage to the gate of T53 through T52, T53 and T55;

[0311] In the M-1th row light-emitting stage S3, EM(M-1) provides a low voltage signal, T14, T16, T24, T26, T54 and T56 are turned on, T13 drives O1 to emit light, T23 drives O2 to emit light, and T53 drives O5 to emit light.

[0312] In at least one embodiment of the present disclosure, N is not limited to being equal to 2, 3, or 5. In a specific implementation, N may be an integer greater than 1.

[0313] The driving method according to at least one embodiment of the present disclosure further includes:

[0314] In the ath writing time period, the data voltage provided by the data voltage supply terminal is controlled to be Va+ΔVa; a is an integer less than or equal to N and greater than 1;

[0315] ΔVa is equal to (Va-Vth-V0)×(e-(t1-t0a) / RC)-e -(t1 / RC) );

[0316] Wherein, Vth is the threshold voltage of the driving transistor included in the driving circuit, and Va is the data voltage to be written into the ath data line in the ath writing time period;

[0317] t1 is the duration of the data writing phase, and t0a is equal to (a-1)×(t2+t3);

[0318] Among them, t2 is the duration of each write time period, t3 is the interval between two adjacent write time periods, R is the resistance value of the resistor on the data line, C is the capacitance value of the coupling capacitor on the data line, and V0 is the voltage on the data line after the reset circuit, under the control of the first multiplexing control signal, controls the initial voltage provided by the initial voltage line to be written into the data lines other than the first data line among the N data lines.

[0319] As shown in Figure 11, when the verification simulation module in Figure 10 is simulated and verified, the potential of g1, the potential of g2 and the potential of g3 will be different. This is because when the scan line is turned on, the coupling capacitor on DL1 will be charged first, and will continue to charge g1 during the period when the second data voltage is written to DL2 and the third data voltage is written to DL3; similarly, DL2 will also continue to charge during the period when the third data voltage is written to DL3, which will cause the potential of g1 to be greater than the potential of g2, and the potential of g2 to be greater than the potential of g3. Therefore, at least one embodiment of the present disclosure provides a data voltage compensation method.

[0320] As shown in FIG23 , the first writing period is marked S21, the second writing period is marked S22, and the third writing period is marked S23; the scanning line is marked GL, the first multiplexing control terminal is marked MUX1, the second multiplexing control terminal is marked MUX2, and the third multiplexing control terminal is marked MUX3.

[0321] The time period labeled S01 is the first interval, the time period labeled S02 is the second interval, and the time period labeled S03 is the third interval;

[0322] The duration of S2 is t1, the duration of S21, S22 and S23 are the same, all t2; the duration of S01, S02 and S03 are the same, all t3; then the compensation charging time of DL2 is t2+t3, and the compensation charging time of DL3 is 2t2+2t3; assuming that when MUX2 is turned on, the voltage to be written to DL2 is V2; when MUX3 is turned on, the voltage to be written to DL3 is V3; then, the compensation voltage ΔV2 to be written to DL2 is approximately V0+(V2-Vth)-V0)×(1-e -(t1 / RC) )-(V0+(V2-Vth-V0)×(1-e-((t1-t2-t3) / RC) )), that is, ΔV2 is approximately (V2-Vth-V0)×(e-((t1-t2-t3) / RC))-e -(t1 / RC)); DL3 needs to write a compensation voltage ΔV3 which is approximately V0+(V2-Vth)-V0)×(1-e -(t1 / RC) )-(V0+(V2-Vth-V0)×(1-e-((t1-2t2-2t3) / RC) )), that is, ΔV3 is approximately (V2-Vth-V0)×(e-((t1-2t2-2t3) / RC))-e -(t1 / RC) ); then the voltage that DL2 needs to actually write is approximately V2+ΔV2, and the voltage that DL3 needs to actually write is approximately V3+ΔV3;

[0323] Among them, Vth is the threshold voltage of the driving transistor included in each driving circuit, R is the resistance value of the resistor on each data line, C is the capacitance value of the coupling capacitor on each data line, and V0 is the voltage on the corresponding data line after TR1 and TR2 write the initial voltage Vint to the corresponding data line; V0 is approximately the same as Vint.

[0324] After the above compensation method is used, as shown in FIG24 , when the verification simulation module in FIG10 is simulated and verified, when the target data voltage is 3V, the potentials of g1 , g2 and g3 all reach about 2.53V.

[0325] The display device described in the embodiment of the present disclosure includes the above-mentioned display panel.

[0326] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A data providing circuit, comprising a multiplexing circuit and a reset circuit; N is an integer greater than 1; The multiplexing circuit is electrically connected to the data voltage supply terminal, N multiplexing control terminals and N data lines respectively, and is used to write the data voltage provided by the data voltage supply terminal into the nth data line under the control of the nth multiplexing control signal provided by the nth multiplexing control terminal; n is a positive integer less than or equal to N; The reset circuit is electrically connected to the first multiplexing control terminal, the initial voltage line and the data lines other than the first data line among the N data lines, respectively, and is used to control the initial voltage provided by the initial voltage line to be written into the data lines other than the first data line among the N data lines under the control of the first multiplexing control signal provided by the first multiplexing control terminal.

2. The data providing circuit according to claim 1, wherein: The reset circuit includes M reset subcircuits; M is equal to N-1; m is a positive integer less than or equal to M; The control end of the mth reset subcircuit is electrically connected to the first multiplexing control end, the first end of the mth reset subcircuit is electrically connected to the initial voltage line, and the second end of the mth reset subcircuit is electrically connected to the (m+1)th data line; The mth reset subcircuit is used for writing the initial voltage provided by the initial voltage line into the (m+1)th data line under the control of the first multiplexing control signal provided by the first multiplexing control terminal.

3. The data providing circuit according to claim 1, wherein: The multiplexing circuit includes N multiplexing sub-circuits; The control end of the nth multiplexing subcircuit is electrically connected to the nth multiplexing control end, the first end of the nth multiplexing subcircuit is electrically connected to the data voltage supply end, and the second end of the nth multiplexing subcircuit is electrically connected to the nth data line; The nth multiplexing sub-circuit is used for writing the data voltage provided by the data voltage providing end into the nth data line under the control of the nth multiplexing control signal provided by the nth multiplexing control end.

4. A display substrate, comprising a base and the data providing circuit according to any one of claims 1 to 3 arranged on the base.

5. The display substrate according to claim 4, wherein: The reset circuit in the data providing circuit includes M reset subcircuits; M is equal to N-1; m is a positive integer less than or equal to M; The control end of the mth reset subcircuit is electrically connected to the first multiplexing control end, the first end of the mth reset subcircuit is electrically connected to the initial voltage line, and the second end of the mth reset subcircuit is electrically connected to the m+1th data line; the mth reset subcircuit is used to write the initial voltage provided by the initial voltage line into the m+1th data line under the control of the first multiplexing control signal provided by the first multiplexing control end; A first end of a reset subcircuit in the M reset subcircuits is multiplexed as a first end of another reset subcircuit in the M multiplexing subcircuits.

6. The display substrate according to claim 5, wherein: The multiplexing circuit in the data providing circuit includes N multiplexing sub-circuits; The control end of the nth multiplexing subcircuit is electrically connected to the nth multiplexing control end, the first end of the nth multiplexing subcircuit is electrically connected to the data voltage supply end, and the second end of the nth multiplexing subcircuit is electrically connected to the nth data line; The circuit is used for writing the data voltage provided by the data voltage providing end into the nth data line under the control of the nth multiplexing control signal provided by the nth multiplexing control end; The second end of the nth multiplexing subcircuit is multiplexed as the second end of the n-1th reset subcircuit.

7. The display substrate according to claim 6, wherein: The mth reset subcircuit includes an mth reset transistor; A gate of the mth reset transistor is electrically connected to the first multiplexing control terminal, a first electrode of the mth reset transistor is electrically connected to the initial voltage line, and a second electrode of the mth reset transistor is electrically connected to the (m+1)th data line; A first electrode of one of the M reset transistors is multiplexed as a first electrode of another reset transistor of the M multiplexed transistors.

8. The display substrate according to claim 7, wherein: The nth multiplexing subcircuit comprises an nth multiplexing transistor; The gate of the nth multiplexing transistor is electrically connected to the nth multiplexing control terminal, the first electrode of the nth multiplexing transistor is electrically connected to the data voltage supply terminal, and the second electrode of the nth multiplexing transistor is electrically connected to the nth data line; The second electrode of the nth multiplexing transistor is multiplexed as the second electrode of the n-1th reset transistor.

9. The display substrate according to claim 8, wherein: N is equal to 3, M is equal to 2; The first electrode of the first reset transistor is multiplexed as the first electrode of the second reset transistor; The first electrode of the first reset transistor is multiplexed as the second electrode of the second multiplexing transistor, and the second electrode of the second reset transistor is multiplexed as the second electrode of the third multiplexing transistor.

10. The display substrate according to claim 8, wherein: N is equal to 5, M is equal to 4; The first electrode of the first reset transistor is multiplexed as the first electrode of the second reset transistor, and the first electrode of the third reset transistor is multiplexed as the first electrode of the fourth reset transistor; The first pole of the first reset transistor is multiplexed as the second pole of the second multiplexing transistor, and the second pole of the second reset transistor is multiplexed as the second pole of the third multiplexing transistor; the first pole of the third reset transistor is multiplexed as the second pole of the fourth multiplexing transistor, and the second pole of the fourth reset transistor is multiplexed as the second pole of the fifth multiplexing transistor.

11. A display panel comprising the display substrate according to any one of claims 4 to 10.

12. A display panel comprising the data providing circuit according to any one of claims 1 to 3.

13. The display panel according to claim 12, wherein: It also includes a plurality of rows and columns of pixel circuits arranged in the display area; The pixel circuit includes a light emitting element, a driving circuit and a writing control circuit; The driving circuit is used to control the generation of a driving current for driving the light-emitting element under the control of the potential of its control terminal; The write control circuit is electrically connected to the scan line, the data line and the first end of the drive circuit respectively, and is used to write the data voltage provided by the data line into the first end of the drive circuit under the control of the scan signal provided by the scan line.

14. A driving method, applied to the display panel according to claim 12 or 13, wherein the display cycle includes a data writing phase; the data writing phase includes N writing time periods; The driving method comprises: In the first writing time period, the reset circuit controls the initial voltage line to provide a voltage level under the control of the first multiplexing control signal. Writing an initial voltage into data lines other than the first data line among the N data lines; In the nth writing time period, the multiplexing circuit writes the data voltage provided by the data voltage supply terminal into the nth data line under the control of the nth multiplexing control signal; N is an integer greater than 1, and n is a positive integer less than or equal to N.

15. The driving method according to claim 14, wherein: The display panel also includes a plurality of rows and columns of pixel circuits arranged in the display area; The pixel circuit includes a light emitting element, a driving circuit and a writing control circuit; the driving method also includes: In the data writing phase, the writing control circuit writes the data voltage provided by the data line into the first end of the driving circuit under the control of the scanning signal.

16. The driving method according to claim 15, wherein: The data writing phase starts at the same time as the first writing time period starts.

17. The driving method according to claim 15, wherein: The display cycle also includes a pre-writing stage, which is arranged before the data writing stage, and the pre-writing stage is adjacent to the data writing stage. The driving method includes: in the pre-writing stage, the reset circuit controls the initial voltage provided by the initial voltage line to be written into the data lines other than the first data line among the N data lines under the control of the first multiplexing control signal, and the multiplexing circuit controls the data voltage provided by the data voltage supply end to be written into the first data line under the control of the first multiplexing control signal.

18. The driving method according to any one of claims 15 to 17, wherein: Also includes: In the ath writing time period, controlling the data voltage provided by the data voltage supply terminal to be Va+ΔVa; a is an integer less than or equal to N and greater than 1; ΔVa is equal to (Va-Vth-V0)×(e -(t1-t0a) / RC )-e -(t1 / RC) ); Wherein, Vth is the threshold voltage of the driving transistor included in the driving circuit, and Va is the data voltage to be written into the ath data line in the ath writing time period; t1 is the duration of the data writing phase, and t0a is equal to (a-1)×(t2+t3); Among them, t2 is the duration of each writing time period, t3 is the interval between two adjacent writing time periods, R is the resistance value of the resistor on the data line, C is the capacitance value of the coupling capacitor on the data line, and V0 is the voltage on the data line after the reset circuit, under the control of the first multiplexing control signal, controls the initial voltage provided by the initial voltage line to be written into the data lines other than the first data line among the N data lines.

19. A display device comprising the display panel according to any one of claims 11 to 13.

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