Pixel drive circuit and display panel

Abstract

The present application provides a pixel drive circuit and a display panel. The pixel drive circuit comprises an output module, a current control module, and a duration control module. The duration control module comprises a first input unit and a first capacitor which are connected to one another. A second polar plate of the first capacitor is connected to a voltage control signal terminal. The voltage control signal terminal outputs periodic light-emitting control signals in a light-emitting stage. When the voltage control signal terminal is configured to be in a first voltage range, the output module is turned on. When the voltage control signal terminal is configured to be in a second voltage range, the output module is turned off.

Description

Pixel driving circuit and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel driving circuit and a display panel. Background Art

[0002] Micro light-emitting diodes, such as Mini LED and Micro LED, have significant advantages such as higher brightness, better luminous efficiency and lower power consumption, and have become the focus of research in the display panel industry.

[0003] Currently, micro-LEDs typically use a hybrid driving method of pulse amplitude modulation (PAM) and pulse width modulation (PWM) to control the display grayscale and pixel emission time. However, when displaying low grayscale, the small driving current of the LED within one frame causes the display device to flicker. SUMMARY OF THE INVENTION

[0004] The present application provides a gate driving circuit and a display panel to solve the technical problem of a large frame of an existing display panel.

[0005] To solve the above problems, the technical solutions provided by this application are as follows:

[0006] The present application provides a pixel driving circuit to solve the technical problem of flickering in existing display panels during low grayscale display.

[0007] To solve the above problems, the technical solutions provided by this application are as follows:

[0008] The present application provides a pixel driving circuit for providing a signal to a driven element, comprising:

[0009] a current control module configured to transmit a first electrical signal;

[0010] a duration control module configured to transmit a second electrical signal, the duration control module comprising a first input unit and a first capacitor, the first input unit and a first plate of the first capacitor being connected to a first control node, and the second plate of the first capacitor being connected to a voltage control signal terminal;

[0011] an output module, wherein a first end of the output module is electrically connected to the current control module, a second end of the output module is electrically connected to the duration control module, and a third end of the output module is electrically connected to the element to be driven;

[0012] In which, in the light-emitting stage of the pixel driving circuit, the voltage control signal end outputs a periodic light-emitting control signal, and the light-emitting control signal includes a first voltage range and a second voltage range. When the voltage control signal end is configured to the first voltage range, the output module is turned on, and when the voltage control signal end is configured to the second voltage range, the output module is turned off.

[0013] The present application further provides a display panel, comprising a plurality of sub-pixel units, each of which is provided with a connected pixel driving circuit and a to-be-driven element, wherein the pixel driving circuit is configured to provide a signal to the to-be-driven element; wherein the pixel driving circuit comprises:

[0014] a current control module configured to transmit a first electrical signal;

[0015] a duration control module configured to transmit a second electrical signal, the duration control module comprising a first input unit and a first capacitor, the first input unit and a first plate of the first capacitor being connected to a first control node, and the second plate of the first capacitor being connected to a voltage control signal terminal;

[0016] an output module, wherein a first end of the output module is electrically connected to the current control module, a second end of the output module is electrically connected to the duration control module, and a third end of the output module is electrically connected to the element to be driven;

[0017] In which, in the light-emitting stage of the pixel driving circuit, the voltage control signal end outputs a periodic light-emitting control signal, and the light-emitting control signal includes a first voltage range and a second voltage range. When the voltage control signal end is configured to output the first voltage range, the output module is turned on, and when the voltage control signal end is configured to output the second voltage range, the output module is turned off. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG1 is a structural diagram of a first type of pixel driving circuit of the present application;

[0019] FIG2 is a second structural diagram of the pixel driving circuit of the present application;

[0020] FIG3 is a timing control diagram of the pixel driving circuit of the present application;

[0021] FIG4 is a timing control diagram of the light emitting control signal in FIG3 ;

[0022] FIG5 is a state diagram of the pixel driving circuit in FIG1 in the first stage;

[0023] FIG6 is a state diagram of the pixel driving circuit in FIG1 in the second stage;

[0024] FIG7 is a diagram showing a first state of the pixel driving circuit in FIG1 during a light emitting phase;

[0025] FIG8 is a second state diagram of the pixel driving circuit in FIG1 during the light emitting stage;

[0026] FIG9 is a simplified structural diagram of the display panel of the present application. Modes for Carrying Out the Invention

[0027] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0028] Currently, when displaying low grayscale images, micro-LED displays experience flickering due to the low driving current of the LEDs within a frame. This application proposes the following technical solutions to address this technical issue:

[0029] Referring to Figures 1 to 9, the present application provides a pixel driving circuit 100 for providing a signal to an element to be driven 140, which includes a current control module 110, a duration control module 120 and an output module 130 connected to each other. The current control module 110 can be configured to transmit a first electrical signal, and the duration control module 120 can be configured to transmit a second electrical signal. The duration control module 120 is used to control the turn-on time of the output module 130, and the output module 130 is used to transmit the first electrical signal output by the current control module 110 to the element to be driven 140.

[0030] In this embodiment, the duration control module 120 includes a first input unit 121 and a first capacitor C1, the first input unit 121 and the first plate of the first capacitor C1 are connected to the first control node P, the second plate of the first capacitor C1 is connected to the voltage control signal terminal Sw, and the output module 130 can be electrically connected to the duration control module 120 and the current control module 110 respectively.

[0031] In this embodiment, a first end of the output module 130 is electrically connected to the current control module 110 , a second end of the output module 130 is electrically connected to the duration control module 120 , and a third end of the output module 130 is electrically connected to the driven element 140 .

[0032] In this embodiment, in the light-emitting stage t3 of the pixel driving circuit 100, the voltage control signal terminal Sw outputs a periodic light-emitting control signal Sw1, and the light-emitting control signal Sw1 includes a first voltage range and a second voltage range. When the voltage control signal terminal Sw is configured to the first voltage range, the output module 130 is turned on, and when the voltage control signal terminal Sw is configured to the second voltage range, the output module 130 is turned off.

[0033] It should be noted that the first electrical signal is a current signal of the pixel driving circuit, and the second electrical signal is a time signal of the pixel driving circuit.

[0034] In the prior art, the duration control module 120 and the current control module 110 are usually arranged in series so that light is emitted after both the duration control module 120 and the current control module 110 complete data writing. However, the series arrangement of the duration control module 120 and the current control module 110 causes the duration control module 120 to affect the output current of the current control module 110. Especially at low grayscale, the output current of the current control module 110 will be further reduced, thereby causing the display device to have a technical problem of flickering.

[0035] The present application controls the conduction time of the output module 130 by regulating the potential of the first control node P in the duration control module 120, thereby outputting multiple pulse signals within one frame time. At the same time, the series connection of the current control module 110 and the output module 130 ensures that the output current of the current control module 110 is not affected by the duration control module 120, thereby increasing the driving current entering the element to be driven 140 and improving the technical problem of flickering in the display device at low grayscale.

[0036] 1 , the duration control module 120 further includes a level amplifying unit 122 . A first terminal of the level amplifying unit 122 is connected to the first control node P, and a second terminal of the level amplifying unit 122 is connected to the second terminal of the output module 130 .

[0037] In this embodiment, the level amplifying unit 122 includes a first amplifying transistor T6 and a second amplifying transistor T7. The gate of the first amplifying transistor T6 is connected to the first control node P, the drain of the first amplifying transistor T6 is connected to the second control node Q, the gate of the second amplifying transistor T7 is connected to the first scan signal terminal Scan1, the source of the second amplifying transistor T7 is connected to the second control node Q, and the output module 130 is connected to the second control node Q.

[0038] In this embodiment, the source of the first amplifying transistor T6 is connected to one of the first low voltage line Vgl or the first high voltage line Vgh, and the drain of the second amplifying transistor T7 is connected to the other of the first low voltage line Vgl or the first high voltage line Vgh. For example, in the structure of FIG. 1 , the source of the first amplifying transistor T6 is connected to the first low voltage line Vgl, and the drain of the second amplifying transistor T7 is connected to the first high voltage line Vgh; or in the structure of FIG. 2 , the source of the first amplifying transistor T6 is connected to the first high voltage line Vgh, and the drain of the second amplifying transistor T7 is connected to the first low voltage line Vgl.

[0039] In this embodiment, the first input unit 121 may include a first input transistor T5, the gate of the first input transistor T5 is connected to the fourth scan signal terminal Scan4, the source of the first input transistor T5 is connected to the first data signal terminal Data1, and the drain of the first input transistor T5 is connected to the first control node P.

[0040] In this embodiment, since the second plate of the first capacitor C1 is connected to the voltage control signal terminal Sw, and the voltage control signal terminal Sw outputs a periodic light-emitting control signal Sw1, as the light-emitting control signal Sw1 increases or decreases, the potential of the first control node P will change following the change of the light-emitting control signal Sw1, and the potential change of the first control node P will control the conduction and shutdown of the first amplifying transistor T6, thereby controlling the potential change of the second control node Q.

[0041] In the pixel driving circuit 100 of the present application, the impedance of the first amplifying transistor T6 is smaller than the impedance of the second amplifying transistor T7 . For example, in the light-emitting stage t3 of the pixel driving circuit 100, the first scan signal terminal Scan1 outputs a high level to turn on the second amplifier transistor T7, and the second control node Q will be connected to the first high voltage line Vgh. The potential of the second control node Q is pulled up to a high level, thereby turning on the output module 130. The driving current output by the current control module 110 is transmitted to the to-be-driven element 140 through the output module 130, and the to-be-driven element 140 emits light; and as the potential of the first control node P is pulled up, the first amplifier transistor T6 is turned on, and the second control node Q will be connected to the first high voltage line Vgh and the first low voltage line Vgl at the same time. Since the impedance of the first amplifier transistor T6 is smaller than the impedance of the second amplifier transistor T7, the divided voltage of the second amplifier transistor T7 is greater than the divided voltage of the first amplifier transistor T6, and the potential of the second control node Q is pulled down to a low level close to the first low voltage line Vgl, thereby turning off the output module 130, and the to-be-driven element 140 does not emit light. Therefore, the present application can adjust the conduction time of the output module 130 by adjusting the output voltage of the voltage control signal terminal Sw, thereby avoiding the influence of the duration control module 120 on the output current of the current control module 110.

[0042] In this embodiment, in the first phase t1 of the pixel driving circuit 100, the gate of the first input transistor T5 receives a high level input by the fourth scan signal terminal Scan4, the first input transistor T5 is turned on, and the data signal input by the first data signal terminal Data1 is transmitted to the first control node P through the first input transistor T5. At this time, the potential of the first control node P is Va; in the second phase t2 of the pixel driving circuit 100, the first input transistor T5 is turned off, and the potential of the second plate of the first capacitor C1 drops from Vc1 to Vc2. At this time, The potential of the first control node P is Va-(Vc1-Vc2); in the light-emitting stage t3 of the pixel driving circuit 100, the potential of the second plate of the first capacitor C1 increases from Vc2 by ΔV. At this time, the potential of the first control node P is Va-(Vc1-Vc2)+ΔV. As ΔV gradually increases, when the difference between the potential of the first control node P and the threshold voltage Vth of the first amplifying transistor T6 is greater than 0, the first amplifying transistor T6 will be turned on, the potential of the second control node Q will be pulled down to a low level, and the output module 130 will be turned off.

[0043] In this embodiment, two adjacent light-emission control signals Sw1 are continuous, and the maximum value of the first voltage range is less than or equal to the minimum value of the second voltage range. For example, referring to FIG3 , the voltage signal output by the voltage control signal terminal Sw during the light-emission phase t3 is a trapezoidal signal, with the two adjacent trapezoidal signals connected to each other. In FIG3 , the area between the dashed lines AB represents the first voltage range, and the dashed line BC represents the second voltage range. When the voltage output by the voltage control signal terminal Sw exceeds the dashed line B, the difference between the potential of the first control node P and the threshold voltage Vth of the first amplifying transistor T6 becomes greater than zero, turning on the first amplifying transistor T6.

[0044] Please refer to Figure 4. In the light-emitting stage of the pixel driving circuit, the voltage of the light-emitting control signal at the first moment a1 can be the first voltage m1, the voltage of the light-emitting control signal at the second moment a2 can be the second voltage m2, and the voltage of the light-emitting control signal at the third moment a3 can be the third voltage m3. The first voltage m1 and the third voltage m3 are within the first voltage range, and the second voltage m2 is within the second voltage range; at the same time, the first voltage m1 and the third voltage m3 can be equal and both are voltage A, and the second voltage m2 is voltage C.

[0045] In this embodiment, during the period from the first moment a1 to the second moment a2, the first voltage m1 is boosted to the second voltage m2, and during the period from the second moment a2 to the third moment a3, the second voltage m2 is reduced to the third voltage m3.

[0046] In this embodiment, the waveform of the light-emitting control signal Sw1 can be a sine wave, a triangle wave, a trapezoidal wave, etc.; it should be noted that, in order to display different gray levels, the output transistor needs to have a time difference for turning on and off. Since the different data voltages in the square wave signal are turned on and off at the same time, no brightness difference can be formed.

[0047] In this embodiment, the first amplifying transistor T6 includes a first channel, the second amplifying transistor T7 includes a second channel, and the width of the first channel is greater than that of the second channel; or the length of the first channel is less than that of the second channel.

[0048] In this embodiment, the impedance of the first amplifying transistor T6 and the second amplifying transistor T7 can be adjusted by adjusting the length and width of the channels in the corresponding transistors. For example, when the lengths of the first channel and the second channel are the same, the width of the first channel can be made larger than the width of the second channel. The increase in the channel width increases the conduction rate of the transistor and reduces the impedance of the transistor. Therefore, the impedance of the first amplifying transistor T6 is smaller than the impedance of the second amplifying transistor T7. Alternatively, when the widths of the first channel and the second channel are the same, the length of the first channel can be made smaller than the length of the second channel. The reduction in the channel length increases the conduction rate of the transistor and reduces the impedance of the transistor. Therefore, the impedance of the first amplifying transistor T6 is smaller than the impedance of the second amplifying transistor T7.

[0049] In this embodiment, the first amplifying transistor T6 includes a first gate, and the second amplifying transistor T7 includes a second gate. The first gate has a first size in a direction from the source to the drain of the first amplifying transistor T6, and the second gate has a second size in a direction from the source to the drain of the second amplifying transistor T7, where the first size is greater than the second size. That is, the width of the first gate is greater than the width of the second gate, and the electric field strength applied by the first gate on the first channel is greater, thereby increasing the conduction rate of the first amplifying transistor T6 and reducing the impedance of the first amplifying transistor T6. Therefore, the impedance of the first amplifying transistor T6 is less than the impedance of the second amplifying transistor T7.

[0050] Referring to Figure 1, the current control module 110 includes a second input unit 111, a second capacitor C2 and a driving transistor T2. The second input unit 111, the first plate of the second capacitor C2 and the gate of the driving transistor T2 are connected to the third control node G, the second plate of the second capacitor C2 and the drain of the driving transistor T2 are connected to the fourth control node S, and the source of the driving transistor T2 is connected to the second high voltage line Vdd.

[0051] In this embodiment, the output module 130 includes an output transistor T4, the gate of the output transistor T4 is connected to the second control node Q, the source of the output transistor T4 is connected to the fourth control node S, the drain of the output transistor T4 is connected to the first end of the driven element 140, and the second end of the driven element 140 is connected to the second low voltage line Vss.

[0052] In this embodiment, the second input unit 111 includes a second input transistor T1, the gate of the second input transistor T1 is connected to the third scan signal terminal Scan3, the source of the second input transistor T1 is connected to the second data signal terminal Data2, and the drain of the second input transistor T1 is connected to the third control node G; in the second phase t2 of the pixel driving circuit 100, the third scan signal terminal Scan3 is input with a high level, the second input transistor T1 is turned on, and the data signal output by the second data signal terminal Data2 is transmitted to the third control node G through the second input transistor T1. At the same time, the second capacitor C2 begins to charge, and since the output transistor T4 is turned off, the driving current output by the driving transistor T2 cannot be transmitted to the element to be driven 140; in the light-emitting phase t3, the second capacitor C2 maintains the potential of the third control node G, so that the driving transistor T2 is turned on. At this time, the output transistor T4 is turned on, and the driving current output by the driving transistor T2 is transmitted to the element to be driven 140.

[0053] Referring to FIG. 1 , the pixel driving circuit 100 further includes a switching transistor T8 connected to the output module 130 and the current control module 110. The gate of the switching transistor T8 is connected to the enable signal line, the source of the switching transistor T8 is connected to the fourth control node S, and the drain of the switching transistor T8 is connected to the source of the output transistor T4. Because the driving transistor T2 and the switching transistor T8 are connected in series, to prevent the driven element 140 from emitting light during the non-light-emitting phase t3, the present application provides a switching transistor T8 between the driving transistor T2 and the switching transistor T8. The switching transistor T8 is only turned on during the light-emitting phase t3.

[0054] Referring to FIG. 1 , the current control module 110 further includes a reference unit 112 including a reference transistor T3. The gate of the reference transistor T3 is connected to the second scan signal terminal Scan2, the source of the reference transistor T3 is connected to a reference voltage line, and the drain of the reference transistor T3 is connected to a fourth control node S. The timing data output by the third scan signal terminal Scan3 is the same as the timing data output by the second scan signal terminal Scan2. The drive current transmitted from the drive transistor T2 is related to the potential of the drive transistor T2 at the third control node G and the fourth control node S. Therefore, to ensure the accuracy of the potential of the fourth control node S, the present application connects the fourth control node S to the reference voltage line to calibrate the potential of the fourth control node S during the second phase t2.

[0055] In this embodiment, in order to prevent the output transistor T4 from affecting the magnitude of the driving current transmitted from the current control module 110, the output transistor T4 needs to be turned on as fully as possible when the driven element 140 is emitting light. Therefore, the voltage of the first high-voltage line Vgh needs to be as high as possible, and the voltage of the first low-voltage line Vgl needs to be as low as possible. For example, the voltage of the first high-voltage line Vgh is greater than the voltage of the second high-voltage line Vdd, and the voltage of the first low-voltage line Vgl is less than the voltage of the second low-voltage line Vss.

[0056] The pixel driving circuit 100 in FIG. 1 of the present application is described in detail below with reference to the timing diagram in FIG. 3 .

[0057] In the first stage t1, please refer to Figure 5, the first scan signal terminal Scan1, the second scan signal terminal Scan2, the third scan signal terminal Scan3, and the enable signal terminal output a low level, the second input transistor T1, the reference transistor T3, the switch transistor T8, and the second amplifier transistor T7 are turned off, the fourth scan signal terminal Scan4 outputs a high level, the first input transistor T5 is turned on, and the data signal output by the first data signal terminal Data1 is transmitted to the first control node P through the source and drain of the first input transistor T5. The potential of the first control node P is pulled up to Va. At this time, the high potential of the first control node P turns on the first amplifier transistor T6, the second control node Q is connected to the first low voltage line Vgl, and the low level of the second control node Q turns off the output transistor T4.

[0058] In the second phase t2, referring to FIG6 , the first scan signal terminal Scan1, the fourth scan signal terminal Scan4, and the enable signal terminal output low levels, the first input transistor T5, the switch transistor T8, and the second amplifier transistor T7 are turned off, and the potential of the second plate of the first capacitor C1 drops from Vc1 to Vc2. At this time, the potential of the first control node P is Va-(Vc1-Vc2), and the potential of the first control node P is insufficient to turn on the first amplifier transistor T6. The first amplifier transistor T6 is turned off, and the second control node Q maintains a low level to turn off the output transistor T4.

[0059] Secondly, the second scan signal terminal Scan2 and the third scan signal terminal Scan3 output a high level, the second input transistor T1 and the reference transistor T3 are turned on, and the data signal output by the second data signal terminal Data2 is transmitted to the third control node G through the source and drain of the second input transistor T1. The potential of the third control node G is pulled to a high potential, and the second capacitor C2 starts to charge. In addition, the reference voltage of the reference voltage line is transmitted to the fourth control node S through the reference transistor T3 to calibrate the potential of the fourth control node S to the reference potential.

[0060] In the light-emitting stage t3, please refer to Figures 7 and 8, the second scan signal terminal Scan2 and the third scan signal terminal Scan3 output a low level, the second input transistor T1 and the reference transistor T3 are turned off, and the second capacitor C2 maintains a high potential at the third control node G to turn on the driving transistor T2.

[0061] Next, referring to FIG7 , the first scan signal terminal Scan1 outputs a low level, the first input transistor T5 is turned off, the fourth scan signal terminal Scan4 outputs a high level, the second amplifying transistor T7 is turned on, and the potential of the second control node Q is pulled to a high level, thereby turning on the output transistor T4. At the same time, the enable signal terminal outputs a high level, turning on the switch transistor T8. The drive current output by the current control module 110 is transmitted to the driven element 140 through the source and drain of the switch transistor T8 and the source and drain of the output transistor T4, thereby causing the driven element 140 to emit light.

[0062] Again, referring to FIG. 8 , when the potential of the second plate of the first capacitor C1 increases by ΔV from Vc2, the potential of the first control node P is Va-(Vc1-Vc2)+ΔV. As ΔV gradually increases, when the difference between the potential of the first control node P and the threshold voltage Vth of the first amplifying transistor T6 is greater than 0, the first amplifying transistor T6 is turned on, and the second control node Q is connected to both the first high voltage line Vgh and the first low voltage line Vgl. Since the impedance of the first amplifying transistor T6 is smaller than the impedance of the second amplifying transistor T7, the divided voltage of the second amplifying transistor T7 is greater than the divided voltage of the first amplifying transistor T6. As a result, the potential of the second control node Q is pulled down to a low level close to the first low voltage line Vgl, the output module 130 is turned off, and the to-be-driven element 140 does not emit light.

[0063] Finally, when the potential of the second plate of the first capacitor C1 gradually decreases, and the difference between the potential of the first control node P and the threshold voltage Vth of the first amplifying transistor T6 is less than or equal to 0, the first amplifying transistor T6 will be turned off, the potential of the second control node Q will be pulled up to a high potential, the output transistor T4 will be turned on, and the driving current output by the current control module 110 will be transmitted to the driven element 140, and the driven element 140 will emit light.

[0064] For example, in the light-emitting stage t3 of Figure 3, the area between the dotted lines AB in Figure 3 is the first voltage range, and the dotted line BC is the second voltage range. When the voltage output by the voltage control signal terminal Sw is between the dotted lines BC, the difference between the potential of the first control node P and the threshold voltage Vth of the first amplifying transistor T6 is greater than 0, the first amplifying transistor T6 will be turned on, the second control node Q will be pulled down to a low level, the output transistor T4 will be turned off, and the element to be driven 140 will not emit light; when the voltage output by the voltage control signal terminal Sw is between the dotted lines AB, the difference between the potential of the first control node P and the threshold voltage Vth of the first amplifying transistor T6 is less than or equal to 0, the first amplifying transistor T6 will be turned off, the second control node Q will be pulled up to a high level, the output transistor T4 will be turned on, and the element to be driven 140 will emit light.

[0065] It should be noted that the timing control diagram in Figure 3 is illustrated using the example of all transistors in the pixel driving circuit 100 being N-type transistors. The transistors in the pixel driving circuit 100 of the present application can also be P-type transistors, or a mixture of P-type transistors or N-type transistors, and different types of transistors have different timing control diagrams.

[0066] For the pixel driving circuit in FIG2 , in the first phase t1, the first amplifying transistor T6 is turned on, the second control node Q is at a high level, and the output transistor T4 is turned on. However, since the switching transistor T8 is turned off, the element to be driven does not emit light in this phase. In the second phase t2, since the switching transistor T8 is turned off, the element to be driven does not emit light. In the third phase, the switching transistor T8 is turned on, but since the second amplifying transistor T7 is turned on, the second control node Q is pulled down to a low level, and the output transistor T4 is turned off. As the potential of the first control node P increases, the first amplifying transistor T6 is turned on, and the second control node Q is connected to both the first high voltage line Vgh and the first low voltage line Vgl. Since the impedance of the first amplifying transistor T6 is smaller than the impedance of the second amplifying transistor T7, the divided voltage of the second amplifying transistor T7 is greater than the divided voltage of the first amplifying transistor T6. As a result, the potential of the second control node Q is pulled down to a high level close to the first high voltage line Vgh, the output module 130 is turned on, and the element to be driven 140 emits light.

[0067] Please refer to Figure 9. The present application also proposes a display panel 200, which includes a plurality of sub-pixel units 210. Each sub-pixel unit is provided with the above-mentioned pixel driving circuit 100 and the element to be driven 140. The pixel driving circuit 100 is connected to the element to be driven 140. The element to be driven is a current-driven light-emitting diode, such as Mini LED, Micro LED or conventional LED.

[0068] This application also proposes a display device comprising a terminal body and the aforementioned display panel, the terminal body and display panel being integrated into one body. The terminal body may be a device such as a circuit board bound to the display panel. The display device may include electronic devices such as mobile phones, televisions, and laptop computers.

[0069] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0070] The above is a detailed introduction to a pixel driving circuit provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A pixel driving circuit for providing a signal to a driven element, comprising: a current control module configured to transmit a first electrical signal; A duration control module is configured to transmit a second electrical signal, the duration control module comprising a first input unit and a first capacitor, the first input unit and a first plate of the first capacitor are connected to a first control node, and a second plate of the first capacitor is connected to a voltage control signal terminal; an output module, wherein a first end of the output module is electrically connected to the current control module, a second end of the output module is electrically connected to the duration control module, and a third end of the output module is electrically connected to the element to be driven; Among them, in the light-emitting stage of the pixel driving circuit, the voltage control signal end outputs a periodic light-emitting control signal, and the light-emitting control signal includes a first voltage range and a second voltage range. When the voltage control signal end is configured to output the first voltage range, the output module is turned on, and when the voltage control signal end is configured to output the second voltage range, the output module is turned off.

2. The pixel driving circuit according to claim 1, wherein: The duration control module further includes a level amplifying unit, a first end of the level amplifying unit is connected to the first control node, and a second end of the level amplifying unit is connected to the second end of the output module.

3. The pixel driving circuit according to claim 2, wherein: The level amplifying unit includes a first amplifying transistor and a second amplifying transistor, the gate of the first amplifying transistor is connected to the first control node, the drain of the first amplifying transistor is connected to the second control node, the gate of the second amplifying transistor is connected to the first scanning signal terminal, the source of the second amplifying transistor is connected to the second control node, and the output module is connected to the second control node; Among them, the source of the first amplifier transistor is connected to one of the first low voltage line or the first high voltage line, the drain of the second amplifier transistor is connected to the other of the first low voltage line or the first high voltage line, and the impedance of the first amplifier transistor is smaller than the impedance of the second amplifier transistor.

4. The pixel driving circuit according to claim 3, wherein: The first amplifying transistor includes a first channel, and the second amplifying transistor includes a second channel; The width of the first channel is greater than the width of the second channel, or the length of the first channel is less than the length of the second channel.

5. The pixel driving circuit according to claim 3, wherein: The first amplifying transistor includes a first gate, and the second amplifying transistor includes a second gate; The first gate has a first size in a direction from the source to the drain of the first amplifying transistor, and the second gate has a second size in a direction from the source to the drain of the second amplifying transistor, and the first size is larger than the second size.

6. The pixel driving circuit according to claim 2, wherein: The current control module includes a second input unit, a second capacitor and a driving transistor, wherein the second input unit, the first plate of the second capacitor and the gate of the driving transistor are connected to a third control node, the second plate of the second capacitor and the drain of the driving transistor are connected to a fourth control node, and the source of the driving transistor is connected to a second high voltage line; The output module comprises an output transistor, a gate of the output transistor is connected to the second control node, a source of the output transistor is connected to the fourth control node, and a drain of the output transistor is connected to the first end of the element to be driven.

7. The pixel driving circuit according to claim 6, wherein: The second end of the driven element is connected to a second low voltage line, the voltage of the first high voltage line is greater than the voltage of the second high voltage line, and the voltage of the first low voltage line is less than the voltage of the second low voltage line.

8. The pixel driving circuit according to claim 1, wherein: Two adjacent light emitting control signals are continuous, and the maximum value of the first voltage range is less than or equal to the minimum value of the second voltage range.

9. The pixel driving circuit according to claim 8, wherein: The voltage of the light-emitting control signal at a first moment is a first voltage, the voltage of the light-emitting control signal at a second moment is a second voltage, the voltage of the light-emitting control signal at a third moment is a third voltage, the first voltage and the third voltage are within the first voltage range, and the second voltage is within the second voltage range; In the process from the first moment to the second moment, the first voltage is boosted to the second voltage, and in the process from the second moment to the third moment, the second voltage is stepped down to the third voltage.

10. The pixel driving circuit according to claim 8, wherein: The waveform of the light emitting control signal is a sine wave, a triangle wave or a trapezoidal wave.

11. A display panel, comprising a plurality of sub-pixel units, each of which is provided with a connected pixel driving circuit and a to-be-driven element, wherein the pixel driving circuit is used to provide a signal to the to-be-driven element; wherein: The pixel driving circuit comprises: a current control module configured to transmit a first electrical signal; A duration control module is configured to transmit a second electrical signal, the duration control module comprising a first input unit and a first capacitor, the first input unit and a first plate of the first capacitor are connected to a first control node, and a second plate of the first capacitor is connected to a voltage control signal terminal; an output module, wherein a first end of the output module is electrically connected to the current control module, a second end of the output module is electrically connected to the duration control module, and a third end of the output module is electrically connected to the element to be driven; Among them, in the light-emitting stage of the pixel driving circuit, the voltage control signal end outputs a periodic light-emitting control signal, and the light-emitting control signal includes a first voltage range and a second voltage range. When the voltage control signal end is configured to output the first voltage range, the output module is turned on, and when the voltage control signal end is configured to output the second voltage range, the output module is turned off.

12. The display panel according to claim 11, wherein: The duration control module further includes a level amplifying unit, a first end of the level amplifying unit is connected to the first control node, and a second end of the level amplifying unit is connected to the second end of the output module.

13. The display panel according to claim 12, wherein: The level amplifying unit includes a first amplifying transistor and a second amplifying transistor, the gate of the first amplifying transistor is connected to the first control node, the drain of the first amplifying transistor is connected to the second control node, the gate of the second amplifying transistor is connected to the first scanning signal terminal, the source of the second amplifying transistor is connected to the second control node, and the output module is connected to the second control node; Among them, the source of the first amplifier transistor is connected to one of the first low voltage line or the first high voltage line, the drain of the second amplifier transistor is connected to the other of the first low voltage line or the first high voltage line, and the impedance of the first amplifier transistor is smaller than the impedance of the second amplifier transistor.

14. The display panel according to claim 13, wherein: The first amplifying transistor includes a first channel, and the second amplifying transistor includes a second channel; The width of the first channel is greater than the width of the second channel, or the length of the first channel is less than the length of the second channel.

15. The display panel according to claim 13, wherein: The first amplifying transistor includes a first gate, and the second amplifying transistor includes a second gate; The first gate has a first size in a direction from the source to the drain of the first amplifying transistor, and the second gate has a second size in a direction from the source to the drain of the second amplifying transistor, and the first size is larger than the second size.

16. The display panel according to claim 12, wherein: The current control module includes a second input unit, a second capacitor and a driving transistor, wherein the second input unit, the first plate of the second capacitor and the gate of the driving transistor are connected to a third control node, the second plate of the second capacitor and the drain of the driving transistor are connected to a fourth control node, and the source of the driving transistor is connected to a second high voltage line; The output module comprises an output transistor, a gate of the output transistor is connected to the second control node, a source of the output transistor is connected to the fourth control node, and a drain of the output transistor is connected to the first end of the element to be driven.

17. The display panel according to claim 16, wherein: The second end of the driven element is connected to a second low voltage line, the voltage of the first high voltage line is greater than the voltage of the second high voltage line, and the voltage of the first low voltage line is less than the voltage of the second low voltage line.

18. The display panel according to claim 11, wherein: Two adjacent light emitting control signals are continuous, and the maximum value of the first voltage range is less than or equal to the minimum value of the second voltage range.

19. The display panel according to claim 18, wherein: The voltage of the light-emitting control signal at a first moment is a first voltage, the voltage of the light-emitting control signal at a second moment is a second voltage, the voltage of the light-emitting control signal at a third moment is a third voltage, the first voltage and the third voltage are within the first voltage range, and the second voltage is within the second voltage range; In the process from the first moment to the second moment, the first voltage is boosted to the second voltage, and in the process from the second moment to the third moment, the second voltage is stepped down to the third voltage.

20. The display panel according to claim 18, wherein: The waveform of the light emitting control signal is a sine wave, a triangle wave or a trapezoidal wave.

Images