Display panel

Abstract

The present application provides a display panel, comprising a reset signal line, clock signal lines, and first-type gate driving units, wherein each first-type gate driving unit comprises: a redundant input unit, a first input end and a second input end of the redundant input unit being in a floating state; and a first-type output unit, a first input end of the first-type output unit being connected to an output end of the redundant input unit and the reset signal line, and a second input end of the first-type output unit being connected to the reset signal line and being disconnected from the clock signal lines.

Description

Display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] For a display panel with a gate driving circuit disposed on an array substrate, when a large-sized display panel needs to be cut again to prepare a small-sized display panel, the cut small-sized display panel may fail to display.

[0003] Therefore, a technical solution is needed to solve the problem that the small-sized display panel cannot display after being cut. SUMMARY OF THE INVENTION

[0004] The purpose of this application is to provide a display panel to ensure that the display panel can display normally.

[0005] In a first aspect, the present application provides a display panel, comprising:

[0006] Reset signal line;

[0007] Clock signal line;

[0008] a plurality of scanning signal lines; and

[0009] A plurality of cascaded gate driving units include a first type of gate driving unit, wherein the first type of gate driving unit includes:

[0010] A redundant input unit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal and the second input terminal of the redundant input unit are in a floating state;

[0011] The first type of output unit has a first input end, a second input end and an output end. The first input end of the first type of output unit is connected to the output end of the redundant input unit and the reset signal line. The second input end of the first type of output unit is connected to the reset signal line and disconnected from the clock signal line. The output end of the first type of output unit is connected to one of the scan signal lines.

[0012] In some embodiments, the plurality of cascaded gate driving units further include a second type of gate driving unit, and the second type of gate driving unit includes:

[0013] An input unit, used for outputting a driving signal;

[0014] The second type of output unit has a first input end, a second input end and an output end. The first input end of the second type of output unit is connected to the output end of the input unit, the second input end of the second type of output unit is connected to the clock signal line, and the output end of the second type of output unit is connected to one of the scanning signal lines.

[0015] In some embodiments, the display panel further includes a constant voltage signal line;

[0016] The first type gate driving unit further includes: a redundant reset unit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the redundant reset unit is connected to the reset signal line, the output terminal of the redundant reset unit is connected to the output terminal of the redundant input unit and the first input terminal of the first type output unit, and the second input terminal of the redundant reset unit is disconnected from the constant voltage signal line;

[0017] The second type of gate driving unit also includes: a reset unit having a first input end, a second input end and an output end, the first input end of the reset unit is connected to the reset signal line, the second input end of the reset unit is connected to the constant voltage signal line, and the output end of the reset unit is connected to the first input end of the second type output unit and the output end of the input unit.

[0018] In some embodiments, the display panel further includes: a first connecting line connected between the constant voltage signal line and the redundant reset unit, and including a first break.

[0019] In some embodiments, the display panel further includes: a second connecting line connected between the clock signal line and the first type output unit, and including a second break.

[0020] In some embodiments, the second connection line is connected to the reset signal line through a first via hole, and the second connection line connects the first type output unit and the reset signal line, and the first via hole and the second break are spaced apart.

[0021] In some embodiments, the display panel further comprises:

[0022] substrate;

[0023] a first conductive layer, disposed on the substrate and comprising the reset signal line;

[0024] a second conductive layer, disposed on a side of the first conductive layer away from the substrate, and comprising the second connecting line, wherein the second fracture is staggered with the conductive portion of the first conductive layer;

[0025] The insulating layer is disposed between the first conductive layer and the second conductive layer and includes the first via hole, wherein an orthographic projection of the first via hole on the substrate overlaps with an orthographic projection of the reset signal line on the substrate.

[0026] In some embodiments, the second conductive layer further comprises:

[0027] A third connecting line connects the first input end of the first type output unit and the reset signal line, and is connected to the reset signal line through a second via hole on the insulating layer, wherein the second via hole is spaced apart from the first via hole.

[0028] In some embodiments, the display panel further includes:

[0029] Multiple data lines;

[0030] a source driving circuit connected to the plurality of data lines and disposed on one side of the display panel;

[0031] The first type gate driving unit is located on a side of the second type gate driving unit away from the source driving circuit.

[0032] In some embodiments, the display panel further comprises:

[0033] The starting signal line is disconnected from the first type of gate driving unit. Beneficial effects

[0034] The present application provides a display panel. For a first-type gate driver unit, when the first input terminal and the second input terminal of a redundant input unit are in a floating state, the first input terminal of the first-type output unit and the output terminal of the redundant input unit are connected to a reset signal line, thereby pulling up the potential of the first input terminal of the first-type output unit via a reset signal transmitted by the reset signal line. Furthermore, the second input terminal of the first-type output unit is connected to the reset signal line and disconnected from the clock signal line, and the output terminal of the first-type output unit is connected to a scan signal line. In this way, under the control of the reset signal of the first input terminal, the reset signal inputted from the second input terminal is outputted as a scan signal to the scan signal line, thereby ensuring that the first-type gate driver unit normally outputs the scan signal, thereby ensuring that the display panel can display normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG. 1 is a schematic structural diagram of an initial display panel in some related technologies.

[0036] FIG2 is a schematic diagram of a planar structure of a display panel according to some embodiments of the present application.

[0037] FIG3 is a circuit diagram of a first type of gate driving unit according to some embodiments of the present application.

[0038] FIG. 4 is a circuit diagram of a second type of gate driving unit according to some embodiments of the present application.

[0039] FIG. 5 is a partially enlarged schematic diagram of a non-display area according to some embodiments of the present application.

[0040] FIG. 6 is a schematic cross-sectional view of the structure taken along the AA′ line in FIG. 5 . Modes for Carrying Out the Invention

[0041] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0042] FIG1 is a schematic diagram illustrating the structure of an initial display panel in some related technologies. Initial display panel 100 is a large-size display panel. For example, the initial display panel has a resolution of 1920×1080, but is not limited thereto. Initial display panel 100 includes, but is not limited to, any of a liquid crystal display panel, an organic light-emitting diode display panel, and a quantum dot display panel.

[0043] The initial display panel 100 includes an initial display area 100a and an initial non-display area 100b, with the initial non-display area 100b surrounding the initial display area 100a. The initial display panel 100 also includes a source driver circuit 11, a gate driver circuit 12, a plurality of data lines 13, and a plurality of scan signal lines 14. The plurality of data lines 13 intersect with the plurality of scan signal lines 14. The plurality of data lines 13 are connected to the source driver circuit 11. The plurality of scan signal lines 14 are connected to the gate driver circuit 12.

[0044] The gate driver circuit 12 is located on at least one side of the initial display area 100a. For example, the gate driver circuit 12 is located on one side of the initial display area 100a, but is not limited thereto. It is understood that the gate driver circuit 12 can also be located on two opposite sides of the initial display area 100a.

[0045] The gate driving circuit 12 includes a plurality of cascaded gate driving units 121. For example, the plurality of cascaded gate driving units 121 include a first-stage gate driving unit GOA(1) to an n-th-stage gate driving unit GOA(n), where n is 1080, but is not limited thereto. The first-stage gate driving unit GOA(1) to the n-th-stage gate driving unit GOA(n) are arranged in sequence along the extension direction of the data line 13. The first-stage gate driving unit GOA(1) is arranged away from the source driving circuit 11, and the n-th-stage gate driving unit GOA(n) is arranged close to the source driving circuit 11.

[0046] The plurality of cascaded gate drive units 121 are all connected to the reset signal line 15. The first-stage gate drive unit GOA(1) to the m-th-stage gate drive unit GOA(m) (not shown) in the plurality of cascaded gate drive units 121 are all connected to the start signal line 16, where m is an integer greater than or equal to 1 and less than n. The (m+1)-th-stage gate drive unit GOA(m+1) to the n-th-stage gate drive unit GOA(n) in the plurality of cascaded gate drive units 121 are all respectively connected to the plurality of clock signal lines 17. For example, m is equal to 4, but is not limited thereto.

[0047] When the initial display panel 100 needs to be cut into a smaller display panel, it can be cut along the cutting line AA' shown in FIG1 , and the panel portion including the first-stage gate driver unit GOA (1) is cut off to obtain a cut display panel. For example, the resolution of the cut display panel is 1920×540 or 1920×810.

[0048] For the display panel after cutting, the gate drive circuit 12 after cutting includes the i-th gate drive unit GOA(i) to the n-th gate drive unit GOA(n), where i is an integer greater than m and less than n. After cutting, since the i-th gate drive unit GOA(i) is not connected to the start signal line 16, the i-th gate drive unit GOA(i) cannot output the scan signal and the corresponding level transmission signal. Therefore, the gate drive circuit 12 of the display panel after cutting cannot output the scan signal normally, resulting in the display panel after cutting not being able to display normally.

[0049] To address the issues in the related art, the inventive concept of this application includes the following: the reset signal transmitted by the reset signal line and the start signal transmitted by the start signal line have the same frequency and potential characteristics, and the reset signal line is connected to each gate drive unit in the gate drive circuit. Therefore, the reset signal transmitted by the reset signal line can be used to replace the start signal. Moreover, the high-level signal of the reset signal can also serve as the drive signal for the pull-up node.

[0050] The specific solution of the present application includes, for the first type of gate drive unit of the display panel that has been processed after cutting, that is, the first few levels of gate drive units of the gate drive circuit in the scanning direction, when the first input end and the second input end of the redundant input unit are in a floating state, the first input end of the first type of output unit is connected to the output end of the redundant input unit and the reset signal line. In this way, the potential of the first input end of the first type of output unit can be pulled up by the reset signal transmitted by the reset signal line to control the conduction and shutdown of the first type of output unit. Moreover, the second input end of the first type of output unit is connected to the reset signal line and disconnected from the clock signal line, that is, the reset signal transmitted by the reset signal line is used to replace the start signal. In this way, under the control of the reset signal of the first input end, the reset signal inputted at the second input end is outputted to the scanning signal line as a scanning signal, thereby ensuring that the first type of gate drive unit outputs the scanning signal normally, thereby ensuring that the display panel can display normally.

[0051] The display panels of some embodiments of the present application are described in detail below with reference to specific embodiments.

[0052] Referring to FIG. 2 , a schematic diagram of the planar structure of a display panel according to some embodiments of the present application is shown. The display panel 200 is obtained through cutting and subsequent processing. The display panel 200 includes a display area 200 a and a non-display area 200 b disposed around the display area 200 a. The display panel 200 includes a source driver circuit 21, a gate driver circuit 22, a plurality of data lines 23, and a plurality of scan signal lines 24.

[0053] At least a portion of each of the plurality of data lines 23 is disposed in the display area 200a. The plurality of data lines 23 extend along the second direction y1 and are spaced apart along the first direction x. The plurality of data lines 23 are connected to the source driver circuit 21. The source driver circuit 21 may be located on a first side of the display area 200a in the second direction y1. The first direction x intersects the second direction y1. Specifically, the first direction x is perpendicular to the second direction y1, but is not limited thereto.

[0054] At least a portion of each of the plurality of scan signal lines 24 is disposed in the display area 200a. The plurality of scan signal lines 24 extend along the first direction x and are spaced apart along the second direction y1. The plurality of scan signal lines 24 are all connected to the gate drive circuit 22. The gate drive circuit 22 can be located on the second side of the display area 200a in the first direction x, with the second side being adjacent to the first side, but is not limited thereto. It is understood that the gate drive circuit 22 can also be located on the second and third sides of the display area 200a in the first direction x, with both the second and third sides being adjacent to the first side.

[0055] As shown in FIG2 , the gate driving circuit 22 includes a plurality of gate driving units 221, and the plurality of gate driving units 221 include a first-stage gate driving unit GOA(1) to a j-th-stage gate driving unit GOA(j), where j is an integer greater than 1. The first-stage gate driving unit GOA(1) to the j-th-stage gate driving unit GOA(j) are sequentially arranged along the second direction y1. The first-stage gate driving unit GOA(1) is disposed away from the source driving circuit 21, and the j-th-stage gate driving unit GOA(j) is disposed close to the source driving circuit 21.

[0056] When the display panel 200 is displaying, the first-stage gate driver unit GOA(1) to the j-stage gate driver unit GOA(j) sequentially output scanning signals. That is, when the display panel 200 is displaying, scanning is performed along the second direction y1, i.e., reverse scanning. In this way, the loads of the multiple data lines 23 when transmitting data signals to the near-end data lines closer to the source driver circuit 21 and the far-end data lines farther from the source driver circuit 21 are uniform, which is beneficial for improving the display effect of the display panel 200.

[0057] 2 , the plurality of gate drive units 221 include a first type of gate drive unit 222 and a second type of gate drive unit 223. The first type of gate drive unit 222 is located on a side of the second type of gate drive unit 223 that is away from the source drive circuit 21. Thus, the first type of gate drive unit 222 is farther away from the source drive circuit 21. The first type of gate drive unit 222 is a processed gate drive unit after cutting, while the second type of gate drive unit 223 is an unprocessed gate drive unit after cutting.

[0058] The plurality of first-class gate driving units 222 may include one or more adjacent gate driving units 221 disposed away from the source driving circuit 21. The plurality of gate driving units 221 other than the plurality of first-class gate driving units 222 are all second-class gate driving units 223. For example, the first-class gate driving unit 222 includes the first-level gate driving unit GOA(1), and the second-class gate driving unit 223 includes the j-th level gate driving unit GOA(j), but is not limited thereto.

[0059] In the present application, the display panel 200 further includes a start signal line 25, a constant voltage signal line 28, a reset signal line 26, and multiple clock signal lines 27. One start signal line 25, one reset signal line 26, multiple clock signal lines 27, and constant voltage signal line 28 are located on a side of the gate driver circuit 22 away from the display area 200a. The start signal line 25 is used to transmit a start signal. The reset signal line 26 is used to transmit a reset signal Reset. The multiple clock signal lines 27 are used to transmit a clock signal CK. The constant voltage signal line 28 is used to transmit a constant voltage signal VSS.

[0060] The display panel 200 is obtained through cutting and subsequent processing. Before cutting, the first several stages of gate driving units along the scanning direction are all connected to the starting signal line 25. After cutting, the first several stages of gate driving units connected to the starting signal line 25 are cut away, and the first type of gate driving units 222 and the second type of gate driving units 223 of the gate driving circuit 22 on the display panel 200 are no longer connected to the starting signal line 25.

[0061] Referring to FIG3 , which is a circuit diagram of a first-class gate driving unit in some embodiments of the present application, the first-class gate driving unit GOA (1) in the first-class gate driving unit 222 is described below. The other levels in the first-class gate driving unit 222 can be deduced similarly and will not be described again here. The first-class gate driving unit 222 includes a redundant input unit 2221, a first-class output unit 2222, a redundant reset unit 2223, a first-class pull-down maintaining unit 2224, a first-class pull-down unit 2225, a first-class stage transmission unit 2226, and a first-class bootstrap capacitor 2227.

[0062] The redundant input unit 2221 has a first input terminal, a second input terminal, and an output terminal. Before being cut, the first and second input terminals of the redundant input unit 2221 can be connected to the previous gate driver unit to receive the previous stage transmission signal and the previous stage scanning signal, respectively. After being cut, the previous gate driver unit to which the first and second input terminals of the redundant input unit 2221 are connected is cut off. Therefore, the first and second input terminals of the redundant input unit 2221 are both in a floating state, that is, the first and second input terminals of the redundant input unit 2221 are not connected to any signal.

[0063] Specifically, the redundant input unit 2221 includes a first transistor T11, the gate of which is in a floating state. One of the source and drain of the first transistor T11 is also in a floating state, and the other of the source and drain of the first transistor T11 is connected to the first input terminal of the first-type output unit 2222.

[0064] The first type output unit 2222 has a first input terminal, a second input terminal and an output terminal. The output terminal of the first type output unit 2222 is connected to a scan signal line 24 .

[0065] The first input terminal of the first-type output unit 2222 is connected to the output terminal of the redundant input unit 2221 and the reset signal line 26. The first-type pull-up node Q1 (e.g., the first-type pull-up node Q(1)) is located on the line connecting the first input terminal of the first-type output unit 2222 and the output terminal of the redundant input unit 2221. The first-type pull-up node Q1 is connected to the reset signal line 26, and the reset signal Reset transmitted by the reset signal line 26 can be directly output to the first-type pull-up node Q1.

[0066] When the two input terminals of the redundant input unit 2221 are in a floating state and cannot output a pull-up control signal to the first type pull-up node Q1, the reset signal Reset transmitted by the reset signal line 26 can control the first input terminal of the first type output unit 2222 and the potential of the first type pull-up node Q, thereby controlling the conduction and closing of the first type output unit 2222.

[0067] The second input terminal of the first type output unit 2222 is connected to the reset signal line 26 and disconnected from the clock signal line 27. In the present application, based on the fact that the reset signal Reset transmitted by the reset signal line 26 and the start signal transmitted by the start signal line have the same frequency and potential characteristics, when the second input terminal of the first type output unit 2222 is disconnected from the clock signal line 27, the reset signal Reset transmitted by the reset signal line 26 replaces the start signal as the input signal of the first type output unit 2222, thereby ensuring the output of the first type output unit 2222.

[0068] It should be noted that before cutting, the second input terminal of the first type output unit 2222 is connected to the clock signal line 27. After cutting and subsequent processing, the second input terminal of the first type output unit 2222 of the display panel 200 is connected to the reset signal line 26 and the clock signal line 27 is disconnected.

[0069] It can be seen from this that for the first type output unit 2222 of the first type gate driving unit 222, under the control of the reset signal Reset of the first input terminal, the reset signal Reset input from the second input terminal is output as a scan signal to the scan signal line 24, ensuring that the first type gate driving unit 222 outputs the scan signal normally, thereby ensuring that the display panel 200 can display normally.

[0070] Specifically, the first-type output unit 2222 includes a second transistor T21. The gate of the second transistor T21 is connected to the other of the source and drain of the first transistor T11 and the reset signal line 26. One of the source and drain of the second transistor T21 is connected to the reset signal line 26 and is disconnected from the clock signal line 27. The other of the source and drain of the second transistor T21 is connected to a scan signal line 24.

[0071] The first-class stage transmission unit 2226 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first-class stage transmission unit 2226 is connected to the output terminal of the redundant input unit 2221 and the reset signal line 26. The second input terminal of the first-class stage transmission unit 2226 is connected to the reset signal line 26 and is disconnected from the clock signal line 27. Therefore, for the first-class stage transmission unit 2226 of the first-class gate driving unit 222, under the control of the reset signal Reset at the first input terminal, the reset signal Reset input at the second input terminal is output through the output terminal of the first-class stage transmission unit 2226 as the stage transmission signal (e.g., ST(1)) of the current stage, so as to control the output of the gate driving unit 221 of the other stage.

[0072] Specifically, the first-class stage transfer unit 2226 includes a third transistor T22. The gate of the third transistor T22 is connected to the other of the source and drain of the first transistor T11 and the reset signal line 26. One of the source and drain of the third transistor T22 is connected to the reset signal line 26 and disconnected from the clock signal line 27. The other of the source and drain of the third transistor T22 outputs the stage transfer signal.

[0073] Two plates of the first-type bootstrap capacitor C are connected to the first-type pull-up node Q1 and the output terminal of the first-type output unit 2222 respectively.

[0074] The redundant reset unit 2223 has a first input, a second input, and an output. The first input of the redundant reset unit 2223 is connected to the reset signal line 26. The output of the redundant reset unit 2223 is connected to the output of the redundant input unit 2221 and the first input of the first-type output unit 2222. The second input of the redundant reset unit 2223 is disconnected from the constant voltage signal line 28. This disconnects the redundant reset unit 2223 from the constant voltage signal line 28 when the reset signal line 26 outputs the reset signal Reset to the first-type pull-up node Q1. This prevents the redundant reset unit 2223 from being turned on and outputting the constant voltage signal VSS transmitted by the constant voltage signal line 28 to the first-type pull-up node Q1, thereby affecting the potential of the first-type pull-up node Q1. Furthermore, disconnecting the redundant reset unit 2223 from the constant voltage signal line 28 can also mitigate the problem of leakage through the redundant reset unit 2223 when the reset signal line 26 outputs the reset signal Reset to the first-type pull-up node Q1.

[0075] Specifically, the redundant reset unit 2223 includes a fourth transistor T71. The gate of the fourth transistor T71 is connected to the reset signal line 26. One of the source and drain of the fourth transistor T71 is disconnected from the constant voltage signal line 28. The other of the source and drain of the fourth transistor T71 is connected to the output terminal of the redundant input unit 2221 and the first input terminal of the first-type output unit 2222. At this time, the other of the source and drain of the fourth transistor T71 is connected to the first-type pull-up node Q1. The constant voltage signal VSS can be a low-level signal, but is not limited thereto.

[0076] The first-class pull-down unit 2225 is used to pull down the potential of the first-class pull-up node Q1. The first-class pull-down unit 2225 is also used to pull down the potential of the scan signal (e.g., G(1)) output by the first-class output unit 2222 to the constant voltage signal VSS. The first-class pull-down unit 2225 has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal of the first-class pull-down unit 2225 is connected to the constant voltage signal line 28 to receive the constant voltage signal VSS. The second input terminal of the first-class pull-down unit 2225 receives the lower-level scan signal (e.g., G(1+X)), where X is an integer greater than or equal to 1. The first output terminal of the first-class pull-down unit 2225 is connected to the first-class pull-up node Q1. The second output terminal of the first-class pull-down unit 2225 is connected to the output terminal of the first-class output unit 2222, that is, the second output terminal of the first-class pull-down unit 2225 is connected to a scan signal line 24.

[0077] The first-type pull-down unit 2225 includes a fifth transistor T31 and a sixth transistor T41. The gate of the fifth transistor T31 and the gate of the sixth transistor T41 both receive the lower-level scan signal G(1+X). One of the source and drain of the fifth transistor T31 and one of the source and drain of the sixth transistor T41 both receive the constant voltage signal VSS transmitted by the constant voltage signal line 28. The other of the source and drain of the fifth transistor T31 is connected to the output terminal of the first-type output unit 2222. The other of the source and drain of the sixth transistor T41 is connected to the first-type pull-up node Q1.

[0078] The first type of pull-down sustaining unit 2224 includes a first pull-down sustaining unit and a second pull-down sustaining unit. During the display process of the display panel 200, the first pull-down sustaining unit and the second pull-down sustaining unit work alternately to extend the service life of the gate driving circuit 22 and thus extend the service life of the display panel 200.

[0079] The first pull-down maintaining unit includes a first inverter 224 and a first pull-down voltage stabilizing unit 225. The first inverter 224 includes a seventh transistor T51, an eighth transistor T52, a ninth transistor T53, and a tenth transistor T54. The first pull-down voltage stabilizing unit 225 includes an eleventh transistor T32 and a twelfth transistor T42.

[0080] A gate of the seventh transistor T51 and one of a source and a drain of the seventh transistor T51 receive the first control signal LC1 .

[0081] The gate of the eighth transistor T52 is connected to the first type pull-up node Q1. One of the source and drain of the eighth transistor T52 receives the constant voltage signal VSS. The other of the source and drain of the eighth transistor T52 is connected to the other of the source and drain of the seventh transistor T51.

[0082] The gate of the ninth transistor T53 is connected to the other of the source and drain of the eighth transistor T52 and the other of the source and drain of the seventh transistor T51. One of the source and drain of the ninth transistor T53 receives the first control signal LC1. The other of the source and drain of the ninth transistor T53 is connected to the gate of the eleventh transistor T32 and the gate of the twelfth transistor T42.

[0083] The gate of the tenth transistor T54 is connected to the first type pull-up node Q1. One of the source and drain of the tenth transistor T54 receives the constant voltage signal VSS. The other of the source and drain of the tenth transistor T54 is connected to the gate of the eleventh transistor T32 and the gate of the twelfth transistor T42.

[0084] One of the source and drain of the eleventh transistor T32 receives the constant voltage signal VSS. The other of the source and drain of the eleventh transistor T32 is connected to the output terminal of the first-type output unit 2222. The pull-down sustain unit including the eleventh transistor T32 is configured to pull down the potential of the scan signal to the constant voltage signal VSS during the pull-down sustain phase.

[0085] One of the source and drain of the twelfth transistor T42 receives the constant voltage signal VSS. The other of the source and drain of the twelfth transistor T42 is connected to the first-type pull-up node Q1. The pull-down sustain unit including the twelfth transistor T42 is configured to pull down the potential of the first-type pull-up node Q1 to the constant voltage signal VSS during a pull-down sustain phase.

[0086] The second pull-down maintaining unit includes a second inverter 227 and a second pull-down stabilizing unit 226. The second inverter 227 includes a thirteenth transistor T61, a fourteenth transistor T62, a fifteenth transistor T63, and a sixteenth transistor T64. The second pull-down stabilizing unit 226 includes a seventeenth transistor T33 and an eighteenth transistor T43.

[0087] A gate of the thirteenth transistor T61 and one of a source and a drain of the thirteenth transistor T61 receive the second control signal LC2 .

[0088] The phase of the second control signal LC2 is opposite to that of the first control signal LC1, and the phase of the second control signal LC2 periodically alternates with the phase of the first control signal LC1. For example, from the 1st frame to the 100th frame, one of the second control signal LC2 and the first control signal LC1 is a high-level signal, and the other is a low-level signal. From the 101st frame to the 200th frame, one of the second control signal LC2 and the first control signal LC1 is a low-level signal, and the other is a high-level signal.

[0089] The gate of the fourteenth transistor T62 is connected to the first type pull-up node Q1. One of the source and drain of the fourteenth transistor T62 receives the constant voltage signal VSS. The other of the source and drain of the fourteenth transistor T62 is connected to the other of the source and drain of the thirteenth transistor T61.

[0090] The gate of the fifteenth transistor T63 is connected to the other of the source and drain of the fourteenth transistor T62 and the other of the source and drain of the thirteenth transistor T61. One of the source and drain of the fifteenth transistor T63 receives the second control signal LC2. The other of the source and drain of the fifteenth transistor T63 is connected to the gate of the seventeenth transistor T33 and the gate of the eighteenth transistor T43.

[0091] The gate of the sixteenth transistor T64 is connected to the first type pull-up node Q1. One of the source and drain of the sixteenth transistor T64 receives the constant voltage signal VSS. The other of the source and drain of the sixteenth transistor T64 is connected to the gate of the seventeenth transistor T33 and the gate of the eighteenth transistor T43.

[0092] One of the source and drain of the seventeenth transistor T33 receives the constant voltage signal VSS. The other of the source and drain of the seventeenth transistor T33 is connected to the output terminal of the first-type output unit 2222. Therefore, the pull-down sustain unit including the seventeenth transistor T33 is used to pull down the potential of the scan signal to the constant voltage signal VSS during the pull-down sustain phase.

[0093] One of the source and drain of the eighteenth transistor T43 receives the constant voltage signal VSS. The other of the source and drain of the eighteenth transistor T43 is connected to the first-type pull-up node Q1. Therefore, the pull-down sustain unit including the eighteenth transistor T43 is used to pull down the potential of the first-type pull-up node Q1 to the constant voltage signal VSS during the pull-down sustain phase.

[0094] In some embodiments, the first transistor T11 to the eighteenth transistor T43 may all be N-type transistors, but the present invention is not limited thereto. The first transistor T11 to the eighteenth transistor T43 may all be P-type transistors.

[0095] As shown in Figure 4, it is a circuit diagram of the second type of gate drive unit in some embodiments of the present application. Taking the Nth stage gate drive unit in the second type gate drive unit 223 as an example, the circuits of other stages in the second type gate drive unit 223 can be deduced similarly and will not be repeated here. N is an integer greater than 1 and less than or equal to j. The design of the second type gate drive unit 223 is basically similar to that of the first type gate drive unit 222. The similarities are not repeated here. The differences include that the second type gate drive unit 223 also includes an input unit 2231, a second type output unit 2232, a reset unit 2233, and a second type stage transmission unit 2234.

[0096] The input unit 2231 is configured to output a driving signal to a second-type pull-up node Q2 (e.g., Q(N)). The second-type pull-up node Q2 is located on the line connecting the input unit 2231 and the second-type output unit 2232. The input unit 2231 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the input unit 2231 receives an upper-level stage transfer signal ST(NX). The second input terminal of the input unit 2231 receives an upper-level scan signal G(NX). The output terminal of the input unit 2231 is connected to the second-type pull-up node Q2.

[0097] Specifically, input unit 2231 includes a transistor T11'. The gate of transistor T11' receives the upper stage transfer signal ST(NX). One of the source and drain of transistor T11' receives the upper stage scan signal G(NX). The other of the source and drain of transistor T11' is connected to the second-type pull-up node Q2.

[0098] The second-type output unit 2232 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second-type output unit 2232 is connected to the output terminal of the input unit 2231. The second input terminal 2232 of the second-type output unit 2232 is connected to the clock signal line 27 to receive the clock signal CK transmitted by the clock signal line 27. The output terminal of the second-type output unit 2232 is connected to a scan signal line 24.

[0099] Specifically, the second-type output unit 2232 includes a transistor T21'. The gate of the transistor T21' is connected to the second-type pull-up node Q2. One of the source and drain of the transistor T21' is connected to the clock signal line 27 to receive the clock signal CK. The other of the source and drain of the transistor T21' is connected to a scan signal line 24.

[0100] The reset unit 2233 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the reset unit 2233 is connected to the reset signal line 26. The second input terminal of the reset unit 2233 is connected to the constant voltage signal line 28 to receive the constant voltage signal VSS. The output terminal of the reset unit 2233 is connected to the second-type pull-up node Q2. With this configuration, the reset unit 2233 can reset the potential of the second-type pull-up node Q2 to the constant voltage signal VSS during the reset period.

[0101] Specifically, the reset unit 2233 includes a transistor T71'. The gate of the transistor T71' is connected to the reset signal line 26 to receive the reset signal Reset. One of the source and drain of the transistor T71' receives the constant voltage signal VSS. The other of the source and drain of the transistor T71' is connected to the second-type pull-up node Q2.

[0102] The first input terminal of the second-type transmission unit 2234 is connected to the second-type pull-up node Q2. The second input terminal of the second-type transmission unit 2234 is connected to the clock signal line 27 to receive the clock signal CK. The output terminal of the second-type transmission unit 2234 outputs the transmission signal of the current stage (e.g., ST(N)).

[0103] Specifically, the second-type stage transfer unit 2234 includes a transistor T22'. The gate of the transistor T22' is connected to the second-type pull-up node Q2. One of the source and drain of the transistor T22' is connected to the clock signal line 27 to receive the clock signal CK. The other of the source and drain of the transistor T22' outputs the stage transfer signal.

[0104] In addition, for the connection relationship between the transistor T51', the transistor T52', the transistor T53', the transistor T54', the transistor T61', the transistor T62', the transistor T63', the transistor T64', the transistor T31', the transistor T32', the transistor T33', the transistor T41', the transistor T42', the transistor T43' and the second type of bootstrap capacitor C' in Figure 4, reference can be made to the connection relationship of the relevant structures in the above-mentioned first type gate driving unit 222, which will not be repeated here.

[0105] 5 , which is a partially enlarged schematic diagram of a non-display area in some embodiments of the present application.

[0106] The display panel 200 further includes a first connection line 31 and a constant voltage signal line 28 located in the non-display area 200b. The first connection line 31 is connected between the constant voltage signal line 28 and the redundant reset unit 2223 and includes a first break 311. The first connection line 31 is disconnected at the location of the first break 311. Thus, the constant voltage signal line 28 is disconnected from the redundant reset unit 2223.

[0107] In some embodiments, the first fracture 311 can be formed by processing the first connecting line 31 through a laser ablation process.

[0108] The display panel 200 also includes a second connecting line 32 located in the non-display area 200b. The second connecting line 32 is connected between the clock signal line 27 and the first-type output unit 2222 and includes a second break 321. The second connecting line 32 is disconnected at the location of the second break 321. Thus, the clock signal line 27 is disconnected from the second input terminal of the first-type output unit 2222.

[0109] In some embodiments, the second connection line 32 is further connected to the first-type stage transmission unit 2226, and the second break 321 is configured to disconnect the first-type stage transmission unit 2226 from the clock signal line 27. Therefore, the design of the second break 321 can simultaneously disconnect the first-type output unit 2222 and the first-type stage transmission unit 2226 from the clock signal line 27.

[0110] In some embodiments, the second break 321 is formed by laser ablation of the second connecting line 32. The second break 321 is spaced apart from the first break 311.

[0111] In some embodiments, the second connection line 32 is connected to the reset signal line 26 through the first via V1. The second connection line 32 connects the first-type output unit 2222 and the reset signal line 26. The first via V1 is spaced apart from the second break 321. In this configuration, the second connection line 32 connects the second input terminal of the first-type output unit 2222 and the reset signal line 26, and also connects the second input terminal of the first-type stage transfer unit 2226 and the reset signal line 26.

[0112] In some embodiments, the display panel 200 further includes a third connection line 33 . The third connection line 33 connects the first input terminal of the first type output unit 2222 and the reset signal line 26 .

[0113] In some embodiments, the second connection lines 32 , the first connection lines 31 , and the third connection lines 33 are located in the same conductive layer and are spaced apart from each other.

[0114] In some embodiments, as shown in FIG6 , the display panel 200 includes a substrate 41, an insulating layer 42, a first conductive layer 43, and a second conductive layer 44. The insulating layer 42, the first conductive layer 43, and the second conductive layer 44 are all disposed on the substrate 41. The first conductive layer 43 is disposed on the substrate 41. The insulating layer 42 is located on a side of the first conductive layer 43 away from the substrate 41. The second conductive layer 44 is located on a side of the insulating layer 42 away from the first conductive layer 43.

[0115] Specifically, a first conductive layer 43 is disposed on the substrate 41. The first conductive layer 43 is a gate metal layer, that is, the first conductive layer 43 includes a gate. The first conductive layer 43 also includes a reset signal line 26. A second conductive layer 44 is disposed on a side of the first conductive layer 43 away from the substrate 41. The second conductive layer 44 is a source / drain metal layer and includes source / drain electrodes, a first connecting line 31, a second connecting line 32, and a third connecting line 33. An insulating layer 42 is disposed between the first conductive layer 43 and the second conductive layer 44. The insulating layer 42 may include an interlayer insulating layer. The insulating layer 42 includes a first via V1 and a second via V2 spaced apart. The orthographic projections of the first via V1 and the second via V2 on the substrate 41 overlap with the orthographic projections of the reset signal line 26 on the substrate 41. This arrangement allows the second connecting line 32 to be connected to the reset signal line 26 through the first via V1, thereby connecting the reset signal line 26 to the first input terminal of the first-type output unit 2222. At the same time, the third connection line 33 is connected to the reset signal line 26 through the second via hole V2 on the insulating layer 42 , thereby connecting the first input terminal of the first type output unit 2222 and the reset signal line 26 .

[0116] In some embodiments, when the second conductive layer 44 includes the first connecting line 31 and the second connecting line 32, the first break 311 and the second break 321 are staggered relative to the conductive portion of the first conductive layer 43. This alleviates the problem of shorting between the second connecting line 32 and the conductive layer below the second break 321, and between the first connecting line 31 and the conductive layer below the first break 311, when laser ablation is performed on the first connecting line 31 and the second connecting line 32 to form the first break 311 and the second break 321, respectively.

[0117] The description of the above embodiments is only used to help understand the technical solutions and core ideas of this application; ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, wherein: include: Reset signal line; Clock signal line; Multiple scanning signal lines; A plurality of cascaded gate driving units include a first type of gate driving unit, wherein the first type of gate driving unit includes: A redundant input unit, comprising a first input terminal, a second input terminal and an output terminal, wherein the first input terminal and the second input terminal of the redundant input unit are in a floating state; A first type of output unit, having a first input end, a second input end and an output end, wherein the first input end of the first type of output unit is connected to the output end of the redundant input unit and the reset signal line, the second input end of the first type of output unit is connected to the reset signal line and is disconnected from the clock signal line, and the output end of the first type of output unit is connected to one of the scan signal lines; a second connecting line connected between the clock signal line and the first type output unit and comprising a second break; and The start signal line is disconnected from the first type of gate driving unit.

2. The display panel according to claim 1, wherein: The plurality of cascaded gate driving units further include a second type of gate driving unit, and the second type of gate driving unit includes: An input unit, used for outputting a driving signal; The second type of output unit has a first input end, a second input end and an output end, the first input end of the second type of output unit is connected to the output end of the input unit, the second input end of the second type of output unit is connected to the clock signal line, and the output end of the second type of output unit is connected to one of the scanning signal lines.

3. The display panel according to claim 2, wherein: The display panel also includes a constant voltage signal line; The first type of gate driving unit further includes: a redundant reset unit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the redundant reset unit is connected to the reset signal line, the output terminal of the redundant reset unit is connected to the output terminal of the redundant input unit and the first input terminal of the first type of output unit, and the second input terminal of the redundant reset unit is disconnected from the constant voltage signal line; The second type of gate driving unit also includes: a reset unit having a first input terminal, a second input terminal and an output terminal, the first input terminal of the reset unit is connected to the reset signal line, the second input terminal of the reset unit is connected to the constant voltage signal line, and the output terminal of the reset unit is connected to the first input terminal of the second type of output unit and the output terminal of the input unit.

4. The display panel according to claim 3, wherein: The display panel further includes: The first connecting line is connected between the constant voltage signal line and the redundant reset unit and includes a first break.

5. The display panel according to claim 1, wherein: The second connection line is connected to the reset signal line through a first via hole, and the second connection line connects the first type output unit and the reset signal line, and the first via hole and the second break are spaced apart.

6. The display panel according to claim 5, wherein: The display panel further includes: substrate; A first conductive layer, disposed on the substrate and including the reset signal line; a second conductive layer, disposed on a side of the first conductive layer away from the substrate, and comprising the second connecting line, wherein the second fracture is staggered with a conductive portion of the first conductive layer; The insulating layer is disposed between the first conductive layer and the second conductive layer and includes the first via hole, wherein an orthographic projection of the first via hole on the substrate overlaps with an orthographic projection of the reset signal line on the substrate.

7. The display panel according to claim 6, wherein: The second conductive layer further comprises: A third connecting line connects the first input end of the first type output unit and the reset signal line, and is connected to the reset signal line through a second via hole on the insulating layer, and the second via hole is spaced apart from the first via hole.

8. The display panel according to claim 2, wherein: The display panel further includes: Multiple data lines; A source driving circuit connected to the plurality of data lines and disposed on one side of the display panel; Wherein, the first type of gate driving unit is located at a side of the second type of gate driving unit away from the source driving circuit.

9. A display panel, wherein: include: Reset signal line; Clock signal line; Multiple scanning signal lines; as well as A plurality of cascaded gate driving units include a first type of gate driving unit, wherein the first type of gate driving unit includes: A redundant input unit, comprising a first input terminal, a second input terminal and an output terminal, wherein the first input terminal and the second input terminal of the redundant input unit are in a floating state; The first type of output unit has a first input end, a second input end and an output end, the first input end of the first type of output unit is connected to the output end of the redundant input unit and the reset signal line, the second input end of the first type of output unit is connected to the reset signal line and disconnected from the clock signal line, and the output end of the first type of output unit is connected to one of the scan signal lines.

10. The display panel according to claim 9, wherein: The plurality of cascaded gate driving units further include a second type of gate driving unit, and the second type of gate driving unit includes: An input unit, used for outputting a driving signal; The second type of output unit has a first input end, a second input end and an output end, the first input end of the second type of output unit is connected to the output end of the input unit, the second input end of the second type of output unit is connected to the clock signal line, and the output end of the second type of output unit is connected to one of the scanning signal lines.

11. The display panel according to claim 10, wherein: The display panel also includes a constant voltage signal line; The first type of gate driving unit further includes: a redundant reset unit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the redundant reset unit is connected to the reset signal line, the output terminal of the redundant reset unit is connected to the output terminal of the redundant input unit and the first input terminal of the first type of output unit, and the second input terminal of the redundant reset unit is disconnected from the constant voltage signal line; The second type of gate driving unit also includes: a reset unit having a first input terminal, a second input terminal and an output terminal, the first input terminal of the reset unit is connected to the reset signal line, the second input terminal of the reset unit is connected to the constant voltage signal line, and the output terminal of the reset unit is connected to the first input terminal of the second type of output unit and the output terminal of the input unit.

12. The display panel according to claim 11, wherein: The display panel further includes: The first connecting line is connected between the constant voltage signal line and the redundant reset unit and includes a first break.

13. The display panel according to claim 9, wherein: The display panel further includes: The second connecting line is connected between the clock signal line and the first type output unit and includes a second break.

14. The display panel according to claim 13, wherein: The second connection line is connected to the reset signal line through a first via hole, and the second connection line connects the first type output unit and the reset signal line, and the first via hole and the second break are spaced apart.

15. The display panel according to claim 14, wherein: The display panel further includes: substrate; A first conductive layer, disposed on the substrate and including the reset signal line; a second conductive layer, disposed on a side of the first conductive layer away from the substrate, and comprising the second connecting line, wherein the second fracture is staggered with a conductive portion of the first conductive layer; The insulating layer is disposed between the first conductive layer and the second conductive layer and includes the first via hole, wherein an orthographic projection of the first via hole on the substrate overlaps with an orthographic projection of the reset signal line on the substrate.

16. The display panel according to claim 15, wherein: The second conductive layer further comprises: A third connecting line connects the first input end of the first type output unit and the reset signal line, and is connected to the reset signal line through a second via hole on the insulating layer, and the second via hole is spaced apart from the first via hole.

17. The display panel according to claim 10, wherein: The display panel further includes: Multiple data lines; A source driving circuit connected to the plurality of data lines and disposed on one side of the display panel; Wherein, the first type of gate driving unit is located at a side of the second type of gate driving unit away from the source driving circuit.

18. The display panel according to claim 9, wherein: The display panel further includes: The start signal line is disconnected from the first type of gate driving unit.

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