Gate driving circuit and display apparatus

Abstract

The present disclosure belongs to the technical field of display and provides a gate driving circuit and a display apparatus. The gate driving circuit of the present disclosure comprises a plurality of cascaded shift registers and two groups of clock signal lines, each group of clock signal lines comprising 2N clock signal lines. The plurality of cascaded shift registers are divided into a plurality of groups of shift registers, each group of shift registers comprising 2N shift registers. The shift registers of the odd-number groups are connected to the same group of clock signal lines, and the shift registers of the even-number groups are connected to the same group of clock signal lines, the shift registers of the odd-number groups and those of the even-number groups being connected to different groups of clock signal lines, and N being an integer greater than or equal to 1. Each shift register at least comprises an input sub-circuit, an output sub-circuit, at least one pull-down control sub-circuit and at least one pull-down sub-circuit. In each group of shift registers, the pull-down control sub-circuit is shared and the pull-down sub-circuit is shared.

Description

Gate drive circuit and display device Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a gate driving circuit and a display device. Background Art

[0002] With the continuous development of display technology, the development of displays in recent years has gradually shown a trend of high integration and low cost. One of the very important technologies is the mass production of GOA (Gate Driver on Array) technology. GOA technology is used to integrate the TFT (Thin Film Transistor) gate switch circuit on the array substrate of the display panel to form a scan drive for the display panel, thereby eliminating the gate driver integrated circuit part. This not only reduces product costs in terms of material costs and manufacturing processes, but also allows the display panel to achieve a beautiful design with symmetry on both sides and narrow borders. At the same time, since the gate direction bonding process can be eliminated, it is also beneficial to improve production capacity and yield. This gate switch circuit integrated on the array substrate using GOA technology is also called a GOA circuit or a shift register circuit.

[0003] Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art and provides a gate drive circuit and a display device.

[0005] An embodiment of the present disclosure provides a gate drive circuit, comprising a plurality of cascaded shift registers and two groups of clock signal lines, each group of clock signal lines comprising 2N clock signal lines; the plurality of cascaded shift registers are divided into a plurality of groups of shift registers, each group of shift registers comprising 2N shift registers; the shift registers in the odd group are connected to the same group of clock signal lines, the shift registers in the even group are connected to the same group of clock signal lines, and the shift registers in the odd group and the even group are connected to different groups of clock signal lines; N is an integer greater than or equal to 1; wherein the shift registers comprise at least an input subcircuit, an output subcircuit, at least one pull-down control subcircuit, and at least one pull-down subcircuit;

[0006] the input subcircuit configured to precharge the pull-up node by the input signal in response to the input signal at the signal input terminal; a connection node between the input subcircuit, the output subcircuit, and the pull-down subcircuit;

[0007] The output sub-circuit is configured to output the clock signal through the signal output terminal in response to the potential of the pull-up node;

[0008] The pull-down control subcircuit is configured to respond to a power supply voltage and control the potential of the pull-down node through the power supply voltage; one pull-down control subcircuit is connected to one pull-down subcircuit and another pull-down subcircuit, and a connection node between the two is the pull-down node;

[0009] The pull-down sub-circuit is configured to pull down the potential of the pull-down node through a non-working level signal in response to the potential of the pull-up node; wherein,

[0010] The pull-down control sub-circuit in each group of the shift registers is shared, and the pull-down sub-circuit is shared.

[0011] Wherein, the shift register further includes: a first reset subcircuit and a second reset subcircuit;

[0012] The first reset sub-circuit is configured to reset the pull-up node via the non-working level signal in response to a reset signal;

[0013] The second reset sub-circuit is configured to reset the output of the signal output terminal through the non-working level signal in response to the reset signal.

[0014] Wherein, for one of the shift registers, the first reset sub-circuit includes a second transistor, and the second reset sub-circuit includes a fourth transistor;

[0015] The first electrode of the second transistor is connected to the non-working level signal terminal, the second electrode is connected to the pull-up node, and the control electrode is connected to the reset signal terminal;

[0016] The first electrode of the fourth transistor is connected to the non-working level signal terminal, the second electrode is connected to the signal output terminal, and the control electrode is connected to the reset signal terminal.

[0017] For the shift registers in the same group, the control electrodes of the second transistors and the control electrodes of the fourth transistors are connected to the same reset signal terminal.

[0018] The shift register further includes at least one first noise reduction sub-circuit and at least one second noise reduction sub-circuit; the first noise reduction sub-circuit and the second noise reduction sub-circuit are both connected to the pull-down nodes in a one-to-one correspondence;

[0019] The first noise reduction sub-circuit is configured to reduce the potential of the pull-up node by a non-working level signal in response to the potential of the pull-down node connected thereto;

[0020] The second noise reduction sub-circuit is configured to reduce the noise of the output of the signal output terminal through a non-working level signal in response to the potential of the pull-down node connected thereto.

[0021] Wherein, for one of the shift registers, the first noise reduction sub-circuit includes a tenth transistor, and the second noise reduction sub-circuit includes an eleventh transistor;

[0022] The first electrode of the tenth transistor is connected to the non-working level signal terminal, the second electrode is connected to the pull-up node, and the control electrode is connected to the pull-down node;

[0023] The first electrode of the eleventh transistor is connected to the non-working level signal terminal, the second electrode is connected to the signal output terminal, and the control electrode is connected to the pull-down node.

[0024] The shift register further includes a discharge sub-circuit configured to respond to a pre-frame start signal and discharge the pull-up node through a non-working level signal.

[0025] Wherein, for one of the shift registers, the discharge subcircuit includes a seventh transistor;

[0026] The first electrode of the seventh transistor is connected to the non-working level signal terminal, the second electrode is connected to the pull-up node, and the control electrode is connected to the pre-frame start signal terminal.

[0027] Wherein, the shift register further includes at least one auxiliary subcircuit, and the auxiliary subcircuit is connected to the pull-down node in a one-to-one correspondence;

[0028] The auxiliary sub-circuit is configured to pull down the pull-down node via the non-working level signal in response to the input signal.

[0029] The auxiliary sub-circuits of the shift registers in the same group are shared.

[0030] Wherein, the auxiliary sub-circuit includes a sixteenth transistor;

[0031] The first electrode of the sixteenth transistor is connected to the non-working level signal terminal, the second electrode is connected to the corresponding pull-down node, and the control electrode is connected to the signal input terminal.

[0032] Wherein, for one of the shift registers, the input subcircuit includes a first transistor, a first electrode and a control electrode of the first transistor are both connected to the signal input terminal, and a second electrode is connected to the pull-up node; or,

[0033] The first electrode of the first transistor is connected to the precharge source signal terminal, the second electrode is connected to the pull-up node, and the control electrode is connected to the signal input terminal.

[0034] Wherein, for one of the shift registers, the output sub-circuit includes a third transistor, a fifteenth transistor and a storage capacitor;

[0035] The first electrode of the third transistor is connected to the clock signal terminal, the second electrode is connected to the signal output terminal and the second terminal of the storage capacitor, and the control electrode is connected to the first terminal of the storage capacitor;

[0036] The first electrode of the fifteenth transistor is connected to the clock signal terminal, the second electrode is connected to the cascade signal output terminal, and the control electrode is connected to the first terminal of the storage capacitor;

[0037] For a group of the shift registers, the clock signal lines connected to the shift registers are in the same group, and different shift registers are connected to different clock signal lines.

[0038] The shift register further includes at least one third noise reduction sub-circuit, and the third noise reduction sub-circuit is connected to the pull-down node in a one-to-one correspondence;

[0039] The third noise reduction sub-circuit is configured to perform noise reduction on the output of the cascade signal output terminal through the non-working level signal in response to the potential of the pull-down node connected thereto.

[0040] Wherein, the third noise reduction sub-circuit includes a seventeenth transistor;

[0041] The first electrode of the seventeenth transistor is connected to the non-working level signal terminal, the second electrode is connected to the cascade signal output terminal, and the control electrode is connected to the pull-down node.

[0042] Wherein, the pull-down control subcircuit includes a fifth transistor and a ninth transistor;

[0043] The first electrode of the fifth transistor is connected to the power supply voltage terminal, the second electrode is connected to the corresponding pull-down node, and the control electrode is connected to the second electrode of the ninth transistor;

[0044] The first electrode and the control electrode of the ninth transistor are both connected to the power supply voltage terminal;

[0045] The first electrodes of the fifth transistors in a group of the shift registers are connected to different power supply voltage terminals.

[0046] Wherein, for one of the shift registers, the pull-down sub-circuit includes a sixth transistor and an eighth transistor;

[0047] The first electrode of the sixth transistor is connected to the non-working level signal terminal, the second electrode is connected to the corresponding pull-down node, and the control electrode is connected to the pull-up node;

[0048] The first electrode of the eighth transistor is connected to the non-working level signal terminal, the second electrode is connected to the control electrode of the fifth transistor and the second electrode of the ninth transistor in the corresponding pull-down control subcircuit, and the control electrode is connected to the pull-up node.

[0049] Wherein, the N is 4.

[0050] The signal input terminal of the i-th shift register is connected to the cascade signal output terminal of the i-2-th shift register; i is an integer greater than or equal to 3;

[0051] The reset signal end of each shift register in the jth group is connected to the signal output end or the cascade signal output end of the fourth shift register in the j+1th group; j is an integer greater than or equal to 1.

[0052] An embodiment of the present disclosure further provides a display device, which includes any of the above-mentioned gate driving circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] FIG1 is a circuit diagram of an exemplary shift register.

[0054] FIG2 is a circuit diagram of another exemplary shift register.

[0055] FIG3 is a circuit diagram of another exemplary shift register.

[0056] FIG4 is a circuit diagram of a group of shift registers of the gate driving circuit according to an embodiment of the present disclosure.

[0057] FIG5 is a partial schematic diagram of the cascade connection of the gate driving circuit according to an embodiment of the present disclosure.

[0058] FIG6 is a timing diagram of the gate driving circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0059] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0060] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0061] It should be noted that the transistors used in the embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present invention, in order to distinguish the source and drain of the transistor, one of the poles is called the first pole, the other pole is called the second pole, and the gate is called the control pole. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. The following embodiments are explained with N-type transistors. When an N-type transistor is used, the first pole is the source of the N-type transistor, and the second pole is the drain of the N-type transistor. When the gate input is a high level, the source and drain are turned on, and the P-type is the opposite. It can be imagined that the use of P-type transistors is something that a person skilled in the art can easily think of without creative work, and therefore it is also within the scope of protection of the embodiments of the present invention.

[0062] Among them, since the transistor used in the embodiment of the present invention is an N-type transistor, the working level signal in the embodiment of the present invention refers to a high level signal, and the non-working level signal is a low level signal; the corresponding working level end is a high level signal end, and the non-working level end is a low level signal end.

[0063] Typically, a display panel includes multiple gate lines and multiple data lines. The gate lines and data lines intersect to define multiple pixel regions, each of which is provided with pixel cells. The structure of the display panel is described below using the example of the direction in which each gate line extends as a row direction and the direction in which each data line extends as a column direction. When the display panel is driven to display, gate scan signals are written to the gate lines row by row, and data voltage signals are written to the data lines simultaneously, so that the pixel cells in the display panel are illuminated row by row, depending on the image to be displayed.

[0064] Among them, the gate scan signal is provided by the gate drive circuit, and the data voltage signal is provided by the source drive circuit; in the related technology, the gate drive circuit can be integrated into the gate drive chip, and the source drive circuit can be integrated into the source drive chip; and currently, in order to reduce the number of chips and achieve a narrow frame or no frame, a technology for integrating the gate drive circuit on an array substrate (Gate On Array; GOA) is provided; wherein, the gate drive circuit includes a plurality of cascaded shift registers integrated on the array substrate, each shift register is connected to a gate line one-to-one, and is used to provide a gate scan signal to the gate line connected thereto.

[0065] In order to make it clearer how the shift register unit realizes the output of the gate scanning signal, a specific example of the shift register unit is used for explanation below.

[0066] In one example, Figure 1 is a circuit diagram of a shift register; as shown in Figure 1, the shift register includes an input sub-circuit 1, an output sub-circuit 2, a first reset sub-circuit 3, and a second reset sub-circuit 4; wherein, the input sub-circuit 1 responds to the input signal input by the signal input terminal INPUT, and charges the pull-up node PU through the input signal; the output sub-circuit 2 responds to the potential of the pull-up node PU, and outputs the clock signal input by the clock signal terminal through the signal output terminal OUTPUT; the first reset sub-circuit 3 responds to the first reset signal output by the first reset signal terminal Reset_PU, and resets the pull-up node PU through a low-level signal; the second reset sub-circuit responds to the output of the second reset signal Reset_Output, and resets the signal output terminal Output through a low-level signal.

[0067] Specifically, continuing to refer to Figure 1, the output sub-circuit 2 includes a first transistor M1; the first reset sub-circuit 3 includes a second transistor M2; the output sub-circuit 2 includes a third transistor M3 and a storage capacitor C; the second reset sub-circuit 4 includes a fourth transistor M4; wherein, the gate and source of M1 are connected to the signal input terminal Input, and the drain of M1 is connected to the pull-up node PU; the gate of M2 is connected to the first reset signal terminal Reset_PU, the source of M2 is connected to the pull-up node PU, and the drain of M2 is connected to the low-level signal terminal; the gate of M3 is connected to the pull-up node PU, the source of M3 is connected to the clock signal terminal, and the drain of M3 is connected to the signal output terminal Output; the first end of C is connected to the pull-up node PU, and the second end of C is connected to the signal output terminal Output; the gate of M4 is connected to the output to the second reset signal terminal Reset_Output, the source of M4 is connected to the signal output terminal Output, and the drain of M4 is connected to the low-level signal terminal.

[0068] In the input stage, a high-level signal is written to the signal input terminal INPUT, M1 is turned on, the PU point is pulled high by the high-level signal, and C is charged.

[0069] In the output stage, since the PU point is pulled high in the input stage, M3 is turned on, and the high-level signal input from the clock signal end is output to the gate line connected to the shift register unit through the signal output end Output.

[0070] In the reset stage, a high-level signal is input to the second reset signal terminal Reset_Output, M4 is turned on, and the output of the signal output terminal Output is pulled low by the low-level signal input to the low-level signal terminal; a high-level signal is input to the first reset signal terminal Reset_PU, M2 is turned on, and the low-level signal input to the low-level signal terminal pulls down the potential of the pull-up node PU, thereby completing the reset of the pull-up node PU and the signal output terminal Output.

[0071] It should be noted that the second reset subcircuit 4 may not be provided in the shift register unit. In the reset phase, after the pull-up node PU is reset, the pull-up node PU is at a low level, M3 is turned off, and the signal output terminal Output no longer outputs, thereby resetting the signal output terminal Output. Of course, the first reset subcircuit and the second reset subcircuit may also be controlled by the same reset signal, that is, the first reset signal terminal and the second reset signal terminal are connected together.

[0072] In another example, FIG2 is a circuit diagram of another shift register according to an embodiment of the present disclosure. As shown in FIG2 , the shift register includes not only the input sub-circuit 1, output sub-circuit 2, and pull-up reset sub-circuit 3 described above, but also includes two pull-down control sub-circuits 5 / 5', two pull-down sub-circuits 6 / 6', two first noise reduction sub-circuits 7 / 7', two second noise reduction sub-circuits 8 / 8', two third noise reduction sub-circuits 9 / 9', two auxiliary sub-circuits 11 / 11', and a discharge sub-circuit 10 / 10'. The pull-down control sub-circuit 5 is connected to a corresponding pull-down sub-circuit 6, with the connection node between the two being the first pull-down node PD1. The pull-down control sub-circuit 5' is connected to a corresponding pull-down sub-circuit 6', with the connection node between the two being the first pull-down node PD2. The first pull-down node PD1 connects a first noise reduction sub-circuit 7, a second noise reduction sub-circuit 8, and a third noise reduction sub-circuit 9. The second pull-down node PD2 connects another first noise reduction sub-circuit 7', another second noise reduction sub-circuit 8', and another third noise reduction sub-circuit 9'. The two pull-down control sub-circuits 5 / 5' in the shift register have identical structures and functions, except that when the shift register is operating, the two pull-down control sub-circuits 5 / 5' operate in time-sharing mode. That is, the timing of the control signals controlling the two pull-down control sub-circuits 5 / 5' is opposite. Similarly, the two pull-down sub-circuits 6 / 6' have identical structures and functions and operate in time-sharing mode; the two first noise reduction sub-circuits 7 / 7' have identical structures and functions and operate in time-sharing mode; the two second noise reduction sub-circuits 8 / 8' have identical structures and functions and operate in time-sharing mode; and the two third noise reduction sub-circuits 9 / 9' have identical structures and functions and operate in time-sharing mode. The input sub-circuit 1 , the output sub-circuit 2 , the first reset sub-circuit 3 and the second reset sub-circuit 4 have the same structures and functions as described above, and therefore are not described again herein.

[0073] The discharge subcircuit 10 responds to a pre-frame start signal inputted from the pre-frame start signal terminal Trst and discharges the pull-up node PU via a low-level signal inputted from the low-level signal terminal. One pull-down control subcircuit 5 controls the potential of the first pull-down node PD1 under the control of the first power supply voltage VDDO, while another pull-down control subcircuit 5' controls the potential of the second pull-down node PD2 under the control of the second power supply voltage VDDE. One pull-down subcircuit 6 pulls down the potential of the first pull-down node PD1 in response to the potential of the pull-up node PU, while another pull-down subcircuit 6' pulls down the potential of the second pull-down node PD2 in response to the potential of the pull-up node PU. One first noise reduction subcircuit 7 reduces the potential of the pull-up node PU in response to the potential of the first pull-down node PD1, while another first noise reduction subcircuit 7' reduces the potential of the pull-up node PU in response to the potential of the second pull-down node PD2. One of the second noise reduction sub-circuits 8 performs noise reduction on the output of the signal output terminal "Output" in response to the potential of the first pull-down node PD1, while another second noise reduction sub-circuit 8' performs noise reduction on the output of the signal output terminal "Out" in response to the potential of the second pull-down node PD2. One of the third noise reduction sub-circuits 9 performs noise reduction on the output of the cascade signal output terminal "Out_C" in response to the potential of the first pull-down node PD1, while another third noise reduction sub-circuit 9' performs noise reduction on the output of the cascade signal output terminal "Out_C" in response to the potential of the second pull-down node PD2. The cascade sub-circuit 12 transmits the clock signal "CLK" through the cascade signal output terminal "Out_C" in response to the potential of the pull-up node PU.

[0074] Specifically, continuing with reference to Figure 2 , each pull-down control sub-circuit includes a fifth transistor and a ninth transistor; the fifth transistor in the two pull-down control sub-circuits 5 / 5' is represented by M5 and M5', respectively, and the ninth transistor is represented by M9 and M9', respectively. Each pull-down sub-circuit includes a sixth transistor and an eighth transistor; the sixth transistor in the two pull-down sub-circuits 6 / 6' is represented by M6 and M6', respectively, and the eighth transistor is represented by M8 and M8', respectively. Each first noise reduction sub-circuit includes a tenth transistor; the tenth transistor in the two first noise reduction sub-circuits 7 / 7' is represented by M10 and M10', respectively. Each second noise reduction sub-circuit includes an eleventh transistor; the eleventh transistor in the two second noise reduction sub-circuits 8 / 8' is represented by M11 and M11', respectively. Each third noise reduction sub-circuit includes a seventeenth transistor; the seventeenth transistor in the two third noise reduction sub-circuits 9 / 9' is represented by M17 and M17', respectively. Each auxiliary subcircuit comprises a sixteenth transistor; the sixteenth transistors in the two auxiliary subcircuits 11 / 11' are denoted by M16 and M16', respectively. The discharge subcircuit 10 comprises a seventh transistor M7. The cascade subcircuit comprises a fifteenth transistor M15.

[0075] Continuing with reference to Figure 3, the gate and source of M1 are connected to the signal input terminal INPUT, and the drain of M1 is connected to the pull-up node PUPU; the gate of M2 is connected to the first reset signal terminal RESET_PU, the source of M2 is connected to the pull-up node PU, and the drain of M2 is connected to the low-level signal terminal; the gate of M3 is connected to the pull-up node PU, the source of M3 is connected to the clock signal terminal, and the drain of M3 is connected to the signal output terminal OUTPUT; the first end of C is connected to the pull-up node PU, and the second end of C is connected to the signal output terminal OUTPUT; the gate and source of M5 are both connected to the first power supply voltage terminal, and the drain of M5 is connected to the first pull-down control node PD_CN1; the gate of M9 is connected to the first pull-down control node PD_CN1, and the source of M9 is connected to the first pull-down control node PD_CN1. The first power supply voltage terminal is connected, and the drain of M9 is connected to the first pull-down node PD1; the gate and source of M5' are both connected to the second power supply voltage terminal, and the drain of M5' is connected to the second pull-down control node PD_CN2; the gate of M9' is connected to the second pull-down control node PD_CN2, the source of M9' is connected to the second power supply voltage terminal, and the drain of M9' is connected to the first pull-down node PD1; the gate of M6 is connected to the pull-up node PU, the source of M6 is connected to the first pull-down node PD1, and the drain of M6 is connected to the low-level signal terminal; the gate of M8 is connected to the pull-up node PU, the source of M8 is connected to the first pull-down control node PD_CN1, and the drain of M8 is connected to the low-level signal terminal; the gate of M6' is connected to the pull-up node PU, and the source of M6' is connected to the first pull-down control node PD_CN1. The second pull-down node PD2 is connected, the drain of M6' is connected to the low-level signal terminal; the gate of M8' is connected to the pull-up node PU, the source of M8' is connected to the second pull-down control node PD_CN2, and the drain of M8' is connected to the low-level signal terminal; the gate of M10 is connected to the first pull-down node PD1, the source of M10 is connected to the pull-up node PU, and the drain of M10 is connected to the low-level signal terminal; the gate of M11 is connected to the first pull-down node PD1, the source of M11 is connected to the signal output terminal OUTPUT, and the drain of M11 is connected to the low-level signal terminal; the gate of M17 is connected to the first pull-down node PD1, the source of M17 is connected to the cascade signal output terminal OUT_C, and the drain of M17 is connected to the low-level signal terminal; the gate of M10' Connected to the second pull-down node PD2, the source of M10' is connected to the pull-up node PU, and the drain of M10' is connected to the low-level signal end; the gate of M11' is connected to the second pull-down node PD2, the source of M11' is connected to the signal output end OUTPUT, and the drain of M11' is connected to the low-level signal end; the gate of M12' is connected to the second pull-down node PD2, the source of M12' is connected to the cascade signal output end OUT_C, and the drain of M12' is connected to the low-level signal end; the gate of M7 is connected to the pre-frame start signal end, the source of M7 is connected to the pull-up node PU, and the drain of M7 is connected to the low-level signal end; the gate of M15 is connected to the pull-up node PU, the source of M15 is connected to the clock signal end, and the drain of M15 is connected to the cascade signal end.The gate of M16 is connected to the signal input terminal INPUT, the source of M16 is connected to the first pull-down node PD1, and the drain of M16 is connected to the low-level signal terminal. The gate of M16' is connected to the signal input terminal INPUT, the source of M16' is connected to the second pull-down node PD2, and the drain of M16' is connected to the low-level signal terminal.

[0076] M5 and M9 form one pull-down control subcircuit, and M5' and M9' form another pull-down control subcircuit. The two pull-down control subcircuits operate in a 5 / 5' time-sharing manner (i.e., they take turns operating). Accordingly, since the first, second, and third noise reduction subcircuits (composed of M10, M11, and M17) are all controlled by the first pull-down node PD1, and the first, second, and third noise reduction subcircuits (composed of M10', M11', and M17') are all controlled by the second pull-down node PD2, when the pull-down control subcircuits operate in a time-sharing manner, the first, second, and third noise reduction subcircuits also operate in a time-sharing manner. The following describes the operating principle of the shift register, taking only one operating cycle as an example.

[0077] In the discharge stage, before the frame, that is, before display, a high-level signal is first input to the pre-frame start signal terminal TRST, and the pull-up node PU is discharged through the low-level signal input by the low-level signal terminal to prevent residual charge on the pull-up node PU from causing display abnormalities.

[0078] In the input stage, a high-level signal is input to the signal input terminal Input, M1 is turned on, the pull-up node PU is pulled high by the high-level signal, and C is charged. At the same time, M16 and M16' are both turned on, pulling down the first pull-down node PD1 and the second pull-down node PD2 to avoid affecting the potential of the pull-up node PU.

[0079] In the output stage, since the pull-up node PU is pulled high in the input stage, M3 and M13 are turned on, and the high-level signal input from the clock signal end is output to the gate line connected thereto through the signal output end Output. At the same time, the cascade signal output end Out_C is the same as the signal output by the signal output end Output, that is, a high-level signal is output to the pull-up reset signal end RESET_PU of the previous-level shift register unit and the signal input end Input of the next-level shift register unit.

[0080] During the reset phase, a high-level signal is input to the first reset signal terminal RESET_PU. M2 is turned on, and the low-level signal input through the low-level signal terminal pulls down the potential of the pull-up node PU to reset the pull-up node PU. Since the pull-up node PU is pulled low, M3 and M13 are turned off, and the signal output terminal Output and the cascade signal output terminal Out_C no longer output high-level signals. At the same time, the pull-down control node PD_CN1 and the first pull-down node PD1 are both high-level signals. M10, M11, and M17 are turned on, respectively, to reduce noise on the outputs of the pull-up node PU, the signal output terminal Output, and the cascade signal output terminal Out_C, until the pull-up node PU potential is pulled high at the start of the next frame scan.

[0081] The inventors discovered that the shift register shown in FIG2 , consisting of 21 transistors and one storage capacitor (21T1C), is relatively large, making it difficult to achieve a narrow-frame design for a display panel. To address this issue, in one example, the auxiliary subcircuit and discharge subcircuit 10 can be omitted, while a second reset subcircuit for the signal output terminal (Output) is added. As shown in FIG3 , the shift register includes 19 transistors and one storage capacitor (19T1C), but the size of the shift register is still relatively large. Therefore, embodiments of the present disclosure provide a gate drive circuit that can achieve a narrow-frame design.

[0082] The gate drive circuit in the embodiment of the present disclosure includes multiple cascaded shift registers and two groups of clock signal lines, each group of clock signal lines includes 2N clock signal lines; the multiple cascaded shift registers are divided into multiple groups of shift registers, each group of shift registers includes 2N shift registers; the shift registers located in the odd array are connected to the same group of clock signal lines, the shift registers located in the even array are connected to the same group of clock signal lines, and the shift registers located in the odd array and the even array are connected to different groups of clock signal lines; N is an integer greater than or equal to 1; wherein the shift register includes at least an input sub-circuit, an output sub-circuit, at least one pull-down control sub-circuit, and at least one pull-down sub-circuit.

[0083] Among them, the input subcircuit is configured to respond to the input signal of the signal input terminal Input and precharge the pull-up node through the input signal; the connection node between the input subcircuit, the output subcircuit and the pull-down subcircuit. The output subcircuit is configured to respond to the potential of the pull-up node and output the clock signal through the signal output terminal Output. The pull-down control subcircuit is configured to respond to the power supply voltage and control the potential of the pull-down node through the power supply voltage; a pull-down control subcircuit is connected to a first pull-down subcircuit and a second pull-down subcircuit, and the connection node between the three is a pull-down node. The pull-down subcircuit is configured to respond to the potential of the pull-up node and pull down the potential of the pull-down node through a non-working level signal. In particular, in the embodiment of the present disclosure, the pull-down control subcircuit in each group of shift registers is shared, and the pull-down subcircuit is shared.

[0084] In the gate drive circuit of the disclosed embodiment, the shift registers in the same group share a common pull-down control subcircuit and a common pull-down subcircuit. Simultaneously, with corresponding timing control, the signal input terminal of each shift register sequentially outputs a gate drive signal to the connected gate line. The specific operating method will be described below. Because the shift registers in the same group in the gate drive circuit share a common pull-down control subcircuit and a common pull-down subcircuit, the overall size of the gate drive circuit can be reduced, thereby achieving a narrow-frame design.

[0085] To better understand the gate drive circuit in the embodiment of the present disclosure, referring to Figures 4 and 5, N is 2 as an example. That is, each group of clock signal lines includes 4 clock signal lines, and two groups of clock signal lines include 8 clock signal lines, represented by CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, and CLK8, respectively. Accordingly, each group of shift registers includes 4 shift registers. For any two adjacent groups of shift registers, the output subcircuits of the four shift registers in one group are connected to CLK1, CLK2, CLK3, and CLK4, respectively, and the output subcircuits of the four shift registers in the other group are connected to CLK5, CLK6, CLK7, and CLK8, respectively. Furthermore, the output subcircuit of the Kth shift register and the output subcircuit of the K+8th shift register are connected to the same clock signal line, where K is an integer greater than or equal to 1. Each shift register includes two pull-down control sub-circuits 5 / 5' and two pull-down sub-circuits 6 / 6', wherein the connection node between one pull-down control sub-circuit and one pull-down sub-circuit is a first pull-down node PD1, and the connection node between the other pull-down control sub-circuit and another pull-down sub-circuit is a second pull-down node PD2.

[0086] The input subcircuit, output subcircuit, pull-down control subcircuit, and pull-down subcircuit in each shift register in the disclosed embodiments can all adopt the same structure as in Figures 2 and 3 , namely, the input subcircuit is composed of a first transistor, the output subcircuit is composed of a third transistor and a storage capacitor, and each pull-down control subcircuit includes a fifth transistor and a ninth transistor; the fifth transistor in the two pull-down control subcircuits 5 / 5' is represented by M5 and M5', respectively, and the ninth transistor is represented by M9 and M9', respectively. Each pull-down subcircuit includes a sixth transistor and an eighth transistor; the sixth transistor in the two pull-down subcircuits 6 / 6' is represented by M6 and M6', respectively, and the eighth transistor is represented by M8 and M8', respectively.

[0087] Continuing with Figure 4 , each shift register in the disclosed embodiment may further include a first reset subcircuit, a second reset subcircuit, two first noise reduction subcircuits 7 / 7', two second noise reduction subcircuits 8 / 8', two third noise reduction subcircuits 9 / 9', and a discharge subcircuit 10. The first reset subcircuit, the second reset subcircuit, the two first noise reduction subcircuits 7 / 7', the two second noise reduction subcircuits 8 / 8', the two third noise reduction subcircuits 9 / 9', and the discharge subcircuit 10 may all employ the same structures as those in Figures 2 and 3 . Each first noise reduction subcircuit includes a tenth transistor; the tenth transistor in the two first noise reduction subcircuits 7 / 7' is represented by M10 and M10', respectively. Each second noise reduction subcircuit includes an eleventh transistor; the eleventh transistor in the two second noise reduction subcircuits 8 / 8' is represented by M11 and M11', respectively. Each third noise reduction subcircuit includes a seventeenth transistor; the seventeenth transistors in the two third noise reduction subcircuits 9 / 9' are denoted by M17 and M17', respectively. Each auxiliary subcircuit includes a sixteenth transistor; the discharge subcircuit 10 includes a seventh transistor M7. The cascade subcircuit includes a fifteenth transistor M15.

[0088] 4 , each shift register in the embodiment of the present disclosure may further include an auxiliary subcircuit that may adopt the same structure as that in FIG. 2 , and the sixteenth transistors in the two auxiliary subcircuits 11 / 11 ′ are represented by M16 and M16 ′, respectively.

[0089] The connection relationship of each sub-circuit in each shift register is the same as that in FIG2 and FIG3 , and thus will not be repeated here.

[0090] In some examples, for each shift register, the gate and source of the first transistor M1 in the input sub-circuit 1 can be connected together, or the gate of the first transistor M1 can serve as the signal input terminal of the shift register. The source of the first transistor M1 can be connected to a precharge signal terminal, such as the operating power supply VDD. FIG4 illustrates the example of the gate and source of the first transistor M1 being connected together. In some examples, the first and second reset sub-circuits in the same group are connected to the same reset signal terminal, Reset. The discharge sub-circuits 10 in the same group are connected to the same pre-frame start signal terminal, TRST.

[0091] In some examples, in the gate drive circuit, the signal input terminal Input of the i-th shift register is connected to the cascade signal output terminal Out_C of the i-2-th shift register; i is an integer greater than or equal to 3. The reset signal terminal Reset of each shift register in the j-th group is connected to the signal output terminal Output of the 4th shift register in the j+1-th group; j is an integer greater than or equal to 1. For example: the P-th to P+3-th shift registers are a group, and the reset signal terminals Reset of the P-th to P+3-th shift registers are connected together and connected to the signal output terminal Output(P+7) of the P+7-th shift register or the cascade signal output terminal Out_C(P+7).

[0092] In order to more clearly understand the gate driving circuit of the embodiment of the present disclosure, the working process of a group of shift registers is specifically described below.

[0093] Referring to Figure 4 , the group of shift registers includes shift registers P through P+3, as indicated by the dashed boxes from left to right in the figure. The first dashed box includes the output subcircuit of each shift register, each including a first transistor. The second dashed box includes the discharge subcircuit 10 of each shift register, each including a seventh transistor. The third dashed box includes the first reset subcircuit of each phase shifter, each including a second transistor. The fourth dashed box includes two auxiliary subcircuits 11 / 11' shared by all shift registers. The fifth dashed box includes two first noise reduction subcircuits 7 / 7' shared by all shift registers. The sixth dashed box includes two pull-down subcircuits 6 / 6' shared by all shift registers. The seventh dashed box includes two third noise reduction subcircuits 9 / 9' shared by all shift registers. The eighth dashed box includes two second noise reduction subcircuits 8 / 8' shared by all shift registers. The ninth dashed box includes the second reset subcircuit of each shift register. The two pull-down control subcircuits shared by the shift registers are arranged 5 / 5' apart on the upper and lower sides of the pull-down subcircuit, and each pull-down control subcircuit includes a fifth transistor and a ninth transistor. The four output subcircuits of the shift registers are arranged in pairs on either side of the seventh and eighth dotted-line boxes.

[0094] Among them, for the structure in the first dotted box, the input signal of the P-th shift register is provided by the cascade signal output terminal Out_C(P-2) of the P-2-th shift register. Therefore, when the cascade signal output terminal Out_C(P) of the P-2-th shift register outputs a high level, the pull-up node PU(P) of the P-th shift register is pre-charged. Similarly, the input signal of the P+1-th shift register is provided by the cascade signal output terminal Out_C(P+1) of the P-1-th shift register. When the cascade signal output terminal Out_C(P-1) of the P-1-th shift register outputs a high level, the pull-up node PU(P+1) of the P+1-th shift register is pre-charged; the input signal of the P+2-th shift register is provided by the cascade signal output terminal Out_C(P) of the P-th shift register. When the cascade signal output terminal Out_C(P) of the shift register outputs a high level, the pull-up node PU(P+2) of the P+2th shift register is pre-charged; the input signal of the P+3th shift register is provided by the cascade signal output terminal Out_C(P+1) of the P+1th shift register, and when the cascade signal output terminal Out_C of the P+1th shift register outputs a high level, the pull-up node PU(P+3) of the P+3th shift register is pre-charged.

[0095] In the structure shown in the second dashed box, when a high-level signal is input to the pre-frame start signal terminal TRST, the discharge subcircuit 10 of each shift register operates. Specifically, the seventh transistor turns on, and the low-level signal input to the low-level signal terminal pulls down the pull-up node in each shift register. In other words, after each frame scan, the potential of the pull-up node in each shift register is simultaneously pulled down, discharging the pull-up node.

[0096] For the structure of the third dotted box, when the cascade signal output terminal Out_C of the P+7th shift register outputs a high-level signal, the first reset sub-circuit of each shift register in the group works, that is, each second transistor is turned on, and the pull-up nodes PU(P)~PU(P+3) of the four shift registers in a group are reset at the same time.

[0097] For the structure in the fourth dotted box, when a high-level signal is written to the signal input terminal Input of the P-th shift register, the two auxiliary sub-circuits 11 / 11' operate simultaneously, that is, the two sixteenth transistors are turned on, pulling down the first pull-down node PD1 and the second pull-down node PD2 respectively, reducing competition for the pull-up nodes PU(P)~PU(P+3).

[0098] For the structure within the fifth dashed box, when the first pull-down node PD1 is at a high level, a first noise reduction sub-circuit in each shift register operates, namely, the tenth transistor M10 operates, to reduce noise on the output of the pull-up node in each shift register. When the second pull-down node PD2 is at a high level, another first noise reduction sub-circuit in each shift register operates, namely, the tenth transistor M10' operates, to reduce noise on the output of the pull-up nodes PU(P) to PU(P+3) in each shift register.

[0099] For the structure in the sixth dotted box, when the pull-up node PU(P) in the P-th shift register is at a high level, one of the pull-down circuits works, that is, the sixth transistor M6 and the eighth transistor M8 work, pulling down the potential of the first lower control node and the first pull-down node PD1; when the pull-up node in the P+3-th shift register is at a high level, the other pull-down circuit works, that is, the sixth transistor M6' and the eighth transistor M8' work, pulling down the potential of the second lower control node and the second pull-down node PD2.

[0100] Regarding the structure within the seventh dotted-line box, when the first pull-down node PD1 is at a high level, a third noise reduction sub-circuit within each shift register operates, namely, the seventeenth transistor M17 operates, to reduce noise on the output of the cascade signal output terminal Out_C (signal output terminal Output) within each shift register. When the second pull-down node PD2 is at a high level, another third noise reduction sub-circuit within each shift register operates, namely, the seventeenth transistor M17' operates, to reduce noise on the output of the cascade signal output terminal Out_C (signal output terminal Output) within each shift register.

[0101] Regarding the structure within the eighth dashed box, when the first pull-down node PD1 is at a high level, one of the second noise reduction sub-circuits within each shift register, namely, the eleventh transistor M11, operates to reduce noise at the output of the signal output terminal "Output" within each shift register. When the second pull-down node PD2 is at a high level, another of the second noise reduction sub-circuits within each shift register, namely, the eleventh transistor M11', operates to reduce noise at the output of the signal output terminal "Output" within each shift register.

[0102] For the structure of the ninth dotted box, when the signal output terminal Output of the P+7th shift register outputs a high-level signal, the second reset sub-circuit of each shift register in the group works, that is, each fourth transistor is turned on, and the signal output terminals Output of the four shift registers in a group are reset at the same time.

[0103] For the two pull-down control sub-circuits 5 / 5', one is controlled by the first power supply voltage written to the first power supply voltage terminal, and the other is controlled by the second power supply voltage written to the second power supply voltage terminal. The first power supply voltage and the second power supply voltage have opposite timings, that is, the pull-down control sub-circuits operate in time-sharing mode, one controls the potential of the first pull-down node PD1, and the other controls the potential of the second pull-down node PD2.

[0104] Each output sub-circuit is controlled by the potential of the pull-up node to which it is connected. When the pull-up node is at a high level, the clock signal written into the clock signal line to which it is connected is output.

[0105] FIG6 is the working timing of the gate drive circuit of the embodiment of the present disclosure. As shown in FIG6 , four dotted lines are provided, namely line 1, line 2, line 3 and line 4. At line 1, when the signal output terminal Output (P-2) of the P-2 shift register outputs a signal, the first transistor in the input sub-circuit of the P-th shift register is turned on, so that the pull-up node PU (P) in the P-th shift register is about to start to be set high. When the clock signal CLK1 in the P-th shift register arrives, at line 2, due to the bootstrap function of the capacitor, the pull-up node PU (P) will continue to increase. At this time, the signal output terminal Output (P) in the P-th shift register will output a high-level signal. , until the clock signal in the Pth shift register at line 3 is set low, the pull-up node PU(P) drops and returns to its original level, until the signal output terminal Output(P+7) in the P+7th shift register at line 4 outputs a high level to reset the outputs of the pull-up nodes PU(P)~PU(P+3) and signal output terminals Output(P)~Output(P+3) of the Pth to P+3th shift registers. At this time, the pull-up node PU(P) in the Pth shift register is completely set low.

[0106] It should be noted that during the 9 H period from line1 to line4, the pull-up node in the Pth shift register is pulled low, but the pull-down node in the P+1th shift register continues to work until the pull-up node in the P+1th shift register is set high. The pull-down nodes in the Pth shift register and the P+1th shift register will not work, so there will be a 6H PD non-working time.

[0107] The inventors compared the space occupied by gate drive circuits of shift registers using 21T1C and 19T1C with that of panels using the above-mentioned gate drive circuits. Taking 218PPI products as an example, the details are shown in the table below.

[0108] As can be seen from the above table, the space occupied by the gate driving circuit in the embodiment of the present disclosure is significantly reduced, which is more conducive to achieving a narrow-frame design of the display panel.

[0109] Correspondingly, an embodiment of the present disclosure further provides a display device, which includes the above-mentioned gate driving circuit.

[0110] The display devices of the embodiments of the present disclosure include, but are not limited to, any products or components with display functions, such as mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, and navigators, but the embodiments of the present disclosure are not limited thereto.

[0111] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A gate drive circuit, comprising a plurality of cascaded shift registers and two groups of clock signal lines, each group of clock signal lines comprising 2N clock signal lines; the plurality of cascaded shift registers are divided into a plurality of groups of shift registers, each group of shift registers comprising 2N shift registers; the shift registers in the odd group are connected to the same group of clock signal lines, the shift registers in the even group are connected to the same group of clock signal lines, and the shift registers in the odd group and the even group are connected to different groups of clock signal lines; N is an integer greater than or equal to 1; wherein, The shift register at least includes an input subcircuit, an output subcircuit, at least one pull-down control subcircuit, and at least one pull-down subcircuit; the input subcircuit configured to precharge the pull-up node by the input signal in response to the input signal of the signal input terminal; a connection node between the input subcircuit, the output subcircuit and the pull-down subcircuit; The output subcircuit is configured to output the clock signal through the signal output terminal in response to the potential of the pull-up node; The pull-down control subcircuit is configured to respond to a power supply voltage and control the potential of the pull-down node by the power supply voltage; One of the pull-down control sub-circuits is connected to one of the pull-down sub-circuits, and a connection node between the two is the pull-down node; The pull-down subcircuit is configured to pull down the potential of the pull-down node through a non-working level signal in response to the potential of the pull-up node; wherein, The pull-down control sub-circuit in each group of the shift registers is shared, and the pull-down sub-circuit is shared.

2. The gate drive circuit according to claim 1, wherein: The shift register further includes: a first reset subcircuit and a second reset subcircuit; The first reset subcircuit is configured to reset the pull-up node via the non-working level signal in response to a reset signal; The second reset subcircuit is configured to reset the output of the signal output terminal through the non-working level signal in response to the reset signal.

3. The gate driving circuit according to claim 2, wherein: For one of the shift registers, the first reset subcircuit includes a second transistor, and the second reset subcircuit includes a fourth transistor; The first electrode of the second transistor is connected to the non-working level signal terminal, the second electrode is connected to the pull-up node, and the control electrode is connected to the reset signal terminal; The first electrode of the fourth transistor is connected to the non-working level signal terminal, the second electrode is connected to the signal output terminal, and the control electrode is connected to the reset signal terminal.

4. The gate driving circuit according to claim 3, wherein: For the shift registers in the same group, the control electrodes of the second transistors and the control electrodes of the fourth transistors are connected to the same reset signal terminal.

5. The gate driving circuit according to claim 1, wherein: The shift register further includes at least one first noise reduction subcircuit and at least one second noise reduction subcircuit; the first noise reduction subcircuit and the second noise reduction subcircuit are both connected to the pull-down nodes in a one-to-one correspondence; The first noise reduction sub-circuit is configured to reduce the potential of the pull-up node by a non-working level signal in response to the potential of the pull-down node connected thereto; The second noise reduction sub-circuit is configured to perform noise reduction on the output of the signal output terminal through a non-working level signal in response to the potential of the pull-down node connected thereto.

6. The gate driving circuit according to claim 5, wherein: For one of the shift registers, the first noise reduction sub-circuit includes a tenth transistor, and the second noise reduction sub-circuit includes an eleventh transistor; The first electrode of the tenth transistor is connected to the non-working level signal terminal, the second electrode is connected to the pull-up node, and the control electrode is connected to the pull-down node; The first electrode of the eleventh transistor is connected to the non-working level signal terminal, the second electrode is connected to the signal output terminal, and the control electrode is connected to the pull-down node.

7. The gate driving circuit according to claim 1, wherein: The shift register further includes a discharge subcircuit configured to respond to a pre-frame start signal and discharge the pull-up node through a non-operating level signal.

8. The gate driving circuit according to claim 7, wherein: For one of the shift registers, the discharge subcircuit includes a seventh transistor; The first electrode of the seventh transistor is connected to the non-working level signal terminal, the second electrode is connected to the pull-up node, and the control electrode is connected to the pre-frame start signal terminal.

9. The gate driving circuit according to claim 1, wherein: The shift register further comprises at least one auxiliary subcircuit, and the auxiliary subcircuit is connected to the pull-down nodes in a one-to-one correspondence; The auxiliary sub-circuit is configured to pull down the pull-down node through the non-working level signal in response to the input signal.

10. The gate driving circuit according to claim 9, wherein: The auxiliary sub-circuit of each shift register in the same group is shared.

11. The gate driving circuit according to claim 9, wherein: The auxiliary subcircuit includes a sixteenth transistor; The first electrode of the sixteenth transistor is connected to the non-working level signal terminal, the second electrode is connected to the corresponding pull-down node, and the control electrode is connected to the signal input terminal.

12. The gate driving circuit according to claim 1, wherein: For one of the shift registers, the input subcircuit comprises a first transistor, a first electrode and a control electrode of the first transistor are both connected to the signal input terminal, and a second electrode is connected to the pull-up node; or, The first electrode of the first transistor is connected to the pre-charge source signal terminal, the second electrode is connected to the pull-up node, and the control electrode is connected to the signal input terminal.

13. The gate driving circuit according to claim 1, wherein: For one of the shift registers, the output subcircuit includes a third transistor, a fifteenth transistor and a storage capacitor; The first electrode of the third transistor is connected to the clock signal terminal, the second electrode is connected to the signal output terminal and the second terminal of the storage capacitor, and the control electrode is connected to the first terminal of the storage capacitor; The first electrode of the fifteenth transistor is connected to the clock signal terminal, the second electrode is connected to the cascade signal output terminal, and the control electrode is connected to the first terminal of the storage capacitor; For a group of the shift registers, the clock signal lines connected to the shift registers are located at Different shift registers in the same group are connected to different clock signal lines.

14. The gate driving circuit according to claim 13, wherein: The shift register further includes at least one third noise reduction subcircuit, and the third noise reduction subcircuit is connected to the pull-down node in a one-to-one correspondence; The third noise reduction sub-circuit is configured to perform noise reduction on the output of the cascade signal output terminal through the non-working level signal in response to the potential of the pull-down node connected thereto.

15. The gate driving circuit according to claim 14, wherein: The third noise reduction sub-circuit includes a seventeenth transistor; The first electrode of the seventeenth transistor is connected to the non-working level signal terminal, the second electrode is connected to the cascade signal output terminal, and the control electrode is connected to the pull-down node.

16. The gate driving circuit according to claim 1, wherein: The pull-down control subcircuit includes a fifth transistor and a ninth transistor; The first electrode of the fifth transistor is connected to the power supply voltage terminal, the second electrode is connected to the corresponding pull-down node, and the control electrode is connected to the second electrode of the ninth transistor; The first electrode and the control electrode of the ninth transistor are both connected to the power supply voltage terminal; The first electrodes of the fifth transistors in a group of the shift registers are connected to different power supply voltage terminals.

17. The gate driving circuit according to claim 16, wherein: For one of the shift registers, the pull-down subcircuit includes a sixth transistor and an eighth transistor; The first electrode of the sixth transistor is connected to the non-working level signal terminal, the second electrode is connected to the corresponding pull-down node, and the control electrode is connected to the pull-up node; The first electrode of the eighth transistor is connected to the non-working level signal terminal, the second electrode is connected to the control electrode of the fifth transistor in the corresponding pull-down control subcircuit and the second electrode of the ninth transistor, and the control electrode is connected to the pull-up node.

18. The gate driving circuit according to claim 1, wherein: The N is 4.

19. The gate driving circuit according to claim 18, wherein: The signal input end of the i-th shift register is connected to the cascade signal output end of the i-2-th shift register; i is an integer greater than or equal to 3; The reset signal terminal of each shift register in the jth group is connected to the signal output terminal or the cascade signal output terminal of the 4th shift register in the j+1th group; j is an integer greater than or equal to 1.

20. A display device comprising the gate driving circuit according to any one of claims 1 to 19.

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