Pixel circuit and driving method thereof, display panel, and display device

Abstract

Provided are a pixel circuit and a driving method thereof, a display panel, and a display device, relating to the technical field of display. The pixel circuit comprises a driving circuit and a compensation circuit. The driving circuit can transmit a reset power signal to a driving node, so as to reset a light-emitting element coupled to the driving node, and can transmit a light-emitting driving signal to the driving node, so as to drive the light-emitting element coupled to the driving node to emit light. The compensation circuit can control a reset power line to provide the same reset power signal in all time periods, thus ensuring that the stability of the potential of the reset power signal transmitted to the driving node is good. In this way, even if the light-emitting element is charged and discharged multiple times within one frame, reliable resetting of the light-emitting element can be ensured, thereby avoiding the occurrence of a display abnormality of uneven screen splitting in a display panel.

Description

Pixel circuit and driving method thereof, display panel, and display device

[0001] This disclosure claims priority to Chinese patent application number 202311271348.X filed on September 28, 2023, entitled “Pixel circuit and driving method thereof, display panel, and display device,” the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, a display panel, and a display device. Background Art

[0003] The display panel generally includes a substrate and pixels located on the substrate. The pixels further include a pixel circuit and a light-emitting element. Among them, the pixel circuit is coupled to the light-emitting element and is used to transmit a light-emitting drive signal to the light-emitting element to drive the light-emitting element to emit light, and transmit a reset power supply signal to the light-emitting element to reset the light-emitting element, so that the light-emitting elements of different pixels can emit light at the same potential based on the received light-emitting drive signal. In addition, in order to reduce power consumption, low-frequency or variable-frequency driving is often used, and pixel circuits are often designed using P-type transistors and N-type transistors made of low-temperature polysilicon oxide (LTPO). Based on this scenario, the light-emitting element will be charged and discharged multiple times within one frame, that is, the reset power supply signal will be repeatedly transmitted multiple times.

[0004] However, due to the poor potential stability of the reset power supply signal, the light-emitting element cannot be reliably charged and discharged, which in turn causes the display panel to have uneven display abnormalities.

[0005] Summary of the Invention

[0006] Provided are a pixel circuit and a driving method thereof, a display panel, and a display device.

[0007] The technical solution is as follows:

[0008] In one aspect, a pixel circuit is provided, comprising:

[0009] a driving circuit coupled to a driving control line, a reset control line, a reset power line, and a driving node, respectively, and configured to: transmit a light-emitting driving signal to the driving node based on a driving control signal provided by the driving control line; and control the connection and disconnection between the reset power line and the driving node under the control of a reset control signal provided by the reset control line; the driving node being configured to be coupled to a light-emitting element;

[0010] The compensation circuit is coupled to the compensation control line, the compensation signal line and the reset power line respectively, and is used to: under the control of the compensation control signal provided by the compensation control line, based on the compensation signal provided by the compensation signal line, control the reset power line to provide the same reset power signal in any time period.

[0011] Optionally, the compensation control line includes: a first compensation control line and a second compensation control line; the potential of the compensation signal provided by the compensation signal line is determined based on the potential of the driving node when the light-emitting element emits light at a target grayscale;

[0012] The compensation circuit is further coupled to an equivalent node of the driving node and a pull-down power line coupled to the light-emitting element, respectively; the compensation circuit is configured to: control the connection and disconnection between the compensation signal line and the equivalent node based on a first compensation control signal provided by the first compensation control line, control the connection and disconnection between the reset power line and the equivalent node based on a second compensation control signal provided by the second compensation control line, and further adjust the potential of the equivalent node based on a pull-down power signal provided by the pull-down power line;

[0013] The driving node is used to couple with the first electrode of the light-emitting element, and the second electrode of the light-emitting element is coupled with the pull-down power line.

[0014] Optionally, the compensation circuit includes:

[0015] a first switch sub-circuit, coupled to the first compensation control line, the compensation signal line, and the equivalent node, respectively, and configured to control the on / off connection between the compensation signal line and the equivalent node based on the first compensation control signal;

[0016] a second switch sub-circuit, coupled to the second compensation control line, the equivalent node, and the reset power line, respectively, and configured to control the connection and disconnection of the reset power line and the equivalent node based on the second compensation control signal;

[0017] The potential regulating subcircuit is coupled to the equivalent node and the pull-down power line respectively, and is used for regulating the potential of the equivalent node based on the pull-down power signal.

[0018] Optionally, the first switch subcircuit includes: a first transistor; the second switch subcircuit includes: a second transistor; the potential adjustment subcircuit includes: a capacitor;

[0019] The gate of the first transistor is coupled to the first compensation control line, the first electrode of the first transistor is coupled to the compensation signal line, and the second electrode of the first transistor is coupled to the equivalent node;

[0020] The gate of the second transistor is coupled to the second compensation control line, the first electrode of the second transistor is coupled to the reset power line, and the second electrode of the second transistor is coupled to the equivalent node;

[0021] The capacitor is connected in series between the equivalent node and the pull-down line.

[0022] Optionally, the compensation control line includes: a first compensation control line and a second compensation control line; the compensation signal line includes: a first compensation signal line and a second compensation signal line, the compensation signal provided by the first compensation signal line is the reset power signal provided by the reset power line during a refresh period, and the reset power signal provided by the reset power line is controlled based on the compensation signal provided by the second compensation signal line to be the same as the compensation signal provided by the first compensation signal line;

[0023] The compensation circuit is used to: control the on / off connection between the first compensation signal line and the reset power line based on a first compensation control signal provided by the first compensation control line, and control the on / off connection between the second compensation signal line and the reset power line based on a second compensation control signal provided by the second compensation control line.

[0024] Optionally, the compensation circuit includes:

[0025] a third switch sub-circuit, coupled to the first compensation control line, the first compensation signal line, and the reset power line, respectively, and configured to control the on / off switching of the first compensation signal line and the reset power line based on the first compensation control signal;

[0026] The fourth switch sub-circuit is coupled to the second compensation control line, the second compensation signal line and the reset power line respectively, and is used to control the connection and disconnection of the second compensation signal line and the reset power line based on the second compensation control signal.

[0027] Optionally, the compensation signal provided by the second compensation signal line is the same as the compensation signal provided by the first compensation signal line;

[0028] Alternatively, the compensation signal provided by the second compensation signal line is different from the compensation signal provided by the first compensation signal line, and the compensation circuit further includes: a voltage divider subcircuit connected in series between the second compensation signal line and the fourth switch subcircuit.

[0029] Optionally, the third switch sub-circuit includes: a third transistor; the fourth switch sub-circuit includes: a fourth transistor; the voltage divider sub-circuit includes: a voltage divider resistor;

[0030] The gate of the third transistor is coupled to the first compensation control line, the first electrode of the third transistor is coupled to the first compensation signal line, and the second electrode of the third transistor is coupled to the reset power line;

[0031] The gate of the fourth transistor is coupled to the second compensation control line, the first electrode of the fourth transistor is coupled to the second compensation signal line, and the second electrode of the fourth transistor is coupled to the reset power line;

[0032] The voltage-dividing resistor is connected in series between the second compensation signal line and the first electrode of the fourth transistor.

[0033] Optionally, the transistors in the pixel circuit all include: an active layer, a gate metal layer, and a source / drain metal layer stacked in sequence;

[0034] In which, the active layer of the transistor in the compensation circuit extends along the first direction; the compensation control line and the compensation signal line coupled to the compensation circuit both extend along the second direction, and the compensation control line and the gate metal layer are located in the same layer; the compensation signal line and the source and drain metal layer are located in the same layer; the second direction intersects with the first direction.

[0035] In another aspect, a method for driving a pixel circuit is provided, which is applied to the pixel circuit described in the first aspect above; the method comprises: a plurality of refresh periods executed sequentially, and a waiting period between each two adjacent refresh periods;

[0036] During the refresh period and the waiting period, the compensation circuit controls the reset power line to provide the same reset power signal based on the compensation signal provided by the compensation signal line under the control of the compensation control signal provided by the compensation control line;

[0037] During the refresh period, the driving circuit, under the control of the reset control signal provided by the reset control line, controls the reset power line and the driving node coupled to the light-emitting element to be first turned on and then disconnected, and after controlling the reset power line to be disconnected from the driving node, transmits a light-emitting driving signal to the driving node based on the driving control signal provided by the driving control line to drive the light-emitting element to emit light.

[0038] Optionally, the compensation control line includes: a first compensation control line and a second compensation control line; the potential of the compensation signal is determined based on the potential of the driving node when the light-emitting element emits light at a target grayscale;

[0039] The compensation circuit controls the reset power line to provide the same reset power signal based on the compensation signal provided by the compensation signal line under the control of the compensation control signal provided by the compensation control line, including:

[0040] During the refresh period, the compensation circuit controls the compensation signal line and the reset power line to be decoupled from the equivalent node of the driving node under the control of a first compensation control signal provided by the first compensation control line and a second compensation control signal provided by the second compensation control line;

[0041] In the waiting stage, the compensation circuit controls the compensation signal line and the reset power line to be alternately turned on with the equivalent node under the control of the first compensation control signal and the second compensation control signal, so as to control the reset power line to provide the same reset power signal during the refresh period and the waiting period.

[0042] Optionally, the compensation control line includes: a first compensation control line and a second compensation control line; the compensation signal line includes: a first compensation signal line and a second compensation signal line, the compensation signal provided by the first compensation signal line is the reset power signal provided by the reset power line during a refresh period, and the reset power signal provided by the reset power line is controlled based on the compensation signal provided by the second compensation signal line to be the same as the compensation signal provided by the first compensation signal line;

[0043] The compensation circuit controls the reset power line to provide the same reset power signal based on the compensation signal provided by the compensation signal line under the control of the compensation control signal provided by the compensation control line, including:

[0044] During the refresh period, the compensation circuit controls the first compensation signal line to be connected to the reset power line under the control of a first compensation control signal provided by the first compensation control line, and controls the second compensation signal line to be disconnected from the reset power line under the control of a second compensation control signal provided by the second compensation control line;

[0045] During the waiting period, the compensation circuit controls the second compensation signal line to be connected to the reset power line under the control of the second compensation control signal, and controls the first compensation signal line to be disconnected from the reset power line under the control of the first compensation control signal.

[0046] In yet another aspect, a display panel is provided, comprising: a substrate, and pixels located on the substrate;

[0047] The pixel includes: a light-emitting element, and the pixel circuit as described in the above aspect; the pixel circuit is coupled to the light-emitting element and is used to drive the light-emitting element to emit light.

[0048] Optionally, the substrate has a display area and a non-display area adjacent to each other;

[0049] The driving circuit included in the pixel circuit is located in the display area, and the compensation circuit included in the pixel circuit is located in the non-display area.

[0050] In another aspect, a display device is provided, comprising: a power supply component, and the display panel as described in the above-mentioned further aspect;

[0051] The power supply component is coupled to the display panel and is used to supply power to the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0053] FIG1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0054] FIG2 is a waveform diagram of a reset power signal provided by a reset power line in the related art;

[0055] FIG3 is a waveform diagram of a reset power signal provided by a reset power line according to an embodiment of the present disclosure;

[0056] FIG4 is a circuit structure diagram of a driving circuit in a pixel circuit provided by an embodiment of the present disclosure;

[0057] FIG5 is a schematic structural diagram of a compensation circuit in a pixel circuit provided by an embodiment of the present disclosure;

[0058] FIG6 is a circuit structure diagram of a compensation circuit in a pixel circuit provided by an embodiment of the present disclosure;

[0059] FIG7 is a schematic structural diagram of a compensation circuit in another pixel circuit provided by an embodiment of the present disclosure;

[0060] FIG8 is a circuit structure diagram of another compensation circuit in a pixel circuit provided by an embodiment of the present disclosure;

[0061] FIG9 is a schematic structural diagram of a compensation circuit in another pixel circuit provided by an embodiment of the present disclosure;

[0062] FIG10 is a circuit structure diagram of a compensation circuit in another pixel circuit provided by an embodiment of the present disclosure;

[0063] FIG11 is a structural diagram of a compensation circuit in a pixel circuit provided by an embodiment of the present disclosure;

[0064] FIG12 is a flow chart of a driving method for a pixel circuit provided in an embodiment of the present disclosure;

[0065] FIG13 is a timing diagram of a compensation control signal provided by an embodiment of the present disclosure;

[0066] FIG14 is a timing diagram of another compensation control signal provided by an embodiment of the present disclosure;

[0067] FIG15 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0068] FIG16 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0069] FIG17 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0070] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0071] It should be noted that the transistors used in all embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of the present disclosure are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as the first electrode, and the drain is referred to as the second electrode. According to the configuration in the accompanying drawings, the middle end of the transistor is designated as the control electrode, which can also be referred to as the gate, the signal input end is designated as the source electrode, and the signal output end is designated as the drain electrode. Furthermore, the switching transistors used in the embodiments of the present disclosure can include either a P-type switching transistor or an N-type switching transistor. A P-type switching transistor is turned on when the gate is at a low level and turned off when the gate is at a high level, while an N-type switching transistor is turned on when the gate is at a high level and turned off when the gate is at a low level. Furthermore, multiple signals in each embodiment of the present disclosure correspond to a first potential and a second potential. The first potential and the second potential merely represent that the potential of the signal has two state variables and do not imply that the first potential or the second potential has a specific value throughout the text.

[0072] FIG1 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure. As shown in FIG1 , the pixel circuit includes:

[0073] The driving circuit 01 is coupled to the driving control line Con1, the reset control line Scan, the reset power line Vinit, and the driving node N0, respectively, and is used to: transmit a light-emitting driving signal to the driving node N0 based on a driving control signal provided by the driving control line Con1; and control the connection and disconnection of the reset power line Vinit and the driving node N0 under the control of a reset control signal provided by the reset control line Scan.

[0074] The driving node N0 is used to couple to the light-emitting element L1. Optionally, referring to FIG1 , the driving node N0 can be coupled to the first electrode of the light-emitting element L1, and the second electrode of the light-emitting element L1 can also be coupled to the pull-down power line VSS. Here, the first electrode of the light-emitting element L1 can be an anode, and the second electrode of the light-emitting element L1 can be a cathode. Of course, in some embodiments, the first electrode of the light-emitting element L1 can also be a cathode, and the second electrode of the light-emitting element L1 can be an anode. That is, the anode and cathode of the light-emitting element L1 can be interchangeable.

[0075] For example, when the potential of the reset control signal provided by the reset control line Scan is at a first potential, the driver circuit 01 can control the reset power line Vinit to be conductive with the driver node N0, so that the reset power signal provided by the reset power line Vinit is transmitted to the driver node N0 to reset the anode of the light-emitting element L1. Furthermore, when the potential of the reset control signal provided by the reset control line Scan is at a second potential, the driver circuit 01 can control the reset power line Vinit to be decoupled from the driver node N0. Thereafter, the driver circuit 01 can transmit a light-emitting drive signal to the driver node N0, so that the light-emitting element L1 reliably emits light under the voltage difference between the light-emitting drive signal and the pull-down power signal provided by the pull-down power line VSS. The period during which the light-emitting element L1 is controlled to emit light is also referred to as a refresh period. Two adjacent refresh periods often include a porch period. During both the porch period and the refresh period, the anode of the light-emitting element L1 can be reset.

[0076] Optionally, in the disclosed embodiment, the first potential may be an effective potential, the second potential may be an ineffective potential, and the first potential may be a low potential relative to the second potential. This is for a P-type transistor with an effective low potential. For an N-type transistor, the first potential is a high potential relative to the second potential.

[0077] As described in the background technology, the potential stability of the reset power signal provided by the reset power terminal Vinit is poor. For example, as shown in FIG2 , the potential of the reset power signal is different in each refresh period and the Porch period between each two adjacent refresh periods, and generally the potential in the Porch period is less than the potential in the refresh period. In this way, the luminous brightness of the light-emitting element L1 of the reset drive node N0 during the Porch period will be low, resulting in an abnormal display problem of uneven split screen. In the embodiment of the present disclosure, it can be seen from FIG1 that the pixel circuit further includes:

[0078] The compensation circuit 02 is coupled to the compensation control line V1, the compensation signal line V2 and the reset power line Vinit, respectively, and is used to: under the control of the compensation control signal provided by the compensation control line V1, based on the compensation signal provided by the compensation signal line V2, control the reset power line Vinit to provide the same reset power signal in any time period, thereby achieving effective compensation for the reset power signal with a lower potential in the Porch period as shown in Figure 2.

[0079] That is, the embodiment of the present disclosure controls the reset power line Vinit to provide the same reset power signal as shown in FIG3 during both the Porch period and the refresh period shown in FIG2 , thereby ensuring good potential stability of the reset power signal and thereby improving the display abnormality problem of uneven split screen. It should be noted that, in conjunction with FIG2 and FIG3 , the embodiment of the present disclosure controls the reset power line Vinit to provide the same reset power signal during any period, which means that the fluctuation of the reset power signal during any period is the same, and the average potential value is the same.

[0080] In summary, an embodiment of the present disclosure provides a pixel circuit. The pixel circuit includes a driving circuit and a compensation circuit. Among them, the driving circuit is capable of transmitting a reset power signal to the driving node to reset the light-emitting element coupled to the driving node; and is capable of transmitting a light-emitting driving signal to the driving node to drive the light-emitting element coupled to the driving node to emit light. The compensation circuit is capable of controlling the reset power line to provide the same reset power signal in any time period, that is, ensuring that the potential stability of the reset power signal transmitted to the driving node is better. In this way, even if the light-emitting element is charged and discharged multiple times within a frame, the light-emitting element can be reliably reset, avoiding the display abnormality of uneven screen splitting of the display panel, and ensuring a better display effect.

[0081] Optionally, FIG4 shows a circuit structure diagram of a driving circuit provided by an embodiment of the present disclosure. As shown in FIG4 , the driving circuit 01 may include a driving part 011 and a reset part 012 .

[0082] The driving part 011 may be coupled to the driving control line Con1 and the driving node N0 respectively, and may be used to transmit a light-emitting driving signal to the driving node N0 based on a driving control signal provided by the driving control line Con1 .

[0083] The reset part 012 can be coupled to the reset control line Scan, the reset power line Vinit and the driving node N0 respectively, and can be used to control the connection and disconnection of the reset power line Vinit and the driving node N0 under the control of the reset control signal provided by the reset control line Scan.

[0084] Optionally, referring to FIG4 , it can be seen that the driving portion 011 may include 8 transistors T01 to T08 and 1 storage capacitor Cst. Among them, the transistor T08 may be an N-type oxide transistor; and the remaining transistors except the transistor T08 may all be P-type low-temperature polysilicon transistors. In this way, the driving circuit 01 including the driving portion 011 may be referred to as a driving circuit 01 of an LTPO structure. In addition, the driving control line Con1 coupled to the driving portion 011 may include: a gate line Gn_P coupled to the gate of the P-type transistor, a gate line Gn_N coupled to the gate of the N-type transistor, a reset line Re_P, a light-emitting control line EM, and also includes the reset control line Scan as described in the above embodiment. In addition, the driving portion 011 may also be coupled to the data line Vdata, the reference line Vref, and the driving power line VDD, respectively. Under the control of the signals provided by the above control lines, the driving portion 011 can transmit a light-emitting drive signal to the driving node N0 based on the data signal provided by the data line Vdata, the reference signal provided by the reference line Vref, the driving power signal provided by the driving power line VDD, and the reset power signal, thereby driving the light-emitting element L1 to emit light. The transistor T03 can be a driving transistor for generating the required light-emitting drive signal. The reset portion 012 can include a transistor T09, which can be a P-type low-temperature polysilicon transistor. The gate of the transistor T09 can be coupled to the reset control line Scan, the first electrode of the transistor T09 can be coupled to the reset power line Vinit, and the second electrode of the transistor T09 can be coupled to the driving node N0.

[0085] Based on the above structure, it can be seen that when the reset control line Scan provides a reset control signal at a first potential, the emission control line EM can provide a light emission control signal at a second potential. At this time, transistor T09 included in the reset portion 012 can be turned on, while transistor T06 included in the drive portion 011 can be turned off. Furthermore, the second electrode of transistor T03 (i.e., the drive transistor) can be disconnected from the second electrode of transistor T06, while the reset power line Vinit is connected to the drive node N0. Accordingly, the reset power line Vinit can transmit the reset power signal to the drive node N0 via the turned-on transistor T09, thereby resetting the anode of the light-emitting element L1 coupled to the drive node N0. When the reset control line Scan provides a reset control signal of the second potential, the light-emitting control line EM can provide a light-emitting control signal of the first potential; at this time, the transistor T06 included in the driving part 011 can be turned on, and the transistor T09 included in the reset part 012 can be turned off; furthermore, the reset power line Vinit and the driving node N0 can be disconnected, and the second electrode of the transistor T03 (i.e., the driving transistor) and the second electrode of the transistor T06 can be turned on. Accordingly, the light-emitting drive signal generated by the transistor T03 can be transmitted to the driving node N0 via the turned-on transistor T06 to drive the light-emitting element L1 to emit light. It can be seen from this that the compensation circuit 02 provided in the embodiment of the present disclosure compensates for the reset power signal provided by the reset power line Vinit coupled to the transistor T09 included in the reset part 012 in Figure 4.

[0086] It should be noted that the driving part 011 in the driving circuit 01 described in the embodiment of the present disclosure is not limited to the 8T1C structure shown in Figure 4. For example, in some embodiments, it can also be a 6T2C or 7T1C structure.

[0087] Optionally, the compensation circuit 02 provided in the embodiment of the present disclosure can compensate the reset power signal in various ways, so that the reset power signal is the same in any time period.

[0088] As an optional implementation:

[0089] 5 shows a schematic diagram of a compensation circuit structure. The compensation control line V1 may include a first compensation control line V11 and a second compensation control line V12. The potential of the compensation signal provided by the compensation signal line V2 may be determined based on the potential of the drive node N0 when the light-emitting element L1 emits light at a target grayscale.

[0090] Here, the target grayscale mostly refers to a low grayscale. For example, the potential V-V2 of the compensation signal can satisfy: V-V2 = VSS0 + Vop_L1 + 0~2V;

[0091] VSS0 refers to the potential of the pull-down power signal provided by the pull-down power line VSS; Vop_L1 refers to the turn-on voltage required for the light-emitting element L1 to emit light, and 0-2V (volts) refers to a preset adjustable value.

[0092] It should be noted that a pixel typically includes multiple sub-pixels (e.g., a red sub-pixel, a green sub-pixel, and a blue sub-pixel), each of which may include a pixel circuit and a light-emitting element. If compensation is performed separately for the multiple sub-pixels in each pixel, the potential V-V2 of the compensation signal can be set one-to-one; this refers to setting the potential of the node N0 driven by the light-emitting element L1 in different sub-pixels when emitting light at the target grayscale. If uniform compensation is performed for a pixel including multiple sub-pixels, the potential V-V2 of the compensation signal can be the average value of the multiple sub-pixels; this refers to taking the average value of the potentials of the compensation signals set separately for different sub-pixels. In this way, a better compensation effect can be ensured.

[0093] Continuing with reference to FIG5 , it can be seen that compensation circuit 02 can also be coupled to the equivalent node N1 of driving node N0 and the pull-down power line VSS. Compensation circuit 02 is configured to: control the connection between compensation signal line V2 and equivalent node N1 based on a first compensation control signal provided by a first compensation control line V11; control the connection between reset power line Vinit and equivalent node N1 based on a second compensation control signal provided by a second compensation control line V12; and adjust the potential of equivalent node N1 based on a pull-down power signal provided by the pull-down power line VSS.

[0094] For example, the compensation circuit 02 can control the compensation signal line V2 to be conductively coupled to the equivalent node N1 when the potential of the first compensation control signal provided by the first compensation control line V11 is a first potential, and can control the compensation signal line V2 to be decoupled from the equivalent node N1 when the potential of the first compensation control signal provided by the first compensation control line V11 is a second potential. Similarly, the compensation circuit 02 can control the reset power line Vinit to be conductively coupled to the equivalent node N1 when the potential of the second compensation control signal provided by the second compensation control line V12 is a first potential, and can control the reset power line Vinit to be decoupled from the equivalent node N1 when the potential of the second compensation control signal provided by the second compensation control line V12 is a second potential.

[0095] Optionally, referring to FIG5 , it can be seen that the compensation circuit 02 may include:

[0096] The first switch sub-circuit 021 can be coupled to the first compensation control line V11, the compensation signal line V2 and the equivalent node N1 respectively, and can be used to control the on / off of the compensation signal line V2 and the equivalent node N1 based on the first compensation control signal.

[0097] For example, the first switch sub-circuit 021 can control the compensation signal line V2 to be connected to the equivalent node N1 when the potential of the first compensation control signal is the first potential, and can control the compensation signal line V2 to be disconnected from the equivalent node N1 when the potential of the first compensation control signal is the second potential.

[0098] The second switch sub-circuit 022 can be coupled to the second compensation control line V12, the equivalent node N1 and the reset power line Vinit respectively, and can be used to control the on / off of the reset power line Vinit and the equivalent node N1 based on the second compensation control signal.

[0099] For example, the second switch sub-circuit 022 can control the reset power line Vinit to be connected to the equivalent node N1 when the potential of the second compensation control signal is the first potential, and can control the reset power line Vinit to be disconnected from the equivalent node N1 when the potential of the second compensation control signal is the second potential.

[0100] The potential regulating sub-circuit 023 may be coupled to the equivalent node N1 and the pull-down power line VSS, respectively, and may be used to regulate the potential of the equivalent node N1 based on the pull-down power signal.

[0101] Based on Figure 5 , Figure 6 shows a circuit structure diagram of a compensation circuit. Referring to Figure 6 , it can be seen that the first switch subcircuit 021 may include a first transistor T1 , the second switch subcircuit 022 may include a second transistor T2 , and the potential adjustment subcircuit 023 may include a capacitor C1 .

[0102] The gate of the first transistor T1 may be coupled to the first compensation control line V11 , the first electrode of the first transistor T1 may be coupled to the compensation signal line V2 , and the second electrode of the first transistor T1 may be coupled to the equivalent node N1 .

[0103] A gate of the second transistor T2 may be coupled to the second compensation control line V12 , a first electrode of the second transistor T2 may be coupled to the reset power line Vinit, and a second electrode of the second transistor T2 may be coupled to the equivalent node N1 .

[0104] The capacitor C1 may be connected in series between the equivalent node N1 and the pull-down line. The capacitor C1 may refer to the equivalent capacitance of the driving node N0.

[0105] It should be noted that if compensation is performed separately for multiple sub-pixels in each pixel, the capacitance of the capacitor C1 can be matched one by one. If uniform compensation is performed for a pixel including multiple sub-pixels, the capacitance of the capacitor C1 can be the sum; here it refers to the sum of the capacitances matched for different sub-pixels. In addition, in some embodiments, based on multiple rows and columns of pixels, the capacitance of the capacitor C1 can be the sum of the capacitances of the equivalent capacitances corresponding to the driving node N0 in all pixels located in the same row; or, it can also be the result of dividing the sum of the capacitances of the equivalent capacitances corresponding to the driving node N0 in all pixels located in the same row, which can be divided equally or unequally. For example, it can be divided into three equal parts.

[0106] It should also be noted that the structure shown in FIG6 can be considered as a 2T1C (comprising two transistors and one capacitor) structure compensation circuit 02, wherein the first transistor T1 and the second transistor T2 can both be P-type transistors.

[0107] For the above-mentioned optional implementation, the compensation control signals provided by the first compensation control line V11 and the second compensation control line V12 can be flexibly controlled to simulate the charging and discharging actions for the driving node N0, so that the reset power signal provided by the final reset power line Vinit is the same during the Porch period and the refresh period, satisfying the fluctuation condition of Figure 3 and eliminating the abnormal display problem of uneven split screen. That is, in conjunction with Figure 4, the first compensation control line V11 can simulate the light-emitting control line EM, which belongs to the EM_dum signal line; the second compensation control line V12 can simulate the reset control line Scan, which belongs to the Scan_dum signal line; the compensation signal line V2 can be identified as V_N0_avr to indicate the compensation signal provided based on the potential of the driving node N0. The above-mentioned optional implementation is similar to the equivalent compensation of the resistor and capacitor RC.

[0108] For example, during the refresh period, the first compensation control line V11 and the second compensation control line V12 can be controlled to provide compensation control signals of the second potential, so that the first transistor T1 and the second transistor T2 are both turned off and no compensation is performed on the reset power signal provided by the reset power line Vinit. During the Porch period, the first compensation control line V11 and the second compensation control line V12 can be controlled to alternately provide compensation control signals of the first potential, so that the first transistor T1 and the second transistor T2 are alternately turned on, thereby simulating the action of the drive circuit O1 controlling the drive node N0, achieving reliable compensation for the reset power signal provided by the reset power line Vinit, and ensuring that the reset power signal provided during the Porch period is the same as the reset power signal provided during the refresh period.

[0109] As another optional implementation:

[0110] Referring to the schematic structural diagram of another compensation circuit shown in FIG7 , the compensation control line V1 may include a first compensation control line V11 and a second compensation control line V12. The compensation signal line V2 may include a first compensation signal line V21 and a second compensation signal line V22. The compensation signal provided by the first compensation signal line V21 is the reset power signal provided by the reset power line Vinit during the refresh period. The reset power signal provided by the reset power line Vinit is controlled based on the compensation signal provided by the second compensation signal line V22 to be the same as the compensation signal provided by the first compensation signal line V21.

[0111] On this basis, the compensation circuit 02 can be used to: control the on-off connection between the first compensation signal line V21 and the reset power line Vinit based on the first compensation control signal provided by the first compensation control line V11, and control the on-off connection between the second compensation signal line V22 and the reset power line Vinit based on the second compensation control signal provided by the second compensation control line V12.

[0112] For example, the compensation circuit 02 can control the first compensation signal line V21 to be electrically connected to the reset power line Vinit when the potential of the first compensation control signal provided by the first compensation control line V11 is a first potential, so that the compensation signal provided by the first compensation signal line V21 is transmitted to the reset power line Vinit. Furthermore, the compensation circuit 02 can control the first compensation signal line V21 to be disconnected from the reset power line Vinit when the potential of the first compensation control signal provided by the first compensation control line V11 is a second potential. Similarly, the compensation circuit 02 can control the second compensation signal line V22 to be electrically connected to the reset power line Vinit when the potential of the second compensation control signal provided by the second compensation control line V12 is a first potential, so that the compensation signal provided by the second compensation signal line V22 is transmitted to the reset power line Vinit. Furthermore, the compensation circuit 02 can control the second compensation signal line V22 to be disconnected from the reset power line Vinit when the potential of the second compensation control signal provided by the second compensation control line V12 is a second potential.

[0113] Optionally, referring to FIG. 7 , it can be seen that the compensation circuit 02 may include:

[0114] The third switch sub-circuit 024 can be coupled to the first compensation control line V11, the first compensation signal line V21 and the reset power line Vinit respectively, and can be used to control the on and off of the first compensation signal line V21 and the reset power line Vinit based on the first compensation control signal.

[0115] For example, the third switch sub-circuit 024 can control the first compensation signal line V21 to be connected to the reset power line Vinit when the potential of the first compensation control signal is the first potential, and can control the first compensation signal line V21 to be disconnected from the reset power line Vinit when the potential of the first compensation control signal is the second potential.

[0116] The fourth switch sub-circuit 025 can be coupled to the second compensation control line V12, the second compensation signal line V22 and the reset power line Vinit respectively, and can be used to control the on and off of the second compensation signal line V22 and the reset power line Vinit based on the second compensation control signal.

[0117] For example, the fourth switch sub-circuit 025 can control the second compensation signal line V22 to be connected to the reset power line Vinit when the potential of the second compensation control signal is the first potential, and can control the second compensation signal line V22 to be disconnected from the reset power line Vinit when the potential of the second compensation control signal is the second potential.

[0118] Based on Figure 7 , Figure 8 shows a circuit structure diagram of another compensation circuit. Referring to Figure 8 , it can be seen that the third switch sub-circuit 024 may include: a third transistor T3 . The fourth switch sub-circuit 025 may include: a fourth transistor T4 .

[0119] The gate of the third transistor T3 may be coupled to the first compensation control line V11 , the first electrode of the third transistor T3 may be coupled to the first compensation signal line V21 , and the second electrode of the third transistor T3 may be coupled to the reset power line Vinit.

[0120] A gate of the fourth transistor T4 may be coupled to the second compensation control line V12 , a first electrode of the fourth transistor T4 may be coupled to the second compensation signal line V22 , and a second electrode of the fourth transistor T4 may be coupled to the reset power line Vinit.

[0121] It should be noted that the structure shown in FIG8 can be considered as a 2T (comprising two transistors) structure compensation circuit 02, wherein the third transistor T3 and the fourth transistor T4 can both be P-type transistors.

[0122] In the alternative implementation described above, the compensation signal provided by the second compensation signal line V22 can be the same as the compensation signal provided by the first compensation signal line V21; this can mean that the average potentials are the same. Thus, by flexibly controlling the compensation control signals provided by the first compensation control line V11 and the second compensation control line V12, the desired reset power signal (i.e., the first compensation signal) can be transmitted to the reset power line Vinit during the refresh period, and the desired reset power signal (i.e., the second compensation signal) can be transmitted to the reset power line Vinit during the porch period. This alternative implementation is similar to power switching.

[0123] For example, during the refresh period, the first compensation control line V11 can be controlled to provide a first compensation control signal with a first potential, and the second compensation control line V12 can be controlled to provide a second compensation control signal with a second potential, so that the third transistor T3 is turned on and the fourth transistor T4 is turned off, thereby allowing the compensation signal provided by the first compensation signal line V21 to be transmitted to the reset power line Vinit via the turned-on third transistor T3. During the Porch period, the second compensation control line V12 can be controlled to provide a second compensation control signal with a first potential, and the first compensation control line V11 can be controlled to provide a first compensation control signal with a second potential, so that the fourth transistor T4 is turned on and the third transistor T3 is turned off, thereby allowing the compensation signal provided by the second compensation signal line V22 to be transmitted to the reset power line Vinit via the turned-on fourth transistor T4, ensuring that the reset power signal provided during the Porch period is the same as the reset power signal provided during the refresh period.

[0124] As another optional implementation:

[0125] In some embodiments, the compensation signal provided by the second compensation signal line V22 can be different from the compensation signal provided by the first compensation signal line V21. For example, the second compensation signal line V22 can be a ground line GND. Based on this, and in conjunction with the structural schematic diagrams of another compensation circuit shown in Figures 7 and 9, it can be seen that the compensation circuit 02 described in the embodiment of the present disclosure can also include: a voltage divider sub-circuit 026 connected in series between the second compensation signal line V22 and the fourth switch sub-circuit 025, so that the voltage divider sub-circuit 026 effectively divides the voltage.

[0126] Based on Figure 9 and in combination with Figure 8, Figure 10 shows a circuit structure diagram of another compensation circuit. Referring to Figure 10, it can be seen that the voltage divider sub-circuit 026 may include: a voltage divider resistor R1.

[0127] Furthermore, the voltage-dividing resistor R1 may be connected in series between the second compensation signal line V22 and the first electrode of the fourth transistor T4 .

[0128] It should be noted that the structure shown in FIG10 can be considered as a compensation circuit 02 with a 2T1R (including 2 transistors and 1 resistor) structure.

[0129] For the aforementioned alternative implementation, its control method can be the same as that of the aforementioned alternative implementation. However, when the fourth transistor T4 is controlled to be on and the third transistor T3 is simultaneously controlled to be off, the reset power signal transmitted to the reset power line Vinit can be divided between the compensation signal provided by the first compensation signal line V21 and the signal provided by the ground line GND, thereby achieving the purpose of compensating the reset power signal. This alternative implementation is similar to voltage switching.

[0130] That is, in the embodiment of the present disclosure, equivalent RC compensation, power switching, or voltage compensation can be performed on the driving node N0 so that during the Porch period, the reset power signal provided by the reset power line Vinit is consistent with the reset power signal provided by the reset power line Vinit during the refresh period, thereby avoiding the problem of uneven display caused by the poor potential stability of the reset power signal. Of course, the above multiple implementation methods are only schematic illustrations. In some other embodiments, the compensation circuit 01 can also be designed to meet other structures, as long as the above compensation effect can be achieved.

[0131] Optionally, the transistors in the pixel circuit provided by the embodiments of the present disclosure may include: an active layer Act, a gate metal layer GT, and a source-drain metal layer SD stacked in sequence.

[0132] On this basis, taking the structure shown in Figure 6 as an example, Figure 11 shows a structural layout of a compensation circuit 02. Referring to Figure 11, it can be seen that the active layer Act of the transistor in the compensation circuit 02 can extend along the first direction X1. The compensation control line V1 and the compensation signal line V2 coupled to the compensation circuit 02 can both extend along the second direction X2, and the compensation control line V1 can be located in the same layer as the gate metal layer GT. The compensation signal line V2 can be located in the same layer as the source and drain metal layer SD. The compensation control line V1 can include an EM_dum signal line (i.e., a first compensation control line V11) for simulating the light emitting control line EM, and a Scan_dum signal line (i.e., a second compensation control line V12) for simulating the reset control line Scan.

[0133] FIG11 also illustrates a pull-down power line VSS, a capacitor C1, and a reset power line Vinit. The pull-down power line VSS can extend along a first direction X1 and be located on the same layer as the gate metal layer GT or the source / drain metal layer SD. The capacitor C1 can be located on the same layer as the gate metal layer GT. The reset power line Vinit can extend along a second direction X2 and be located on the same layer as the source / drain metal layer SD. FIG11 also illustrates that the active layer Act can be provided with multiple vias K0 to provide overlapping connections between upper and lower layers.

[0134] Optionally, in some embodiments, the gate metal layer GT may include three gate metal layers GT1, GT2, and GT3 stacked in sequence; the source / drain metal layer SD may include two source / drain metal layers SD1 and SD2 stacked in sequence. The first compensation control line V11 and the second compensation control line V12 may both be located on the same layer as the gate metal layer GT1. The compensation signal line V2 and the reset power line Vinit may both be located on the same layer as the source / drain metal layer SD1. The capacitor C1 may include gate metal layers GT1 and GT2. The pull-down power line VSS may be located on the same layer as the gate metal layer GT3 or the source / drain metal layer SD2.

[0135] The second direction X2 may intersect the first direction X1. For example, referring to Figure 11 , the second direction X2 is shown perpendicular to the first direction X1. Based on this, it can be seen that the compensation control line V1, the compensation signal line V2, and the reset power line Vinit can be arranged horizontally as shown in Figure 11 ; the pull-down power line VSS and the active layer Act can be arranged vertically as shown in Figure 11 . This, combined with the embodiment employing a relatively thin gate metal layer GT layout, shows that the disclosed embodiments can effectively reduce wiring area.

[0136] It should be noted that being located in the same layer may refer to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures, and / or parts located in the "same layer" are made of the same material and are formed through the same patterning process. In this way, the preparation process and preparation costs can be saved, and the preparation efficiency can be accelerated.

[0137] In summary, an embodiment of the present disclosure provides a pixel circuit. The pixel circuit includes a driving circuit and a compensation circuit. Among them, the driving circuit is capable of transmitting a reset power signal to the driving node to reset the light-emitting element coupled to the driving node; and is capable of transmitting a light-emitting driving signal to the driving node to drive the light-emitting element coupled to the driving node to emit light. The compensation circuit is capable of controlling the reset power line to provide the same reset power signal in any time period, that is, ensuring that the potential stability of the reset power signal transmitted to the driving node is better. In this way, even if the light-emitting element is charged and discharged multiple times within a frame, the light-emitting element can be reliably reset, avoiding the display abnormality of uneven screen splitting of the display panel, and ensuring a better display effect.

[0138] FIG12 is a flowchart of a pixel circuit driving method according to an embodiment of the present disclosure, which is applied to the pixel circuit described in the above embodiment. As shown in FIG12 , the method includes: a plurality of refresh periods executed sequentially, and a waiting period (i.e., a porch period) between each two adjacent refresh periods.

[0139] Wherein, referring to step 1201, during the refresh period and the waiting period, the compensation circuit controls the reset power line to provide the same reset power signal based on the compensation signal provided by the compensation signal line under the control of the compensation control signal provided by the compensation control line.

[0140] Referring to step 1202, during the refresh period, the driving circuit, under the control of the reset control signal provided by the reset control line, controls the reset power line and the driving node coupled to the light-emitting element to be first turned on and then disconnected, and after controlling the reset power line to be disconnected from the driving node, transmits a light-emitting driving signal to the driving node based on the driving control signal provided by the driving control line to drive the light-emitting element to emit light.

[0141] Of course, during the Porch period, the driving circuit can also control the reset power line and the driving node coupled to the light-emitting element to be turned on under the control of the reset control signal provided by the reset control line, so that the reset power line transmits the reset power signal to the driving node to achieve the reset of the driving node.

[0142] It should be noted that FIG12 only illustrates one method step and does not limit the order in which the steps are executed.

[0143] Optionally, with respect to an optional implementation shown in FIG5 and FIG6 , the compensation control line V1 includes: a first compensation control line V11 and a second compensation control line V12. The potential of the compensation signal can be determined based on the potential of the drive node when the light-emitting element emits light at a target grayscale. On this basis, the compensation circuit, under the control of the compensation control signal provided by the compensation control line, controls the reset power line to provide the same reset power signal based on the compensation signal provided by the compensation signal line. That is, the above-mentioned step 1201 may include:

[0144] A1. During the refresh period, the compensation circuit, under the control of a first compensation control signal provided by the first compensation control line and a second compensation control signal provided by the second compensation control line, controls the compensation signal line and the reset power line to be disconnected from the equivalent node of the driving node.

[0145] A2. In the waiting stage, the compensation circuit, under the control of the first compensation control signal and the second compensation control signal, controls the compensation signal line and the reset power line to be alternately turned on with the equivalent node, so as to control the reset power line to provide the same reset power signal during the refresh period and the waiting period.

[0146] Optionally, taking the structure shown in Figures 5 and 6, where the transistor is a P-type transistor, the first potential (i.e., the effective potential) is a low potential, and the second potential (i.e., the invalid potential) is a high potential as an example, Figure 13 shows a timing diagram of a compensation control signal.

[0147] Referring to FIG. 13 , it can be seen that during the refresh period, the first compensation control line V11 can be controlled to provide a high-voltage first compensation control signal, while the second compensation control line V12 can be controlled to provide a high-voltage second compensation control signal. Accordingly, the first transistor T1 and the second transistor T2 can both remain off, disconnecting the compensation signal line V2 and the reset power supply line Vinit from the equivalent node N1. During the Porch period, the first compensation control line V11 and the second compensation control line V12 can be controlled to alternately provide low-voltage compensation control signals. As shown in FIG. 13 , the second compensation control line V12 is first controlled to provide a low-voltage second compensation control signal while the first compensation control line V11 is controlled to provide a high-voltage first compensation control signal. Then, the first compensation control line V11 is controlled to provide a low-voltage first compensation control signal while the second compensation control line V12 is controlled to provide a high-voltage second compensation control signal, and so on. The time intervals of alternating on-state can be consistent with the phase difference between the adjacent reset control signals used to reset the drive node N0 in the drive circuit 01. For example, if scanning is performed line by line, the charging time for one line can be 1 hour; if every two lines are driven at the same time, the charging time for the two lines can be 2 hours, and so on, thereby achieving an equivalent charging and discharging process for the driving node N0, ensuring that the fluctuation of the reset power signal provided by the reset power line Vinit is the same during the refresh period and the Porch period, thereby eliminating the problem of uneven display caused by split screen.

[0148] Optionally, for another optional implementation shown in Figures 7 and 8 or another optional implementation shown in Figures 9 and 10, the compensation control line V1 may include: a first compensation control line V11 and a second compensation control line V12. The compensation signal line V2 may include: a first compensation signal line V21 and a second compensation signal line V22. Moreover, the compensation signal provided by the first compensation signal line V21 is the reset power signal provided by the reset power line Vinit during the refresh period, and the reset power signal provided by the reset power line Vinit is controlled based on the compensation signal provided by the second compensation signal line V22 to be the same as the compensation signal provided by the first compensation signal line V21. On this basis, the compensation circuit, under the control of the compensation control signal provided by the compensation control line, controls the reset power line to provide the same reset power signal based on the compensation signal provided by the compensation signal line, that is, the above-mentioned step 1201 may include:

[0149] B1. During the refresh period, the compensation circuit controls the first compensation signal line to be connected to the reset power line under the control of the first compensation control signal provided by the first compensation control line, and controls the second compensation signal line to be disconnected from the reset power line under the control of the second compensation control signal provided by the second compensation control line.

[0150] B2. During the waiting period, the compensation circuit controls the second compensation signal line to be connected to the reset power line under the control of the second compensation control signal, and controls the first compensation signal line to be disconnected from the reset power line under the control of the first compensation control signal.

[0151] Optionally, taking the structure shown in Figures 7 and 8 or the structure shown in Figures 9 and 10, the transistor is a P-type transistor, the first potential (i.e., the effective potential) is a low potential, and the second potential (i.e., the invalid potential) is a high potential as an example, Figure 14 shows another timing diagram of the compensation control signal.

[0152] Referring to Figure 14 , it can be seen that during the refresh period, the first compensation control line V11 can be controlled to provide a low-voltage first compensation control signal, while the second compensation control line V12 can be controlled to provide a high-voltage second compensation control signal. Accordingly, the third transistor T3 can be turned on, while the fourth transistor T4 can be turned off, allowing the compensation signal provided by the first compensation signal line V21 to be transmitted to the reset power line Vinit via the turned-on third transistor T3. During the Porch period, the second compensation control line V12 can be controlled to provide a low-voltage second compensation control signal, while the first compensation control line V11 can be controlled to provide a high-voltage first compensation control signal. Accordingly, the fourth transistor T4 can be turned on, while the third transistor T3 is turned off. Based on this, for the structures shown in Figures 7 and 8 , the compensation signal provided by the second compensation signal line V22 can be transmitted to the reset power line Vinit via the turned-on fourth transistor T4. For the structures shown in Figures 9 and 10 , the reset power signal provided by the reset power line Vinit can be divided between the compensation signal provided by the first compensation signal line V21 and the signal provided by the ground line GND. Ultimately, it is ensured that the reset power line Vinit is controlled to provide the same reset power signal during the refresh period and the Porch period, eliminating the problem of uneven display caused by split screen.

[0153] Since the driving method can have substantially the same technical effects as the pixel circuit described in the previous embodiment, the technical effects of the driving method will not be repeatedly described here for the purpose of brevity.

[0154] FIG15 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure. As shown in FIG15 , the display panel includes: a substrate 10 and pixels P1 located on the substrate 10 .

[0155] The pixel P1 includes a light emitting element L1 (not shown in FIG15 ) and a pixel circuit as described in the above embodiment. The pixel circuit is coupled to the light emitting element L1 and is used to drive the light emitting element L1 to emit light.

[0156] Alternatively, Figure 16 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure. Referring to Figure 16 , it can be seen that the substrate 10 may have a display area A1 and a non-display area B1 adjacent to each other. As shown in Figure 16 , the non-display area B1 surrounds the display area A1.

[0157] In conjunction with Figure 1 , the driver circuit 01 included in the pixel circuit can be located in the display area A1, and the compensation circuit 01 included in the pixel circuit can be located in the non-display area B1. For example, in some embodiments, referring to Figure 16 , the compensation circuit 02 can be located at the top, bottom, left, or right end of the display area A1. Multiple pixels P1 can share the same compensation circuit 02. This facilitates a narrow bezel design without compromising the resolution of the display area A1.

[0158] Since the display panel can have substantially the same technical effects as the pixel circuit described in the previous embodiment, the technical effects of the display panel will not be repeatedly described here for the purpose of brevity.

[0159] Fig. 17 is a schematic diagram of the structure of a display device provided by an embodiment of the present disclosure. As shown in Fig. 17, the display device includes: a power supply component J1 and a display panel M1 as described in the above embodiment.

[0160] The power supply component J1 is coupled to the display panel M1 and is used to supply power to the display panel M1.

[0161] Optionally, the display device may be any product or component having a display function, such as an organic light-emitting diode (OLED) display device, an active-matrix organic light-emitting diode (AMOLED) display device, or a liquid crystal display device.

[0162] AMOLED displays offer low power consumption, a wide operating temperature range, low cost, high contrast, wide viewing angles, a wide color gamut, and thin display panels, enabling flexible displays and are poised to become the next generation of display technology. OLED displays meet most of the high-performance and high-capacity requirements of today's information age. They can be used for indoor and outdoor lighting, decorative wallpaper, and foldable electronic newspapers. They can also be incorporated into portable electronic products such as mobile phones, tablets, and wearable electronics.

[0163] It should be noted that the terms used in the examples of this disclosure are only used to explain the examples and are not intended to limit the present disclosure. Unless otherwise defined, technical terms or scientific terms used in the embodiments of this disclosure should have the common meanings understood by people with ordinary skills in the field to which this disclosure belongs.

[0164] For example, the terms "first," "second," or "third," and similar terms used in the patent specification and claims of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. "Connected" or "coupled" refers to an electrical connection.

[0165] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0166] Words such as “include” or “comprising” mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0167] “Up,” “down,” “left,” or “right” are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0168] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A pixel circuit, comprising: A driving circuit is coupled to a driving control line, a reset control line, a reset power line and a driving node respectively, and is used to: transmit a light-emitting driving signal to the driving node based on a driving control signal provided by the driving control line; and control the connection and disconnection between the reset power line and the driving node under the control of a reset control signal provided by the reset control line; the driving node is used to couple with a light-emitting element; The compensation circuit is coupled to the compensation control line, the compensation signal line and the reset power line, respectively, and is used to: under the control of the compensation control signal provided by the compensation control line, based on the compensation signal provided by the compensation signal line, control the reset power line to provide the same reset power signal in any time period.

2. The pixel circuit according to claim 1, wherein: The compensation control line includes: a first compensation control line and a second compensation control line; the potential of the compensation signal provided by the compensation signal line is determined based on the potential of the driving node when the light-emitting element emits light at a target gray scale; The compensation circuit is also coupled to the equivalent node of the driving node and the pull-down power line coupled to the light-emitting element respectively; the compensation circuit is used to: control the on-off of the compensation signal line and the equivalent node based on the first compensation control signal provided by the first compensation control line, control the on-off of the reset power line and the equivalent node based on the second compensation control signal provided by the second compensation control line, and also adjust the potential of the equivalent node based on the pull-down power signal provided by the pull-down power line; The driving node is used to couple with the first electrode of the light emitting element, and the second electrode of the light emitting element is coupled with the pull-down power line.

3. The pixel circuit according to claim 2, wherein: The compensation circuit comprises: a first switch subcircuit, coupled to the first compensation control line, the compensation signal line and the equivalent node respectively, and used to control the on-off of the compensation signal line and the equivalent node based on the first compensation control signal; a second switch subcircuit, coupled to the second compensation control line, the equivalent node and the reset power line, respectively, and used to control the on / off of the reset power line and the equivalent node based on the second compensation control signal; A potential regulating subcircuit is coupled to the equivalent node and the pull-down power line respectively and is used to The pull-down power signal is used to adjust the potential of the equivalent node.

4. The pixel circuit according to claim 3, wherein: The first switch subcircuit includes: a first transistor; the second switch subcircuit includes: a second transistor; the potential adjustment subcircuit includes: a capacitor; Wherein, the gate of the first transistor is coupled to the first compensation control line, the first electrode of the first transistor is coupled to the compensation signal line, and the second electrode of the first transistor is coupled to the equivalent node; The gate of the second transistor is coupled to the second compensation control line, the first electrode of the second transistor is coupled to the reset power line, and the second electrode of the second transistor is coupled to the equivalent node; The capacitor is connected in series between the equivalent node and the pull-down line.

5. The pixel circuit according to claim 1, wherein: The compensation control line includes: a first compensation control line and a second compensation control line; the compensation signal line includes: a first compensation signal line and a second compensation signal line, the compensation signal provided by the first compensation signal line is the reset power signal provided by the reset power line during a refresh period, and the reset power signal provided by the reset power line is controlled to be the same as the compensation signal provided by the first compensation signal line based on the compensation signal provided by the second compensation signal line; The compensation circuit is used to: control the on-off of the first compensation signal line and the reset power line based on the first compensation control signal provided by the first compensation control line, and control the on-off of the second compensation signal line and the reset power line based on the second compensation control signal provided by the second compensation control line.

6. The pixel circuit according to claim 5, wherein: The compensation circuit comprises: a third switch sub-circuit, coupled to the first compensation control line, the first compensation signal line and the reset power line respectively, and used for controlling the on / off of the first compensation signal line and the reset power line based on the first compensation control signal; The fourth switch sub-circuit is coupled to the second compensation control line, the second compensation signal line and the reset power line respectively, and is used to control the on-off of the second compensation signal line and the reset power line based on the second compensation control signal.

7. The pixel circuit according to claim 6, wherein: The compensation signal provided by the second compensation signal line is the same as the compensation signal provided by the first compensation signal line; Alternatively, the compensation signal provided by the second compensation signal line is different from the compensation signal provided by the first compensation signal line, and the compensation circuit further includes: a voltage divider subcircuit connected in series between the second compensation signal line and the fourth switch subcircuit.

8. The pixel circuit according to claim 7, wherein: The third switch subcircuit includes: a third transistor; the fourth switch subcircuit includes: a fourth transistor; the voltage divider subcircuit includes: a voltage divider resistor; The gate of the third transistor is coupled to the first compensation control line, the first electrode of the third transistor is coupled to the first compensation signal line, and the second electrode of the third transistor is coupled to the reset power line; The gate of the fourth transistor is coupled to the second compensation control line, the first electrode of the fourth transistor is coupled to the second compensation signal line, and the second electrode of the fourth transistor is coupled to the reset power line; The voltage-dividing resistor is connected in series between the second compensation signal line and the first electrode of the fourth transistor.

9. The pixel circuit according to any one of claims 1 to 8, wherein: The transistors in the pixel circuit all include: an active layer, a gate metal layer and a source-drain metal layer stacked in sequence; Among them, the active layer of the transistor in the compensation circuit extends along the first direction; the compensation control line and the compensation signal line coupled to the compensation circuit both extend along the second direction, and the compensation control line and the gate metal layer are located in the same layer; the compensation signal line and the source and drain metal layer are located in the same layer; the second direction intersects with the first direction.

10. A method for driving a pixel circuit, applied to the pixel circuit according to any one of claims 1 to 9; the method comprising: A plurality of refresh periods executed sequentially, and a waiting period between each two adjacent refresh periods; During the refresh period and the waiting period, the compensation circuit controls the reset power line to provide the same reset power signal based on the compensation signal provided by the compensation signal line under the control of the compensation control signal provided by the compensation control line; During the refresh period, the driving circuit, under the control of the reset control signal provided by the reset control line, controls the reset power line and the driving node coupled to the light-emitting element to be first turned on and then disconnected, and after controlling the reset power line to be disconnected from the driving node, transmits a light-emitting driving signal to the driving node based on the driving control signal provided by the driving control line to drive the light-emitting element to emit light.

11. The method according to claim 10, wherein: The compensation control line includes: a first compensation control line and a second compensation control line; the potential of the compensation signal is determined based on the potential of the driving node when the light-emitting element emits light at a target gray scale; The compensation circuit controls the reset power line to provide the same reset power signal based on the compensation signal provided by the compensation signal line under the control of the compensation control signal provided by the compensation control line, including: During the refresh period, the compensation circuit controls the compensation signal line and the reset power line to be decoupled from the equivalent node of the driving node under the control of a first compensation control signal provided by the first compensation control line and a second compensation control signal provided by the second compensation control line; In the waiting stage, the compensation circuit, under the control of the first compensation control signal and the second compensation control signal, controls the compensation signal line and the reset power line to be alternately turned on with the equivalent node, so as to control the reset power line to provide the same reset power signal during both the refresh period and the waiting period.

12. The method according to claim 10, wherein: The compensation control line includes: a first compensation control line and a second compensation control line; the compensation signal line includes: a first compensation signal line and a second compensation signal line, the compensation signal provided by the first compensation signal line is the reset power signal provided by the reset power line during a refresh period, and the reset power signal provided by the reset power line is controlled to be the same as the compensation signal provided by the first compensation signal line based on the compensation signal provided by the second compensation signal line; The compensation circuit controls the reset power line to provide the same reset power signal based on the compensation signal provided by the compensation signal line under the control of the compensation control signal provided by the compensation control line, including: During the refresh period, the compensation circuit controls the first compensation signal line to be connected to the reset power line under the control of a first compensation control signal provided by the first compensation control line, and controls the second compensation signal line to be disconnected from the reset power line under the control of a second compensation control signal provided by the second compensation control line; During the waiting period, the compensation circuit is controlled by the second compensation control signal to The second compensation signal line is connected to the reset power line, and under the control of the first compensation control signal, the first compensation signal line is controlled to be disconnected from the reset power line.

13. A display panel, comprising: A substrate, and pixels located on the substrate; Wherein, the pixel comprises: a light-emitting element, and a pixel circuit as described in any one of claims 1 to 9; the pixel circuit is coupled to the light-emitting element and is used to drive the light-emitting element to emit light.

14. The display panel according to claim 13, wherein: The substrate has a display area and a non-display area adjacent to each other; The driving circuit included in the pixel circuit is located in the display area, and the compensation circuit included in the pixel circuit is located in the non-display area.

15. A display device, comprising: A power supply component, and a display panel as claimed in claim 13 or 14; Wherein, the power supply component is coupled to the display panel and is used to supply power to the display panel.

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