Display substrate and display apparatus

Abstract

The present disclosure provides a display substrate and a display apparatus. In the display substrate, a peripheral region comprises a first frame area and a second frame area. A display region is located between the first frame area and the second frame area, the display region comprises a first display area and a second display area, the first display area comprises a first sub-area and a second sub-area, and at least part of the second sub-area and the second display area are located in a same row in a first direction. At least part of a first target scanning line in the display substrate is located in the second sub-area. In the first target scanning line, a first end of a first scanning layer is coupled to a first end of a second scanning layer and is coupled to a corresponding first scanning drive unit, a second end of the first scanning layer is coupled to a second end of the second scanning layer, the first ends are close to the first frame area, and the second ends are close to the second frame area.

Description

Display substrate and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202311243257.5 filed in China on September 25, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0004] Low-temperature polycrystalline oxide (LTPO) transistors are highly favored for their low power consumption and excellent image retention. However, due to their poor illumination performance, top and bottom gates are typically required during LTPO transistor design to ensure device stability under illumination.

[0005] With the continuous advancement of display technology, narrow bezels have become a mainstream trend in display product development. This trend has led to widespread adoption of single-sided drive technology using GOA (Gate On Array). Display products using this drive technology place higher demands on the design of the device's top and bottom gates, using a double layer of scan lines to provide scanning signals for these two gates. However, current display products compatible with GOA single-sided drive technology and LTPO transistors suffer from defects such as display distortion and hole mura.

[0006] Summary of the Invention

[0007] An object of the present disclosure is to provide a display substrate and a display device.

[0008] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0009] A first aspect of the present disclosure provides a display substrate, comprising: a display area and a peripheral area located around the display area; the peripheral area comprising a first frame area and a second frame area disposed opposite each other along a first direction; the display area being located between the first frame area and the second frame area, the display area comprising a first display area and a second display area, the first display area comprising a first sub-area and a second sub-area, at least a portion of the second sub-area being located in the same row as the second display area along the first direction, and the first sub-area and the second display area being located in different rows along the first direction;

[0010] The display substrate further includes: a plurality of first scan driving units and a plurality of first scan lines; the first scan driving units are located in the first frame area; the first scan lines include a first scan layer and a second scan layer;

[0011] The multiple first scan lines include multiple first target scan lines, at least part of the first target scan lines are located in the second sub-area, in the first target scan lines, the first end of the first scanning layer and the first end of the second scanning layer are coupled, and are coupled to the corresponding first scan driving unit, the second end of the first scanning layer and the second end of the second scanning layer are coupled, the first end is located in the first border area, and the second end is located in the second border area.

[0012] Optionally, the multiple first scan lines include multiple second target scan lines, at least part of the second target scan lines are located in the first sub-area, and in the second target scan lines, the first end of the first scanning layer and the first end of the second scanning layer are coupled and coupled to the corresponding first scanning drive unit, the second end of the first scanning layer and the second end of the second scanning layer are coupled, the first end is located in the first border area, and the second end is located in the second border area.

[0013] Optionally, in the first target scan line, the first scanning layer includes a first scanning pattern and a second scanning pattern, and the second scanning layer includes a third scanning pattern and a fourth scanning pattern; the second display area is located between the first scanning pattern and the second scanning pattern, and the second display area is located between the third scanning pattern and the fourth scanning pattern;

[0014] The first end of the first scanning pattern serves as the first end of the first scanning layer, the second end of the second scanning pattern serves as the second end of the first scanning layer, the first end of the third scanning pattern serves as the first end of the second scanning layer, and the second end of the fourth scanning pattern serves as the second end of the second scanning layer; the second end of the first scanning pattern is coupled to the second end of the third scanning pattern, and the first end of the second scanning pattern is coupled to the first end of the fourth scanning pattern.

[0015] Optionally, the first target scan line also includes a winding portion, which is located in the second sub-area, and at least part of the winding portion is arranged around the second display area; the winding portion is respectively coupled to the second end of the first scanning graphic, the first end of the second scanning graphic, the second end of the third scanning graphic and the first end of the fourth scanning graphic.

[0016] Optionally, the winding portions to which adjacent first scanning patterns are coupled are independent of each other; or, the winding portions to which adjacent first scanning patterns are coupled are the same.

[0017] Optionally, the multiple first scanning lines are divided into multiple scanning groups, each scanning group including two adjacent first scanning lines; the display substrate includes multiple first transfer parts, and the first transfer parts are respectively coupled to the first end of each first scanning layer, the first end of each second scanning layer, and the corresponding first scanning driving unit in the corresponding scanning group.

[0018] Optionally, the display substrate includes a plurality of third transition portions; the third transition portions are respectively coupled to the second end of the first scanning layer and the second end of the second scanning layer in the corresponding first scanning lines.

[0019] Optionally, in the scanning group, the third transfer portions coupled to the first scanning lines are coupled to each other.

[0020] Optionally, the display substrate includes a first gate metal layer, a second gate metal layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer stacked in sequence on the base substrate in a direction away from the display substrate;

[0021] At least a portion of the first transfer portion is provided in the same layer and material as the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source-drain metal layer, or the second source-drain metal layer;

[0022] At least a portion of the third transfer portion is provided in the same layer and made of the same material as the first gate metal layer, the second gate metal layer, the first source-drain metal layer, or the second source-drain metal layer.

[0023] Optionally, the longer the length of the winding portion is, the smaller the load of the third transition portion is.

[0024] Optionally, in the same first scanning line, an orthographic projection of the first end of the first scanning layer on the base substrate of the display substrate and an orthographic projection of the first end of the second scanning layer on the base substrate have an overlapping area, and the first end of the first scanning layer and the first end of the second scanning layer are coupled through a via hole in the overlapping area; and / or,

[0025] In the same first scanning line, the orthographic projection of the second end of the first scanning layer on the base substrate has an overlapping area with the orthographic projection of the second end of the second scanning layer on the base substrate, and the first end of the first scanning layer and the first end of the second scanning layer are coupled through a via in the overlapping area.

[0026] Optionally, the display substrate includes a plurality of sub-pixels, the sub-pixels include a sub-pixel driving circuit, the sub-pixel driving circuit includes a driving transistor and a compensation transistor, the gate of the compensation transistor is respectively coupled to the first scanning layer and the second scanning layer in the corresponding first scanning line, the first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor.

[0027] Optionally, the display substrate includes a first gate metal layer, a second gate metal layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer stacked in sequence on the base substrate in a direction away from the display substrate;

[0028] The winding portion is provided in the same layer and made of the same material as the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source-drain metal layer or the second source-drain metal layer.

[0029] Optionally, the winding parts of two adjacent first target scanning lines are arranged in the same layer or in different layers.

[0030] Optionally, the display substrate further includes a plurality of second scan lines, a plurality of light emitting control signal lines, a plurality of first reset signal lines, and a plurality of second reset signal lines;

[0031] The orthographic projection of the winding portion on the base substrate of the display substrate at least partially overlaps with the orthographic projection of at least one signal line among the second scanning line, the light-emitting control signal line, the first reset signal line and the second reset signal line on the base substrate; the at least one signal line is arranged in a different layer from the winding portion.

[0032] Optionally, the display substrate includes a plurality of sub-pixels, and the sub-pixels include sub-pixel driving circuits;

[0033] The first scanning layer and the second scanning layer belonging to the same first target scanning line are coupled via at least one fourth transition portion.

[0034] Optionally, at least a portion of the fourth transition portion is located within a layout area of ​​the sub-pixel driving circuit, or at least a portion of the fourth transition portion is located between layout areas of adjacent sub-pixel driving circuits.

[0035] Optionally, the first scan line includes at least two fourth transition portions, at least one of the fourth transition portions is located between the first frame area and the second display area, and at least one of the fourth transition portions is located between the second frame area and the second display area.

[0036] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present disclosure provides a display device including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0038] FIG1 is a schematic diagram of a circuit structure of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0039] FIG2 is a schematic cross-sectional view of each film layer in a display substrate provided by an embodiment of the present disclosure;

[0040] FIG3 is a schematic diagram of a first layout of a display substrate provided by an embodiment of the present disclosure;

[0041] FIG4 is a schematic diagram of a layout of a first scan line entering a first display area in a first frame area according to an embodiment of the present disclosure;

[0042] FIG5 is a schematic diagram of a first layout of a winding portion of a first scan line provided by an embodiment of the present disclosure;

[0043] FIG6 is a schematic diagram showing the distribution of various areas in a display area according to an embodiment of the present disclosure;

[0044] FIG7 is a schematic diagram of a layout of a first scan line entering a second border area from a first display area according to an embodiment of the present disclosure;

[0045] FIG8 is a schematic diagram of a second layout of the winding portion of the first scan line provided by an embodiment of the present disclosure;

[0046] FIG9 is an enlarged schematic diagram of the winding portion of the first scanning line corresponding to the position of FIG8;

[0047] FIG10 is an enlarged schematic diagram of a winding portion of the first scanning line corresponding to a position symmetrical to that of FIG8 ;

[0048] FIG11 is a schematic diagram of the overall winding of a first scanning line provided by an embodiment of the present disclosure;

[0049] FIG12 is a schematic diagram of a second layout of a display substrate provided in an embodiment of the present disclosure;

[0050] FIG13 is a schematic diagram of a third layout of a display substrate provided in an embodiment of the present disclosure;

[0051] FIG14 is a schematic diagram showing the layout of the first scan line in the second sub-area according to an embodiment of the present disclosure;

[0052] FIG15 is a schematic diagram of a fourth layout of a display substrate provided in an embodiment of the present disclosure; DETAILED DESCRIPTION

[0053] In order to further illustrate the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0054] As shown in Figure 1, the present disclosure provides a display substrate, which includes a plurality of sub-pixels, and the sub-pixels include sub-pixel driving circuits; the display substrate also includes a plurality of power lines VDD, a plurality of light-emitting control signal lines EM, a plurality of first scanning lines GA1, a plurality of second scanning lines GA2, a plurality of first reset signal lines Rst1, a plurality of second reset signal lines Rst2, a plurality of first initialization signal lines Vinit1, a plurality of second initialization signal lines Vinit2, a plurality of third initialization signal lines Vinit3, and a plurality of data lines DA.

[0055] Exemplarily, the sub-pixel driving circuit adopts an 8T1C (ie, 8 transistors and 1 storage capacitor) circuit structure.

[0056] As shown in FIG1 , exemplarily, the sub-pixel driving circuit includes a first reset transistor T1 , a compensation transistor T2 , a driving transistor T3 , a data writing transistor T4 , a second reset transistor T7 , a power control transistor T5 , a light emitting control transistor T6 , a node control transistor T8 and a storage capacitor Cst.

[0057] The gate of the first reset transistor T1 is coupled to the corresponding first reset signal line Rst1, the first electrode of the first reset transistor T1 is coupled to the corresponding first initialization signal line Vinit1, and the second electrode of the first reset transistor T1 is coupled to the second electrode of the driving transistor T3 (i.e., the N3 node).

[0058] The gate of the compensation transistor T2 is coupled to the corresponding first scan line GA1 , the first electrode of the compensation transistor T2 is coupled to the second electrode of the driving transistor T3 , and the second electrode of the compensation transistor T2 is coupled to the gate of the driving transistor T3 (ie, the N1 node).

[0059] The gate of the data writing transistor T4 is coupled to the corresponding second scanning line GA2, the first electrode of the data writing transistor T4 is coupled to the corresponding data line DA, and the second electrode of the data writing transistor T4 is coupled to the first electrode of the driving transistor T3 (ie, the N2 node).

[0060] The gate of the power control transistor T5 is coupled to the corresponding light emitting control signal line EM, the first electrode of the power control transistor T5 is coupled to the corresponding power line VDD, and the second electrode of the power control transistor T5 is coupled to the first electrode of the driving transistor T3.

[0061] The gate of the light-emitting control transistor T6 is coupled to the corresponding light-emitting control signal line EM, the first electrode of the light-emitting control transistor T6 is coupled to the second electrode of the driving transistor T3, the second electrode of the light-emitting control transistor T6 is coupled to the anode of the corresponding light-emitting element (i.e., the N4 node), and the cathode of the light-emitting element receives the negative power supply signal VSS.

[0062] The gate of the second reset transistor T7 is coupled to the corresponding second reset signal line Rst2, the first electrode of the second reset transistor T7 is coupled to the corresponding second initialization signal line Vinit2, and the second electrode of the second reset transistor T7 is coupled to the corresponding anode of the light emitting element.

[0063] The gate of the node control transistor T8 is coupled to the corresponding second reset signal line Rst2 , the first electrode of the node control transistor T8 is coupled to the corresponding third initialization signal line Vinit3 , and the second electrode of the node control transistor T8 is coupled to the first electrode of the driving transistor T3 .

[0064] A first plate of the storage capacitor Cst is coupled to the gate of the driving transistor T3 , and a second plate of the storage capacitor Cst is coupled to the corresponding power line VDD.

[0065] Exemplarily, the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the power control transistor T5, the light emission control transistor T6, the second reset transistor T7, and the node control transistor T8 are all LTPS transistors, and the compensation transistor T2 is an LTPO transistor.

[0066] Exemplarily, the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are distributed in an array. The plurality of sub-pixel driving circuits are divided into a plurality of rows of sub-pixel driving circuits and a plurality of columns of sub-pixel driving circuits. The plurality of rows of sub-pixel driving circuits are arranged along a second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction. The plurality of columns of sub-pixel driving circuits are arranged along a first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. Exemplarily, the first direction and the second direction intersect. For example, the first direction includes a transverse direction, and the second direction includes a longitudinal direction.

[0067] Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to an anode of the light-emitting element and is configured to provide a driving signal to the light-emitting element to drive the light-emitting element to emit light.

[0068] Exemplarily, the multiple rows of sub-pixel driving circuits are divided into multiple groups of driving circuit rows, each group of driving circuit rows includes two adjacent rows of sub-pixel driving circuits, and the two adjacent rows of sub-pixel driving circuits include one row of odd-numbered sub-pixel driving circuits and one row of even-numbered sub-pixel driving circuits.

[0069] The display substrate further includes a plurality of gate driving circuits, which include a first scan driving circuit, a second scan driving circuit, a first reset driving circuit, a second reset driving circuit and a light emitting control driving circuit.

[0070] As shown in FIG3 , the first scan driving circuit includes a plurality of first scan driving units GA1GOA. The second scan driving circuit includes a plurality of second scan driving units GA2GOA. The first reset driving circuit includes a plurality of first reset driving units Rst1GOA. The second reset driving circuit includes a plurality of second reset driving units Rst2GOA. The light emission control driving circuit includes a plurality of light emission control driving units EM GOA.

[0071] Exemplarily, the first scan driving circuit is located in a first border region of the display substrate. The plurality of first scan driving units GA1GOA correspond one-to-one to a plurality of groups of driving circuit rows, and the first scan driving unit GA1GOA is respectively coupled to two first scan lines GA1 coupled to two rows of sub-pixel driving circuits in a corresponding group of driving circuit rows.

[0072] Exemplarily, the second scan drive circuit is located in the first border area and the second border area of ​​the display substrate. The second scan drive circuit located in the first border area includes a plurality of second scan drive units GA2GOA. The second scan drive circuit located in the second border area includes a plurality of second scan drive units GA2GOA. The first end of the second scan line coupled to each row of sub-pixel drive circuits is coupled to the corresponding second scan drive unit GA2GOA located in the first border area. The second end of the second scan line coupled to each row of sub-pixel drive circuits is coupled to the corresponding second scan drive unit GA2GOA located in the second border area.

[0073] Exemplarily, the first reset drive circuit is located in a first border region of the display substrate. The plurality of first reset drive units Rst1GOA correspond one-to-one to the plurality of drive circuit rows. The first reset drive unit Rst1GOA is respectively coupled to two first reset signal lines Rst1 coupled to two rows of sub-pixel drive circuits in a corresponding group of drive circuit rows. The two first reset signal lines Rst1 coupled to the two rows of sub-pixel drive circuits in a group of drive circuit rows may be coupled or uncoupled at their ends away from the first reset drive unit Rst1GOA.

[0074] Exemplarily, the second reset drive circuit is located in the second border region of the display substrate. The plurality of second reset drive units Rst2GOA correspond one-to-one to the plurality of drive circuit rows, and the second reset drive unit Rst2GOA is respectively coupled to two second reset signal lines Rst2 coupled to two rows of sub-pixel drive circuits in a corresponding group of drive circuit rows. The two second reset signal lines Rst2 coupled to the two rows of sub-pixel drive circuits in a group of drive circuit rows may be coupled or uncoupled at their ends away from the second reset drive unit Rst2GOA.

[0075] Exemplarily, the light emission control driving circuit is located in the second border region of the display substrate. The plurality of light emission control driving units EM GOA correspond one-to-one to the plurality of groups of driving circuit rows, and the light emission control driving units EM GOA are respectively coupled to two light emission control signal lines EM coupled to two rows of sub-pixel driving circuits in a corresponding group of driving circuit rows. The two light emission control signal lines EM coupled to the two rows of sub-pixel driving circuits in a group of driving circuit rows may be coupled or uncoupled at the ends away from the light emission control driving units EM GOA.

[0076] As shown in Figures 4 and 6 , the display substrate exemplarily includes a display area 10 and a peripheral area 20 located around the display area 10. The display area includes a first display region 101 and a second display region 102, with the first display region at least partially surrounding the second display region. The second display region, also known as the aperture region, can be used for, but is not limited to, placing cameras, sensors, and the like. The second display region is not used for display, but dummy sub-pixels can be fabricated within it to ensure uniformity of the display substrate.

[0077] As shown in FIG6 , the first display area 101 includes a first sub-area 1011 and a second sub-area 1012 , at least a portion of the second sub-area 1012 and the second display area 102 are located in the same row along the first direction, and the first sub-area 1011 and the second display area 1012 are located in different rows along the first direction.

[0078] As shown in FIG2 , the display substrate exemplarily includes a buffer layer BF, a polysilicon active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, a third gate insulating layer GI3, an oxide active layer ACT, a fourth gate insulating layer GI4, a third gate metal layer gate3, an interlayer insulating layer ILD, a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, a second planarization layer PLN2, an anode layer ANO, a pixel defining layer PDL, a light-emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2. A passivation layer PVX may also be provided on the display substrate as needed. The passivation layer PVX may be located between the first source / drain metal layer SD1 and the first planarization layer PLN1, or between the first planarization layer PLN1 and the second source / drain metal layer SD2.

[0079] Exemplarily, the first scanning line includes a first scanning layer and a second scanning layer, the first scanning layer and the second gate metal layer are provided in the same layer and the same material, and the second scanning layer and the third gate metal layer are provided in the same layer and the same material.

[0080] As shown in Figure 4 , the output end OUT of the first scan drive unit GA1GOA is bifurcated before entering the display area 10 from the peripheral area 20. Each end is then coupled to a first scan line GA1 connected to a corresponding row of sub-pixel drive circuits via a first adapter 31 made of a first source / drain metal layer. The first scan line GA1 includes a first scanning layer GA11 and a second scanning layer GA12, and the first adapter 31 is coupled to the corresponding first scanning layer GA11 and second scanning layer GA12, respectively. It should be noted that the black dots in Figure 4 represent vias.

[0081] As shown in Figures 5 and 6 , near the second display area 102, in the second sub-area 1012, one end of the first scanning layer GA11 included in the first scanning line GA1 is coupled to one end of the second scanning layer GA22. Furthermore, two first scanning lines GA1 coupled to two rows of sub-pixel driving circuits in the same group of driving circuit rows are coupled together via a second adapter 32. To narrow the border width of the second display area 102, the two first scanning lines GA1 coupled to two rows of sub-pixel driving circuits in the same group of driving circuit rows are coupled together via the second adapter 32 and then bypass the second display area 102 via a winding portion 40. It should be noted that the black dots in Figure 5 represent vias.

[0082] As shown in FIG3 , in the display substrate of the above structure, in the first scanning layer GA11 and the second scanning layer GA12 belonging to the same first scanning line GA1, an end of the first scanning layer GA11 close to the second border area and an end of the second scanning layer GA12 close to the second border area are independent of each other, such as parts A1 and A2 in FIG3 .

[0083] The above display substrate, when compatible with GOA unilateral drive technology and LTPO transistors, has problems such as abnormal display and hole mura. The specific analysis is as follows:

[0084] As shown in Figures 3 to 6, the display substrate adopts the following structure: the display substrate adopts GOA unilateral driving technology, and at the end of the first scanning line GA1 away from the first scanning driving unit GA1GOA, the end of the first scanning layer GA11 and the end of the second scanning layer GA12 are independent of each other; in the second sub-area 1012, before winding in the first display area 101, one end of the first scanning layer GA11 included in the first scanning line GA1 is coupled to one end of the second scanning layer GA22, and the two first scanning lines GA1 coupled to the two rows of sub-pixel driving circuits in the same group of driving circuit rows are coupled through the second adapter 32, and after coupling, they bypass the second display area 102 through a winding portion.

[0085] On the one hand: for the display substrate of the above structure, when the second scanning line GA2 controls the data writing transistor T4 to be turned on, and the data signal transmitted by the data line DA is sequentially written into the N2 node, the N3 node and the N1 node, the potential of the first scanning signal transmitted on the first scanning layer GA11 and the second scanning layer GA12 is pulled up by the parasitic capacitance formed by the N1 node, the N2 node and the N3 node, and the potential increase amplitude of the first scanning signal transmitted by the first scanning layer GA11 and the second scanning layer GA12 is different, and this increase will slowly recover during the writing of the data signal.

[0086] In the second sub-area 1012, near the second display area 102, since the first scanning layer GA11 and the second scanning layer GA12 are coupled, and two adjacent first scanning lines GA1 are bypassed around the second display area 102 through the same winding portion, this arrangement will cause the potential increase amplitude of the first scanning signal transmitted by the first scanning layer GA11 and the second scanning layer GA12 to be averaged near the second display area 102.

[0087] In the first display area 101, except for the area near the second display area 102, the first scanning layer GA11 and the second scanning layer GA12 are short-circuited at their ends before entering the first display area 101 from the peripheral area 20. The end of the first scanning layer GA11 and the end of the second scanning layer GA12 near the second side frame are independent of each other. As a result, in the first sub-area 1011 and the second sub-area 1012, the potential increase amplitudes of the first scanning signals transmitted by the first scanning layer GA11 and the second scanning layer GA12 are different, and the recovery is also slower. This causes the compensation transistor T2 to receive different first scanning signals in the first sub-area 1011 and the second sub-area 1012, resulting in different states of the compensation transistor T2 and ultimately causing differences in the N1 node.

[0088] More specifically, at the moment the data write transistor T4 on the second scan line GA2 is turned off, the potential of the first scan signal transmitted on the first scan layer GA11 and the second scan layer GA12 is momentarily pulled up due to the coupling effect of nodes N1, N2, and N3, and then restored to the target potential. During this process, the parasitic capacitance formed between the first scan line GA1 and the N1 node, as well as the gate-source capacitance Cgs of the compensation transistor T2, releases charge to the N1 node, resulting in a difference in the N1 node position, and thus a brightness difference between the first sub-area 1011 and the second sub-area 1012 of the display substrate.

[0089] On the other hand, when the data signal transmitted by the data line DA experiences a large jump, at the moment when the second scan line GA2 controls the data write transistor T4 to turn on, the potential of the first scan signal transmitted on the first scan layer GA11 and the second scan layer GA12 is pulled up due to the coupling effect of the N1 node, the N2 node, and the N3 node. Different data signals are pulled up to different degrees. After the second scan line GA2 controls the data write transistor T4 to turn off, the first scan signal transmitted on the first scan layer GA11 and the second scan layer GA12 returns to the target potential. In this process, the parasitic capacitance formed between the first scan line GA1 and the N1 node, as well as the gate-source capacitance Cgs of the compensation transistor T2, releases charge to the N1 node, resulting in a difference in the N1 point position and ultimately the crosstalk phenomenon.

[0090] Therefore, when the display products with the above structure are compatible with GOA unilateral driving technology and LTPO technology, there are problems such as abnormal display and Hole Mura.

[0091] Referring to Figures 4, 6, and 7, an embodiment of the present disclosure provides a display substrate, comprising: a display area 10 and a peripheral area 20 located around the display area 10; the peripheral area 20 includes a first border area 201 and a second border area 202 arranged opposite to each other along a first direction; the display area 10 is located between the first border area 201 and the second border area 202, the display area 10 includes a first display area 101 and a second display area 102, the first display area 101 includes a first sub-area 1011 and a second sub-area 1012, at least a portion of the second sub-area 1012 is located in the same row as the second display area 102 along the first direction, and the first sub-area 1011 and the second display area 102 are located in different rows along the first direction;

[0092] The display substrate further includes: a plurality of first scan driving units GA1GOA and a plurality of first scan lines GA1; the first scan driving units GA1GOA are located in the first frame area 201; the first scan lines GA1 include a first scan layer GA11 and a second scan layer GA12;

[0093] The multiple first scan lines GA1 include multiple first target scan lines, at least part of the first target scan lines are located in the second sub-area 1012, in the first target scan lines, the first end of the first scanning layer GA11 and the first end of the second scanning layer GA12 are coupled, and are coupled to the corresponding first scan driving unit GA1GOA, the second end of the first scanning layer GA11 and the second end of the second scanning layer GA12 are coupled, the first end is close to the first border area 201, and the second end is close to the second border area 202.

[0094] Exemplarily, the first display area 101 surrounds the second display area 102 .

[0095] Exemplarily, the second sub-region 1012 includes an area for arranging sub-pixels and also includes an area for arranging winding parts.

[0096] Exemplarily, a portion of the second sub-area 1012 is located in the same row as the second display area 102 along the first direction. Another portion of the second sub-area 1012 is arranged along the second direction with the second display area 102. The another portion of the second sub-area 1012 is provided on both sides of the second display area 102 along the second direction.

[0097] Exemplarily, in some embodiments, the display substrate includes a plurality of sub-pixels, the sub-pixels include a sub-pixel driving circuit, the sub-pixel driving circuit includes a driving transistor T3 and a compensation transistor T2, the gate of the compensation transistor T2 is respectively coupled to the first scanning layer GA11 and the second scanning layer GA12 in the corresponding first scanning line GA1, the first electrode of the compensation transistor T2 is coupled to the second electrode of the driving transistor T3, and the second electrode of the compensation transistor T2 is coupled to the gate of the driving transistor T3.

[0098] According to the specific structure of the above-mentioned display substrate, in the display substrate provided by the embodiment of the present disclosure, the multiple first scan lines GA1 are provided, including multiple first target scan lines, at least part of the first target scan lines are located in the second sub-area 1012, and in the first target scan lines, the first end of the first scanning layer GA11 and the first end of the second scanning layer GA12 are coupled, and are coupled to the corresponding first scan driving unit GA1GOA, the second end of the first scanning layer GA11 and the second end of the second scanning layer GA12 are coupled, the first end is located in the first border area 201, and the second end is located in the second border area 202.

[0099] The above-mentioned setting method enables the first target scanning line located in the second sub-area 1012 to couple the first end of the first scanning layer GA11 and the first end of the second scanning layer GA12 in the first border area 201, and couple the second end of the first scanning layer GA11 and the second end of the second scanning layer GA12 in the second border area 202. In this way, the differential charges accumulated by the first target scanning line due to the different structures can be better averaged, thereby effectively reducing the amplitude of the first scanning signal transmitted by the first target scanning line that is pulled up due to the influence of the change of the second scanning signal transmitted by the second scanning line GA2, realizing the rapid release of charges, and achieving the purpose of quickly restoring the first scanning signal transmitted by the first target scanning line to the target potential, thereby reducing the impact on the N1 node, improving the crosstalk phenomenon, and improving the brightness difference between the first sub-area 1011 and the second sub-area 1012 of the display substrate.

[0100] Therefore, when the display substrate of the above structure is compatible with GOA unilateral driving technology and LTPO technology, there are problems such as abnormal display and Hole Mura.

[0101] As shown in Figures 4 and 7, in some embodiments, the multiple first scan lines GA1 include multiple second target scan lines, at least part of the second target scan lines are located in the first sub-area 1011, and in the second target scan lines, the first end of the first scanning layer GA11 and the first end of the second scanning layer GA12 are coupled, and are coupled to the corresponding first scan driving unit GA1GOA, the second end of the first scanning layer GA11 and the second end of the second scanning layer GA12 are coupled, the first end is located in the first border area 201, and the second end is located in the second border area 202.

[0102] Exemplarily, the first target scan line is located in the first sub-area 1011 , the second target scan line is located in the second sub-area 1012 , and the first target scan line does not include a winding portion.

[0103] The above-mentioned setting method enables the second target scanning line located in the first sub-area 1011 to couple the first end of the first scanning layer GA11 and the first end of the second scanning layer GA12 in the first border area 201, and couple the second end of the first scanning layer GA11 and the second end of the second scanning layer GA12 in the second border area 202. In this way, the charges accumulated on the second target scanning line can be better averaged, thereby effectively reducing the amplitude of the first scanning signal transmitted by the second target scanning line that is pulled up due to the influence of the change of the second scanning signal, realizing the rapid release of charges, and achieving the purpose of quickly restoring the first scanning signal transmitted by the first target scanning line to the target potential, thereby reducing the impact on the N1 node, improving the crosstalk phenomenon, and improving the brightness difference of the display substrate in the first sub-area 1011 and the second sub-area 1012.

[0104] As shown in FIG8 to FIG11, in some embodiments, in the first target scan line, the first scanning layer GA11 includes a first scanning pattern 111 and a second scanning pattern 112, and the second scanning layer GA12 includes a third scanning pattern 121 and a fourth scanning pattern 122; the second display area 102 is located between the first scanning pattern 111 and the second scanning pattern 112, and the second display area 102 is located between the third scanning pattern 121 and the fourth scanning pattern 122;

[0105] The first end of the first scanning pattern 111 serves as the first end of the first scanning layer GA11, the second end of the second scanning pattern 112 serves as the second end of the first scanning layer GA11, the first end of the third scanning pattern 121 serves as the first end of the second scanning layer GA12, and the second end of the fourth scanning pattern 122 serves as the second end of the second scanning layer GA12; the second end of the first scanning pattern 111 is coupled to the second end of the third scanning pattern 121, and the first end of the second scanning pattern 112 is coupled to the first end of the fourth scanning pattern 122.

[0106] Exemplarily, the first target scan line also includes a winding portion 41, which is located in the second sub-area 1012, and at least a portion of the winding portion 41 is arranged around the second display area 102; the winding portion 41 is respectively coupled to the second end of the first scanning pattern 111, the first end of the second scanning pattern 112, the second end of the third scanning pattern 121 and the first end of the fourth scanning pattern 122.

[0107] Illustratively, as shown in FIG9 and FIG10 , the winding portions 41 to which adjacent first scanning patterns 111 are coupled are independent of each other; or, as shown in FIG5 , adjacent first scanning patterns 111 are coupled to the same winding portion 40 .

[0108] The winding portions coupling the adjacent first scanning patterns 111 are independent of each other, which can reduce the structural difference between the first target scanning line and the second target scanning line, thereby reducing the difference in charge accumulated on the first target scanning line and the second target scanning line, and further improving the brightness difference between the first sub-area 1011 and the second sub-area 1012 of the display substrate.

[0109] As shown in Figure 4, in some embodiments, the multiple first scanning lines GA1 are divided into multiple scanning groups, each of which includes two adjacent first scanning lines GA1; the display substrate includes multiple first adapters 31, and the first adapters 31 are respectively coupled to the first end of each first scanning layer GA11, the first end of each second scanning layer GA12, and the corresponding first scanning driving unit GA1GOA in the corresponding scanning group.

[0110] The above configuration can reduce the number of the required first scan driving units GA1GOA, which is beneficial to the development of a narrow frame of the display substrate.

[0111] As shown in FIG7 and FIG12, in some embodiments, the display substrate includes a plurality of third transfer portions 33; the third transfer portions 33 are respectively coupled to the second end of the first scanning layer GA11 and the second end of the second scanning layer GA12 in the corresponding first scanning line GA1.

[0112] As shown in FIG. 13 , illustratively, in the scanning group, the third transfer portions 33 to which the first scanning lines GA1 are coupled are coupled.

[0113] The above-mentioned setting method can better average the charges accumulated in the first target scan line, thereby effectively reducing the amplitude of the first scan signal transmitted by the second target scan line that is pulled up due to the influence of the change of the second scan signal, realizing the rapid release of charges, and achieving the purpose of quickly restoring the first scan signal transmitted by the first target scan line to the target potential, thereby reducing the impact on the N1 node, improving the crosstalk phenomenon, and improving the brightness difference between the first sub-area 1011 and the second sub-area 1012 of the display substrate.

[0114] In some embodiments, the longer the length of the winding portion is, the smaller the load of the third transition portion 33 is.

[0115] The above configuration can achieve differentiated compensation, which is beneficial to better improve the brightness uniformity of the display substrate.

[0116] In some embodiments, the display substrate includes a first gate metal layer, a second gate metal layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, which are sequentially stacked on the base substrate in a direction away from the display substrate;

[0117] At least a portion of the first transfer portion 31 is provided in the same layer and material as the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source-drain metal layer or the second source-drain metal layer;

[0118] At least a portion of the third transfer portion 33 is provided in the same layer and material as the first gate metal layer, the second gate metal layer, the first source-drain metal layer, or the second source-drain metal layer.

[0119] The above configuration enables the first transfer portion 31 to be formed in the same patterning process as the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source-drain metal layer, or the second source-drain metal layer.

[0120] The above configuration enables the third transfer portion 33 to be formed in the same patterning process as the first gate metal layer, the second gate metal layer, the first source-drain metal layer, or the second source-drain metal layer.

[0121] In some embodiments, on the same first scanning line GA1, an orthographic projection of the first end of the first scanning layer GA11 on the base substrate of the display substrate and an orthographic projection of the first end of the second scanning layer GA12 on the base substrate have an overlapping area, and the first end of the first scanning layer GA11 and the first end of the second scanning layer GA12 are coupled in the overlapping area through a via hole; and / or,

[0122] In the same first scanning line GA1, the orthographic projection of the second end of the first scanning layer GA11 on the base substrate and the orthographic projection of the second end of the second scanning layer GA12 on the base substrate have an overlapping area, and the first end of the first scanning layer GA11 and the first end of the second scanning layer GA12 are coupled through a via in the overlapping area.

[0123] The above configuration is beneficial for narrowing the border width of the display substrate.

[0124] In some embodiments, the display substrate includes a first gate metal layer, a second gate metal layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, which are sequentially stacked on the base substrate in a direction away from the display substrate;

[0125] The winding portion is provided in the same layer and made of the same material as the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source-drain metal layer or the second source-drain metal layer.

[0126] The winding portion is set in the same layer and material as the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source-drain metal layer or the second source-drain metal layer, so that the winding portion can be formed in the same composition process as the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source-drain metal layer or the second source-drain metal layer.

[0127] In some embodiments, the winding portions of two adjacent first target scanning lines are arranged in the same layer or in different layers.

[0128] The same-layer arrangement is conducive to simplifying the manufacturing process. The different-layer arrangement can not only reduce the risk of short circuits between adjacent winding parts, but also overlap the orthographic projections of adjacent winding parts on the substrate to achieve high-resolution display.

[0129] In some embodiments, the display substrate further includes a plurality of second scan lines GA2, a plurality of light emitting control signal lines EM, a plurality of first reset signal lines Rst1, and a plurality of second reset signal lines Rst2;

[0130] The orthographic projection of the winding portion on the base substrate of the display substrate at least partially overlaps with the orthographic projection of at least one signal line among the second scanning line GA2, the light emitting control signal line EM, the first reset signal line Rst1 and the second reset signal line Rst2 on the base substrate; the at least one signal line is arranged in a different layer from the winding portion.

[0131] Exemplarily, in the second sub-area 1012 , the second scan line GA2 , the light emitting control signal line EM, the first reset signal line Rst1 , and the second reset signal line Rst2 all have winding portions.

[0132] The above arrangement can reduce the risk of short circuit in the winding portion and can also achieve high-resolution display.

[0133] As shown in FIG14 and FIG15 , in some embodiments, the display substrate includes a plurality of sub-pixels, and the sub-pixels include a sub-pixel driving circuit;

[0134] The first scanning layer GA11 and the second scanning layer GA12 belonging to the same first target scanning line are coupled via at least one fourth connecting portion 34 .

[0135] Exemplarily, the fourth transfer portion 34 is provided in the same layer and made of the same material as the first source / drain metal layer, but is not limited thereto.

[0136] Exemplarily, at least a portion of the fourth transition portion 34 is located within the layout area of ​​the sub-pixel driving circuit, or at least a portion of the fourth transition portion 34 is located between the layout areas of adjacent sub-pixel driving circuits.

[0137] Exemplarily, the first scan line GA1 includes at least two fourth transfer portions 34 , at least one of the fourth transfer portions 34 is located between the first border area 201 and the second display area 102 , and at least one of the fourth transfer portions 34 is located between the second border area 202 and the second display area 102 .

[0138] The above-mentioned setting method can better average the differential charges accumulated by the first target scan line, thereby effectively reducing the amplitude of the first scan signal transmitted by the first target scan line that is pulled up due to the influence of the change of the second scan signal transmitted by the second scan line GA2, realizing the rapid release of charges, and achieving the purpose of quickly restoring the first scan signal transmitted by the first target scan line to the target potential, thereby reducing the impact on the N1 node, improving the crosstalk phenomenon, and improving the brightness difference between the first sub-area 1011 and the second sub-area 1012 of the display substrate.

[0139] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0140] It should be noted that the display device may be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, or a tablet computer, wherein the display device also includes a flexible circuit board, a printed circuit board, and a backplane.

[0141] The display substrate provided by the above embodiment can better average the differential charges accumulated by the first target scan line, thereby effectively reducing the amplitude of the first scan signal transmitted by the first target scan line that is pulled up due to the influence of the change of the second scan signal transmitted by the second scan line, realizing the rapid release of charges, and achieving the purpose of quickly restoring the first scan signal transmitted by the first target scan line to the target potential, thereby reducing the impact on the N1 node, improving the crosstalk phenomenon, and improving the brightness difference between the first sub-area and the second sub-area of ​​the display substrate.

[0142] The display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0143] It should be noted that the signal line extending along the X-direction means that the signal line includes a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment, or a strip-shaped body, the main portion extends along the X-direction, and the length of the main portion extending along the X-direction is greater than the length of the secondary portion extending along other directions.

[0144] It should be noted that the layout area occupied by each sub-pixel driving circuit may be an area that can accommodate the sub-pixel driving circuit. Exemplarily, the area may be a rectangular area, but is not limited thereto.

[0145] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0146] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0147] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0148] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0149] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0150] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0151] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A display area and a peripheral area located around the display area; The peripheral area includes a first frame area and a second frame area that are arranged opposite to each other along a first direction; the display area is located between the first frame area and the second frame area, the display area includes a first display area and a second display area, the first display area includes a first sub-area and a second sub-area, at least part of the second sub-area is located in the same row as the second display area along the first direction, and the first sub-area and the second display area are located in different rows along the first direction; The display substrate further includes: a plurality of first scan driving units and a plurality of first scan lines; the first scan driving units are located in the first frame area; the first scan lines include a first scan layer and a second scan layer; The multiple first scanning lines include multiple first target scanning lines, at least part of the first target scanning lines are located in the second sub-area, in the first target scanning lines, the first end of the first scanning layer is coupled to the first end of the second scanning layer, and is coupled to the corresponding first scanning driving unit, the second end of the first scanning layer is coupled to the second end of the second scanning layer, the first end is located in the first border area, and the second end is located in the second border area.

2. The display substrate according to claim 1, wherein: The multiple first scanning lines include multiple second target scanning lines, at least part of the second target scanning lines are located in the first sub-area, in the second target scanning lines, the first end of the first scanning layer is coupled to the first end of the second scanning layer, and is coupled to the corresponding first scanning driving unit, the second end of the first scanning layer is coupled to the second end of the second scanning layer, the first end is located in the first border area, and the second end is located in the second border area.

3. The display substrate according to claim 1, wherein: In the first target scanning line, the first scanning layer includes a first scanning pattern and a second scanning pattern, and the second scanning layer includes a third scanning pattern and a fourth scanning pattern; the second display area is located between the first scanning pattern and the second scanning pattern, and the second display area is located between the third scanning pattern and the fourth scanning pattern; The first end of the first scanning pattern is used as the first end of the first scanning layer, the second end of the second scanning pattern is used as the second end of the first scanning layer, and the first end of the third scanning pattern is used as the first end of the first scanning layer. The second end of the fourth scanning pattern serves as the first end of the second scanning layer, and the second end of the first scanning pattern is coupled to the second end of the third scanning pattern, and the first end of the second scanning pattern is coupled to the first end of the fourth scanning pattern.

4. The display substrate according to claim 3, wherein: The first target scan line also includes a winding portion, which is located in the second sub-area, and at least a portion of the winding portion is arranged around the second display area; the winding portion is respectively coupled to the second end of the first scan pattern, the first end of the second scan pattern, the second end of the third scan pattern and the first end of the fourth scan pattern.

5. The display substrate according to claim 4, wherein: The winding portions to which adjacent first scanning patterns are coupled are independent of each other; or, adjacent first scanning patterns are coupled to the same winding portion.

6. The display substrate according to claim 4, wherein: The multiple first scanning lines are divided into multiple scanning groups, and the scanning group includes two adjacent first scanning lines; the display substrate includes multiple first adapters, and the first adapters are respectively coupled to the first ends of each first scanning layer, the first ends of each second scanning layer, and the corresponding first scanning driving unit in the corresponding scanning group.

7. The display substrate according to claim 6, wherein: The display substrate includes a plurality of third transfer portions; the third transfer portions are respectively coupled to the second end of the first scanning layer and the second end of the second scanning layer in the corresponding first scanning lines.

8. The display substrate according to claim 7, wherein: In the scanning group, the third transfer portions to which the first scanning lines are coupled are coupled to each other.

9. The display substrate according to claim 7, wherein: The display substrate comprises a first gate metal layer, a second gate metal layer, a third gate metal layer, a first source-drain metal layer and a second source-drain metal layer which are sequentially stacked on the base substrate in a direction away from the display substrate; At least a portion of the first transfer portion is provided in the same layer and material as the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source-drain metal layer or the second source-drain metal layer; At least a portion of the third transfer portion is provided in the same layer and the same material as the first gate metal layer, the second gate metal layer, the first source-drain metal layer, or the second source-drain metal layer.

10. The display substrate according to claim 7, wherein: The longer the length of the winding portion is, the smaller the load of the third transition portion is.

11. The display substrate according to claim 1 or 2, wherein: In the same first scanning line, the orthographic projection of the first end of the first scanning layer on the base substrate of the display substrate and the orthographic projection of the first end of the second scanning layer on the base substrate have an overlapping area, and the first end of the first scanning layer and the first end of the second scanning layer are coupled through a via in the overlapping area; and / or, In the same first scanning line, the orthographic projection of the second end of the first scanning layer on the base substrate has an overlapping area with the orthographic projection of the second end of the second scanning layer on the base substrate, and the first end of the first scanning layer and the first end of the second scanning layer are coupled through a via in the overlapping area.

12. The display substrate according to claim 1, wherein: The display substrate includes a plurality of sub-pixels, each of which includes a sub-pixel driving circuit, wherein the sub-pixel driving circuit includes a driving transistor and a compensation transistor, wherein a gate of the compensation transistor is respectively coupled to a first scanning layer and a second scanning layer in the corresponding first scanning line, a first electrode of the compensation transistor is coupled to a second electrode of the driving transistor, and a second electrode of the compensation transistor is coupled to a gate of the driving transistor.

13. The display substrate according to claim 4, wherein: The display substrate comprises a first gate metal layer, a second gate metal layer, a third gate metal layer, a first source-drain metal layer and a second source-drain metal layer which are sequentially stacked on the base substrate in a direction away from the display substrate; The winding portion is provided in the same layer and with the same material as the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source-drain metal layer or the second source-drain metal layer.

14. The display substrate according to claim 4, wherein: The winding parts included in two adjacent first target scanning lines are arranged in the same layer or in different layers.

15. The display substrate according to claim 4, wherein: The display substrate further includes a plurality of second scan lines, a plurality of light emitting control signal lines, a plurality of first reset signal lines and a plurality of second reset signal lines; The orthographic projection of the winding portion on the base substrate of the display substrate at least partially overlaps with the orthographic projection of at least one of the second scan line, the light emission control signal line, the first reset signal line and the second reset signal line on the base substrate; The at least one signal line and the winding portion are arranged in a different layer.

16. The display substrate according to claim 1, wherein: The display substrate includes a plurality of sub-pixels, and the sub-pixels include a sub-pixel driving circuit; The first scanning layer and the second scanning layer belonging to the same first target scanning line are coupled via at least one fourth switching portion.

17. The display substrate according to claim 16, wherein: At least a portion of the fourth transfer portion is located within a layout area of ​​the sub-pixel driving circuit, or at least a portion of the fourth transfer portion is located between layout areas of adjacent sub-pixel driving circuits.

18. The display substrate according to claim 16, wherein: The first scan line includes at least two fourth transfer portions, at least one of the fourth transfer portions is located between the first frame area and the second display area, and at least one of the fourth transfer portions is located between the second frame area and the second display area.

19. A display device comprising the display substrate according to any one of claims 1 to 18.

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