Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel comprises a driving backplane and a light-emitting device. The driving backplane is provided with pixel circuits located in a display area and a peripheral circuit located in a peripheral area, wherein the peripheral circuit comprises a plurality of cascaded shift registers; one shift register is used for scanning at least one row of pixel circuit; the pixel circuits and the shift registers each comprise a plurality of transistors; the transistors of the pixel circuits comprise driving transistors, and the driving transistors and at least some of the other transistors are metal oxide transistors; the transistors in the shift registers are polycrystalline silicon transistors; the light-emitting device is arranged on one side of the driving backplane; the light-emitting device comprises a first electrode, a light-emitting layer and a second electrode which are sequentially stacked in the direction that is away from the driving backplane; a first electrode of each driving transistor is connected to the first electrode of the light-emitting device, and a second electrode thereof is connected to a first power line which is used for transmitting a first power signal; and the second electrode of the light-emitting device is used for receiving a second power signal.

Description

Display panel and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202311279584.6 filed on September 28, 2023, entitled “Display Panel and Display Device,” and the entire contents of this Chinese patent application are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0004] Display panels using organic light-emitting diodes (OLEDs) as light-emitting devices suffer from low image quality uniformity, especially for large-sized display panels, where image quality uniformity is difficult to improve. Furthermore, the wide bezels of the display panels make it difficult to increase the screen-to-body ratio.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0006] Summary of the Invention

[0007] The present disclosure aims to provide a display panel and a display device that improve image quality while increasing the screen-to-body ratio.

[0008] According to one aspect of the present disclosure, a display panel is provided, comprising a display area and a peripheral area outside the display area; the display panel comprises:

[0009] A driving backplane having a pixel circuit located in the display area and a peripheral circuit located in the peripheral area, wherein the peripheral circuit includes a plurality of cascaded shift registers; the shift register is used to scan at least one row of the pixel circuits; the pixel circuits and the shift register each include a plurality of transistors; the transistors of the pixel circuits include a driving transistor, and the driving transistor and at least some other transistors in the pixel circuits are metal oxide transistors; and the transistors in the shift register are polysilicon transistors;

[0010] A plurality of light-emitting devices are arrayed on one side of the driving backplane; the light-emitting devices include a first electrode, a light-emitting layer, and a second electrode stacked in sequence in a direction away from the driving backplane; the first electrode of the driving transistor is connected to the first electrode of the light-emitting device, and the second electrode is connected to the first power line transmitting a first power signal; the second electrode of the light-emitting device is used to receive a second power signal.

[0011] In an exemplary embodiment of the present disclosure, the pixel circuit further includes a first reset circuit, a second reset circuit and a write circuit; the first reset circuit is connected to the gate of the driving transistor, and is used to transmit a first reset signal in response to a first reset scan signal; the second reset circuit is connected to the first electrode of the driving transistor, and is used to transmit a second reset signal in response to a second reset scan signal; the write circuit is connected to the gate of the driving transistor, and is used to transmit a data signal in response to a write scan signal.

[0012] In an exemplary embodiment of the present disclosure, the pixel circuit further includes a light-emitting control circuit and a storage capacitor; the first power line is connected to the second electrode of the driving transistor through the light-emitting control circuit, and the light-emitting control circuit is used to be turned on in response to a light-emitting scanning signal; the storage capacitor is connected to the gate and the first electrode of the driving transistor.

[0013] In an exemplary embodiment of the present disclosure, the first reset circuit includes a first reset transistor, the second reset circuit includes a second reset transistor, the write circuit includes a write transistor, and the light emission control circuit includes a light emission control transistor;

[0014] The gate of the first reset transistor is used to receive the first reset scan signal, the first electrode is used to receive the first reset signal, and the second electrode is connected to the gate of the driving transistor; the gate of the second reset transistor is used to receive the second reset scan signal, the first electrode is used to receive the second reset signal, and the second electrode is connected to the first electrode of the driving transistor; the gate of the write transistor is used to receive the write scan signal, the first electrode is used to receive the data signal, and the second electrode is connected to the gate of the driving transistor; the gate of the light-emitting control transistor is used to receive the light-emitting scan signal, the first electrode is connected to the first power line, and the second electrode is connected to the second electrode of the driving transistor.

[0015] In an exemplary embodiment of the present disclosure, the shift register includes an input circuit, a first control circuit, a second control circuit, and a first output circuit;

[0016] The input circuit is connected to the input terminal, the first node and a first clock signal line providing a first clock signal, and is configured to transmit the input signal of the input terminal to the first node in response to the first clock signal;

[0017] The first control circuit is connected to the first node, the second node, the first clock signal line, and a first voltage line providing a first voltage, and is configured to control the voltage of the second node in response to the first clock signal, the first voltage, and the voltage of the first node;

[0018] The second control circuit is connected to the first node, the second node, a second voltage line providing a second voltage, and a second clock signal line providing a second clock signal, and is configured to control the voltage of the first node in response to the second clock signal, the second voltage, and the voltage of the second node;

[0019] The first output circuit is connected to the first node, the second node, a third voltage line providing a third voltage, a third clock signal line providing a third clock signal, and the first output end, and is used to output the third voltage or the third clock signal from the first output end under the control of the voltages of the first node and the second node.

[0020] In an exemplary embodiment of the present disclosure, the first output circuit includes a first output sub-circuit and a second output sub-circuit;

[0021] The first output sub-circuit is connected to the first node, the first output terminal and the third clock signal line, and is used to control the first output terminal and the third clock signal line to be turned on or off under the control of the voltage of the first node;

[0022] The second output sub-circuit is connected to the second node, the third voltage line and the first output terminal, and is configured to control the first output terminal and the third voltage line to be turned on or off in response to the voltage of the second node.

[0023] In an exemplary embodiment of the present disclosure, the shift register further includes a second output circuit, which is connected to the first node, the second node, the second voltage line, the second clock signal line and the second output terminal, and is used to output the second voltage or the second clock signal from the second output terminal under the control of the voltages of the first node and the second node.

[0024] In an exemplary embodiment of the present disclosure, the second output circuit includes a third output sub-circuit and a fourth output sub-circuit;

[0025] The third output sub-circuit is connected to the first node, the second voltage line and the second output terminal, and is used to control the second output terminal and the second clock signal line to be turned on or off in response to the voltage of the first node;

[0026] The fourth output sub-circuit is connected to the second node and the second output terminal, and is configured to control the second output terminal and the second voltage line to be turned on or off in response to the voltage of the second node.

[0027] In an exemplary embodiment of the present disclosure, the shift register further includes a first isolation circuit and a second isolation circuit;

[0028] The first isolation circuit is connected to the first node and the first output sub-circuit, and is connected to the first voltage line;

[0029] The second isolation circuit is connected to the first node and the third output sub-circuit, and is connected to the first voltage line.

[0030] In an exemplary embodiment of the present disclosure, the third output subcircuit is connected to the first node via a third node;

[0031] The shift register further includes a third control circuit connected to the first node, the third node and a fourth voltage line providing a fourth voltage, and configured to control the voltage of the first node in response to the voltage of the third node and the fourth voltage.

[0032] In an exemplary embodiment of the present disclosure, the input circuit includes an input transistor, wherein a gate of the input transistor is connected to the first clock signal line, a first electrode is connected to the input terminal, and a second electrode is connected to the first node;

[0033] The first control circuit includes a first control transistor and a second control transistor, wherein the gate of the first control transistor is connected to the first clock signal line, the first electrode is connected to the first voltage line, and the second electrode is connected to the second node; the gate of the second control transistor is connected to the first node, the first electrode is connected to the first clock signal line, and the second electrode is connected to the second node;

[0034] The second control circuit includes a third control transistor and a fourth control transistor, wherein the gate of the third control transistor is connected to the second node, the first electrode is connected to the second voltage line, the second electrode is connected to the first electrode of the fourth control transistor, the second electrode of the fourth control transistor is connected to the first node, and the gate of the fourth control transistor is connected to the second clock signal line;

[0035] The first output sub-circuit includes a first output transistor, and the first isolation circuit includes a first isolation transistor; the first isolation transistor has a gate connected to the first voltage line, a first electrode connected to the first node, and a second electrode connected to the gate of the first output transistor; the first electrode of the first output transistor is connected to the third clock signal line, and the second electrode is connected to the first output terminal;

[0036] The second output sub-circuit includes a second output transistor and a first capacitor, the gate of the second output transistor is connected to the second node, the first electrode is connected to the third voltage line, and the second electrode is connected to the first output end; the first capacitor is connected to the gate and the first electrode of the second output transistor.

[0037] In an exemplary embodiment of the present disclosure, the third output sub-circuit includes a third output transistor and a second capacitor, and the second isolation circuit includes a second isolation transistor; the gate of the second isolation transistor is connected to the first voltage line, the first electrode is connected to the first node, and the second electrode is connected to the third node; the gate of the third output transistor is connected to the third node, the first electrode is connected to the second clock signal line, and the second electrode is connected to the second output terminal; the second capacitor is connected to the gate and the second electrode of the third output transistor;

[0038] The fourth output sub-circuit includes a fourth output transistor, wherein a gate of the fourth output transistor is connected to the second node, a first electrode is connected to the second voltage line, and a second electrode is connected to the second output terminal.

[0039] In an exemplary embodiment of the present disclosure, the third control circuit includes a fifth control transistor having a gate connected to the third node, a first electrode connected to the fourth voltage line, and a second electrode connected to the first node.

[0040] In an exemplary embodiment of the present disclosure, the transistors of the pixel circuit are all metal oxide transistors; and the transistors of the shift register are all polysilicon transistors.

[0041] In an exemplary embodiment of the present disclosure, the driving backplane includes a substrate and a light shielding layer, a polysilicon semiconductor layer, a first gate layer, a second gate layer, an oxide semiconductor layer, a third gate layer, a first source-drain layer, and a second source-drain layer distributed in a direction away from the substrate; the first electrode is provided on a side of the second source-drain layer away from the substrate;

[0042] The channel portion of the transistor of the shift register is located in the polysilicon semiconductor layer; the channel portion of each transistor of the pixel circuit is located in the oxide semiconductor layer;

[0043] The first plates of the first capacitor and the second capacitor are located on the first gate layer, and the second plates are located on the second gate layer; the first plate of the storage capacitor is located on the light shielding layer, and the second plate is located on the second gate layer;

[0044] The first clock signal line, the second clock signal line, the third clock signal line, the first voltage line, the second voltage line and the third voltage line are located in the first source-drain layer; the fourth voltage line is located in the second source-drain layer.

[0045] In an exemplary embodiment of the present disclosure, the first clock signal line, the second clock signal line, the second voltage line, the first voltage line, the fourth voltage line, the third clock signal line, and the third voltage line all have orthographic projections on the substrate extending in a column direction and are sequentially distributed along a row direction toward the display area;

[0046] In a shift register, the first output transistor and the second output transistor are located between the third voltage line and the orthographic projection of the pixel circuit on the substrate, and the orthographic projection of other transistors and the first capacitor on the substrate are located between the second voltage line and the orthographic projection of the third clock signal line on the substrate.

[0047] In an exemplary embodiment of the present disclosure, channel portions of the input transistor, the first control transistor, the second control transistor, the third control transistor, and the fourth control transistor are located between orthographic projections of the first voltage line and the second voltage line on the substrate.

[0048] The orthographic projections of the third output transistor, the fourth output transistor, the fifth control transistor, the first isolation transistor, the second isolation transistor, and the first capacitor on the substrate are located between the orthographic projections of the first voltage line and the third clock signal line on the substrate.

[0049] In an exemplary embodiment of the present disclosure, a channel portion of at least one of the input transistor, the first output transistor, and the second output transistor includes at least two channels connected in series.

[0050] In an exemplary embodiment of the present disclosure, the polycrystalline silicon semiconductor layer includes a first semiconductor portion, a second semiconductor portion, a third semiconductor portion, a fourth semiconductor portion, a fifth semiconductor portion, a sixth semiconductor portion, a seventh semiconductor portion, an eighth semiconductor portion, and a ninth semiconductor portion;

[0051] The orthographic projections of the first semiconductor portion to the fourth semiconductor portion on the substrate are located between the orthographic projection of the second voltage line and the first voltage line on the substrate; the first semiconductor portion, the second semiconductor portion, and the third semiconductor portion are distributed along the row direction; and the first semiconductor portion and the fourth semiconductor portion are distributed along the column direction;

[0052] The orthographic projections of the fifth to eighth semiconductor portions on the substrate are located between the orthographic projections of the first voltage line and the third clock signal line on the substrate; the fifth to eighth semiconductor portions are distributed along the column direction;

[0053] The ninth semiconductor portion is located between the third voltage line and the pixel circuit on an orthographic projection of the substrate;

[0054] The channel portion of the input transistor is located in the first semiconductor portion; the channel portion of the second control transistor is located in the second semiconductor portion; the channel portion of the first control transistor is located in the second semiconductor portion; the channel portion of the third control transistor and the fourth control transistor are located in the fourth semiconductor portion; the channel portion of the first isolation transistor is located in the fifth semiconductor portion; the channel portion of the second isolation transistor is located in the sixth semiconductor portion; the channel portion of the fifth control transistor is located in the seventh semiconductor portion; the channel portions of the three output transistors and the fourth output transistor are located in the eighth semiconductor portion; and the channel portions of the first output transistor and the second output transistor are located in the ninth semiconductor portion.

[0055] In an exemplary embodiment of the present disclosure, the first gate layer includes a first gate portion, a second gate portion, a third gate portion, a fourth gate portion, a fifth gate portion, a sixth gate portion, and a seventh gate portion;

[0056] The first gate portion overlaps with the first semiconductor portion and the third semiconductor portion to form the input transistor and the first control transistor, and the first gate portion is connected to the first clock signal line through a contact hole;

[0057] The second gate portion overlaps the second semiconductor portion to form the second control transistor;

[0058] The third gate portion overlaps with the fourth semiconductor portion to form the fourth control transistor, and the third gate portion is connected to the second clock signal line through a contact hole;

[0059] The fourth gate portion overlaps with the fourth semiconductor portion, the eighth semiconductor portion, and the ninth semiconductor portion to form the third control transistor, the fourth output transistor, and the second output transistor; the third gate portion includes a first plate of the second capacitor;

[0060] The fifth gate portion overlaps with the fifth semiconductor portion and the sixth semiconductor portion to form the first isolation transistor and the second isolation transistor; and the fifth gate portion is connected to the first voltage line through a contact hole;

[0061] The sixth gate portion overlaps with the seventh semiconductor portion and the eighth semiconductor portion to form the fifth control transistor and the third output transistor; the sixth gate portion includes a first plate of the first capacitor;

[0062] The seventh gate portion overlaps the ninth semiconductor portion to form the first output transistor.

[0063] In an exemplary embodiment of the present disclosure, in the shift register, the width of the channel portions of the first output transistor, the second output transistor, the third output transistor and the fourth output transistor in the row direction is greater than the width of the channel portions of other transistors in the row direction.

[0064] In an exemplary embodiment of the present disclosure, the first gate layer further includes a cascade jumper portion; the second gate layer includes a first transfer portion and a second transfer portion; the first source and drain layer includes a scan output portion, a cascade output portion, a cascade line, a first connection portion, a second connection portion, and a third connection portion;

[0065] The scan output portion overlaps with the ninth semiconductor portion and is connected via a contact hole to connect the second electrodes of the first output transistor and the second output transistor;

[0066] The cascade output portion overlaps with the eighth semiconductor portion and is connected through a contact hole to connect the second electrodes of the third output transistor and the fourth output transistor; the cascade line extends along the column direction and is located between the second voltage line and the first voltage line; the cascade jumper portion extends along the row direction and overlaps with the first voltage line, and is connected to the cascade output portion and the cascade line through a contact hole;

[0067] The first connecting portion overlaps with the ninth semiconductor portion and is connected through a contact hole to connect to the first electrode of the first output transistor; the first transfer portion extends along the row direction and overlaps with the first connecting portion and the third voltage line, and is connected to the third clock signal line and the first connecting portion through a contact hole;

[0068] The second connection portion overlaps with the eighth semiconductor portion and is connected through a contact hole to connect to the first electrode of the fourth output transistor; the third connection portion is connected to the second voltage line; the second transfer portion extends along the row direction and overlaps with the first voltage line, and the second transfer portion is connected to the second connection portion and the third connection portion through a contact hole.

[0069] According to one aspect of the present disclosure, a display device is provided, comprising any one of the display panels described above.

[0070] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0072] FIG1 is a schematic top view of an embodiment of a display panel disclosed herein.

[0073] FIG2 is a schematic cross-sectional view of an embodiment of a display panel according to the present disclosure.

[0074] FIG3 is a schematic diagram of a pixel circuit of an embodiment of a display panel according to the present disclosure.

[0075] FIG. 4 is a timing diagram of a driving method of a pixel circuit of an embodiment of a display panel disclosed herein.

[0076] FIG. 5 is a schematic diagram of a shift register of an embodiment of a display panel according to the present disclosure.

[0077] FIG. 6 is a timing diagram of a driving method of a shift register in an embodiment of a display panel disclosed herein.

[0078] 7 to 10 are schematic diagrams of the shift register in FIG. 5 during the first to fourth stages.

[0079] FIG11 is a partial top view of a display area in one embodiment of a display panel disclosed herein.

[0080] FIG12 is a partial top view of the display panel according to one embodiment of the present disclosure, from the light shielding layer to the first source and drain layer in the display area.

[0081] FIG13 is a partial top view of the display panel from the light shielding layer to the third gate layer in the display area according to one embodiment of the present disclosure.

[0082] 14 to 19 are partial top views of a portion of the film layer in the display area of ​​an embodiment of the display panel disclosed herein.

[0083] FIG20 is a partial top view of the peripheral area of ​​an embodiment of a display panel disclosed herein.

[0084] FIG21 is a partial top view of the polysilicon semiconductor layer to the first source and drain layer in the peripheral region of an embodiment of the display panel disclosed herein.

[0085] FIG22 is a partial top view of the polysilicon semiconductor layer to the second gate layer in the peripheral region of an embodiment of the display panel disclosed herein.

[0086] FIG23 is a partial top view of the polysilicon semiconductor layer to the first gate layer in the peripheral region of an embodiment of the display panel disclosed herein.

[0087] 24 to 28 are partial top views of a portion of the film layer in the peripheral area of ​​an embodiment of the display panel disclosed herein. DETAILED DESCRIPTION

[0088] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0089] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0090] The row direction X and column direction Y herein are two intersecting directions, which may be perpendicular to each other or at an angle other than a right angle. In the drawings of this disclosure, the row direction X is horizontal and the column direction Y is vertical, but this is not limiting. Those skilled in the art will appreciate that if the display panel is rotated, the actual orientations of the row direction X and column direction Y may change.

[0091] Herein, "overlapping" of A and B means that the orthographic projection of A on the substrate SU and the orthographic projection of B on the substrate SU at least partially overlap. Of course, the orthographic projections of A and B on a plane parallel to the substrate SU may also at least partially overlap.

[0092] The transistor in this article includes a gate, a first electrode, and a second electrode. Controlling the gate voltage enables the first electrode and the second electrode to be turned on and off. The first electrode can be a source, and the second electrode can be a drain. Of course, the first electrode can also be a drain, and the second electrode can also be a source. Specifically, if the signal is input through the first electrode, the first electrode becomes the source, and the second electrode becomes the drain. If the signal is input through the second electrode, the second electrode becomes the source, and the first electrode becomes the drain. In other words, the source and drain can be interchanged depending on the input signal.

[0093] For a P-type transistor, when the gate receives a high level, the first and second electrodes are turned off; when the gate receives a low level, the first and second electrodes are turned on. For an N-type transistor, when the gate receives a high level, the first and second electrodes are turned on; when the gate receives a low level, the first and second electrodes are turned off.

[0094] An embodiment of the present disclosure provides a display panel, as shown in FIG1 , which may include a display area AA and a peripheral area WA located outside the display area AA. The peripheral area WA may be a continuous annular area surrounding the display area AA or a discontinuous area surrounding the display area AA.

[0095] As shown in FIG2 , the display panel may include a driving backplane BP and a plurality of light-emitting devices LD arranged on one side of the driving backplane BP. The light-emitting devices LD may be distributed in an array along the row direction X and the column direction Y. The driving circuit in the driving backplane BP may drive the light-emitting devices LD to emit light to display images.

[0096] As shown in Figure 2, the light-emitting device LD can use an OLED (organic light-emitting diode) made of organic light-emitting materials; it can also use an LED (light-emitting diode) made of inorganic light-emitting materials, such as Micro LED (micrometer light-emitting diode) and Mini LED (sub-millimeter light-emitting diode); it can also use devices such as QLED (quantum dot diode). No special restrictions are made on the specific structure of the light-emitting device LD here.

[0097] Taking the light-emitting device LD as an example, which is an OLED, it may include a first electrode ANO, a light-emitting layer EL, and a second electrode CAT stacked in sequence in a direction away from the driving backplane BP. By applying a first power signal to the first electrode ANO and a second power signal to the second electrode CAT, the light-emitting layer EL can be stimulated to emit light. The specific principle will not be detailed here. At the same time, in order to limit the range of the light-emitting device LD, a pixel definition layer PDL can be provided on the driving backplane BP. The pixel definition layer PDL and the first electrode ANO are located on the same surface of the driving backplane BP, and the pixel definition layer PDL can have pixel openings that expose each first electrode ANO, so that the range of the light-emitting device LD can be limited by each pixel opening.

[0098] The driving circuit may include a pixel circuit PC located in the display area AA and a peripheral circuit located in the peripheral area WA. The pixel circuit PC may be distributed in an array along the row direction X and the column direction Y. A pixel circuit PC may be connected to the first electrode ANO of a light-emitting device LD. Of course, the same pixel circuit PC may also be connected to the first electrodes ANO of multiple light-emitting devices LD.

[0099] As shown in FIG3 , the pixel circuit PC may include multiple transistors. Any of the transistors in the pixel circuit PC includes at least a driving transistor M5. The driving transistor M5 may be a metal oxide transistor (MOT). At least a portion of the other transistors may also be MOTs. Of course, only the driving transistor M5 may be a MOT. A MOT refers to an active layer made of, for example, IGZO (Indium Gallium Zinc Oxide) or IZO (Indium Zinc Oxide). The active layer of the transistor includes a channel portion and a conductor portion connected to the channel.

[0100] Taking a pixel circuit PC as an example, as shown in FIG3 , the pixel circuit PC may include a driving transistor M5 , a writing circuit 1 , a first reset circuit 2 , a second reset circuit 3 and a light emitting control circuit 4 , wherein:

[0101] The first reset circuit 2 is connected to the gate of the driving transistor M5 and can be turned on or off in response to the first reset scan signal Gate2. The first reset circuit 2 can receive the first reset signal Vref and transmit the first reset signal Vref when turned on.

[0102] The second reset circuit 3 is connected to the first electrode of the driving transistor M5 and can be turned on or off in response to the second reset scan signal Gate3. The second reset circuit 3 can receive the second reset signal Vinit and transmit the second reset signal Vinit when turned on.

[0103] The write circuit 1 is connected to the gate of the driving transistor M5 and can be turned on or off in response to a write scan signal Gate1 . The write circuit 1 can receive a data signal Data and transmit the data signal Data when turned on.

[0104] The light-emitting control circuit 4 can receive a first power supply signal VDD and is connected to the second electrode of the driving transistor M5. The light-emitting control circuit 4 can be turned on or off in response to the light-emitting scanning signal EM. When turned on, the light-emitting control circuit 4 can transmit the first power supply signal VDD to the driving transistor M5. The storage capacitor Cst is connected to the gate and the first electrode of the driving transistor M5.

[0105] Furthermore, in some embodiments of the present disclosure, as shown in FIG3 , the pixel circuit PC has a 5T1C structure, i.e., five transistors and one capacitor. Specifically, the first reset circuit 2 includes a first reset transistor M2, the second reset circuit 3 includes a second reset transistor M3, the write circuit 1 includes a write transistor M1, and the light-emission control circuit 4 includes a light-emission control transistor M4. Each transistor in the pixel circuit PC is a metal oxide transistor.

[0106] As shown in Figures 11 to 13, to facilitate signal transmission, the driving backplane BP may further include a first power line VDL, a data line DAL, a first reset scan line GL2, a second reset scan line GL3, a write scan line GL1, a light-emitting scan line EML, a first reset signal line VRL, and a second reset signal line VIL. The first power line VDL and the data line DAL may extend along a column direction Y and may be distributed along a row direction X. The first reset scan line GL2, the second reset scan line GL3, the write scan line GL1, the light-emitting scan line EML, the first reset signal line VRL, and the second reset signal line VIL may extend along a row direction X and may be distributed along a column direction Y.

[0107] The first reset scan line GL2 is connected to the gate of the first reset transistor M2 and is used to transmit a first reset scan signal Gate2. The first reset signal line VRL is connected to the first electrode of the first reset transistor M2 and can transmit the first reset signal Vref. The second electrode of the first reset transistor M2 is connected to the gate of the drive transistor M5 and is connected to the N1 node. The first reset scan signal Gate2 can control the first reset transistor M2 to be turned on or off. When turned on, the first reset signal Vref is transmitted to the gate of the drive transistor M5 through the first reset transistor M2, that is, the first reset signal Vref is transmitted to the N1 node.

[0108] The second reset scan line GL3 is connected to the gate of the second reset transistor M3 and is used to transmit a second reset scan signal Gate3. The second reset signal line VIL is connected to the first electrode of the second reset transistor M3 and can transmit a second reset signal Vinit. The second electrode of the second reset transistor M3 is connected to the first electrode of the drive transistor M5 and can be connected to the N3 node. The second reset scan signal Gate3 can control the second reset transistor M3 to be turned on or off. When turned on, the second reset signal Vinit is transmitted to the first electrode of the drive transistor M5 through the second reset transistor M3, that is, the second reset signal Vinit is transmitted to the N3 node.

[0109] The emission scan line EML is connected to the gate of the emission control transistor M4 and is used to transmit a light emission scan signal EM. The first power line VDL is connected to the first electrode of the emission control transistor M4. The second electrode of the emission control transistor M4 is connected to the second electrode of the drive transistor M5 and can be connected to the N2 node. The first power line VDL is used to transmit a first power signal VDD. The emission scan signal EM can be used to turn the emission control transistor M4 on or off. When the emission control transistor M4 is on, the first power signal VDD is transmitted to the second electrode of the drive transistor M5 through the emission control transistor M4.

[0110] The write scan line GL1 is connected to the gate of the write transistor M1 and is used to transmit the write scan signal Gate1. The data line DAL is connected to the first electrode of the write transistor M1 and can transmit the data signal Data. The second electrode of the write transistor M1 is connected to the gate of the drive transistor M5 and can be connected to the N1 node. The write scan signal Gate1 can control the turn-on or turn-off of the write transistor M1. When the write transistor M1 is turned on, the data signal Data is transmitted to the gate of the drive transistor M5 through the write transistor M1, that is, the data signal Data is transmitted to the N1 node.

[0111] Meanwhile, the storage capacitor Cst has a first plate Cst1 and a second plate Cst2 facing each other. The first plate Cst1 is connected to the first electrode of the driving transistor M5 and can be connected to the N3 node. The second plate Cst2 is connected to the gate of the driving transistor M5 and can be connected to the N1 node. The first electrode of the driving transistor M5 and the second electrode of the second reset transistor M3 can be connected to the first electrode ANO of the light-emitting device LD and can be connected to the N3 node.

[0112] In some embodiments of the present disclosure, as shown in FIG11 to FIG13 , the driving backplane BP further includes a second power line, a first auxiliary first power line VDLs, and a second auxiliary power line VSLs, wherein:

[0113] The second power line may extend along the column direction Y and may be multiple in number and distributed along the row direction X. Of course, the number of second power lines may also be one. The second power line is used to transmit the second power signal VSS and may be connected to the second electrode CAT of the light-emitting device LD. For example, the driver backplane BP includes a first power bus for transmitting the first power signal VDD and a second power bus for transmitting the second power signal VSS in the peripheral area WA. Each first power line VDL may be connected to the first power bus, while the second power line may be connected to the second power bus. Furthermore, the second electrode CAT of the light-emitting device LD may extend to the peripheral area WA and be directly or indirectly connected to the second power bus. The second power line and the second power bus may form a unit that transmits the second power signal VSS. While transmitting the second power signal VSS to the second electrode via the second power bus, the second power line reduces resistance and voltage drop, thereby facilitating signal stability and uniformity. Of course, in some embodiments, the second power line may not be provided.

[0114] The first auxiliary first power lines VDLs can extend along the row direction X. There can be multiple first auxiliary first power lines VDLs, distributed along the column direction Y, or there can be only one. Furthermore, the first auxiliary first power lines VDLs can intersect with the first power lines VDL in space, but they can be located on different layers and connected via contact holes. This allows the first auxiliary first power lines VDLs and the first power lines VDL to form a network for transmitting the first power signal VDD, which helps reduce resistance, minimize voltage drop, and maintain signal stability and uniformity.

[0115] The second power lines can extend in the row direction X. There can be multiple second power lines, distributed along the column direction Y, or there can be only one. Furthermore, the second auxiliary power lines VSLs can intersect with the second power lines in space, but they can be located on different layers and connected via contact holes. This allows the second auxiliary power lines VSLs and the second power lines to form a network for transmitting the second power signal VSS, which helps reduce resistance, minimize voltage drop, and maintain signal stability and uniformity.

[0116] Furthermore, in some embodiments of the present disclosure, as shown in Figures 10 to 12 , the driver backplane BP further includes a first auxiliary reset line extending along the column direction Y. Multiple first auxiliary reset lines may be provided, distributed along the column direction Y, or, alternatively, only one. Furthermore, the first auxiliary reset line and the first reset signal line VRL are located on different layers and connected via contact holes, thereby forming a network for transmitting the first reset signal Vref. This helps reduce resistance, minimize voltage drop, and maintain signal stability and uniformity.

[0117] Furthermore, in some embodiments of the present disclosure, as shown in Figures 10 to 12 , the driver backplane BP further includes a plurality of second auxiliary reset lines VILs extending along the column direction Y. These lines may be distributed along the column direction Y, or, alternatively, may be a single line. Furthermore, the second auxiliary reset lines VILs and the second reset signal line VIL are located on different layers and connected via contact holes, thereby forming a network for transmitting the second reset signal Vinit. This helps reduce resistance, minimize voltage drop, and maintain signal stability and uniformity.

[0118] The following is an example of the distribution of the above wiring:

[0119] In some embodiments of the present disclosure, as shown in Figures 1 and 11-13, a data line DAL is connected to the write transistor M1 of a column of pixel circuits PC; a first power line VDL is connected to the light-emitting control transistor M4 of a column of pixel circuits PC. The data line DAL and the first power line VDL connected to the same column of pixel circuits PC can be defined as a column line group, that is, each column of pixel circuits PC can be connected to a column line group. At the same time, a second power line, a first auxiliary reset line, or a second auxiliary reset line VILs can be provided between two adjacent column line groups. In other words, the second power line, the first auxiliary reset line, and the second auxiliary reset line VILs are distributed in the space between the column line groups. At the same time, two of the second power line, the first auxiliary reset line, and the second auxiliary reset line VILs can be provided on both sides of the same column line group. This allows for full utilization of space and a more uniform distribution of the wiring in the column direction Y.

[0120] For example, as shown in Figures 1 and 11-13, the second power line, the first auxiliary reset line, and the second auxiliary reset line VILs can all be defined as auxiliary lines. These auxiliary lines and the aforementioned column line groups can be alternately distributed along the row direction X. In the row direction X, if the nth auxiliary line is the second power line, then the n+1th auxiliary line is the second auxiliary reset line VILs, and the n+2th auxiliary line is the first auxiliary reset line, where n is a positive integer. Of course, the auxiliary lines can also be arranged in other arrangements, which will not be detailed here.

[0121] In some embodiments of the present disclosure, as shown in Figures 11-13, a row of pixel circuits PC is simultaneously connected to a first reset scan line GL2, a second reset scan line GL3, a write scan line GL1, an emission scan line EML, a first reset signal line VRL, and a second reset signal line VIL. The specific connection relationships have been described above in the context of pixel circuits PC and will not be repeated here. The first reset scan line GL2, the second reset scan line GL3, the write scan line GL1, the emission scan line EML, the first reset signal line VRL, and the second reset signal line VIL connected to the same row of pixel circuits PC can be defined as a row line group, that is, each row of pixel circuits PC is connected to a row line group. Furthermore, a first auxiliary first power line VDLs and a second auxiliary power line VSLs can be provided between two adjacent row line groups. A row line group is located between a first auxiliary first power line VDLs and a second auxiliary power line VSLs.

[0122] The structure of the pixel circuit PC and its driving method based on the above embodiment are described below:

[0123] As shown in FIG3 and FIG4, taking the above-mentioned 5T1C structure pixel circuit PC as an example, each transistor is a metal oxide transistor and is an N-type transistor, which is convenient for improving the uniformity of the transistors in the display area AA. The driving method of the pixel circuit may include:

[0124] During initialization phase t1, the first reset scan signal Gate2 is high, turning on the first reset transistor M2 and the second reset transistor M3. This transmits the first reset signal Vref to the gate of the drive transistor M5 and the second reset signal Vinit to the first electrode of the drive transistor M5 and the first electrode ANO of the light-emitting device, thereby transmitting the second reset signal Vinit to the N3 node. Simultaneously, the write scan signal Gate1 and the emission scan signal EM are low, turning off the write transistor M1 and the emission control transistor M4. The first reset signal Vref and the second reset signal Vinit initialize the gate and first electrode of the drive transistor M5 and the first electrode ANO of the light-emitting device, thereby initializing the N1 and N3 nodes. At this point, the voltage at the N1 node equals Vref, and the voltage at the N3 node equals Vinit.

[0125] Compensation phase t2: The first reset scan signal Gate2 remains high, the second reset scan signal Gate3 is low, the first reset transistor M2 continues to conduct and transmits the first reset signal Vref to the gate of the drive transistor M5, that is, transmits the first reset signal Vref to the N1 node, and the second reset transistor M3 is turned off. Simultaneously, the emission scan signal EM is high, and the emission control transistor M4 is turned on.

[0126] When the voltage difference between the first reset signal Vref and the second reset signal Vinit exceeds the threshold voltage of the driving transistor M5, that is, when the voltage difference between the N1 node and the N3 node exceeds the threshold voltage, the driving transistor M5 turns on. The first power supply signal VDD charges the first electrode of the driving transistor M5 until the difference between the first reset signal Vref and the threshold voltage of the driving transistor M5 is reached, that is, when the voltage at the N3 node is Vref-Vth, the driving transistor M5 turns off, thereby writing the threshold voltage to the first electrode of the driving transistor M5. At this time, the voltage at the N1 node = Vref, and the voltage at the N3 node = Vref-Vth.

[0127] During the write phase t3, the first reset scan signal Gate2, the second reset scan signal Gate3, and the emission scan signal EM are all at a low level, and the write scan signal Gate1 is at a high level. The first reset transistor M2, the second reset transistor M3, and the emission control transistor M4 are off, and the write transistor M1 is on. The data signal Data is written to the N1 node via the write transistor M1, that is, the data signal Data is written to the gate of the drive transistor M5 and the second plate Cst2 of the storage capacitor Cst. At this time, the voltage Vg at the N1 node = Vdata, and the voltage at the N3 node = Vld + Vss = Vref - Vth, where Vld is the voltage of the light-emitting device LD, that is, the voltage of the capacitor Co of the light-emitting device LD itself.

[0128] In the light-emitting stage t4: the light-emitting scanning signal EM is at a high level, the first reset scanning signal Gate2, the second reset scanning signal Gate3, and the write scanning signal Gate1 are at a low level, the light-emitting control transistor M4 is turned on, and the first reset transistor M2, the second reset transistor M3, and the write transistor M1 are turned off; under the action of the storage capacitor Cst, the driving transistor M5 outputs a current, and the output current satisfies the following formula: I = (μWCox / 2L)(Vgs-Vth) 2 ;

[0129] I is the output current of the driving transistor M5; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the channel of the driving transistor M5, and L is the channel length of the driving transistor M5.

[0130] According to the above output current formula, the voltage difference Vgs between the gate voltage and the source voltage of the driving transistor M5 in the pixel circuit PC of the present disclosure is substituted into the above formula to obtain: the output current I of the driving transistor M5 = (μWCox / 2L)(Vdata-Vref) 2 .

[0131] As can be seen, the threshold voltage compensation phase and the data signal writing phase are performed separately. The output current (i.e., the current of the light-emitting device) is not affected by the voltage of the first power signal VDD or the threshold voltage Vth, but is only affected by Vdata and Vref. The first reset signal Vref has a lower current than the first power signal VDD, minimizing the risk of IR drop.

[0132] The peripheral area WA of the display panel may also be provided with a power bus connected to the second electrode CAT of the light emitting device LD, and a second power signal is applied to the second electrode CAT. The current passing through the light emitting device LD can be controlled through the pixel circuit PC, thereby controlling the brightness of the light emitting device LD.

[0133] As shown in Figures 1-3, the peripheral circuit can be connected to the light-emitting device LD via the pixel circuit PC and apply a first power signal VDD to the first electrode ANO of the light-emitting device LD. The peripheral circuit may also include a gate drive circuit and a light-emitting drive circuit for scanning the pixel circuit PC. Simultaneously, the peripheral circuit may also be connected to the second electrode CAT of the light-emitting device LD and apply a second power signal VSS to the second electrode CAT. The pixel circuit PC can control the current passing through the light-emitting device LD, thereby controlling the brightness of the light-emitting device LD.

[0134] As shown in Figure 1, a peripheral circuit may include multiple cascaded shift registers GOA, where the output of the previous-stage shift register GOA is connected to the input IN of the next-stage shift register GOA, so that the output signal of the previous-stage shift register GOA serves as the input signal of the next-stage shift register GOA. Simultaneously, the input signal of the first-stage shift register GOA may be a trigger signal. Furthermore, in some embodiments, the first-stage shift register GOA may be a dummy register, whose output is not connected to the pixel circuit PC but serves only as the input signal of the next-stage shift register GOA. Any shift register GOA may include multiple transistors and capacitors, which may be 12T2C, 8T2C, 10T3C, or other structures, without particular limitation. At least some of the transistors in the shift register may be polysilicon transistors. Polysilicon transistors can achieve good mobility and electrical characteristics in a smaller size, thereby reducing the space occupied while maintaining good electrical characteristics. This helps reduce the width of the peripheral area, narrow the border, and increase the screen-to-body ratio.

[0135] As shown in FIG4 , the peripheral circuit can be connected to the light-emitting device LD via the pixel circuit PC and apply a first power supply signal to the first electrode ANO of the light-emitting device LD. The number of peripheral circuits can be multiple and divided into multiple categories for scanning the transistors in the pixel circuit. Taking the above-mentioned 5T1C pixel circuit as an example, the peripheral circuit may include a gate drive circuit for scanning some transistors in the pixel circuit PC (e.g., at least one of the write transistor M1, the first reset transistor M2, and the second reset transistor M3), that is, outputting a write scan signal Gate1, a first reset scan signal Gate2, and a second reset scan signal Gate3 to the gates of the write transistor M1, the first reset transistor M2, and the second reset transistor M3. The peripheral circuit may also include a light-emitting drive circuit, which can be used to scan the light-emitting control transistor M4, that is, outputting a light-emitting scan signal EM to the gate of the light-emitting control transistor M4. The write scan signal Gate1, the first reset scan signal Gate2, the second reset scan signal Gate3, and the light-emitting scan signal EM are all scan signals output by the peripheral circuit. The scan signals output by the above-mentioned gate drive circuit and the light-emitting drive circuit can control the conduction and shutdown of the transistors in the pixel circuit PC, that is, scan the pixel circuit PC.

[0136] The output signal of the output end of the shift register GOA includes the above-mentioned scanning signal, and the gates of some transistors of a row of pixel circuits PC can be connected to the output end of the first-level shift register GOA; of course, the first-level shift register GOA can be connected to multiple rows of pixel circuits PC and scan multiple rows of pixel circuits PC at the same time, but the output signal of the same shift register GOA may have different effects in different rows of pixel circuits PC. For example, when the pixel circuit PC in the i-th row is in the writing stage, the pixel circuit PC in the i+1-th row is in the first reset stage, where i is a positive integer.

[0137] In addition, as shown in FIG5 , in some embodiments, the shift register GOA may have two output terminals, for example, a first output terminal Gout1 and a second output terminal Gout2, wherein the output signal of the first output terminal Gout1 is a scanning signal for scanning the pixel circuit PC. The second output terminal Gout2 may be connected to the input terminal IN of the next-stage shift register GOA. The output signal of the second output terminal Gout2 serves as the input signal of the next-stage shift register and does not scan the pixel circuit.

[0138] The following is an example of a shift register GOA:

[0139] As shown in FIG1 and FIG5 , the shift register may include an input circuit 10, a first control circuit 20, a second control circuit 30, a first output circuit 40, and a second output circuit 50, wherein:

[0140] The input circuit 10 is connected to the first node N11 of the input terminal IN and the first clock signal line CKL1 providing the first clock signal CK1 , and is configured to transmit the input signal of the input terminal IN to the first node N11 in response to the first clock signal CK1 .

[0141] The first control circuit 20 is connected to the first node N11, the second node N12, the first clock signal line CKL1 and the first voltage line VGLL1 providing the first voltage VGL1, and is used to control the voltage of the second node N12 in response to the first clock signal CK1, the first voltage VGL1 and the voltage of the first node N11.

[0142] The second control circuit 30 is connected to the first node N11, the second node N12, the second voltage line VGHL providing the second voltage VGH and the second clock signal line CBL1 providing the second clock signal CB1, and is used to control the voltage of the first node N11 in response to the second clock signal CB1, the second voltage VGH and the voltage of the second node N12.

[0143] The first output circuit 40 is connected to a first node N11, a second node N12, a third voltage line VGLL2 that provides a third voltage VGL2, a third clock signal line CKL2 that provides a third clock signal CK2, and a first output terminal Gout1. The first output circuit 40 is configured to output the third voltage VGL2 or the third clock signal CK2 from the first output terminal Gout1 under the control of the voltages of the first node N11 and the second node N12. The output signal of the first output terminal Gout1 is a scanning signal that can be used to scan at least a portion of the transistors in each pixel circuit in at least one row of pixel circuits.

[0144] Furthermore, as shown in FIG5 , in some embodiments of the present disclosure, the first output circuit 40 may include a first output sub-circuit 401 and a second output sub-circuit 402 , wherein:

[0145] The first output sub-circuit 401 is connected to the first node N11 , the first output terminal Gout1 and the third clock signal line CKL2 , and is used to control the first output terminal Gout1 and the third clock signal line CKL2 to be turned on or off under the control of the voltage of the first node N11 .

[0146] The second output sub-circuit 402 is connected to the second node N12 , the third voltage line VGLL2 and the first output terminal Gout1 , and is configured to control the first output terminal Gout1 and the third voltage line VGLL2 to be turned on or off in response to the voltage of the second node N12 .

[0147] For example, the third voltage VGL2 of the third voltage line VGLL2 can be a high-level signal; the third clock signal CK2 is a pulse signal, which has low and high levels. By controlling the first output terminal Gout1 and the third clock signal line CKL2 to be turned on or off, the output signal of the first output terminal Gout1 can be made high or low.

[0148] In some embodiments of the present disclosure, as shown in FIG5 , the shift register GOA may further include a second output circuit 50, which is connected to the first node N11, the second node N12, the second voltage line VGHL, the second clock signal line CBL1, and the second output terminal Gout2, and is configured to output the second voltage VGH or the second clock signal CB1 from the second output terminal Gout2 under the control of the voltages of the first node N11 and the second node N12. The second output terminal Gout2 may be connected to the input terminal IN of the next-stage shift register, and the output signal of the second output terminal Gout2 serves as the input signal of the next-stage shift register.

[0149] Furthermore, as shown in FIG5 , the second output circuit 50 may include a third output sub-circuit 501 and a fourth output sub-circuit 502 , wherein:

[0150] The third output sub-circuit 501 is connected to the first node N11, the second voltage line VGHL and the second output terminal Gout2, and is used to control the second output terminal Gout2 and the second clock signal line CBL1 to be turned on or off in response to the voltage of the first node N11;

[0151] The fourth output sub-circuit 502 is connected to the second node N12 and the second output terminal Gout2 and is configured to control the second output terminal Gout2 and the second voltage line VGHL to be turned on or off in response to the voltage of the second node N12 .

[0152] For example, the second voltage VGH of the second voltage line VGHL can be a high level; the second clock signal CB1 is a pulse signal, which has a low level and a high level. By controlling the second output terminal Gout2 and the second clock signal line CBL1 to be turned on or off, the output signal of the second output terminal Gout2 can be made high level or low level.

[0153] In some embodiments of the present disclosure, the shift register GOA may further include a first isolation circuit 60 and a second isolation circuit 70, wherein:

[0154] The first isolation circuit 60 connects the first node N11 and the first output sub-circuit 401 and is also connected to the first voltage line VGLL1. The first isolation circuit 60 isolates the first node N11 from direct signal transmission to the first output sub-circuit 401, thereby isolating the first output sub-circuit 401 from the effects of fluctuations in the first clock signal CK1, thereby maintaining stability.

[0155] The second isolation circuit 70 connects the first node N11 and the third output sub-circuit 501 and is also connected to the first voltage line VGLL1. The second isolation circuit 70 isolates the first node N11 from direct signal transmission to the third output sub-circuit 501, thereby isolating the third output sub-circuit 501 from the effects of fluctuations in the first clock signal CK1, thereby maintaining stability.

[0156] Furthermore, in some embodiments of the present disclosure, the third output sub-circuit 501 may be connected to the first node N11 via the third node N13. The shift register may further include a third control circuit 80, which may be connected to the first node N11, the third node N13, and a fourth voltage line VGLL3 providing a fourth voltage VGL3. The third control circuit 80 may control the voltage of the first node N11 in response to the voltage of the third node N13 and the fourth voltage VGL3.

[0157] The specific structure of the above-mentioned shift register is exemplified below:

[0158] As shown in FIG5 , the input circuit 10 includes an input transistor T1 , wherein the gate of the input transistor T1 is connected to the first clock signal line CKL1 , the first electrode is connected to the input terminal, and the second electrode is connected to the first node N11 .

[0159] The first control circuit 20 includes a first control transistor T3 and a second control transistor T2. The gate of the first control transistor T3 is connected to the first clock signal line CKL1, the first electrode is connected to the first voltage line VGLL1, and the second electrode is connected to the second node N12; the gate of the second control transistor T2 is connected to the first node N11, the first electrode is connected to the first clock signal line CKL1, and the second electrode is connected to the second node N12.

[0160] The second control circuit 30 includes a third control transistor T6 and a fourth control transistor T7. The gate of the third control transistor T6 is connected to the second node N12, the first electrode is connected to the second voltage line VGHL, the second electrode is connected to the first electrode of the fourth control transistor T7, the second electrode of the fourth control transistor T7 is connected to the first node N11, and the gate of the fourth control transistor T7 is connected to the second clock signal line CBL1.

[0161] The first output sub-circuit 401 includes a first output transistor T9, and the first isolation circuit 60 includes a first isolation transistor T12; the gate of the first isolation transistor T12 is connected to the first voltage line VGLL1, the first electrode is connected to the first node N11, and the second electrode is connected to the gate of the first output transistor T9; the first electrode of the first output transistor T9 is connected to the third clock signal line CKL2, and the second electrode of the first output transistor T9 is connected to the first output end Gout1.

[0162] The second output sub-circuit 402 includes a second output transistor T10 and a first capacitor C1. The gate of the second output transistor T10 is connected to the second node N12, the first electrode is connected to the third voltage line VGLL2, and the second electrode is connected to the first output terminal Gout1; the first capacitor C1 is connected to the gate and the first electrode of the second output transistor T10.

[0163] The third output sub-circuit 501 includes a third output transistor T5 and a second capacitor C2, and the second isolation circuit 70 includes a second isolation transistor T8; the gate of the second isolation transistor T8 is connected to the first voltage line VGLL1, the first electrode is connected to the first node N11, and the second electrode is connected to the third node N13; the gate of the third output transistor T5 is connected to the third node N13, the first electrode is connected to the second clock signal line CBL1, and the second electrode is connected to the second output end Gout2; the second capacitor C2 is connected to the gate and the second electrode of the third output transistor T5.

[0164] The fourth output sub-circuit 502 includes a fourth output transistor T4 , wherein the gate of the fourth output transistor T4 is connected to the second node N12 , the first electrode is connected to the second voltage line VGHL, and the second electrode is connected to the second output terminal Gout2 .

[0165] The third control circuit 80 includes a fifth control transistor T11 . The fifth control transistor T11 has a gate connected to the third node N13 , a first electrode connected to the fourth voltage line VGLL3 , and a second electrode connected to the first node N11 .

[0166] The driving method of the above shift register is described in detail below:

[0167] As shown in Figures 6 and 7, in the first stage t11, the first clock signal CK1 is at a low level, the second clock signal CB1 is at a high level, the third clock signal CK2 is at a low level, and the input signal is at a high level; the first voltage VGL1, the third voltage VGL2 and the fourth voltage VGL3 can be the same low level, and of course, can also be different low levels.

[0168] The input transistor T1, the first control transistor T3, and the fourth control transistor T7 are turned on, and the first isolation transistor T12 and the second isolation transistor T8 are always on; the input signal is transmitted to the first node N11 and the third node N13, causing the second control transistor T2, the fourth output transistor T4, the first output transistor T9, and the fifth control transistor T11 to be turned off; the first voltage VGL1 is transmitted to the second node N12 and charges the first capacitor C1, causing the third control transistor T6, the second output transistor T10, and the fourth output transistor T4 to be turned on; at this time, the voltage of the output signal of the first output terminal Gout1 is the first voltage VGL1; the voltage of the output signal of the second output terminal Gout2 is the second voltage VGH.

[0169] As shown in FIG6 and FIG8, in the second phase t12, the first clock signal CK1 is at a high level, the second clock signal CB1 is at a low level, the third clock signal CK2 is at a high level, and the input signal is at a high level;

[0170] The input transistor T1 and the first control transistor T3 are turned off, while the fourth control transistor T7 is turned on. The first isolation transistor T12 and the second isolation transistor T8 are constantly on. Under the action of the second capacitor C2, the first node N11, the second node N12, and the third node N13 maintain the voltages of the first stage, turning off the second control transistor T2, the fourth control transistor T7, the fifth control transistor T11, and the first output transistor T9. Simultaneously, under the action of the first capacitor C1, the third control transistor T6, the third output transistor T5, and the second output transistor T1010 continue to be turned on, thereby writing the second voltage VGH to the first node N11 and the third node N13, stabilizing the second control transistor T2, the fourth control transistor T7, the fifth control transistor T11, and the first output transistor T9 in the off state. At this point, the voltage of the output signal at the first output terminal Gout1 is the first voltage VGL1, and the voltage of the output signal at the second output terminal Gout2 is the second voltage VGH.

[0171] As shown in FIG6 and FIG9, in the third stage t13, the first clock signal CK1 is at a low level, the second clock signal CB1 is at a high level, the third clock signal CK2 is at a low level, and the input signal is at a low level;

[0172] The input transistor T1 and the first control transistor T3 are turned on, the fourth control transistor T7 is turned off, and the first isolation transistor T12 and the second isolation transistor T8 are always on. The input signal is transmitted to the first node N11 and the third node N13, causing the second control transistor T2, the fourth output transistor T4, the first output transistor T9, and the fifth control transistor T11 to be turned off. The first voltage VGL1 is transmitted to the second node N12 and charges the first capacitor C1, causing the third control transistor T6, the second output transistor T10, and the fourth output transistor T4 to be turned on. At this time, the voltage of the output signal at the first output terminal Gout1 continues to be high due to the first voltage VGL1 and the high-level second clock signal CB1. The voltage of the output signal at the second output terminal Gout2 continues to be low due to the second voltage VGH and the low-level third clock signal CK2.

[0173] As shown in FIG6 and FIG10, in the fourth stage t14, the first clock signal CK1 is at a high level, the second clock signal CB1 is at a low level, the third clock signal CK2 is at a high level, and the input signal is at a high level;

[0174] The input transistor T1 and the first control transistor T3 are turned off, while the fourth control transistor T7 is turned on. The first isolation transistor T12 and the second isolation transistor T8 are always on. Under the action of the second capacitor C2, the first node N11, the second node N12, and the third node N13 maintain the voltage at the third stage, causing the second control transistor T2, the fifth control transistor T11, the third output transistor T5, and the first output transistor T9 to continue to conduct. Simultaneously, the high-level first clock signal CK1 is written to the second node N12, turning off the third control transistor T6, the third output transistor T5, and the second output transistor T1010. At this time, the voltage of the output signal of the first output terminal Gout1 is the high level of the third clock signal CK2, and the voltage of the output signal of the second output terminal Gout2 is the low level of the second clock signal CB1. During this process, the fifth control transistor T11 writes the fourth voltage VGL3 of the fourth voltage line VGLL3 to the first node N11 and the third node N13, acting as a voltage regulator and keeping the first output transistor T9 and the fourth output transistor T4 stably conducting.

[0175] It should be noted that although the steps of the driving method of the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0176] The following is an exemplary description of the film layer of the driving backplane BP:

[0177] As shown in FIG2 , the driving backplane BP may include a substrate SU and a light shielding layer BSM, a polysilicon semiconductor layer SE, a first gate layer GA1, a second gate layer GA2, an oxide semiconductor layer IG, a third gate layer GA3, a first source and drain layer SD1, and a second source and drain layer SD2, which are sequentially distributed in a direction away from the substrate SU.

[0178] The light shielding layer BSM is disposed on one side of the substrate SU and can be made of metal or other conductive and light shielding materials. The light shielding layer BSM can at least overlap with the driving transistor M5 to prevent the bottom signal and light from affecting the driving transistor M5.

[0179] The polysilicon semiconductor layer SE is disposed on a side of the light shielding layer BSM away from the substrate SU. The polysilicon semiconductor layer SE may be made of polysilicon and may be manufactured using a low-temperature polysilicon process. The polysilicon semiconductor layer SE may include active portions of transistors of the shift register GOA.

[0180] The first gate layer GA1 is disposed on a side of the polysilicon semiconductor layer SE away from the substrate SU. The first gate layer GA1 may include first plates of the first capacitor C1 and the second capacitor C2 in the shift register GOA and gates of some transistors.

[0181] The second gate layer GA2 is disposed on a side of the first gate layer GA1 away from the substrate SU, and includes second plates of the first capacitor C1 and the second capacitor C2 of the shift register GOA.

[0182] The oxide semiconductor layer IG may be disposed on a side of the second gate layer GA2 away from the substrate SU. The material thereof may be a metal oxide such as IGZO (indium gallium zinc oxide). The oxide semiconductor layer IG may include active portions of transistors of the pixel circuit PC.

[0183] The third gate layer GA3 may be disposed on a side of the oxide semiconductor layer IG away from the substrate SU and overlap the oxide semiconductor layer IG. The third gate layer GA3 may include gates of at least some transistors of the pixel circuit PC.

[0184] The first source-drain layer SD1 may be disposed on a side of the third gate layer GA3 away from the substrate SU, and may be connected to some transistors and capacitors.

[0185] The second source / drain layer SD2 is disposed on a side of the first source / drain layer SD1 away from the substrate SU.

[0186] The following describes the pattern of the above-mentioned part of the film layer in the display area AA in conjunction with the pixel circuit PC:

[0187] As shown in Figures 11-14, the light shielding layer BSM may include multiple light shielding portions BS, and the light shielding portions BS may overlap with the channel portion of the driving transistor M5, thereby shielding the driving transistor M5 from light on the side close to the substrate SU, thereby improving the stability of the driving transistor M5. The first gate layer GA1 may include a first plate Cst1 of the storage capacitor Cst.

[0188] As shown in Figures 11-13 and 16, the oxide semiconductor layer IG may include a first oxide semiconductor portion IG1 and a second oxide semiconductor portion IG2 spaced apart along the row direction X, and both the first oxide semiconductor portion IG1 and the second oxide semiconductor portion IG2 extend along the column direction Y. The channels of the first reset transistor M2 and the write transistor M1 are located in the first oxide semiconductor portion IG1 along the column direction Y. The channels of the emission control transistor M4, the drive transistor M5, and the second reset transistor M3 are located in the second oxide semiconductor portion IG2 along the column direction Y, with the channel of the drive transistor M5 located between the channels of the emission control transistor M4 and the second reset transistor M3. The channel of the drive transistor M5 protrudes toward both sides of the second oxide semiconductor portion IG2 along the row direction X, thereby increasing the width-to-length ratio of the drive transistor M5 and facilitating increased output current.

[0189] Each transistor in the pixel circuit can adopt a top gate + bottom gate structure, and the bottom gate and top gate are connected to achieve equipotentiality, which is beneficial to improving the stability of the transistor and obtaining a good SS (subthreshold swing). The bottom gate of each transistor can be located on the second gate layer GA2, and the top gate of each transistor can be located on the third gate layer GA3. For example:

[0190] As shown in Figures 11 to 13 and 15, for the pixel circuit, in addition to the second plate Cst2 of the storage capacitor Cst, the second gate layer GA2 also includes a first pixel gate portion G1, a second pixel gate portion G2, a third pixel gate portion G3, and a fourth pixel gate portion G4; the second gate layer GA2 may include a fifth pixel gate portion G5, a sixth pixel gate portion G6, a seventh pixel gate portion G7, an eighth pixel gate portion G8, and a ninth pixel gate portion G9; wherein:

[0191] On the basis that the first oxide semiconductor portion IG1 and the second oxide semiconductor portion IG2 both extend along the column direction Y, the first pixel gate portion G1 to the ninth pixel gate portion G9 can extend along the row direction X, and the width in the column direction Y is smaller than the length in the row direction X.

[0192] The first pixel gate portion G1 and the fifth pixel gate portion G5 may overlap with the channel portion of the first reset transistor M2, and the first pixel gate portion G1 and the fifth pixel gate portion G5 are connected. The second pixel gate portion G2 and the sixth pixel gate portion G6 may overlap with the channel portion of the write transistor M1, and the second pixel gate portion G2 and the sixth pixel gate portion G6 are connected. The third pixel gate portion G3 and the seventh pixel gate portion G7 may overlap with the channel portion of the emission control transistor M4, and the third pixel gate portion G3 and the seventh pixel gate portion G7 are connected. The fourth pixel gate portion G4 and the eighth pixel gate portion G8 overlap with the channel portion of the second reset transistor M3, and the fourth pixel gate portion G4 and the eighth pixel gate portion G8 are connected. The ninth pixel gate portion G9 overlaps with the channel portion of the drive transistor M5, and the length of the ninth pixel gate portion G9 in the row direction X is greater than the width of the channel portion of the drive transistor M5 in the row direction X. The orthographic projection of the ninth pixel gate portion G9 on the substrate SU is located within the orthographic projections of the second electrode plate Cst2 and the light shielding portion BS on the substrate SU. The ninth pixel gate portion G9 serves as the gate of the driving transistor M5.

[0193] The first reset scan line GL2, the second reset scan line GL3, the write scan line GL1, the emission scan line EML, the first reset signal line VRL, the second reset signal line VIL, the first auxiliary first power line VDLs, and the second auxiliary power line VSLs mentioned above are located on the first source / drain layer SD1. FIG1 schematically illustrates one scan line SL (connected to the first output terminal Gout1) for each shift register GOA. This scan line SL can be any one of the first reset scan line GL2, the second reset scan line GL3, the write scan line GL1, and the emission scan line EML. Of course, one shift register GOA can be connected to multiple scan lines SL.

[0194] As shown in FIG11 to FIG13 and FIG18 , the first source-drain layer SD1 may further include a first connecting portion S1, a second connecting portion S2 and a third connecting portion S3, wherein:

[0195] The first connection portion S1 can be connected to the second electrode of the first reset transistor M2 and the gate of the driving transistor M5 through contact holes respectively. For example, one end of the first connection portion S1 can be connected to the area between the channel portion of the first reset transistor M2 and the write transistor M1 in the first oxide semiconductor portion IG1 through a contact hole, and the other end can be connected to the ninth pixel gate portion G9 through a contact hole.

[0196] Furthermore, the first connecting portion S1 may extend along a straight line, a broken line or a curved trajectory, as long as it can play the aforementioned connecting role; for example, the first connecting portion S1 may include a first connecting segment and a second connecting segment, the first connecting segment may extend along the row direction X, and be located between the first reset scan line GL2 and the ninth pixel gate portion G9, the second connecting segment may extend along the column direction Y, and be located between the first oxide semiconductor portion IG1 and the second oxide semiconductor portion IG2; one end of the first connecting segment is connected to the first oxide semiconductor portion IG1 between the channel portion of the first reset transistor M2 and the write transistor M1 through a contact hole, and the other end is connected to one end of the second connecting segment, and the other end of the second connecting segment is connected to the ninth pixel gate portion G9 through a contact hole.

[0197] The second connection portion S2 can be connected to the second electrode plate Cst2 and the first electrode of the drive transistor M5 through a contact hole. For example, the second connection portion S2 can extend along the row direction X and be located between the write scan line GL1 and the first connection portion S1, with its orthographic projection on the substrate SU located between the ninth pixel gate portion G9 and the orthographic projection of the write scan line GL1 on the substrate SU. Furthermore, the orthographic projection of the second connection portion S2 on the substrate SU can be located within the orthographic projection of the second electrode plate Cst2 on the substrate SU. The second connection portion S2 connects the second electrode plate Cst2 to the second oxide semiconductor portion IG2 between the channel portions of the drive transistor M5 and the second reset transistor M3 through contact holes.

[0198] The third connection portion S3 can be connected to the first electrode of the write transistor M1 and the data line DAL through contact holes, respectively, to realize the transmission of the data signal Data. For example, the third connection portion S3 is located between the second reset scan line GL3 and the second reset signal line VIL, and between the first oxide semiconductor portion IG1 and the second oxide semiconductor portion IG2. The third connection portion S3 is connected to one end of the first oxide semiconductor portion IG1 through a contact hole, and this end is located on the side of the channel portion of the write transistor M1 away from the channel portion of the first reset transistor M2. The third connection portion S3 is also connected to the data line DAL through a contact hole.

[0199] The first power line VDL, the second power line, the data line DAL, the first auxiliary reset line and the second auxiliary reset line VILs are located on the second source / drain layer SD2.

[0200] As shown in Figures 11-13 and 19, the second source-drain layer SD2 may further include a transition portion S4, which may be connected to the first electrode of the drive transistor M5 and the second electrode of the second reset transistor M3. For example, the transition portion S4 may be connected to the second connection portion S2 via a contact hole. The transition portion S4 may also be connected to the first electrode ANO of the light-emitting device LD via a contact hole.

[0201] The following describes the pattern of the above-mentioned film layer in the display area in conjunction with the shift register GOA:

[0202] As shown in Figures 20, 21, 27 and 28, in some embodiments of the present disclosure, the orthographic projections of the first clock signal line CKL1, the second clock signal line CBL1, the second voltage line VGHL, the first voltage line VGLL1, the fourth voltage line VGLL3, the third clock signal line CKL2 and the third voltage line VGLL2 on the substrate SU all extend along the column direction Y and are spaced apart along the row direction X, and the first clock signal line CKL1, the second clock signal line CBL1, the second voltage line VGHL, the first voltage line VGLL1, the fourth voltage line VGLL3, the third clock signal line CKL2 and the third voltage line VGLL2 are arranged in sequence along the direction toward the display area.

[0203] As shown in Figures 20 to 23, 27 and 28, in a shift register GOA, the first output transistor T9 and the second output transistor T10 are located between the third voltage line VGLL2 and the positive projection of the pixel circuit PC on the substrate SU, and the positive projections of other transistors and the first capacitor C1 on the substrate SU are located between the second voltage line VGHL and the positive projection of the third clock signal line CKL2 on the substrate SU.

[0204] The orthographic projections of the channel portions of the input transistor T1, the first control transistor T3, the second control transistor T2, the third control transistor T6 and the fourth control transistor T7 on the substrate SU are located between the orthographic projections of the first voltage line VGLL1 and the second voltage line VGHL on the substrate SU;

[0205] The orthographic projections of the third output transistor T5 , the fourth output transistor T4 , the fifth control transistor T11 , the first isolation transistor T12 , the second isolation transistor T8 and the first capacitor C1 on the substrate SU are located between the orthographic projections of the first voltage line VGLL1 and the fourth voltage line VGLL3 on the substrate SU.

[0206] The first clock signal line CKL1, the second clock signal line CBL1, the third clock signal line CKL2, the first voltage line VGLL1, the second voltage line VGHL, the third voltage line VGLL2 and the fourth voltage line VGLL3 all extend along the column direction Y and are spaced apart in the first source and drain layer SD1 and the second source and drain layer SD2 along the row direction X. For example, the first clock signal line CKL1, the second clock signal line CBL1, the third clock signal line CKL2, the first voltage line VGLL1, the second voltage line VGHL and the third voltage line VGLL2 in the above text are located in the first source and drain layer SD1; the fourth voltage line VGLL3 is located in the second source and drain layer SD2.

[0207] As shown in FIG. 20 to FIG. 23 and FIG. 24 , in some embodiments of the present disclosure, the polycrystalline silicon semiconductor layer SE may include a first semiconductor portion SE1, a second semiconductor portion SE2, a third semiconductor portion SE3, a fourth semiconductor portion SE4, a fifth semiconductor portion SE5, a sixth semiconductor portion SE6, a seventh semiconductor portion SE7, an eighth semiconductor portion SE8, and a ninth semiconductor portion SE9, wherein:

[0208] The orthographic projections of the first semiconductor portion SE1, the second semiconductor portion SE2, the third semiconductor portion SE3, and the fourth semiconductor portion SE4 on the substrate SU are located between the orthographic projections of the second voltage line VGHL and the first voltage line VGLL1 on the substrate SU. The first semiconductor portion SE1, the second semiconductor portion SE2, and the third semiconductor portion SE3 are arranged along the row direction X; the first semiconductor portion SE1 and the fourth semiconductor portion SE4 are arranged along the column direction Y.

[0209] The orthographic projections of the fifth semiconductor portion SE5 , the sixth semiconductor portion SE6 , the seventh semiconductor portion SE7 and the eighth semiconductor portion SE8 on the substrate SU are located between the orthographic projections of the first voltage line VGLL1 and the third clock signal line CKL2 on the substrate SU; the fifth semiconductor portion SE5 to the eighth semiconductor portion SE8 are distributed along the column direction Y.

[0210] An orthographic projection of the ninth semiconductor portion SE9 on the substrate SU is located between the third voltage line VGLL2 and the pixel circuit.

[0211] The channel portion of the input transistor is located in the first semiconductor portion SE1; the channel portion of the second control transistor T2 is located in the second semiconductor portion SE2; the channel portion of the first control transistor T3 is located in the second semiconductor portion SE2; the channel portion of the third control transistor T6 and the fourth control transistor T7 are located in the fourth semiconductor portion SE4; the channel portion of the first isolation transistor T12 is located in the fifth semiconductor portion SE5; the channel portion of the second isolation transistor T8 is located in the sixth semiconductor portion SE6; the channel portion of the fifth control transistor T11 is located in the seventh semiconductor portion SE7; the channel portions of the three output transistors and the fourth output transistor T4 are located in the eighth semiconductor portion SE8; the channel portions of the first output transistor T9 and the second output transistor T10 are located in the ninth semiconductor portion SE9.

[0212] As shown in FIG. 20 to FIG. 23 and FIG. 25 , based on the pattern of the polysilicon semiconductor layer SE described above, for example, the first gate layer GA1 may include a first gate portion G11, a second gate portion G12, a third gate portion G13, a fourth gate portion G14, a fifth gate portion G15, a sixth gate portion G16, and a seventh gate portion G17, wherein:

[0213] The first gate portion G11 can extend along the row direction X and overlap with the first semiconductor portion SE1 and the third semiconductor portion SE3, forming the input transistor T1 and the first control transistor T3. The first gate portion G11 is connected to the first clock signal line CKL1 through a contact hole. The area where the first gate portion G11 overlaps with the first semiconductor portion SE1 serves as the gate of the input transistor, and the area where the first gate portion G11 overlaps with the third semiconductor portion SE3 serves as the gate of the first control transistor T3.

[0214] The second gate portion G12 may extend along the row direction X and overlap with the second semiconductor portion SE2 to form the second control transistor T2 . The region where the second gate portion G12 overlaps with the second semiconductor portion SE2 serves as the gate of the second control transistor T2 .

[0215] The third gate portion G13 may extend along the row direction X and overlap with the fourth semiconductor portion SE4 to form the fourth control transistor T7. The third gate portion G13 is connected to the second clock signal line CBL1 through a contact hole. The region where the third gate portion G13 overlaps with the fourth semiconductor portion SE4 serves as the gate of the fourth control transistor T7.

[0216] The fourth gate portion G14 can extend along the row direction X and overlap with the fourth semiconductor portion SE4, the eighth semiconductor portion SE8, and the ninth semiconductor portion SE9, forming the third control transistor T6, the fourth output transistor T4, and the second output transistor T10. The third gate portion G13 includes the first plate of the second capacitor C2. The region where the fourth gate portion G14 overlaps with the fourth semiconductor portion SE4 serves as the gate of the third control transistor T6. The region where the fourth gate portion G14 overlaps with the eighth semiconductor portion SE8 serves as the gate of the fourth output transistor T4. The region where the fourth gate portion G14 overlaps with the ninth semiconductor portion SE9 serves as the gate of the second output transistor T10. The third control transistor T6, the fourth output transistor T4, the first plate of the second capacitor C2, and the second output transistor T10 are sequentially arranged along the direction toward the pixel circuit.

[0217] The fifth gate portion G15 extends at least partially along the column direction Y and overlaps with the fifth semiconductor portion SE5 and the sixth semiconductor portion SE6, forming a first isolation transistor T12 and a second isolation transistor T8. The fifth gate portion G15 is connected to the first voltage line VGLL1 via a contact hole. The region where the fifth gate portion G15 overlaps with the fifth semiconductor portion SE5 serves as the gate of the first isolation transistor T12, while the region where the fifth gate portion G15 overlaps with the sixth semiconductor portion SE6 serves as the gate of the second isolation transistor T8. Furthermore, to facilitate connection to the first voltage line VGLL1, the fifth gate portion G15 extends at least partially along the row direction X. The portion extending along the row direction X is connected to the portion extending along the column direction Y, and the portion extending along the row direction X is connected to the first voltage line VGLL1 via a contact hole.

[0218] The sixth gate portion G16 overlaps with the seventh semiconductor portion SE7 and the eighth semiconductor portion SE8 to form the fifth control transistor T11 and the third output transistor T5. The sixth gate portion G16 includes the first plate of the first capacitor C1. The region where the sixth gate portion G16 overlaps with the seventh semiconductor portion SE7 serves as the gate of the fifth control transistor T11, while the region where the sixth gate portion G16 overlaps with the eighth semiconductor portion SE8 serves as the gate of the third output transistor T5. The orthographic projection of the first plate of the first capacitor C1 on the substrate SU may be located between the orthographic projections of the seventh and eighth semiconductor portions SE7 and SE8 on the substrate SU and the orthographic projection of the third clock signal line CKL2 on the substrate SU, and extends along the column direction Y.

[0219] The sixth gate portion G16 includes a first segment and a second segment extending outward from the edge of the first electrode plate of the first capacitor C1 and distributed along the column direction Y. The first segment includes a first sub-segment extending along the row direction X and a second sub-segment extending along the column direction Y. One end of the first sub-segment is connected to the above-mentioned first electrode plate, and the other end is connected to one end of the second sub-segment. The second sub-segment overlaps with the seventh semiconductor portion SE7 to form the fifth control transistor T11. The second segment of the sixth gate portion G16 overlaps with the eighth semiconductor portion SE8 to form the third output transistor T5.

[0220] The seventh gate portion G17 overlaps with the ninth semiconductor portion SE9 to form the first output transistor T9 ; the region where the seventh gate portion G17 overlaps with the ninth semiconductor portion SE9 is the gate of the first output transistor T9 .

[0221] Furthermore, in some embodiments of the present disclosure, in order to improve the aspect ratio of the first output transistor T9, the second output transistor T10, the third output transistor T5 and the fourth output transistor T4 and increase the current, the width of the eighth semiconductor portion SE8 and the ninth semiconductor portion SE9 in the row direction X can be greater than the width of the first capacitor C1 and the second capacitor C2 in the row direction X, and greater than the width of any one of the first clock signal line CKL1, the second clock signal line CBL1, the second voltage line VGHL, the first voltage line VGLL1, the fourth voltage line VGLL3, the third clock signal line CKL2 and the third voltage line VGLL2 in the row direction X, and greater than the width of the channel portion of the other transistors in the row direction X.

[0222] Furthermore, as shown in FIG. 20 to FIG. 23 , in some embodiments of the present disclosure, the channel portion of at least one of the input transistor T1, the first output transistor T9, and the second output transistor T10 may include at least two channels connected in series to prevent leakage. For example:

[0223] The first gate portion G11 may include two sub-gate portions extending along the row direction X. The two sub-gate portions are distributed and connected along the column direction Y. The two sub-gate portions overlap with the first semiconductor portion SE1 to form two channels of the input transistor. Of course, more sub-gate portions may also be provided.

[0224] The portion where the fourth gate portion G14 overlaps with the ninth semiconductor portion SE9 may include two sub-gate portions extending along the row direction X. The two sub-gate portions are distributed and connected along the column direction Y. The two sub-gate portions also overlap with the ninth semiconductor portion to form two channels of the second output transistor T10. Of course, more sub-gate portions may also be provided.

[0225] The portion where the seventh gate portion G17 overlaps with the ninth semiconductor portion SE9 may include four sub-gate portions extending along the row direction X. The four sub-gate portions are distributed and connected along the column direction Y. The four sub-gate portions simultaneously overlap with the ninth semiconductor portion SE9 to form two channels of the first output transistor T9. Of course, fewer or more sub-gate portions may also be provided.

[0226] As shown in FIG20 to FIG26 , in some embodiments of the present disclosure, the second output terminal Gout2 of the upper-stage shift register in two adjacent stages of shift registers is connected to the input terminal IN of the lower-stage shift register. The wiring connecting the second output terminal Gout2 and the input terminal IN may be distributed on the first source and drain layer SD1 and the first gate layer GA1. For example, the first gate layer GA1 further includes a cascade jumper portion G18, and the first gate layer GA1 may further include a cascade output portion S14 and a cascade line S15, wherein:

[0227] The cascade output portion S14 overlaps with the eighth semiconductor portion SE8 and is connected to the second electrodes of the third output transistor T5 and the fourth output transistor T4 via contact holes. A cascade line S15 extends along the column direction Y, located between the second voltage line VGHL and the first voltage line VGLL1, and is connected to the input terminal IN of the next-stage shift register. The cascade jumper portion G18 extends along the row direction X, overlapping with but insulated from the first voltage line VGLL1. The cascade jumper portion G18 connects the cascade output portion S14 and the cascade line S15 via contact holes. Thus, the cascade output portion S14, the cascade jumper portion G18, and the cascade line S15 form a path connecting the two-stage shift register. The cascade jumper portion G18 and the first voltage line VGLL1 are located on different layers to prevent short circuits.

[0228] As shown in FIG. 20 to FIG. 23 , FIG. 26 and FIG. 27 , the second gate layer GA2 may include a first transfer portion G21 and a second transfer portion G22 ; the first source / drain layer SD1 may include a scan output portion S16 , a first connection portion S11 , a second connection portion S12 and a third connection portion S13 ; wherein:

[0229] The scan output portion S16 may overlap with the ninth semiconductor portion SE9 and be connected to the second electrodes of the first output transistor T9 and the second output transistor T10 through a contact hole. Furthermore, the scan output portion S16 may include a plurality of sub-scan output portions extending along the row direction X and distributed along the column direction Y. Each sub-scan output portion overlaps with the ninth semiconductor portion SE9 and is alternately distributed along the column direction Y with each channel portion of the first output transistor T9 and the second output transistor T10 having multiple channel portions. Each sub-scan output portion is connected to the ninth semiconductor portion SE9 through a contact hole.

[0230] Furthermore, as shown in Figures 20-23, 26 and 27, the second gate layer GA2 may also include a scan transfer part G23, which can be connected to the scan output part S16 through a contact hole, and can be connected to the scan line SL of the scan pixel circuit PC. The scan line SL can be one or more of the first reset scan line GL2, the second reset scan line GL3, the write scan line GL1, and the light-emitting scan line EML.

[0231] The first connection portion S11 may overlap with the ninth semiconductor portion SE9 and be connected to the first electrode of the first output transistor T9 via a contact hole. The first transition portion G21 may extend along the row direction X, overlap with the first connection portion S11 and the third voltage line VGLL2, and connect the third clock signal line CKL2 and the first connection portion S11 via a contact hole, thereby connecting the third clock signal line CKL2 to the first electrode of the first output transistor T9. The first transition portion G21, the first connection portion S11, and the third voltage line VGLL2 are located on different layers to prevent short circuits.

[0232] The second connection portion S12 overlaps with the eighth semiconductor portion SE8 and is connected to the first electrode of the fourth output transistor T4 through a contact hole. The third connection portion S13 is connected to the second voltage line VGHL. The second transition portion G22 extends along the row direction X and overlaps with the first voltage line VGLL1. The second transition portion G22 is connected to the second connection portion S12 and the third connection portion S13 through contact holes. Thus, the second voltage line VGHL and the first electrode of the fourth output transistor T4 are connected through the second connection portion S12, the second transition portion G22, and the third connection portion S13. The second transition portion G22 and the first voltage line VGLL1 are located on different layers to prevent short circuits between them.

[0233] The first source / drain layer SD1 may further include a trigger signal line STVL, which may be connected to the input terminal IN of the first shift register in the cascaded shift register for transmitting a trigger signal. The trigger signal line STVL may extend along the column direction Y and be located on a side of the second clock signal line CBL1 away from the pixel circuit. Furthermore, the first source / drain layer SD1 may further include a fourth clock signal line CBL2, which may be provided between the third clock signal line CKL2 and the third voltage line VGLL2.

[0234] In addition, as shown in Figures 20-23 and 27, the first source and drain layer SD1 may further include a signal transfer portion S17, which may be connected to the gate of the fifth control transistor T11 and may be connected to the fourth voltage line VGLL3 through a contact hole so as to control the fifth control transistor T11 through the fourth voltage VGL3.

[0235] As shown in Figures 20 to 23 and 28, the second source and drain layer SD2 also includes a first auxiliary clock signal line CKL1s, a second auxiliary clock signal line CBL1s, a third auxiliary clock signal line CKL2s and a fourth auxiliary clock signal line CBL2s extending along the column direction Y, and the first auxiliary clock signal line CKL1s, the second auxiliary clock signal line CBL1s, the third auxiliary clock signal line CKL2s and the fourth auxiliary clock signal line CBL2s are spaced apart in sequence along the row direction X toward the pixel circuit.

[0236] The first auxiliary clock signal line CKL1s overlaps and connects with the first clock signal line CKL1, which helps reduce resistance and improve the stability of the first clock signal CK1. The second auxiliary clock signal line CBL1s overlaps and connects with the second clock signal line CBL1, which helps reduce resistance and improve the stability of the second clock signal CB1. The third auxiliary clock signal line CKL2s overlaps and connects with the third clock signal line CKL2, which helps reduce resistance and improve the stability of the third clock signal CK2. The fourth auxiliary clock signal line CBL2s overlaps and connects with the fourth clock signal line CBL2, which helps reduce resistance and improve the stability of the fourth clock signal CB2.

[0237] The present disclosure also provides a display device, which may include a display panel according to any of the above-mentioned embodiments. The display panel is a display panel according to any of the above-mentioned embodiments. Its specific structure and beneficial effects can be referred to in the embodiments of the display panel above, and will not be repeated here. The display device of the present disclosure can be an electronic device such as a mobile phone, tablet computer, or television, or a wearable device with image display function such as a smart watch, virtual reality device, or augmented reality device, or other electronic device with display function such as an in-vehicle display device, which will not be listed one by one here.

[0238] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel having a display area and a peripheral area outside the display area; the display panel comprises: A driving backplane, comprising a pixel circuit located in the display area and a peripheral circuit located in the peripheral area, wherein the peripheral circuit comprises a plurality of cascaded shift registers; the shift register is used to scan at least one row of the pixel circuit; the pixel circuit and the shift register both comprise a plurality of transistors; the transistors of the pixel circuit comprise a driving transistor, and the driving transistor and at least part of other transistors in the pixel circuit are metal oxide transistors; the transistors in the shift register are polysilicon transistors; A plurality of light-emitting devices are arrayed on one side of the driving backplane; the light-emitting devices include a first electrode, a light-emitting layer, and a second electrode stacked in sequence in a direction away from the driving backplane; the first electrode of the driving transistor is connected to the first electrode of the light-emitting device, the second electrode is connected to a first power line transmitting a first power signal, and the second electrode of the light-emitting device is used to receive a second power signal.

2. The display panel according to claim 1, wherein: The pixel circuit also includes a first reset circuit, a second reset circuit and a write circuit; the first reset circuit is connected to the gate of the driving transistor, and is used to transmit a first reset signal in response to a first reset scan signal; the second reset circuit is connected to the first electrode of the driving transistor, and is used to transmit a second reset signal in response to a second reset scan signal; the write circuit is connected to the gate of the driving transistor, and is used to transmit a data signal in response to a write scan signal.

3. The display panel according to claim 2, wherein: The pixel circuit also includes a light-emitting control circuit and a storage capacitor; the first power line is connected to the second electrode of the driving transistor through the light-emitting control circuit, and the light-emitting control circuit is used to be turned on in response to a light-emitting scanning signal; the storage capacitor is connected to the gate and the first electrode of the driving transistor.

4. The display panel according to claim 3, wherein: The first reset circuit includes a first reset transistor, the second reset circuit includes a second reset transistor, the write circuit includes a write transistor, and the light emission control circuit includes a light emission control transistor; The gate of the first reset transistor is used to receive the first reset scan signal, the first electrode is used to receive the first reset signal, and the second electrode is connected to the gate of the driving transistor; the gate of the second reset transistor is used to receive the second reset scan signal, the first electrode is used to receive the first reset signal, and the second electrode is connected to the gate of the driving transistor; The second electrode is connected to the first electrode of the driving transistor for receiving the second reset signal; the gate of the write transistor is used to receive the write scan signal, the first electrode is used to receive the data signal, and the second electrode is connected to the gate of the driving transistor; the gate of the light-emitting control transistor is used to receive the light-emitting scan signal, the first electrode is connected to the first power line, and the second electrode is connected to the second electrode of the driving transistor.

5. The display panel according to claim 3, wherein: The shift register comprises an input circuit, a first control circuit, a second control circuit and a first output circuit; The input circuit is connected to the input terminal, the first node and a first clock signal line providing a first clock signal, and is used to transmit the input signal of the input terminal to the first node in response to the first clock signal; The first control circuit is connected to the first node, the second node, the first clock signal line and a first voltage line providing a first voltage, and is used to control the voltage of the second node in response to the first clock signal, the first voltage and the voltage of the first node; The second control circuit is connected to the first node, the second node, a second voltage line providing a second voltage, and a second clock signal line providing a second clock signal, and is used to control the voltage of the first node in response to the second clock signal, the second voltage, and the voltage of the second node; The first output circuit is connected to the first node, the second node, a third voltage line providing a third voltage, a third clock signal line providing a third clock signal, and the first output terminal, and is used to output the third voltage or the third clock signal from the first output terminal under the control of the voltages of the first node and the second node.

6. The display panel according to claim 5, wherein: The first output circuit includes a first output subcircuit and a second output subcircuit; The first output subcircuit is connected to the first node, the first output terminal and the third clock signal line, and is used to control the first output terminal and the third clock signal line to be turned on or off under the control of the voltage of the first node; The second output subcircuit is connected to the second node, the third voltage line and the first output terminal, and is used to control the first output terminal and the third voltage line to be turned on or off in response to the voltage of the second node.

7. The display panel according to claim 6, wherein: The shift register also includes a second output circuit, which is connected to the first node, the second node, the second voltage line, the second clock signal line and the second output terminal, and is used to output the second voltage or the second clock signal from the second output terminal under the control of the voltages of the first node and the second node.

8. The display panel according to claim 7, wherein: The second output circuit includes a third output sub-circuit and a fourth output sub-circuit; The third output subcircuit is connected to the first node, the second voltage line and the second output terminal, and is used to control the second output terminal and the second clock signal line to be turned on or off in response to the voltage of the first node; The fourth output subcircuit is connected to the second node and the second output terminal, and is used for controlling the second output terminal and the second voltage line to be turned on or off in response to the voltage of the second node.

9. The display panel according to claim 8, wherein: The shift register further includes a first isolation circuit and a second isolation circuit; The first isolation circuit is connected to the first node and the first output sub-circuit, and is connected to the first voltage line; The second isolation circuit is connected to the first node and the third output sub-circuit, and is connected to the first voltage line.

10. The display panel according to claim 9, wherein: The third output subcircuit is connected to the first node via a third node; The shift register further includes a third control circuit connected to the first node, the third node and a fourth voltage line providing a fourth voltage, and configured to control the voltage of the first node in response to the voltage of the third node and the fourth voltage.

11. The display panel according to claim 10, wherein: The input circuit comprises an input transistor, a gate of the input transistor is connected to the first clock signal line, a first electrode is connected to the input terminal, and a second electrode is connected to the first node; The first control circuit includes a first control transistor and a second control transistor, wherein the gate of the first control transistor is connected to the first clock signal line, the first electrode is connected to the first voltage line, and the second electrode is connected to the second node; the gate of the second control transistor is connected to the first node, the first electrode is connected to the first clock signal line, and the second electrode is connected to the second node. Two-node connection; The second control circuit includes a third control transistor and a fourth control transistor, wherein the gate of the third control transistor is connected to the second node, the first electrode is connected to the second voltage line, the second electrode is connected to the first electrode of the fourth control transistor, the second electrode of the fourth control transistor is connected to the first node, and the gate of the fourth control transistor is connected to the second clock signal line; The first output subcircuit includes a first output transistor, and the first isolation circuit includes a first isolation transistor; a gate of the first isolation transistor is connected to the first voltage line, a first electrode is connected to the first node, and a second electrode is connected to the gate of the first output transistor; a first electrode of the first output transistor is connected to the third clock signal line, and a second electrode is connected to the first output terminal; The second output subcircuit includes a second output transistor and a first capacitor, the gate of the second output transistor is connected to the second node, the first electrode is connected to the third voltage line, and the second electrode is connected to the first output end; the first capacitor is connected to the gate and the first electrode of the second output transistor.

12. The display panel according to claim 11, wherein: The third output subcircuit includes a third output transistor and a second capacitor, and the second isolation circuit includes a second isolation transistor; the gate of the second isolation transistor is connected to the first voltage line, the first electrode is connected to the first node, and the second electrode is connected to the third node; the gate of the third output transistor is connected to the third node, the first electrode is connected to the second clock signal line, and the second electrode is connected to the second output terminal; the second capacitor is connected to the gate and the second electrode of the third output transistor; The fourth output subcircuit includes a fourth output transistor, a gate of the fourth output transistor is connected to the second node, a first electrode is connected to the second voltage line, and a second electrode is connected to the second output terminal.

13. The display panel according to claim 12, wherein: The third control circuit includes a fifth control transistor, a gate of the fifth control transistor is connected to the third node, a first electrode is connected to the fourth voltage line, and a second electrode is connected to the first node.

14. The display panel according to claim 13, wherein: The transistors of the pixel circuit are all metal oxide transistors; the transistors of the shift register are all polysilicon transistors.

15. The display panel according to claim 14, wherein: The driving backplane comprises a substrate and a light shielding layer, a polysilicon semiconductor layer, a first gate layer, a second gate layer, an oxide semiconductor layer, a third gate layer, a first source-drain layer and a second source-drain layer distributed in a direction away from the substrate; the first electrode is arranged on a side of the second source-drain layer away from the substrate; The channel portion of the transistor of the shift register is located in the polysilicon semiconductor layer; the channel portion of each transistor of the pixel circuit is located in the oxide semiconductor layer; The first plates of the first capacitor and the second capacitor are located in the first gate layer, and the second plates are located in the second gate layer; the first plate of the storage capacitor is located in the light shielding layer, and the second plate is located in the second gate layer; The first clock signal line, the second clock signal line, the third clock signal line, the first voltage line, the second voltage line and the third voltage line are located in the first source-drain layer; the fourth voltage line is located in the second source-drain layer.

16. The display panel according to claim 15, wherein: The first clock signal line, the second clock signal line, the second voltage line, the first voltage line, the fourth voltage line, the third clock signal line and the third voltage line are all projected on the substrate along the column direction and are sequentially distributed along the row direction toward the display area; In a shift register, the first output transistor and the second output transistor are located between the third voltage line and the pixel circuit's orthographic projection on the substrate, and the other transistors and the first capacitor's orthographic projection on the substrate are located between the second voltage line and the third clock signal line's orthographic projection on the substrate.

17. The display panel according to claim 16, wherein: The orthographic projections of the channel portions of the input transistor, the first control transistor, the second control transistor, the third control transistor and the fourth control transistor on the substrate are located between the orthographic projections of the first voltage line and the second voltage line on the substrate; The orthographic projections of the third output transistor, the fourth output transistor, the fifth control transistor, the first isolation transistor, the second isolation transistor and the first capacitor on the substrate are located between the orthographic projections of the first voltage line and the third clock signal line on the substrate.

18. The display panel according to claim 15, wherein: A channel portion of at least one of the input transistor, the first output transistor, and the second output transistor includes at least two channels connected in series.

19. The display panel according to claim 16, wherein: The polycrystalline silicon semiconductor layer includes a first semiconductor portion, a second semiconductor portion, a third semiconductor portion, a fourth semiconductor portion, a fifth semiconductor portion, a sixth semiconductor portion, a seventh semiconductor portion, an eighth semiconductor portion and a ninth semiconductor portion; The orthographic projections of the first semiconductor portion to the fourth semiconductor portion on the substrate are located between the orthographic projections of the second voltage line and the first voltage line on the substrate; the first semiconductor portion, the second semiconductor portion and the third semiconductor portion are distributed along the row direction; the first semiconductor portion and the fourth semiconductor portion are distributed along the column direction; The orthographic projections of the fifth semiconductor portion to the eighth semiconductor portion on the substrate are located between the orthographic projections of the first voltage line and the third clock signal line on the substrate; the fifth semiconductor portion to the eighth semiconductor portion are distributed along the column direction; The ninth semiconductor portion is located between the third voltage line and the pixel circuit on an orthographic projection of the substrate; A channel portion of the input transistor is located in the first semiconductor portion; The channel portion of the second control transistor is located in the second semiconductor portion; the channel portion of the first control transistor is located in the second semiconductor portion; the channel portion of the third control transistor and the fourth control transistor are located in the fourth semiconductor portion; the channel portion of the first isolation transistor is located in the fifth semiconductor portion; the channel portion of the second isolation transistor is located in the sixth semiconductor portion; the channel portion of the fifth control transistor is located in the seventh semiconductor portion; the channel portions of the three output transistors and the fourth output transistor are located in the eighth semiconductor portion; and the channel portions of the first output transistor and the second output transistor are located in the ninth semiconductor portion.

20. The display panel according to claim 19, wherein: The first gate layer includes a first gate portion, a second gate portion, a third gate portion, a fourth gate portion, a fifth gate portion, a sixth gate portion, and a seventh gate portion; The first gate portion overlaps with the first semiconductor portion and the third semiconductor portion to form the input transistor and the first control transistor, and the first gate portion is connected to the first clock signal line through a contact hole; The second gate portion overlaps with the second semiconductor portion to form the second control transistor; The third gate portion overlaps with the fourth semiconductor portion to form the fourth control transistor, and the third gate portion is connected to the second clock signal line through a contact hole; The fourth gate portion overlaps with the fourth semiconductor portion, the eighth semiconductor portion and the ninth semiconductor portion to form the third control transistor, the fourth output transistor and the second output transistor; the third gate portion includes a first plate of the second capacitor; The fifth gate portion overlaps with the fifth semiconductor portion and the sixth semiconductor portion to form the first isolation transistor and the second isolation transistor; and the fifth gate portion is connected to the first voltage line through a contact hole; The sixth gate portion overlaps with the seventh semiconductor portion and the eighth semiconductor portion to form the fifth control transistor and the third output transistor; the sixth gate portion includes a first plate of the first capacitor; The seventh gate portion overlaps the ninth semiconductor portion to form the first output transistor.

21. The display panel according to claim 20, wherein: In the shift register, widths of channel portions of the first output transistor, the second output transistor, the third output transistor, and the fourth output transistor in the row direction are greater than widths of channel portions of other transistors in the row direction.

22. The display panel according to claim 20, wherein: The first gate layer further includes a cascade jumper portion; the second gate layer includes a first transfer portion and a second transfer portion; the first source-drain layer includes a scan output portion, a cascade output portion, a cascade line, a first connection portion, a second connection portion and a third connection portion; The scan output portion overlaps with the ninth semiconductor portion and is connected through a contact hole to connect the second electrodes of the first output transistor and the second output transistor; The cascade output portion overlaps with the eighth semiconductor portion and is connected through a contact hole to connect the second electrodes of the third output transistor and the fourth output transistor; the cascade line extends along the column direction and is located between the second voltage line and the first voltage line; the cascade jumper portion extends along the row direction and overlaps with the first voltage line, and the cascade output portion and the cascade line are connected through a contact hole; The first connecting portion overlaps with the ninth semiconductor portion and is connected through a contact hole to connect the first electrode of the first output transistor; the first switching portion extends along the row direction, and overlaps with the first connection portion and the third voltage line, and connects the third clock signal line and the first connection portion through a contact hole; The second connection portion overlaps with the eighth semiconductor portion and is connected through a contact hole to connect to the first electrode of the fourth output transistor; the third connection portion is connected to the second voltage line; the second transfer portion extends along the row direction and overlaps with the first voltage line, and the second transfer portion is connected to the second connection portion and the third connection portion through a contact hole.

23. A display device comprising the display panel according to any one of claims 1 to 22.

Images