Display panel and display device

Abstract

A display panel and a display device, relating to the technical field of display. The display panel comprises a driving backplane (BP) and a light-emitting device (LD); the driving backplane (BP) comprises a plurality of pixel circuits (PC) distributed in an array along a row direction and a column direction; the pixel circuits (PC) each comprise a plurality of transistors, and the transistors in any pixel circuit (PC) include a driving transistor (T5); the driving transistor (T5) and at least some of the other transistors in any pixel circuit (PC) are metal oxide transistors; the driving backplane (BP) comprises a substrate (SU), and a semiconductor layer (SE) and at least one source / drain layer which are distributed in a direction distant from the substrate; channel portions of at least some of the transistors are located in the semiconductor layer (SE); the source / drain layer overlaps with channel portions of at least some of the metal oxide transistors; the light-emitting device (LD) is disposed on one side of the driving backplane (BP), and comprises a first electrode (ANO), a light-emitting layer (EL), and a second electrode (CAT) which are distributed in a direction distant from the driving backplane (BP); and a first electrode of the driving transistor (T5) is connected to the first electrode (ANO) of the light-emitting device (LD).

Description

Display panel and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202311258013.4 filed on September 26, 2023, entitled “Display Panel and Display Device,” and the entire contents of this Chinese patent application are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0004] For display panels that use organic light-emitting diodes as light-emitting devices, the brightness of the light-emitting devices is generally controlled by pixel circuits. If the pixel circuits use metal oxide transistors, they are easily affected by light and may cause threshold voltage shift, affecting picture quality.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0006] Summary of the Invention

[0007] The present disclosure provides a display panel and a display device.

[0008] According to one aspect of the present disclosure, there is provided a display panel, comprising:

[0009] A driving backplane, comprising a plurality of pixel circuits arranged in an array along row and column directions, the pixel circuits comprising a plurality of transistors, and the transistors in any of the pixel circuits comprising a driving transistor; the driving transistor and at least some of the other transistors in any of the pixel circuits being metal oxide transistors; the driving backplane comprising a substrate, a semiconductor layer and at least one source / drain layer arranged in a direction away from the substrate; channel portions of at least some of the transistors being located in the semiconductor layer; and the source / drain layer overlapping with the channel portions of at least some of the metal oxide transistors;

[0010] The light emitting device is arranged on one side of the driving backplane and comprises a first electrode, a light emitting layer and a second electrode distributed in a direction away from the driving backplane; the first electrode of the driving transistor is connected to the first electrode of the light emitting device.

[0011] In an exemplary embodiment of the present disclosure, the pixel circuit further includes a storage capacitor, and the transistor of the pixel circuit further includes a first reset circuit, a second reset circuit, a write circuit, and a light emitting control circuit;

[0012] The first reset circuit is connected to the gate of the driving transistor and is used to transmit a first reset signal in response to a first reset scan signal; the second reset circuit is connected to the first electrode of the driving transistor and is used to transmit a second reset signal in response to a second reset scan signal; the write circuit is connected to the gate of the driving transistor and is used to transmit a data signal in response to a write scan signal; the light-emitting control circuit is used to receive a first power supply signal and is connected to the second electrode of the driving transistor, and is used to be turned on in response to a light-emitting control signal; the storage capacitor is connected to the gate and the first electrode of the driving transistor.

[0013] In an exemplary embodiment of the present disclosure, the driving backplane further includes a first power line and a data line extending along the column direction, and a first reset scan line, a second reset scan line, a write scan line, a light emitting control line, a first reset signal line, and a second reset signal line extending along the row direction;

[0014] The first reset circuit includes a first reset transistor, the second reset circuit includes a second reset transistor, the write circuit includes a write transistor, and the light emitting control circuit includes a light emitting control transistor; each transistor in the pixel circuit is a metal oxide transistor;

[0015] The first reset scan line is connected to the gate of the first reset transistor and is used to transmit the first reset scan signal; the first reset signal line is connected to the gate of the driving transistor through the first reset transistor and is used to transmit the first reset signal;

[0016] The second reset scan line is connected to the gate of the second reset transistor and is used to transmit the second reset scan signal; the second reset signal line is connected to the first electrode of the driving transistor through the second reset transistor and is used to transmit the second reset signal;

[0017] The first power line is connected to the second electrode of the driving transistor through the light emitting control transistor, and is used to transmit the first power signal;

[0018] The write scan line is connected to the gate of the write transistor for transmitting the write scan signal; the data line is connected to the gate of the drive transistor through the write transistor for transmitting the data signal;

[0019] The light emitting control line is connected to the gate of the light emitting control transistor and is used for transmitting the light emitting control signal.

[0020] In an exemplary embodiment of the present disclosure, the driving backplane further includes a second power line extending along the column direction and a first auxiliary power line and a second auxiliary power line extending along the row direction;

[0021] The first auxiliary power line and the first power line are located in different layers and are connected via a contact hole;

[0022] The second power line and the second auxiliary power line are located in different layers and are connected through a contact hole; the second power line is connected to the second electrode for transmitting a second power signal.

[0023] In an exemplary embodiment of the present disclosure, the driving backplane further includes a first auxiliary reset line extending along the column direction, wherein the first auxiliary reset line and the first reset signal line are located in different layers and are connected through a contact hole.

[0024] In an exemplary embodiment of the present disclosure, the driving backplane further includes a second auxiliary reset line extending along the column direction, wherein the second auxiliary reset line and the second reset signal line are located in different layers and are connected through a contact hole.

[0025] In an exemplary embodiment of the present disclosure, one of the data lines is connected to the write transistors of one column of the pixel circuits; one of the first power lines is connected to the light emission control transistors of one column of the pixel circuits;

[0026] The data lines and the first power lines connected to the same column of pixel circuits are defined as a column line group YG. The second power line, one of the first auxiliary reset line and the second auxiliary reset line is provided between two adjacent column line groups.

[0027] In an exemplary embodiment of the present disclosure, a row of pixel circuits is simultaneously connected to a first reset scan line, a second reset scan line, a write scan line, a light emitting control line, a first reset signal line, and a second reset signal line;

[0028] The first reset scan line, the second reset scan line, the write scan line, the light emission control line, the first reset signal line, and the second reset signal line connected to the pixel circuits in the same row are defined as a row line group;

[0029] A first auxiliary power line and a second auxiliary power line are provided between two adjacent row line groups.

[0030] In an exemplary embodiment of the present disclosure, the source-drain layer includes a first source-drain layer and a second source-drain layer distributed in a direction away from the substrate;

[0031] Channel portions of the write transistor and the second reset transistor overlap with the first source-drain layer; channel portions of the first reset transistor and the light emission control transistor overlap with the second source-drain layer.

[0032] In an exemplary embodiment of the present disclosure, the semiconductor layer includes a first semiconductor portion and a second semiconductor portion spaced apart along the row direction, and the first semiconductor portion and the second semiconductor portion extend along the row direction;

[0033] The channel portions of the first reset transistor and the write transistor are located in the first semiconductor portion along the column direction; the channel portions of the light emission control transistor, the drive transistor, and the second reset transistor are located in the second semiconductor portion along the column direction;

[0034] A channel portion of the write transistor overlaps with one of the write scan lines; a channel portion of the second reset transistor overlaps with one of the second reset scan lines;

[0035] The first power line overlaps with channel portions of the second reset transistor, the drive transistor, and the light emission control transistor.

[0036] In an exemplary embodiment of the present disclosure, at least a portion of the second semiconductor portion has a boundary of an orthographic projection of the substrate in the row direction located within a boundary of an orthographic projection of the first power line on the substrate in the row direction.

[0037] In an exemplary embodiment of the present disclosure, a boundary of at least a portion of the second semiconductor portion where the orthographic projection of the substrate is in the row direction is taken as a first boundary, and a boundary of the orthographic projection of the first power line on the substrate in the row direction is taken as a second boundary;

[0038] The first boundary is located inside the second boundary, and a distance between the first boundary and the second boundary is less than 2 μm.

[0039] In an exemplary embodiment of the present disclosure, the first reset scan line, the second reset scan line, the write scan line, the light emitting control line, the first reset signal line, the second reset signal line, the first auxiliary power line, and the second auxiliary power line are located in the first source and drain layer;

[0040] The first power line, the second power line, the data line, the first auxiliary reset line and the second auxiliary reset line are located in the second source and drain layer.

[0041] In an exemplary embodiment of the present disclosure, the driving backplane further includes:

[0042] A light shielding layer is provided on one side of the substrate and includes a light shielding portion; the semiconductor layer is provided on a side of the light shielding layer away from the substrate, the light shielding portion overlaps with the channel portion of the driving transistor, and the light shielding portion is multiplexed as the first plate of the storage capacitor;

[0043] a first gate layer, provided on a side of the light shielding layer away from the substrate, and comprising a second electrode plate of the storage capacitor; the semiconductor layer is provided on a side of the first gate layer away from the substrate, and the first electrode plate overlaps with a channel portion of the driving transistor;

[0044] The second gate layer is provided on a side of the semiconductor layer away from the substrate and overlaps with the channel portion of the driving transistor; the first source and drain layer is provided on a side of the second gate layer away from the substrate.

[0045] In an exemplary embodiment of the present disclosure, the first gate layer further includes a first gate portion, a second gate portion, a third gate portion, and a fourth gate portion; the second gate layer includes a fifth gate portion, a sixth gate portion, a seventh gate portion, an eighth gate portion, and a ninth gate portion;

[0046] The first gate portion and the fifth gate portion overlap with the channel portion of the first reset transistor, and the first gate portion and the fifth gate portion are connected;

[0047] The second gate portion and the sixth gate portion overlap with the channel portion of the write transistor, and the second gate portion and the sixth gate portion are connected;

[0048] The third gate portion and the seventh gate portion overlap with the channel portion of the light emission control transistor, and the third gate portion and the seventh gate portion are connected;

[0049] The fourth gate portion and the eighth gate portion overlap with the channel portion of the second reset transistor, and the fourth gate portion and the eighth gate portion are connected;

[0050] The ninth gate portion overlaps with a channel portion of the driving transistor.

[0051] In an exemplary embodiment of the present disclosure, a boundary between the first gate portion and the fifth gate portion, as projected in the column direction of the substrate, is located within a boundary between the second power line, the first auxiliary reset line, and the second auxiliary reset line, as projected in the column direction of the substrate; and the first gate portion and the fifth gate portion are connected to the first reset scan line.

[0052] The boundary between the orthographic projection of the third gate portion and the seventh gate portion in the column direction of the substrate is located within the boundary of the orthographic projection of the first power line in the column direction of the substrate; and the third gate portion and the seventh gate portion are connected to the light emission control line;

[0053] The boundary between the second gate portion and the sixth gate portion, where the orthographic projection of the substrate is projected in the column direction, is located within the boundary between the orthographic projection of the write scan line and the substrate in the column direction; and the second gate portion and the sixth gate portion are connected to the first reset scan line;

[0054] The boundary between the fourth gate portion and the eighth gate portion in the column direction of the orthographic projection of the substrate is located within the boundary of the second reset scan line in the column direction of the orthographic projection of the substrate; and the fourth gate portion and the eighth gate portion are connected to the second reset scan line.

[0055] In an exemplary embodiment of the present disclosure, a first electrode at least overlaps with a channel portion of the driving transistor.

[0056] In an exemplary embodiment of the present disclosure, the first electrode includes an electrode body and an extension portion connected to an edge of the electrode body, and the extension portion is connected to a first electrode of the driving transistor;

[0057] At least a portion of the first electrode further includes an extension portion connected to an edge of the electrode body, and the extension portion overlaps with a channel portion of the driving transistor;

[0058] The display panel further includes:

[0059] The pixel definition layer is arranged on the same side of the driving backplane as the light-emitting device and has a pixel opening exposing each first electrode; the boundary of the positive projection of the pixel opening on the substrate is located within the boundary of the electrode body of the exposed first electrode.

[0060] In an exemplary embodiment of the present disclosure, at least a portion of the first electrode overlaps with channel portions of a plurality of the driving transistors at the same time.

[0061] According to one aspect of the present disclosure, a display device is provided, comprising any one of the display panels described above.

[0062] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0064] FIG1 is a top view schematic diagram of an embodiment of a display panel disclosed herein.

[0065] FIG2 is a schematic cross-sectional view of an embodiment of a display panel according to the present disclosure.

[0066] FIG. 3 is a schematic diagram of a pixel opening of an embodiment of a display panel according to the present disclosure.

[0067] FIG4 is a schematic diagram of a pixel circuit in an embodiment of a display panel disclosed herein.

[0068] FIG5 is a driving timing diagram of a pixel circuit in an embodiment of a display panel disclosed herein.

[0069] FIG6 is a schematic diagram of a pixel circuit in an initialization stage in an embodiment of a display panel disclosed herein.

[0070] FIG. 7 is a schematic diagram of a pixel circuit in a compensation stage in an embodiment of a display panel disclosed herein.

[0071] FIG8 is a schematic diagram of a pixel circuit in a writing phase in an embodiment of a display panel disclosed herein.

[0072] FIG9 is a schematic diagram of a pixel circuit in a light-emitting stage in an embodiment of a display panel disclosed herein.

[0073] FIG. 10 is a partial top view of an embodiment of a display panel according to the present disclosure.

[0074] FIG11 is a partial top view of the light shielding layer to the second source and drain layer in one embodiment of the display panel disclosed herein.

[0075] FIG12 is a partial top view of the light shielding layer to the first source and drain layer in one embodiment of the display panel disclosed herein.

[0076] FIG13 is a cross-sectional view taken along line AA of FIG12 .

[0077] FIG14 is a cross-sectional view taken along line BB in FIG12 .

[0078] FIG15 is a cross-sectional view taken along line CC in FIG12 .

[0079] FIG16 is a partial top view of the light shielding layer to the second gate layer in one embodiment of the display panel disclosed herein.

[0080] FIG17 is a partial top view of the first gate layer to the second gate layer in one embodiment of the display panel disclosed herein.

[0081] FIG18 is a partial top view of the first gate layer and the semiconductor layer in one embodiment of the display panel disclosed herein.

[0082] FIG19 is a partial top view of the semiconductor layer and the second gate layer in one embodiment of the display panel of the present disclosure.

[0083] FIG20 is a partial top view of a light shielding layer and a first gate layer in one embodiment of a display panel disclosed herein.

[0084] 21 to 26 are partial top views of multiple film layers of the display panel of the present disclosure.

[0085] FIG. 27 is a top view of a first electrode in an embodiment of a display panel according to the present disclosure.

[0086] FIG. 28 is a partial top view of a first power line and a second semiconductor portion in one embodiment of a display panel according to the present disclosure.

[0087] FIG29 is a partial top view of another embodiment of the display panel disclosed herein.

[0088] FIG30 is a partial top view of the light shielding layer to the second source and drain layer in another embodiment of the display panel disclosed herein. DETAILED DESCRIPTION

[0089] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0090] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0091] The row direction X and the column direction Y herein are two intersecting directions, which may be perpendicular to each other. In the drawings of this disclosure, the row direction X is horizontal and the column direction Y is vertical, but this is not limiting. Those skilled in the art will appreciate that if the display panel is rotated, the actual orientations of the row direction X and the column direction Y may change.

[0092] In this context, "A and B overlap" means that the orthographic projection of A on the substrate and the orthographic projection of B on the substrate at least partially overlap. Alternatively, the orthographic projections of A and B on a plane parallel to the substrate may at least partially overlap. In this context, "A and B are located in different layers" means that A and B are different film layers formed at different times.

[0093] An embodiment of the present disclosure provides a display panel, as shown in FIG1 , which may include a display area AA and a peripheral area WA located outside the display area AA. The peripheral area WA may be a continuous annular area surrounding the display area AA or a discontinuous area surrounding the display area AA.

[0094] As shown in FIG2 , the display panel may include a driving backplane BP and a plurality of light-emitting devices LD arranged on one side of the driving backplane BP. The light-emitting devices LD may be distributed in an array along the row direction X and the column direction Y. The driving circuit in the driving backplane BP may drive the light-emitting devices LD to emit light to display images.

[0095] As shown in Figures 1 and 2, the light-emitting device LD can be located in the display area AA. It can be an OLED (organic light-emitting diode) made of organic light-emitting materials; it can also be an LED (light-emitting diode) made of inorganic light-emitting materials, such as Micro LED (micrometer light-emitting diode) and Mini LED (sub-millimeter light-emitting diode); it can also be a device such as QLED (quantum dot diode). The specific structure of the light-emitting device LD is not specifically limited here.

[0096] As shown in Figures 2 and 3, taking an OLED as an example, the light-emitting device LD may include a first electrode ANO, a light-emitting layer EL, and a second electrode CAT stacked in sequence away from the driving backplane BP. By applying a first power signal VDD to the first electrode ANO and a second power signal VSS to the second electrode CAT, the light-emitting layer EL can be excited to emit light. The specific principle will not be described in detail here. At the same time, in order to limit the range of the light-emitting device LD, a pixel definition layer PDL can be provided on the driving backplane BP. The pixel definition layer PDL and the first electrode ANO are located on the same surface of the driving backplane BP, and the pixel definition layer PDL can have pixel openings PH that expose each first electrode ANO, so that the range of the light-emitting device LD can be limited by each pixel opening PH.

[0097] The driving circuit may include a pixel circuit PC located in the display area AA and a peripheral circuit located in the peripheral area WA. The pixel circuit PC may be distributed in an array along the row direction X and the column direction Y. A pixel circuit PC may be connected to the first electrode ANO of a light-emitting device LD. Of course, the same pixel circuit PC may also be connected to the first electrodes of multiple light-emitting devices LD.

[0098] The peripheral circuit can be connected to the light-emitting device LD via the pixel circuit PC and apply a first power signal VDD to the first electrode ANO of the light-emitting device LD. The peripheral circuit can also include a gate drive circuit and a light-emitting drive circuit for scanning the pixel circuit PC. Simultaneously, the peripheral circuit can also be connected to the second electrode CAT of the light-emitting device LD and apply a second power signal VSS to the second electrode CAT. The pixel circuit PC can control the current passing through the light-emitting device LD, thereby controlling the brightness of the light-emitting device LD.

[0099] The pixel circuit PC may include multiple transistors. Each of the pixel circuits PC includes at least a driving transistor T5. The driving transistor T5 may be a metal oxide transistor. At least a portion of the other transistors may also be metal oxide transistors. Of course, only the driving transistor T5 may be a metal oxide transistor. A metal oxide transistor is one whose active layer is made of materials such as IGZO (Indium Gallium Zinc Oxide) or IZO (Indium Zinc Oxide). The active layer of the transistor includes a channel and a conductor connected to the channel.

[0100] Each transistor can include a gate, a first electrode, and a second electrode. The first electrode and the second electrode can be turned on and off by controlling the voltage of the gate. The first electrode can be a source, and the second electrode can be a drain. Of course, the first electrode can also be a drain, and the second electrode can also be a source. Specifically, if the signal is input through the first electrode, the first electrode becomes the source and the second electrode becomes the drain. If the signal is input through the second electrode, the second electrode becomes the source and the first electrode becomes the drain. In other words, the source and drain can be interchanged depending on the input signal.

[0101] For a P-type transistor, when the gate receives a high level, the first and second electrodes are turned off; when the gate receives a low level, the first and second electrodes are turned on. For an N-type transistor, when the gate receives a high level, the first and second electrodes are turned on; when the gate receives a low level, the first and second electrodes are turned off.

[0102] Taking a pixel circuit PC as an example, as shown in FIG4 , the pixel circuit PC may include a driving transistor T5, a writing circuit 1, a first reset circuit 2, a second reset circuit 3 and a light emitting control circuit 4, wherein:

[0103] The first reset circuit 2 is connected to the gate of the driving transistor T5 and can be turned on or off in response to the first reset scan signal Gate2. The first reset circuit 2 can receive the first reset signal Vref and transmit the first reset signal Vref when turned on.

[0104] The second reset circuit 3 is connected to the first electrode of the driving transistor T5 and can be turned on or off in response to the second reset scan signal Gate3. The second reset circuit 3 can receive the second reset signal Vinit and transmit the second reset signal Vinit when turned on.

[0105] The write circuit 1 is connected to the gate of the driving transistor T5 and can be turned on or off in response to a write scan signal Gate1 . The write circuit 1 can receive a data signal Data and transmit the data signal Data when turned on.

[0106] The light-emitting control circuit 4 can receive a first power supply signal VDD and is connected to the second electrode of the driving transistor T5. The light-emitting control circuit 4 can be turned on or off in response to the light-emitting control signal EM. When turned on, the light-emitting control circuit 4 can transmit the first power supply signal VDD to the driving transistor T5. The storage capacitor Cst is connected to the gate and the first electrode of the driving transistor T5.

[0107] Furthermore, in some embodiments of the present disclosure, as shown in Figures 1, 4, 11, and 12, the pixel circuit PC has a 5T1C structure, where T represents five transistors and one capacitor. Specifically, the first reset circuit 2 includes a first reset transistor T2, the second reset circuit 3 includes a second reset transistor T3, the write circuit 1 includes a write transistor T1, and the emission control circuit 4 includes an emission control transistor T4. Each transistor in the pixel circuit PC is a metal oxide transistor. To facilitate signal transmission, the driver backplane BP may further include a first power line VDL, a data line DAL, a first reset scan line GL2, a second reset scan line GL3, a write scan line GL1, an emission control line EML, a first reset signal line VRL, and a second reset signal line VIL. The first power line VDL and the data line DAL may extend in the column direction Y and may be distributed in the row direction X. The first reset scan line GL2, the second reset scan line GL3, the write scan line GL1, the emission control line EML, the first reset signal line VRL, and the second reset signal line VIL may extend in the row direction X and may be distributed in the column direction Y.

[0108] The first reset scan line GL2 is connected to the gate of the first reset transistor T2 and is used to transmit a first reset scan signal Gate2. The first reset signal line VRL is connected to the first electrode of the first reset transistor T2 and can transmit the first reset signal Vref. The second electrode of the first reset transistor T2 is connected to the gate of the drive transistor T5 and is connected to the N1 node. The first reset scan signal Gate2 can control the first reset transistor T2 to be turned on or off. When turned on, the first reset signal Vref is transmitted to the gate of the drive transistor T5 through the first reset transistor T2, that is, the first reset signal Vref is transmitted to the N1 node.

[0109] The second reset scan line GL3 is connected to the gate of the second reset transistor T3 and is used to transmit a second reset scan signal Gate3. The second reset signal line VIL is connected to the first electrode of the second reset transistor T3 and can transmit a second reset signal Vinit. The second electrode of the second reset transistor T3 is connected to the first electrode of the drive transistor T5 and can be connected to the N3 node. The second reset scan signal Gate3 can control the second reset transistor T3 to be turned on or off. When turned on, the second reset signal Vinit is transmitted through the second reset transistor T3 to the first electrode of the drive transistor T5, that is, the second reset signal Vinit is transmitted to the N3 node.

[0110] The emission control line EML is connected to the gate of the emission control transistor T4 and is used to transmit the emission control signal EM. The first power line VDL is connected to the first electrode of the emission control transistor T4. The second electrode of the emission control transistor T4 is connected to the second electrode of the drive transistor T5 and can be connected to the N2 node. The first power line VDL is used to transmit the first power signal VDD. The emission control signal EM can be used to turn the emission control transistor T4 on or off. When on, the first power signal VDD is transmitted through the emission control transistor T4 to the second electrode of the drive transistor T5.

[0111] The write scan line GL1 is connected to the gate of the write transistor T1 and is used to transmit the write scan signal Gate1. The data line DAL is connected to the first electrode of the write transistor T1 and can transmit the data signal Data. The second electrode of the write transistor T1 is connected to the gate of the drive transistor T5 and can be connected to the N1 node. The write scan signal Gate1 can control the turn-on and turn-off of the write transistor T1. When the write transistor T1 is turned on, the data signal Data is transmitted to the gate of the drive transistor T5 through the write transistor T1, that is, the data signal Data is transmitted to the N1 node.

[0112] Meanwhile, the storage capacitor Cst has a first plate Cst1 and a second plate Cst2 facing each other. The first plate Cst1 is connected to the first electrode of the driving transistor T5 and can be connected to the N3 node. The second plate Cst2 is connected to the gate of the driving transistor T5 and can be connected to the N1 node. The first electrode of the driving transistor T5 and the second electrode of the second reset transistor T3 can be connected to the first electrode ANO of the light-emitting device and can be connected to the N3 node.

[0113] In some embodiments of the present disclosure, as shown in FIG1 , FIG11 and FIG12 , the driving backplane BP further includes a second power line VSL, a first auxiliary power line VDLs and a second auxiliary power line VSLs, wherein:

[0114] The second power line VSL may extend along the column direction Y and may be multiple and distributed along the row direction X. Alternatively, there may be only one second power line VSL. The second power line VSL is used to transmit the second power signal VSS and may be connected to the second electrode of the light-emitting device. For example, the driver backplane BP may include a first power bus for transmitting the first power signal VDD and a second power bus for transmitting the second power signal VSS in the peripheral region. Each first power line VDL may be connected to the first power bus, while the second power line VSL may be connected to the second power bus. Furthermore, the second electrode of the light-emitting device may extend to the peripheral region and be directly or indirectly connected to the second power bus. The second power line VSL and the second power bus may form a single unit that transmits the second power signal VSS. While the second power signal VSS is transmitted to the second electrode via the second power bus, the second power line VSL reduces resistance and voltage drop, thereby facilitating signal stability and uniformity. Of course, in some embodiments, the second power line VSL may not be provided.

[0115] Multiple first auxiliary power lines VDLs can extend along the row direction X. They can be distributed along the column direction Y, or, alternatively, there can be only one. Furthermore, the first auxiliary power lines VDLs can intersect with the first power lines VDL in space, but they can be located on different layers and connected via contact holes. This allows the first auxiliary power lines VDLs and the first power lines VDL to form a network for transmitting the first power signal VDD, which helps reduce resistance, minimize voltage drop, and maintain signal stability and uniformity.

[0116] The second power line VSL can extend along the row direction X. There can be multiple second power lines VSL, distributed along the column direction Y, or there can be only one. Furthermore, the second auxiliary power lines VSLs can intersect with the second power line VSL in space, but be located on different layers and connected via contact holes. This allows the second auxiliary power lines VSLs and the second power line VSL to form a network for transmitting the second power signal VSS, which helps reduce resistance, minimize voltage drop, and maintain signal stability and uniformity.

[0117] Furthermore, in some embodiments of the present disclosure, as shown in Figures 10 to 12 , the driver backplane BP further includes a plurality of first auxiliary reset lines VRLs extending along the column direction Y. The number of first auxiliary reset lines VRLs may be multiple and distributed along the column direction Y, or, alternatively, there may be only one. Furthermore, the first auxiliary reset lines VRLs and the first reset signal line VRL are located on different layers and connected via contact holes, thereby forming a network for transmitting the first reset signal Vref. This helps reduce resistance, minimize voltage drop, and maintain signal stability and uniformity.

[0118] Furthermore, in some embodiments of the present disclosure, as shown in Figures 10 to 12 , the driver backplane BP further includes a plurality of second auxiliary reset lines VILs extending along the column direction Y. These lines may be distributed along the column direction Y, or, alternatively, may be a single line. Furthermore, the second auxiliary reset lines VILs and the second reset signal line VIL are located on different layers and connected via contact holes, thereby forming a network for transmitting the second reset signal Vinit. This helps reduce resistance, minimize voltage drop, and maintain signal stability and uniformity.

[0119] The following is an example of the distribution of the above wiring:

[0120] In some embodiments of the present disclosure, as shown in Figures 1, 11, and 26, a data line DAL is connected to the write transistor T1 of a column of pixel circuits PC; a first power line VDL is connected to the light-emission control transistor T4 of a column of pixel circuits PC. The data line DAL and the first power line VDL connected to the same column of pixel circuits PC can be defined as a column line group YG, meaning each column of pixel circuits PC can be connected to a column line group YG. Furthermore, one of the second power line VSL, the first auxiliary reset line VRLs, and the second auxiliary reset line VILs can be located between two adjacent column line groups YG. In other words, the second power line VSL, the first auxiliary reset line VRLs, and the second auxiliary reset line VILs are distributed in the space between the column line groups YG. Furthermore, two of the second power line VSL, the first auxiliary reset line VRLs, and the second auxiliary reset line VILs can be located on either side of the same column line group YG. This allows for full utilization of space and a more uniform distribution of wiring in the column direction Y.

[0121] For example, as shown in Figures 1, 11, and 26, the second power line VSL, the first auxiliary reset line VRLs, and the second auxiliary reset line VILs can all be defined as auxiliary lines. These auxiliary lines and the aforementioned column line groups YG can be alternately arranged along the row direction X. In the row direction X, if the nth auxiliary line is the second power line VSL, then the n+1th auxiliary line is the second auxiliary reset line VILs, and the n+2th auxiliary line is the first auxiliary reset line VRLs, where n is a positive integer. Of course, the auxiliary lines can also be arranged in other arrangements, which will not be detailed here.

[0122] In some embodiments of the present disclosure, as shown in Figures 1, 12, and 25, a row of pixel circuits PC is simultaneously connected to a first reset scan line GL2, a second reset scan line GL3, a write scan line GL1, an emission control line EML, a first reset signal line VRL, and a second reset signal line VIL. The specific connection relationships have been described above in connection with the pixel circuits PC and will not be repeated here. The first reset scan line GL2, the second reset scan line GL3, the write scan line GL1, the emission control line EML, the first reset signal line VRL, and the second reset signal line VIL connected to the same row of pixel circuits PC can be defined as a row line group XG, i.e., each row of pixel circuits PC is connected to a row line group XG. Furthermore, a first auxiliary power line VDLs and a second auxiliary power line VSLs can be provided between two adjacent row line groups XG. A row line group XG is located between a first auxiliary power line VDLs and a second auxiliary power line VSLs.

[0123] The structure of the pixel circuit PC and its driving method based on the above embodiment are described below:

[0124] As shown in FIG4 , taking the above-mentioned 5T1C structure pixel circuit PC as an example, each transistor is a metal oxide transistor and is an N-type transistor. As shown in FIG5 , the driving method of the embodiment of the present disclosure may include:

[0125] As shown in Figures 5 and 6, during initialization phase t1, the first reset scan signal Gate2 is high, turning on the first reset transistor T2 and the second reset transistor T3. The first reset signal Vref is transmitted to the gate of the driving transistor T5, and the second reset signal Vinit is transmitted to the first electrode of the driving transistor T5 and the first electrode ANO of the light-emitting device, that is, the second reset signal Vinit is transmitted to the N3 node. Simultaneously, the write scan signal Gate1 and the light-emitting control signal EM are low, turning off the write transistor T1 and the light-emitting control transistor T4. The first reset signal Vref and the second reset signal Vinit initialize the gate and first electrode of the driving transistor T5 and the first electrode ANO of the light-emitting device, that is, initialize the N1 and N3 nodes. At this point, the voltage at the N1 node = Vref, and the voltage at the N3 node = Vinit.

[0126] As shown in Figures 5 and 7, during compensation phase t2, the first reset scan signal Gate2 maintains a high level, the second reset scan signal Gate3 is at a low level, the first reset transistor T2 continues to conduct and transmits the first reset signal Vref to the gate of the drive transistor T5, that is, transmits the first reset signal Vref to the N1 node, and the second reset transistor T3 is turned off. Simultaneously, the emission control signal EM is at a high level, and the emission control transistor T4 is turned on.

[0127] When the voltage difference between the first reset signal Vref and the second reset signal Vinit exceeds the threshold voltage of the driving transistor T5, that is, when the voltage difference between the N1 node and the N3 node exceeds the threshold voltage, the driving transistor T5 turns on. The first power supply signal VDD charges the first electrode of the driving transistor T5 until the difference between the first reset signal Vref and the threshold voltage of the driving transistor T5 is reached, that is, when the voltage at the N3 node is Vref-Vth, the driving transistor T5 turns off, thereby writing the threshold voltage to the first electrode of the driving transistor T5. At this time, the voltage at the N1 node = Vref, and the voltage at the N3 node = Vref-Vth.

[0128] As shown in Figures 5 and 8, during write phase t3, the first reset scan signal Gate2, the second reset scan signal Gate3, and the emission control signal EM are all low, and the write scan signal Gate1 is high. The first reset transistor T2, the second reset transistor T3, and the emission control transistor T4 are off, and the write transistor T1 is on. The data signal Data is written to the N1 node via the write transistor T1, i.e., the data signal Data is written to the gate of the drive transistor T5 and the second plate Cst2 of the storage capacitor Cst. At this time, the voltage Vg at the N1 node = Vdata, and the voltage at the N3 node = Vld + Vss = Vref - Vth, where Vld is the voltage of the light-emitting device LD, i.e., the voltage of the capacitor Co of the light-emitting device LD itself.

[0129] As shown in Figures 5 and 9, in the light-emitting stage t4: the light-emitting control signal EM is at a high level, the first reset scan signal Gate2, the second reset scan signal Gate3, and the write scan signal Gate1 are at a low level, the light-emitting control transistor T4 is turned on, and the first reset transistor T2, the second reset transistor T3, and the write transistor T1 are turned off; under the action of the storage capacitor Cst, the driving transistor T5 outputs a current, and the output current satisfies the following formula:

[0130] I=(μWCox / 2L)(Vgs-Vth) 2 ;

[0131] I is the output current of the driving transistor T5; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the channel of the driving transistor T5, and L is the channel length of the driving transistor T5.

[0132] According to the above output current formula, the voltage difference Vgs between the gate voltage and the source voltage of the driving transistor T5 in the pixel circuit PC of the present disclosure is substituted into the above formula to obtain: the output current I of the driving transistor T5 = (μWCox / 2L)(Vgs-Vth) 2

[0133] =(μWCox / 2L)(Vdata-(Vld+VSS)-(Vref-Vld-VSS)) 2

[0134] =(μWCox / 2L)(Vdata-(Vref-Vth)-Vth) 2

[0135] =(μWCox / 2L)(Vdata-Vref) 2

[0136] As can be seen, the threshold voltage compensation phase and the data signal writing phase are performed separately. The output current (i.e., the current of the light-emitting device) is not affected by the voltage of the first power signal VDD or the threshold voltage Vth, but is only affected by Vdata and Vref. The first reset signal Vref has a lower current than the first power signal VDD, minimizing the risk of IR drop.

[0137] In other embodiments of the present disclosure, at least a portion of the transistors other than the driving transistor T5 may be P-type transistors, whose channel portions may be made of polysilicon. These transistors may be turned on at a low level and turned off at a high level.

[0138] The following describes the film layer of the driving backplane BP based on the above-mentioned pixel circuit PC:

[0139] As shown in FIG2 and FIG3 , the driving backplane BP includes a substrate SU, a semiconductor layer SE and at least one source / drain layer, wherein:

[0140] The substrate SU can be made of glass, polyimide or other materials to play a supporting role. At the same time, the substrate SU can adopt a single-layer or multi-layer structure, which is not particularly limited here.

[0141] The semiconductor layer SE is disposed on one side of the substrate SU, and the channel portions of at least some of the transistors are located in the semiconductor layer SE. For example, if each transistor is a metal oxide transistor, the material of the semiconductor layer SE is metal oxide, and the channel portion of each transistor is located in the semiconductor layer SE. Of course, if there are both metal oxide transistors and transistors with channel portions made of polysilicon or other materials, the number of semiconductor layers SE can be multiple, and the channel portions made of different materials can be distributed in different semiconductor layers SE. This article only uses the example of transistors being all metal oxide transistors for illustration.

[0142] The number of source and drain layers is at least one, for example, two. The source and drain layers are located on the side of the semiconductor layer SE away from the substrate SU. The source and drain layers enable connection of at least some transistors and signal transmission. Each source and drain layer can have a single-layer or multi-layer structure, and each layer can be made of a conductive material such as a metal or alloy. For example, the source and drain layers can include three sublayers stacked in a direction away from the substrate SU, with the middle layer made of aluminum and the other two layers made of titanium, thereby forming a titanium / aluminum / titanium structure.

[0143] Furthermore, the driving backplane BP may also include a gate layer, which may overlap with the semiconductor layer SE to form a transistor. The region of the semiconductor layer SE that overlaps with the gate layer serves as the transistor's channel. The non-overlapping region may be conductively connected to form the transistor's first and second electrodes. The region of the gate layer that overlaps with the semiconductor layer SE serves as the transistor's gate. Any transistor may employ a top-gate structure, where its gate is located between the substrate SU and the semiconductor layer SE; a bottom-gate structure, where the gate is located on the side of the semiconductor layer SE away from the substrate SU; or a top-gate + bottom-gate structure, where two gates are located, one between the substrate SU and the semiconductor layer SE and the other on the side of the semiconductor layer SE away from the substrate SU, with the two gates also overlapping.

[0144] In some embodiments of the present disclosure, as shown in FIG. 2 , FIG. 3 , and FIG. 16 to FIG. 24 , the channel portion of each transistor is located in the same semiconductor layer SE, and the driving backplane BP may further include a light shielding layer BSM, a first gate layer GA1, and a second gate layer GA2, wherein:

[0145] As shown in Figure 21, a light shielding layer BSM is disposed on one side of the substrate SU, and a semiconductor layer SE is disposed on the side of the light shielding layer BSM away from the substrate SU. The light shielding layer BSM may include multiple light shielding portions BS, and the light shielding portions BS may overlap with the channel portion of the driving transistor T5, thereby shielding the driving transistor T5 from light on the side closer to the substrate SU, thereby improving the stability of the driving transistor T5.

[0146] As shown in Figure 20, the first gate layer GA1 can be disposed on the side of the light shielding layer BSM away from the substrate SU, the semiconductor layer SE is disposed on the side of the first gate layer GA1 away from the substrate SU, and the second gate layer GA2 is disposed on the side of the semiconductor layer SE away from the substrate SU. The source and drain layers are disposed on the side of the second gate layer GA2 away from the substrate SU.

[0147] As shown in Figures 16 and 20, the light shielding portion BS can be reused as the first plate Cst1 of the storage capacitor Cst. The first gate layer GA1 includes the second plate Cst2 of the storage capacitor Cst. The first plate Cst1 and the second plate Cst2 overlap. Simultaneously, the first plate Cst1 and the second plate Cst2 both overlap with the channel portion of the drive transistor T5. Furthermore, the orthographic projection of the second plate Cst2 on the substrate SU is located within the orthographic projection of the first plate Cst1 on the substrate SU, and the orthographic projection of the channel portion of the drive transistor T5 on the substrate SU is located within the orthographic projection of the light shielding portion BS on the substrate SU.

[0148] Furthermore, as shown in Figures 16-23 , the semiconductor layer SE may include a first semiconductor portion SE1 and a second semiconductor portion SE2 spaced apart along the row direction X, with both the first semiconductor portion SE1 and the second semiconductor portion SE2 extending along the column direction Y. The channels of the first reset transistor T2 and the write transistor T1 are located in the first semiconductor portion SE1 along the column direction Y. The channels of the emission control transistor T4, the drive transistor T5, and the second reset transistor T3 are located in the second semiconductor portion SE2 along the column direction Y, with the channel of the drive transistor T5 located between the channels of the emission control transistor T4 and the second reset transistor T3. The channel of the drive transistor T5 protrudes toward both sides of the second semiconductor portion SE2 along the row direction X, increasing the width-to-length ratio of the drive transistor T5 and facilitating increased output current.

[0149] Each transistor can adopt a top gate + bottom gate structure, and the bottom gate and top gate are connected to achieve equipotentiality, which is beneficial to improving the stability of the transistor and obtaining a good SS (subthreshold swing). The bottom gate of each transistor can be located on the first gate layer GA1, and the top gate of each transistor can be located on the second gate layer GA2. For example:

[0150] As shown in Figures 22 and 24 , in addition to the second plate Cst2 of the storage capacitor Cst, the first gate layer GA1 further includes a first gate portion G1, a second gate portion G2, a third gate portion G3, and a fourth gate portion G4; the second gate layer GA2 may include a fifth gate portion G5, a sixth gate portion G6, a seventh gate portion G7, an eighth gate portion G8, and a ninth gate portion G9; wherein:

[0151] On the basis that the first semiconductor portion SE1 and the second semiconductor portion SE2 extend along the column direction Y, the first to ninth gate portions G1 to G9 may extend along the row direction X, and the width in the column direction Y is smaller than the length in the row direction X.

[0152] As shown in Figures 17-19, the first gate portion G1 and the fifth gate portion G5 may overlap with the channel portion of the first reset transistor T2, and the first gate portion G1 and the fifth gate portion G5 are connected. The second gate portion G2 and the sixth gate portion G6 may overlap with the channel portion of the write transistor T1, and the second gate portion G2 and the sixth gate portion G6 are connected. The third gate portion G3 and the seventh gate portion G7 may overlap with the channel portion of the light emission control transistor T4, and the third gate portion G3 and the seventh gate portion G7 are connected. The fourth gate portion G4 and the eighth gate portion G8 overlap with the channel portion of the second reset transistor T3, and the fourth gate portion G4 and the eighth gate portion G8 are connected. The ninth gate portion G9 overlaps with the channel portion of the drive transistor T5, and the length of the ninth gate portion G9 in the row direction X is greater than the width of the channel portion of the drive transistor T5 in the row direction X. The orthographic projection of the ninth gate portion G9 on the substrate SU is located within the orthographic projections of the second electrode plate Cst2 and the light shielding portion BS on the substrate SU, and the ninth gate portion G9 serves as the gate of the driving transistor T5.

[0153] As shown in Figures 2, 10-12, 25, and 26, the source / drain layer includes a first source / drain layer SD1 and a second source / drain layer SD2, extending away from the substrate SU. The first source / drain layer SD1 is located on the side of the second source / drain layer SD2 away from the substrate SU, while the second source / drain layer SD2 is located on the side of the first source / drain layer SD1 away from the substrate SU. The first reset scan line GL2, second reset scan line GL3, write scan line GL1, emission control line EML, first reset signal line VRL, second reset signal line VIL, first auxiliary power lines VDLs, and second auxiliary power lines VSLs are located on the first source / drain layer SD1. The first power line VDL, second power line VSL, data line DAL, first auxiliary reset lines VRLs, and second auxiliary reset lines VILs are located on the second source / drain layer SD2.

[0154] Furthermore, as shown in FIG. 10 , FIG. 12 and FIG. 25 , the first source / drain layer SD1 may further include a first connection portion S1 , a second connection portion S2 and a third connection portion S3 , wherein:

[0155] The first connection portion S1 can be connected to the second electrode of the first reset transistor T2 and the gate of the driving transistor T5 through contact holes respectively. For example, one end of the first connection portion S1 can be connected to the area between the channel portion of the first reset transistor T2 and the write transistor T1 in the first semiconductor portion SE1 through a contact hole, and the other end can be connected to the ninth gate portion G9 through a contact hole.

[0156] Furthermore, as shown in Figures 12, 14 and 16, the first connecting portion S1 may extend along a straight line, a broken line or a curved trajectory, as long as it can play the aforementioned connection role; for example, the first connecting portion S1 may include a first connecting segment and a second connecting segment, the first connecting segment may extend along the row direction X, and be located between the first reset scan line GL2 and the ninth gate portion G9, the second connecting segment may extend along the column direction Y, and be located between the first semiconductor portion SE1 and the second semiconductor portion SE2; one end of the first connecting segment is connected to the first semiconductor portion SE1 between the channel portion of the first reset transistor T2 and the write transistor T1 through a contact hole, and the other end is connected to one end of the second connecting segment, and the other end of the second connecting segment is connected to the ninth gate portion G9 through a contact hole.

[0157] As shown in Figures 12, 15, and 16, the second connection portion S2 can be connected to the second electrode plate Cst2 and the first electrode of the drive transistor T5 through a contact hole. For example, the second connection portion S2 can extend along the row direction X and be located between the write scan line GL1 and the first connection portion S1, with its orthographic projection on the substrate SU located between the ninth gate portion G9 and the orthographic projection of the write scan line GL1 on the substrate SU. Furthermore, the orthographic projection of the second connection portion S2 on the substrate SU can be located within the orthographic projection of the second electrode plate Cst2 on the substrate SU. The second connection portion S2 connects the second electrode plate Cst2 to the second semiconductor portion SE2 between the channel portions of the drive transistor T5 and the second reset transistor T3 through the contact holes.

[0158] The third connection portion S3 can be connected to the first electrode of the write transistor T1 and the data line DAL through contact holes, respectively, to enable the transmission of the data signal Data. For example, the third connection portion S3 is located between the second reset scan line GL3 and the second reset signal line VIL, and between the first semiconductor portion SE1 and the second semiconductor portion SE2. The third connection portion S3 is connected to one end of the first semiconductor portion SE1 through a contact hole. This end is located on the side of the channel portion of the write transistor T1 away from the channel portion of the first reset transistor T2. The third connection portion S3 is also connected to the data line DAL through a contact hole.

[0159] Furthermore, as shown in Figures 10, 11, and 26, the second source-drain layer SD2 may further include a transition portion S4, which may be connected to the first electrode of the driving transistor T5 and the second electrode of the second reset transistor T3. For example, the transition portion S4 may be connected to the second connecting portion S2 via a contact hole. Simultaneously, the transition portion S4 may also be connected to the first electrode ANO of the light-emitting device LD via a contact hole.

[0160] In addition, as shown in FIG2 , the driving backplane BP may further include a buffer layer BUF of an insulating material, a first gate insulating layer GI1 , a second gate insulating layer GI2 , an interlayer dielectric layer ILD , a first planar layer PLN1 , and a second planar layer PLN2 , wherein:

[0161] The buffer layer BUF can be provided on one side of the substrate SU and cover the light shielding layer BSM. The first gate layer GA1 is provided on the surface of the buffer layer BUF away from the substrate SU; the first gate insulating layer GI1 covers the first gate layer GA1; the semiconductor layer SE is provided on the surface of the first gate insulating layer GI1 away from the substrate SU; the second gate insulating layer GI2 covers the semiconductor layer SE; the second gate layer GA2 is provided on the surface of the second gate insulating layer GI2 away from the substrate SU; the interlayer dielectric layer ILD covers the second gate layer GA2, and the interlayer dielectric layer can be a single-layer structure or a multi-layer structure. For example, the interlayer dielectric layer can include multiple sub-dielectric layers stacked in sequence; the first source and drain layer S D1 is arranged on the surface of the interlayer dielectric layer ILD away from the substrate SU; the first source and drain layer SD1 can be covered with a passivation layer, and then the passivation layer is covered with the first flat layer PLN1. Of course, the passivation layer can also be omitted, and the first source and drain layer SD1 can be directly covered with the first flat layer PLN1; the second source and drain layer SD2 is arranged on the surface of the first flat layer PLN1 away from the substrate SU; the second flat layer PLN2 covers the second source and drain layer SD2; the first electrode ANO of the light-emitting device LD is arranged on the surface of the second flat layer PLN2 away from the substrate SU, and can be separated by the pixel definition layer PDL.

[0162] Since there are metal oxide transistors in the pixel circuit PC, and metal oxide semiconductors are easily affected by light, resulting in problems such as threshold voltage shift and low light stability, the source and drain layers can be used to at least shield the metal oxide transistors to reduce the light irradiating the metal oxide transistors. Specifically, at least one source and drain layer can be overlapped with the channel portion of at least part of the metal oxide transistors to achieve a light shielding effect and improve the light stability of these transistors.

[0163] For multiple source and drain layers, the pattern of the source and drain layer closest to the semiconductor layer SE can be used for shielding to minimize light exposure to the transistor. However, considering the limitations of the pattern of the same source and drain layer itself, the space available for shielding is limited. Therefore, multiple source and drain layers can be used to shield different metal oxide transistors, reducing the limitations of the pattern of each source and drain layer and avoiding problems such as short circuits. The following example uses the first source and drain layer SD1 and the second source and drain layer SD2 to shield different metal oxide transistors respectively:

[0164] In some embodiments of the present disclosure, as shown in FIG12 , FIG16 and FIG25 , the first source-drain layer SD1 may be used to shield the channel portions of the write transistor T1 and the second reset transistor T3 . For example:

[0165] The write scan line GL1 overlaps with the channel portion of the write transistor T1, and the second gate portion G2 and the sixth gate portion G6 are staggered in the row direction X. The write scan line GL1 overlaps with the second gate portion G2 and the sixth gate portion G6, and is connected to the second gate portion G2 and the sixth gate portion G6 through contact holes respectively. It can simultaneously transmit the write scan signal Gate1 to the second gate portion G2 and the sixth gate portion G6, and also realizes the connection between the second gate portion G2 and the sixth gate portion G6.

[0166] Furthermore, the boundaries of the second gate portion G2 and the sixth gate portion G6, as projected onto the substrate SU in the column direction Y, can be positioned within the boundaries of the write scan line GL1, as projected onto the substrate SU in the column direction Y, ensuring that the channel of the write transistor T1 is completely shielded. For example, the write scan line GL1 has a write shielding portion GL11 that protrudes toward both sides along the column direction Y. The write shielding portion GL11 can partially increase the width of the write scan line GL1, so that the boundaries of the second gate portion G2 and the sixth gate portion G6, as projected onto the substrate SU in the column direction Y, are positioned within the boundaries of the write shielding portion GL11, thereby eliminating the need to increase the overall width of the write scan line GL1.

[0167] The second reset scan line GL3 overlaps with the channel portion of the second reset transistor T3, and the fourth gate portion G4 and the eighth gate portion G8 are staggered in the row direction X. The second reset scan overlaps with the fourth gate portion G4 and the eighth gate portion G8, and is connected to the fourth gate portion G4 and the eighth gate portion G8 through contact holes, respectively. The second reset scan signal Gate3 can be transmitted to the fourth gate portion G4 and the eighth gate portion G8 at the same time, and the connection between the fourth gate portion G4 and the eighth gate portion G8 is also realized.

[0168] Furthermore, the boundaries of the fourth gate portion G4 and the eighth gate portion G8, as projected onto the substrate SU in the column direction Y, are located within the boundaries of the second reset scan line GL3, as projected onto the substrate SU in the column direction Y, ensuring that the channel of the second reset transistor T3 is completely shielded. For example, the second reset scan line GL3 has a first reset shielding portion GL31 that protrudes toward both sides along the column direction Y. The first reset shielding portion GL31 can partially increase the width of the second reset scan line GL3, so that the boundaries of the second gate portion G2 and the sixth gate portion G6, as projected onto the substrate SU in the column direction Y, are located within the boundaries of the write shielding portion GL11, as projected onto the substrate SU in the column direction Y, thereby eliminating the need to increase the width of the write scan line GL1 as a whole.

[0169] In the above embodiment, the write transistor T1 and the second reset transistor T3 are blocked by the write scan line GL1 and the second reset scan line GL3. Since the top gate and the bottom gate of the write transistor T1 and the second reset transistor T3 are connected and have the same potential, the write scan line GL1 and the second reset scan line GL3 that transmit signals to the gates of the two will not increase the capacitance of the blocked area.

[0170] In some embodiments of the present disclosure, as shown in FIG11 , FIG16 and FIG26 , the second source-drain layer SD2 may be used to shield the channel portions of the first reset transistor T2 and the light emission control transistor T4. For example:

[0171] As shown in Figures 12, 13 and 16, the first reset scan line GL2 overlaps with the first gate portion G1 and the fifth gate portion G5; the first gate portion G1 and the fifth gate portion G5 are staggered in the row direction X, and the first reset scan line GL2 overlaps with the first gate portion G1 and the fifth gate portion G5, and is respectively connected to the first gate portion G1 and the fifth gate portion G5 through contact holes, and can simultaneously transmit the first reset scan signal Gate2 to the first gate portion G1 and the fifth gate portion G5, and also realizes the connection between the first gate portion G1 and the fifth gate portion G5.

[0172] Furthermore, the boundary of the first gate portion G1 and the fifth gate portion G5, as projected onto the substrate SU in the column direction Y, lies within the boundary of one of the second power line VSL, the first auxiliary reset line VRLs, and the second auxiliary reset line VILs, as projected onto the substrate SU in the column direction Y, thereby ensuring that the channel of the first reset transistor T2 is completely shielded. For example, one of the second power line VSL, the first auxiliary reset line VRLs, and the second auxiliary reset line VILs has a second reset shielding portion V1 that protrudes toward both sides along the row direction X. This second reset shielding portion V1 can locally increase the width of one of the second power line VSL, the first auxiliary reset line VRLs, and the second auxiliary reset line VILs, so that the boundary of the first gate portion G1 and the fifth gate portion G5, as projected onto the substrate SU in the column direction Y, lies within the boundary of the second reset shielding portion V1, thereby eliminating the need to increase the overall width of one of the second power line VSL, the first auxiliary reset line VRLs, and the second auxiliary reset line VILs.

[0173] The emission control line EML overlaps with the channel portion of the emission control transistor T4. The third gate portion G3 and the seventh gate portion G7 are staggered in the row direction X. The emission control line EML overlaps with the third gate portion G3 and the seventh gate portion G7 and is connected to the third gate portion G3 and the seventh gate portion G7 through contact holes, respectively. This allows the emission control signal EM to be transmitted to both the third gate portion G3 and the seventh gate portion G7, thereby connecting the third gate portion G3 and the seventh gate portion G7.

[0174] Furthermore, the boundaries of the third gate portion G3 and the seventh gate portion G7, as projected onto the substrate SU in the column direction Y, lie within the boundaries of the first power line VDL, as projected onto the substrate SU in the column direction Y. This ensures that the channel of the light-emitting control transistor T4 is completely shielded. For example, the first power line VDL includes a power shielding portion VDL1 that protrudes toward both sides along the row direction X. The boundaries of the third gate portion G3 and the seventh gate portion G7, as projected onto the substrate SU in the column direction Y, lie within the boundaries of the power shielding portion VDL1, as projected onto the substrate SU in the column direction Y. The power shielding portion VDL1 can be used to partially increase the width of the first power line VDL to shield the third gate portion G3 and the seventh gate portion G7, without increasing the width of the first power line VDL as a whole.

[0175] In some embodiments of the present disclosure, the first power line VDL and the second semiconductor portion SE2 both extend along the column direction Y, and the first power line VDL can be used to shield the second semiconductor portion SE2, so that the first power line VDL simultaneously overlaps with the channel portions of the second reset transistor T3, the driving transistor T5 and the light emitting control transistor T4.

[0176] Furthermore, as shown in Figures 11 and 28 , the boundary of at least a portion of the second semiconductor portion SE2, as projected onto the substrate SU in the row direction X, can be positioned within the boundary of the first power line VDL, as projected onto the substrate SU in the row direction X. This increases the shielding range and reduces the amount of light reaching the second semiconductor portion SE2. For example, the boundary of at least a portion of the second semiconductor portion SE2, as projected onto the substrate SU in the row direction X, is defined as the first boundary, and the boundary of the first power line VDL, as projected onto the substrate SU in the row direction X, is defined as the second boundary. The first boundary is positioned inside the second boundary, and the distance L between the first and second boundaries is less than 2 μm. Furthermore, the distance L between the first and second boundaries can be less than 1 μm. This ensures shielding while preventing the first power line VDL from being too wide and interfering with other traces. Of course, the first and second boundaries can also overlap, as long as the first boundary does not lie outside the first boundary.

[0177] The first boundary mentioned above may include at least the boundary of the orthographic projections of a portion of the second semiconductor portion SE2 between the channel portion of the emission control transistor T4 and the channel portion of the drive transistor T5, and between the channel portion of the drive transistor T5 and the channel portion of the second reset transistor T3, on the substrate SU. To ensure the width-to-length ratio of the channel of the drive transistor T5, the boundary of the orthographic projection of the channel portion of the drive transistor T5 on the substrate SU in the row direction X may be located outside the boundary of the orthographic projection of the first power line VDL on the substrate SU in the row direction X.

[0178] The channel portion of the driving transistor T5 can be shielded by the first source-drain layer SD1. However, the first source-drain layer SD1 is close to the driving transistor T5, which easily generates a large parasitic capacitance. Therefore, the second source-drain layer SD2 can be used for setting. For example, the positive projection of the channel portion of the driving transistor T5 on the substrate SU is located within the positive projection of the first power line VDL on the substrate SU. This can be achieved by increasing the overall or local line width of the first power line VDL. However, in order to avoid a short circuit between the first power line VDL and the data line DAL, the first electrode ANO can also be used to shield the channel portion of the driving transistor T5, thereby reducing light exposure. Of course, the first electrode ANO is not limited to shielding only the driving transistor T5, but can also shield other metal oxide transistors. The following is an example of shielding the driving transistor T5:

[0179] In some embodiments of the present disclosure, as shown in Figures 10 and 16, a first electrode ANO can overlap at least one channel portion of a driving transistor T5. Furthermore, the orthographic projection of the channel portion on the substrate SU can be within the orthographic projection of the first electrode ANO on the substrate SU, thereby providing light shielding through the first electrode ANO. The first electrode ANO can have a single-layer or multi-layer structure and can be made of a metal such as aluminum or titanium, or an alloy, as long as it can shield light and is conductive.

[0180] Furthermore, in some embodiments of the present disclosure, as shown in Figures 10 and 27, the first electrode ANO may include an electrode body A1 and a connecting extension A2 connected to the edge of the electrode body A1, and the connecting extension A2 is connected to the first electrode of a driving transistor T5 through a contact hole. The boundary of the orthographic projection of the pixel opening PH on the substrate SU may be located within the boundary of the electrode body A1 of the first electrode ANO exposed by the pixel opening PH. The electrode body A1 within the pixel opening PH is stacked with the light-emitting layer to form a light-emitting device, while the pixel definition layer PDL is stacked on the first electrode ANO in the area outside the pixel opening PH. By connecting the connecting extension A2 to the contact hole, the electrode body A1 can be kept flat, in particular, the electrode body A1 within the pixel opening PH can be kept flat without connecting to the contact hole, thereby preventing the contact hole from affecting the light emission of the light-emitting device.

[0181] In some embodiments of the present disclosure, as shown in Figures 10 and 27, the channel portion of the driving transistor T5 can be blocked by increasing the area of ​​the first electrode ANO, but the number of first electrodes ANO is large and the space is limited. Therefore, the channel portion of the driving transistor T5 can be blocked by partially extending the first electrode ANO outward to increase the area. Specifically, at least a portion of the first electrode ANO may also include a blocking extension portion A3 connected to the edge of the electrode body A1, and the blocking extension portion A3 may overlap with the channel portion of the driving transistor T5. For example, the orthographic projection of at least a portion of the channel portion of the driving transistor T5 on the substrate SU can be located within the orthographic projection of the blocking extension portion A3 on the substrate SU, thereby improving the shading effect.

[0182] Furthermore, at least a portion of the first electrode ANO can overlap with the channel portions of multiple driving transistors T5 simultaneously. That is, a single first electrode ANO can simultaneously block the channel portions of multiple driving transistors T5. For a single first electrode ANO and the channel portions of the multiple driving transistors T5 it blocks, the blocking extension A3 can block portions of the channel portions, the electrode body A1 can block portions of the channel portions, and the connecting extension A2 can block portions of the channel portions. In other words, any region of the first electrode ANO can block the channel portions.

[0183] In some embodiments of the present disclosure, the light-emitting device may include a first light-emitting device, a second light-emitting device, and a third light-emitting device emitting different colors. The area of ​​the first electrode ANO of the first light-emitting device is larger than the areas of the first electrodes ANO of the second and third light-emitting devices. For example, the first light-emitting device may emit blue light, the second light-emitting device may emit red light, and the third light-emitting device may emit green light. The first electrode ANO of the first light-emitting device can overlap with the channel portion of the driver transistor T5 to achieve shielding. At the same time, the second and third light-emitting devices can be distributed along the row direction X, and the second and third light-emitting devices can be distributed as a whole with the first light-emitting device along the column direction Y. The first electrode ANO of a single first light-emitting device LD1 can simultaneously shield the channel portions of the driver transistor T5 of two, three, or more pixel circuits PC distributed along the row direction X.

[0184] In other embodiments of the present disclosure, as shown in Figures 16 and 30, the first electrodes ANO of the first, second, and third light-emitting devices can each be provided with a shielding extension A3. The shielding extension A3 of the first electrode ANO of the first light-emitting device can shield the channel of the drive transistor T5; the shielding extension A3 of the second light-emitting device can shield the channel of the write transistor T1, and the shielding extension A3 of the third light-emitting device can shield the channel of the second reset transistor T3. Of course, the positions of the second and third light-emitting devices can be interchanged. By making full use of the first electrode ANO shielding the transistor channel, the impact of light on the transistor can be minimized.

[0185] It should be noted that while the above embodiment describes the first electrode ANO blocking the channel of the driving transistor T5, this does not mean that the first electrode ANO only overlaps the channel of the driving transistor T5. The first electrode ANO may also overlap the channels of other transistors. Furthermore, the first electrode ANO that overlaps the channels of transistors is not limited to the first light-emitting device, but may also overlap the second and third light-emitting devices.

[0186] In some embodiments of the present disclosure, the second source-drain layer SD2 can also be used to shield the channels of the write transistor T1 and the second reset transistor T3. For example, as shown in FIG29 , the second power line VSL, the first auxiliary reset line VRLs, and the second auxiliary reset line VILs can be provided with a first routing shielding portion B1 that protrudes along the row direction X. The first routing shielding portion B1 at least partially overlaps the channel of the write transistor T1, thereby shielding the channel of the write transistor T1 and reducing the effects of light. Simultaneously, the first power line VDL can be provided with a second routing shielding portion B2 that protrudes along the row direction X. The second routing shielding portion B2 at least partially overlaps the channel of the second reset transistor T3, thereby shielding the channel of the second reset transistor T3 and reducing the effects of light. Of course, the second power line VSL, the first auxiliary reset line VRLs, the second auxiliary reset line VILs, and the first power line VDL can also be widened as a whole, as long as this does not cause a short circuit between the routings.

[0187] It should be noted that, as shown in Figures 10, 12, 29 and 30, the shielding of the second reset transistor T3 and the write transistor T1 can be achieved through the first reset shielding portion GL31 and the write shielding portion GL11 mentioned above, or through the above-mentioned shielding extension portion A3 and the first routing shielding portion B1 and the second routing shielding portion B2, that is, shielding using the first source and drain layer SD1, the second source and drain layer SD2 and the first electrode ANO. The above-mentioned methods can be adopted simultaneously, that is, the first source and drain layer SD1, the second source and drain layer SD2 and the first electrode ANO are used for shielding at the same time; or a single layer can be used for shielding, or any two layers can be used in combination, as long as the second reset transistor T3 and the write transistor T1 can be shielded, for example, only one of the first source and drain layer SD1, the second source and drain layer SD2 and the first electrode ANO is used for shielding; or, by shielding through the first source and drain layer SD1 and the second source and drain layer SD2, the first electrode ANO may not have the shielding extension A3; or, by shielding through the first source and drain layer SD1 and the first electrode ANO, the second source and drain layer SD2 may not have the first routing shielding portion B1 and the second routing shielding portion B2; in addition, the second reset transistor T3 and the write transistor T1 can also be shielded by different film layers, for example, the second reset transistor T3 is shielded by the shielding extension A3 and the first reset shielding portion GL31, while the write transistor T1 can be shielded by the write shielding portion GL11 and the first routing shielding portion B1. The shielding methods for the second reset transistor T3 and the write transistor T1 are not listed one by one here.

[0188] In addition, compared with the first source and drain layer SD1, the distance between the second source and drain layer SD2 and the first electrode ANO and the second gate layer GA2 is farther, so that the parasitic capacitance between the first wiring shielding portion B1 and the second wiring shielding portion B2 and the shielding extension portion A3 and the second gate layer GA2 is smaller. However, in order to improve the shading effect, the boundaries of the positive projections of the first wiring shielding portion B1, the second wiring shielding portion B2 and the shielding extension portion A3 on the substrate SU can be at least partially located outside the boundaries of the positive projections of the channels of the transistors they shield on the substrate SU, and the distance between the boundaries is not less than 2μm, for example, 2μm to 5μm, so as to ensure the shading effect while avoiding interference with other structures.

[0189] The present disclosure also provides a display device, which may include a display panel according to any of the above-mentioned embodiments. The display panel is a display panel according to any of the above-mentioned embodiments. Its specific structure and beneficial effects can be referred to in the embodiments of the display panel above, and will not be repeated here. The display device of the present disclosure can be an electronic device such as a mobile phone, tablet computer, or television, or a wearable device with image display function such as a smart watch, virtual reality device, or augmented reality device, or other electronic device with display function such as an in-vehicle display device, which will not be listed one by one here.

[0190] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel, comprising: A driving backplane, comprising a plurality of pixel circuits arranged in an array along row and column directions, wherein the pixel circuits comprise a plurality of transistors, and the transistors in any of the pixel circuits comprise a driving transistor; the driving transistor and at least some of the other transistors in any of the pixel circuits are metal oxide transistors; the driving backplane comprises a substrate, a semiconductor layer and at least one source-drain layer arranged in a direction away from the substrate; the channel portions of at least some of the transistors are located in the semiconductor layer; the source-drain layer overlaps with the channel portions of at least some of the metal oxide transistors; The light emitting device is arranged on one side of the driving backplane and comprises a first electrode, a light emitting layer and a second electrode distributed in a direction away from the driving backplane; the first electrode of the driving transistor is connected to the first electrode of the light emitting device.

2. The display panel according to claim 1, wherein: The pixel circuit further includes a storage capacitor, and the transistor of the pixel circuit further includes a first reset circuit, a second reset circuit, a write circuit and a light emitting control circuit; The first reset circuit is connected to the gate of the driving transistor and is used to transmit a first reset signal in response to a first reset scan signal; the second reset circuit is connected to the first electrode of the driving transistor and is used to transmit a second reset signal in response to a second reset scan signal; the write circuit is connected to the gate of the driving transistor and is used to transmit a data signal in response to a write scan signal; the light-emitting control circuit is used to receive a first power supply signal and is connected to the second electrode of the driving transistor, and is used to be turned on in response to a light-emitting control signal; the storage capacitor is connected to the gate and the first electrode of the driving transistor.

3. The display panel according to claim 2, wherein: The driving backplane further includes a first power line and a data line extending in the column direction, and a first reset scan line, a second reset scan line, a write scan line, a light emitting control line, a first reset signal line, and a second reset signal line extending in the row direction; The first reset circuit includes a first reset transistor, the second reset circuit includes a second reset transistor, the write circuit includes a write transistor, and the light emitting control circuit includes a light emitting control transistor; each of the transistors in the pixel circuit is a metal oxide transistor; The first reset scan line is connected to the gate of the first reset transistor and is used to transmit the first reset scan signal; The first reset signal line passes through the first reset transistor connected to the gate of the driving transistor, and used for transmitting the first reset signal; The second reset scan line is connected to the gate of the second reset transistor and is used for transmitting the second reset scan signal; The second reset signal line is connected to the first electrode of the driving transistor through the second reset transistor, and is used for transmitting the second reset signal; The first power line is connected to the second electrode of the driving transistor through the light emitting control transistor, and is used to transmit the first power signal; The write scan line is connected to the gate of the write transistor for transmitting the write scan signal; the data line is connected to the gate of the drive transistor through the write transistor for transmitting the data signal; The light emitting control line is connected to the gate of the light emitting control transistor and is used for transmitting the light emitting control signal.

4. The display panel according to claim 3, wherein: The driving backplane further comprises a second power line extending in the column direction and a first auxiliary power line and a second auxiliary power line extending in the row direction; The first auxiliary power line and the first power line are located in different layers and are connected through a contact hole; The second power line and the second auxiliary power line are located in different layers and are connected through a contact hole; the second power line is connected to the second electrode for transmitting a second power signal.

5. The display panel according to claim 4, wherein: The driving backplane further includes a first auxiliary reset line extending along the column direction. The first auxiliary reset line and the first reset signal line are located in different layers and are connected through a contact hole.

6. The display panel according to claim 5, wherein: The driving backplane further includes a second auxiliary reset line extending along the column direction, wherein the second auxiliary reset line and the second reset signal line are located in different layers and are connected through a contact hole.

7. The display panel according to claim 6, wherein: One of the data lines is connected to a write transistor of a column of the pixel circuit; one of the first power lines is connected to a light emitting control transistor of a column of the pixel circuit; The data lines and the first power lines connected to the same column of pixel circuits are defined as a column line group, and between two adjacent column line groups there is provided the second power line, one of the first auxiliary reset line and the second auxiliary reset line.

8. The display panel according to claim 5, wherein: A row of the pixel circuits is simultaneously connected to a first reset scan line, a second reset scan line, a write scan line, a light emitting control line, a first reset signal line, and a second reset signal line; The first reset scan line, the second reset scan line, the write scan line, the light emission control line, the first reset signal line and the second reset signal line connected to the pixel circuits in the same row are defined as a row line group; A first auxiliary power line and a second auxiliary power line are disposed between two adjacent row line groups.

9. The display panel according to claim 6, wherein: The source-drain layer comprises a first source-drain layer and a second source-drain layer distributed in a direction away from the substrate; Channel portions of the write transistor and the second reset transistor overlap with the first source-drain layer; channel portions of the first reset transistor and the light emission control transistor overlap with the second source-drain layer.

10. The display panel according to claim 9, wherein: The semiconductor layer includes a first semiconductor portion and a second semiconductor portion spaced apart along the row direction, and the first semiconductor portion and the second semiconductor portion extend along the row direction; The channel portions of the first reset transistor and the write transistor are located in the first semiconductor portion along the column direction; The channel portions of the light emission control transistor, the drive transistor and the second reset transistor are located in the second semiconductor portion along the column direction; A channel portion of the write transistor overlaps with one of the write scan lines; a channel portion of the second reset transistor overlaps with one of the second reset scan lines; The first power line overlaps with channel portions of the second reset transistor, the drive transistor, and the light emission control transistor.

11. The display panel according to claim 10, wherein: At least a portion of the second semiconductor portion has a boundary of an orthographic projection of the substrate in the row direction located within a boundary of an orthographic projection of the first power line in the row direction.

12. The display panel according to claim 11, wherein: The boundary of at least a portion of the second semiconductor portion in the row direction of the orthographic projection of the substrate is taken as a first boundary, and the boundary of the first power line in the row direction of the orthographic projection of the substrate is taken as a second boundary; The first boundary is located inside the second boundary, and a distance between the first boundary and the second boundary is less than 2 μm.

13. The display panel according to claim 9, wherein: The first reset scan line, the second reset scan line, the write scan line, the light emitting control line, the first reset signal line, the second reset signal line, the first auxiliary power line and the second auxiliary power line are located in the first source-drain layer; The first power line, the second power line, the data line, the first auxiliary reset line and the second auxiliary reset line are located in the second source-drain layer.

14. The display panel according to claim 13, wherein: The driving backplane also includes: A light shielding layer is provided on one side of the substrate and includes a light shielding portion; the semiconductor layer is provided on a side of the light shielding layer away from the substrate, the light shielding portion overlaps with the channel portion of the driving transistor, and the light shielding portion is reused as a first plate of the storage capacitor; A first gate layer is provided on a side of the light shielding layer away from the substrate and includes a second electrode plate of the storage capacitor; the semiconductor layer is provided on a side of the first gate layer away from the substrate, and the first electrode plate overlaps with a channel portion of the driving transistor; The second gate layer is arranged on a side of the semiconductor layer away from the substrate and overlaps with the channel portion of the driving transistor; the first source and drain layer is arranged on a side of the second gate layer away from the substrate.

15. The display panel according to claim 14, wherein: The first gate layer further includes a first gate portion, a second gate portion, a third gate portion and a fourth gate portion; the second gate layer includes a fifth gate portion, a sixth gate portion, a seventh gate portion, an eighth gate portion and a ninth gate portion; The first gate portion and the fifth gate portion overlap with the channel portion of the first reset transistor, and the first gate portion and the fifth gate portion are connected; The second gate portion and the sixth gate portion overlap with the channel portion of the write transistor, and the second gate portion and the sixth gate portion are connected; The third gate portion and the seventh gate portion overlap with the channel portion of the light emission control transistor, and the third gate portion and the seventh gate portion are connected; The fourth gate portion and the eighth gate portion overlap with the channel portion of the second reset transistor, and the fourth gate portion and the eighth gate portion are connected; The ninth gate portion overlaps with a channel portion of the driving transistor.

16. The display panel according to claim 15, wherein: The boundary of the first gate portion and the fifth gate portion in the column direction of the orthogonal projection of the substrate is located within the boundary of the orthogonal projection of one of the second power line, the first auxiliary reset line and the second auxiliary reset line in the column direction of the substrate; and the first gate portion and the fifth gate portion are connected to the first reset scan line; The boundary between the orthographic projection of the third gate portion and the seventh gate portion in the column direction of the substrate is located within the boundary of the orthographic projection of the first power line in the column direction of the substrate; and the third gate portion and the seventh gate portion are connected to the light emitting control line; The boundary of the orthogonal projection of the second gate portion and the sixth gate portion in the column direction of the substrate is located within the boundary of the orthogonal projection of the write scan line in the column direction of the substrate; and the second gate portion and the sixth gate portion are connected to the first reset scan line; The boundary of the fourth gate portion and the eighth gate portion in the column direction of the orthographic projection of the substrate is located within the boundary of the orthographic projection of the substrate in the column direction; and the fourth gate portion and the eighth gate portion are connected to the second reset scan line.

17. The display panel according to any one of claims 2 to 16, wherein: A first electrode at least overlaps with a channel portion of the driving transistor.

18. The display panel according to claim 17, wherein: The first electrode comprises an electrode body and an extension portion connected to an edge of the electrode body, wherein the extension portion is connected to a first electrode of the driving transistor; At least a portion of the first electrode further includes an extension portion connected to an edge of the electrode body, and the extension portion overlaps with a channel portion of the driving transistor; The display panel further includes: The pixel definition layer is arranged on the same side of the driving backplane as the light-emitting device and has a pixel opening exposing each of the first electrodes; the boundary of the positive projection of the pixel opening on the substrate is located within the boundary of the electrode body of the exposed first electrode.

19. The display panel according to claim 17, wherein: At least a portion of the first electrode overlaps with channel portions of a plurality of the driving transistors at the same time.

20. A display device comprising the display panel according to any one of claims 1 to 19.

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