Display screen, display driver, and electronic device and driving method therefor

Abstract

The embodiments of the present application relate to the technical field of electronics. Provided are a display screen, a display driver, and an electronic device and a driving method therefor, which are used for ameliorating the problem of the display brightness of a display screen being non-uniform. The display screen comprises N rows of pixels and reset voltage ends, wherein N is a positive integer, each row of pixels comprise a plurality of pixel circuits arranged at intervals, each reset voltage end is electrically connected to the N rows of pixels, each reset voltage end is configured to provide a first reset voltage within a first period in an image frame, and provide a second reset voltage within a second period in the image frame, and the value of the first reset voltage is different from the value of the second reset voltage. That is to say, the reset voltages output by the reset voltage ends to the N rows of pixels are not fixed values, and the N rows of pixels may receive the reset voltages of various values, thereby reversely compensating for the influence caused by an unfixed load, an unfixed frame rate and a voltage fluctuation, and thus ameliorating the problem of the display brightness being non-uniform.

Description

Display screen, display driver, electronic device and driving method thereof

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on September 27, 2023, with application number 202311261835.8 and application name “Display screen, display driver, electronic device and driving method thereof”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of electronic technology, and in particular to a display screen, a display driver, an electronic device and a driving method thereof. Background Art

[0003] In recent years, as the electronic device market has gradually increased its demand for a higher screen-to-body ratio, various display technologies have emerged, such as display area punch-holes, hyperbolic waterfall screens, quad-curved technology, and under-screen cameras. Among them, display area punch-hole technology is currently a mainstream trend.

[0004] However, because punching holes in the display area requires removing some pixels, the signal lines in the punched and non-punched areas have different loads, affecting the pixel charging time and resulting in uneven display brightness. Other issues, such as varying frame rates in different areas of the display and fluctuations in reset voltage, can also lead to uneven display brightness, affecting the user experience.

[0005] Summary of the Invention

[0006] Embodiments of the present application provide a display screen, a display driver, an electronic device, and a driving method thereof, for improving the problem of uneven display brightness of the display screen.

[0007] To achieve the above objectives, this application adopts the following technical solutions:

[0008] According to a first aspect of an embodiment of the present application, a display screen is provided, comprising: N rows of pixels and a plurality of reset voltage terminals. N is a positive integer, and each row of pixels includes a plurality of pixel circuits arranged in an alternating pattern. Each reset voltage terminal is electrically connected to the N rows of pixels; at least one of the plurality of reset voltage terminals is configured to provide a first reset voltage to the pixel circuit during a first period within an image frame and to provide a second reset voltage to the pixel circuit during a second period within the image frame; the value of the first reset voltage is different from the value of the second reset voltage.

[0009] In the display screen provided by the embodiment of the present application, the reset voltage terminal provides a first reset voltage in the first time period within an image frame and provides a second reset voltage in the second time period within the image frame, and the value of the first reset voltage is different from the value of the second reset voltage. Then, the first part of the rows of pixels in the display screen receives the first reset voltage, and the second part of the rows of pixels receives the second reset voltage. Although the reset voltage is fixed, factors such as non-fixed load, non-fixed frame rate, and voltage fluctuations will cause the problem of uneven display brightness. In the embodiment of the present application, by providing a variable reset voltage to N rows of pixel circuits within an image frame, the effects of non-fixed load, non-fixed frame rate, and voltage fluctuations can be reversely compensated, thereby improving the problem of uneven display brightness. Moreover, the value of the reset voltage can be dynamically adjusted according to the position of the pixel rows in the display screen. The pixel rows receiving the first reset voltage and the pixel rows receiving the second reset voltage can be dynamically adjusted and can be arranged according to any rules. The adjustment method is dynamic and flexible, applicable to many scenarios, and has a wide range of applications.

[0010] In one possible implementation, the multiple reset voltage terminals include a first reset voltage terminal; the pixel circuit includes a driving transistor and a first reset circuit; and two terminals of the first reset circuit are electrically connected to a control electrode of the driving transistor and the first reset voltage terminal, respectively. By adjusting the reset voltage of the first reset voltage terminal, the driving current of the pixel circuit can be adjusted, thereby adjusting the brightness of the pixel circuit.

[0011] In one possible implementation, the multiple reset voltage terminals include a second reset voltage terminal; the pixel circuit includes a driving transistor and a second reset circuit; and two terminals of the second reset circuit are electrically connected to a first electrode of the driving transistor and the second reset voltage terminal, respectively. By adjusting the reset voltage of the second reset voltage terminal, the driving current of the pixel circuit can be adjusted, thereby adjusting the brightness of the pixel circuit.

[0012] In one possible implementation, the multiple reset voltage terminals include a third reset voltage terminal; the pixel circuit includes a light-emitting device and a third reset circuit; and two terminals of the third reset circuit are electrically connected to an anode of the light-emitting device and the third reset voltage terminal, respectively. By adjusting the reset voltage of the third reset voltage terminal, the duration of light emission of the pixel circuit can be adjusted, thereby adjusting the brightness of the light emitted by the pixel circuit.

[0013] In one possible implementation, a first portion of N rows of pixels are configured to receive a first reset voltage during a first time period, and a second portion of N rows of pixels are configured to receive a second reset voltage during a second time period. The rows of pixels receiving the first reset voltage and the rows of pixels receiving the second reset voltage can be dynamically adjusted and arranged in any pattern. This dynamic and flexible adjustment method is applicable to a wide range of scenarios and applications.

[0014] In a possible implementation, the reset voltage terminal is configured to provide a first reset voltage to the pixels in rows 1 to M, a second reset voltage to the pixels in rows M + 1 to I, and a first reset voltage to the pixels in rows I + 1 to N; M < I < N. This is an adjustment scenario where the emission brightness of the pixels in rows M + 1 to I is different from that of the pixels in other rows.

[0015] In a possible implementation, the reset voltage terminal is configured to provide a first reset voltage to the pixels in rows 1 to M, a second reset voltage to the pixels in rows M + 1 to I, a first reset voltage to the pixels in rows I + 1 to L, a second or third reset voltage to the pixels in rows L + 1 to T, and a first reset voltage to the pixels in rows T + 1 to N, M < I < L < T < N. This is an adjustment scenario where the emission brightness of the pixels in rows M + 1 to I and the emission brightness of the pixels in rows L + 1 to T are different from that of the pixels in other rows.

[0016] In a possible implementation, the values of the first reset voltage output by the first reset voltage terminal, the first reset voltage output by the second reset voltage terminal, and the first reset voltage output by the third reset voltage terminal are different. The value of the reset voltage terminal is related to the required value of the node to be reset and can be dynamically and flexibly adjusted.

[0017] In the second aspect of the embodiments of the present application, a display driver is provided, including: an image data receiving terminal for receiving image data; a processing circuit for generating a first reset voltage and a second reset voltage according to the image data, where the value of the first reset voltage is different from the value of the second reset voltage; a plurality of reset voltage output terminals; at least one of the reset voltage output terminals is configured to output the first reset voltage in a first period within an image frame and output the second reset voltage in a second period within the image frame. The beneficial effects of the display driver provided in the second aspect of the embodiments of the present application are the same as those of the display screen and will not be elaborated here.

[0018] In a possible implementation, the display driver further includes a temperature receiving terminal for receiving temperature data; the processing circuit is further configured to generate a first reset voltage and a second reset voltage according to the temperature data. Since the temperature of the display screen will affect the device performance of the pixel circuit in the display screen, therefore, taking the temperature of the display screen as a consideration factor for adjusting the reset voltage value can further improve the uniformity of the display brightness.

[0019] In one possible implementation, the processing circuit includes a voltage calculation module for receiving image data and outputting a base voltage and a compensation voltage; a voltage timing control module for receiving the base voltage, the compensation voltage, and a row signal and outputting a first reset voltage or a second reset voltage, as well as a trigger signal; and a voltage output module for receiving the trigger signal, the first reset voltage, and the second reset voltage, and outputting the first reset voltage or the second reset voltage. This is a simple implementation.

[0020] In one possible implementation, the voltage calculation module is further configured to receive a frame rate signal, which is an application scenario for high and low frame rate displays.

[0021] In one possible implementation, the multiple reset voltage output terminals include a first reset voltage output terminal, a second reset voltage output terminal, and a third reset voltage output terminal; the first reset voltage output by the first reset voltage output terminal, the first reset voltage output by the second reset voltage output terminal, and the first reset voltage output by the third reset voltage output terminal have different values.

[0022] According to a third aspect of an embodiment of the present application, an electronic device is provided, comprising a display screen and a display driver, wherein the display screen comprises any display screen of the first aspect, and the display driver comprises any display driver of the second aspect; a reset voltage terminal of the display screen is electrically connected to a reset voltage output terminal of the display driver.

[0023] According to a fourth aspect of an embodiment of the present application, a method for driving an electronic device is provided, comprising: within an image frame, N rows of pixels of a display screen are turned on row by row; a reset voltage output terminal of a display driver outputs a first reset voltage to the display screen in a first time period, and a first portion of pixels in the N rows of pixels receive the first reset voltage for reset; the reset voltage output terminal outputs a second reset voltage to the display screen in a second time period, and a second portion of pixels in the N rows of pixels receive the second reset voltage for reset; and the value of the first reset voltage is different from the value of the second reset voltage.

[0024] In one possible implementation, when the pixels in the first row are turned on, the reset voltage output terminal outputs a first reset voltage to the display screen; when the pixels in the M+1th row are turned on, the reset voltage output terminal outputs a second reset voltage to the display screen; when the pixels in the I+1th row are turned on, the reset voltage output terminal outputs the first reset voltage to the display screen.

[0025] In one possible implementation, when the pixels in the first row are turned on, the reset voltage output terminal outputs a first reset voltage to the display screen; when the pixels in the M+1th row are turned on, the reset voltage output terminal outputs a second reset voltage to the display screen; when the pixels in the I+1th row are turned on, the reset voltage output terminal outputs a second reset voltage or a third reset voltage to the display screen; when the pixels in the L+1th row are turned on, the reset voltage output terminal outputs the first reset voltage to the display screen. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG1 is a schematic diagram of the layout of an electronic device provided in an embodiment of the present application;

[0027] FIG2 is a schematic diagram of a topological structure of a pixel circuit provided in an embodiment of the present application;

[0028] FIG3 is a driving timing diagram of a pixel circuit provided in an embodiment of the present application;

[0029] FIG4A is a pulse diagram of a reset voltage according to an embodiment of the present application;

[0030] FIG4B is a diagram showing a display effect of a display screen according to an embodiment of the present application;

[0031] FIG4C is a schematic diagram of a wiring arrangement of a display screen according to an embodiment of the present application;

[0032] FIG4D is a schematic diagram of a refresh rate distribution of a display screen according to an embodiment of the present application;

[0033] FIG5 is a driving timing diagram of a display screen according to an embodiment of the present application;

[0034] FIG6 is a pulse diagram of a reset voltage at a first reset voltage terminal provided in an embodiment of the present application;

[0035] FIG7 is a pulse diagram of a reset voltage at a first reset voltage terminal provided in an embodiment of the present application;

[0036] FIG8 is a pulse diagram of a reset voltage at a third reset voltage terminal provided in an embodiment of the present application;

[0037] FIG9 is a schematic structural diagram of a display driver provided in an embodiment of the present application;

[0038] FIG10 is a schematic structural diagram of another display driver provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0040] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature qualified as "second," "first," etc., may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0041] In the embodiments of the present application, directional terms such as "up", "down", "left" and "right" may be defined including but not limited to the orientation relative to the components schematically placed in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.

[0042] In the embodiments of this application, unless otherwise specified or limited, the term "connection" should be understood in a broad sense. For example, "connection" can mean fixed connection, detachable connection, or integration; it can mean direct connection or indirect connection through an intermediate medium. In addition, the term "electrically connected" can mean direct electrical connection or indirect electrical connection through an intermediate medium. The term "contact" can mean direct contact or indirect contact through an intermediate medium.

[0043] In the embodiments of the present application, "and / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0044] An embodiment of the present application provides an electronic device. The electronic device is, for example, a consumer electronic product with a display function, a home electronic product, a car-mounted electronic product, or a financial electronic device product. Consumer electronic products include mobile phones, tablet computers, laptop computers, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop displays, smart wearable products (for example, smart watches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, drones, etc. Home electronic products include smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (for example, soymilk machines, sweeping robots), etc. Car-mounted electronic products include car navigation systems, car high-density digital video discs (DVDs), etc. Financial electronic device products include automated teller machines (ATMs), self-service electronic devices, etc. The embodiment of the present application does not impose any special restrictions on the specific form of the above-mentioned electronic devices.

[0045] Taking a mobile phone as an example, as shown in Figure 1, the electronic device 1 includes a display screen 10 and a display driver 20. Figure 1 illustrates the electronic device 1 as a straight-screen mobile phone, which is only an example in the embodiment of the present application.

[0046] In some embodiments, the display screen 10 may be an organic light emitting diode (OLED) display screen, a mini organic light emitting diode (micro OLED) display screen, a quantum dot light emitting diode (QLED) display screen, or other display screen capable of self-luminescence.

[0047] For any of the above-mentioned display screens 10, the display screen 10 includes an effective display area (active area, AA) and a non-display area BB located around the effective display area AA. The effective display area AA is used to display images, and the effective display area AA includes a plurality of sub-pixels (sub pixels, SP). For example, the plurality of sub-pixels SP are arranged in a matrix form into multiple rows and columns. For example, the sub-pixels SP arranged in a row along the horizontal direction X are called a row of sub-pixels SP, and the sub-pixels SP arranged in a row along the vertical direction Y are called a column of sub-pixels SP. A pixel circuit is provided in each sub-pixel SP, and the effective display area AA of the display screen 10 is provided with a plurality of pixel circuits, and the plurality of pixel circuits are arranged into multiple rows and columns. The horizontal direction X in the embodiment of the present application refers to the direction intersecting with the data line in the display screen 10, and the vertical direction Y refers to the direction parallel to the data line in the display screen 10. The data line is a signal line for transmitting data voltage to the pixel circuit in the display screen 10.

[0048] The display driver 20 is used to provide the pixel circuits in the display screen 10 with control signals, reset voltages, and data signals required for light emission. The following describes the signals sent by the display driver 20 in conjunction with the structure of the pixel circuits. The display driver 20 is, for example, a display driver integrated circuit (DDIC).

[0049] FIG2 is a schematic diagram of a topological structure of a pixel circuit provided in an embodiment of the present application.

[0050] Active matrix organic light emitting diode (AMOLED) displays based on self-luminous display technology have a curved, foldable and flexible form. They also have advantages such as high contrast, wide color gamut, wide viewing angle and wide operating temperature. They are widely used in displays of televisions, notebooks, mobile phones, etc.

[0051] Taking AMOLED as an example, in some embodiments, as shown in FIG2 , the pixel circuit 11 generally includes a driving circuit composed of multiple transistors and a light-emitting device. The driving circuit generates a driving current to drive the light-emitting device to emit light, thereby realizing the light-emitting of the pixel circuit 11 .

[0052] For example, the pixel circuit 11 includes a first reset circuit 111, a second reset circuit 112, a third reset circuit 113, a write and threshold compensation circuit 114, a light emitting control circuit 115, and a light emitting device 116. The pixel circuit 11 shown in FIG2 is only for illustration and is not intended to be limiting.

[0053] The first reset circuit 111 is electrically connected to the first reset voltage terminal Vref1, the first control signal terminal P1 and the first node N1, and is used to transmit the reset voltage of the first reset voltage terminal Vref1 to the first node N1 under the control of the first control signal of the first control signal terminal P1, thereby resetting (or initializing) the first node N1.

[0054] The second reset circuit 112 is electrically connected to the second reset voltage terminal Vref2, the second control signal terminal P2 and the second node N2, and is used to transmit the reset voltage of the second reset voltage terminal Vref2 to the second node N2 under the control of the second control signal of the second control signal terminal P2, thereby resetting (or initializing) the second node N2.

[0055] The third reset circuit 113 is electrically connected to the third reset voltage terminal Vref3, the third control signal terminal P3 and the anode of the light-emitting device 116, and is used to transmit the reset voltage of the third reset voltage terminal Vref3 to the anode of the light-emitting device 116 under the control of the third control signal of the third control signal terminal P3, thereby resetting (or initializing) the anode of the light-emitting device 116.

[0056] The write and threshold compensation circuit 114 is electrically connected to the fourth control signal terminal P4, the fifth control signal terminal P5, the second node N2, the first power supply voltage terminal ELVDD and the data voltage terminal Vdata, and is used to transmit the data voltage of the data voltage terminal Vdata to the write and threshold compensation circuit 114 under the control of the fourth control signal of the fourth control signal terminal P4 and the fifth control signal of the fifth control signal terminal P5, for data writing and threshold compensation.

[0057] The emission control circuit 115 is electrically connected to the emission control signal terminal (emission, EM), the first power supply voltage terminal ELVDD, the write and threshold compensation circuit 114 and the light-emitting device 116, and is used to provide a driving current to the light-emitting device 116 under the control of the emission control signal provided by the emission control signal terminal EM.

[0058] The light emitting device 116 is electrically connected to the second power voltage terminal ELVSS and is configured to emit light when driven by a driving current.

[0059] In the embodiment of the present application, the first power supply voltage terminal ELVDD is a high-level power supply voltage terminal, and the second power supply voltage terminal ELVSS is a low-level power supply voltage terminal. However, this is not limiting.

[0060] In some embodiments, referring to FIG. 2 , the write and threshold compensation circuit 114 includes a driving thin film transistor (DTFT) T1. The control electrode (e.g., gate) of the driving transistor T1 is electrically connected to a first node N1 (i.e., to the first reset circuit 111). The first electrode (e.g., source or drain) of the driving transistor T1 is electrically connected to a second node N2 (i.e., to the second reset circuit 112).

[0061] Furthermore, the write and threshold compensation circuit 114 also includes a second transistor T2, a third transistor T3, and a storage capacitor Cst, the first reset circuit 111 includes a fourth transistor T4, the second reset circuit 112 includes an eighth transistor T8, the third reset circuit 113 includes a seventh transistor T7, and the light emitting control circuit 115 includes a fifth transistor T5 and a sixth transistor T6.

[0062] The second transistor T2 , the third transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 and the eighth transistor T8 are switching transistors, and the light emitting device 116 is, for example, an OLED, a micro OLED, a QLED, etc.

[0063] In the following description, the control electrode of the transistor may be, for example, the gate electrode of the transistor, and the first electrode of the transistor and the second electrode of the transistor may be the source electrode and the drain electrode of the transistor, respectively.

[0064] The control electrode of the driving transistor T1 is electrically connected to the first node N1 , the first electrode of the driving transistor T1 is electrically connected to the second node N2 , and the second electrode of the driving transistor T1 is electrically connected to the first electrode of the third transistor T3 .

[0065] The control electrode of the second transistor T2 is electrically connected to the fourth control signal terminal P4 , the first electrode of the second transistor T2 is electrically connected to the data voltage terminal Vdata, and the second electrode of the second transistor T2 is electrically connected to the second node N2 .

[0066] A control electrode of the third transistor T3 is electrically connected to the fifth control signal terminal P5 , and a second electrode of the third transistor T3 is electrically connected to the first node N1 .

[0067] One end of the storage capacitor Cst is electrically connected to the first node N1 , and the other end of the storage capacitor Cst is coupled to the first power voltage terminal ELVDD.

[0068] A control electrode of the fourth transistor T4 is electrically connected to the first control signal terminal P1 , a first electrode of the fourth transistor T4 is electrically connected to the first reset voltage terminal Vref1 , and a second electrode of the fourth transistor T4 is electrically connected to the first node N1 .

[0069] The control electrode of the seventh transistor T7 is electrically connected to the third control signal terminal P3 , the first electrode of the seventh transistor T7 is electrically connected to the third reset voltage terminal Vref3 , and the second electrode of the seventh transistor T7 is electrically connected to the anode of the light emitting device 116 .

[0070] A control electrode of the eighth transistor T8 is electrically connected to the second control signal terminal P2 , a first electrode of the eighth transistor T8 is electrically connected to the second reset voltage terminal Vref2 , and a second electrode of the eighth transistor T8 is electrically connected to the second node N2 .

[0071] A control electrode of the fifth transistor T5 is electrically connected to the light emitting control signal terminal EM, a first electrode of the fifth transistor T5 is electrically connected to the first power supply voltage terminal ELVDD, and a second electrode of the fifth transistor T5 is electrically connected to the second node N2.

[0072] The control electrode of the sixth transistor T6 is electrically connected to the light emitting control signal terminal EM, the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the driving transistor T1 , and the second electrode of the sixth transistor T6 is electrically connected to the anode of the light emitting device 116 .

[0073] For example, in the pixel circuit 11, the third transistor T3 and the fourth transistor T4 are oxide thin-film transistors (oxide thin-film transistors, Oxide TFTs), which are N-type transistors and are turned on under the control of a high-level signal. The third transistor T3 and the fourth transistor T4 can also be other types of transistors, which are not limited in the embodiments of the present application. The driving transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are low-temperature polysilicon thin-film transistors (low temperature poly-silicon thin-film transistors, LTPS TFTs), which are P-type transistors and are turned on under the control of a low-level signal. The driving transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 can also be other types of transistors, which are not limited in the embodiments of the present application.

[0074] FIG3 is a driving timing diagram of a pixel circuit provided in an embodiment of the present application.

[0075] 2 and 3 , the light emitting process of the pixel circuit 11 in one image frame can be divided into an initialization phase t1 , a data writing and compensation phase t2 , a light emitting phase t3 , and an anode reset phase t4 .

[0076] In the initialization phase t1:

[0077] The first control signal at the first control signal terminal P1 changes from a low level to a high level, and then from a high level to a low level. Consequently, the fourth transistor T4 changes from off to on, and then from on to off. The second control signal at the second control signal terminal P2 changes from a high level to a low level, and then from a low level to a high level. Consequently, the eighth transistor T8 changes from off to on, and then from on to off.

[0078] The fifth control signal of the fifth control signal terminal P5 maintains a low level, the fourth control signal of the fourth control signal terminal P4 and the light-emitting control signal of the light-emitting control signal terminal EM all maintain a high level, therefore, the seventh transistor T7, the second transistor T2, the third transistor T3, the fifth transistor T5 and the sixth transistor T6 all remain in the off state.

[0079] During the initialization phase t1, the fourth transistor T4 is turned on, achieving voltage control of the first node N1. Since the fourth transistor T4 is electrically connected to the control electrode of the driving transistor T1, during the initialization phase t1, voltage control of the control electrode of the driving transistor T1 and voltage control of one end of the storage capacitor Cst are achieved, so that the voltage of the control electrode of the driving transistor T1 and the voltage of one end of the storage capacitor Cst are respectively reset to the reset voltage of the first reset voltage terminal Vref1. In other words, the voltage of the control electrode of the driving transistor T1 and the voltage of one end of the storage capacitor Cst are reset.

[0080] At the same time, the eighth transistor T8 is turned on, achieving voltage control of the second node N2. Since the eighth transistor T8 is electrically connected to the first electrode of the driving transistor T1, the voltage of the first electrode of the driving transistor T1 is controlled during the initialization phase t1, so that the voltage of the first electrode of the driving transistor T1 is reset to the reset voltage of the second reset voltage terminal Vref2. In other words, the voltage of the first electrode of the driving transistor T1 is reset to adjust the threshold voltage of the driving transistor T1.

[0081] In the data writing and compensation phase t2:

[0082] The fourth control signal at the fourth control signal terminal P4 changes from a high level to a low level, and then from a low level to a high level. Consequently, the second transistor T2 changes from off to on, and then from on to off. The fifth control signal at the fifth control signal terminal P5 changes from a low level to a high level, and then from a high level to a low level. Consequently, the third transistor T3 changes from off to on, and then from on to off.

[0083] The second control signal at the second control signal terminal P2, the third control signal at the third control signal terminal P3, and the light-emitting control signal at the light-emitting control signal terminal EM all maintain a high level, and the first control signal at the first control signal terminal P1 maintains a low level. Therefore, the seventh transistor T7, the eighth transistor T8, the fifth transistor T5, the sixth transistor T6, and the fourth transistor T4 all remain in the off state.

[0084] During the data writing and compensation phase t2, transistors T2, T3, and T1 are turned on, storing the data voltage at the data voltage terminal Vdata in the storage capacitor Cst, completing the data voltage writing. This also compensates for the threshold voltage of the driving transistor T1. The threshold voltage compensation process of the driving transistor T1 can be considered as the process of the driving transistor T1 switching from an on state to an off state.

[0085] In the lighting phase t3:

[0086] The light emitting control signal changes from high level to low level, and then changes from low level to high level. Thus, the sixth transistor T6 and the fifth transistor T5 change from off to on, and then from on to off.

[0087] The first control signal at the first control signal terminal P1 and the fifth control signal at the fifth control signal terminal P5 remain at a low level, and the fourth transistor T4 and the third transistor T3 both remain in an off state. The second control signal at the second control signal terminal P2, the third control signal at the third control signal terminal P3, and the fourth control signal at the fourth control signal terminal P4 each remain at a high level, and the seventh transistor T7, the eighth transistor T8, and the second transistor T2 all remain in an off state.

[0088] In the light emitting stage t3 , the fifth transistor T5 , the driving transistor T1 and the sixth transistor T6 are turned on respectively to transmit the driving current to the light emitting device 116 , and the light emitting device 116 emits light under the driving current.

[0089] Anode reset phase t:

[0090] The third control signal of the third control signal terminal P3 changes from high level to low level and then changes from low level to high level. Thus, the seventh transistor T7 changes from off to on and then from on to off.

[0091] The first control signal at the first control signal terminal P1 and the fifth control signal at the fifth control signal terminal P5 always maintain a low level, the second control signal at the second control signal terminal P2, the fourth control signal at the fourth control signal terminal P4, and the light-emitting control signal at the light-emitting control signal terminal EM always maintain a high level. The third transistor T3, the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 all remain in the off state.

[0092] In the anode reset phase t, the seventh transistor T7 is turned on to control the anode voltage of the light emitting device 116 so that the anode voltage of the light emitting device 116 is the reset voltage of the third reset voltage terminal Vref3, thereby resetting the anode voltage of the light emitting device 116.

[0093] Within an image frame, an anode reset phase t1 can be performed before each of the initialization phase t1, the data writing and compensation phase t2, and the light-emitting phase t3. Alternatively, an anode reset can be performed before one or both of the three phases. The drive timing diagram shown in FIG3 illustrates an example in which an anode reset is performed before each of the initialization phase t1, the data writing and compensation phase t2, and the light-emitting phase t3.

[0094] The working mode of the multiple rows of pixel circuits 11 is row-by-row refresh, that is, after the first row of pixel circuits 11 completes the above-mentioned initialization stage t1, data writing and compensation stage t2, light-emitting stage t3, and anode reset stage t, the second row of pixel circuits 11 enters the above-mentioned initialization stage t1, data writing and compensation stage t2, light-emitting stage t3, and anode reset stage t, and then each subsequent row of pixel circuits 11 repeats the above-mentioned initialization stage t1, data writing and compensation stage t2, light-emitting stage t3, and anode reset stage t, and so on, row by row from top to bottom.

[0095] Below, the origins of the control signals received by the first control signal terminal P1, the second control signal terminal P2, the third control signal terminal P3, the fourth control signal terminal P4, the fifth control signal terminal P5, and the light-emitting control signal terminal EM in the pixel circuit 11, the reset voltages received by the first reset voltage terminal Vref1, the second reset voltage terminal Vref2, and the third reset voltage terminal Vref3, and the data voltage received by the data voltage terminal Vdata are schematically explained.

[0096] As shown in FIG1 , in some embodiments, the display screen 10 further includes a plurality of first integrated gate arrays GOA1, each of which is configured to provide a first control signal to a first control signal terminal P1 of a row of pixel circuits 11. Of course, each first integrated gate array GOA1 may also provide a first control signal to the first control signal terminals P1 of some pixel circuits 11 in a row of pixel circuits 11, and each row of pixel circuits 11 may correspond to a plurality of first integrated gate arrays GOA1.

[0097] For example, multiple first integrated gate circuits GOA1 are cascaded. The first integrated gate circuit GOA1 of the first stage receives the first start control signal and outputs the first control signal to the first control signal terminal P1 of the first row. Starting from the second stage of the first integrated gate circuit GOA1, the first integrated gate circuit GOA1 of each stage receives the first control signal output by the first integrated gate circuit GOA1 of the previous stage and outputs the first control signal to the first control signal terminal P1 coupled to the first integrated gate circuit GOA1 of the current stage, thereby providing the first control signal to the first control signal terminals P1 of multiple rows of pixel circuits 11 row by row.

[0098] As shown in FIG1 , in some embodiments, the display screen 10 further includes a plurality of second integrated gate circuits GOA2, each of which is configured to provide a second control signal to a second control signal terminal P2 of a row of pixel circuits 11. Of course, each second integrated gate circuit GOA2 may also provide a second control signal to the second control signal terminals P2 of some pixel circuits 11 in a row of pixel circuits 11, and each row of pixel circuits 11 may correspond to a plurality of second integrated gate circuits GOA2.

[0099] In some embodiments, the display screen 10 further includes a plurality of third integrated gate circuits GOA3, each of which is configured to provide a third control signal to a third control signal terminal P3 of a row of pixel circuits 11. Of course, each third integrated gate circuit GOA3 may also provide a third control signal to the third control signal terminals P3 of some pixel circuits 11 in a row of pixel circuits 11, and each row of pixel circuits 11 may correspond to a plurality of third integrated gate circuits GOA3.

[0100] In some embodiments, the display screen 10 further includes a plurality of fourth integrated gate circuits GOA4, each of which is configured to provide a fourth control signal to a fourth control signal terminal P4 of a row of pixel circuits 11. Of course, each fourth integrated gate circuit GOA4 may also provide a fourth control signal to the fourth control signal terminals P4 of some pixel circuits 11 in a row of pixel circuits 11, and each row of pixel circuits 11 may correspond to a plurality of fourth integrated gate circuits GOA4.

[0101] In some embodiments, the display screen 10 further includes a plurality of fifth integrated gate circuits GOA5, each of which is configured to provide a fifth control signal to a fifth control signal terminal P5 of a row of pixel circuits 11. Of course, each fifth integrated gate circuit GOA5 may also provide a fifth control signal to the fifth control signal terminals P5 of some pixel circuits 11 in a row of pixel circuits 11, and each row of pixel circuits 11 may correspond to a plurality of fifth integrated gate circuits GOA5.

[0102] In some embodiments, the display screen 10 further includes a plurality of sixth integrated gate circuits GOA6, each of which is configured to provide a light emission control signal to a light emission control signal terminal EM of a row of pixel circuits 11. Of course, each sixth integrated gate circuit GOA6 may also provide a light emission control signal to the light emission control signal terminals EM of some pixel circuits 11 in a row of pixel circuits 11, and each row of pixel circuits 11 may correspond to a plurality of sixth integrated gate circuits GOA6.

[0103] By pulling up and down the first integrated gate circuit GOA1, the second integrated gate circuit GOA2, the third integrated gate circuit GOA3, the fourth integrated gate circuit GOA4, the fifth integrated gate circuit GOA5 and the sixth integrated gate circuit GOA6 at different times, the multiple rows of pixel circuits 11 enter the above-mentioned initialization phase t1, data writing and compensation phase t2, light emitting phase t3, and anode reset phase t1 row by row.

[0104] It should be understood that the first integrated gate circuit GOA1, the second integrated gate circuit GOA2, the third integrated gate circuit GOA3, the fourth integrated gate circuit GOA4, the fifth integrated gate circuit GOA5, and the sixth integrated gate circuit GOA6 shown in FIG1 are distributed along the row direction on both sides of the multiple rows of pixel circuits 11 to generate control signals. The locations of the first integrated gate circuit GOA1, the second integrated gate circuit GOA2, the third integrated gate circuit GOA3, the fourth integrated gate circuit GOA4, the fifth integrated gate circuit GOA5, and the sixth integrated gate circuit GOA6 in the display screen 10 in FIG1 are merely illustrative and do not constitute any limitation.

[0105] The display screen 10 includes a plurality of data voltage terminals Vdata. Pixel circuits 11 in the same column are coupled to the same data voltage terminal Vdata. A display driver 20 is coupled to the plurality of data voltage terminals Vdata to provide data voltages to the plurality of data voltage terminals Vdata.

[0106] The display screen 10 also includes multiple reset voltage terminals. As shown in FIG. 2 , the embodiment of the present application uses a display screen including a first reset voltage terminal Vref1, a second reset voltage terminal Vref2, and a third reset voltage terminal Vref3 as an example. The display driver 20 is coupled to the first reset voltage terminal Vref1, the second reset voltage terminal Vref2, and the third reset voltage terminal Vref3 to provide reset voltages to the first reset voltage terminal Vref1, the second reset voltage terminal Vref2, and the third reset voltage terminal Vref3. The first reset voltage terminal Vref1, the second reset voltage terminal Vref2, and the third reset voltage terminal Vref3 are each coupled to multiple rows of pixel circuits 11 in the display screen 10.

[0107] To improve the display effect, a reset voltage is typically used in the pixel circuit 11 to improve the voltage stability of certain nodes in the pixel circuit 11. For example, in the pixel circuit 11 shown in FIG2 , a first reset voltage terminal Vref1, a second reset voltage terminal Vref2, and a third reset voltage terminal Vref3 provide reset voltages for the first node N1, the second node N2, and the anode of the light-emitting device 116 of the pixel circuit 11. The first reset voltage terminal Vref1 resets and initializes the storage capacitor Cst, the second reset voltage terminal Vref2 resets and initializes the source (or drain) of the driving transistor T1, and the third reset voltage terminal Vref3 resets and initializes the anode of the light-emitting device 116.

[0108] The reset voltages of the first reset voltage terminal Vref1, the second reset voltage terminal Vref2, and the third reset voltage terminal Vref3 are provided by the display driver 20 (DDIC), and during the scanning process of all row pixel circuits 11, the reset voltages of the first reset voltage terminal Vref1, the second reset voltage terminal Vref2, and the third reset voltage terminal Vref3 are always fixed. Then, when the scanning signal scans the vertical blanking area row by row, since the vertical blanking area is not actually coupled to the pixel circuit 11, the load coupled to the first reset voltage terminal Vref1, the second reset voltage terminal Vref2, and the third reset voltage terminal Vref3 as the power supply will be reduced. This causes the first reset voltage terminal Vref1, the second reset voltage terminal Vref2, and the third reset voltage terminal Vref3 to have reset voltage jitter in high and low load scenarios, thereby causing the reset voltages of the specific row pixel circuits 11 to be different (different reset states), and the display brightness to be different, causing horizontal bright bands or dark bands to appear on the display screen 10.

[0109] Figure 4A is a pulse diagram of a reset voltage according to an embodiment of the present application. Figure 4B is a display effect diagram of a display screen according to an embodiment of the present application.

[0110] For example, using the drive timing sequence shown in FIG3 as an example, within an image frame, the anode reset phase t is executed three times. As shown in FIG4A , within an image frame, during the three on-off reset cycles of the third reset circuit 113, the third reset voltage terminal Vref3 resets the pixel circuit 11 three times, resulting in three voltage jitters at the third reset voltage terminal Vref3. However, due to the presence of a vertical blanking region (V blank) in the display screen 10, as shown in FIG4B , this voltage jitter results in two dark bands appearing on the display: the pixel circuits 11 in rows M+1-1 appear darker, and the pixel circuits 11 in rows L+1-T appear darker.

[0111] FIG4C is a schematic diagram of a layout of wiring in a display screen according to an embodiment of the present application.

[0112] Furthermore, as shown in FIG4C , due to the specific design features of display screen 10, such as a punch-hole display, a notch display, a multi-hole display, or a pillar display, the routing lines coupled to the integrated gate circuits in the special design areas differ from those in other areas. Taking the routing lines coupled to the first integrated gate circuit GOA1 as an example, the routing lines in the special design areas need to bypass the special area, causing the routing lines in the rows corresponding to the special areas to be longer and have a heavier load than those in the normal areas, thereby affecting the charging time of the pixel circuits 11. For example, in FIG4C , the M+1th routing line bypasses above the special area, while the Ith routing line bypasses below the special area. Therefore, the routing lines corresponding to the pixel circuits 11 in the M+1th row and the Nth row are longer and have a heavier load than those in the normal areas. This results in a difference in display brightness between the pixel circuits 11 in the M+1th row and the Nth row, compared to the display brightness of the other pixel circuits 11 in display screen 10, resulting in noticeable horizontal bright or dark bands during low-brightness and low-grayscale display, or what can be understood as mura in the special area.

[0113] FIG4D is a schematic diagram of a partition display of a display screen 10 according to an embodiment of the present application.

[0114] Furthermore, as shown in FIG4D , with the development of display technology, the display screen 10 will have the need to display multiple frame rates in different areas, that is, a multi-frequency display scenario. In a multi-frequency display scenario, there are multiple refresh rates when the same screen is displayed. For example, the area of ​​a certain width in the middle of FIG4D is a high refresh rate, and the upper and lower areas are low refresh rates. Since there are multiple different refresh rates on the display screen 10 at the same time, and the brightness between different refresh rates is different, the brightness of the two areas may be different when the high refresh rate and the low refresh rate are displayed. Then, the display screen 10 will have obvious display boundaries at the boundaries of different frame rates, that is, the display brightness is uneven.

[0115] Therefore, as display application scenarios continue to increase, the display screen 10 has a significant problem of uneven brightness, which affects the user experience.

[0116] FIG5 is a timing diagram of a display screen according to an embodiment of the present application.

[0117] To improve the uniformity of the display screen 10, in some embodiments, as shown in FIG5 , a scheme for dynamically adjusting the bias voltage Vbias and the reset voltage Vref is designed to address the flicker problem during low frame rate display. During low frame rate display, the voltage drift of the driving transistor T1 in the pixel circuit 11 causes brightness changes, resulting in subjective perception of flicker. Therefore, the bias voltage Vbias and the reset voltage Vref are adjusted at the beginning of some or all frames to compensate for the brightness differences between different frames through voltage compensation.

[0118] However, this method can only compensate for the brightness difference between different frames when displayed at a low frame rate, and has no effect on the brightness difference when displayed at a high frame rate or the bright or dark bands in the same frame.

[0119] Based on this, the embodiment of the present application also provides a row-level voltage regulation scheme, that is, the reset voltage in the pixel circuit 11 can be adjusted to compensate for the display brightness according to the number of displayed rows (or display position) in an image frame, so as to improve the display process of the display screen 10 due to the brightness difference between high and low frame rate areas during multi-frequency display, uneven display brightness in the hole screen area, load changes and other reasons. The problem of horizontal brightness unevenness (horizontal bright bands or dark bands).

[0120] An embodiment of the present application provides a display screen 10, which includes N rows of pixels, and each row of pixels includes a plurality of pixel circuits 11 arranged at intervals. The arrangement of the pixel circuits 11 can be shown in FIG1 , and the structure of the pixel circuits 11 can be shown in FIG2 . N is a positive integer, and the embodiment of the present application does not limit the value of N, which can be determined in combination with the shape of the display screen 10. Of course, the value of the number of rows N in the display screen 10 can be greater than the number of pixel circuits 11 included in each row of pixels (that is, the number of columns of the display screen 10), and the value of the number of rows N in the display screen 10 can also be less than or equal to the number of pixel circuits 11 included in each row of pixels (that is, the number of columns of the display screen 10).

[0121] The display screen 10 further includes a plurality of reset voltage terminals, each of which is electrically connected to N rows of pixels. In other words, each reset voltage terminal is coupled to all pixel circuits 11 in the display screen 10 .

[0122] Among them, at least one reset voltage terminal among the multiple reset voltage terminals is configured to provide a first reset voltage to the pixel circuit in a first time period within an image frame, and to provide a second reset voltage to the pixel circuit in a second time period within the image frame; the value of the first reset voltage is different from the value of the second reset voltage.

[0123] That is to say, within an image frame, the same reset voltage terminal will provide a first reset voltage to the display screen 10 in the first time period. However, in the second time period, the reset voltage terminal will provide a second reset voltage to the display screen 10. The reset voltage provided by the same reset voltage terminal is variable, so the reset voltages received by the same ports (such as the first reset voltage terminal Vref1) of different rows of pixel circuits 11 are also different. The first part of the row pixels in the N rows of pixels are used to receive the first reset voltage in the first time period, and the second part of the row pixels in the N rows of pixels are used to receive the second reset voltage in the second time period. The sum of the first part and the second part can be equal to N, and the sum of the first part and the second part can also be less than N. The embodiment of the present application does not limit the arrangement of the pixels that receive the first reset voltage and the pixels that receive the second reset voltage in the N rows of pixels.

[0124] In the display screen 10 provided in an embodiment of the present application, a reset voltage terminal provides a first reset voltage during a first period within an image frame and a second reset voltage during a second period within the image frame, with the value of the first reset voltage being different from the value of the second reset voltage. Consequently, a first portion of rows of pixels in the display screen 10 receive the first reset voltage, while a second portion of rows of pixels receive the second reset voltage. While the reset voltage is fixed, factors such as a non-constant load, a non-constant frame rate, and voltage fluctuations can lead to uneven display brightness. In the embodiment of the present application, by providing a variable reset voltage to N rows of pixel circuits within an image frame, the effects of these non-constant loads, non-constant frame rates, and voltage fluctuations can be compensated, thereby improving the uneven display brightness. Furthermore, the reset voltage value can be dynamically adjusted based on the position of the pixel rows in the display screen 10. The rows receiving the first reset voltage and the rows receiving the second reset voltage can be dynamically adjusted, and pixel rows in multiple alternate regions can receive the first reset voltage, while pixel rows in multiple alternate regions receive the second reset voltage. This dynamic and flexible adjustment method is applicable to a wide range of scenarios and applications.

[0125] The brightness of the pixel circuit 11 is related to the magnitude of the driving current I, where I=α·(V N1 -ELVDD+Vth) 2 α is a constant that is related to the width-to-length ratio and mobility of the driving transistor T1. Once the driving transistor T1 in the pixel circuit 11 is determined, α becomes a fixed value. N1 is the voltage of the first node N1, and Vth is the threshold voltage of the driving transistor T1.

[0126] The voltage V at the first node N1 N1 The data voltage terminal Vdata charges the driving transistor T1 during the data writing and compensation phase t2, which is equivalent to charging the resistor-capacitor (RC) circuit. In one row, the lower the initial voltage of the first node N1, the higher the voltage V at the first node N1 after charging.N1 According to the above formula of driving current I, the voltage V N1 The lower the voltage V of the first node N1 is, the N1 The larger the absolute value of , the larger the driving current I is, and the higher the brightness of the light emitting device 116 is. On the contrary, the voltage V N1 The higher the voltage, the smaller the driving current I, and the lower the brightness of the light-emitting device 116. Therefore, adjusting the initial voltage of the first node N1 can adjust the brightness of the light-emitting device 116. The initial voltage of the first node N1 can be adjusted by the reset voltage of the first reset voltage terminal Vref1.

[0127] The threshold voltage Vth of the driving transistor T1 is obtained by performing threshold voltage compensation on the driving transistor T1 using the data voltage terminal Vdata during the data writing and compensation phase t2. Within a row, the higher the voltage at the second node N2, the greater the absolute value of the threshold voltage Vth of the driving transistor T1 after compensation, resulting in a greater drive current I and higher brightness of the light-emitting device 116. Therefore, adjusting the voltage at the second node N2 can adjust the brightness of the light-emitting device 116. The voltage at the second node N2 can also be adjusted by the reset voltage at the second reset voltage terminal Vref2.

[0128] Furthermore, the brightness of light-emitting device 116 is proportional to the duration of its illumination, which in turn is related to both the initial voltage at the anode of light-emitting device 116 and the drive current I. The principle of light-emitting device 116's illumination is as follows: when the voltage difference between the anode and cathode of light-emitting device 116 exceeds a set value, light-emitting device 116 begins to emit light. The drive circuit charges the anode of light-emitting device 116. Once the anode of light-emitting device 116 is charged to a preset value, light-emitting device 116 begins to emit light. The size of drive circuit I affects the speed at which the anode is charged to the preset value, and the initial voltage of the anode also affects the speed at which the anode is charged to the preset value. For example, if the charging speed is the same, a lower initial voltage will take longer to charge to the preset value, resulting in a shorter illumination duration and a lower brightness of light-emitting device 116. A higher initial voltage will shorten the time required to charge to the preset value, increasing the illumination duration. This is equivalent to increasing the duty cycle of light-emitting device 116, which in turn increases the brightness of light-emitting device 116. Therefore, by adjusting the starting voltage of the anode of the light emitting device 116, the brightness of the light emitting device 116 can also be adjusted. The starting voltage of the anode of the light emitting device 116 can be adjusted by the reset voltage of the third reset voltage terminal Vref3.

[0129] In summary, the brightness of the light emitting device 116 can be adjusted by adjusting the voltage of the first node N1 , adjusting the voltage of the second node N2 , and adjusting the voltage of the anode of the light emitting device 116 .

[0130] Based on this, in some embodiments, as shown in FIG. 2 , the multiple reset voltage terminals in the display screen 10 include a first reset voltage terminal Vref1 , and the pixel circuit 11 includes a first reset circuit 111 .

[0131] The first reset circuit 111 has two terminals electrically connected to the control electrode of the driving transistor T1 and the first reset voltage terminal Vref1, respectively. Under the control of the first control signal terminal P1, the reset voltage of the first reset voltage terminal Vref1 is transmitted to the control electrode (first node N1) of the driving transistor T1 via the first reset circuit 111, thereby initializing and resetting the control electrode of the driving transistor T1. By adjusting the reset voltage of the first reset voltage terminal Vref1, the driving current of the pixel circuit 11 can be adjusted, thereby adjusting the light emission brightness of the pixel circuit 11.

[0132] In other embodiments, as shown in FIG. 2 , the plurality of reset voltage terminals in the display screen 10 include a second reset voltage terminal Vref2 , and the pixel circuit 11 includes a driving transistor T1 and a second reset circuit 112 .

[0133] The two ends of the second reset circuit 112 are electrically connected to the first electrode (source or drain) of the driving transistor T1 and the second reset voltage terminal Vref2, respectively. Under the control of the second control signal terminal P2, the reset voltage of the second reset voltage terminal Vref2 is transmitted to the first electrode (second node N2) of the driving transistor T1 via the second reset circuit 112, thereby initializing and resetting the first electrode of the driving transistor T1. By adjusting the reset voltage of the second reset voltage terminal Vref2, the driving current of the pixel circuit 11 can be adjusted, thereby adjusting the light emitting brightness of the pixel circuit 11.

[0134] In some further embodiments, as shown in FIG. 2 , the multiple reset voltage terminals in the display screen 10 include a third reset voltage terminal Vref3 , and the pixel circuit 11 includes a light emitting device 116 and a third reset circuit 113 .

[0135] The third reset circuit 113 has two terminals electrically connected to the anode of the light-emitting device 116 and the third reset voltage terminal Vref3, respectively. Under the control of the third control signal terminal P3, the reset voltage of the third reset voltage terminal Vref3 is transmitted to the anode of the light-emitting device 116 via the third reset circuit 113, thereby initializing and resetting the anode of the light-emitting device 116. By adjusting the reset voltage of the third reset voltage terminal Vref3, the light-emitting duration of the pixel circuit 11 can be adjusted, thereby adjusting the light-emitting brightness of the pixel circuit 11.

[0136] In some embodiments, the first reset voltage terminal Vref1 is configured to provide a first reset voltage to pixels in the 1st to Mth rows, a second reset voltage to pixels in the M+1th to Ith rows, and a first reset voltage to pixels in the I+1th to Nth rows.

[0137] In some embodiments, the second reset voltage terminal Vref2 is configured to provide a first reset voltage to pixels in the 1st to Mth rows, a second reset voltage to pixels in the M+1th to Ith rows, and a first reset voltage to pixels in the I+1th to Nth rows.

[0138] In some embodiments, the third reset voltage terminal Vref1 is configured to provide a first reset voltage to pixels in the 1st to Mth rows, a second reset voltage to pixels in the M+1th to Ith rows, and a first reset voltage to pixels in the I+1th to Nth rows.

[0139] Of course, the values ​​of the first reset voltage provided by the first reset voltage terminal Vref1, the first reset voltage provided by the second reset voltage terminal Vref2, and the first reset voltage provided by the third reset voltage terminal Vref3 are not limited to being the same, and the values ​​of the second reset voltage provided by the first reset voltage terminal Vref1, the second reset voltage provided by the second reset voltage terminal Vref2, and the second reset voltage provided by the third reset voltage terminal Vref3 are not limited to being the same, and are related to the values ​​of the reset voltages actually required by the pixel circuit 11.

[0140] In addition, the first reset voltage terminal Vref1 provides a first time period of the first reset voltage, the second reset voltage terminal Vref2 provides a first time period of the first reset voltage, and the third reset voltage terminal Vref3 provides a first time period of the first reset voltage, which are not limited to being the same; the first reset voltage terminal Vref1 provides a second time period of the second reset voltage, the second reset voltage terminal Vref2 provides a second time period of the second reset voltage, and the third reset voltage terminal Vref3 provides a second time period of the second reset voltage, which are not limited to being the same, and are related to the driving stage of the pixel circuit 11 within an image frame.

[0141] In the first application scenario, uneven display brightness is caused by uneven arrangement of pixel circuits 11 in various areas of the display screen 10, such as display screens with holes, bangs, multi-holes, and pill screens.

[0142] In some embodiments, the first reset voltage terminal Vref1 transmits a first reset voltage to the uniformly arranged area and transmits a second reset voltage to the non-uniformly arranged area.

[0143] As shown in FIG6 , the first reset voltage is used as the base voltage. Within an image frame, when the display screen 10 scans the non-special area (rows 1 to M) shown in FIG4C , the first reset voltage terminal Vref1 outputs the first reset voltage. When the display screen 10 scans the special area (rows M+1 to I) shown in FIG4C , a determination is made as to whether to increase or decrease the reset voltage (determine the compensation voltage) based on the brightness difference between the pixel circuits 11 in the special area and the pixel circuits 11 in the non-special area. At this time, the second reset voltage output by the first reset voltage terminal Vref1 is the adjusted reset voltage. For example, if the brightness of the pixel circuits 11 in the special area needs to be increased, the reset voltage needs to be decreased based on the first reset voltage. If the brightness of the pixel circuits 11 in the special area needs to be decreased, the reset voltage needs to be increased based on the first reset voltage. After the display screen 10 completes scanning the special area (enters row I+1), the first reset voltage terminal Vref1 again outputs the first reset voltage.

[0144] Of course, in other embodiments, the second reset voltage is used as the base voltage. Within an image frame, when the display screen 10 scans and opens to the non-special area (rows 1 to M) shown in FIG4C , a determination is made as to whether to increase the reset voltage or decrease the reset voltage (determine the compensation voltage) based on the second reset voltage based on the brightness difference between the pixel circuits 11 in the special area and the pixel circuits 11 in the non-special area. At this time, the first reset voltage output by the first reset voltage terminal Vref1 is the adjusted reset voltage. For example, if the brightness of the pixel circuits 11 in the non-special area needs to be increased, the reset voltage needs to be decreased based on the second reset voltage. If the brightness of the pixel circuits 11 in the special area needs to be decreased, the reset voltage needs to be increased based on the second reset voltage. When the display screen 10 scans and opens to the special area (rows M+1 to I) shown in FIG4C , the first reset voltage terminal Vref1 outputs the second reset voltage. After the display screen 10 completes scanning the special area (enters row I+1), the first reset voltage terminal Vref1 again outputs the first reset voltage.

[0145] It should be noted here that in the embodiments of the present application, the display brightness of the non-special regions on the upper and lower sides of the special region is taken as an example to be the same. Therefore, the non-special regions on the upper and lower sides of the special region both receive the first reset voltage from the first reset voltage terminal Vref1. If the display brightness of the non-special regions on the upper and lower sides of the special region is different, then the values of the reset voltages received by the non-special regions on the upper and lower sides of the special region from the first reset voltage terminal Vref1 may also be different, but the principle of reset voltage adjustment remains the same. That is, if it is necessary to increase the brightness of the pixel circuit 11, the reset voltage needs to be adjusted downward based on the set basic voltage. If it is necessary to decrease the brightness of the pixel circuit 11, the reset voltage needs to be adjusted upward based on the set basic voltage.

[0146] In the embodiments of the present application, M can take a value of 0 or a positive integer, the values of I and N are both positive integers, and M < I < N. Of course, the embodiments of the present application do not limit the values of M, I, and N, and they can be combined according to the product settings.

[0147] For the display screen 10 provided in the embodiments of the present application, to solve the problem of uneven display brightness caused by the uneven arrangement of the pixel circuits 11, when the first reset voltage terminal Vref1 supplies power to multiple rows of pixel circuits 11, it provides the first reset voltage for the regions where the pixel circuits 11 are evenly arranged, and provides the second reset voltage for the special regions where the pixel circuits 11 are unevenly arranged, so as to compensate the reset voltage for either the regions where the pixel circuits 11 are unevenly arranged or the regions where they are evenly arranged, thereby achieving brightness compensation for regions with different arrangement rules and improving the problem of uneven display brightness.

[0148] In some embodiments, the second reset voltage terminal Vref2 transmits the first reset voltage to the uniformly arranged region and transmits the second reset voltage to the non-uniformly arranged region. The switching principle of the reset voltage is the same as that of the first reset voltage and the second reset voltage in the first reset voltage terminal Vref1, and will not be elaborated here.

[0149] In some embodiments, the third reset voltage terminal Vref3 transmits the first reset voltage to the uniformly arranged region and transmits the second reset voltage to the non-uniformly arranged region. The switching principle of the reset voltage is the same as that of the first reset voltage and the second reset voltage in the first reset voltage terminal Vref1, and will not be elaborated here.

[0150] In the second application scenario, the problem of uneven display brightness is caused by different refresh rates in different regions of the display screen 10.

[0151] In some embodiments, the first reset voltage terminal Vref1 transmits the first reset voltage to the low refresh rate region and transmits the second reset voltage to the high refresh rate region.

[0152] As shown in FIG7 , the first reset voltage is used as the base voltage. Within an image frame, when the display screen 10 scans and opens to the low refresh rate area (row 1 to row M) shown in FIG7 , the first reset voltage terminal Vref1 outputs the first reset voltage. When the display screen 10 scans and opens to the high refresh rate area (row M+1 to row I) shown in FIG7 , based on the brightness difference between the pixel circuits 11 in the low refresh rate area and the pixel circuits 11 in the high refresh rate area, it is determined whether to increase the reset voltage or decrease the reset voltage (determine the compensation voltage) based on the first reset voltage. At this time, the second reset voltage output by the first reset voltage terminal Vref1 is the adjusted reset voltage. For example, if it is necessary to increase the brightness of the pixel circuit 11 in the high refresh rate area, it is necessary to decrease the reset voltage based on the first reset voltage. If it is necessary to decrease the brightness of the pixel circuit 11 in the high refresh rate area, it is necessary to increase the reset voltage based on the first reset voltage. After the display screen 10 scans the high refresh rate area and enters the low refresh rate area (enters row I+1), the first reset voltage terminal Vref1 again outputs the first reset voltage.

[0153] Of course, in other embodiments, the second reset voltage is used as the base voltage. Within an image frame, when the display screen 10 scans and opens to the low refresh rate area (row 1-row M) shown in FIG4D, based on the brightness difference between the pixel circuit 11 in the low refresh rate area and the pixel circuit 11 in the high refresh rate area, it is determined whether to increase the reset voltage or decrease the reset voltage (determine the compensation voltage) based on the second reset voltage. At this time, the first reset voltage output by the first reset voltage terminal Vref1 is the adjusted reset voltage. For example, if it is necessary to increase the brightness of the pixel circuit 11 with a low refresh rate, it is necessary to lower the reset voltage based on the second reset voltage. If it is necessary to reduce the brightness of the pixel circuit 11 in the low refresh rate area, it is necessary to increase the reset voltage based on the second reset voltage. When the display screen 10 scans and opens to the high refresh rate area (row M+1-row I) shown in FIG4D, the first reset voltage terminal Vref1 outputs the second reset voltage. After the display screen 10 finishes scanning the high refresh rate area and enters the low refresh rate area (enters row I+1), the first reset voltage terminal Vref1 again outputs the first reset voltage.

[0154] It should be noted here that in the embodiments of the present application, the display brightness of the low refresh rate regions on the upper and lower sides of the high refresh rate region is taken as an example to be the same. Therefore, the low refresh rate regions on the upper and lower sides of the high refresh rate region both receive the first reset voltage from the first reset voltage terminal Vref1. If the display brightness of the low refresh rate regions on the upper and lower sides of the ultra-high refresh rate region is different, then the values of the reset voltages received by the low refresh rate regions on the upper and lower sides of the high refresh rate region from the first reset voltage terminal Vref1 may also be different, but the principle of reset voltage adjustment remains the same. That is, if it is necessary to increase the brightness of the pixel circuit 11, the reset voltage needs to be adjusted downward based on the set basic voltage. If it is necessary to decrease the brightness of the pixel circuit 11, the reset voltage needs to be adjusted upward based on the set basic voltage.

[0155] In the embodiments of the present application, M can take a value of 0 or a positive integer, and the values of I and N are both positive integers, and M < I < N. Of course, the embodiments of the present application do not limit the values of M, I, and N, and they can be combined according to the product settings.

[0156] For the display screen 10 provided in the embodiments of the present application, to address the problem of uneven display brightness caused by different refresh rates, when the first reset voltage terminal Vref1 supplies power to multiple rows of pixel circuits 11, it provides the first reset voltage for the low refresh rate region and the second reset voltage for the high refresh rate region, so as to compensate the reset voltage for either the low refresh rate region or the high refresh rate region to achieve brightness compensation for regions with different refresh rates and improve the problem of uneven display brightness.

[0157] In some embodiments, the second reset voltage terminal Vref2 transmits the first reset voltage to the low refresh rate region and the second reset voltage to the high refresh rate region. The switching principle of the reset voltage is the same as that of the first reset voltage and the second reset voltage in the first reset voltage terminal Vref1, and will not be elaborated here.

[0158] In some embodiments, the third reset voltage terminal Vref3 transmits the first reset voltage to the low refresh rate region and the second reset voltage to the high refresh rate region. The switching principle of the reset voltage is the same as that of the first reset voltage and the second reset voltage in the first reset voltage terminal Vref1, and will not be elaborated here.

[0159] In the third application scenario, due to the uneven arrangement of the pixel circuits 11 in each region of the display screen 10 and different refresh rates, there is a problem of uneven display brightness.

[0160] Then, the reset voltage output by the first reset voltage terminal Vref not only includes the first reset voltage and the second reset voltage, but may also include the third reset voltage or more reset voltages with different values.

[0161] As shown in FIG. 7, when the special area is located in the low refresh rate area, when the first reset voltage terminal Vref1 provides a reset voltage to the pixel rows in the low refresh rate area, the relevant description of FIG. 6 can be combined to perform reset voltage compensation for the special area and the non-special area in the low refresh rate area, so as to make the display in the low refresh rate area uniform.

[0162] It should be understood that taking the structure shown in FIG. 7 as an example, when combining the reset voltage compensation for the special area and the non-special area with the reset voltage compensation for the high refresh rate area and the low refresh rate area, the values of M and I when dividing the special area and the non-special area are different from the values of M and I when dividing the high refresh rate area and the low refresh rate area.

[0163] Then it can be equivalently considered that the first reset voltage terminal Vref1 is configured to provide a first reset voltage to the pixels in rows 1 - row M (non-special area in the low refresh rate area), provide a second reset voltage to the pixels in rows M + 1 - row I (non-special area in the low refresh rate area), provide a first reset voltage to the pixels in rows I + 1 - row L (non-special area in the low refresh rate area), provide a third reset voltage to the pixels in rows L + 1 - row T (high refresh rate area), and provide a first reset voltage to the pixels in rows T + 1 - row N (low refresh rate area).

[0164] In the embodiments of the present application, the value of M can be 0 or a positive integer, and the values of I, L, T, and N are all positive integers, and M < I < L < T < N. Of course, the embodiments of the present application do not limit the values of M, I, L, T, and N, and they can be combined according to the product settings.

[0165] In some embodiments, the second reset voltage terminal Vref2 transmits a first reset voltage to the non-special area in the low refresh rate area, transmits a second reset voltage to the non-special area in the low refresh rate area, transmits a first reset voltage to the non-special area in the low refresh rate area, transmits a third reset voltage to the high refresh rate area, and transmits a first reset voltage to the low refresh rate area. The switching principle of the reset voltage is the same as the switching principle of the first reset voltage, the second reset voltage, and the third reset voltage in the first reset voltage terminal Vref1, and will not be elaborated here.

[0166] In some embodiments, the third reset voltage terminal Vref3 transmits a first reset voltage to the non-special area in the low refresh rate area, transmits a second reset voltage to the non-special area in the low refresh rate area, transmits a first reset voltage to the non-special area in the low refresh rate area, transmits a third reset voltage to the high refresh rate area, and transmits a first reset voltage to the low refresh rate area. The switching principle of the reset voltage is the same as the switching principle of the first reset voltage, the second reset voltage, and the third reset voltage in the first reset voltage terminal Vref1, and will not be elaborated here.

[0167] The display screen 10 provided in the embodiment of the present application addresses the problem of uneven display brightness caused by uneven arrangement of pixel circuits 11 and different refresh rates. The first reset voltage terminal Vref1 provides a first reset voltage for a low refresh rate area and a second reset voltage for a high refresh rate area when powering multiple rows of pixel circuits 11. By selecting a compensation reset voltage for either the low refresh rate area or the high refresh rate area, brightness compensation is achieved for areas with different refresh rates, thereby improving the problem of uneven display brightness.

[0168] In the fourth application scenario, reset voltage jitter causes the problem of uneven display brightness.

[0169] In some embodiments, the first reset voltage terminal Vref1 is configured to provide a first reset voltage to pixels in the 1st to Mth rows (bright band area), provide a second reset voltage to pixels in the M+1th to Ith rows (dark band area), provide a first reset voltage to pixels in the I+1th to Lth rows (bright band area), provide a second reset voltage to pixels in the L+1th to Tth rows (dark band area), and provide a first reset voltage to pixels in the T+1th to Nth rows (bright band area).

[0170] Of course, the present embodiment is merely illustrative of an example in which the display brightness of the multiple bright band regions in the display screen 10 is the same. If the display brightness of the multiple bright band regions is different, the reset voltages outputted by the first reset voltage terminal Vref1 to these regions will also be different. Similarly, the embodiment in which the display brightness of the multiple dark band regions in the display screen 10 is the same is illustrative of an example in which the display brightness of the multiple dark band regions is different. If the display brightness of the multiple dark band regions is different, the reset voltages outputted by the first reset voltage terminal Vref1 to these regions will also be different.

[0171] In some embodiments, the second reset voltage terminal Vref2 is configured to provide a first reset voltage to the pixels in the 1st to Mth rows (bright band area), provide a second reset voltage to the pixels in the M+1th to Ith rows (dark band area), provide a first reset voltage to the pixels in the I+1th to Lth rows (bright band area), provide a second reset voltage to the pixels in the L+1th to Tth rows (dark band area), and provide a first reset voltage to the pixels in the T+1th to Nth rows (bright band area).

[0172] In some embodiments, as shown in Figure 8, the third reset voltage terminal Vref3 is configured to provide a first reset voltage to the pixels in the 1st to Mth rows (bright band area), provide a second reset voltage to the pixels in the M+1th to Ith rows (dark band area), provide a first reset voltage to the pixels in the I+1th to Lth rows (bright band area), provide a second reset voltage to the pixels in the L+1th to Tth rows (dark band area), and provide a first reset voltage to the pixels in the T+1th to Nth rows (bright band area).

[0173] In the embodiments of the present application, M can take a value of 0 or a positive integer, the values of I, L, T, and N are all positive integers, and M < I < L < T < N. Of course, the embodiments of the present application do not limit the values of M, I, L, T, and N, and they can be set according to the product.

[0174] Of course, the values of the first reset voltage provided by the first reset voltage terminal Vref1, the first reset voltage provided by the second reset voltage terminal Vref2, and the first reset voltage provided by the third reset voltage terminal Vref3 are not limited to being the same. The values of the second reset voltage provided by the first reset voltage terminal Vref1, the second reset voltage provided by the second reset voltage terminal Vref2, and the second reset voltage provided by the third reset voltage terminal Vref3 are not limited to being the same, and are related to the value of the reset voltage actually required by the pixel circuit 11.

[0175] In addition, the first time periods during which the first reset voltage terminal Vref1 provides the first reset voltage, the second reset voltage terminal Vref2 provides the first reset voltage, and the third reset voltage terminal Vref3 provides the first reset voltage are not limited to being the same. The second time periods during which the first reset voltage terminal Vref1 provides the second reset voltage, the second reset voltage terminal Vref2 provides the second reset voltage, and the third reset voltage terminal Vref3 provides the second reset voltage are not limited to being the same, and are related to the driving stage of the pixel circuit 11 within an image frame.

[0176] Furthermore, in the embodiments of the present application, it is not limited that the pixel rows receiving the first reset voltage provided by the first reset voltage terminal Vref1, the pixel rows receiving the first reset voltage provided by the second reset voltage terminal Vref2, and the pixel rows receiving the first reset voltage provided by the third reset voltage terminal Vref3 are the same. The above is only an illustration. Similarly, in the embodiments of the present application, it is not limited that the pixel rows receiving the second reset voltage provided by the first reset voltage terminal Vref1, the pixel rows receiving the second reset voltage provided by the second reset voltage terminal Vref2, and the pixel rows receiving the second reset voltage provided by the third reset voltage terminal Vref3 are the same. The above is only an illustration.

[0177] Taking the third reset voltage terminal Vref3 as an example, as shown in FIG8 , the first reset voltage is used as the base voltage. Within an image frame, when the display screen 10 scans the bright band region (rows 1 to M) shown in FIG8 , the third reset voltage terminal Vref3 outputs the first reset voltage. When the display screen 10 scans the dark band region (rows M+1 to I) shown in FIG8 , the brightness difference between the pixel circuits 11 in the bright band region and the pixel circuits 11 in the dark band region determines whether to increase or decrease the reset voltage (determine the compensation voltage) based on the first reset voltage. At this point, the second reset voltage output by the third reset voltage terminal Vref3 is the adjusted reset voltage. For example, if the brightness of the pixel circuits 11 in the dark band region needs to be increased, the reset voltage needs to be increased based on the first reset voltage. If the brightness of the pixel circuits 11 in the dark band region needs to be decreased, the reset voltage needs to be decreased based on the first reset voltage. After the display screen 10 scans the dark band region and then re-scans into the bright band region (rows I+1 to L), the third reset voltage terminal Vref3 again outputs the first reset voltage. When the display screen 10 re-scans into the dark band area (entering the L+1th row to the Tth row), the third reset voltage terminal Vref3 re-outputs the second reset voltage. When the display screen 10 re-scans into the bright band area (entering the L+1th row to the Nth row), the third reset voltage terminal Vref3 re-outputs the first reset voltage.

[0178] The third reset voltage terminal Vref3 can perform compensation at the reset voltage jitter location, and exit compensation after the jitter ends. Each time the reset voltage jitters, the reset voltage output by the third reset voltage terminal Vref3 is compensated once. Of course, the compensation values ​​at different jitter locations can be different, and this embodiment of the present application is not limited to this. This embodiment of the present application is merely illustrative of an example in which the reset voltage jitters three times, with the same compensation value each time.

[0179] Alternatively, the second reset voltage is used as the base voltage. Within an image frame, when the display screen 10 scans and opens to the bright band region (rows 1 to M) shown in FIG8 , the brightness difference between the pixel circuits 11 in the bright band region and the pixel circuits 11 in the dark band region determines whether to increase or decrease the reset voltage (determine the compensation voltage) based on the second reset voltage. At this time, the first reset voltage output by the third reset voltage terminal Vref3 is the adjusted reset voltage. For example, if the brightness of the pixel circuits 11 in the bright band region needs to be increased, the reset voltage needs to be increased based on the second reset voltage. If the brightness of the pixel circuits 11 in the bright band region needs to be decreased, the reset voltage needs to be decreased based on the second reset voltage. When the display screen 10 scans and opens to the dark band region (rows M+1 to I) shown in FIG8 , the third reset voltage terminal Vref3 outputs the second reset voltage. When the display screen 10 re-scans and enters the bright band region (rows I+1 to L), the third reset voltage terminal Vref3 resumes outputting the first reset voltage. When the display screen 10 re-scans into the dark band area (entering the L+1th row to the Tth row), the third reset voltage terminal Vref3 re-outputs the second reset voltage. When the display screen 10 re-scans into the bright band area (entering the L+1th row to the Nth row), the third reset voltage terminal Vref3 re-outputs the first reset voltage.

[0180] As shown in FIG8 , by adjusting the reset voltage output by the third reset voltage terminal Vref3, the reset voltages actually received by the anodes of multiple rows of pixel circuits 11 are equal after the third reset voltage terminal Vref3 is subjected to load jitter, thereby improving the problem of uneven display brightness caused by reset voltage jitter.

[0181] Of course, the third application scenario and the fourth application scenario can be considered in a superimposed manner. Then, when transmitting the reset voltage, the first reset voltage terminal Vref1, the second reset voltage terminal Vref2, and the third reset voltage terminal Vref3 will comprehensively consider the situations in the third application scenario and the fourth application scenario.

[0182] The embodiment of the present application further provides a display driver 20 , which includes an image data receiving terminal, a processing circuit, and a plurality of reset voltage output terminals.

[0183] The image data receiving end is used to receive image data; the image data may be provided by a system on chip (SOC) of an electronic device, for example.

[0184] The processing circuit is configured to generate a first reset voltage and a second reset voltage based on the image data, wherein the value of the first reset voltage is different from the value of the second reset voltage. The values ​​of the first reset voltage and the second reset voltage can refer to the above description of the display screen 10 and the display driver 20.

[0185] The plurality of reset voltage output terminals include at least one reset voltage output terminal configured to output a first reset voltage during a first period within an image frame and to output a second reset voltage during a second period within the aforementioned image frame.

[0186] Of course, the processing circuit may output one set of the first reset voltage and the second reset voltage, or may output multiple sets of the first reset voltage and the second reset voltage, but the first reset voltage and the second reset voltage in the same set are output from the same reset voltage output terminal.

[0187] In some embodiments, the display driver 20 further includes a temperature receiving terminal configured to receive temperature data. A processing circuit is configured to combine the temperature data with the image data to generate a first reset voltage and a second reset voltage. The temperature data may be provided, for example, by a temperature sensor in the electronic device.

[0188] Since the temperature of the display screen 10 affects the device performance of the pixel circuit 11 in the display screen 10 , taking the temperature of the display screen 10 as a factor to adjust the reset voltage value can further improve the uniformity of the display brightness.

[0189] FIG9 is a schematic structural diagram of a display driver provided in an embodiment of the present application.

[0190] As shown in Figure 9, in some embodiments, the display screen 10 includes the above-mentioned first reset voltage terminal Vref1, and the display driver 20 includes a first reset voltage output terminal V1. The first reset voltage output terminal V1 is used to couple with the first reset voltage terminal Vref1 to output the above-mentioned first reset voltage and second reset voltage to the first reset voltage terminal Vref1.

[0191] In some embodiments, the display screen 10 includes the above-mentioned second reset voltage terminal Vref2, and the display driver 20 includes a second reset voltage output terminal V2, which is used to couple with the second reset voltage terminal Vref2 to output the above-mentioned first reset voltage and second reset voltage to the second reset voltage terminal Vref2.

[0192] In some embodiments, the display screen 10 includes the above-mentioned third reset voltage terminal Vref3, and the display driver 20 includes a third reset voltage output terminal V3, which is used to couple with the third reset voltage terminal Vref3 to output the above-mentioned first reset voltage and second reset voltage to the third reset voltage terminal Vref3.

[0193] In some embodiments, as shown in FIG. 9 , the display driver 20 includes a voltage calculation module 21 , a voltage timing control module 22 , and a voltage output module 23 .

[0194] The voltage calculation module 21 is used to receive image data and output a base voltage and a compensation voltage. Grayscale signals (R / G / B), display brightness value (DBV), and frame rate signals can be obtained from the image data. The voltage calculation module 21 uses these grayscale signals, display brightness value (DBV), and frame rate signals to calculate the base voltage and compensation voltage for the reset voltages of the first reset voltage terminal Vref1, the second reset voltage terminal Vref2, and the third reset voltage terminal Vref3. The voltage calculation module 21 can directly receive image data or receive image data through other modules and transmit the processed results to the voltage calculation module 21.

[0195] The voltage timing control module 22 is used to receive the base voltage, the compensation voltage, and the row signal, and output a first reset voltage or a second reset voltage, as well as a trigger signal. The row signal includes information such as the currently scanned row, which rows need to output the base voltage, and which rows need to output the adjusted voltage. Based on the row signal, the voltage timing control module 22 determines whether to output the base voltage or the sum of the base voltage and the compensation voltage. The base voltage and the sum of the base voltage and the compensation voltage, one of which serves as the first reset voltage, and the other as the second reset voltage. The voltage timing control module 22 outputs the first reset voltage or the second reset voltage, and simultaneously outputs a trigger signal.

[0196] The voltage output module 23 is configured to receive a trigger signal, a first reset voltage, and a second reset voltage, and output the first reset voltage or the second reset voltage. Upon receiving the trigger signal, the voltage output module 23 determines that the current reset voltage is a valid output voltage and outputs the received first reset voltage or the second reset voltage. It should be understood that the voltage output module 23 can receive and output the first reset voltage and the second reset voltage at different times, but can only receive and output the first reset voltage or the second reset voltage at the same time.

[0197] In the case where the display driver 20 includes a first reset voltage output terminal V1, a second reset voltage output terminal V2, and a third reset voltage output terminal V3, if the display driver 20 includes only one set of voltage calculation module 21, voltage timing control module 22, and voltage output module 23, the display driver 20 can sequentially output the reset voltage from the first reset voltage output terminal V1, the second reset voltage output terminal V2, and the third reset voltage output terminal V3. If the display driver 20 includes three sets of voltage calculation module 21, voltage timing control module 22, and voltage output module 23, then each set of the display driver 20 outputs the reset voltage to one reset voltage output terminal, and the display driver 20 can simultaneously output the reset voltage from the first reset voltage output terminal V1, the second reset voltage output terminal V2, and the third reset voltage output terminal V3.

[0198] FIG10 is a schematic structural diagram of a display driver provided in an embodiment of the present application.

[0199] In some embodiments, as shown in FIG10 , the voltage calculation module 21 is further configured to receive a frame rate signal.

[0200] For example, in the second application scenario, the reset voltage value is also related to the frame rate information of the high refresh rate area and the low refresh rate area. Then, the voltage calculation module 21 can receive the frame rate signal to calculate the basic voltage and the compensation voltage.

[0201] The display driver 20 provided in the embodiment of the present application can dynamically adjust the reset voltage according to the grayscale signal, display brightness signal, temperature signal and frame rate signal, so that the multiple rows of pixel circuits 11 of the display screen 10 receive a dynamically adjustable reset voltage, which can effectively improve the brightness difference problems such as horizontal bright bands and dark bands during the display process and improve the display consistency.

[0202] The embodiment of the present application further provides an electronic device, comprising any of the above display screens 10 and any of the above display drivers 20. A method for driving the electronic device includes:

[0203] During an image frame, N rows of pixels on display screen 10 are turned on row by row. Pixel turning on can be understood as the N rows of pixels sequentially executing the aforementioned initialization phase t1, data writing and compensation phase t2, light emission phase t3, and anode reset phase t3. The integrated gate circuits in display screen 10 output turn-on signals to pixel circuits 11 row by row.

[0204] The reset voltage output terminal of the display driver 20 outputs a first reset voltage to the display screen 10 during a first period of time, and a first portion of the N rows of pixels receive the first reset voltage for reset. The reset voltage output terminal outputs a second reset voltage to the display screen 10 during a second period of time, and a second portion of the N rows of pixels receive the second reset voltage for reset. The first and second reset voltages output by the display driver 20 can be found in the above description of the display driver 20 and the display screen 10, and will not be further elaborated here.

[0205] For example, in the first or second application scenario described above, the first row of pixels is turned on, and the reset voltage output terminal (eg, the first reset voltage output terminal V1 ) outputs the first reset voltage to the reset voltage terminal (eg, the first reset voltage terminal Vref1 ) of the display screen 10 .

[0206] When the pixels in the M+1th row are turned on, the reset voltage output terminal (eg, the first reset voltage output terminal V1 ) outputs the second reset voltage to the reset voltage terminal (eg, the first reset voltage terminal Vref1 ) of the display screen 10 .

[0207] When the pixels in the (I+1)th row are turned on, the reset voltage output terminal (eg, the first reset voltage output terminal V1 ) outputs the first reset voltage to the reset voltage terminal (eg, the first reset voltage terminal Vref1 ) of the display screen 10 .

[0208] Or, for example, in the third application scenario described above, the first row of pixels is turned on, and the reset voltage output terminal (eg, the first reset voltage output terminal V1 ) outputs the first reset voltage to the reset voltage terminal (eg, the first reset voltage terminal Vref1 ) of the display screen 10 .

[0209] When the pixels in the M+1th row are turned on, the reset voltage output terminal (eg, the first reset voltage output terminal V1 ) outputs the second reset voltage to the reset voltage terminal (eg, the first reset voltage terminal Vref1 ) of the display screen 10 .

[0210] When the pixels in the (I+1)th row are turned on, the reset voltage output terminal (eg, the first reset voltage output terminal V1 ) outputs the third reset voltage to the reset voltage terminal (eg, the first reset voltage terminal Vref1 ) of the display screen 10 .

[0211] When the pixels in the L+1th row are turned on, the reset voltage output terminal (eg, the first reset voltage output terminal V1 ) outputs the first reset voltage to the reset voltage terminal (eg, the first reset voltage terminal Vref1 ) of the display screen 10 .

[0212] Or, for example, in the fourth application scenario described above, the first row of pixels is turned on, and the reset voltage output terminal (for example, the third reset voltage output terminal V3) outputs the first reset voltage to the reset voltage terminal (for example, the third reset voltage terminal Vref3) of the display screen 10.

[0213] When the pixels in the M+1th row are turned on, the reset voltage output terminal (eg, the third reset voltage output terminal V3 ) outputs the second reset voltage to the reset voltage terminal (eg, the third reset voltage terminal Vref3 ) of the display screen 10 .

[0214] When the pixels in the (I+1)th row are turned on, the reset voltage output terminal (eg, the third reset voltage output terminal V3) outputs the second reset voltage to the reset voltage terminal (eg, the third reset voltage terminal Vref3) of the display screen 10.

[0215] When the pixels in the L+1th row are turned on, the reset voltage output terminal (eg, the third reset voltage output terminal V3 ) outputs the first reset voltage to the reset voltage terminal (eg, the third reset voltage terminal Vref3 ) of the display screen 10 .

[0216] The above is only a specific embodiment of the present application, but the scope of protection of this application is not limited to this. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A display screen, characterized in that: include: N rows of pixels, each row of pixels including a plurality of pixel circuits arranged at intervals; A plurality of reset voltage terminals; each of the reset voltage terminals is electrically connected to the N rows of pixels; Among them, at least one of the multiple reset voltage terminals is configured to provide a first reset voltage to the pixel circuit in a first time period within an image frame, and to provide a second reset voltage to the pixel circuit in a second time period within the image frame; the value of the first reset voltage is different from the value of the second reset voltage.

2. The display screen according to claim 1, characterized in that: A first portion of the rows of pixels in the N rows of pixels are used to receive the first reset voltage in the first time period, and a second portion of the rows of pixels in the N rows of pixels are used to receive the second reset voltage in the second time period.

3. The display screen according to claim 1 or 2, characterized in that: The plurality of reset voltage terminals include a first reset voltage terminal; the pixel circuit includes a driving transistor and a first reset circuit; Two ends of the first reset circuit are electrically connected to the control electrode of the driving transistor and the first reset voltage end respectively.

4. The display screen according to any one of claims 1 to 3, characterized in that: The plurality of reset voltage terminals include a second reset voltage terminal; the pixel circuit includes a driving transistor and a second reset circuit; Two ends of the second reset circuit are electrically connected to the first electrode of the driving transistor and the second reset voltage end respectively.

5. The display screen according to any one of claims 1 to 4, characterized in that: The plurality of reset voltage terminals include a third reset voltage terminal; the pixel circuit includes a light emitting device and a third reset circuit; Two ends of the third reset circuit are electrically connected to the anode of the light emitting device and the third reset voltage terminal respectively.

6. The display screen according to any one of claims 1 to 5, characterized in that: The reset voltage terminal is configured to provide the first reset voltage to the pixels in the 1st to Mth rows, provide the second reset voltage to the pixels in the M+1th to Ith rows, and provide the first reset voltage to the pixels in the I+1th to Nth rows; <I<N。 7. The display screen according to any one of claims 1 to 5, characterized in that: The reset voltage terminal is configured to provide the first reset voltage to the pixels in the 1st to Mth rows, provide the second reset voltage to the pixels in the M+1st to Ith rows, provide the first reset voltage to the pixels in the I+1st to Lth rows, provide the second reset voltage or the third reset voltage to the pixels in the L+1st to Tth rows, provide the first reset voltage to the pixels in the T+1st to Nth rows, and M <I<L<T<N。 8. The display screen according to claim 5, characterized in that: The first reset voltage outputted by the first reset voltage terminal, the first reset voltage outputted by the second reset voltage terminal, and the first reset voltage outputted by the third reset voltage terminal have different values.

9. A display driver, characterized in that: include: An image data receiving end, used for receiving image data; a processing circuit, configured to generate a first reset voltage and a second reset voltage according to the image data, wherein a value of the first reset voltage is different from a value of the second reset voltage; Multiple reset voltage output terminals; At least one of the reset voltage output terminals is used to output the first reset voltage in a first time period within an image frame, and to output the second reset voltage in a second time period within the image frame.

10. The display driver according to claim 9, characterized in that: Also includes: The temperature receiving end is used to receive temperature data; the processing circuit is also used to generate the first reset voltage and the second reset voltage according to the temperature data.

11. The display driver according to claim 9, characterized in that: The processing circuit comprises: A voltage calculation module, used for receiving the image data and outputting a basic voltage and a compensation voltage; A voltage timing control module, configured to receive the basic voltage, the compensation voltage and a row signal, and output the first reset voltage or the second reset voltage, and a trigger signal; A voltage output module is used to receive the trigger signal, the first reset voltage and the second reset voltage, and output the first reset voltage or the second reset voltage.

12. The display driver according to any one of claims 9 to 11, characterized in that: The plurality of reset voltage output terminals include a first reset voltage output terminal, a second reset voltage output terminal and a third reset voltage output terminal; The first reset voltage outputted by the first reset voltage output terminal, the first reset voltage outputted by the second reset voltage output terminal, and the first reset voltage outputted by the third reset voltage output terminal have different values.

13. An electronic device, characterized in that: It comprises a display screen and a display driver, wherein the display screen comprises the display screen according to any one of claims 1 to 8, and the display driver comprises the display driver according to any one of claims 9 to 12; and a reset voltage terminal of the display screen is electrically connected to a reset voltage output terminal of the display driver.

14. A method for driving an electronic device according to claim 13, characterized in that: include: In one image frame, The N rows of pixels on the display are turned on row by row; The reset voltage output terminal of the display driver outputs a first reset voltage to the display screen in a first time period, and a first part of the rows of pixels in the N rows of pixels receive the first reset voltage for reset; the reset voltage output terminal outputs a second reset voltage to the display screen in a second time period, and a second part of the rows of pixels in the N rows of pixels receive the second reset voltage for reset; the value of the first reset voltage is different from the value of the second reset voltage.

15. The driving method of the electronic device according to claim 14, characterized in that: The first row of pixels is turned on, and the reset voltage output terminal outputs the first reset voltage to the display screen; When the pixels in the M+1th row are turned on, the reset voltage output terminal outputs the second reset voltage to the display screen; When the pixels in the (I+1)th row are turned on, the reset voltage output terminal outputs the first reset voltage to the display screen.

16. The driving method of the electronic device according to claim 14, characterized in that: The first row of pixels is turned on, and the reset voltage output terminal outputs the first reset voltage to the display screen; When the pixels in the M+1th row are turned on, the reset voltage output terminal outputs the second reset voltage to the display screen; When the pixels in the (I+1)th row are turned on, the reset voltage output terminal outputs the second reset voltage or the third reset voltage to the display screen; When the pixels in the L+1th row are turned on, the reset voltage output terminal outputs the first reset voltage to the display screen.

Images