Display apparatus and electronic device

Abstract

The present invention improves an influence on the image quality due to pixel load fluctuation with a simple configuration, for example.　This display apparatus includes: ramp wiring to which a ramp signal having a voltage level that changes with time is supplied; a first switch provided between the ramp wiring and a signal line connected to each pixel; a second switch which operates in reverse with respect to the first switch; a correction current source which supplies a correction current to the ramp wiring according to an operation of the second switch; and a correction current control circuit which controls the current value of the correction current source on the basis of a current generated on the basis of a set voltage for determining the amplitude of the ramp signal.

Description

Display devices and electronic devices

[0001] The present technology relates to a display device and an electronic device.

[0002] Display devices that are driven using a ramp signal whose voltage level changes over time are known. Patent Document 1 listed below discloses a configuration in which a correction current source (compensation current source) is provided in parallel with a pixel load. The correction current source is provided between a buffer output that outputs a ramp signal (ramp voltage) and ground (GND), and a compensation switch is provided between the correction current source and the buffer output. A technology has been proposed in which the compensation switch operates in the opposite direction to a pixel switch that writes the ramp signal to a pixel, thereby suppressing fluctuations in the waveform of the ramp signal when the pixel load is disconnected.

[0003] Patent Document 2 discloses a technique for controlling a correction current (see FIG. 3). The figure discloses a configuration in which a transistor is provided between a ramp wiring (ramp signal line) and ground (Gnd) as a circuit for supplying a correction current, and a switch having a reverse connection relationship to a pixel switch (video switch) is provided between the transistor and ground. The figure also discloses a configuration including a dummy pixel and a diode-connected transistor between the ramp wiring and the data line of the dummy pixel. The proposed technique applies a signal voltage of the ramp signal to the dummy pixel via a diode-connected transistor during a ramp signal generation operation, and maintains and uses the gate-source voltage (VGS) of this transistor as a correction current, thereby accurately correcting waveform fluctuations when the pixel load is disconnected.

[0004] US Patent Application Publication No. 2019 / 0279562 JP 2011-053644 A

[0005] Patent Document 1 does not disclose any technology for controlling (setting) the correction current source. As mentioned above, Patent Document 2 discloses a technology for controlling the correction current to accurately correct waveform fluctuations when a pixel load is disconnected, but it requires a dummy pixel as a detection circuit for the correction current, which makes the configuration complicated.

[0006] One object of the present technology is to improve the influence of pixel load fluctuations on image quality with a simple configuration, for example.

[0007] The present technology relates to a display device having, for example, a ramp wiring to which a ramp signal whose voltage level changes over time is supplied, a first switch provided between the ramp wiring and a signal line connected to a pixel, a second switch that operates inversely to the first switch, a correction current source that supplies a correction current to the ramp wiring in accordance with the operation of the second switch, and a correction current control circuit that controls a current value of the correction current source based on a current generated based on a set voltage that determines the amplitude of the ramp signal.The present technology relates to, for example, an electronic device having the display device of the present technology.

[0008] FIG. 1 is a block diagram showing an example of the configuration of a display device according to a first embodiment. FIG. 2 is a diagram showing an example of the configuration of a horizontal driver according to the embodiment. FIG. 3 is a diagram explaining output of a ramp signal to a signal line. FIG. 4 is a timing chart showing the relationship between a ramp waveform and fluctuations in load current. FIG. 5 is a diagram explaining installation of a correction current source. FIG. 6 is a diagram explaining suppression of ramp waveform distortion when a correction current source is installed. FIG. 7 is a block diagram showing an example of the configuration of a ramp processing unit according to the embodiment. FIG. 8 is a diagram showing an example of the layout of a lamp drive circuit and a correction current supply circuit. FIG. 9 is a block diagram showing a specific example of the internal configuration of a ramp generation circuit. FIG. 10 is an operation timing diagram of the ramp generation circuit. FIG. 11 is a diagram showing a schematic configuration related to the correction current of a display device. FIG. 12 is a diagram showing an example of the configuration of a display device according to a second embodiment. FIG. 13 is a diagram showing an example of the configuration of a display device according to a third embodiment. FIG. 14 is a diagram showing an example of the configuration of a display device according to a fourth embodiment. FIG. 15 is a diagram showing an example of the configuration of a display device according to a fifth embodiment. FIG. 16 is a diagram showing an example of the configuration of a display device according to a sixth embodiment. FIG. 17 is a block diagram showing another example of the configuration of a ramp generation circuit. FIG. 18 is a block diagram showing another example of the configuration of a ramp generation circuit. FIG. 19 is a block diagram showing another example of the configuration of a ramp generation circuit. FIG. 20 is a block diagram showing another example of the configuration of a ramp generation circuit. FIG. 21 is a block diagram showing another example of the configuration of a ramp generation circuit. FIG. 22 is a block diagram showing another example of the configuration of a ramp generation circuit. FIG. 23 is a block diagram showing another example of the configuration of a ramp generation circuit. FIG. 24 is a block diagram showing another example of the configuration of a ramp generation circuit. FIG. 25 is a block diagram showing another example of the configuration of a ramp generation circuit. FIG. 26 is a block diagram showing another example of the configuration of a ramp generation circuit. FIG. 27 is a block diagram showing another example of the configuration of a ramp generation circuit. FIG. 28 is a block diagram showing an example of the configuration of a vertical driver. FIG. 29 is a block diagram showing an example of the configuration of a vertical driver. FIG. 30 is a diagram showing an example of the configuration of a pixel (pixel circuit). FIG. 31 is a diagram showing an example of the configuration of a pixel (pixel circuit). FIG. 32 is a diagram showing an example of the configuration of a pixel (pixel circuit). FIG. 33 is a diagram showing an example of the configuration of a pixel (pixel circuit).FIG. 34 is a diagram showing an example of the configuration of a pixel (pixel circuit). FIG. 35 is a diagram showing an example of the configuration of a pixel (pixel circuit). FIG. 36 is a diagram showing an example of the configuration of a pixel (pixel circuit). FIG. 37 is a diagram showing an example of the configuration of a pixel (pixel circuit). FIG. 38 is a perspective view showing an example of the appearance of a head-mounted display. FIG. 39 is a perspective view showing an example of the appearance of a see-through head-mounted display. FIG. 40A is a front view showing an example of the appearance of a digital still camera. FIG. 40B is a rear view showing an example of the appearance of a digital still camera. FIG. 41 is a perspective view showing an example of the appearance of a television device. FIG. 42 is a perspective view showing an example of the appearance of a smartphone. FIG. 43A is a diagram showing an example of the interior of a vehicle from the rear to the front of the vehicle. FIG. 43B is a diagram showing an example of the interior of a vehicle from diagonally rear to diagonally front of the vehicle.

[0009] Hereinafter, embodiments of the present technology will be described with reference to the drawings. The description will be made in the following order. In this specification and the drawings, components having substantially the same functions or configurations will be denoted by the same reference numerals, and duplicated description will be omitted as appropriate. Furthermore, for the sake of simplicity, reference numerals may be omitted in the drawings. <1. First embodiment> <2. Second embodiment> <3. Third embodiment> <4. Fourth embodiment> <5. Fifth embodiment> <6. Sixth embodiment> <7. Other configuration examples of ramp generation circuit> <8. Configuration example of vertical driver> <9. Configuration example of pixel> <10. Modified example> <11. Application example>

[0010] 1. First Embodiment [1-1. Overall Configuration] Fig. 1 is a block diagram showing an example configuration of a display device according to a first embodiment of the present technology. The display device 1 shown in Fig. 1 is a device that displays an image or the like using light-emitting elements. The light-emitting elements are, for example, LEDs (Light Emitting Diodes). LEDs include LEDs used in micro LED displays and OLEDs (Organic Light Emitting Diodes) used in organic EL (Electro-Luminescence) displays. Organic EL displays include, for example, OLED microdisplays (Organic Light-Emitting Diode Microdisplays). The following description will be given assuming that the display device 1 is an OLED microdisplay.

[0011] The display device 1 is, for example, a display mounted on an electronic device such as an electronic viewfinder (EVF) of a digital camera, AR glasses, or VR glasses. Note that the electronic devices to which the display device 1 can be applied are not limited to these. Specific configuration examples of electronic devices to which the display device 1 can be applied will be described later.

[0012] The display device 1 has a display panel including a semiconductor substrate such as a silicon substrate, etc. As shown in the figure, the display device 1 has an input / output unit (IO) 2, a gamma processing unit 3, a power supply processing unit 4, an interface unit (IF) 5, a timing controller (TCON) 6, a pixel unit 7, a vertical logic unit (VLOGIC) 8, a vertical analog unit (VANALOG) 9, a horizontal logic unit (HLOGIC) 10, and a horizontal analog unit (HANALOG) 11.

[0013] The input / output unit 2 inputs and outputs various data and is configured, for example, with an externally connectable FPC (Flexible Printed Circuit). The input / output unit 2 is connected to the gamma processing unit 3, the power supply processing unit 4, and the interface unit 5. The gamma processing unit 3 performs gamma correction processing. The gamma processing unit 3 is connected to the input / output unit 2 and the horizontal analog unit 11, and sets gamma correction based on a setting value for gamma correction input via the input / output unit 2, and gamma-corrects the pixel signal output from the horizontal analog unit 11 to the pixel unit 7.

[0014] The power supply processing unit 4 is a circuit that outputs power for driving the pixel unit 7 and is configured to include, for example, an LDO (Low Drop Out) regulator. The power supply processing unit 4 is connected to the input / output unit 2 and the pixel unit 7, and converts the supply power input via the input / output unit 2 into a power supply voltage for driving the pixel unit 7 and supplies it to the pixel unit 7. The interface unit 5 is connected to the input / output unit 2 and the timing controller 6. The interface unit 5 is an interface for inputting and outputting image data and the like to and from the outside via the input / output unit 2. For example, a high-speed interface standard such as MIPI (Mobile Industry Processor Interface) can be adopted as this interface.

[0015] The timing controller 6 controls the timing of each block operation. The timing controller 6 is connected to the interface unit 5, vertical logic unit 8, vertical analog unit 9, horizontal logic unit 10, and horizontal analog unit 11. The timing controller 6 outputs control signals to the vertical logic unit 8 and vertical analog unit 9 as needed based on a clock signal. The timing controller 6 also outputs image data input via the input / output unit 2 and interface unit 5 to the horizontal logic unit 10 based on the clock signal, and outputs control signals to the horizontal logic unit 10 and horizontal analog unit 11 as needed.

[0016] Although not shown here, the pixel unit 7 has a plurality of pixels (pixel circuits) arranged in a matrix of m rows and n columns (m and n are natural numbers). The pixel unit 7 is provided with pixels that represent the three primary colors of R (red), G (green), and B (blue), for example, to represent a color image. Note that the color representation of an image is not limited to this, and a configuration that represents a monochrome (black and white) image, for example, may also be used. The configuration and operation of the pixel will be described later.

[0017] The pixel section 7 also has control lines extending along the row direction of the pixel array and signal lines extending along the column direction of the pixel array. A control line is provided for each pixel row, and a signal line is provided for each pixel column. Each control line is connected to an output terminal of the corresponding row of the vertical analog section 9 and to a group of pixels in that row. Each signal line is connected to an output terminal of the corresponding column of the horizontal analog section 11 and to a group of pixels in that column.

[0018] The vertical logic unit 8 and the vertical analog unit 9 constitute a vertical driver. The vertical logic unit 8 generates a shift signal for each pixel row from a start pulse input from the timing controller 6. The vertical analog unit 9 generates a control signal for driving a control line from the shift signal and outputs it to the pixel unit 7. The horizontal logic unit 10 and the horizontal analog unit 11 constitute a horizontal driver. The horizontal logic unit 10 distributes image data input from the timing controller 6 to each signal line. The horizontal analog unit 11 converts the distributed image data into gamma-corrected pixel signals and outputs them to the corresponding signal lines of the pixel unit 7. The present technology is characterized particularly by the configuration of this horizontal driver.

[0019] [1-2. Configuration of Horizontal Driver] Fig. 2 is a diagram showing an example of the configuration of a horizontal driver according to this embodiment. The horizontal driver shown in Fig. 2 is configured with a RAMPDAC circuit that uses a ramp waveform analog signal to generate pixel signals to be output to signal lines. A horizontal logic unit 10 that constitutes this horizontal driver has a shift register unit (S / R) 12, a first latch unit 13, a second latch unit 14, a synchronous counter 15, a DLL (delay-locked loop) circuit 16, a comparator unit 17, and a PWM generation unit 18.

[0020] The shift register unit 12 sequentially shifts the pixel data DATA input from the timing controller 6 and outputs it as pixel data of a number corresponding to the number n of pixels in the row direction (for example, N-1=n). The 1st latch unit 13 is made up of the corresponding number of 1st latch circuits 13A described above, and latches each piece of pixel data input from the shift register unit 12 based on the latch clock LATCLK. The 2nd latch unit 14 is made up of the corresponding number of 2nd latch circuits 14A described above, and line-sequentially arranges each piece of latched data from the 1st latch circuits 13A in response to the line pulse LINECLK.

[0021] The synchronous counter 15 receives a main clock signal MCLK from the timing controller 6 via a DLL (delay-locked loop) circuit 16. The synchronous counter 15 counts down or up in synchronization with the main clock signal MCLK and outputs a signal representing the count result.

[0022] The comparator unit 17 is composed of a corresponding number of digital comparators 17A as described above. Each digital comparator 17A compares the latch data of each 2ND latch circuit 14A with the output from the synchronous counter 15 and outputs the comparison result. The PWM generation unit 18 is composed of a corresponding number of PWM generation circuits 18A as described above. Each PWM generation circuit 18A generates a PWM (pulse width) signal corresponding to the gradation data of each pixel in response to a start pulse RAMPST input from the timing controller 6. The generated PWM signal is output to the horizontal analog unit 11. As a result, an 8-bit, 10-bit, 12-bit, or other signal is converted into a signal having a width corresponding to the data and input to the horizontal analog unit 11.

[0023] The horizontal analog unit 11 constituting the horizontal driver shown in FIG. 2 includes a level shifter unit 19, a ramp processing unit 20, and a switch unit 21. The level shifter unit 19 is composed of the same number of level shifter circuits 19A as described above, and converts the levels of the PWM signals converted by each PWM generation circuit 18A into signals of drive levels (voltage levels). This signal is used to control the PWM switches 21A in the switch unit 21. The ramp processing unit 20 generates a ramp signal whose voltage level changes over time and outputs it to the switch unit 21 via a ramp wiring RL. In this way, the ramp signal generated by the ramp processing unit 20 is supplied to the ramp wiring RL. Although not described here, the ramp processing unit 20 also functions as a gamma correction circuit, for example, and outputs a ramp voltage that has been gamma-corrected based on a setting value input from the gamma processing unit 3.

[0024] The switch unit 21 is composed of the corresponding number of PWM switches (first switches) 21A described above. Each PWM switch 21A is provided between a signal line SIG connected to a pixel in the pixel unit 7 and a ramp line RL, and controls the connection between the ramp line RL and the corresponding signal line SIG. Specifically, each PWM switch 21A samples the ramp waveform by turning off (closing) at a timing corresponding to the gradation to be written to the pixel in accordance with the output voltage of each level shifter circuit 19A, and determines the signal voltage to be written to the pixel.

[0025] [1-3. Explanation of Pixel Load Fluctuation] FIG. 3 is a diagram illustrating the output of a ramp signal to the signal line SIG. FIG. 4 is a timing chart showing the relationship between the ramp waveform and fluctuations in the load current. As shown in FIG. 3, the ramp processing unit 20 of this embodiment generates and outputs a ramp signal whose voltage level decreases over time. Note that FIG. 3 illustrates an example in which the ramp processing unit 20 generates a ramp voltage corresponding to an 8-bit gradation (256 levels of VPCG-VG255) and outputs it as a ramp signal, but as mentioned above, the gradation level may be 10 bits, 12 bits, or the like. Also, while the signal line SIG1 will be described here as an example, the same applies to the other signal lines.

[0026] In FIG. 3, the capacitance on the signal line SIG1 side including the connected pixel (an example of the pixel configuration will be described later) is represented as pixel load capacitance Cpix, and the parasitic capacitance parasitic on the lamp line RL is represented as line load capacitance Cline.

[0027] Load fluctuations due to switching of the PWM switch 21A will be described with reference to Fig. 4. The load current Iload shown in Fig. 4 is calculated from the voltages (VPCG, VG255) that determine the drive amplitude of the ramp waveform and the calculated value of the ramp operation period tRAMP. Specifically, the load current Iload is calculated by the following equation (1): Iload = Cload × (VPCG - VG255) / tRAMP (1)

[0028] The pixel load capacitance Cload in equation (1) is calculated by equation (2) when the PWM signal that controls the on / off of the PWM switch 21A is high (switch on), and by equation (3) when the PWM signal is low (switch off): Cload=Cline+Cpix (2) Cload=Cline (3)

[0029] At the start of the ramp operation period tRAMP, the ramp voltage VRAMP of the ramp wiring RL of the ramp processing unit 20 is the precharge voltage VPCG, and in this state the PWM signal switches from low to high, turning on the PWM switch 21A. Then, at a timing corresponding to the gradation of the pixel data to be written, the PWM signal goes low, turning off the PWM switch 21A. As a result, a voltage representing the gradation corresponding to the pixel data is written to the pixel.

[0030] As shown in FIG. 4 , when the PWM switch 21A switches from on to off, the load current Iload fluctuates (decreases in the illustrated example). That is, when the PWM switch 21A is on, the capacitive load Cload is calculated using equation (2), resulting in a high current. On the other hand, when the PWM switch 21A is off, the capacitive load Cload is calculated using equation (3), resulting in a low current, resulting in a fluctuation in the load current Iload. This load current fluctuation then causes transient distortion in the ramp voltage VRAMP. For example, if this current fluctuation is detected and feedback is applied to control the gate voltage of a current control transistor, the resulting time lag can result in distortion, as shown in the figure. This distortion degrades the accuracy of the write voltage. For example, load fluctuations can affect image quality, such as horizontal crosstalk.

[0031] Therefore, in this embodiment, as shown in FIG. 5, a correction current source 28 is provided in the ramp processing unit 20, and the load current (specifically, the step difference shown in the figure) when the PWM switch 21A is off is compensated for by this correction current source 28. For example, the load current Iload during the ramp operation period tRAMP is corrected to maintain a constant state. Switching to the correction current source is controlled by an XPWM switch 27 (second switch) that operates inversely to the PWM switch 21A (having opposite on / off behavior). In other words, the XPWM switch 27 is controlled complementarily to the pixel load. The correction current Ic can be calculated by equation (4): Ic=Cpix×(VPCG-VG255) / tRAMP (4)

[0032] This makes it possible to suppress distortion in the output of the ramp voltage to the signal line SIG1, as shown in Fig. 6. A specific configuration of the ramp processing unit 20 according to this embodiment will now be described.

[0033] [1-4. Configuration of the Ramp Processing Unit] Fig. 7 is a block diagram showing an example configuration of the ramp processing unit 20 according to this embodiment. The ramp processing unit 20 has a correction current supply circuit 24, a ramp generation circuit 25, and a correction current control circuit 26. The correction current supply circuit 24 and the correction current control circuit 26 are provided according to the arrangement of the ramp generation circuit 25. First, this arrangement will be described. The ramp generation circuit 25 and the correction current control circuit 26 are collectively referred to as the lamp drive circuit 23.

[0034] FIG. 8 is a diagram showing an example of the arrangement of the lamp drive circuit 23 and the correction current supply circuit 24. The lamp drive circuit 23 drives each pixel PIX based on a reference voltage VREF and a precharge voltage VPCG. At this time, as shown in FIG. 8, for example, an offset voltage VOFS may be used to correct the threshold voltage (Vth) of a drive transistor (DR transistor) that drives a light-emitting element included in the pixel PIX. The reference voltage VREF, the precharge voltage VPCG, and the offset voltage VOFS are set voltages that determine the amplitude of the ramp signal and are used to generate the ramp signal in the ramp generation circuit 25 shown in FIG. 7. Note that these set voltages may be any voltages that determine the amplitude of the ramp signal and may include other voltages, for example.

[0035] As shown in FIG. 8 , in this embodiment, all pixels PIX are driven by one lamp drive circuit 23. All pixels refer to, for example, all pixels constituting the display area. It should be noted that all pixels outside the display area may also be included. The currents of the correction current sources 28 are uniformly controlled by the lamp drive circuit 23. Specifically, one ramp generation circuit 25 and one correction current control circuit 26 shown in FIG. 7 are provided for all pixels. One lamp drive circuit 23 also has one correction current supply circuit 24. One variable current source 35 in the ramp generation circuit 25 shown in FIG. 7 is used to collectively control the currents of the correction current sources 28 corresponding to all pixels.

[0036] (Correction Current Supply Circuit) As shown in FIG. 7 , the correction current supply circuit 24 includes XPWM switches (second switches) 27, the number of which corresponds to the number of pixel columns (e.g., n), and correction current sources 28, the number of which corresponds to the number of pixel columns (e.g., n). Each XPWM switch 27 and each correction current source 28 is arranged, for example, along the row direction of the pixels PIX. As described above, the XPWM switch 27 is a complementary switch to the PWM switch 21A. That is, the XPWM switch 27 is turned off when the PWM switch 21A in the corresponding column is turned on, and is turned on when the PWM switch 21A in the corresponding column is turned off. Note that the PWM switch 21A is turned on / off based on the PWM signal, and the XPWM switch 27 is turned on / off based on the XPWM signal. For example, the XPWM signal falls from high level to low level at the timing when the PWM signal rises from low level to high level. Furthermore, when the PWM signal falls from high to low, the XPWM signal rises from low to high. As a result, when the PWM switch 11A turns on, the XPWM switch 27 turns off, and when the PWM switch 11A turns off, the XPWM switch 27 turns on. The PWM switch 21A and the XPWM switch 27 are each composed of, for example, a transistor. The correction current source 28 is a current source that supplies a correction current to the lamp wiring RL.

[0037] Each XPWM switch 27 is provided between the power supply and a corresponding correction current source 28. Each correction current source 28 is provided between the corresponding XPWM switch 27 and the lamp wiring RL. Specifically, one end of the XPWM switch 27 is connected to the power supply voltage node, and the other end is connected to the corresponding correction current source 28. The correction current source 28 is connected to the other end of the XPWM switch 27 in the corresponding column, the lamp wiring RL, and the correction current control circuit 26. Connecting the XPWM switches 27 in this order keeps the voltage across the XPWM switch 27 unchanged through complementary operation with the PWM switch 21A and operation with the same amplitude and capacitance. This minimizes charge scattering (charge scattering to the node) when the XPWM switch 27 is disconnected (off), thereby improving write accuracy.

[0038] When the XPWM switch 27 of the corresponding column is on, that is, when the PWM switch 21A of the corresponding column is off, the correction current source 28 passes the correction current generated by the correction current control circuit 26 to the lamp wiring RL. The correction current source 28 is configured, for example, by a transistor diode-connected between the XPWM switch 27 and the lamp wiring RL, or by a circuit combining the transistor with a resistor.

[0039] (Ramp Generation Circuit) The ramp generation circuit 25 includes an output buffer 31, a current generation circuit 32, a current control circuit 33, and an SMPL switch 34.

[0040] The output buffer 31 generates and outputs a ramp voltage as a ramp signal. An output node (VOUT) of the output buffer 31 is connected to a ramp wiring RL, and one end of each PWM switch 21A constituting the switch unit 21 is connected to the ramp wiring RL. The other end of each PWM switch 21A is connected to the pixel PIX in the corresponding column via a corresponding signal line SIG.

[0041] The output buffer 31 includes an amplifier 41 , a load circuit 42 , a RAMPEN switch 43 , and a PRCG switch 44 .

[0042] The amplifier 41 compares the ramp voltage VRAMP with the precharge voltage VPCG and outputs a ramp voltage as a comparison result signal. The amplifier 41 includes a differential amplifier having a first input node to which the precharge voltage VPCG is supplied, a second input node to which a feedback voltage (ramp voltage) is supplied via a load circuit 42, and an output node to which a ramp voltage having a voltage level corresponding to the voltage difference between the precharge voltage VPCG and the feedback voltage (ramp voltage) is output. As described above, when correcting the threshold voltage of the drive transistor that drives the light-emitting element, this can be achieved by replacing the precharge voltage VPCG (VG0) with the offset voltage VOFS so that a correction ramp signal is generated. Specifically, this can be achieved by placing a switch (not shown) that switches between VG0 and VOFST in a stage preceding the first input node of the output buffer 31 and controlling the switching of this switch. This allows the offset voltage VOFST to be written first and the threshold voltage of the pixel circuit to be corrected.

[0043] The load circuit 42 is disposed on a feedback path of the amplifier 41. More specifically, the load circuit 42 is connected between the second input node and the output node. The load circuit 42 includes at least one of a resistor, a capacitor, and a diode.

[0044] The RAMPEN switch 43 is turned on / off based on the logic of the RAMPEN signal. The RAMPEN switch 43 is connected between the output node of the current generating circuit 32 and the second input node of the amplifier 41. When the RAMPEN switch 43 is turned on, the current output from the current generating circuit 32 flows to the load circuit 42, and the voltage level of the ramp voltage drops. When the RAMPEN switch 43 is turned off, no current flows from the current generating circuit 32 to the load circuit 42, and the voltage level of the ramp voltage is maintained.

[0045] The current generating circuit 32 includes a correction current variable current source 30 (described later) and a variable current source 35. The variable current source 35 is used to generate a ramp signal. The variable current source 35 generates a current based on set voltages (specifically, VPCG, VREF, and VOFS) that set the amplitude of the ramp signal. The variable current source 35 is a current source whose current value changes depending on the amplitude of the ramp signal, i.e., the drive amplitude. The variable current source 35 is configured, for example, by a transistor diode-connected between the power supply voltage node and the RAMPEN switch 43, or a circuit combining such a transistor and a resistor. One end of the variable current source 35 is connected to the power supply voltage node, and the other end is connected to one end of the RAMPEN switch 43 in the output buffer 31. The variable current source 35 controls the current flowing through the load circuit 42 based on the comparison result signal output from the current control circuit 33. When the RAMPEN switch 43 is turned on, the current from the variable current source 35 flows through the RAMPEN switch 43 to the load circuit 42, and the ramp voltage that is the output voltage of the output buffer 31 decreases over time.

[0046] The correction current variable current source 30 is, for example, the same current source as the variable current source 35. That is, the correction current variable current source 30 is a current source whose current value changes depending on the amplitude of the ramp signal, i.e., the drive amplitude, and generates a current based on a set voltage that sets the amplitude of the ramp signal. The correction current variable current source 30 is, for example, configured with a diode-connected transistor between a power supply voltage node and a current mirror unit 29 (described later) of the correction current control circuit 26, or a circuit combining such a transistor and a resistor. One end of the correction current variable current source 30 is connected to the power supply voltage node, and the other end is connected to the input node of the current mirror unit 29 of the correction current control circuit 26. The correction current variable current source 30 controls the current flowing to each correction current source 28 based on the comparison result signal output from the current control circuit 33. Note that the correction current variable current source 30 does not necessarily have to be the same current source as the variable current source 35, and may be a current source that uses the current of the variable current source 35.

[0047] The PRCG switch 44 is turned on / off based on the logic of a precharge (PRCG) signal. The PRCG switch 44 is connected in parallel to the load circuit 42. The PRCG switch 44 is turned on for a predetermined period immediately after one horizontal line period starts, and short-circuits both ends of the load circuit 42, i.e., the second node and the output node of the amplifier 41.

[0048] The current control circuit 33 controls the current generated by the current generation circuit 32 based on the voltage difference between the ramp voltage and the reference voltage VREF. The current control circuit 33 has a comparator 36 and a holding unit 37. The comparator 36 compares the reference voltage VREF with the output voltage (VOUT) of the output buffer 31 and outputs a comparison result signal. The holding unit 37 holds the comparison result signal output from the comparator 36. The holding unit 37 is configured with, for example, a memory, a voltage holding capacitor, etc. As a result, the current generation circuit 32 controls the current flowing through the load circuit 42 in accordance with the ramp voltage and the reference voltage VREF.

[0049] An SMPL switch 34 is connected between the output buffer 31 and the comparator 36. The SMPL switch 34 turns on / off based on the logic of the SMPL signal. The SMPL switch 34 is on for a predetermined period after the RAMPEN signal transitions from high to low within one horizontal line period. When the SMPL switch 34 is on, the ramp voltage output from the output buffer 31 is input to the comparator 36 via the SMPL switch 34. The comparator 36 compares the ramp voltage with the reference voltage VREF only while the SMPL switch 34 is on, and outputs a comparison result signal. While the SMPL switch 34 is off, the holding unit 37 continues to hold the comparison result signal output by the comparator 36 when the SMPL switch 34 was last turned on.

[0050] The current generating circuit 32 controls the current to be supplied to the load circuit 42 in the output buffer 31 based on the comparison result signal held by the holding unit 37. As described above, the current generated by the current generating circuit 32 is supplied to the load circuit 42 only while the RAMPEN switch 43 is on. Furthermore, the current generating circuit 32 controls the current to be supplied to each correction current source 28 in the correction current supply circuit 24 based on the comparison result signal held by the holding unit 37.

[0051] Fig. 9 is a block diagram showing a more specific internal configuration of the ramp generation circuit 25 of Fig. 7. The ramp generation circuit 25 of Fig. 9 shows a more specific internal configuration of the current control circuit 33 having the comparator 36 and the holding unit 37 of Fig. 7. The ramp generation circuit 25 of Fig. 9 shows an example in which the load circuit 42 in the output buffer 31 has a capacitor.

[0052] 9 includes a differential amplifier 36 a and a resistor element 36 b. The differential amplifier 36 a has a first input node to which the ramp voltage is input via the SMPL switch 34 and the resistor element 36 b, a second input node to which the reference voltage VREF is input, and an output node from which a comparison result signal is output.

[0053] 9, a capacitor 37a functioning as a holding unit 37 is connected between the first input node and the output node of the differential amplifier 36a. When the SMPL switch 34 is on, the differential amplifier 36a outputs a comparison result signal corresponding to the voltage difference between the ramp voltage and the reference voltage VREF from the output node. The holding unit 37 holds this comparison result signal in the capacitor 37a while the SMPL switch 34 is off.

[0054] 10 is an operation timing diagram of the ramp generating circuit 25 of FIG. 9. As shown in FIG. 10, one horizontal line period has periods T1 to T3. When one horizontal line period starts, as shown in period T1, the PRCG signal goes high and the PRCG switch 44 turns on. This resets the capacitance of the output buffer 31. In other words, the second input node and the output node of the amplifier 41 in the output buffer 31 are short-circuited, and the ramp voltage rises to the precharge voltage VPCG. This precharge voltage VPCG is, for example, a power supply voltage.

[0055] Thereafter, during period T2 (ramp operation period tRAMP), the RAMPEN signal goes high and turns on the RAMPEN switch 43. As a result, a current (specifically, a constant current) from the variable current source 35 is applied to the load circuit 42 via the RAMPEN switch 43, and the voltage level of the ramp voltage VOUT output from the amplifier 41 decreases over time. While the RAMPEN switch 43 is on, the voltage level of the ramp voltage changes over time.

[0056] After this current is applied, the RAMPEN signal transitions from high to low at the timing when the ramp operation period tRAMP ends and period T3 begins, turning off the RAMPEN switch 43, preventing the current from the variable current source 35 from being applied to the load circuit 42, and keeping the ramp voltage at a constant level.

[0057] The output voltage at the start of the ramp operation period tRAMP is VG0, and the output voltage at the end is VG255. In this case, the output waveform drops from VG0 (VPCG) to VG255 by integrating the current flowing through the capacitor 37a. This waveform voltage VG255 can be calculated using the following equations (5) and (6). VG255=VG0-1 / capacitance of capacitor 37a×∫Iin dt (5) =VG0-Iin×tRAMP / capacitance of capacitor 37a (6)

[0058] During this period T3, the SMPL signal temporarily transitions to a high level. As a result, the ramp voltage is supplied to a first input node of a differential amplifier 36a in the comparator 36 via the SMPL switch 34. The differential amplifier 36a outputs a comparison result signal corresponding to the voltage difference between the ramp voltage and the reference voltage VREF, and stores the comparison result signal in a capacitor 42a. The comparison result signal stored in the capacitor 42a during period T3 is used to determine the current flowing from the variable current source 35 during the next horizontal line period.

[0059] In this way, during the period T3, the ultimate potential of the output voltage VOUT is sampled by the current control circuit 33, which functions as a voltage comparison mechanism, and the current of the variable current source 35 of the current generating circuit 32 is controlled. For example, this control is performed by modulating the gate potential of the current control transistor of the variable current source 35 with the output signal of the current control circuit 33.

[0060] Based on this modulated current value, the same series of operations from periods T1 to T3 is repeated in the next horizontal line period. Ultimately, a ramp waveform is generated in which the voltage reached when current IIN from variable current source 35 is applied for ramp waveform period tFS is equal to reference voltage VREF. In other words, control stabilizes when the voltage reached after ramp operation period tRAMP coincides with reference voltage VREF.

[0061] As described above, in the first embodiment, the load circuit 42 is disposed on the feedback path of the amplifier 41 that outputs the ramp voltage, and the current flowing through the load circuit 42 is variably controlled based on the voltage difference between the ramp voltage and the reference voltage VREF. As a result, even if fluctuations in the coupling capacitance between adjacent signal lines occur, the current flowing through the load circuit 42 can be adjusted in accordance with the fluctuations in the ramp voltage due to the coupling capacitance, thereby suppressing variations in the ramp voltage. Therefore, according to this embodiment, variations in brightness within the display area can be suppressed, thereby improving display quality.

[0062] 7 is provided between the ramp generating circuit 25 and the correction current supplying circuit 24, and controls the current value of each correction current source 28 based on a current generated based on a set voltage that determines the amplitude of the ramp signal described above. Specifically, the current value of the correction current source 28 is determined based on the variable current source 35 of the ramp generating circuit 25. The correction current control circuit 26 specifically has the correction current variable current source 30 of the ramp generating circuit 25 described above, and a current mirror unit 29. The current mirror unit 29 copies (duplicates) the reference current generated by the correction current variable current source 30.

[0063] The current mirror unit 29 is configured with a current mirror circuit that receives a current from the current generating circuit 32 and controls the received current to be an integer multiple or an integer fraction to generate a desired voltage. The current mirror unit 29 copies the current of the correction current variable current source 30 using the current mirror circuit and supplies a current based on the copied current to the correction current source 28. The current mirror circuit has a configuration in which, for example, the gates of two transistors that are diode-connected to the correction current source 28 and the correction current variable current source 30, respectively, are connected to each other, and the collector and base of the transistor on the reference current input side (the correction current variable current source 30 side) are connected. Note that the configuration of the current mirror circuit is not limited to this and can be selected appropriately depending on the correction current to be supplied to the lamp wiring RL.

[0064] Next, with reference to FIG. 10 , the supply operation of the correction current from the correction current source 28 will be described. In FIG. 10 , when the PWM signal changes from high level to low level, the corresponding PWM switch 21A switches from on to off. At this time, as described with reference to FIG. 4 , it is conceivable that distortion will occur in the ramp voltage VRAMP due to fluctuations in the load current. However, by providing the X PWM switch 27 and the correction current source 28, it is possible to suppress fluctuations in the load current and prevent distortion of the ramp voltage VRAMP, as described with reference to FIG. 5 . Specifically, the X PWM signal rises in response to the falling edge of the PWM signal, and the corresponding X PWM switch 27 switches from off to on, causing a correction current to flow through the ramp wiring RL, thereby preventing this distortion. From the perspective of simplifying control, it is preferable that the falling and rising timings of the X PWM signal are the same as the rising and falling timings of the PWM signal, as shown in FIG. 10 . However, this is not limiting. For example, the rising timing of the XPWM signal may be shifted within a range in which distortion suppression is effective within the period in which the ramp waveform is operating (specifically, the ramp waveform period tFS). In other words, as long as distortion suppression is achieved, the period in which both the PWM switch 11A and the XPWM switch 27 are on or both are off may be included. Note that the current of the correction current source 28 is controlled so that the amplitude of the ramp signal becomes the set voltage, thereby improving correction accuracy. Because the current value of the correction current source 28 is determined based on the variable current source 35 for generating the ramp signal, distortion can be suppressed with a simple configuration.

[0065] As described above, in the display device 1 according to this embodiment, the ramp generating circuit 25 generates a ramp signal having a ramp waveform by passing a current through the load circuit 42 attached to the feedback path of the output buffer 31. The correction current control circuit 26 then copies a current based on this applied current. Each correction current source 28 then applies a correction current based on this copied current to the ramp wiring RL starting from the timing when the pixel load is closed, thereby suppressing load fluctuations as seen from the output buffer 31. In other words, waveform distortion upon load disconnection can be appropriately suppressed. In this way, by utilizing the configuration of the ramp generating circuit 25 already provided in the display device 1, pixel load fluctuations can be suppressed with a simple configuration. As a result, horizontal crosstalk caused by load fluctuations can be suppressed, improving image quality. Because this can be achieved with a simple configuration, the display device 1 can be made smaller, consume less power, and be more convenient. Even when the drive amplitude fluctuates, the correction current is appropriately adjusted to track the fluctuation, enabling correction at any ramp amplitude setting. Although the above-described example of the X PWM switch 27 operating in the opposite direction to the PWM switch 11A has been described, in which the X PWM switch 27 is turned off when the PWM switch 11A is on throughout the entire period and turned on when the PWM switch 11A is off, the operation example is not limited to this. For example, the X PWM switch 27 may operate in the opposite direction to the PWM switch 11A only during the period in which the ramp waveform is operating, during which the above-described distortion may occur. That is, in the above-described example, the timing at which the PWM signal rises from low to high outside the ramp waveform operation period and the timing at which the X PWM signal falls from high to low may or may not coincide. For example, the X PWM switch 27 may be turned off or on outside the ramp waveform operation period. Turning the X PWM switch 27 off outside the ramp waveform operation period can reduce unnecessary load current.

[0066] 11 , in the display device 1 of the first embodiment described above, each XPWM switch 27 is provided between the power supply and the corresponding correction current source 28, and each correction current source 28 is provided between the corresponding XPWM switch 27 and the lamp wiring RL. That is, the connection from the power supply voltage node to the lamp wiring RL in the correction current supply circuit 24 is in the order of power supply voltage node → XPWM switch 27 → correction current source 28 → lamp wiring RL. However, this order can be changed.

[0067] FIG. 12 shows an example configuration of a display device 1 according to the second embodiment. In the display device 1 shown in FIG. 12, the connection path to the lamp wiring RL in the correction current supply circuit 24 is formed by arranging the power supply → correction current source 28 → XPWM switch 27 in this order. That is, the correction current source 28 is provided between the power supply and the XPWM switch 27, and the XPWM switch 27 is provided between the correction current source 28 and the lamp wiring RL. This configuration can also achieve the same effects as the first embodiment described above. Furthermore, connecting in this order results in the same layout relationship as the PWM switch 21A connected to the pixel load side. Therefore, the XPWM switch 27 operates complementarily with the PWM switch 21A, thereby canceling signal feedthrough (for example, the phenomenon of charge inflow via capacitance between the gate and source or between the gate and drain due to fluctuations in the switch control signal when the switch is configured using a transistor).

[0068] 3. Third Embodiment The arrangement of the correction current source 28 described above is determined according to the lamp operation direction associated with the waveform of the ramp signal supplied to the lamp wiring RL. In the display device 1 of the first embodiment, the ramp signal has a ramp waveform in which the voltage level decreases over time, as shown in FIG. 11 . That is, the configuration has been described in which the correction current source 28 is provided on the power supply side so as to correspond to a ramp waveform that operates from a high voltage side to a low voltage side. However, the ramp signal is not limited to this.

[0069] Fig. 13 shows an example of the configuration of a display device 1 according to the third embodiment. In the display device 1 shown in Fig. 13, the waveform of the ramp signal generated by the ramp generating circuit 25 is different from that described in the first embodiment. The ramp generating circuit 25 of this display device 1 is configured to generate a ramp signal having a ramp waveform that increases over time, and outputs the generated ramp signal to the ramp wiring RL.

[0070] In this way, a ramp signal having a ramp waveform that operates from a low voltage side to a high voltage side can be handled by providing the correction current source 28 on the ground side. Specifically, in this display device 1, the connection path to the lamp wiring RL in the correction current supply circuit 24 is formed by arranging the ground → XPWM switch 27 → correction current source 28 in this order. That is, the XPWM switch 27 is provided between the ground (GND) and the correction current source 28. The correction current source 28 is also provided between the XPWM switch 27 and the lamp wiring RL. Specifically, one end of the XPWM switch 27 is connected to the ground node. With this configuration, the same effects as those of the first embodiment described above can be achieved.

[0071] 4. Fourth Embodiment FIG. 14 shows a configuration example of a display device 1 according to a fourth embodiment. Similar to the third embodiment, the ramp generating circuit 25 of the display device 1 shown in FIG. 14 is configured to generate a ramp signal having a ramp waveform that increases over time. Furthermore, in this display device 1, a connection path to the ramp wiring RL in the correction current supply circuit 24 is formed by arranging the ground, the correction current source 28, and the XPWM switch 27 in this order. That is, the XPWM switch 27 is provided between the correction current source 28 and the ramp wiring RL. The correction current source 28 is provided between the ground and the XPWM switch 27. Specifically, one end of the correction current source 28 is connected to the ground node. This configuration can also achieve the same effects as the first embodiment described above.

[0072] The signal waveform of the ramp signal supplied to the ramp wiring RL is not limited to those shown in FIGS. 11 to 14 . For example, it may be a triangular wave, a V-shaped wave, a sawtooth wave, or the like, and the slope of the waveform may not be linear but may be stepped. Furthermore, it is not limited to a waveform that changes regularly over time, but may also be a waveform that changes irregularly. Furthermore, it may have a waveform that combines these. In this way, various ramp signals that change over time can be employed for the display device 1. For example, in the case of a triangular wave, a configuration can be adopted in which the correction current source 28 and the XPWM switch 27 are arranged on both the power supply side and the ground side, and the corresponding one is switched depending on the output waveform.

[0073] 8, the display device 1 of the first embodiment described above is configured such that one lamp drive circuit 23 and one correction current supply circuit 24 are provided for all pixels PIX, but the arrangement of the lamp drive circuit 23 and the correction current supply circuit 24 is not limited to this. The same applies to the first to fourth embodiments described above.

[0074] 15 is a diagram showing an example of the configuration of a display device 1 according to a fifth embodiment. The display device 1 of this embodiment has a ramp generation circuit 25 for each pixel color, and uses a variable current source 35 corresponding to the color used in each ramp generation circuit 25 to control the current of each correction current source 28 in accordance with the color of the corresponding pixel PIX.

[0075] Specifically, this display device 1 is provided with a lamp drive circuit 23 and a correction current supply circuit 24 for each color of sub-pixels, which are divided into R (red) pixels PIX, G (green) pixels PIX, and B (blue) pixels PIX. The R lamp drive circuit 23 receives an R reference voltage VREF_R, an R pre-charge voltage VPCG_R, and an offset voltage VOFS to generate an R correction current, and outputs the generated correction current from the R correction current supply circuit 24 to an R lamp wiring RL, thereby driving the R pixel PIX. The G lamp drive circuit 23 receives a G reference voltage VREF_G, a G pre-charge voltage VPCG_G, and an offset voltage VOFS to generate a G correction current, and outputs the generated correction current from the G correction current supply circuit 24 to the G lamp wiring RL, thereby driving the G pixel PIX. The B lamp driving circuit 23 receives the B reference voltage VREF_B, the B precharge voltage VPCG_B, and the offset voltage VOFS as input to generate a B correction current, and outputs the generated correction current from the B correction current supply circuit 24 to the B lamp wiring RL to drive the B pixel PIX.

[0076] This allows for precise waveform correction for each color. For example, even if the waveform amplitude of the ramp signal is arbitrarily changed for each color (for example, the G system is controlled by a ramp waveform with a large amplitude, and the R and B systems are controlled by ramp waveforms with small amplitudes), each can be tracked and controlled with an appropriate correction current value. Note that the colors of the subpixels are not limited to the three colors of R, G, and B, and may also include, for example, W (white).

[0077] 16 is a diagram showing an example of the configuration of a display device 1 according to a sixth embodiment. The display device 1 of this embodiment has a ramp generation circuit 25 for each block made up of a predetermined number of pixels, and controls the current of each correction current source 28 on a block-by-block basis using a variable current source 35 used in each ramp generation circuit 25.

[0078] Specifically, the display device 1 has the lamp drive circuits 23 and the correction current supply circuits 24 arranged every predetermined number of pixel columns (for example, every several tens of pixel columns or every several hundreds of pixel columns). For example, when arranged every 10 pixel columns, one block includes 10×m pixels PIX.

[0079] This allows for precise waveform correction for each block. For example, by driving each block in this manner, the reference bias is determined for each circuit in each block, thereby mitigating the influence of IR drop from the power supply (or the ground if the correction current source 28 is connected to the ground side). Note that the predetermined number may be arranged in a regular or irregular pattern, with multiple types of blocks. Furthermore, the blocks may be arranged not only along the row direction as shown in FIG. 16 , but also along the column direction, or may be distributed. In this way, the arrangement of the lamp drive circuit 23 and the correction current supply circuit 24 is not limited to that shown in FIG. 8 , and may be appropriately arranged with respect to the arrangement of the pixels PIX.

[0080] 7. Configuration Examples of Applicable Ramp Generation Circuits (Another Configuration Example 1) FIG. 17 is a block diagram showing another configuration example of the ramp generation circuit 25. The ramp generation circuit 25 of FIG. 17 generates a ramp voltage whose voltage level increases over time. This ramp generation circuit 25 differs from the ramp generation circuit 25 shown in FIG. 9 in the configuration of the current generation circuit 32. In this ramp generation circuit 25, one end of the variable current source 35 is connected to the ground node, and the other end is connected to one end of the RAMPEN switch 43 of the output buffer 31. The other configuration is the same as that of FIG. 9.

[0081] For example, the ramp generation circuit 25 operates as follows: When one horizontal line period starts, the PRCG switch 44 turns on and the ramp voltage drops to the precharge voltage VPCG (e.g., ground voltage). Next, the PRCG switch 44 turns off and the RAMPEN switch 43 turns on, causing a current to flow from the load circuit 42 to the variable current source 35 via the RAMPEN switch 43, causing the ramp voltage, which is the output voltage of the output buffer 31, to rise over time.

[0082] Subsequently, after the RAMPEN switch 43 is turned off and the voltage level of the ramp voltage becomes constant, the SMPL switch 34 is turned on, and the ramp voltage is supplied to the first input node of the differential amplifier 36a via the SMPL switch 34. The differential amplifier 36a outputs a comparison result signal corresponding to the voltage difference between the ramp voltage and the reference voltage VREF, and stores the comparison result signal in the capacitor 37a. This stored comparison result signal is used to determine the current flowing from the variable current source 35 during the next horizontal line period. This series of operations is repeated in the same manner during the next horizontal line period.

[0083] In this configuration example, the correction current variable current source 30 may have one end connected to the ground node, similar to the variable current source 35, for example.

[0084] (Another Configuration Example 2) Fig. 18 is a block diagram showing another configuration example of the ramp generation circuit 25. The ramp generation circuit 25 shown in Fig. 18 generates a ramp voltage with a triangular waveform. This ramp generation circuit 25 differs from the ramp generation circuit 25 shown in Fig. 9 in the configurations of the output buffer 31 and the current generation circuit 32. The output buffer 31 in Fig. 18 has, instead of the RAMPEN switch 43 in Fig. 9, a first RAMPEN switch 43a that is turned on / off in response to a RAMPEN1 signal and a second RAMPEN switch 43b that is turned on / off in response to a RAMPEN2 signal.

[0085] 18 includes a first variable current source 35a and a second variable current source 35b as variable current sources 35, and a bias circuit 38. One end of the first variable current source 35a is connected to a power supply voltage node, and the other end is connected to one end of a first RAMPEN switch 43a. One end of the second variable current source 35b is connected to a ground node, and the other end is connected to one end of a second RAMPEN switch 43b. The other ends of the first RAMPEN switch 43a and the second RAMPEN switch 43b are connected to a load circuit 42 and a second input node of an amplifier 41. The bias circuit 38 controls the currents flowing through the first variable current source 35a and the second variable current source 35b based on the comparison result signal held in a holding unit 37.

[0086] The ramp generation circuit 25 operates, for example, as follows. At the start of one horizontal line, both the first RAMPEN switch 43a and the second RAMPEN switch 43b are off. In this state, the PRCG switch 44 is turned on, and the ramp voltage rises to the precharge voltage. Next, the first RAMPEN switch 43a is turned on, and current flows from the first variable current source 35a to the load circuit 42 via the first RAMPEN switch 43a, causing the ramp voltage, which is the output voltage of the output buffer 31, to decrease over time. After that, after a period of tFS / 2 has elapsed, the SMPL switch 34 is temporarily turned on, and the comparator 36 outputs a comparison result signal between the ramp voltage at that time and the reference voltage VREF, and the holding unit 37 holds this comparison result signal.

[0087] Next, the first RAMPEN switch 43a is turned off and the second RAMPEN switch 43b is turned on. As a result, current flows from the load circuit 42 to the second variable current source 35b via the second RAMPEN switch 43b, and the ramp voltage that is the output voltage of the output buffer 31 increases over time. Thereafter, both the first RAMPEN switch 43a and the second RAMPEN switch 43b are turned off, and the ramp voltage that is the output voltage of the output buffer 31 maintains the precharge voltage VPCG.

[0088] 18, even when generating a triangular ramp voltage whose voltage level changes direction during one horizontal line period, current control is possible according to the voltage level of the ramp voltage. Note that a sawtooth ramp voltage can also be generated by processing with timing that shifts the peak of the triangular wave.

[0089] In this configuration example, for example, the variable current source 30 for correction current may be provided with a current source corresponding to the first variable current source 35 a, a current source corresponding to the second variable current source 35 b, and a selector switch, and the selector switch may be used to select the current source corresponding to the one controlling the current flowing to the load circuit 42.

[0090] 19 is a block diagram showing another example of the configuration of the ramp generation circuit 25. The ramp generation circuit 25 shown in FIG. 19 is different from the ramp generation circuit 25 shown in FIG. 9 in the configuration of the current control circuit 33, but the other configurations are similar. The current control circuit 33 in FIG. 19 has a digital comparator 51, an SR latch 52, a phase comparator 53, a first current source 54 a, a second current source 54 b, and a holding unit 37.

[0091] The digital comparator 51 compares the ramp voltage, which is the output voltage of the output buffer 31, with a reference voltage VREF, and outputs a binary signal that is a comparison result signal. For example, when the ramp voltage falls below the reference voltage VREF, the digital comparator 51 outputs a high-level comparison result signal. When the START signal goes high, the SR latch 52 goes into a set state and outputs a high-level signal, and when the comparison result signal of the digital comparator 51 goes high, the SR latch 52 goes into a reset state and outputs a low-level signal. Hereinafter, the output signal of the SR latch 52 will be referred to as a comparison pulse signal.

[0092] The phase comparator 53 outputs an UP signal or a DOWN signal according to the phase difference between the comparison pulse signal and the reference pulse signal output from the SR latch 52. The first current source 54a supplies current while the UP signal is at a high level to charge a capacitor constituting the holding unit 37. The second current source 54b discharges this capacitor while the DOWN signal is at a high level to supply a discharge current to the ground node.

[0093] The ramp generating circuit 25 operates, for example, as follows. If the comparison pulse signal output from the SR latch 52 falls later than the reference pulse signal, the ramp voltage is too high, and the phase comparator 53 sets the DOWN signal to high level. Therefore, the variable current source 35 controls the load circuit 42 to allow more current to flow, further reducing the voltage level of the ramp voltage. If the comparison pulse signal falls earlier than the reference pulse signal, the ramp voltage is too low, and the phase comparator 53 sets the UP signal to high level. Therefore, the variable current source 35 controls the load circuit 42 to allow less current to flow, further increasing the voltage level of the ramp voltage. If the comparison pulse signal and the reference pulse signal are in phase, the phase comparator 53 sets both the UP signal and the DOWN signal to low level. Therefore, the variable current source 35 passes a current to the load circuit 42 according to the comparison result signal held in the holding unit 37.

[0094] In this way, in the ramp generating circuit 25 of FIG. 19, the current control circuit 33 that controls the current of the variable current source 35 can be configured using the phase comparator 53, which makes integration easier and enables a smaller area and lower power consumption to be achieved.

[0095] (Another Configuration Example 4) Fig. 20 is a block diagram showing another configuration example of the ramp generation circuit 25. The ramp generation circuit 25 shown in Fig. 20 differs from the ramp generation circuit 25 shown in Fig. 9 in the configurations of the current generation circuit 32 and the current control circuit 33, but the other configurations are similar. The current generation circuit 32 in Fig. 20 has a variable current source 35 and a DA converter (hereinafter referred to as DAC) 55. The variable current source 35 generates a current according to a current control signal output from the DAC 55.

[0096] The current control circuit 33 of FIG. 20 includes a digital comparator 51, an SR latch 52, a pulse counter 56, a holding unit 37, and an arithmetic circuit 57. The digital comparator 51 and the SR latch 52 are similar to those of the current control circuit 33 of FIG. 19, and the SR latch 52 outputs a comparison pulse signal. The pulse counter 56 counts the pulse width of the comparison pulse signal output from the SR latch 52 using a clock signal CLK and outputs the count value. The holding unit 37 holds the count value output from the pulse counter 56. The holding unit 37 holds the count value using, for example, a flip-flop. Alternatively, the holding unit 37 may hold the count value using multiple logic gates. The arithmetic circuit 57 generates a digital current control signal for controlling the current of the variable current source 35 based on the count value. The DAC 55 of the current generation circuit 32 generates a current control signal by digital-to-analog converting the digital current control signal.

[0097] In this configuration example, the correction current variable current source 30 may generate a current according to the current control signal output from the DAC 55, similar to the variable current source 35. The same applies to the following configuration examples 5 and 11.

[0098] (Another Configuration Example 5) Fig. 21 is a block diagram showing another configuration example of the ramp generation circuit 25. The ramp generation circuit 25 shown in Fig. 21 differs from the ramp generation circuit 25 shown in Fig. 20 in the configuration of the current control circuit 33, but the other configurations are similar. The current control circuit 33 in Fig. 20 has a comparator 36 and a successive approximation register analog-to-digital converter (hereinafter referred to as SAR ADC) 58.

[0099] The comparator 36 outputs a comparison result signal corresponding to the potential difference between the ramp voltage, which is the output voltage of the output buffer 31, and the reference voltage VREF. The SAR ADC 58 performs successive approximation processing on the comparison result signal output from the comparator 36, and outputs a digital signal corresponding to the comparison result signal. The DAC 55 in the current generation circuit 32 converts the digital signal output from the SAR ADC 58 into an analog current control signal. The variable current source 35 controls the current flowing through the load circuit 42 based on the current control signal. The SAR ADC 58 performs AD conversion processing when the SMPL switch 34 is on, and holds the digital signal immediately before the SMPL switch 34 transitions from on to off.

[0100] (Another Configuration Example 6) Fig. 22 is a block diagram showing another configuration example of the ramp generation circuit 25. In the configuration example of the ramp generation circuit 25 described above, the variable current source 35 is used in the current generation circuit 32, but it is not necessary to use the variable current source 35. The ramp generation circuit 25 shown in Fig. 22 has an output buffer 31 having the same configuration as in Fig. 9 (however, the RAMPEN switch 43 is not required), a comparator 36, and a holding unit 37. A voltage follower circuit 59 is connected to the output of the comparator 36.

[0101] 22 has a charge pump 61 provided in place of the variable current source 35, and a DAC control counter 62. The charge pump 61 has a capacitor 63 and a switch SW1 connected in series between the output node of the voltage follower circuit 59 and the second input node of the amplifier 41 in the output buffer 31, and a switch SW2 connected between the connection node of the capacitor 63 and the switch SW1 and the precharge voltage VPCG node.

[0102] The DAC control counter 62 performs counting at predetermined time intervals. The predetermined time intervals are the time intervals at which the ramp voltage is updated. The comparator 36 in the current control circuit 33 compares the ramp voltage with the reference voltage VREF for each horizontal line period and inputs a voltage signal corresponding to the comparison result signal to the charge pump 61.

[0103] The switches SW1 and SW2 in the charge pump 61 are temporarily turned on each time the DAC control counter 62 counts up. The cycle in which the DAC control counter 62 counts up is much shorter than one horizontal line period. The charge pump 61 can gradually switch the current flowing to the load circuit 42 by repeatedly turning on the switches SW1 and SW2 temporarily. This causes the voltage level of the ramp voltage to decrease gradually (in a step-like manner). In this configuration example, the charge pump 61 can be used as the correction current variable current source 30, for example. Specifically, the above-mentioned variable current source 35 can be configured with the charge pump 61, and a current source based on the current of the charge pump 61 can be used as the correction current variable current source 30.

[0104] (Another Configuration Example 7) Fig. 23 is a block diagram showing another configuration example of the ramp generation circuit 25. The ramp generation circuit 25 of Fig. 23 differs from the ramp generation circuit 25 shown in Fig. 9 in the configuration of the load circuit 42 of the output buffer 31. The other configurations are similar. As shown in Fig. 23, the load circuit 42 of this output buffer 31 has a resistor element 42b and a capacitor 42a connected in series between the second input node and the output node of the amplifier 41.

[0105] If the load circuit 42 were composed only of a capacitor as in Fig. 9, the waveform of the ramp voltage would likely change nonlinearly when the voltage level of the ramp voltage begins to drop. In contrast, the load circuit 42 in Fig. 23 includes a resistor element 42b connected in series with the capacitor 42a, and therefore can change the voltage level substantially linearly when the ramp voltage begins to drop. This reduces errors in the signal line voltage when the signal line voltage is determined using the ramp voltage.

[0106] (Another Configuration Example 8) FIG. 24 is a block diagram showing another configuration example of the ramp generation circuit 25. The ramp generation circuit 25 of FIG. 24 has a current generation circuit 32 and a current control circuit 33 configured similarly to those of FIG. 9. The output buffer 31 of FIG. 24 differs from that shown in FIG. 23 in the circuit configuration of the load circuit 42. The load circuit 42 of FIG. 24 is composed of a variable resistor 42c. The resistance value of the variable resistor is controlled in stages by the DAC control counter 62. More specifically, the resistance value of the variable resistor increases in stages as the count value of the DAC control counter 62 increases. As a result, the ramp voltage decreases in stages (in a stepwise manner) from the precharge voltage.

[0107] (Another Configuration Example 9) Fig. 25 is a block diagram showing another configuration example of the ramp generation circuit 25. The ramp generation circuit 25 of Fig. 25 has an output buffer 31 and a current control circuit 33 configured similarly to those of Fig. 9. The current generation circuit 32 of Fig. 25 has a current DAC 66 including x (x is an integer of 2 or greater) current sources 64 that each supply a different current, and x switches 65. Corresponding current sources 64 and switches 65 are connected in series. Each current source 64 and each switch 65 corresponds to a bit of the x-bit count value output from the DAC control counter 62. The most significant bit of the count value corresponds to the leftmost current source 64 and switch 65, and the least significant bit of the count value corresponds to the rightmost current source 64 and switch 65.

[0108] The x current sources 64 variably control the current IIN in response to the comparison result signal output from the comparator 36 in the current control circuit 33. The leftmost current source 64 is ｘ ×IIN, and the adjacent current source 64 flows a current of 2 ｘ－１ The current source 64 that is second from the right end passes a current of 2×IIN, and the current source 64 at the right end passes a current of IIN. The currents that flow through the x current sources 64 and the x switches 65 are summed and supplied to the load circuit 42.

[0109] When the voltage difference between the ramp voltage and the reference voltage VREF is small, a small current flows from the x current sources 64 to the load circuit 42. Furthermore, since the count value of the DAC 55 counter becomes larger toward the latter half of one horizontal line period, a larger current flows from the x current sources 64, and the ramp voltage becomes lower in stages.

[0110] In the case of this configuration example, for example, this current DAC 66 can be used as the correction current variable current source 30. Specifically, the above-mentioned variable current source 35 can be configured with this current DAC 66, and a current source based on the current of this current DAC 66 can be used as the correction current variable current source 30. The same applies to the next configuration example 10.

[0111] (Another Configuration Example 10) FIG. 26 is a block diagram showing another configuration example of the ramp generation circuit 25. The ramp generation circuit 25 of FIG. 26 has a current generation circuit 32 and a current control circuit 33 configured similarly to those of FIG. 25. The load circuit 42 of the output buffer 31 of FIG. 26 has a diode instead of a resistor element. Since the relationship between the forward voltage and the forward current of a diode is nonlinear, the ramp voltage has a nonlinear waveform. Note that the load circuit 42 may also be configured with a diode connected in series to a resistor element. This allows the nonlinear waveform of the ramp voltage to approach a linear waveform.

[0112] (Another Configuration Example 11) FIG. 27 is a block diagram showing another configuration example of the ramp generation circuit 25. The ramp generation circuit 25 of FIG. 27 includes an output buffer 31 and a current generation circuit 32 configured similarly to those of FIG. 21. The ramp generation circuit 25 of FIG. 27 includes a setting and holding register 69 instead of the current control circuit 33. In this configuration example, before shipping a display device 1 including the ramp generation circuit 25, the ramp voltage, which is the output voltage of the output buffer 31, is monitored to detect in advance the current to be passed through the load circuit 42 and the control value of the variable current source 35 for passing that current. The control value is then stored in the setting and holding register 69 before shipping the display device 1. During operation, the current generation circuit 32 passes a current from the variable current source 35 to the load circuit 42 based on a control signal obtained by digital-to-analog converting the control value stored in the setting and holding register 69 using a DAC 55, thereby adjusting the voltage level of the ramp voltage.

[0113] 28 is a block diagram showing a configuration example (first configuration example) of a vertical driver. The vertical driver can be configured, for example, by a shift register type circuit having a shift register circuit in a signal input section. The vertical logic section 8 constituting this vertical driver has a shift register section 81 and a logic circuit section 82. The vertical analog section 9 also has a level shifter section 91 and an output buffer section 92.

[0114] The shift register unit 81 is composed of shift registers 81A, the number of which corresponds to the number m of pixels in the column direction (for example, m), and a start pulse VST is synchronized with a clock signal CLK, propagated in sequence, and output as shift signals SR0, SR1, ... in sequence for each row.

[0115] The logic circuit section 82 is composed of the corresponding number of logic circuits (LOGIC) 82A described above, and performs logical operations as needed in response to input control signals (not shown). The level shifter section 91 is composed of the corresponding number of level shifters 91A described above, and converts the levels of the signals SR0, SR1, ... that have undergone logical operations into drive level signals (control signals). The output buffer section 92 is composed of the corresponding number of buffer circuits 92A described above, and buffers and outputs the control signals.

[0116] 29 is a block diagram showing a configuration example (second configuration example) of a vertical driver. This vertical driver has an address decoder 83 instead of the shift register unit 81 of the vertical driver shown in FIG. 28. In this way, the vertical driver can be configured, for example, by an address decoder type circuit having the address decoder 83 in the signal input unit. Other configurations are the same as those of the vertical driver in FIG. 28.

[0117] The address decoder 83 decodes the address based on the address information COUNT supplied from the timing controller 6, and outputs the decoded result in correspondence with the logic circuit 82A of each row. The shift register section 81 described above is configured to always shift in a predetermined order, such as from top to bottom or from bottom to top, but the address decoder 83 can sequentially specify and scan between predetermined addresses, such as incrementing from an arbitrary address to a certain address.

[0118] The configuration of the vertical driver is not limited to that shown in FIGS. 28 and 29, but can be changed as appropriate in accordance with the pixel configuration, operation, etc.

[0119] 9. Pixel Circuit Configuration Examples (First Configuration Example) FIG. 30 shows one configuration example of a pixel PIX. The pixel PIX has a capacitor C01, transistors MN02 and MN03, and a light-emitting element EL. The transistors MN02 and MN03 are N-type metal oxide semiconductor field effect transistors (MOSFETs). The gate of transistor MN02 is connected to a control line WSL, the drain is connected to a signal line SGL, and the source is connected to the gate of transistor MN03 and capacitor C01. One end of capacitor C01 is connected to the source of transistor MN02 and the gate of transistor MN03, and the other end is connected to the source of transistor MN03 and the anode of the light-emitting element EL. The gate of transistor MN03 is connected to the source of transistor MN02 and one end of capacitor C01, the drain is connected to the power supply line VCCP, and the source is connected to the other end of capacitor C01 and the anode of the light-emitting element EL. The anode of the light-emitting element EL is connected to the source of the transistor MN03 and the other end of the capacitor C01, and the cathode is connected to the power supply line Vcath. The voltage of the power supply line VCCP is appropriately switched between a first voltage and a second voltage lower than the first voltage.

[0120] With this configuration, in pixel PIX, when transistor MN02 is turned on, the voltage across capacitor C01 is set based on the pixel signal supplied from signal line SGL. During a period when the voltage of power supply line VCCP is at a first voltage, transistor MN03 passes a current corresponding to the voltage across capacitor C01 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN03. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. During a period when the voltage of power supply line VCCP is at a second voltage, light-emitting element EL is turned off.

[0121] (Second Configuration Example) Figure 31 shows one configuration example of pixel PIX. This pixel PIX has capacitors C11 and C12, transistors MP12 to MP15, and a light-emitting element EL. Transistors MP12 to MP15 are P-type MOSFETs. The gate of transistor MP12 is connected to a control line WSL, the source is connected to a signal line SGL, and the drain is connected to the gate of transistor MP14 and capacitor C12. One end of capacitor C11 is connected to a power supply line VCCP, and the other end is connected to capacitor C12, the drain of transistor MP13, and the source of transistor MP14. One end of capacitor C12 is connected to the other end of capacitor C11, the drain of transistor MP13, and the source of transistor MP14, and the other end is connected to the drain of transistor MP12 and the gate of transistor MP14. The gate of transistor MP13 is connected to the control line DSL, the source is connected to the power supply line VCCP, and the drain is connected to the source of transistor MP14, the other end of capacitor C11, and one end of capacitor C12. The gate of transistor MP14 is connected to the drain of transistor MP12 and the other end of capacitor C12, the source is connected to the drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12, and the drain is connected to the anode of the light-emitting element EL and the source of transistor MP15. The gate of transistor MP15 is connected to the control line AZSL, the source is connected to the drain of transistor MP14 and the anode of the light-emitting element EL, and the drain is connected to the power supply line VSS.

[0122] With this configuration, in pixel PIX, when transistor MP12 is turned on, the voltage across capacitor C12 is set based on the pixel signal supplied from signal line SGL. Transistor MP13 is turned on and off based on the signal on control line DSL. While transistor MP13 is on, transistor MP14 passes a current corresponding to the voltage across capacitor C12 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP14. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP15 is turned on and off based on the signal on control line AZSL. While transistor MP15 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0123] The transistors MP12 to MP15 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP12 and MP15 may be a transistor using an oxide semiconductor.

[0124] (Third Configuration Example) Figure 32 shows one configuration example of pixel PIX. This pixel PIX has a capacitor C21, transistors MN22 to MN25, and a light-emitting element EL. Transistors MN22 to MN25 are N-type MOSFETs. The gate of transistor MN22 is connected to a control line WSL, the drain is connected to a signal line SGL, and the source is connected to the gate of transistor MN24 and capacitor C21. One end of capacitor C21 is connected to the source of transistor MN22 and the gate of transistor MN24, and the other end is connected to the source of transistor MN24, the drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN23 is connected to a control line DSL, the drain is connected to a power supply line VCCP, and the source is connected to the drain of transistor MN24. The gate of transistor MN24 is connected to the source of transistor MN22 and one end of capacitor C21, the drain is connected to the source of transistor MN23, the source is connected to the other end of capacitor C21, the drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN25 is connected to control line AZSL, the drain is connected to the source of transistor MN24, the other end of capacitor C21, and the anode of light-emitting element EL, and the source is connected to power supply line VSS.

[0125] With this configuration, in pixel PIX, when transistor MN22 is turned on, the voltage across capacitor C21 is set based on the pixel signal supplied from signal line SGL. Transistor MN23 is turned on and off based on the signal on control line DSL. While transistor MN23 is on, transistor MN24 passes a current corresponding to the voltage across capacitor C21 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MN24. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN25 is turned on and off based on the signal on control line AZSL. While transistor MN25 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0126] The transistors MN22 to MN25 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MN22 and MN25 may be a transistor using an oxide semiconductor.

[0127] (Fourth Configuration Example) Figure 33 shows one configuration example of a pixel PIX. This pixel PIX has a capacitor C31, transistors MP32 to MP36, and a light-emitting element EL. Transistors MP32 to MP36 are P-type MOSFETs. The gate of transistor MP32 is connected to a control line WSL, its source is connected to a signal line SGL, and its drain is connected to the gate of transistor MP33, the drain of transistor MP34, and capacitor C31. One end of capacitor C31 is connected to a power supply line VCCP, and the other end is connected to the drain of transistor MP32, the gate of transistor MP33, and the drain of transistor MP34. The gate of transistor MP34 is connected to a control line AZSL1, its source is connected to the drain of transistor MP33 and the source of transistor MP35, and its drain is connected to the drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31. The gate of transistor MP35 is connected to the control line DSL, the source is connected to the drain of transistor MP33 and the source of transistor MP34, the drain is connected to the source of transistor MP36 and the anode of the light-emitting element EL, the gate of transistor MP36 is connected to the control line AZSL2, the source is connected to the drain of transistor MP35 and the anode of the light-emitting element EL, and the drain is connected to the power supply line VSS.

[0128] With this configuration, in pixel PIX, when transistor MP32 is turned on, the voltage across capacitor C31 is set based on the pixel signal supplied from signal line SGL. Transistor MP35 is turned on and off based on the signal on control line DSL. While transistor MP35 is on, transistor MP33 passes a current corresponding to the voltage across capacitor C31 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP33. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP34 is turned on and off based on the signal on control line AZSL1. While transistor MP34 is on, the drain and gate of transistor MP33 are connected to each other. Transistor MP36 is turned on and off based on the signal on control line AZSL2. While transistor MP36 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0129] The transistors MP32 to MP36 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP32, MP34, and MP36 may be a transistor using an oxide semiconductor.

[0130] 34 shows a configuration example of pixel PIX. One end of capacitor C48 is connected to signal line SGL1, and the other end is connected to power supply line VSS. One end of capacitor C49 is connected to signal line SGL1, and the other end is connected to signal line SGL2. Transistor MP49 is a P-type MOSFET, and its gate is connected to control line WSL2, its source is connected to signal line SGL1, and its drain is connected to signal line SGL2.

[0131] The pixel PIX includes a capacitor C41, transistors MP42 to MP46, and a light-emitting element EL. Transistors MP42 to MP46 are P-type MOSFETs. The gate of transistor MP42 is connected to a control line WSL1, its source is connected to a signal line SGL2, and its drain is connected to the gate of transistor MP43 and capacitor C41. One end of capacitor C41 is connected to a power supply line VCCP, and the other end is connected to the drain of transistor MP42 and the gate of transistor MP43. The gate of transistor MP43 is connected to the drain of transistor MP42 and the other end of capacitor C41, its source is connected to the power supply line VCCP, and its drain is connected to the sources of transistors MP44 and MP45. The gate of transistor MP44 is connected to a control line AZSL1, its source is connected to the drain of transistor MP43 and the source of transistor MP45, and its drain is connected to signal line SGL2. The gate of transistor MP45 is connected to control line DSL, the source is connected to the drain of transistor MP43 and the source of transistor MP44, the drain is connected to the source of transistor MP46 and the anode of light-emitting element EL, the gate of transistor MP46 is connected to control line AZSL2, the source is connected to the drain of transistor MP45 and the anode of light-emitting element EL, and the drain is connected to power supply line VSS.

[0132] With this configuration, in pixel PIX, when transistor MP42 is turned on, the voltage across capacitor C41 is set based on the pixel signal supplied from signal line SGL1 via capacitor C49. Transistor MP45 is turned on and off based on the signal on control line DSL. While transistor MP45 is on, transistor MP43 passes a current corresponding to the voltage across capacitor C41 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP43. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP44 is turned on and off based on the signal on control line AZSL1. While transistor MP44 is on, the drain of transistor MP43 and signal line SGL2 are connected to each other. Transistor MP46 is turned on and off based on the signal on control line AZSL2. While transistor MP46 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0133] The transistors MP42 to MP46 and MP49 may be transistors using low temperature polysilicon (LTPS). At least one of the transistors MP42, MP46 and MP49 may be a transistor using an oxide semiconductor.

[0134] 35 shows an example of the configuration of a pixel PIX. A plurality of pixels PIX are arranged in a matrix in a display area 100, and the display area 100 is provided between a first control unit 40 and a second control unit 70.

[0135] The first control unit 40 includes transmission gates TG45 and TG46, transistors MP50 and MP51, and a capacitor C71. The transistors MP50 and MP51 are P-type MOSFETs. A pixel signal is supplied to the input terminal of the transmission gate TG45, and the output terminal of the transmission gate TG45 is connected to one end of a signal line 50a. The input terminal of the transmission gate TG46 is connected to a signal line 50b, and the output terminal of the transmission gate TG46 is connected to a power supply line Vorst. One end of the capacitor C71 is connected to the signal line 50a, and the other end is connected to a power supply line VSS1. The gate of the transistor MP50 is connected to a control line INIL, the source is connected to a power supply line Vini, and the drain is connected to a signal line 50b. The gate of the transistor MP51 is connected to a control line ELL, the source is connected to a power supply line Vel, and the drain is connected to the signal line 50b.

[0136] The second control unit 70 has a transmission gate TG72, a transistor MP73, and a capacitor C82. The transistor MP73 is a P-type MOSFET. The input terminal of the transmission gate TG72 is connected to the other end of the signal line 50a, and the output terminal is connected to the drain of the transistor MP73 and one end of the capacitor C82. The gate of the transistor MP73 is connected to the control line REFL, the source is connected to the power supply line Vref, and the drain is connected to the output terminal of the transmission gate TG72 and one end of the capacitor C82. One end of the capacitor C82 is connected to the output terminal of the transmission gate TG72 and the drain of the transistor MP73, and the other end is connected to one end of the signal line 50b.

[0137] The pixel PIX includes a capacitor C132, transistors MP121 to MP125, and a light-emitting element EL. The transistors MP121 to MP125 are P-type MOSFETs. The gate of the transistor MP122 is connected to the control line WSL, its source is connected to the signal line 50b, and its drain is connected to the gate of the transistor MP121 and the capacitor C132. One end of the capacitor C132 is connected to the power supply line Vel, and the other end is connected to the drain of the transistor MP122 and the gate of the transistor MP121. The gate of the transistor MP121 is connected to the drain of the transistor MP122 and the other end of the capacitor C132, its source is connected to the power supply line Vel, and its drain is connected to the sources of the transistors MP123 and MP124. The gate of the transistor MP123 is connected to the control line AZSL, its source is connected to the drain of the transistor MP121 and the source of the transistor MP124, and its drain is connected to the signal line 50b. The gate of transistor MP124 is connected to the control line DSL, the source is connected to the drain of transistor MP121 and the source of transistor MP123, and the drain is connected to the drain of transistor MP125 and the anode of the light-emitting element EL. The gate of transistor MP125 is connected to the control line AZSL, the source is connected to the power supply line Vorst, and the drain is connected to the drain of transistor MP124 and the anode of the light-emitting element EL.

[0138] With this configuration, in pixel PIX, when transistor MP122 is turned on, the voltage across capacitor C132 is set based on the pixel signal supplied via transmission gate TG45, signal line 50a, transmission gate TG72, capacitor C82, and signal line 50b. Transistor MP124 is turned on and off based on the signal on control line DSL. While transistor MP124 is on, transistor MP121 passes a current corresponding to the voltage across capacitor C132 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP121. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistors MP123 and MP125 are turned on and off based on the signal on control line AZSL. While transistor MP123 is on, the drain of transistor MP121 and the source of transistor MP124 are connected to signal line 50b. During the period when transistor MP125 is in the ON state, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line Vorst. Furthermore, transistor MP50 is turned on and off based on the signal on control line INIL, transistor MP51 is turned on and off based on the signal on control line ELL, and transistor MP73 is turned on and off based on the signal on control line REFL. When transistor MP50 is in the ON state, signal line 50b is set to the voltage of power supply line Vini, and when transistor MP51 is in the ON state, signal line 50b is set to the voltage of power supply line Vel. When transistor MP73 is in the ON state, one end of capacitor C82 is initialized by being set to the voltage of power supply line Vref.

[0139] The transistors MP121 to MP125, MP50, and MP51 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP122 and MP125 may be a transistor using an oxide semiconductor.

[0140] (Seventh Configuration Example) Figure 36 shows one configuration example of a pixel PIX. This pixel PIX has a capacitor C51, transistors MP52 to MP60, and a light-emitting element EL. Transistors MP52 to MP60 are P-type MOSFETs. The gate of transistor MP52 is connected to a control line WSL, its source is connected to a signal line SGL, and its drain is connected to the drain of transistor MP53 and the source of transistor MP54. The gate of transistor MP53 is connected to a control line DSL, its source is connected to a power supply line VCCP, and its drain is connected to the drain of transistor MP52 and the source of transistor MP54. The gate of transistor MP54 is connected to the source of transistor MP55, the drain of transistor MP57, and capacitor C51, its source is connected to the drains of transistors MP52 and MP53, and its drain is connected to the sources of transistors MP58 and MP59. One end of capacitor C51 is connected to the power supply line VCCP, and the other end is connected to the gate of transistor MP54, the source of transistor MP55, and the drain of transistor MP57. Capacitor C51 may include two capacitors connected in parallel. Transistor MP55 has a gate connected to control line AZSL1, a source connected to the gate of transistor MP54, the drain of transistor MP57, and the other end of capacitor C51, and a drain connected to the source of transistor MP56. Transistor MP56 has a gate connected to control line AZSL1, a source connected to the drain of transistor MP55, and a drain connected to power supply line VSS. Transistor MP57 has a gate connected to control line WSL, a drain connected to the gate of transistor MP54, the source of transistor MP55, and the other end of capacitor C51, and a source connected to the drain of transistor MP58. The gate of the transistor MP58 is connected to the control line WSL, the drain is connected to the source of the transistor MP57, and the source is connected to the drain of the transistor MP54 and the source of the transistor MP59.The gate of transistor MP59 is connected to control line DSL, the source is connected to the drain of transistor MP54 and the source of transistor MP58, the drain is connected to the source of transistor MP60 and the anode of light-emitting element EL, the gate of transistor MP60 is connected to control line AZSL2, the source is connected to the drain of transistor MP59 and the anode of light-emitting element EL, and the drain is connected to power supply line VSS.

[0141] With this configuration, in pixel PIX, transistors MP52, MP54, MP58, and MP57 are turned on, and the voltage across capacitor C51 is set based on the pixel signal supplied from signal line SGL. Transistors MP53 and MP59 are turned on and off based on the signal on control line DSL. While transistors MP53 and MP59 are on, transistor MP54 passes a current corresponding to the voltage across capacitor C51 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP54. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistors MP55 and MP56 are turned on and off based on the signal on control line AZSL1. While transistors MP55 and MP56 are on, the gate voltage of transistor MP54 is initialized by being set to the voltage of power supply line VSS. Transistor MP60 is turned on and off based on the signal on control line AZSL2. During the period in which the transistor MP60 is in the on state, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0142] The transistors MP52 to MP60 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP55 to MP58 and MP60 may be a transistor using an oxide semiconductor.

[0143] 37 shows an example (eighth example) of the configuration of the pixel PIX. The signal on the control line WSNL and the signal on the control line WSPL are mutually inverted signals.

[0144] The pixel PIX has capacitors C61 and C62, transistors MN63, MP64, and MN65 to MN67, and a light-emitting element EL. The transistors MN63, MN65 to MN67 are N-type MOSFETs, and the transistor MP64 is a P-type MOSFET. The gate of the transistor MN63 is connected to a control line WSNL, the drain is connected to a signal line SGL and the source of the transistor MP64, and the source is connected to the drain of the transistor MP64, the capacitors C61 and C62, and the gate of the transistor MN65. The gate of the transistor MP64 is connected to a control line WSPL, the source is connected to the signal line SGL and the drain of the transistor MN63, and the drain is connected to the source of the transistor MN63, the capacitors C61 and C62, and the gate of the transistor MN65. The capacitor C61 is configured using, for example, a metal oxide metal (MOM) capacitor, with one end connected to the source of transistor MN63, the drain of transistor MP64, capacitor C62, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C61 may be configured using, for example, a metal oxide metal (MOS) capacitor or a metal insulator metal (MIM) capacitor. The capacitor C62 is configured using, for example, a MOS capacitor, with one end connected to the source of transistor MN63, the drain of transistor MP64, one end of capacitor C61, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C62 may be configured using, for example, a MOM capacitor or a MIM capacitor. The other end of the capacitor C62 may be connected to the power supply line VSS3 (not shown). The gate of transistor MN65 is connected to the source of transistor MN63, the drain of transistor MP64, and one end of capacitors C61 and C62, the drain is connected to the power supply line VCCP, and the source is connected to the drains of transistors MN66 and MN67. The gate of transistor MN66 is connected to control line AZL, the drain is connected to the source of transistor MN65 and the drain of transistor MN67, and the source is connected to power supply line VSS1.The gate of transistor MN67 is connected to the control line DSL, the drain is connected to the source of transistor MN65 and the drain of transistor MN66, and the source is connected to the anode of the light-emitting element EL. Note that the transistor MN67 and the control line DSL may be omitted, and the source of transistor MN65 may be connected to the drain of transistor MN66 and the anode of the light-emitting element EL.

[0145] With this configuration, in pixel PIX, when at least one of transistors MN63 and MP64 is turned on, the voltage across capacitors C61 and C62 is set based on the pixel signal supplied from signal line SGL. Transistor MN67 is turned on and off based on the signal on control line DSL. While transistor MN67 is on, transistor MN65 passes a current corresponding to the voltage across capacitors C61 and C62 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP65. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN66 may be turned on and off based on the signal on control line AZL. Transistor MN66 may also function as a resistor element having a resistance value corresponding to the signal on control line AZL. In this case, transistors MN65 and MN66 form a so-called source follower circuit.

[0146] The transistors MN63, MP64, MN65 to MN67 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MN63, MP64, and MN66 may be a transistor using an oxide semiconductor.

[0147] <10. Modifications> Although the embodiments and application examples of the present technology have been specifically described above, the content of the present technology is not limited to the above-described embodiments and application examples, and various modifications based on the technical concept of the present technology are possible. For example, the configurations, methods, processes, materials, shapes, and numerical values ​​of the above-described embodiments and application examples can be combined or replaced with each other as long as they do not deviate from the spirit of the present technology. Furthermore, it is also possible to divide one thing into two or more parts, and it is also possible to omit some parts. Furthermore, as long as the present technology is applicable, the above-described configurations may be appropriately deleted, modified, or added with other configurations, or replaced with alternative configurations.

[0148] In the above-described embodiment, the display device 1 is an OLED microdisplay, but the present technology is not limited to this. For example, the present technology may be applied to a display panel such as an SXRD (Silicon X-tal Reflective Display: registered trademark) used in a projector, or a phase modulation panel using an SLM (Spatial Light Modulator) for displaying holograms. In addition, the present technology may be applied to a panel such as an LCOS (Liquid crystal on silicon, LCoS is a trademark) or an HTPS (High Temperature Poly-Silicon) panel.

[0149] 11. Application Examples Next, application examples of the display systems described in the above embodiments and modifications will be described.

[0150] 38 shows an example of the appearance of a head-mounted display 110. The head-mounted display 110 has, for example, ear hooks 112 for wearing on the user's head on both sides of a glasses-shaped display unit 111. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 110.

[0151] (Application Example 2) FIG. 39 shows an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a see-through head-mounted display having a main body 121, an arm 122, and a lens barrel 123. This head-mounted display 120 is attached to eyeglasses 128. The main body 121 has a control board and a display unit for controlling the operation of the head-mounted display 120. The display unit emits image light of a displayed image. The arm 122 connects the main body 121 to the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light supplied from the main body 121 via the arm 122 toward the user's eyes via lenses 129 of the eyeglasses 128. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 120.

[0152] The head-mounted display 120 is a so-called light guide plate type head-mounted display, but is not limited to this and may be, for example, a so-called birdbath type head-mounted display. The birdbath type head-mounted display includes, for example, a beam splitter and a partially transparent mirror. The beam splitter outputs light encoded with image information toward the mirror, and the mirror reflects the light toward the user's eyes. Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.

[0153] (Application Example 3) Figures 40A and 40B show an example of the appearance of a digital still camera 130, with Figure 40A showing a front view and Figure 40B showing a rear view. This digital still camera 130 is a single-lens reflex camera with interchangeable lenses and includes a camera body 131, a photographing lens unit 132, a grip 133, a monitor 134, and an electronic viewfinder 135. The photographing lens unit 132 is an interchangeable lens unit and is provided near the center of the front of the camera body 131. The grip 133 is provided on the left side of the front of the camera body 131, and is held by the photographer. The monitor 134 is provided to the left of the center of the back of the camera body 131. The electronic viewfinder 135 is provided above the monitor 134 on the back of the camera body 131. By looking through this electronic viewfinder 135, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 132 and determine the composition. The techniques according to the above-described embodiments and the like can be applied to the electronic viewfinder 135.

[0154] 41 shows an example of the appearance of a television device 140. The television device 140 has an image display screen unit 141 including a front panel 142 and a filter glass 143. The techniques according to the above-described embodiments and the like can be applied to this image display screen unit 141.

[0155] 42 shows an example of the appearance of a smartphone 150. The smartphone 150 has a display unit 151 that displays various information and an operation unit 152 that includes buttons and the like that accept operation inputs from a user. The techniques according to the above-described embodiments and the like can be applied to this display unit 151.

[0156] (Application Example 6) Figures 43A and 43B show an example configuration of a vehicle to which the technology of the present disclosure is applied, where Figure 43A shows an example of the interior of the vehicle as seen from the rear of vehicle 200, and Figure 43B shows an example of the interior of the vehicle as seen from the left rear of vehicle 200.

[0157] The vehicle in Figures 43A and 43B has a center display 201, a console display 202, a head-up display 203, a digital rearview mirror 204, a steering wheel display 205, and a rear entertainment display 206.

[0158] The center display 201 is disposed on the dashboard 261 in a position facing the driver's seat 262 and the passenger's seat 263. While FIG. 43A illustrates an example of a horizontally elongated center display 201 extending from the driver's seat 262 side to the passenger's seat 263 side, the screen size and location of the center display 201 are not limited to this. The center display 201 can display information detected by various sensors. As a specific example, the center display 201 can display an image captured by an image sensor, a distance image to obstacles in front of or to the side of the vehicle measured by a ToF sensor, and the body temperature of an occupant detected by an infrared sensor. The center display 201 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information.

[0159] The safety-related information includes information based on sensor detection results, such as detection of drowsiness, distraction, child mischief, whether a seatbelt is fastened, and whether a passenger is abandoned. The operation-related information includes gesture information related to passenger operations detected by sensors. The gestures may include operations of various vehicle equipment, such as air conditioning, navigation, audiovisual (AV) equipment, and lighting. The life log includes life logs of all passengers. For example, the life log includes a record of each passenger's behavior. By acquiring and storing the life log, it is possible to determine the condition of the passengers at the time of an accident. The health-related information includes the passenger's body temperature detected using a temperature sensor and information on the passenger's health condition estimated based on the detected body temperature. Alternatively, the passenger's health condition information may be estimated based on the passenger's face captured by an image sensor. Furthermore, the passenger's health condition information may be estimated based on the passenger's responses obtained through an automated voice conversation with the passenger. The authentication / identification-related information includes information on a keyless entry function that uses a sensor to perform facial authentication, a function that automatically adjusts the seat height and position by facial recognition, etc. The entertainment-related information includes information on AV device operations by occupants detected by the sensor, and information on content to be displayed that is appropriate for the occupants detected and recognized by the sensor.

[0160] The console display 202 can be used to display, for example, life log information. The console display 202 is disposed near a shift lever 265 on a center console 264 between a driver's seat 262 and a passenger seat 263. The console display 202 can also display information detected by various sensors. The console display 202 may also display an image of the vehicle's surroundings captured by an image sensor, or an image showing the distance to an obstacle around the vehicle.

[0161] The head-up display 203 is virtually displayed behind a windshield 266 in front of the driver's seat 262. The head-up display 203 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. Since the head-up display 203 is often virtually disposed in front of the driver's seat 262, it is suitable for displaying information directly related to vehicle operation, such as the vehicle speed, the remaining fuel level, and the remaining battery level.

[0162] The digital rearview mirror 204 can not only display the rear of the vehicle, but also display the status of passengers in the rear seats, and can therefore be used to display life log information of passengers in the rear seats, for example.

[0163] The steering wheel display 205 is disposed near the center of the vehicle's steering wheel 267. The steering wheel display 205 can be used to display at least one of, for example, safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 205 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information related to the operation of AV equipment, air conditioning equipment, etc.

[0164] The rear entertainment display 206 is attached to the rear side of the driver's seat 262 and the passenger seat 263 and is intended for viewing by rear seat passengers. The rear entertainment display 206 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, since the rear entertainment display 206 is located in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 206. The rear entertainment display 206 may display, for example, information related to the operation of an AV device or an air conditioning system, or may display the results of measurement of the body temperature of the rear seat passengers using a temperature sensor.

[0165] The techniques according to the above-described embodiments can be applied to the center display 201, console display 202, head-up display 203, digital rearview mirror 204, steering wheel display 205, and rear entertainment display 206.

[0166] The present technology may also have the following configurations: (1) A display device comprising: a ramp wiring to which a ramp signal whose voltage level changes over time is supplied; a first switch provided between the ramp wiring and a signal line connected to a pixel; a second switch that operates inversely to the first switch; a correction current source that supplies a correction current to the ramp wiring in accordance with the operation of the second switch; and a correction current control circuit that controls a current value of the correction current source based on a current generated based on a set voltage that determines the amplitude of the ramp signal. (2) The display device according to (1), further comprising: a variable current source that generates a current based on a set voltage, wherein the correction current control circuit copies the current of the variable current source and determines the current of the correction current source based on the copied current. (3) The display device according to (2), wherein the variable current source is used to generate the ramp signal. (4) The display device according to (2) or (3), further comprising: a ramp generation circuit that generates the ramp signal, the ramp generation circuit comprising: an amplifier that outputs the ramp signal; a load circuit arranged on a feedback path of the amplifier; and a current generation circuit that controls a current flowing through the load circuit in accordance with a signal voltage of the ramp signal and a reference voltage included in the set voltage, wherein the variable current source is constituted by the current generation circuit. (5) The display device according to any one of (1) to (4), further comprising: a correction current supply circuit having the correction current source and the second switch; and a correction current control circuit, each of which is provided in accordance with the arrangement of the ramp generation circuit that generates the ramp signal. (6) The display device according to (5), further comprising: one ramp generation circuit for every pixel; and one variable current source used in the ramp generation circuit for collectively controlling the currents of the correction current sources corresponding to all pixels. (7) The display device according to (5), further comprising: a ramp generation circuit for each color of pixel; and a variable current source corresponding to the color used in each ramp generation circuit for controlling the current of each correction current source in accordance with the color of the corresponding pixel.(8) The display device according to (5), wherein the ramp generation circuit is provided for each block formed of a predetermined number of pixels, and the current of each correction current source is controlled on a block-by-block basis using the variable current source used in each ramp generation circuit. (9) The display device according to any of (1) to (8), wherein the ramp signal has a ramp waveform that changes from a high voltage level to a low voltage level. (10) The display device according to (9), wherein the correction current source is provided between the second switch and the ramp wiring, and the second switch is provided between a power supply and the correction current source. (11) The display device according to (9), wherein the correction current source is provided between a power supply and the second switch, and the second switch is provided between the correction current source and the ramp wiring. (12) The display device according to any of (1) to (11), wherein the ramp signal has a ramp waveform that changes from a low voltage level to a high voltage level. (13) The display device according to (12), wherein the correction current source is provided between the second switch and the lamp wiring, and the second switch is provided between ground (GND) and the correction current source. (14) The display device according to (12), wherein the correction current source is provided between ground (GND) and the second switch, and the second switch is provided between the correction current source and the lamp wiring. (15) An electronic device having the display device according to any one of (1) to (14).

[0167] 1...display device, 6...timing controller, 7...pixel unit, 8...vertical logic unit, 9...vertical analog unit, 10...horizontal logic unit, 11...horizontal analog unit, 20...ramp processing unit, 21A...PWM switch, 23...lamp driving circuit, 24...correction current supply circuit, 25...ramp generating circuit, 26...correction current control circuit, 27...XPWM switch, 28...correction current source, 29...current mirror unit, 30...variable current source for correction current, 31...output buffer, 33...current control circuit, 34...SMPL switch, 35...variable current source, 36...comparator, 37...holding unit, 41...amplifier, 42...load circuit, 43...RAMPEN switch, 44...PRCG switch, PIX...pixel (pixel circuit), RL...lamp wiring

Claims

1. A display device comprising: a ramp wiring to which a ramp signal whose voltage level changes over time is supplied; a first switch provided between the ramp wiring and a signal line connected to a pixel; a second switch that operates inversely to the first switch; a correction current source that supplies a correction current to the ramp wiring in response to the operation of the second switch; and a correction current control circuit that controls the current value of the correction current source on the basis of a current generated on the basis of a set voltage that determines the amplitude of the ramp signal.

2. The display device according to claim 1, further comprising a variable current source that generates a current based on a set voltage, and the correction current control circuit copies the current of the variable current source and determines the current of the correction current source based on the copied current.

3. The display device according to claim 2, wherein the variable current source is used to generate the ramp signal.

4. The display device according to claim 2, further comprising a ramp generating circuit for generating the ramp signal, the ramp generating circuit comprising: an amplifier for outputting the ramp signal; a load circuit arranged on a feedback path of the amplifier; and a current generating circuit for controlling a current flowing through the load circuit in accordance with a signal voltage of the ramp signal and a reference voltage included in the set voltage, and the variable current source is constituted by the current generating circuit.

5. The display device according to claim 1, wherein the correction current supply circuit having the correction current source and the second switch, and the correction current control circuit are each provided in accordance with the arrangement of a ramp generating circuit that generates the ramp signal.

6. The display device according to claim 5, wherein one ramp generating circuit is provided for all pixels, and the currents of the correction current sources corresponding to all pixels are collectively controlled by one variable current source used in the ramp generating circuit.

7. The display device according to claim 5, further comprising a ramp generating circuit for each pixel color, and wherein the current of each correction current source is controlled in accordance with the color of the corresponding pixel by using the variable current source corresponding to the color used in each ramp generating circuit.

8. The display device according to claim 5, further comprising a ramp generating circuit for each block made up of a predetermined number of pixels, and wherein the variable current source used in each ramp generating circuit is used to control the current of each correction current source on a block-by-block basis.

9. The display device according to claim 1, wherein the ramp signal has a ramp waveform whose voltage level changes from a high side to a low side.

10. The display device according to claim 9, wherein the correction current source is provided between the second switch and the lamp wiring, and the second switch is provided between a power source and the correction current source.

11. The display device according to claim 9, wherein the correction current source is provided between a power source and the second switch, and the second switch is provided between the correction current source and the lamp wiring.

12. The display device according to claim 1, wherein the ramp signal has a ramp waveform whose voltage level changes from a low side to a high side.

13. The display device according to claim 12, wherein the correction current source is provided between the second switch and the lamp wiring, and the second switch is provided between ground (GND) and the correction current source.

14. The display device according to claim 12, wherein the correction current source is provided between a ground (GND) and the second switch, and the second switch is provided between the correction current source and the lamp wiring.

15. An electronic device comprising the display device according to claim 1.

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