Display device and electronic apparatus

Abstract

The present invention, for example, suppresses a decrease in image quality caused by variation in signals outputted from output sources.　This display device comprises: a first output source that outputs a first analog voltage; a second output source that outputs a second analog voltage and is different from the first output source; a plurality of first signal lines that are connected to the first output source; a plurality of second signal lines that are connected to the second output source; and a pixel array unit in which the first signal lines, first pixels connected to the first signal lines, the second signal lines, and second pixels connected to the second signal lines are arranged. The pixel array unit has a first area in which the first signal lines are continuously arranged, a second area in which the second signal lines are continuously arranged, and a third area which is formed between the first area and the second area and in which the first signal lines and the second signal lines are substantially alternately arranged.

Description

Display devices and electronic devices

[0001] The present technology relates to a display device and an electronic device.

[0002] Display devices using self-luminous elements (light-emitting elements) are known. Such display devices have advantages such as higher visibility compared to conventional display devices using liquid crystal, and the ability to be lightweight, thin, and compact with low power consumption. For example, Patent Document 1 listed below describes a display device in which the output of a single lamp digital-to-analog converter (DAC) is branched into two systems and the branched outputs are supplied to different pixels.

[0003] Japanese Patent Application Laid-Open No. 2021-152680

[0004] When a plurality of pixels arranged in a pixel array unit are driven in a distributed manner using different output sources (source drivers), there is a risk that the image quality of the display device will be reduced due to variations in the signals output from the output sources. The display device described in Patent Document 1 lacks this perspective and has room for improvement.

[0005] An object of the present technology is to provide a display device that suppresses degradation of image quality caused by variations in signals output from an output source, and an electronic device that includes the display device.

[0006] The present technology relates to a display device having, for example, a first output source that outputs a first analog voltage, a second output source that outputs a second analog voltage and is different from the first output source, a plurality of first signal lines connected to the first output source, a plurality of second signal lines connected to the second output source, and a pixel array section in which the first signal lines, first pixels connected to the first signal lines, second signal lines, and second pixels connected to the second signal lines are arranged, wherein the pixel array section has a first region in which the first signal lines are continuously arranged, a second region in which the second signal lines are continuously arranged, and a third region formed between the first region and the second region and in which the first signal lines and the second signal lines are substantially alternately arranged. The present technology may also relate to an electronic device having the above display device.

[0007] 1 is a schematic diagram for explaining a distributed driving method, which is one of driving methods for a display device; FIG. 2 is a diagram showing an example waveform of a ramp wave generated by a RAMPDAC; FIG. 3 is a diagram for explaining an overview of the present technology; FIG. 4 is a diagram showing an example configuration of a display device according to a first embodiment; FIG. 5 is a diagram showing an example configuration of a pixel array unit according to the first embodiment; FIG. 6 is a diagram showing an example configuration of a pixel according to the first embodiment; FIG. 7 is a diagram for explaining an example configuration of a signal line driver according to the first embodiment; FIG. 8 is a diagram referred to when explaining an example operation of a lamp driver circuit etc. according to the first embodiment; FIG. 9 is a diagram referred to when explaining a specific configuration example of a pixel array unit etc. according to the first embodiment; FIG. 10 is a diagram referred to when explaining a specific configuration example of a pixel array unit etc. according to the second embodiment; FIG. 11 is a diagram referred to when explaining a specific configuration example of a pixel array unit etc. according to the third embodiment; FIG. 12 is a diagram referred to when explaining an effect obtained in the display device according to the third embodiment; FIG. 13 is a diagram referred to when explaining an effect obtained in the display device according to the third embodiment. FIG. 1 is a diagram showing a general configuration example of a display device having lamp drive circuits corresponding to different color types. FIG. 2 is a diagram referred to when describing a specific configuration example of a pixel array section etc. according to a fourth embodiment. FIG. 3 is a diagram referred to when describing a specific configuration example of a pixel array section etc. according to the fourth embodiment. FIG. 4 is a diagram referred to when describing a specific configuration example of a pixel array section etc. according to the fourth embodiment. FIG. 5 is a diagram referred to when describing a specific configuration example of a pixel array section etc. according to the fifth embodiment. FIG. 6 is a diagram referred to when describing a specific configuration example of a pixel array section etc. according to the fifth embodiment. FIG. 7 is a perspective view showing an example of the appearance of a head-mounted display. FIG. 8 is a perspective view showing an example of the appearance of a see-through head-mounted display. FIG. 9 is a front view showing an example of the appearance of a digital still camera.1B is a rear view showing an example of the appearance of a digital still camera; FIG. 1B is a perspective view showing an example of the appearance of a television device; FIG. 1C is a perspective view showing an example of the appearance of a smartphone; FIG. 1A is a diagram showing an example of the interior of a vehicle from the rear to the front of the vehicle; FIG. 1B is a diagram showing an example of the interior of a vehicle from diagonally rear to diagonally front of the vehicle; FIG. 1C is a diagram showing an example of the configuration of a pixel circuit to which the present technology can be applied; FIG. 1D is a diagram showing an example of the configuration of a pixel circuit to which the present technology can be applied; FIG. 1E is a diagram showing an example of the configuration of a pixel circuit to which the present technology can be applied; FIG. 1F is a diagram showing an example of the configuration of a pixel circuit to which the present technology can be applied; FIG. 1G is a diagram for explaining a modified example; FIG. 1H and FIG. 1H are diagrams for explaining a modified example;

[0008] Hereinafter, embodiments of the present technology will be described with reference to the drawings. The description will be given in the following order: <Outline of the present technology> <First embodiment> <Second embodiment> <Third embodiment> <Fourth embodiment> <Fifth embodiment> <Application example> <Modification example> Note that in this specification and drawings, components having substantially the same function or configuration are assigned the same reference numerals, and duplicated descriptions will be omitted as appropriate. Furthermore, to simplify the illustrations, reference numerals may be omitted in the drawings, or only some of the same components may be assigned the same reference numerals.

[0009] <Outline of the Present Technology> First, an outline of the present technology will be described while explaining problems to be considered in the present technology. A display device according to the present technology is, for example, a device having a light-emitting element. The light-emitting element is, for example, an LED (Light Emitting Diode). LEDs include LEDs used in micro LED displays and OLEDs (Organic Light Emitting Diodes) used in organic EL (Electro-Luminescence) displays. Organic EL displays include, for example, OLED micro displays (Organic Light-Emitting Diode Micro Displays). The display device is, for example, a display mounted on an electronic device such as an electronic viewfinder (EVF) of a digital camera, augmented reality (AR) glasses, or virtual reality (VR) glasses. Note that the display device is not limited to this, and may be, for example, a medium-sized or large display of a smartphone, tablet, or the like.

[0010] As a driving method for the above-mentioned display device, a method is known in which a lamp driving circuit as an output source generates a ramp wave with a uniformly fluctuating potential and supplies a voltage obtained by sampling the ramp wave to pixels. Also, in a display device with a relatively large angle of view, a distributed driving method is used in which multiple pixels are divided into blocks, and a lamp driving circuit is provided for each block, and the lamp driving circuit drives the corresponding pixel.

[0011] Fig. 1 is a schematic diagram illustrating a distributed driving method used in a display device. The display device shown in Fig. 1 (hereinafter referred to as display device 1) has a lamp driving circuit 2A and a lamp driving circuit 2B. In an actual distributed driving method, more lamp driving circuits may be used, but for convenience of explanation, only two lamp driving circuits (two channels) are shown here.

[0012] A plurality of signal lines 3A are connected to the lamp drive circuit 2A. A plurality of pixels P are connected to each of the signal lines 3A. A switch unit 4A is provided between the lamp drive circuit 2A and each of the signal lines 3A. A plurality of signal lines 3B are connected to the lamp drive circuit 2B. A plurality of pixels P are connected to each of the signal lines 3B. A switch unit 4B is provided between the lamp drive circuit 2B and each of the signal lines 3B.

[0013] The processing performed in the distributed driving method using the lamp driving circuits 2A and 2B will now be briefly described. The lamp driving circuit 2A generates a ramp wave. The ramp wave is sampled when the switch unit 4A is turned on, and a voltage corresponding to a predetermined gradation is output from the lamp driving circuit 2A. The output voltage is supplied to a signal line 3A via the turned-on switch unit 4A. Thereafter, the switch unit 4A is turned off, and the signal line 3A is fixed at a voltage corresponding to the predetermined gradation. The pixel P connected to the signal line 3A then emits light at a luminance corresponding to the supplied voltage. The lamp driving circuit 2B also generates a ramp wave. The ramp wave is sampled when the switch unit 4B is turned on, and a voltage corresponding to the predetermined gradation is output from the lamp driving circuit 2B. The output voltage is supplied to a signal line 3B via the turned-on switch unit 4B. Thereafter, the switch unit 4B is turned off, and the signal line 3B is fixed at a voltage corresponding to the predetermined gradation. The pixel P connected to the signal line 3B then emits light at a luminance corresponding to the supplied voltage.

[0014] Fig. 2 is a diagram showing an example of the waveform of a ramp wave generated by a lamp drive circuit. The waveform on the left side of Fig. 2 shows the waveform of a ramp wave generated by, for example, lamp drive circuit 2A, and the waveform on the right side of Fig. 2 shows the waveform of a ramp wave generated by, for example, lamp drive circuit 2B. The upper side of each ramp waveform corresponds to, for example, the 0 gradation voltage (pixel color is, for example, black), and the lower side corresponds to the MAX gradation voltage (pixel color is, for example, white, and 255 gradations for 8 bits or 1023 gradations for 10 bits).

[0015] For example, a difference occurs in the MAX gradation voltages of the two ramp waves due to variations in the characteristics of the components of the lamp drive circuit (e.g., DAC, operational amplifier, etc.). Note that a difference may occur in the 0 gradation voltages of the two ramp waves, or a difference may occur in the slope of the potential fluctuations of the respective ramp waves.

[0016] When such a difference occurs, even if the respective ramp waves are sampled to achieve the same gradation, the voltages after sampling may not achieve the same gradation. That is, variations occur between the output of lamp driving circuit 2A and the output of lamp driving circuit 2B. This variation causes a difference in brightness between the pixel P connected to signal line 3A and the pixel P connected to signal line 3B, and this brightness difference is visually recognized as, for example, a vertical band-like line. This phenomenon is also called "surface cracking," and can cause a decrease in the image quality of the display device 1. Note that this problem can also occur when the output source is a circuit other than the lamp driving circuit (e.g., a voltage follower circuit).

[0017] The embodiment of the present technology addresses the above-mentioned problem. Schematically, as shown in FIG. 3 , the boundary between an area where a signal line 3A, which is the output destination of a lamp driving circuit 2A, is disposed and an area where a signal line 3B, which is the output destination of a lamp driving circuit 2B, is disposed, is partially overlapped. As a result, even if a luminance difference occurs between a pixel connected to signal line 3A and a pixel connected to signal line 3B, the presence of the overlapping portion mitigates the luminance difference. For example, the luminance of the overlapping portion is approximately intermediate between the luminance of the pixel connected to signal line 3A and the luminance of the pixel connected to signal line 3B, thereby mitigating the luminance difference between the pixels connected to each signal line. This prevents a band-like line from being visible to the user, thereby preventing a decrease in the image quality of the display device 1. Taking the above points into consideration, the details of the present technology will be described with reference to the embodiment.

[0018] First Embodiment [Overall Configuration Example of Display Device] Fig. 4 is a block diagram showing a schematic configuration example of a display device (display device 100A) to which the present technology can be applied. Note that the display device described below can be formed by a known manufacturing method. Furthermore, components of the display device can be observed using a known method.

[0019] The display device 100A has a display panel including a semiconductor substrate such as a silicon substrate. As shown in the figure, the display device 100A has an input / output unit 5, a gamma processing unit 6, a power supply processing unit 7, an interface unit 8, an oscillator unit 9, a buffer 10, a timing controller 11, a pixel array unit 20, a signal line driving unit 30, and a control line driving unit 40. The signal line driving unit 30 has a horizontal logic circuit (HLOGIC) 31 and a horizontal analog circuit (HANALOG) 32, and the control line driving unit 40 has a vertical logic circuit (VLOGIC) 41 and a vertical analog circuit (VANALOG) 42.

[0020] The input / output unit 5 inputs and outputs various data and is configured, for example, by an externally connectable FPC (Flexible Printed Circuits). The input / output unit 5 is connected to the gamma processing unit 6, the power supply processing unit 7, and the interface unit 8. The gamma processing unit 6 performs gamma correction processing. The gamma processing unit 6 is connected to the input / output unit 5 and the horizontal analog circuit 32, and sets gamma correction based on a setting value for gamma correction input via the input / output unit 5, and gamma-corrects the pixel signal (pixel signal Data) output from the horizontal analog circuit 32.

[0021] The power supply processing unit 7 is a circuit that outputs power for driving the pixel array unit 20 and includes, for example, an LDO (Low Drop Out) regulator. The power supply processing unit 7 is connected to the input / output unit 5 and the pixel array unit 20, and converts the supply power input via the input / output unit 5 into a power supply voltage for driving the pixel array unit 20 and supplies the converted voltage to the pixel array unit 20. The interface unit 8 is an interface for inputting and outputting image data and the like to and from the outside via the input / output unit 5. For example, a high-speed interface standard such as MIPI (Mobile Industry Processor Interface) can be adopted. The interface unit 8 is connected to the input / output unit 5, the oscillator unit 9, the buffer 10, and the timing controller 11.

[0022] The oscillator 9 is configured, for example, by an oscillator circuit (OSC (Oscillator)) and generates various clock signals. The oscillator 9 is connected to the interface 8, buffer 10, and timing controller 11, and supplies the generated clock signals to each component. The buffer 10 is configured, for example, by a line buffer that holds image data for one horizontal line of an image. The buffer 10 is connected to the interface 8, oscillator 9, and timing controller 11, and sequentially buffers and outputs image data based on the clock signals generated by the oscillator 9.

[0023] The timing controller 11 controls the timing of each block operation. The timing controller 11 is connected to the interface unit 8, the oscillator unit 9, the buffer 10, the horizontal logic circuit 31, the horizontal analog circuit 32, the vertical logic circuit 41, and the vertical analog circuit 42. The timing controller 11 outputs image data output by the buffer 10 to the horizontal logic circuit 31 based on a clock signal generated by the oscillator unit 9, and outputs control signals as needed to the horizontal logic circuit 31 and the horizontal analog circuit 32. The timing controller 11 also outputs control signals as needed to the vertical logic circuit 41 and the vertical analog circuit 42 based on the clock signal generated by the oscillator unit 9. For example, the timing controller 11 outputs start pulses WSST1, DSST, and AZST to the vertical logic circuit 41.

[0024] The pixel array unit 20 has, for example, a rectangular display area and is configured with a plurality of pixels arranged in a matrix, each having a display element such as an organic EL element that is driven for display. In the pixel array unit 20, control lines are provided in the horizontal direction (transverse direction) for each row of the pixels arranged in the matrix, and signal lines are provided for each column, perpendicular to the control lines. The pixel array unit 20 is provided with pixels (also referred to as subpixels) of the three primary colors R (red), G (green), and B (blue). These three pixels represent one dot of a color image. The combination of pixels that represent one dot is not limited to this; a W (white) pixel may be added to improve brightness, or a complementary color pixel may be added to expand the color reproduction range. Furthermore, the display device 100A is not limited to displaying color images, and may also be configured to display monochrome (black and white) images. The shape of the pixel array unit 20 may be circular, elliptical, or other shapes other than rectangular.

[0025] The horizontal logic circuit 31 distributes image data input from the timing controller 11 to each signal line. The horizontal analog circuit 32 converts the distributed image data into gamma-corrected pixel signals (pixel signals Data) and outputs them to corresponding signal lines of the pixel array unit 20. The vertical logic circuit 41 generates shift signals (e.g., shift signals WSSR, DSSR, AZSR) from start pulses (e.g., start pulses WSST1, DSST, AZST). The vertical analog circuit 42 generates control signals (e.g., control signals WS, DS, AZ) from the shift signals and outputs them to the pixel array unit 20.

[0026] As a result, the display device 100A sequentially drives each pixel arranged in the pixel array section 20, causing each pixel to emit light based on the signal level of each signal line, thereby displaying a desired image on the pixel array section 20. Note that the display device 100A is an example of a display device to which the present technology can be applied, and is also applicable to display devices with other configurations. Specifically, as shown in the figure, the present technology is applicable to any display device that drives each pixel with a signal from a first direction (the column direction in the illustrated example) and a signal from a second direction (the row direction in the illustrated example) intersecting the first direction. For example, scanning is not limited to line-sequential scanning, but may also be point-sequential scanning. Furthermore, the pixel arrangement is not limited to a matrix arrangement, and may be arranged along an arc, for example. The signal lines and control lines may be formed accordingly.

[0027] [Schematic Configuration Example of Pixel Array Section] Figure 5 is a diagram showing a schematic configuration example of the pixel array section 20. In the pixel array section 20, signal lines SIG are wired for each pixel column along the column direction CD with respect to the arrangement of pixels (pixel circuits) PIX. Furthermore, first control lines (control lines WSL, DSL, AZSL) are wired for each pixel row along the row direction RD with respect to the arrangement of pixels PIX. Note that the pixel arrangement shown in Figure 5 is merely an example for the purpose of simplifying the illustration.

[0028] Each signal line SIG is connected to an output terminal of a corresponding column of the horizontal analog circuit 32. Each control line WSL, DSL, AZSL is connected to an output terminal of a corresponding row of the vertical analog circuit 42.

[0029] The horizontal analog circuit 32 supplies pixel signals corresponding to the display image to each signal line SIG based on image data supplied from the timing controller 11. The horizontal analog circuit 32 selectively outputs, as pixel signals, for example, a signal voltage Vsig corresponding to the luminance of the display image and various reference voltages that serve as references for the signal voltage Vsig.

[0030] The vertical analog circuit 42 supplies control signals (control signals WS, DS, AZ) that control driving based on pixel signals to each control line WSL, DSL, AZSL. The control signal WS is a control signal that scans each of the multiple pixels, the control signal DS is a control signal that controls light emission / extinction, and the control signal AZ is a control signal that controls so as not to emit light during the extinction period. Specifically, when writing pixel signals to each pixel PIX in the pixel array section 20, the vertical analog circuit 42 sequentially supplies control signals WS0, WS1, ... to each control line WSL, thereby scanning each pixel PIX in the pixel array section 20 row by row (line sequential scanning). Furthermore, the vertical analog circuit 42 controls light emission / extinction of the pixels PIX by supplying control signals DS0, DS1, ... to the control line DSL in synchronization with the scanning. Furthermore, the vertical analog circuit 42 controls the pixels PIX so that they do not emit light during the extinction period by supplying control signals AZ0, AZ1, . . . to the control lines AZSL in synchronization with the scanning.

[0031] [Configuration Example of Pixel PIX] Figure 6 shows an example configuration of pixel PIX. Pixel PIX has a capacitor C01, transistors MN02 and MN03, and a light-emitting element EL. Transistors MN02 and MN03 are N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The gate of transistor MN02 is connected to a control line WSL, the drain is connected to a signal line SIG, and the source is connected to the gate of transistor MN03 and capacitor C01. One end of capacitor C01 is connected to the source of transistor MN02 and the gate of transistor MN03, and the other end is connected to the source of transistor MN03 and the anode of light-emitting element EL. The gate of transistor MN03 is connected to the source of transistor MN02 and one end of capacitor C01, the drain is connected to the power supply line VCCP, and the source is connected to the other end of capacitor C01 and the anode of light-emitting element EL. The anode of the light-emitting element EL is connected to the source of the transistor MN03 and the other end of the capacitor C01, and the cathode is connected to the power supply line Vcath. The voltage of the power supply line VCCP is appropriately switched between a first voltage and a second voltage lower than the first voltage.

[0032] With this configuration, in pixel PIX, when transistor MN02 is turned on, the voltage across capacitor C01 is set based on the pixel signal supplied from signal line SIG. During a period when the voltage of power supply line VCCP is at a first voltage, transistor MN03 passes a current corresponding to the voltage across capacitor C01 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN03. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. During a period when the voltage of power supply line VCCP is at a second voltage, light-emitting element EL is turned off.

[0033] [Configuration Example of Signal Line Driver] Next, a configuration example of the signal line driver 30 according to this embodiment will be described with reference to Fig. 7. The signal line driver 30 according to this embodiment can be configured, for example, by a RAMPDAC circuit that uses a ramp waveform analog signal to generate pixel signals to be output to each signal line SIG.

[0034] The horizontal logic circuit 31 of the signal line driving section 30 has a shift register (S / R) section 51 , a 1ST latch section 52 , a 2ND latch section 53 , a comparator section 54 , and a PWM generating section 55 .

[0035] The shift register unit 51 is composed of a group of shift registers (not shown) whose number corresponds to the number of pixels in the row direction, and outputs shift pulses (sampling pulses) sequentially from each transfer stage in synchronization with a horizontal clock pulse HCK (not shown).

[0036] The 1ST latch unit 52 is composed of a plurality of 1ST latch circuits 52A, and sequentially samples and latches the image data DATA in response to sampling pulses LATCLK[0], [1], ... output by each shift register. A plurality of 1ST latch circuits 52A is provided for each signal line.

[0037] The second latch unit 53 is made up of a plurality of second latch circuits 53A, and line-sequentializes the latched data of the first latch circuit 52A in response to a line pulse LINECLK. A plurality of second latch circuits 53A are provided for each signal line.

[0038] The comparator section 54 is composed of a plurality of digital comparators 54A. Each digital comparator 54A compares the latch data of each 2ND latch circuit 53A with the output from the synchronous counter 61 and outputs the comparison result. A plurality of digital comparators 54A is provided for each signal line.

[0039] The PWM generation unit 55 is composed of a plurality of PWM generation circuits 55A. Each PWM generation circuit 55A generates a PWM signal corresponding to the gradation data of each pixel in response to the start pulse RAMPST input from the timing controller 11. As a result, the level shifter unit 56 converts signals of 8 bits, 10 bits, 12 bits, etc. into signals having a width corresponding to the data. A plurality of PWM generation circuits 55A is provided for each signal line.

[0040] The horizontal analog circuit 32 of the signal line driver 30 includes a level shifter 56 , a plurality of switch sections 57 , and a lamp driver circuit 65 .

[0041] The level shifter unit 56 is made up of a plurality of level shifter circuits 56A, and converts the levels of the PWM signals converted by the PWM generating circuits 55A into drive level signals. The plurality of level shifter circuits 56A are provided for each signal line.

[0042] The synchronous counter 61 in the figure receives the main clock signal MCLK from the timing controller 11 via a DLL (Delay Locked Loop) circuit 62. The synchronous counter 61 counts down or up in synchronization with the main clock signal MCLK and outputs a signal representing the count result.

[0043] The ramp drive circuit 65 includes a voltage follower circuit 66, which is an example of a buffer unit, and a RAMPDAC unit 67, which is an example of a ramp wave output unit. The RAMPDAC unit 67 is configured, for example, with a DAC and also serves as a gamma correction circuit. The RAMPDAC unit 67 generates and outputs, for example, a ramp wave (analog voltage) whose potential fluctuates uniformly. The ramp drive circuit 65 outputs the ramp wave generated by the RAMPDAC 67 to the switch unit 57 via the voltage follower circuit 66.

[0044] The switch section 57 is composed of a plurality of switch elements 57A, and each switch element 57A samples the ramp wave by turning on (closing) at a timing corresponding to the gradation to be written to the pixel PIX in accordance with the output voltage of each level shifter circuit 56A, and determines the signal voltage to be written to the pixel PIX. A plurality of switch elements 57A is provided for each signal line.

[0045] Next, an example of the operation of the lamp drive circuit 65 will be briefly described with reference to Fig. 8. Fig. 8 shows the ramp voltage RW output by the RAMPDAC unit 67 of the lamp drive circuit 65. The RAMPDAC unit 67 outputs a ramp voltage RW having a gradation ranging from 0 gradation to MAX gradation. The MAX gradation is a gradation corresponding to 8 bits, 10 bits, etc.

[0046] The PWM generation unit 55 supplies a PWM signal having a width corresponding to the data, i.e., a PWM width corresponding to the gradation, to the level shifter unit 56. Each level shifter circuit 56A converts the level of the PWM signal converted by the PWM generation circuit 55A into a drive level signal. Each switch element 57A samples a ramp waveform by turning on (closed) at a timing corresponding to the gradation to be written to the pixel PIX according to the output voltage of the corresponding level shifter circuit 56A. The voltage of the sampled gradation is determined as the signal voltage to be written to the pixel PIX connected to the signal line SIG that is turned on. That is, as shown in FIG. 8 , the ramp voltage RW is sampled in accordance with the PWM width corresponding to the gradation, and a voltage corresponding to the gradation is selected. This voltage is written to the pixel PIX connected to the signal line that turned on the switch element 57A.

[0047] Note that the ramp voltage RW shown in FIG. 8 has a voltage level that decreases linearly for each horizontal line, but the present technology can also be applied to a ramp voltage whose voltage level increases linearly, a triangular waveform ramp voltage, or a ramp voltage whose voltage level changes nonlinearly (irregularly).

[0048] [Specific Configuration Example of Pixel Array Section] Next, a specific configuration example of the pixel array section 20 according to the first embodiment and its peripheral components will be described with reference to FIG.

[0049] As shown in Fig. 9, the display device 100A according to the first embodiment has a plurality of lamp drive circuits. For example, the display device 100A has a first lamp drive circuit 65A and a second lamp drive circuit 65B. The first lamp drive circuit 65A and the second lamp drive circuit 65B have the same configuration and function as the lamp drive circuit 65 described above. The first lamp drive circuit 65A and the second lamp drive circuit 65B are aligned along the upper outer edge 21 of the pixel array unit 20 when viewed facing the paper surface of Fig. 9.

[0050] The first lamp driving circuit 65A includes a first voltage follower circuit 66A and a first RAMPDAC unit 67A. The first RAMPDAC unit 67A outputs a first ramp voltage (an example of a first analog voltage), which is an analog voltage. In this embodiment, the first lamp driving circuit 65A corresponds to an example of a first output source. A plurality of first signal lines SIGa are connected to the first voltage follower circuit 66A. Each of the first signal lines SIGa extends in the column direction CD. The plurality of first signal lines SIGa are connected to the first voltage follower circuit 66A via a switch element 57C (a component corresponding to the switch element 57A described above) provided for each signal line. A first pixel Pa is connected to each of the first signal lines SIGa. The first pixel Pa has, for example, a configuration similar to that of the pixel PIX (see FIG. 6 ).

[0051] The second ramp drive circuit 65B includes a second voltage follower circuit 66B and a second RAMPDAC unit 67B. The second RAMPDAC unit 67B outputs a second ramp voltage (an example of a second analog voltage), which is an analog voltage. In this embodiment, the second ramp drive circuit 65B corresponds to an example of a second output source. Ideally, the first ramp voltage output by the first RAMPDAC unit 67A and the second ramp voltage output by the second RAMPDAC unit 67B have the same waveform. However, as described above, they may have different waveforms depending on DAC characteristic variations and the like. Multiple second signal lines SIGb are connected to the second voltage follower circuit 66B. Each second signal line SIGb extends in the column direction CD. The multiple second signal lines SIGb are connected to the second voltage follower circuit 66B via a switch element 57D (a component corresponding to the switch element 57A described above) provided for each signal line. A second pixel Pb is connected to each second signal line SIGb. The second pixel Pb has, for example, a configuration similar to that of the pixel PIX (see FIG. 6 ). In this manner, the first signal line SIGa, the first pixel Pa connected to the first signal line SIGa, the second signal line SIGb, and the second pixel Pb connected to the second signal line SIGb are arranged in the pixel array unit 20.

[0052] The pixel array section 20 also has a first region AR1 in which the first signal lines SIGa are continuously arranged, a second region AR2 in which the second signal lines SIGb are continuously arranged, and a third region AR3 formed between the first region AR1 and the second region AR2 and in which the first signal lines SIGa and the second signal lines SIGb are arranged approximately alternately.

[0053] Here, in this specification, "continuously arranged" means that two or more signal lines connected to the same output source are continuously arranged along a predetermined direction (the row direction RD in this embodiment). Furthermore, in this specification, "the first signal lines SIGa and the second signal lines SIGb are arranged substantially alternately" means that the first signal lines SIGa and the second signal lines SIGb are mixed in the third region AR3 and are repeatedly arranged according to a predetermined rule. This also applies to other embodiments.

[0054] For example, in this embodiment, the first signal lines SIGa and the second signal lines SIGb are arranged alternately, that is, alternately one by one, in the third region AR3.

[0055] The number of pixels arranged in the third region AR3 (the total number of pixels including the number of first pixels Pa arranged in the third region AR3 and the number of second pixels Pb arranged in the third region AR3) is not particularly limited, but from the viewpoint of effectively achieving the effects of the present technology, it is preferable that the number be between five pixels and several tens of pixels or more.

[0056] In addition, a distributed driving method using multiple lamp driving circuits can use a larger number of lamp driving circuits. The multiple lamp driving circuits 65, including the first lamp driving circuit 65A and the second lamp driving circuit 65B, are arranged, for example, along the upper outer edge 21 of the pixel array unit 20, as shown in FIG. 10 . In this case, as described above, the first region AR1, the second region AR2, and the third region AR3 are defined, so that the pixel array unit 20 has a plurality of first regions AR1, a plurality of second regions AR2, and a plurality of third regions AR3. In this embodiment, the multiple first regions AR1, the multiple second regions AR2, and the multiple third regions AR3 are arranged alternately (non-contiguous) along the row direction RD, which is the horizontal direction of the pixel array unit 20, so that the third region AR3 is located between the first region AR1 and the second region AR2.

[0057] [Effects Obtained by the Present Embodiment] In the present embodiment, by providing a third region AR3 in the pixel array unit 20 in which the first signal line SIGa and the second signal line SIGb overlap, the boundary between the first region AR1 in which the first signal line SIGa is disposed and the second region AR2 in which the second signal line SIGb is disposed can be blurred. This makes it possible to reduce the visibility of band-like lines resulting from the brightness difference, thereby improving the image quality of the display device 100A. Furthermore, since only the signal line arrangement needs to be changed and no new logic circuits or the like need to be added, the image quality of the display device 100A can be improved without increasing the circuit size.

[0058] Second Embodiment Next, a second embodiment will be described. In the description of the second embodiment, the same or similar components as those in the above description will be denoted by the same reference numerals, and duplicated descriptions will be omitted as appropriate. Furthermore, unless otherwise specified, the matters described in the first embodiment can be applied to the second embodiment.

[0059] 11 is a diagram illustrating an example of the configuration of a pixel array unit 20 of a display device (display device 100B) according to a second embodiment. Similar to the pixel array unit 20 of the display device 100A, the pixel array unit 20 of the display device 100B has a first region AR1, a second region AR2, and a third region AR3. In the first embodiment, the first signal lines SIGa and the second signal lines SIGb were alternately arranged in the third region AR3. However, in this embodiment, the first signal lines SIGa and the second signal lines SIGb are arranged in the third region AR3 so as to have a gradient. Here, "arranged so as to have a gradient" means that, for example, when viewed in each of a plurality of regions virtually defined in the third region AR3, the first signal lines SIGa and the second signal lines SIGb are arranged so that the ratio of the number of first signal lines SIGa or second signal lines SIGb to the total number of signal lines in that region gradually decreases or gradually increases.

[0060] For example, in the third region AR3 in FIG. 11 , let us assume that three regions are hypothetically defined: a region AR3a including three signal lines on the left side of the drawing, a region AR3b including two central signal lines, and a region AR3c including three signal lines on the right side of the drawing. Here, in region AR3a, there are three signal lines (two first signal lines SIGa and one second signal line SIGb), but there are two first signal lines SIGa. That is, the ratio of the number of first signal lines SIGa to the number of signal lines in region AR3a is 2 / 3. Also, in region AR3b, there are two signal lines (one first signal line SIGa and one second signal line SIGb), but there is only one first signal line SIGa. That is, the ratio of the number of first signal lines SIGa to the number of signal lines in region AR3b is 1 / 2. In the area AR3c, the number of signal lines is three (one first signal line SIGa and two second signal lines SIGb), but the number of first signal lines SIGa is one. That is, the ratio of the number of first signal lines SIGa to the total number of signal lines in the area AR3c is 1 / 3. In this way, the first signal lines SIGa and the second signal lines SIGb are arranged in the third area AR3 so that the ratio of the number of first signal lines SIGa to the total number of signal lines in each area virtually set in the third area AR3 gradually decreases from 2 / 3, to 1 / 2, to 1 / 3.

[0061] Alternatively, the first signal lines SIGa and the second signal lines SIGb may be arranged so that the ratio of the number of the second signal lines SIGb to the number of the signal lines in each virtually set region gradually decreases or gradually increases, instead of the first signal lines SIGa. Furthermore, the change in the ratio of the number of the first signal lines SIGa or the second signal lines SIGb to the number of the signal lines in each region may be a change from the right to the left of the pixel array unit 20, or a change from the left to the right of the pixel array unit 20.

[0062] The configuration of the pixel array unit 20 according to this embodiment also provides the same effects as those of the first embodiment. Furthermore, since the first signal lines SIGa and the second signal lines SIGb are arranged to have a gradient, the change in luminance in the third region AR3 is smoothed. This effectively prevents band-like lines from being visible.

[0063] <Third Embodiment> Next, a third embodiment will be described. In the description of the third embodiment, the same or similar components as those in the above description will be denoted by the same reference numerals, and duplicate descriptions will be omitted as appropriate. Furthermore, unless otherwise specified, matters described in other embodiments can be applied to the third embodiment.

[0064] 12 is a diagram illustrating the pixel array unit 20 and its peripheral components of a display device (display device 100C) according to a third embodiment. As shown in FIG. 12 , the display device 100C according to this embodiment, like the display device 100A, has a first lamp drive circuit 65A and a second lamp drive circuit 65B. In this embodiment, the first lamp drive circuit 65A is disposed near the upper outer edge 21 of the pixel array unit 20, and the second lamp drive circuit 65B is disposed near the lower outer edge 22 of the pixel array unit 20. For example, the first lamp drive circuit 65A and the second lamp drive circuit 65B are disposed so as to substantially face each other across the pixel array unit 20.

[0065] As described above, the first lamp drive circuit 65A includes a first voltage follower circuit 66A and a first RAMPDAC unit 67A. The first RAMPDAC unit 67A outputs a first ramp voltage, which is an analog voltage. A plurality of first signal lines SIGa are connected to the first voltage follower circuit 66A. Each first signal line SIGa extends in the column direction CD. Specifically, each first signal line SIGa extends from near the upper outer edge 21 to near the center of the pixel array unit 20. The plurality of first signal lines SIGa are connected to the first voltage follower circuit 66A via switch elements 57C provided for each signal line. A first pixel Pa is connected to each first signal line SIGa. The first pixel Pa has, for example, a configuration similar to that of the pixel PIX (see FIG. 6 ).

[0066] As described above, the second ramp drive circuit 65B includes a second voltage follower circuit 66B and a second RAMPDAC unit 67B. The second RAMPDAC unit 67B outputs a second ramp voltage, which is an analog voltage. A plurality of second signal lines SIGb are connected to the second voltage follower circuit 66B. Each second signal line SIGb extends in the column direction CD. Specifically, each second signal line SIGb extends from near the lower outer edge 22 to near the center of the pixel array unit 20. For example, each second signal line SIGb is arranged between two first signal lines SIGa without overlapping with the first signal lines SIGa. The plurality of second signal lines SIGb are connected to the second voltage follower circuit 66B via a switch element 57D provided for each signal line. A second pixel Pb is connected to each second signal line SIGb. The second pixel Pb has, for example, the same configuration as the pixel PIX (see FIG. 6).

[0067] The pixel array unit 20 of the display device 100C also includes a first region AR1 in which the first signal lines SIGa are continuously arranged, a second region AR2 in which the second signal lines SIGb are continuously arranged, and a third region AR3 formed between the first region AR1 and the second region AR2 and in which the first signal lines SIGa and the second signal lines SIGb are substantially alternately arranged. The first region AR1 is formed on the upper side of the pixel array unit 20, the second region AR2 is formed on the lower side of the pixel array unit 20, and the third region AR3 is formed near the center of the pixel array unit 20 between the first region AR1 and the second region AR2.

[0068] In the first region AR1, a portion of the first signal line SIGa is continuously arranged. For example, a portion of the first signal line SIGa connected to the switch element 57C is arranged in the first region AR1. In addition, in the second region AR2, a portion of the second signal line SIGb is continuously arranged. For example, a portion of the second signal line SIGb connected to the switch element 57D is arranged in the second region AR2. In addition, in the third region AR3, the vicinity of the tip of the first signal line SIGa and the vicinity of the tip of the second signal line SIGb are arranged alternately, i.e., alternately one by one. In this way, the first signal line SIGa and the second signal line SIGb arranged in the first region AR1, the second region AR2, and the third region AR3 may be only a portion of each signal line, not necessarily the entirety of each signal line.

[0069] In addition, a distributed driving method using multiple lamp driving circuits can use a larger number of lamp driving circuits. For example, multiple lamp driving circuits 65 including a first lamp driving circuit 65A and a second lamp driving circuit 65B are arranged along the upper outer edge 21 and the lower outer edge 22 of the pixel array unit 20, as shown in Fig. 13. In this case, the pixel array unit 20 has a first region AR1, a third region AR3, and a second region AR2 that are arranged alternately (not consecutively) along the column direction CD, which is the vertical direction of the pixel array unit 20.

[0070] In the case where lamp drive circuits are provided in each of the upper outer edge portion 21 and the lower outer edge portion 22 of the pixel array unit 20 as in the present embodiment, if the third region AR3 is not provided, there is a risk that a belt-shaped line extending in the row direction RD will be visible near the center of the pixel array unit 20 (at the boundary between the first region AR1 and the second region AR2). In the present embodiment, the third region AR3 is provided, and therefore, for the same reason as in the first embodiment, it is possible to prevent the belt-shaped line from being visible.

[0071] In order to prevent the band-like lines from being visible without providing the third region AR3, it is necessary to alternately arrange the first signal lines SIGa and the second signal lines SIGb extending in the column direction CD across the entire pixel array section 20, as schematically shown in Figure 14. In such a configuration, the area available for each signal line is halved, which doubles the parasitic resistance. Furthermore, the layout density of the signal lines is doubled, which doubles the parasitic capacitance.

[0072] In contrast, as shown in FIG. 15 , in this embodiment, a third region AR3 is provided near the center of the pixel array section 20. The first signal lines SIGa and the second signal lines SIGb are alternately arranged only in the third region AR3. In the first region AR1 and the second region AR2, which are regions other than the third region AR3, only one of the first signal lines SIGa and the second signal lines SIGb is arranged. That is, compared to the configuration shown in FIG. 14 , the number of signal lines arranged in the first region AR1 and the second region AR2 can be halved. This allows for approximately half the parasitic resistance and parasitic capacitance compared to the configuration shown in FIG. 13 . Furthermore, because the size of the third region AR3 does not need to be that large, the proportion of the pixel array section 20 occupied by the first region AR1 and the second region AR2 is relatively large. Therefore, the parasitic resistance and parasitic capacitance can be significantly reduced compared to the configuration shown in FIG. 14 .

[0073] In this embodiment, similarly to the second embodiment, the first signal lines SIGa and the second signal lines SIGb may be arranged in the third region AR3 so as to have a gradient.

[0074] <Fourth Embodiment> Next, a fourth embodiment will be described. In the description of the fourth embodiment, the same or similar components as those in the above description will be denoted by the same reference numerals, and duplicate descriptions will be omitted as appropriate. Furthermore, unless otherwise specified, matters described in other embodiments can be applied to the fourth embodiment.

[0075] In the fourth embodiment, lamp drive circuits corresponding to different colors are provided. The different colors include, for example, red (R), green (G), and blue (B). FIG. 16 is a diagram showing a typical configuration example of a display device having lamp drive circuits corresponding to different colors. As an example, a plurality of lamp drive circuits for driving green pixels are arranged along an upper outer edge portion 21. Furthermore, a plurality of lamp drive circuits for driving red pixels and blue pixels are arranged along a lower outer edge portion 22.

[0076] 16 shows two lamp drive circuits, lamp drive circuit 65Ga and lamp drive circuit 65Gb, as a plurality of lamp drive circuits that drive green pixels. Also shown are lamp drive circuit 65RBa and lamp drive circuit 65RBb as a plurality of lamp drive circuits that drive red and blue pixels. In this embodiment, for example, lamp drive circuit 65Ga corresponds to an example of a first output source, lamp drive circuit 65Gb corresponds to an example of a second output source, lamp drive circuit 65RBa corresponds to an example of a third output source, and lamp drive circuit 65RBb corresponds to an example of a fourth output source.

[0077] Each of the lamp drive circuit 65Ga, the lamp drive circuit 65Gb, the lamp drive circuit 65RBa, and the lamp drive circuit 65RBb has the same configuration and function as the lamp drive circuit 65 described above.

[0078] The lamp drive circuit 65Ga includes a voltage follower circuit 66Ga and a RAMPDAC unit 67Ga. The RAMPDAC unit 67Ga outputs a ramp voltage (an example of a first analog voltage in this embodiment), which is an analog voltage. A plurality of signal lines SIGga (an example of a first signal line in this embodiment) are connected to the voltage follower circuit 66Ga. Each signal line SIGga extends in the column direction CD. The plurality of signal lines SIGga are connected to the voltage follower circuit 66Ga via a switch element 57Ga (a component corresponding to the switch element 57A described above) provided for each signal line. A green (an example of a first color type) pixel PGa (an example of a first pixel in this embodiment) is connected to each signal line SIGga. The pixel PGa has, for example, a configuration similar to that of the pixel PIX (see FIG. 6 ).

[0079] The lamp drive circuit 65Gb includes a voltage follower circuit 66Gb and a RAMPDAC unit 67Gb. The RAMPDAC unit 67Gb outputs a ramp voltage (an example of a second analog voltage in this embodiment), which is an analog voltage. A plurality of signal lines SIGgb (an example of a second signal line in this embodiment) are connected to the voltage follower circuit 66Gb. Each signal line SIGgb extends in the column direction CD. The plurality of signal lines SIGgb are connected to the voltage follower circuit 66Gb via a switch element 57Gb (a component corresponding to the switch element 57A described above) provided for each signal line. A green pixel PGb (an example of a second pixel in this embodiment) is connected to each signal line SIGgb. The pixel PGb has, for example, a configuration similar to that of the pixel PIX (see FIG. 6 ).

[0080] The ramp driver circuit 65RBa includes a voltage follower circuit 66RBa and a RAMPDAC unit 67RBa. The RAMPDAC unit 67RBa outputs a ramp voltage (an example of a third analog voltage in this embodiment), which is an analog voltage. A plurality of signal lines (an example of a third signal line in this embodiment) are connected to the voltage follower circuit 66RBa. Each signal line extends in the column direction CD. The plurality of signal lines includes, for example, a pair of signal lines SIGr (an example of a fifth signal line in this embodiment) and SIGba (an example of a sixth signal line in this embodiment). Note that in FIG. 16 , the signal line SIGba is shown slightly thinner than the signal line SIGr to facilitate understanding of the illustration.

[0081] The signal lines SIGr and SIGba are connected to the voltage follower circuit 66RBa, for example, so that the signal lines SIGr and SIGba are arranged alternately. Specifically, the multiple signal lines SIGr are connected to the voltage follower circuit 66RBa via switch elements 57Ra (components corresponding to the switch elements 57A described above) provided for each signal line. Each signal line SIGr is connected to a pixel of a different color type from the pixels PGa and PGb, for example, a red pixel PRa (an example of a third pixel in this embodiment) (an example of a second color type). The pixel PRa has a configuration similar to that of the pixel PIX (see FIG. 6 ). The multiple signal lines SIGba are also connected to the voltage follower circuit 66RBa via switch elements 57Ba (components corresponding to the switch elements 57A described above) provided for each signal line. Each signal line SIGba is connected to a pixel PGa, a pixel PGb, and a pixel of a different color type from pixel PRa, such as a blue pixel PBa (an example of a third color type) (an example of a fourth pixel in this embodiment). Pixel PBa has, for example, a configuration similar to that of pixel PIX (see FIG. 6).

[0082] The ramp driver circuit 65RBb includes a voltage follower circuit 66RBb and a RAMPDAC unit 67RBb. The RAMPDAC unit 67RBb outputs a ramp voltage (an example of a fourth analog voltage in this embodiment), which is an analog voltage. A plurality of signal lines (an example of a fourth signal line in this embodiment) are connected to the voltage follower circuit 66RBb. Each signal line extends in the column direction CD. The plurality of signal lines includes, for example, a pair of signal lines SIGrb (an example of a seventh signal line in this embodiment) and SIGbb (an example of an eighth signal line in this embodiment). In FIG. 16 , the signal line SIGbb is shown slightly thinner than the signal line SIGrb to facilitate understanding of the illustration.

[0083] The signal lines SIGrb and SIGbb are connected to the voltage follower circuit 66RBb, for example, so that the signal lines SIGrb and SIGbb are arranged alternately. Specifically, the multiple signal lines SIGrb are connected to the voltage follower circuit 66RBb via switch elements 57Rb (components corresponding to the switch elements 57A described above) provided for each signal line. Each signal line SIGrb is connected to a pixel PGb or a pixel of a different color from pixel PGb, for example, a red pixel PRb (an example of the fifth pixel in this embodiment). The pixel PRb has a configuration similar to that of pixel PIX (see FIG. 6 ), for example. The multiple signal lines SIGbb are also connected to the voltage follower circuit 66RBb via switch elements 57Bb (components corresponding to the switch elements 57A described above) provided for each signal line. Each signal line SIGbb is connected to a pixel PGb, a pixel PGb, and a pixel PRb having a different color, such as a blue pixel PBb (an example of the sixth pixel in this embodiment). The pixel PBb has a configuration similar to that of the pixel PIX (see FIG. 6).

[0084] In this way, the present technology can also be applied to a display device in which a lamp drive circuit is provided for each color type. Fig. 17 is a diagram for explaining an example configuration of a pixel array unit 20 included in a display device (display device 100D) according to this embodiment. Fig. 18 is a diagram illustrating, from the components shown in Fig. 17, a lamp drive circuit 65Ga, a signal line connected to the lamp drive circuit 65Ga, a lamp drive circuit 65Gb, and a signal line connected to the lamp drive circuit 65Gb. Fig. 19 is a diagram illustrating, from the components shown in Fig. 17, a lamp drive circuit 65RBa, a signal line connected to the lamp drive circuit 65RBa, a lamp drive circuit 65RBb, and a signal line connected to the lamp drive circuit 65RBb.

[0085] 18 , the pixel array unit 20 has a first region AR1 in which the signal lines SIGga are continuously arranged, a second region AR2 in which the signal lines SIGgb are continuously arranged, and a third region AR3 that is arranged between the first region AR1 and the second region AR2 and in which the signal lines SIGga and SIGgb are arranged substantially alternately. In this embodiment, the signal lines SIGga and SIGgb are arranged alternately in the third region AR3, but as described in the first embodiment, the arrangement of the signal lines is not limited to the arrangement according to this example as long as they are arranged substantially alternately.

[0086] As shown in FIG. 19 , the pixel array unit 20 includes a fourth region AR4 in which pairs of signal lines SIGr and SIGba are continuously arranged, and a fifth region AR5 in which pairs of signal lines SIGrb and SIGbb are continuously arranged. The pixel array unit 20 also includes a sixth region AR6 located between the fourth region AR4 and the fifth region AR5. The sixth region AR6 is a region in which the signal lines SIGr, SIGba, SIGrb, and SIGbb are substantially alternately arranged. For example, in the sixth region AR6, the pair of signal lines SIGr and SIGba and the pair of signal lines SIGrb and SIGbb are alternately arranged along the row direction RD. However, the arrangement of the signal lines is not limited to this. For example, the signal lines SIGr a, SIGbb, SIGrb, and SIGba may be arranged alternately.

[0087] When the display device 100D is viewed as a whole, in the pixel array unit 20, the first region AR1 and the fourth region AR4 overlap, the second region AR2 and the fifth region AR5 overlap, and the third region AR3 and the sixth region AR6 overlap therebetween so that the signal lines do not overlap. Specifically, as shown in Fig. 17 , in the overlapping region of the first region AR1 and the fourth region AR4, a set of signal lines SIGga, SIGr a, and SIGba is repeatedly arranged. In the overlapping region of the second region AR2 and the fifth region AR5, a set of signal lines SIGgb, SIGrb, and SIGbb is repeatedly arranged. In the region where the third region AR3 and the sixth region AR6 overlap, a set of signal lines SIGga, SIGra, and SIGba and a set of signal lines SIGgb, SIGrb, and SIGbb are repeatedly arranged.

[0088] The configuration of the pixel array unit 20 according to this embodiment also achieves the same effects as those of the first embodiment. Furthermore, when lamp drive circuits of different colors are used, as in this embodiment, there is a risk that a user will perceive a difference in brightness due to variations in the output of the lamp drive circuit as a color difference. However, in this embodiment, by providing the third region AR3 and the sixth region AR6, the difference in brightness due to variations in the output of the lamp drive circuit can be alleviated. This prevents a user from perceiving a difference in brightness as a color difference.

[0089] Fifth Embodiment Next, a fifth embodiment will be described. In the description of the fifth embodiment, the same or similar components as those in the above description will be denoted by the same reference numerals, and duplicate descriptions will be omitted as appropriate. Furthermore, unless otherwise specified, matters described in other embodiments can be applied to the fifth embodiment.

[0090] FIG. 20 is a diagram for explaining an example of the configuration of the pixel array unit 20 of a display device (display device 100E) according to this embodiment. Like the display device 100D, the display device 100E according to this embodiment is also an example in which a lamp drive circuit is provided for each color type. FIG. 21 is a diagram illustrating, from the components shown in FIG. 20, a lamp drive circuit 65Ga, a signal line connected to the lamp drive circuit 65Ga, a lamp drive circuit 65Gb, and a signal line connected to the lamp drive circuit 65Gb. FIG. 22 is a diagram illustrating, from the components shown in FIG. 21, a lamp drive circuit 65RBa, a signal line connected to the lamp drive circuit 65RBa, a lamp drive circuit 65RBb, and a signal line connected to the lamp drive circuit 65RBb.

[0091] 21 , the pixel array unit 20 of the display device 100E includes a first region AR1 in which the signal lines SIGga are continuously arranged, a second region AR2 in which the signal lines SIGgb are continuously arranged, and a third region AR3 disposed between the first region AR1 and the second region AR2 and in which the signal lines SIGga and SIGgb are substantially alternately arranged. In this respect, the configuration of the pixel array unit 20 of the display device 100E is similar to that of the pixel array unit 20 of the display device 100D. Note that, in this embodiment, the signal lines SIGga and SIGgb are alternately arranged in the third region AR3. However, as described in the first embodiment, the arrangement of the signal lines is not limited to the arrangement according to this example, as long as they are substantially alternately arranged.

[0092] 22 , the pixel array unit 20 has a fourth region AR4 in which pairs of signal lines SIGr and SIGba are continuously arranged, and a fifth region AR5 in which pairs of signal lines SIGrb and SIGbb are continuously arranged. However, the pixel array unit 20 does not have a region corresponding to the sixth region AR6 described above, in other words, a region in which the signal lines SIGr, SIGba, SIGrb, and SIGbb are substantially alternately arranged. This is what distinguishes the display device 100E from the display device 100D described above.

[0093] When viewing the display device 100E as a whole, in the pixel array section 20, the first region AR1 and the fourth region AR4 overlap, and the second region AR2 and the fifth region AR5 overlap so that the signal lines do not overlap. Between them, the third region AR3 and the fourth region AR4 partially overlap, and the third region AR3 and the fifth region AR5 partially overlap. Specifically, as shown in FIG. 20 , in the overlapping region between the first region AR1 and the fourth region AR4, a set of signal lines SIGga, SIGr a, and SIGba is repeatedly arranged. In the overlapping region between the second region AR2 and the fifth region AR5, a set of signal lines SIGgb, SIGrb, and SIGbb is repeatedly arranged. In the left region between the two regions, a set of signal lines SIGgb, SIGra, and SIGba and a set of signal lines SIGga, SIGra, and SIGba are alternately arranged, while in the right region, a set of signal lines SIGga, SIGrb, and SIGbb and a set of signal lines SIGgb, SIGrb, and SIGbb are alternately arranged.

[0094] In this embodiment, as described above, an overlapping region is set only for signal lines driving specific color pixels derived from different lamp drive circuits 65, specifically, green pixels, which have a relatively higher luminosity factor than red or blue. The reason for setting an overlapping region for signal lines driving only green pixels is that green has a higher luminosity factor than red or blue, making band-like lines more visible. In this embodiment, a third region AR3 is provided in which signal lines driving green pixels overlap, thereby preventing the band-like lines from being visible to the user. Furthermore, since there is no need to provide an overlapping region for signal lines driving red and blue, the manufacturing process of the display device 100E may be relatively simplified in some cases.

[0095] <Application Examples> (Electronic Device) The display device according to the above-described embodiment to which the present technology is applied may be provided in various electronic devices. Application examples of electronic devices include the following.

[0096] 23 shows an example of the appearance of a head-mounted display 110. The head-mounted display 110 has, for example, ear hooks 112 for wearing on the user's head on both sides of a glasses-shaped display unit 111. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 110.

[0097] (Application Example 2) FIG. 24 shows an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a see-through head-mounted display having a main body 121, an arm 122, and a lens barrel 123. This head-mounted display 120 is attached to eyeglasses 128. The main body 121 has a control board and a display unit for controlling the operation of the head-mounted display 120. The display unit emits image light of a display image. The arm 122 connects the main body 121 to the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light supplied from the main body 121 via the arm 122 toward the user's eyes via lenses 129 of the eyeglasses 128. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 120.

[0098] The head-mounted display 120 is a so-called light guide plate type head-mounted display, but is not limited to this and may be, for example, a so-called birdbath type head-mounted display. The birdbath type head-mounted display includes, for example, a beam splitter and a partially transparent mirror. The beam splitter outputs light encoded with image information toward the mirror, and the mirror reflects the light toward the user's eyes. Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.

[0099] (Application Example 3) Figures 25A and 25B show an example of the appearance of a digital still camera 138, with Figure 25A showing a front view and Figure 25B showing a rear view. This digital still camera 138 is an interchangeable lens single-lens reflex camera and has a camera main body 131, a photographing lens unit 132, a grip unit 133, a monitor 134, and an electronic viewfinder 135. The photographing lens unit 132 is an interchangeable lens unit and is provided near the center of the front of the camera main body 311. The grip unit 133 is provided on the left side of the front of the camera main body 311, and the photographer holds the grip unit 133. The monitor 134 is provided to the left of the center of the back of the camera main body 131. The electronic viewfinder 135 is provided above the monitor 134 on the back of the camera main body 131. By looking through this electronic viewfinder 135, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 132 and determine the composition. The techniques according to the above-described embodiments can be applied to the electronic viewfinder 135.

[0100] 26 shows an example of the appearance of a television device 140. The television device 140 has an image display screen unit 141 including a front panel 142 and a filter glass 143. The techniques according to the above-described embodiments and the like can be applied to this image display screen unit 141.

[0101] 27 shows an example of the appearance of a smartphone 150. The smartphone 150 has a display unit 151 that displays various information and an operation unit 152 that includes buttons and the like that accept operation inputs from a user. The techniques according to the above-described embodiments and the like can be applied to this display unit 151.

[0102] Application Example 6 The display device according to the above embodiment may be provided in various displays provided in vehicles.

[0103] 28A and 28B are diagrams showing an example of the internal configuration of a vehicle 200 equipped with various displays. Specifically, Fig. 28A is a diagram showing an example of the internal appearance of the vehicle 200 from the rear to the front of the vehicle 200, and Fig. 28B is a diagram showing an example of the internal appearance of the vehicle 200 from diagonally rear to diagonally front of the vehicle 200.

[0104] The vehicle 200 includes a center display 201, a console display 202, a head-up display 203, a digital rearview mirror 204, a steering wheel display 205, and a rear entertainment display 206. At least one of these displays includes a display device according to an embodiment. For example, all of these displays may include a display device according to an embodiment.

[0105] The center display 201 is disposed in a portion of the dashboard facing the driver's seat 208 and the passenger's seat 209. While FIGS. 28A and 28B show an example of a horizontally elongated center display 201 extending from the driver's seat 208 side to the passenger's seat 209 side, the screen size and location of the center display 201 are arbitrary. The center display 201 can display information detected by various sensors. As a specific example, the center display 201 can display an image captured by an image sensor, a distance image to obstacles in front of or to the side of the vehicle 200 measured by a ToF sensor, and the body temperature of a passenger detected by an infrared sensor. The center display 201 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information.

[0106] The safety-related information includes information such as detection of drowsiness, distraction, child mischief, whether a seatbelt is fastened, and whether a passenger has been abandoned. For example, this information is detected by a sensor disposed on the rear side of the center display 201. The operation-related information is obtained by detecting gestures related to passenger operations using a sensor. The detected gestures may include operations of various equipment within the vehicle 200. For example, operations of the air conditioning system, navigation system, AV system, lighting system, etc. are detected. The life log includes life logs of all passengers. For example, the life log includes a record of each passenger's actions while on board. By acquiring and saving the life log, the condition of the passenger at the time of the accident can be confirmed. The health-related information is obtained by detecting the passenger's body temperature using a sensor such as a temperature sensor, and inferring the passenger's health condition based on the detected body temperature. Alternatively, an image sensor may be used to capture an image of the passenger's face, and the passenger's health condition may be inferred from the facial expression in the image. Furthermore, the system may have an automated voice conversation with the occupant and estimate the occupant's health condition based on the occupant's responses. The authentication / identification-related information includes a keyless entry function that uses a sensor to perform facial recognition, a function that automatically adjusts seat height and position using facial recognition, etc. The entertainment-related information includes a function that uses a sensor to detect operation information of an AV device by the occupant, and a function that recognizes the occupant's face using a sensor and provides content suitable for the occupant via the AV device.

[0107] The console display 202 can be used to display, for example, life log information. The console display 202 is disposed near a shift lever 211 on a center console 210 between a driver's seat 208 and a passenger seat 209. Information detected by various sensors can also be displayed on the console display 202. Furthermore, the console display 202 may display an image of the surroundings of the vehicle captured by an image sensor, or may display an image showing the distance to an obstacle around the vehicle.

[0108] The head-up display 203 is virtually displayed behind the windshield 212 in front of the driver's seat 208. The head-up display 203 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. Because the head-up display 203 is often virtually located in front of the driver's seat 208, it is suitable for displaying information directly related to the operation of the vehicle 200, such as the speed of the vehicle 200 and the remaining fuel (battery) level.

[0109] The digital rearview mirror 204 can not only display the rear of the vehicle 200 but also display the state of passengers in the rear seats. Therefore, by placing a sensor on the back side of the digital rearview mirror 204, it can be used to display life log information, for example.

[0110] The steering wheel display 205 is disposed near the center of the steering wheel 213 of the vehicle 200. The steering wheel display 205 can be used to display at least one of, for example, safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 205 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information related to the operation of AV equipment, air conditioning equipment, etc.

[0111] The rear entertainment display 206 is attached to the back side of the driver's seat 208 and the passenger seat 209 and is intended for viewing by rear seat passengers. The rear entertainment display 206 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, since the rear entertainment display 206 is located directly in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 206. For example, the rear entertainment display 206 may display information related to the operation of an AV device or an air conditioning system, or may display the results of measuring the body temperature of the rear seat passengers using a temperature sensor.

[0112] A sensor may be arranged on the rear side of the display device to measure the distance to surrounding objects. Optical distance measurement methods are broadly divided into passive and active types. Passive methods measure distance by receiving light from an object without projecting light from the sensor onto the object. Passive methods include the lens focusing method, the stereo method, and the monocular vision method. Active methods measure distance by projecting light onto an object and receiving the light reflected from the object with a sensor. Active methods include the optical radar method, the active stereo method, the photometric stereo method, the moire topography method, and the interferometry method. The display device described above can be applied to any of these distance measurement methods. By using a sensor arranged on the rear side of the display device described above, the passive or active distance measurement described above can be performed.

[0113] <Modifications> Although the embodiments and application examples of the present technology have been specifically described above, the content of the present technology is not limited to the above-described embodiments and application examples, and various modifications based on the technical ideas of the present technology are possible.

[0114] [Modifications of the Pixel Circuit] First, modifications of the pixel circuit will be described. FIG. 29 shows another example of the configuration of the pixel PIX. This pixel PIX has capacitors C11 and C12, transistors MP12 to MP15, and a light-emitting element EL. Transistors MP12 to MP15 are P-type MOSFETs. The gate of transistor MP12 is connected to a control line WSL, its source is connected to a signal line SIG, and its drain is connected to the gate of transistor MP14 and capacitor C12. One end of capacitor C11 is connected to a power supply line VCCP, and the other end is connected to capacitor C12, the drain of transistor MP13, and the source of transistor MP14. One end of capacitor C12 is connected to the other end of capacitor C11, the drain of transistor MP13, and the source of transistor MP14, and the other end is connected to the drain of transistor MP12 and the gate of transistor MP14. The gate of transistor MP13 is connected to the control line DSL, the source is connected to the power supply line VCCP, and the drain is connected to the source of transistor MP14, the other end of capacitor C11, and one end of capacitor C12. The gate of transistor MP14 is connected to the drain of transistor MP12 and the other end of capacitor C12, the source is connected to the drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12, and the drain is connected to the anode of the light-emitting element EL and the source of transistor MP15. The gate of transistor MP15 is connected to the control line AZSL, the source is connected to the drain of transistor MP14 and the anode of the light-emitting element EL, and the drain is connected to the power supply line VSS.

[0115] With this configuration, in pixel PIX, when transistor MP12 is turned on, the voltage across capacitor C12 is set based on the pixel signal supplied from signal line SIG. Transistor MP13 is turned on and off based on the signal on control line DSL. While transistor MP13 is on, transistor MP14 passes a current corresponding to the voltage across capacitor C12 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP14. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP15 is turned on and off based on the signal on control line AZSL. While transistor MP15 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0116] The transistors MP12 to MP15 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP12 and MP15 may be a transistor using an oxide semiconductor.

[0117] 30 shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C21, transistors MN22 to MN25, and a light-emitting element EL. Transistors MN22 to MN25 are N-type MOSFETs. The gate of transistor MN22 is connected to a control line WSL, the drain is connected to a signal line SIG, and the source is connected to the gate of transistor MN24 and capacitor C21. One end of capacitor C21 is connected to the source of transistor MN22 and the gate of transistor MN24, and the other end is connected to the source of transistor MN24, the drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN23 is connected to a control line DSL, the drain is connected to a power supply line VCCP, and the source is connected to the drain of transistor MN24. The gate of transistor MN24 is connected to the source of transistor MN22 and one end of capacitor C21, the drain is connected to the source of transistor MN23, the source is connected to the other end of capacitor C21, the drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN25 is connected to control line AZSL, the drain is connected to the source of transistor MN24, the other end of capacitor C21, and the anode of light-emitting element EL, and the source is connected to power supply line VSS.

[0118] With this configuration, in pixel PIX, when transistor MN22 is turned on, the voltage across capacitor C21 is set based on the pixel signal supplied from signal line SIG. Transistor MN23 is turned on and off based on the signal on control line DSL. While transistor MN23 is on, transistor MN24 passes a current corresponding to the voltage across capacitor C21 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MN24. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN25 is turned on and off based on the signal on control line AZSL. While transistor MN25 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0119] The transistors MN22 to MN25 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MN22 and MN25 may be a transistor using an oxide semiconductor.

[0120] 31 shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C31, transistors MP32 to MP36, and a light-emitting element EL. Transistors MP32 to MP36 are P-type MOSFETs. The gate of transistor MP32 is connected to a control line WSL, its source is connected to a signal line SIG, and its drain is connected to the gate of transistor MP33, the drain of transistor MP34, and capacitor C31. One end of capacitor C31 is connected to a power supply line VCCP, and the other end is connected to the drain of transistor MP32, the gate of transistor MP33, and the drain of transistor MP34. The gate of transistor MP34 is connected to a control line AZSL1, its source is connected to the drain of transistor MP33 and the source of transistor MP35, and its drain is connected to the drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31. The gate of transistor MP35 is connected to the control line DSL, the source is connected to the drain of transistor MP33 and the source of transistor MP34, the drain is connected to the source of transistor MP36 and the anode of the light-emitting element EL, the gate of transistor MP36 is connected to the control line AZSL2, the source is connected to the drain of transistor MP35 and the anode of the light-emitting element EL, and the drain is connected to the power supply line VSS.

[0121] With this configuration, in pixel PIX, when transistor MP32 is turned on, the voltage across capacitor C31 is set based on the pixel signal supplied from signal line SIG. Transistor MP35 is turned on and off based on the signal on control line DSL. During the period when transistor MP35 is on, transistor MP33 passes a current corresponding to the voltage across capacitor C31 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP33. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP34 is turned on and off based on the signal on control line AZSL1. During the period when transistor MP34 is on, the drain and gate of transistor MP33 are connected to each other. Transistor MP36 is turned on and off based on the signal on control line AZSL2. During the period when transistor MP36 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0122] The transistors MP32 to MP36 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP32, MP34, and MP36 may be a transistor using an oxide semiconductor.

[0123] 32 shows another example of the configuration of pixel PIX. One end of capacitor C48 is connected to signal line SIG1, and the other end is connected to power supply line VSS. One end of capacitor C49 is connected to signal line SIG1, and the other end is connected to signal line SIG2. Transistor MP49 is a P-type MOSFET, and its gate is connected to control line WSL2, its source is connected to signal line SIG1, and its drain is connected to signal line SIG2.

[0124] The pixel PIX includes a capacitor C41, transistors MP42 to MP46, and a light-emitting element EL. Transistors MP42 to MP46 are P-type MOSFETs. The gate of transistor MP42 is connected to a control line WSL1, its source is connected to a signal line SIG2, and its drain is connected to the gate of transistor MP43 and capacitor C41. One end of capacitor C41 is connected to a power supply line VCCP, and the other end is connected to the drain of transistor MP42 and the gate of transistor MP43. The gate of transistor MP43 is connected to the drain of transistor MP42 and the other end of capacitor C41, its source is connected to the power supply line VCCP, and its drain is connected to the sources of transistors MP44 and MP45. The gate of transistor MP44 is connected to a control line AZSL1, its source is connected to the drain of transistor MP43 and the source of transistor MP45, and its drain is connected to signal line SIG2. The gate of transistor MP45 is connected to control line DSL, the source is connected to the drain of transistor MP43 and the source of transistor MP44, the drain is connected to the source of transistor MP46 and the anode of light-emitting element EL, the gate of transistor MP46 is connected to control line AZSL2, the source is connected to the drain of transistor MP45 and the anode of light-emitting element EL, and the drain is connected to power supply line VSS.

[0125] With this configuration, in pixel PIX, when transistor MP42 is turned on, the voltage across capacitor C41 is set based on the pixel signal supplied from signal line SIG1 via capacitor C49. Transistor MP45 is turned on and off based on the signal on control line DSL. While transistor MP45 is on, transistor MP43 passes a current corresponding to the voltage across capacitor C41 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP43. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP44 is turned on and off based on the signal on control line AZSL1. While transistor MP44 is on, the drain of transistor MP43 and signal line SIG2 are connected to each other. Transistor MP46 is turned on and off based on the signal on control line AZSL2. While transistor MP46 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0126] The transistors MP42 to MP46 and MP49 may be transistors using low temperature polysilicon (LTPS). At least one of the transistors MP42, MP46 and MP49 may be a transistor using an oxide semiconductor.

[0127] 33 shows another example of the configuration of the pixel PIX. A plurality of pixels PIX are arranged in a matrix in the display area 100, and the display area 100 is provided between the first control unit 400 and the second control unit 70.

[0128] The first control unit 400 includes transmission gates TG45 and TG46, transistors MP56 and MP57, and a capacitor C61. Transistors MP56 and MP57 are P-type MOSFETs. A pixel signal is supplied to the input terminal of the transmission gate TG45, and the output terminal of the transmission gate TG45 is connected to one end of the signal line 14a. The input terminal of the transmission gate TG46 is connected to the signal line 14b, and the output terminal of the transmission gate TG46 is connected to the power supply line Vorst. One end of the capacitor C61 is connected to the signal line 14a, and the other end is connected to the power supply line VSS1. The gate of the transistor MP56 is connected to the control line INIL, the source is connected to the power supply line Vini, and the drain is connected to the signal line 14b. The gate of the transistor MP57 is connected to the control line ELL, the source is connected to the power supply line Vel, and the drain is connected to the signal line 14b.

[0129] The second control unit 70 has a transmission gate TG72, a transistor MP73, and a capacitor C82. The transistor MP73 is a P-type MOSFET. The input terminal of the transmission gate TG72 is connected to the other end of the signal line 14a, and the output terminal is connected to the drain of the transistor MP73 and one end of the capacitor C82. The gate of the transistor MP73 is connected to the control line REFL, the source is connected to the power supply line Vref, and the drain is connected to the output terminal of the transmission gate TG72 and one end of the capacitor C82. One end of the capacitor C82 is connected to the output terminal of the transmission gate TG72 and the drain of the transistor MP73, and the other end is connected to one end of the signal line 14b.

[0130] The pixel PIX includes a capacitor C132, transistors MP121 to MP125, and a light-emitting element EL. Transistors MP121 to MP125 are P-type MOSFETs. The gate of transistor MP122 is connected to a control line WSL, its source is connected to a signal line 14b, and its drain is connected to the gate of transistor MP121 and capacitor C132. One end of capacitor C132 is connected to a power supply line Vel, and the other end is connected to the drain of transistor MP122 and the gate of transistor MP121. The gate of transistor MP121 is connected to the drain of transistor MP122 and the other end of capacitor C132, its source is connected to the power supply line Vel, and its drain is connected to the sources of transistors MP123 and MP124. The gate of transistor MP123 is connected to a control line AZSL, its source is connected to the drain of transistor MP121 and the source of transistor MP124, and its drain is connected to signal line 14b. The gate of transistor MP124 is connected to the control line DSL, the source is connected to the drain of transistor MP121 and the source of transistor MP123, and the drain is connected to the drain of transistor MP125 and the anode of the light-emitting element 130. The gate of transistor MP125 is connected to the control line AZSL, the source is connected to the power supply line Vorst, and the drain is connected to the drain of transistor MP124 and the anode of the light-emitting element 130.

[0131] With this configuration, in pixel PIX, when transistor MP122 is turned on, the voltage across capacitor C132 is set based on the pixel signal supplied via transmission gate TG45, signal line 14a, transmission gate TG72, capacitor C82, and signal line 14b. Transistor MP124 is turned on and off based on the signal on control line DSL. While transistor MP124 is on, transistor MP121 passes a current corresponding to the voltage across capacitor C132 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP121. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistors MP123 and MP125 are turned on and off based on the signal on control line AZSL. While transistor MP123 is on, the drain of transistor MP121 and the source of transistor MP124 are connected to signal line 14b. During the period when transistor MP125 is in the ON state, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line Vorst. Furthermore, transistor MP56 is turned on and off based on the signal on control line INIL, transistor MP57 is turned on and off based on the signal on control line ELL, and transistor MP73 is turned on and off based on the signal on control line REFL. When transistor MP56 is turned on, signal line 14b is set to the voltage of power supply line Vini, and when transistor MP57 is turned on, signal line 14b is set to the voltage of power supply line Vel. When transistor MP73 is turned on, one end of capacitor C82 is initialized by being set to the voltage of power supply line Vref.

[0132] The transistors MP121 to MP125, MP56, and MP57 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP122 and MP125 may be a transistor using an oxide semiconductor.

[0133] 34 shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C51, transistors MP52 to MP60, and a light-emitting element EL. Transistors MP52 to MP60 are P-type MOSFETs. The gate of transistor MP52 is connected to a control line WSL, its source is connected to a signal line SIG, and its drain is connected to the drain of transistor MP53 and the source of transistor MP54. The gate of transistor MP53 is connected to a control line DSL, its source is connected to a power supply line VCCP, and its drain is connected to the drain of transistor MP52 and the source of transistor MP54. The gate of transistor MP54 is connected to the source of transistor MP55, the drain of transistor MP57, and capacitor C51, its source is connected to the drains of transistors MP52 and MP53, and its drain is connected to the sources of transistors MP58 and MP59. One end of capacitor C51 is connected to the power supply line VCCP, and the other end is connected to the gate of transistor MP54, the source of transistor MP55, and the drain of transistor MP57. Capacitor C51 may include two capacitors connected in parallel. Transistor MP55 has a gate connected to control line AZSL1, a source connected to the gate of transistor MP54, the drain of transistor MP57, and the other end of capacitor C51, and a drain connected to the source of transistor MP56. Transistor MP56 has a gate connected to control line AZSL1, a source connected to the drain of transistor MP55, and a drain connected to power supply line VSS. Transistor MP57 has a gate connected to control line WSL, a drain connected to the gate of transistor MP54, the source of transistor MP55, and the other end of capacitor C51, and a source connected to the drain of transistor MP58. The gate of the transistor MP58 is connected to the control line WSL, the drain is connected to the source of the transistor MP57, and the source is connected to the drain of the transistor MP54 and the source of the transistor MP59.The gate of transistor 59 is connected to control line DSL, the source is connected to the drain of transistor MP54 and the source of transistor MP58, the drain is connected to the source of transistor MP60 and the anode of light-emitting element EL, the gate of transistor MP60 is connected to control line AZSL2, the source is connected to the drain of transistor MP59 and the anode of light-emitting element EL, and the drain is connected to power supply line VSS.

[0134] With this configuration, in pixel PIX, transistors MP52, MP54, MP58, and MP57 are turned on, and the voltage across capacitor C51 is set based on the pixel signal supplied from signal line SIG. Transistors MP53 and MP59 are turned on and off based on the signal on control line DSL. While transistors MP53 and MP59 are on, transistor MP54 passes a current corresponding to the voltage across capacitor C51 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP54. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistors MP55 and MP56 are turned on and off based on the signal on control line AZSL1. While transistors MP55 and MP56 are on, the gate voltage of transistor MP54 is initialized by being set to the voltage of power supply line VSS. Transistor MP60 is turned on and off based on the signal on control line AZSL2. During the period in which the transistor MP60 is in the on state, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0135] The transistors MP52 to MP60 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP55 to MP58 and MP60 may be a transistor using an oxide semiconductor.

[0136] 35 shows another example of the configuration of the pixel PIX. The signal on the control line WSNL and the signal on the control line WSPL are mutually inverted signals.

[0137] The pixel PIX has capacitors C61 and C62, transistors MN63, MP64, and MN65 to MN67, and a light-emitting element EL. The transistors MN63, MN65 to MN67 are N-type MOSFETs, and the transistor MP64 is a P-type MOSFET. The gate of the transistor MN63 is connected to a control line WSNL, the drain is connected to a signal line SIG and the source of the transistor MP64, and the source is connected to the drain of the transistor MP64, the capacitors C61 and C62, and the gate of the transistor MN65. The gate of the transistor MP64 is connected to a control line WSPL, the source is connected to the signal line SIG and the drain of the transistor MN63, and the drain is connected to the source of the transistor MN63, the capacitors C61 and C62, and the gate of the transistor MN65. The capacitor C61 is configured using, for example, a metal oxide metal (MOM) capacitor, with one end connected to the source of transistor MN63, the drain of transistor MP64, capacitor C62, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C61 may be configured using, for example, a metal oxide metal (MOS) capacitor or a metal insulator metal (MIM) capacitor. The capacitor C62 is configured using, for example, a MOS capacitor, with one end connected to the source of transistor MN63, the drain of transistor MP64, one end of capacitor C61, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C62 may be configured using, for example, a MOM capacitor or a MIM capacitor. The other end of the capacitor C62 may be connected to the power supply line VSS3 (not shown). The gate of transistor MN65 is connected to the source of transistor MN63, the drain of transistor MP64, and one end of capacitors C61 and C62, the drain is connected to the power supply line VCCP, and the source is connected to the drains of transistors MN66 and MN67. The gate of transistor MN66 is connected to control line AZL, the drain is connected to the source of transistor MN65 and the drain of transistor MN67, and the source is connected to power supply line VSS1.The gate of transistor MN67 is connected to the control line DSL, the drain is connected to the source of transistor MN65 and the drain of transistor MN66, and the source is connected to the anode of the light-emitting element EL. Note that the transistor MN67 and the control line DSL may be omitted, and the source of transistor MN65 may be connected to the drain of transistor MN66 and the anode of the light-emitting element EL.

[0138] With this configuration, in pixel PIX, when at least one of transistors MN63 and MP64 is turned on, the voltage across capacitors C61 and C62 is set based on the pixel signal supplied from signal line SIG. Transistor MN67 is turned on and off based on the signal on control line DSL. While transistor MN67 is on, transistor MN65 passes a current corresponding to the voltage across capacitors C61 and C62 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN65. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN66 may be turned on and off based on the signal on control line AZL. Transistor MN66 may also function as a resistor element having a resistance value corresponding to the signal on control line AZL. In this case, transistors MN65 and MN66 form a so-called source follower circuit.

[0139] The transistors MN63, MP64, MN65 to MN67 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MN63, MP64, and MN66 may be a transistor using an oxide semiconductor.

[0140] [Modification of Output Source] In the above-described embodiment, a lamp drive circuit was given as an example of an output source, but it may also be configured as a voltage follower circuit. Fig. 36 is a diagram showing an example configuration of a signal line drive unit 30 according to this modification. The horizontal logic circuit 31 of the signal line drive unit 30 has a shift register (S / R) unit 71, a first latch unit 72, and a second latch unit 73. The horizontal analog circuit 32 also has a level shifter unit 74, a DAC unit 75, an output buffer unit 76, and a gamma resistor unit 80.

[0141] The shift register unit 71 is composed of a group of shift registers (not shown) whose number corresponds to the number of pixels in the row direction, and sequentially outputs shift pulses (sampling pulses) from each transfer stage in synchronization with a horizontal clock pulse HCK (not shown). The 1st latch unit 72 is composed of a plurality of 1st latch circuits 72A, and sequentially samples and latches image data DATA using sampling pulses LATCLK[0], [1], ... output by each shift register. The 2nd latch unit 73 is composed of a plurality of 2nd latch circuits 73A, and line-sequentially converts each latched data of the 1st latch circuits 72A into data using a line pulse LINECLK.

[0142] The level shifter unit 74 is composed of a group of level shifter circuits (not shown) and converts the level of each pixel data line-sequentially processed by the 2nd latch circuit 73A from a logic level to analog level data corresponding to the drive level. The DAC unit 75 is composed of multiple DAC circuits 75A and receives a grayscale voltage corresponding to the gamma resistance set by the gamma resistor unit 80, and converts the image data level-converted by each level shifter circuit from digital data to analog data. The output buffer unit 76 is composed of a voltage follower composed of multiple operational amplifiers 76A and demultiplexers 76B and outputs pixel signals Data obtained by conversion by each DAC circuit 75A to signal lines connected to each pixel PIX of the pixel array unit 20 in a time-division manner during each horizontal period. The output source according to the present technology may be composed of components including the signal line driver 30 shown in FIG. 30 , the DAC 32A, the operational amplifier 76A, the demultiplexer 76B, and the gamma resistor unit 80.

[0143] [Other Modifications] In the above-described embodiments, the display device may have a circuit that cancels DC offset, which is a variation inherent in each operational amplifier in the panel. Figures 37A and 37B are diagrams for explaining an example of the configuration of a circuit that cancels DC offset and an example of the operation of the circuit.

[0144] For example, a switch SW1 is provided between the output side of an operational amplifier OP of the voltage follower circuit 66 and a first input terminal of the operational amplifier OP, and a switch SW2 is provided between the output side of the operational amplifier OP and a second input terminal of the operational amplifier OP. Furthermore, a switch SW3 is provided between a terminal to which an input voltage Vin is input and the first input terminal of the operational amplifier OP, and a switch SW4 is provided between the terminal to which the input voltage Vin is input and a second input terminal of the operational amplifier OP.

[0145] 37A, when switches SW1 and SW4 are on (closed) and switches SW2 and SW3 are off (open), the operational amplifier OP outputs a voltage (Vin+ΔV) to which an offset voltage ΔV has been added. Also, as shown in FIG. 37B, when switches SW1 and SW4 are off (open) and switches SW2 and SW3 are on (closed), the polarity of the operational amplifier OP is reversed, and the operational amplifier OP outputs a voltage (Vin-ΔV) to which the offset voltage ΔV has been subtracted.

[0146] For example, the polarity of the operational amplifier OP is inverted every horizontal period or every vertical period, which causes the average output voltage of the operational amplifier OP to approach Vin, i.e., the DC offset can be attenuated on a time average basis, thereby reducing the influence of the DC offset.

[0147] In the fourth and fifth embodiments described above, the lamp drive circuits that drive the red pixels and the blue pixels are a common lamp drive circuit, but the display device may have a lamp drive circuit that drives the red pixels and a separate lamp drive circuit that drives the blue pixels. Also, although green, red, and blue are exemplified as pixel color types, other colors may also be used.

[0148] For example, the configurations, methods, processes, shapes, materials, and numerical values ​​of the above-described embodiments and application examples can be combined or substituted with each other without departing from the spirit of the present technology. Furthermore, one thing can be divided into two or more parts, and some parts can be omitted. Furthermore, as long as the present technology is applicable, the above-described configurations can be added, deleted, or modified as appropriate.

[0149] Note that the present technology may also have the following configuration: (1) A display device comprising: a first output source that outputs a first analog voltage; a second output source that outputs a second analog voltage and is different from the first output source; a plurality of first signal lines connected to the first output source; a plurality of second signal lines connected to the second output source; and a pixel array section in which the first signal lines, first pixels connected to the first signal lines, the second signal lines, and second pixels connected to the second signal lines are arranged, wherein the pixel array section has a first region in which the first signal lines are continuously arranged, a second region in which the second signal lines are continuously arranged, and a third region formed between the first region and the second region and in which the first signal lines and the second signal lines are substantially alternately arranged. (2) The display device according to (1), including a plurality of output sources including the first output source and the second output source, wherein the pixel array section has a plurality of the first regions, a plurality of the second regions, and a plurality of the third regions. (3) The display device according to (1) or (2), wherein the pixel array section has a substantially rectangular shape, and the first region, the second region, and the third region are alternately arranged along a horizontal direction of the pixel array section. (4) The display device according to (1), wherein the pixel array section has a substantially rectangular shape, and the first region, the second region, and the third region are alternately arranged along a vertical direction of the pixel array section. (5) The display device according to any of (1) to (4), comprising: a third output source that outputs a third analog voltage and is different from the first output source and the second output source; a fourth output source that outputs a fourth analog voltage and is different from the first output source, the second output source, and the third output source; a plurality of third signal lines connected to the third output source; and a plurality of fourth signal lines connected to the fourth output source, wherein the third signal lines include a pair of a fifth signal line and a sixth signal line, and the fourth signal lines include a pair of a seventh signal line and an eighth signal line.(6) The display device according to (5), wherein the pixel array unit has a fourth region in which the paired fifth signal line and the sixth signal line are continuously arranged, a fifth region in which the paired seventh signal line and the eighth signal line are continuously arranged, and a sixth region formed between the fourth region and the fifth region in which the fifth signal line, the sixth signal line, the seventh signal line, and the eighth signal line are substantially alternately arranged. (7) The display device according to (5), wherein the pixel array unit has a fourth region in which the paired fifth signal line and the sixth signal line are continuously arranged, and a fifth region adjacent to the fourth region in which the paired seventh signal line and eighth signal line are continuously arranged. (8) The display device according to any of (5) to (7), wherein a third pixel is connected to the fifth signal line, a fourth pixel is connected to the sixth signal line, a fifth pixel is connected to the seventh signal line, and a sixth pixel is connected to the eighth signal line. (9) The display device according to (8), wherein the first pixel and the second pixel are pixels corresponding to a first color type, the third pixel and the fifth pixel are pixels corresponding to a second color type different from the first color type, and the fourth pixel and the sixth pixel are pixels corresponding to a third color type different from the first color type and the second color type. (10) The display device according to (9), wherein the first color type is a color type having higher luminosity than the second color type and the third color type. (11) The display device according to (10), wherein the first color type is green, the second color type is red, and the third color type is blue. (12) The display device according to any of (1) to (11), wherein the first signal lines and the second signal lines are arranged alternately in the third region. (13) The display device according to any one of (1) to (11), wherein the first signal lines and the second signal lines are arranged in the third region such that, when viewed in each of a plurality of regions virtually set in the third region, a ratio of the number of first signal lines or the number of second signal lines to the number of signal lines in the region gradually decreases or gradually increases. (14) The display device according to any one of (1) to (13), wherein a total number of the first pixels and the second pixels arranged in the third region is five or more.(15) The display device according to any one of (1) to (14), wherein each output source has a ramp wave output unit that outputs a ramp wave whose potential fluctuates uniformly, and a buffer unit that is supplied with the ramp wave generated by the ramp wave output unit, and each signal line is connected to the buffer unit via a switch element provided for each of the signal lines. (16) The display device according to (15), wherein the ramp wave is sampled at a timing when the switch element is turned on, and the voltage of the sampled gradation is written to a pixel connected to the signal line connected to the switch element. (17) The display device according to (15) or (16), wherein the polarity of an operational amplifier included in the buffer unit is inverted at predetermined intervals. (18) An electronic device having the display device according to any one of (1) to (17).

[0150] 20...Pixel array section 57C, 57D...Switching elements 65A, 65B...Lamp driving circuit 66A, 66B...Voltage follower circuit 67A, 67B...RAMPDAC section 100A, 100B, 100C, 100D, 100E...Display device AR1...First region AR2...Second region AR3...Third region AR4...Fourth region AR5...Fifth region AR6...Sixth region SIG...Signal line OP...Operational amplifier

Claims

1. A display device comprising: a first output source that outputs a first analog voltage; a second output source that outputs a second analog voltage and is different from the first output source; a plurality of first signal lines connected to the first output source; a plurality of second signal lines connected to the second output source; and a pixel array section in which the first signal lines, first pixels connected to the first signal lines, the second signal lines, and second pixels connected to the second signal lines are arranged, wherein the pixel array section has a first region in which the first signal lines are continuously arranged, a second region in which the second signal lines are continuously arranged, and a third region formed between the first region and the second region and in which the first signal lines and the second signal lines are arranged substantially alternately.

2. The display device according to claim 1, further comprising a plurality of output sources including the first output source and the second output source, and the pixel array portion comprises a plurality of the first regions, a plurality of the second regions, and a plurality of the third regions.

3. The display device according to claim 1, wherein the pixel array section has a substantially rectangular shape, and the first region, the second region, and the third region are alternately arranged along the horizontal direction of the pixel array section.

4. The display device according to claim 1, wherein the pixel array section has a substantially rectangular shape, and the first region, the second region, and the third region are alternately arranged along the vertical direction of the pixel array section.

5. The display device of claim 1, comprising: a third output source that outputs a third analog voltage and is different from the first output source and the second output source; a fourth output source that outputs a fourth analog voltage and is different from the first output source, the second output source, and the third output source; a plurality of third signal lines connected to the third output source; and a plurality of fourth signal lines connected to the fourth output source, wherein the third signal lines include a pair of a fifth signal line and a sixth signal line, and the fourth signal lines include a pair of a seventh signal line and an eighth signal line.

6. The display device according to claim 5, wherein the pixel array section has a fourth region in which the fifth signal line and the sixth signal line forming a pair are continuously arranged, a fifth region in which the seventh signal line and the eighth signal line forming a pair are continuously arranged, and a sixth region formed between the fourth region and the fifth region and in which the fifth signal line, the sixth signal line, the seventh signal line, and the eighth signal line are substantially alternately arranged.

7. The display device according to claim 5, wherein the pixel array section has a fourth region in which the fifth and sixth signal lines forming a pair are continuously arranged, and a fifth region adjacent to the fourth region in which the seventh and eighth signal lines forming a pair are continuously arranged.

8. The display device according to claim 5, wherein a third pixel is connected to the fifth signal line, a fourth pixel is connected to the sixth signal line, a fifth pixel is connected to the seventh signal line, and a sixth pixel is connected to the eighth signal line.

9. The display device according to claim 8, wherein the first pixel and the second pixel are pixels corresponding to a first color type, the third pixel and the fifth pixel are pixels corresponding to a second color type different from the first color type, and the fourth pixel and the sixth pixel are pixels corresponding to a third color type different from the first color type and the second color type.

10. The display device according to claim 9, wherein the first color type has a higher visibility than the second color type and the third color type.

11. The display device of claim 10, wherein the first color type is green, the second color type is red, and the third color type is blue.

12. The display device according to claim 1, wherein the first signal lines and the second signal lines are arranged alternately in the third region.

13. The display device of claim 1, wherein the first signal lines and the second signal lines are arranged in the third region so that, when viewed in each of a plurality of regions virtually set in the third region, the ratio of the number of the first signal lines or the second signal lines to the number of signal lines in the region gradually decreases or gradually increases.

14. The display device according to claim 1, wherein the total number of the first pixels and the second pixels arranged in the third region is five or more.

15. The display device according to claim 1, wherein each output source has a ramp wave output section which outputs a ramp wave with a uniform potential fluctuation, and a buffer section which is supplied with the ramp wave generated by the ramp wave output section, and each signal line is connected to the buffer section via a switch element provided for each signal line.

16. The display device according to claim 15, wherein the ramp wave is sampled at the timing when the switch element is turned on, and a voltage of the sampled gray scale is written to a pixel connected to the signal line connected to the switch element.

17. The display device according to claim 15, wherein the polarity of the operational amplifier included in the buffer section is inverted at predetermined intervals.

18. An electronic device comprising the display device according to claim 1.

Images