Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel comprises a substrate, multiple data lines, multiple fourth switching lines, multiple fifth switching lines, multiple first switching blocks, multiple second switching blocks, and multiple first electrodes. The multiple data lines comprise multiple fourth data lines, and the multiple fourth data lines are disposed in an edge region; portions of the fourth data lines and the fifth switching lines disposed in the edge region are connected by means of a first switching block; and portions of the fourth switching lines and the fifth switching lines disposed in a central region are connected by means of a second switching block. The multiple first electrodes are disposed at the side of the substrate at which the multiple first switching blocks and multiple of second switching blocks are provided, and, in an orthographic projection onto the substrate, the first electrodes are disposed alternating with the first switching blocks and / or the second switching blocks.

Description

Display panel and display device

[0001] This application claims priority to Chinese patent application No. 202311776280.0, filed on December 21, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] With the rapid development of display technology, display devices have become increasingly ubiquitous in our lives. Organic light-emitting diodes (OLEDs) are widely used in smart products such as mobile phones, televisions, and laptops due to their advantages such as self-luminescence, low power consumption, wide viewing angle, fast response, high contrast, and flexible display.

[0004] In the related art, the flatness of the first electrode of the light emitting device is low, and the direction of the light emitted by the light emitting device will deviate, thereby causing color separation and color deviation problems in the display device, and reducing the display effect.

[0005] Summary of the Invention

[0006] In one aspect, a display panel is provided. The display panel comprises a functional device placement area and a main display area at least partially surrounding the functional device placement area. The display panel further comprises a fan-out area, which is disposed on one side of the main display area along a second direction. The main display area further comprises a central area and an edge area, which is disposed on at least one side of the central area along a first direction. The display panel comprises a substrate, a plurality of data lines, a plurality of fourth transfer lines, a plurality of fifth transfer lines, a plurality of first transfer blocks, a plurality of second transfer blocks, a plurality of first electrodes, a plurality of first scan signal lines, and a plurality of first initialization signal lines. A plurality of data lines are provided on the substrate; the plurality of data lines are arranged at intervals along the first direction; the plurality of data lines include at least one first data line and a plurality of fourth data lines; the first data line is provided in the main display area, and the plurality of first data lines include a first data line segment, a first connecting line, and a second data line segment connected in sequence; the first data line segment and the second data line segment both extend along the second direction and are provided on both sides of the functional device setting area along the second direction; the extension direction of the first data line segment coincides with the extension direction of the second data line segment and passes through the functional device setting area; the plurality of fourth data lines are provided in the edge area and extend along the second direction; wherein the first direction intersects the second direction. The plurality of fourth transfer lines are provided on the substrate and in the central area; the fourth transfer lines extend along the second direction and are connected to the fan-out area. The plurality of fifth transfer lines are disposed on the substrate and in the edge region. The plurality of fifth transfer lines extend along the first direction to the center region and are spaced apart along the second direction. At least a portion of the plurality of fifth transfer lines crosses over at least one data line and is insulated from the data line it crosses over. The plurality of first transfer blocks are disposed on the substrate. The fourth data line and the portion of the fifth transfer line disposed in the edge region are connected via a first transfer block. The plurality of second transfer blocks are disposed on the substrate. The fourth transfer line and the portion of the fifth transfer line disposed in the center region are connected via a second transfer block. The plurality of first electrodes are disposed on the plurality of first transfer blocks and the plurality of second transfer blocks are disposed on one side of the substrate. In an orthographic projection onto the substrate, the first electrode is staggered with the first transfer block and / or the second transfer block. The multiple first scanning signal lines extend along the first direction and are spaced apart along the second direction; the multiple first initialization signal lines extend along the first direction and are spaced apart along the second direction; one of the first initialization signal lines is located between one of the first scanning signal lines and one of the fifth transfer lines.

[0007] In some embodiments, the display panel further comprises a first conductive layer, a second conductive layer, and a first electrode layer. The first conductive layer is disposed on the substrate; the fourth data line and the fourth adapter line are disposed on the first conductive layer. The second conductive layer is disposed between the substrate and the first conductive layer; the fifth adapter line, the first adapter block, and the second adapter block are disposed on the second conductive layer. The first electrode layer is disposed on a side of the first conductive layer away from the substrate and includes the plurality of first electrodes.

[0008] In some embodiments, the plurality of data lines are divided into a plurality of groups, each group of data lines includes two data lines, and a minimum interval between two data lines in a group of data lines is greater than a minimum interval between two adjacent groups of data lines;

[0009] The data line includes alternating first straight segments and first bend segments; the first straight segments extend along the second direction, and the first bend segments bend in a direction away from another data line in the same group of data lines; each of the fourth adapter lines is arranged between two data lines in a group of data lines. The multiple first electrodes include multiple first sub-electrodes and multiple second sub-electrodes. In an orthographic projection onto the substrate, a first sub-electrode overlaps with two adjacent first bend segments in two adjacent groups, and a second sub-electrode is arranged between two first straight segments in a group. In an orthographic projection onto the substrate, the first adapter block and the second adapter block are arranged on both sides of the fourth adapter line, the first adapter block at least partially overlaps with the first straight segment, and the second adapter block at least partially overlaps with the fourth adapter line and is arranged between the first bend segments on both sides of the fourth adapter line.

[0010] In some embodiments, the first conductive layer further comprises a plurality of first power supply voltage signal lines, the plurality of first power supply voltage signal lines being divided into a plurality of groups, each group of first power supply voltage signal lines comprising two first power supply voltage signal lines; the group of first power supply voltage signal lines being disposed between the two data lines in a group of data lines, and each of the fourth adapter lines being disposed between the two first power supply voltage signal lines in a group of first power supply voltage signal lines. In an orthographic projection onto the substrate, the first sub-electrode is disposed between two mutually distant boundaries of two adjacent groups of first power supply voltage signal lines.

[0011] In some embodiments, in the orthographic projection onto the substrate, the midline of the fifth connecting line along the first direction coincides with a straight line formed by connecting the intersection of the first straight segment and the first bending segment, and the first electrode is disposed between two adjacent fifth transfer lines.

[0012] In some embodiments, in the orthographic projection onto the substrate, the portion where the first sub-electrode overlaps with the data line is symmetrical about the fifth axis and / or the sixth axis; the fifth axis extends along the first direction and passes through the center of the first sub-electrode, and the sixth axis extends along the second direction and passes through the center of the first sub-electrode; the midline of the portion where the second sub-electrode overlaps with the fourth transfer line passes through the center of the second sub-electrode.

[0013] In some embodiments, the multiple data lines and the multiple fourth transfer lines are alternately distributed; the multiple first electrodes include multiple third sub-electrodes, multiple fourth sub-electrodes and multiple fifth sub-electrodes; in the orthographic projection onto the substrate, the third sub-electrode overlaps with the adjacent data line and the fourth transfer line, and the overlapping part is symmetrical about the ninth axis and / or the tenth axis; the ninth axis extends along the first direction and passes through the center of the third sub-electrode, and the tenth axis extends along the second direction and passes through the center of the third sub-electrode; in the orthographic projection onto the substrate, the fourth sub-electrode overlaps with two data lines and two fourth transfer lines, and the overlapping part is symmetrical about the eleventh axis and / or the twelfth axis; the eleventh axis extends along the first direction and passes through the center of the fourth sub-electrode, and the twelfth axis extends along the second direction and passes through the center of the fourth sub-electrode; in the orthographic projection onto the substrate, the fifth sub-electrode overlaps with the adjacent data line and the fourth transfer line, and the overlapping part is symmetrical about the center of the fifth sub-electrode.

[0014] In some embodiments, the display panel further includes a third conductive layer and a fourth conductive layer. The third conductive layer is disposed between the second conductive layer and the substrate; the plurality of first scan signal lines are disposed in the third conductive layer. The fourth conductive layer is disposed between the third conductive layer and the second conductive layer; the plurality of first initialization signal lines are disposed in the fourth conductive layer. In an orthographic projection onto the substrate, the first initialization signal line overlaps with the first scan signal line, and the fifth transfer line is disposed within the range of the first initialization signal line.

[0015] In some embodiments, the display panel further includes a fifth conductive layer and a sixth conductive layer. The fifth conductive layer is disposed between the second conductive layer and the substrate; the plurality of first scan signal lines are disposed in the fifth conductive layer. The sixth conductive layer is disposed between the fifth conductive layer and the second conductive layer; the plurality of first initialization signal lines are disposed in the sixth conductive layer. The plurality of first initialization signal lines, the plurality of first scan signal lines, and the fifth transfer line are divided into a plurality of groups, each group including a first initialization signal line, a first scan signal line, and a fifth transfer line. In an orthographic projection onto the substrate, the first initialization signal line is disposed between the first scan signal line and the fifth transfer line.

[0016] In some embodiments, in an orthographic projection onto the substrate, the second adapter block is disposed on a side of the fifth adapter line connected to the second adapter block that is away from the first scan signal line.

[0017] In some embodiments, the fourth adapter line has a first opening, the first opening dividing the first adapter line into a first routing segment and a second routing segment, the first routing segment being disposed on a side of the second routing segment close to the fan-out region, one end of the first routing segment being connected to the fan-out region, and the other end being connected to the fifth adapter line. In an orthographic projection onto the substrate, the first opening is staggered with respect to the first electrode.

[0018] In some embodiments, the second conductive layer further includes a plurality of power supply voltage blocks; the power supply voltage blocks are configured to transmit power supply voltage signals; and in an orthographic projection onto the substrate, the first opening is disposed within the range of the power supply voltage blocks.

[0019] In some embodiments, the display panel further includes a seventh conductive layer disposed between the second conductive layer and the substrate; the seventh conductive layer includes a plurality of spacers; and in an orthographic projection onto the substrate, the first opening is disposed within the spacers.

[0020] In some embodiments, the fifth adapter line has a second opening and a third opening; the second opening and the third opening divide the fifth adapter line into a third routing segment, a fourth routing segment and a fifth routing segment; one end of the fourth routing segment is connected to the first adapter block, and the other end is connected to the second adapter block, and the third routing segment and the fifth routing segment are arranged on both sides of the fourth routing segment; in the orthographic projection onto the substrate, the first electrode and the second opening and / or the third opening are staggered.

[0021] In some embodiments, in an orthographic projection onto the substrate, the second opening and / or the third opening is disposed within the range of the data line.

[0022] In some embodiments, the first conductive layer further includes a plurality of first power supply voltage signal lines, the plurality of first power supply voltage signal lines being spaced apart along the first direction and extending along the second direction. In an orthographic projection onto the substrate, the second opening and / or the third opening are disposed within the range of the first power supply voltage signal lines.

[0023] In some embodiments, the display panel further includes an eighth conductive layer. The eighth conductive layer is disposed between the substrate and the second conductive layer and includes a plurality of third initialization signal lines; the third initialization signal lines include at least portions extending along the second direction. In an orthographic projection onto the substrate, the fourth adapter line overlaps with portions of the third initialization signal lines extending along the second direction.

[0024] In some embodiments, the plurality of data lines include at least one second data line, the second data line including a third data line segment, a second connecting line, and a fourth data line segment connected in sequence; the third data line segment and the fourth data line segment are both disposed in the main display area; the third data line segment and the fourth data line segment both extend along the second direction and are disposed on either side of the functional device placement area along the second direction; the extension direction of the third data line segment coincides with the extension direction of the fourth data line segment; and the second connecting line is parallel to a boundary of the functional device placement area.

[0025] In another aspect, a display device is provided, comprising: a display panel as described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0027] FIG1 is a structural diagram of a display device according to some embodiments;

[0028] FIG2 is a structural diagram of a display panel according to some embodiments;

[0029] FIG3 is a partial enlarged view of point C in FIG2 ;

[0030] FIG4 is a partial enlarged view of point D in FIG2 ;

[0031] FIG5 is a structural diagram of a first conductive layer according to some embodiments;

[0032] FIG6 is another structural diagram of the first conductive layer according to some embodiments;

[0033] FIG7 is a structural diagram of a second conductive layer according to some embodiments;

[0034] FIG8 is another structural diagram of a second conductive layer according to some embodiments;

[0035] FIG9 is a structural diagram of a first conductive layer and a second conductive layer stacked according to some embodiments;

[0036] FIG10 is another structural diagram of a first conductive layer and a second conductive layer stacked according to some embodiments;

[0037] FIG11 is a structural diagram of a third conductive layer according to some embodiments;

[0038] FIG12 is a structural diagram of a fourth conductive layer according to some embodiments;

[0039] FIG13 is a structural diagram of a stacked second conductive layer, a third conductive layer, and a fourth conductive layer according to some embodiments;

[0040] FIG14 is a structural diagram of a fifth conductive layer according to some embodiments;

[0041] FIG15 is a structural diagram of a sixth conductive layer according to some embodiments;

[0042] FIG16 is a structural diagram of a stacked second conductive layer, a fourth conductive layer, and a fifth conductive layer according to some embodiments;

[0043] FIG17 is a structural diagram of a seventh conductive layer according to some embodiments;

[0044] FIG18 is a structural diagram of a stacked first conductive layer, a second conductive layer, and an eighth conductive layer according to some embodiments;

[0045] FIG. 19 is a structural diagram of a sixth conductive layer and an eighth conductive layer according to some embodiments. DETAILED DESCRIPTION

[0046] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0047] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "examples," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0048] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0049] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0050] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C,” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0051] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0052] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0053] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0054] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0055] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0056] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0057] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0058] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0059] As shown in FIG1 , some embodiments of the present disclosure provide a display device 1000 . The display device 1000 may be any device that displays either moving (eg, video) or fixed (eg, still image) content, and either text or images.

[0060] For example, the display device 1000 can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigation system, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, an in-vehicle display, or an aircraft display. For example, as shown in FIG1 , the display device 1000 can be a mobile phone.

[0061] In terms of the light-emitting type of the display device 1000, the display device 1000 may be an organic light-emitting diode display device, a quantum dot electroluminescent display device (QLED), or a mini / micro light-emitting diode (MLED). In terms of the form of the display device 1000, the display device 1000 may be a flat display device, a curved display device, or a foldable display device. In terms of the shape of the display device 1000, the display device 1000 may be rectangular or circular, etc. The embodiments of the present disclosure do not specifically limit this.

[0062] Below, some embodiments of the present disclosure are schematically described using a rectangular and planar organic light-emitting diode display device 1000 as an example. However, the embodiments of the present disclosure are not limited thereto, and any other display device may also be considered as long as the same technical concept is applied.

[0063] In some embodiments, as shown in FIG. 1 , a display device 1000 includes a display panel 100 .

[0064] For example, the display device 1000 may further include a housing 200 , a functional device 300 , a circuit board, and other electronic components. The display panel 100 , the functional device 300 , and the circuit board may be disposed within the housing 200 .

[0065] It should be noted that the functional device 300 may be a camera, an infrared sensor, a proximity sensor, an eye tracking module, a face recognition module, etc. For example, as shown in FIG1 , the functional device 300 is a camera.

[0066] In some embodiments, as shown in FIG2 , the display panel 100 includes a display area A and a peripheral area B disposed on at least one side of the display area A. FIG2 illustrates an example in which the peripheral area B surrounds the display area A. The display area A further includes a functional device placement area A1 and a main display area A2 that at least partially surrounds the functional device placement area A1.

[0067] The display area A is an area for displaying images and is configured to set multiple sub-pixels. The peripheral area B is an area for not displaying images and is configured to set display driving circuits, such as scan driving circuits and source driving circuits.

[0068] In some embodiments, the display panel 100 has a display side and a non-display side 10B disposed opposite to each other, wherein the display side refers to a side of the display panel displaying an image, and the non-display side refers to the other side opposite to the display side.

[0069] The display device 1000 can use under-screen technology to set functional devices, that is, to set the functional device 300 on the non-display side of the functional device setting area A1. For example, a front camera assembly is set on the non-display side of the functional device setting area A1, that is, the display device 1000 uses under-screen camera technology.

[0070] In other embodiments, as shown in FIG2 , the display panel 100 may be provided with a mounting hole H, which is provided in the functional device placement area A1. The functional device placement area A1 also includes a border area A11 surrounding the mounting hole H. FIG2 illustrates an example in which the main display area A2 surrounds the functional device placement area A1. The functional device 300 may be installed in the mounting hole H.

[0071] Exemplarily, the border area A11 is configured to provide an encapsulation layer to prevent corrosion from water and oxygen.

[0072] In some embodiments, the shape of the functional device placement area A1 may be circular, diamond-shaped, rectangular, square, or elliptical, which is not specifically limited in the embodiments of the present disclosure.

[0073] Below, some embodiments of the present disclosure are schematically illustrated by taking the circular shape of the functional device setting area A1 as an example, but the implementation of the present disclosure is not limited to this, and any other shapes of functional device setting areas A1 can also be considered as long as the same technical concept is applied.

[0074] In some embodiments, as shown in FIG. 3 , the display panel 100 includes a substrate 10 and a plurality of data lines 20 .

[0075] The substrate 10 may be a flexible substrate 10 or a rigid substrate 10. The material used for the substrate 10 may include a polymer resin or glass. For example, the substrate 10 may be flexible, and the material used for the substrate 10 may include a polymer resin, such as one of polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate two formal acid glycol ester (PEN), polyethylene terephthalate (PET), polyphenylene sulfide granule (PPS), polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). Illustratively, the substrate 10 may be rigid and include a glass material containing SiO 2 as a main component.

[0076] It should be noted that the substrate 10 can be a single-layer structure or a multi-layer structure. For example, in the case of a multi-layer structure, the substrate 10 can include a base and a buffer layer provided on the base. The buffer layer is provided on the base. The material used for the buffer layer can include inorganic insulating materials such as silicon nitride (SiNx, x>0), silicon oxynitride (SiON) and silicon oxide (SiOx, x>0). The buffer layer is used to provide a good foundation for the formation of thin films when thin films are formed on the substrate 10.

[0077] 3 , a plurality of data lines 20 are disposed on a substrate 10 . The plurality of data lines 20 are spaced apart along a first direction X and extend along a second direction Y. The first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular.

[0078] In this document, "the data line 20 extends along the second direction Y" means that the overall routing direction of the data line 20 is along the second direction Y, but is not limited to the data line 20 strictly extending along the second direction Y at every position. In other words, "extending along the second direction Y" here includes not only data lines 20 that strictly extend along the second direction Y at every position, but also data lines 20 that are partially bent to avoid interference from other structures.

[0079] As shown in FIG. 3 , some embodiments of the present disclosure provide a display panel 100 including at least one first data line 22 . For example, the display panel 100 includes one first data line 22 , five first data lines 22 , or ten first data lines 22 .

[0080] The first data line 22 is disposed in the main display area A2 and includes a first data line segment 221, a first connecting line 222, and a second data line segment 223, which are connected in sequence. The first data line segment 221 and the second data line segment 223 both extend along the second direction Y and are disposed on either side of the functional device placement area A1 along the second direction Y. The extension direction of the first data line segment 221 and the extension direction of the second data line segment 223 coincide with each other and both pass through the functional device placement area A1. The first direction X intersects the second direction Y. Thus, along the second direction Y, the first data line segment 221 and the second data line segment 223 disposed on either side of the functional device placement area A1 can be connected via the first connecting line 222.

[0081] When the functional device 300 is arranged on the non-display side of the display panel 100, the first connecting line 222 is arranged in the main display area A2, so that the first connecting line 222 will not block light from entering the functional device 300, thereby enabling the functional device 300 to receive a sufficient amount of light.

[0082] When the functional device 300 is disposed in the mounting hole H, the first connecting line 222 is disposed in the main display area A2, which can reduce the number of connecting lines disposed in the border area A11, thereby reducing the size of the border area A11. Based on this, during the display process, the black border around the edge of the mounting hole H can be reduced, thereby increasing the screen-to-body ratio of the display panel 100 and improving the integrity of the low-definition display image.

[0083] In some embodiments, as shown in FIG2 , the peripheral area B includes a fan-out area B1 , which is disposed on one side of the display area A along the second direction Y. Exemplarily, the fan-out area B1 is disposed below the display area A, and the fan-out area B1 and the display area A share a common boundary (as shown in FIG2 ).

[0084] As shown in FIG2 , the main display area A2 further includes a central area A21 and an edge area A22 . The edge area A22 is disposed on at least one side of the central area A21 along the first direction X. For example, the edge area A22 is disposed on both sides of the central area A21 .

[0085] As shown in FIG. 4 , FIG. 5 and FIG. 6 , the plurality of data lines 20 further include a plurality of fourth data lines 24 . The plurality of fourth data lines 24 are disposed in the edge area A22 .

[0086] It should be noted that, when the functional device setting area A1 is set in the edge area A22 , the fourth data line 24 may be the first data line segment 221 of the first data line 22 described above.

[0087] On this basis, the display panel 100 further includes a plurality of fourth adapter lines 1011 , a plurality of fifth adapter lines 1021 , a plurality of first adapter blocks 1022 and a plurality of second adapter blocks 1023 .

[0088] The plurality of fourth transition lines 1011 are disposed in the central area A21 . The plurality of fourth transition lines 1011 extend along the second direction Y and are connected to the fan-out area B1 .

[0089] A plurality of fifth adapter lines 1021 are disposed in the edge region A22 and extend along the first direction to the center region A21. The plurality of fifth adapter lines 1021 are spaced apart along the second direction Y. At least a portion of the plurality of fifth adapter lines 1021 crosses over at least one data line 20 and is insulated from the crossed data line 20. The crossed data line 20 may be the fourth data line 24 and / or the first data line 22.

[0090] The fourth data line 24 and the portion of the fifth adapter line 1021 disposed in the edge area A22 are connected via a first adapter block 1022 , and the fourth adapter line 1011 and the portion of the fifth adapter line 1021 disposed in the center area A21 are connected via a second adapter block 1023 .

[0091] On this basis, as shown in FIG4 , the plurality of data lines 20 further include a plurality of fifth data lines 25 . The plurality of fifth data lines 25 are disposed in the central area A21 and are spaced apart along the first direction X. The plurality of fifth data lines 25 are directly connected to the fan-out area B1 . The fifth data lines 25 may be the first data lines 22 described above.

[0092] That is, the fifth data line 25 located in the center area A21 is directly connected to the fan-out area B1, while the fourth data line 24 located in the edge area A22 is connected to the fan-out area B1 via the fifth adapter line 1021 and the fourth adapter line 1011. This configuration can be referred to as fan-out in display area A (FIAA) or fan-out in panel (FIP). This configuration helps reduce the size of the fan-out area B1 along the second direction Y, thereby reducing the bezel width of the display panel 100 and facilitating a narrow bezel for the display device 1000.

[0093] In some embodiments, the display panel 100 further includes a first conductive layer 101 , a second conductive layer 102 , and a light emitting device layer.

[0094] As shown in FIG. 5 and FIG. 6 , the first conductive layer 101 is disposed on the substrate 10 , and the fourth data line 24 , the fifth data line 25 and the fourth transfer line 1011 are disposed on the first conductive layer 101 .

[0095] As shown in Figures 7 and 8 , the second conductive layer 102 is disposed between the substrate 10 and the first conductive layer 101. The fifth transfer line 1021, the first transfer block 1022 and the second transfer block 1023 are located in the second conductive layer 102.

[0096] The light-emitting device layer is disposed on a side of the first conductive layer 101 away from the substrate 10 and includes a plurality of light-emitting devices. For example, the light-emitting device layer comprises a first light-emitting device, a second light-emitting device, and a third light-emitting device each emitting different colors. The colors emitted by the first light-emitting device, the second light-emitting device, and the third light-emitting device constitute three primary colors. For example, the first light-emitting device emits red, the second light-emitting device emits blue, and the third light-emitting device emits green.

[0097] The light-emitting device includes a first electrode 30, a light-emitting functional layer, and a second electrode. The first electrode 30 serves as the anode of the light-emitting device, and the second electrode serves as the cathode of the light-emitting device; alternatively, the first electrode 30 serves as the cathode of the light-emitting device, and the second electrode serves as the anode of the light-emitting device. The embodiments disclosed herein are described using an example in which the first electrode 30 serves as the anode of the light-emitting stack, and the second electrode serves as the cathode of the light-emitting stack.

[0098] The first electrode 30 may have a single-layer structure or a stacked structure. For example, in the case of a stacked structure, the first electrode 30 includes indium tin oxide (ITO), silver (Ag), and ITO stacked together. A reflective electrode refers to an electrode having a reflectivity greater than 90%.

[0099] In some examples, the light-emitting functional layer includes only a light-emitting layer. Alternatively, in addition to the light-emitting layer, the light-emitting functional layer may further include at least one of an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL), and a hole injection layer (HIL).

[0100] In the related art, the flatness of the first electrode of the light emitting device is low, and the direction of the light emitted by the light emitting device will deviate, thereby causing color separation and color deviation problems in the display device, and reducing the display effect.

[0101] In order to solve the above technical problem, as shown in FIG9 , in some embodiments of the present disclosure, in the orthographic projection onto the substrate 10 , the first electrode 30 and the first adapter block 1022 and / or the second adapter block 1023 are staggered.

[0102] Setting it in this way can reduce the risk of the first electrode 30 protruding, thereby improving the flatness of the first electrode 30 and weakening the deviation in the direction of the light emitted by the light-emitting device, making the display brightness of the display panel 100 more uniform, improving the problems of color separation and color deviation of the display panel 100, and improving the display effect.

[0103] In some examples, the orthographic projection of the first electrode 30 on the substrate 10 and the orthographic projection of the first adapter block 1022 on the substrate 10 are staggered.

[0104] Arranged in this manner, the risk of the first adapter block 1022 causing the first electrode 30 to bulge can be reduced, thereby improving the flatness of the first electrode 30 and reducing the deviation in the direction of the light emitted by the light-emitting device, making the display brightness of the display panel 100 more uniform, improving the problems of color separation and color deviation of the display panel 100, and enhancing the display effect.

[0105] In some other examples, the orthographic projection of the first electrode 30 on the substrate 10 and the orthographic projection of the second adapter block 1023 on the substrate 10 are staggered.

[0106] Arranged in this manner, the risk of the second adapter block 1023 causing the first electrode 30 to bulge can be reduced, thereby improving the flatness of the first electrode 30 and reducing the deviation in the direction of the light emitted by the light-emitting device, making the display brightness of the display panel 100 more uniform, improving the problems of color separation and color deviation of the display panel 100, and enhancing the display effect.

[0107] In some other examples, in an orthographic projection onto the substrate 10 , the first electrode 30 is staggered with the first adapter block 1022 and the second adapter block 1023 .

[0108] Arranged in this manner, the risk of the first adapter block 1022 and the second adapter block 1023 causing the first electrode 30 to bulge can be reduced, thereby improving the flatness of the first electrode 30 and reducing the deviation in the direction of the light emitted by the light-emitting device, making the display brightness of the display panel 100 more uniform, improving the problems of color separation and color deviation of the display panel 100, and enhancing the display effect.

[0109] In some embodiments, as shown in Figures 5 and 9, the plurality of data lines 20 are divided into a plurality of data line groups 201. Each data line group 201 includes two data lines 20. The minimum spacing d1 between the two data lines 20 in a data line group 201 is greater than the minimum spacing d2 between two adjacent data line groups 20. The data lines 20 include alternating first straight segments 26 and first curved segments 27. The first straight segments 26 extend along the second direction Y, and the first curved segments 27 bend away from the other data lines 20 in the same data line group 20. Each fourth adapter line 1011 is disposed between the two data lines 20 in a data line group 201.

[0110] 9 , the plurality of first electrodes 30 include a plurality of first sub-electrodes 301 and a plurality of second sub-electrodes 302 . In the orthographic projection onto the substrate 10 , the first adapter block 1022 and the second adapter block 1023 are disposed on both sides of the fourth adapter line 1011 .

[0111] As shown in Figure 9, in an orthographic projection onto the substrate 10, one first sub-electrode 301 overlaps with two adjacent first bent segments 27, and the first adapter block 1022 at least partially overlaps with the first straight segment 26. This allows the first sub-electrode 301 and the first adapter block 1022 to be staggered, reducing the risk of the first sub-electrode 301 being embossed.

[0112] As shown in FIG9 , in an orthographic projection onto the substrate 10, a second sub-electrode 302 is disposed between two first straight segments 26 in a group, and the second adapter block 1023 at least partially overlaps with the fourth adapter line 1011 and is disposed between the first bent segments 27 on either side of the fourth adapter line 1011. This allows the second sub-electrode 302 and the second adapter block 1023 to be staggered, reducing the risk of the second sub-electrode 302 protruding.

[0113] It should be noted that the multiple first sub-electrodes 301 include the first electrode 30 of the first light-emitting device, the first electrode 30 of the first light-emitting device and at least one of the first electrode 30 of the first light-emitting device, and the multiple second sub-electrodes 302 include the first electrodes 30 of the remaining light-emitting devices.

[0114] In some embodiments, as shown in FIG9 , the first conductive layer 101 further includes a plurality of first power supply voltage signal lines 1012. Exemplarily, the first power supply voltage signal lines 1012 are configured to transmit VDD signals. The plurality of first power supply voltage signal lines 1012 are divided into a plurality of groups of first power supply voltage signal lines 1, each group of first power supply voltage signal lines 1 including two first power supply voltage signal lines 1012. A group of first power supply voltage signal lines 1 is disposed between two data lines 20 included in a group of data lines 201. Each fourth adapter line 1011 is disposed between two first power supply voltage signal lines 1012 included in a group of first power supply voltage signal lines 1, i.e., the second adapter block 1023 is disposed between two first power supply voltage signal lines 1012 included in a group of first power supply voltage signal lines 1.

[0115] As shown in Figure 9, in an orthographic projection onto the substrate 10, the first sub-electrode 301 is positioned between two mutually distant boundaries of two adjacent first power supply voltage signal lines 1012 in two adjacent groups of first power supply voltage signal lines 1. This arrangement allows the first sub-electrode 301 and the second adapter block 1023 to be staggered, reducing the risk of protrusions on the first sub-electrode 301.

[0116] In some embodiments, as shown in FIG9 , the second sub-electrode 302 is disposed between two mutually distant boundaries of two first power supply voltage signal lines 1012 included in a group of first power supply voltage signal lines 1. The first adapter block 1022 is disposed between two mutually adjacent boundaries of two mutually adjacent first power supply voltage signal lines 1012 in two adjacent groups of first power supply voltage signal lines 1. The second sub-electrode 302 is disposed between two mutually distant boundaries of the same group of first power supply voltage signal lines 1. This arrangement allows the second sub-electrode 302 and the first adapter block 1022 to be staggered, thereby reducing the risk of protrusions on the first sub-electrode 301.

[0117] In some embodiments, as shown in FIG9 , the first power supply voltage signal line 1012 includes alternately connected second straight segments 11 and second curved segments 12. The second straight segments 11 extend along the second direction Y, and the second curved segments 12 bend away from another first power supply voltage signal line 1012 in the same group of first power supply voltage signal lines 1. The second curved segments 12 and the first straight segments 26 are arranged side by side along the second direction Y.

[0118] As shown in FIG9 , when the second adapter block 1023 is disposed between two first power supply voltage signal lines 1012 included in a group of first power supply voltage signal lines 1, the second adapter block 1023 is disposed between two adjacent second bending sections 12. In this case, the space between the two adjacent second bending sections 12 is larger, and the second adapter block 1023 can be made larger, which helps to increase the facing area between the second adapter block 1023 and the fourth adapter line 1011, thereby increasing the contact area between the second adapter block 1023 and the fourth adapter line 1011, and improving the connection reliability and stability between the second adapter block 1023 and the fifth adapter line.

[0119] In some embodiments, as shown in Figures 7 and 8 , multiple first adapter blocks 1022 are arranged in rows along the first direction X and in columns along the second direction Y. First adapter blocks 1022 are provided in both the edge region A22 and the center region A21. This arrangement improves the pattern consistency of the second conductive layer 102 and reduces the difference in light reflection between the edge region A22 and the center region A21, improving the uniformity of light reflection from the display panel 100 and reducing the risk of mura on the display panel 100.

[0120] In some embodiments, as shown in Figures 7 and 8, multiple second adapter blocks 1023 are arranged in rows along the first direction X and in columns along the second direction Y. Second adapter blocks 1023 are provided in both the edge region A22 and the center region A21. This arrangement improves the pattern consistency of the second conductive layer 102. Furthermore, it reduces the difference in light reflection between the edge region A22 and the center region A21, improving the uniformity of light emitted by the display panel 100 and reducing the risk of mura on the display panel 100.

[0121] In some embodiments, as shown in FIG. 9 , the midline of the fifth adapter line 1021 extending along the first direction X coincides with the straight line formed by the intersection of the first straight segment 26 and the first bent segment 27 , and the first electrode 30 is disposed between two adjacent fifth adapter lines 1021 .

[0122] By setting it in this way, the first electrode 30 and the fifth adapter line 1021 can be staggered, reducing the risk of the fifth adapter line 1021 causing the first electrode 30 to bulge, thereby improving the flatness of the first electrode 30 and reducing the deviation in the direction of the light emitted by the light-emitting device, making the display brightness of the display panel 100 more uniform, improving the problems of color separation and color deviation of the display panel 100, and enhancing the display effect.

[0123] In some embodiments, as shown in FIG9 , in an orthographic projection onto the substrate 10, the portion where the first sub-electrode 301 overlaps the data line 20 is symmetrical about the fifth axis X5 and / or the sixth axis X6. The fifth axis X5 extends along the first direction X and passes through the center of the first sub-electrode 301, while the sixth axis extends along the second direction Y and passes through the center of the first sub-electrode 301. This arrangement improves the height uniformity and flatness of the first sub-electrode 301.

[0124] In some examples, in an orthographic projection onto the substrate 10, the portion where the first sub-electrode 301 overlaps the data line 20 is symmetrical about the fifth axis. In this manner, the height of the first sub-electrode 301 on both sides along the second direction Y is more consistent, and the first sub-electrode 301 has a higher flatness.

[0125] In other examples, in an orthographic projection onto the substrate 10, the overlapping portion of the first sub-electrode 301 and the data line 20 is symmetrical about the sixth axis. In this manner, the height of the first sub-electrode 301 on both sides along the first direction X is more consistent, and the first sub-electrode 301 has a higher flatness.

[0126] In yet other examples, as shown in FIG9 , in an orthographic projection onto the substrate 10, the portion where the first sub-electrode 301 overlaps the data line 20 is symmetrical about the fifth axis X5 and the sixth axis X6. This arrangement improves the height uniformity of the first sub-electrode 301 along the first direction X and along the second direction Y, resulting in a higher flatness of the first sub-electrode 301.

[0127] In some embodiments, as shown in FIG9 , in an orthographic projection onto the substrate 10, the midline between the second sub-electrode 302 and the fourth transition line 1011 passes through the center of the second sub-electrode 302. This arrangement ensures good height consistency between the left and right sides of the second sub-electrode 302, and improves the flatness of the second sub-electrode 302. The midline between the second sub-electrode 302 and the fourth transition line 1011 may include a first midline extending along the first direction X and / or a second midline extending along the second direction X.

[0128] In some examples, the first center line passes through the center of the second sub-electrode 302 . In this way, the height consistency of the second sub-electrode 302 on both sides along the second direction Y is better, and the flatness of the second sub-electrode 302 is higher.

[0129] In other examples, the second center line passes through the center of the second sub-electrode 302 . In this way, the height consistency of the second sub-electrode 302 on both sides along the first direction X is better, and the flatness of the second sub-electrode 302 is higher.

[0130] In some other examples, the first center line passes through the center of the second sub-electrode 302, and the second center line passes through the center of the second sub-electrode 302. In this arrangement, the height uniformity of the second sub-electrode 302 on both sides along the first direction X is better, and the height uniformity of the second sub-electrode 302 on both sides along the second direction Y is better, and the flatness of the second sub-electrode 302 is higher.

[0131] In some embodiments, as shown in FIG10 , a plurality of data lines 20 and a plurality of fourth patch cables 1011 are alternately arranged. The plurality of first electrodes 30 include a plurality of third sub-electrodes 303, a plurality of fourth sub-electrodes 304, and a plurality of fifth sub-electrodes 305. Exemplarily, the third sub-electrode 303 is one of the first electrode 30 in the first light-emitting device, the first electrode 30 in the second light-emitting device, and the first electrode 30 in the third light-emitting device; the fourth sub-electrode 304 is one of the first electrodes 30 in the remaining two light-emitting devices; and the fifth sub-electrode 305 is the first electrode 30 in the last light-emitting device.

[0132] In some embodiments, as shown in Figure 10, in an orthographic projection onto the substrate 10, the third sub-electrode 303 overlaps with the adjacent data line 20 and the fourth adapter line 1011, and the overlapping portions are symmetrical about the ninth axis X9 and / or the tenth axis X10. The ninth axis X9 extends along the first direction X and passes through the center of the third sub-electrode 303, while the tenth axis X10 extends along the second direction Y and passes through the center of the third sub-electrode 303. This arrangement ensures greater height uniformity and flatness of the third sub-electrode 303. The data line 20 overlapping the third sub-electrode 303 may be the first data line 22 and / or the fifth data line 25.

[0133] In some examples, in an orthographic projection onto the substrate 10, the portions of the third sub-electrode 303 that overlap with the adjacent data line 20 and the fourth adapter line 1011 are symmetrical about the ninth axis X9. This arrangement allows for greater height consistency of the second sub-electrode 302 on both sides along the second direction Y, and a higher degree of flatness for the third sub-electrode 303.

[0134] In other examples, in an orthographic projection onto the substrate 10, the portions of the third sub-electrode 303 that overlap with the adjacent data line 20 and the fourth adapter line 1011 are symmetrical about the tenth axis X10. This arrangement provides greater height consistency between the two sides of the third sub-electrode 303 along the second direction Y, resulting in a higher degree of flatness for the third sub-electrode 303.

[0135] In some other examples, in an orthographic projection onto the substrate 10, the portions of the third sub-electrode 303 that overlap with the adjacent data line 20 and the fourth interconnect line 1011 are symmetrical about the ninth axis X9 and the tenth axis X10. In this arrangement, the second sub-electrode 302 has better height consistency along both sides of the first direction X, and the second sub-electrode 302 has better height consistency along both sides of the first direction X, resulting in a higher flatness of the second sub-electrode 302.

[0136] In some embodiments, as shown in Figure 10, in an orthographic projection onto the substrate 10, the fourth sub-electrode 304 overlaps with two data lines 20 and two fourth transfer lines 1011, and the overlapping portions are symmetrical about the eleventh axis X11 and / or the twelfth axis X12. The eleventh axis X11 extends along the first direction X and passes through the center of the fourth sub-electrode 304, while the twelfth axis X12 extends along the second direction Y and passes through the center of the fourth sub-electrode 304. This arrangement improves the height uniformity and flatness of the third sub-electrode 303. The data line 20 overlapping the fourth sub-electrode 304 may be the first data line 22 and / or the fifth data line 25.

[0137] In some examples, in an orthographic projection onto the substrate 10, the portions of the fourth sub-electrode 304 that overlap with the two data lines 20 and the two fourth transfer lines 1011 are symmetrical about the eleventh axis X11. This arrangement allows for greater height consistency between the second sub-electrode 302 on both sides along the second direction Y, and for greater flatness of the third sub-electrode 303.

[0138] In other examples, in an orthographic projection onto the substrate 10, the portions of the fourth sub-electrode 304 that overlap with the two data lines 20 and the two fourth transfer lines 1011 are symmetrical about the twelfth axis X12. In this arrangement, the height of the third sub-electrode 303 on both sides along the first direction X is highly consistent, and the third sub-electrode 303 has a high degree of flatness.

[0139] In some other examples, in an orthographic projection onto the substrate 10, the portions of the fourth sub-electrode 304 that overlap with the two data lines 20 and the two fourth transfer lines 1011 are symmetrical about the eleventh axis X11 and the twelfth axis X12. In this arrangement, the second sub-electrode 302 has better height consistency along both sides of the first direction X, and the second sub-electrode 302 has better height consistency along both sides of the second direction Y, resulting in a higher flatness of the second sub-electrode 302.

[0140] In some embodiments, as shown in FIG10 , in an orthographic projection onto the substrate 10, the fifth sub-electrode 305 overlaps with the adjacent data line 20 and the fourth patch cord 1011, and the overlapping portions are symmetrical about the center of the fifth sub-electrode 305. This arrangement ensures that the overlapping portions of the fifth sub-electrode 305, the adjacent data line 20 and the fourth patch cord 1011, have approximately equal maximum and minimum distances from the thirteenth axis X13 in the first direction X, and approximately equal maximum and minimum distances from the fourteenth axis X14 in the second direction Y. This balances the height of the fifth sub-electrode 305 in the first direction X and in the second direction Y, improving the flatness of the fifth sub-electrode 305. The thirteenth axis X13 extends along the second direction Y and passes through the center of the fifth sub-electrode 305, while the fourteenth axis X14 extends along the first direction X and passes through the center of the fifth sub-electrode 305. The data line 20 overlapping the fifth sub-electrode 305 may be the first data line 22 and / or the fifth data line 25.

[0141] In some embodiments, the display panel 100 further includes a plurality of first scan signal lines 40 and a plurality of first initialization signal lines 50 .

[0142] Among them, multiple first scan signal lines 40 extend along the first direction X and are spaced apart along the second direction Y. Multiple first initialization signal lines 50 extend along the first direction X and are spaced apart along the second direction Y. A first initialization signal line 50 is located between a first scan signal line 40 and a fifth transfer line (in the second direction Y, the first initialization signal line 50 is located between the first scan signal line 40 and the fifth transfer line; and / or, in the third direction Z, the first initialization signal line 50 is located between the first scan signal line 40 and the fifth transfer line. Wherein, the third direction Z is perpendicular to the substrate 10). In this way, the first initialization signal line 50 arranged between the first scan signal line 40 and the fifth transfer line 1021 can reduce the interference of the first scan signal line 40 on the fifth transfer line 1021.

[0143] In some examples, as shown in Figures 11 to 13, the display panel 100 further includes a third conductive layer 103 and a fourth conductive layer 104. The third conductive layer 103 is disposed between the second conductive layer 102 and the substrate 10, and a plurality of first scan signal lines 40 are disposed in the third conductive layer 103. Exemplarily, the first scan signal lines 40 are configured to transmit a Reset (H) signal.

[0144] As shown in FIG12 , the fourth conductive layer 104 is disposed between the third conductive layer 103 and the second conductive layer 102 , and a plurality of first initialization signal lines 50 are disposed in the fourth conductive layer 104 . Exemplarily, the first initialization signal lines 50 are configured to transmit first initialization signals.

[0145] As shown in FIG13 , in an orthographic projection onto the substrate 10, the first initialization signal line 50 and the first scan signal line 40 overlap, and the fifth transfer line 1021 is disposed within the first initialization signal line 50. The first initialization signal line 50 can reduce interference from the first scan signal line 40 on the fifth transfer line 1021.

[0146] On this basis, as shown in FIG11 , the third conductive layer 103 further includes a plurality of third scan signal lines 1032 and a plurality of fourth scan signal lines 1033. The plurality of third scan signal lines 1032 and the plurality of fourth scan signal lines 1033 extend along the first direction X and are spaced apart along the second direction Y. The third scan signal lines 1032 are configured to transmit EM scan signals, and the fourth scan signal lines 1033 are configured to transmit Reset(p) scan signals.

[0147] As shown in FIG12 , the fourth conductive layer 104 further includes a plurality of fourth initialization signal lines 1043, a plurality of fifth initialization signal lines 1044, and a plurality of fifth scan signal lines 1045. The plurality of fourth initialization signal lines 1043, the plurality of fifth initialization signal lines 1044, and the plurality of fifth scan signal lines 1045 all extend along the first direction X and are spaced apart along the second direction Y. The fourth initialization signal lines 1043 are configured to transmit the second initialization signal, the fifth initialization signal lines 1044 are configured to transmit the third initialization signal, and the fifth scan signal lines 1045 are configured to transmit the Gata(n) scan signal.

[0148] In other examples, as shown in FIG14 , the display panel 100 further includes a fifth conductive layer 105. The fifth conductive layer 105 is disposed between the second conductive layer 102 and the substrate 10, and the first scan signal line 40 is disposed in the fifth conductive layer 105. Exemplarily, the first scan signal line 40 is configured to transmit a Gata scan signal.

[0149] On this basis, as shown in FIG15 , the display panel 100 further includes a sixth conductive layer 106. The sixth conductive layer 106 is disposed between the fifth conductive layer 105 and the second conductive layer 102. A plurality of first initialization signal lines 50 are disposed in the sixth conductive layer 106. Exemplarily, the first initialization signal lines 50 are configured to transmit a fourth initialization signal.

[0150] As shown in FIG16 , the plurality of first initialization signal lines 50, the plurality of first scan signal lines 40, and the fifth transfer line 1021 are divided into a plurality of groups, each group including a first initialization signal line 50, a first scan signal line 40, and a fifth transfer line 1021. In an orthographic projection onto the substrate 10, the first initialization signal line 50 in a group is arranged between the first scan signal line 40 and the fifth transfer line 1021. Arranged in this manner, on the one hand, the first scan signal line 40 and the fifth transfer line 1021 can be staggered, which can reduce the risk of parasitic capacitance forming between the first scan signal line 40 and the fifth transfer line 1021. On the other hand, the first initialization signal line 50 can reduce the interference of the first scan signal line 40 on the fifth transfer line 1021.

[0151] 14 , the fifth conductive layer 105 may further include a plurality of sixth scan signal lines 1056 and a plurality of seventh scan signal lines 1057. The sixth scan signal lines 1056 and the seventh scan signal lines 1057 extend along the first direction X and are spaced apart along the second direction Y. The sixth scan signal lines 1056 are configured to transmit a Reset scan signal, and the seventh scan signal lines 1057 are also configured to transmit an EM scan signal.

[0152] As shown in Figures 15 and 16 , the sixth conductive layer 106 may further include a plurality of seventh initialization signal lines 1062 configured to transmit a fifth initialization signal. The plurality of seventh initialization signal lines 1062 extend along the first direction X and are spaced apart along the second direction Y. The seventh initialization signal lines 1062 are disposed on a side of the fifth adapter line 1021 away from the first initialization signal line 50.

[0153] In some embodiments, as shown in FIG16 , in an orthographic projection onto the substrate 10, the second adapter block 1023 is disposed on a side of the fifth adapter line 1021 connected to the second adapter block 1023 that is away from the first scan signal line 40. This arrangement allows the second adapter block 1023 and the first scan signal line 40 to be staggered, reducing the risk of parasitic capacitance between the second adapter block 1023 and the first scan signal line 40.

[0154] In some embodiments, as shown in Figures 4, 5, 6, and 9, the fourth patch cable 1011 has a first opening K1, which divides the first patch cable 2221 into a first routing segment L1 and a second routing segment L2. The first routing segment L1 is located on the side of the second routing segment L2 that is closer to the fan-out area B1. One end of the first routing segment L1 is connected to the fan-out area B1, and the other end is connected to the fifth patch cable 1021. This arrangement helps to shorten the transmission path of the data signal on the fourth patch cable 1011, thereby reducing the voltage drop during the transmission of the data signal on the fourth patch cable 1011.

[0155] Exemplarily, the second routing segment L2 can also be used to transmit other signals. For example, the second routing segment L2 can be electrically connected to the third power supply voltage signal line VSS and to the cathode layer. In other words, the second routing segment L2 is arranged in parallel with the cathode layer, which helps reduce the resistance of the cathode layer.

[0156] In some embodiments, as shown in FIG9 , in an orthographic projection onto the substrate 10, the first opening K1 is staggered with the first electrode 30. This arrangement reduces the risk of the first electrode 30 being recessed, thereby improving the flatness of the first electrode 30 and reducing the deviation in the direction of light emitted by the light-emitting device. This makes the display brightness of the display panel 100 more uniform, improves the color separation and color shift problems of the display panel 100, and enhances the display effect.

[0157] In some embodiments, as shown in Figures 7 and 9 , second conductive layer 102 further includes multiple power supply voltage blocks 1024. Power supply voltage blocks 1024 are connected to first power supply voltage signal line 1012. That is, power supply voltage blocks 1024 are configured to transmit power supply voltage signals. This arrangement places power supply voltage blocks 1024 and first power supply voltage signal line 1012 in parallel, which helps reduce the resistance of first power supply voltage signal line 1012.

[0158] 9 , in the orthographic projection onto the substrate 10 , the first opening K1 is disposed within the range of the power supply voltage block 1024. In this manner, the first opening K1 can also reflect light, thereby reducing the risk of uneven light reflection in the display panel 100 when the screen is off.

[0159] In some embodiments, as shown in FIG17 , the display panel 100 further includes a seventh conductive layer 107. The seventh conductive layer 107 is disposed between the second conductive layer 102 and the substrate 10 and includes a plurality of spacers 1071. As shown in FIG18 , in an orthographic projection onto the substrate 10, the first opening K1 is disposed within the spacers 1071. This arrangement allows light to be reflected from the first opening K1, thereby reducing the risk of uneven light reflection when the display panel 100 is off.

[0160] In some embodiments, as shown in Figures 7 and 8, the fifth patch cable 1021 has a second opening K2 and a third opening K3. The second opening K2 and the third opening K3 divide the fifth patch cable 1021 into a third routing segment L3, a fourth routing segment L4, and a fifth routing segment L5. As shown in Figures 9 and 10, one end of the fourth routing segment L4 is connected to the first adapter block 1022, and the other end is connected to the second adapter block 1023. The third routing segment L3 and the fifth routing segment L5 are arranged on both sides of the fourth routing segment L4. This arrangement helps to reduce the transmission path of the data signal on the fifth patch cable 1021, thereby reducing the voltage drop during the transmission of the data signal on the fifth patch cable 1021.

[0161] Exemplarily, the second routing segment L2 can also be used to transmit other signals. For example, the second routing segment L2 can be electrically connected to the third power supply voltage signal line VSS and to the cathode layer. In other words, the second routing segment L2 is arranged in parallel with the cathode layer, which helps reduce the resistance of the cathode layer.

[0162] In some embodiments, as shown in Figures 9 and 10, the first electrode 30 and the second opening K2 and / or the third opening K3 are staggered in an orthographic projection onto the substrate 10. This arrangement reduces the risk of the first electrode 30 being recessed, thereby improving the flatness of the first electrode 30 and reducing the deviation in the direction of light emitted by the light-emitting device. This makes the display brightness of the display panel 100 more uniform, improves the color separation and color shift problems of the display panel 100, and enhances the display effect.

[0163] 10 , the second opening K2 and / or the third opening K3 are disposed within the data line 20. In this manner, the first opening K1 can also reflect light, thereby reducing the risk of uneven light reflection on the display panel 100 when the screen is off.

[0164] In some embodiments, as shown in FIG9 , the first conductive layer 101 includes a first power supply voltage signal line 1012. In an orthographic projection onto the substrate 10, the second opening K2 and / or the third opening K3 are disposed within the range of the first power supply voltage signal line 1012. This arrangement allows light to be reflected from the first opening K1, thereby reducing the risk of uneven light reflection when the display panel 100 is off.

[0165] In some embodiments, as shown in FIG17 , the display panel 100 further includes an eighth conductive layer 108 . The eighth conductive layer 108 is disposed between the substrate 10 and the second conductive layer 102 . The eighth conductive layer 108 includes a plurality of third initialization signal lines 1081 . The third initialization signal line 1081 includes at least a portion extending along the second direction Y. In an orthographic projection onto the substrate 10 , the fourth transfer line 1011 overlaps with the portion of the third initialization signal line 1081 extending along the second direction Y. Providing the overlapping portion of the fourth transfer line 1011 and the third initialization signal line 1081 in this manner can reduce the light-shielding area of ​​the fourth transfer line 1011 and the third initialization signal line 1081 , thereby increasing the light-transmitting area of ​​the display panel 100 and improving the light transmittance of the display panel 100 .

[0166] It is understandable that the third initialization signal line 1081 may further include a portion extending along the first direction X.

[0167] 17 , the plurality of third initialization signal lines 1081 include a plurality of eighth initialization signals 1088 and a plurality of ninth initialization signals 1089. When the display panel 100 includes the sixth conductive layer 106, the eighth conductive layer 108 is disposed between the sixth conductive layer 106 and the substrate 10.

[0168] As shown in FIG19 , multiple eighth initialization signals 1088 are connected to the first initialization signal line 50. That is, multiple eighth initialization signals 1088 and multiple first initialization signal lines 50 are connected in parallel to form a grid structure, which is beneficial for reducing the power consumption of the display panel 100. Multiple ninth initialization signals 1089 are connected to the multiple seventh initialization signal lines 1062. That is, multiple ninth initialization signals 1089 and multiple seventh initialization signal lines 1062 form a grid structure, which is beneficial for reducing the power consumption of the display panel 100.

[0169] 17 , the eighth conductive layer 108 includes a plurality of second power supply voltage signal lines 1083. For example, the second power supply voltage signal lines 1083 are configured to transmit VDD signals. The plurality of second power supply voltage signal lines 1083 are spaced apart along the first direction X and extend along the second direction Y.

[0170] In some embodiments, as shown in FIG. 17 , the eighth conductive layer 108 is multiplexed into the seventh conductive layer 107 .

[0171] In some embodiments, as shown in FIG3 , the plurality of data lines 20 includes at least one second data line 21. The second data line 21 includes a third data line segment 211, a second connecting line 212, and a fourth data line segment 213, which are sequentially connected. The third data line segment 211 and the fourth data line segment 213 are both located in the main display area A2. The third data line segment 211 and the fourth data line segment 213 extend along the second direction Y and are located on both sides of the functional device arrangement area A1 along the second direction Y. The extension direction of the third data line segment 211 coincides with the extension direction of the fourth data line segment 213. The second connecting line 212 is located in the border area A11.

[0172] It can be understood that, compared to the case where the first data line segment 221 and the first connection line 222 connected to the first data line segment 221 are arranged on different sides of the first axis X1, the first data line segment 221 and the first connection line 222 connected to the first data line segment 221 are arranged on the same side of the first axis X. This facilitates reducing the length of the first connection line 222 connecting the first data line segment 221 and the second data line segment 223, thereby reducing the capacitive load between the first data line segment 221 and the second data line segment 223. Therefore, to reduce the capacitive load, the first data line segment 221 and the first connection line 222 connected to the first data line segment 221 are generally arranged on the same side of the first axis X. The first axis X1 extends along the second direction Y and passes through the center of the functional device arrangement area A1.

[0173] In the following, some embodiments of the present disclosure are schematically described by taking the example that the first data line segment 221 and the first connection line 222 connected to the first data line segment 221 are arranged on the same side of the first axis X.

[0174] In some examples, along the first direction X, the functional device arrangement area A1 may be arranged at the center of the main display area A2 or at the edge of the main display area A2.

[0175] Exemplarily, the functional device placement area A1 is disposed at the edge of the main display area A2. Thus, there is less space in the functional device placement area A1 on the side away from the centerline of the main display area A2 extending along the second direction Y, and less space for disposing the first connection line 222. Therefore, the data line segments disposed on the side of the first axis X1 away from the centerline of the main display area A2 extending along the second direction Y are partially connected by the first connection line 222 and partially connected by the second connection line 212. There is more space in the functional device placement area A1 on the side closer to the centerline of the main display area A2, and more space for disposing the first connection line 222. Therefore, all data line segments disposed on the side of the first axis X1 close to the centerline of the main display area A2 are connected by the first connection line 222. That is, the data line segments arranged on the side of the midline extending along the second direction Y away from the main display area A2 along the first axis X1 include the first data line segment 221, the second data line segment 223, the third data line segment 211 and the fourth data line segment 213. The data lines arranged on the side of the midline extending along the second direction Y close to the main display area A2 along the first axis X1 only include the first data line segment 221 and the second data line segment 223.

[0176] For example, in the data line segments arranged on the side of the midline of the first axis X1 extending away from the main display area A2 along the second direction Y, the data line segments close to the first axis X1 are connected by the second connecting line 212, and the data line segments away from the first axis X1 are connected by the first connecting line 222.

[0177] Alternatively, for example, the functional device arrangement area A1 is arranged at the center of the main display area A2, but the size of the functional device arrangement area A1 along the second direction Y is larger. Thus, there is less space on both sides of the functional device arrangement area A1 along the second direction Y, and less space for arranging the first connecting line 222. The data line segments arranged on both sides of the first axis X1 are partially connected by the first connecting line 222, and partially connected by the second connecting line 212. That is, the data line segments arranged on one side of the first axis X1 include the first data line segment 221, the second data line segment 223, the third data line segment 211, and the fourth data line segment 213, and the data line segments arranged on the other side of the first axis X1 also include the first data line segment 221, the second data line segment 223, the third data line segment 211, and the fourth data line segment 213.

[0178] For example, the data line segments close to the first axis X1 are connected via the second connection line 212 , and the data line segments far from the first axis X1 are connected via the first connection line 222 .

[0179] On this basis, the second connection line 212 is parallel to the boundary of the functional device placement area A1.

[0180] It should be noted that the second connection line 212 being parallel to the boundary of the functional device placement area A1 means that the second connection line 212 is equidistant from the boundary of the functional device placement area A1 .

[0181] In some embodiments, as shown in FIG. 3 , the first data line segment 221 , the second data line segment 223 , and the second data line 21 described above are disposed in the first conductive layer 101 .

[0182] The first connection line 222 includes a first adapter line 2221, a second adapter line 2222, and a third adapter line 2223, which are connected in sequence. One of the first adapter line 2221 and the third adapter line 2223 is connected to the first data line segment 221, and the other is connected to the second data line segment 223 corresponding to the first data line segment 221. In this way, the data signal in the first data line segment 221 can be transmitted to the corresponding second data line segment 223 through the first adapter line 2221, the second adapter line 2222, and the third adapter line 2223.

[0183] Exemplarily, the first data line segment 221 is connected to the first patch line 2221, and the second data line segment 223 is connected to the third patch line 2223. Alternatively, exemplary, the first data line segment 221 is connected to the third patch line 2223, and the second data line segment 223 is connected to the first patch line 2221.

[0184] The following takes the connection between the first data line segment 221 and the first adapter line 2221 , and the connection between the second data line segment 223 and the third adapter line 2223 as an example to schematically illustrate some embodiments of the present disclosure.

[0185] As shown in Figure 3, the first adapter line 2221 and the third adapter line 2223 are both disposed in the second conductive layer 102 and extend along the first direction X. The second adapter line 2222 is disposed in the first conductive layer 101 and extends along the second direction Y. Along the first direction X, the second adapter line 2222 is disposed on one side of the functional device placement area A1. The plurality of data lines 20 also includes a plurality of third data lines 23. The plurality of third data lines 23 are disposed in the first conductive layer 101, extending along the second direction Y and disposed on both sides of the functional device placement area A1 along the second direction Y. A second adapter line 2222 is disposed between two adjacent third data lines 23.

[0186] 3 , the display panel 100 includes a plurality of first data lines 22 , ie, a plurality of second adapter lines 2222 spaced apart along the first direction X. The first data line segments 221 and the second adapter lines 2222 are disposed on the same side of the first axis X1 .

[0187] As the distance between the first data line segments 221 and the second axis X2 decreases away from the first axis X1, the length of the first data line segments 221 increases. As the distance away from the first axis X1 increases, the first data line segments 221 sequentially connect to the second adapter lines 2222 located farther from the functional device placement area A1 among the plurality of second adapter lines 2222. The second axis X2 extends along the first direction X and passes through the center of the functional device placement area A1.

[0188] This arrangement reduces the distance between the first data line segment 221 and the second adapter line 2222 connected thereto in a direction away from the first axis X1, thereby reducing the lengths of the first adapter line 2221 and the third adapter line 2223 disposed between the first data line segment 221 and the second adapter line 2222 in a direction away from the first axis X1. In other words, the longer first data line segment 221 is connected to the shorter first adapter line 2221 disposed between the first data line 22 and the second adapter line 2222; and the longer second data line segment 223 is connected to the shorter third adapter line 2223 disposed between the first data line 22 and the second adapter line 2222. This reduces the differences in the effective lengths of the multiple first data lines 22, thereby reducing differences in the capacitive loads between the multiple first data lines 22 and improving the brightness uniformity of the display panel 100.

[0189] Among them, the effective length of the first data line 22 refers to the total length of the first data line segment 221, the first adapter line 2221 arranged between the first data line segment 221 and the second adapter line 2222, the second adapter line 2222 arranged between the first adapter line 2221 and the third adapter line 2223, the third adapter line 2223 arranged between the second data line segment 223 and the second adapter line 2222, and the second data line 21.

[0190] 3 , the display panel 100 further includes a plurality of first data lines 22 , namely a plurality of first transfer lines 2221 and a plurality of third transfer lines 2223 , which are spaced apart along the second direction Y. The first transfer lines 2221 and the third transfer lines 2223 are disposed on both sides of the second axis X2 .

[0191] In some examples, along a direction away from the first axis X1 , the plurality of first data line segments 221 are sequentially connected to the first transfer lines 2221 that are farther away from the second axis X2 among the plurality of first transfer lines 2221 .

[0192] This arrangement reduces the distance between the first adapter line 2221 and the third adapter line 2223 connected thereto in a direction away from the first axis X1, thereby reducing the length of the second adapter line 2222, which is disposed between the first adapter line 2221 and the third adapter line 2223, in the direction away from the first axis X1. In this way, the longer first data line segment 221 is connected to the shorter second adapter line 2222, which is disposed between the first adapter line 2221 and the third adapter line 2223. This reduces the differences in the effective lengths of the multiple first data lines 22, thereby reducing the differences in the capacitive loads among the multiple first data lines 22, and thus improving the brightness uniformity of the display panel 100.

[0193] In some examples, along a direction away from the first axis X1 , the plurality of second data line segments 223 are sequentially connected to the third transfer lines 2223 , which are farther from the second axis X2 , among the plurality of third transfer lines 2223 .

[0194] This arrangement reduces the distance between the third adapter line 2223 and the first adapter line 2221 connected thereto in a direction away from the first axis X1, thereby reducing the length of the second adapter line 2222, which is disposed between the third adapter line 2223 and the first adapter line 2221, in the direction away from the first axis X1. In this way, the longer first data line segment 221 is connected to the shorter second adapter line 2222, which is disposed between the third adapter line 2223 and the first adapter line 2221. This reduces the differences in the effective lengths of the multiple first data lines 22, thereby reducing the differences in the capacitive loads among the multiple first data lines 22, and thus improving the brightness uniformity of the display panel.

[0195] In some examples, along the direction away from the first axis X1, multiple first data line segments 221 are sequentially connected to the first adapter line 2221 among the multiple first adapter lines 2221, which is farther away from the second axis X2, and multiple second data line segments 223 are sequentially connected to the third adapter line 2223 among the multiple third adapter lines 2223, which is farther away from the second axis X2.

[0196] This arrangement reduces the distance between the first adapter line 2221 and the third adapter line 2223 connected thereto in a direction away from the first axis X1, thereby reducing the length of the second adapter line 2222, which is disposed between the first adapter line 2221 and the third adapter line 2223, in the direction away from the first axis X1. In this way, the longer first data line segment 221 is connected to the shorter second adapter line 2222, which is disposed between the first adapter line 2221 and the third adapter line 2223. This reduces the differences in the effective lengths of the multiple first data lines 22, thereby reducing the differences in the capacitive loads among the multiple first data lines 22, and thus improving the brightness uniformity of the display panel.

[0197] In some embodiments, as shown in FIG. 3 , the second adapter line 2222 passes through the main display area A2 along the second direction Y. That is, in the main display area A2 , the length of the second adapter line 2222 along the second direction Y is substantially the same as the length of the third data line 23 .

[0198] As shown in Figure 3, the third adapter cable 2223 further has a fourth opening K4 and a fifth opening K5, which divide the second adapter cable 2222 into a sixth routing segment L6, a seventh routing segment L7, and an eighth routing segment L8. One end of the seventh routing segment L7 is connected to the first adapter cable 2221, and the other end is connected to the third adapter cable 2223. The sixth routing segment L6 and the eighth routing segment L8 are provided on either side of the seventh routing segment L7.

[0199] Arranged in this manner, it is beneficial to shorten the transmission path of the data signal on the second adapter line 2222 , thereby reducing the voltage drop of the data signal during transmission on the second connecting line 212 .

[0200] Exemplarily, the sixth and eighth routing segments L6 and L8 can also be used to transmit other signals. For example, the display panel 100 further includes a third power supply voltage signal line VSS disposed within the peripheral area B and at least partially surrounding the display area A. The third power supply voltage signal line VSS can, for example, be electrically connected to the cathode layer of the light-emitting device. The sixth and eighth routing segments L6 and L8 can be electrically connected to the third power supply voltage signal line VSS and to the cathode layer. In other words, the sixth and eighth routing segments L6 and L8 are disposed in parallel with the cathode layer, which helps reduce the resistance of the cathode layer.

[0201] In some embodiments, as shown in FIG. 3 , the first adapter line 2221 penetrates the main display area A2 along the first direction X, and both ends of the first adapter line 2221 along the first direction X extend to edges of the main display area A2 .

[0202] As shown in Figure 3, the first adapter cable 2221 further has a sixth opening K6 and a seventh opening K7, which divide the first adapter cable 2221 into a ninth routing segment L9, a tenth routing segment L10, and an eleventh routing segment L11. One end of the tenth routing segment L10 is connected to the first data line segment 221, and the other end is connected to the second adapter cable 2222. The ninth routing segment L9 and the eleventh routing segment L11 are disposed on either side of the tenth routing segment L10.

[0203] Arranged in this manner, it is beneficial to shorten the transmission path of the data signal on the first adapter line 2221 , thereby reducing the voltage drop of the data signal during transmission on the first adapter line 2221 .

[0204] Illustratively, the ninth routing segment L9 and the eleventh routing segment L11 can also be used to transmit other signals. For example, the ninth routing segment L9 and the eleventh routing segment L11 can be electrically connected to the third power supply voltage signal line VSS and to the cathode layer. In other words, the ninth routing segment L9 and the eleventh routing segment L11 are arranged in parallel with the cathode layer, which helps reduce the resistance of the cathode layer.

[0205] In some embodiments, as shown in FIG. 3 , the third adapter line 2223 penetrates the main display area A2 along the second direction Y, and both ends of the third adapter line 2223 along the second direction Y extend to edges of the main display area A2 .

[0206] As shown in FIG3 , the third adapter cable 2223 further has an eighth opening K8 and a ninth opening K9, which divide the third adapter cable 2223 into a twelfth routing segment L12, a thirteenth routing segment L13, and a fourteenth routing segment L14. One end of the twelfth routing segment L12 is connected to the second data line segment 223, and the other end is connected to the second adapter cable 2222. The twelfth routing segment L12 and the fourteenth routing segment L14 are disposed on either side of the thirteenth routing segment L13.

[0207] Arranged in this manner, it is beneficial to shorten the transmission path of the data signal on the third adapter line 2223 , thereby reducing the voltage drop of the data signal during transmission on the third adapter line 2223 .

[0208] For example, the ninth routing segment L9 and the eleventh routing segment L11 can also be used to transmit other signals. For example, the twelfth routing segment L12 and the fourteenth routing segment L14 can be electrically connected to the third power supply voltage signal line VSS and to the cathode layer. In other words, the twelfth routing segment L12 and the fourteenth routing segment L14 are arranged in parallel with the cathode layer, which helps reduce the resistance of the cathode layer.

[0209] 3 , the display panel includes a plurality of first data lines 22, that is, the display panel includes a plurality of first connection lines 222. The plurality of first connection lines 222 are disposed on both sides of the first axis X1.

[0210] In this way, along the first direction X, the space on both sides of the functional device setting area A1 can be used to set the first connection line 222, that is, more first connection lines 222 can be set in the display panel, thereby further reducing the number of connection lines set in the functional device setting area A1.

[0211] On this basis, the plurality of first connection lines 222 are symmetrical about the first axis X1. This arrangement allows the lengths of the first connection lines 222 between two first data line segments 221 and corresponding second data line segments 223 that are symmetrical about the first axis X1 to be the same, thereby allowing the capacitive loads between the two first data line segments 221 and corresponding second data line segments 223 that are symmetrical about the first axis X1 to be the same. This allows the display brightness on both sides of the first axis X1 to be the same, thereby improving the uniformity of the display brightness of the display panel 100 and reducing the risk of uneven display brightness of the display panel 100.

[0212] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0213] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel comprising a functional device placement area and a main display area at least partially surrounding the functional device placement area; the display panel further comprising a fan-out area, the fan-out area being disposed on one side of the main display area along a second direction; the main display area further comprising a central area and an edge area, the edge area being disposed on at least one side of the central area along a first direction; The display panel includes: substrate; a plurality of data lines disposed on the substrate; the plurality of data lines are arranged at intervals along the first direction; the plurality of data lines include at least one first data line and a plurality of fourth data lines; the first data line is disposed in the main display area, the plurality of first data lines include a first data line segment, a first connecting line, and a second data line segment connected in sequence; the first data line segment and the second data line segment both extend along the second direction and are disposed on both sides of the functional device arrangement area along the second direction; the extension direction of the first data line segment coincides with the extension direction of the second data line segment and passes through the functional device arrangement area; the plurality of fourth data lines are disposed in the edge area and extend along the second direction; wherein the first direction intersects the second direction; A plurality of fourth transfer lines are provided on the substrate and in the central area; the fourth transfer lines extend along the second direction and are connected to the fan-out area; a plurality of fifth transfer lines disposed on the substrate and in the edge region, the plurality of fifth transfer lines extending along the first direction to the central region and spaced apart along the second direction; at least a portion of the plurality of fifth transfer lines crossing over at least one data line and being insulated from the crossed data line; A plurality of first transfer blocks are provided on the substrate; the fourth data line and the portion of the fifth transfer line provided in the edge region are connected via one of the first transfer blocks; A plurality of second transfer blocks are provided on the substrate; parts of the fourth transfer line and the fifth transfer line provided in the central area are connected via one of the second transfer blocks; A plurality of first electrodes are arranged on one side of the substrate where the plurality of first adapter blocks and the plurality of second adapter blocks are arranged, and in an orthographic projection onto the substrate, the first electrodes are staggered with the first adapter blocks and / or the second adapter blocks; a plurality of first scanning signal lines extending along the first direction and spaced apart along the second direction; A plurality of first initialization signal lines extend along the first direction and are spaced apart along the second direction; one of the first initialization signal lines is located between one of the first scanning signal lines and one of the fifth transfer lines.

2. The display panel according to claim 1, further comprising: A first conductive layer is provided on the substrate; the fourth data line and the fourth transfer line are provided on the first conductive layer; A second conductive layer is provided between the substrate and the first conductive layer; the fifth adapter wire, the first adapter block and the second adapter block are provided in the second conductive layer; The first electrode layer is disposed on a side of the first conductive layer away from the substrate and includes the plurality of first electrodes.

3. The display panel according to claim 2, wherein: The plurality of data lines are divided into a plurality of groups, each group of data lines includes two data lines, and the minimum interval between two data lines in a group of data lines is greater than the minimum interval between two adjacent groups of data lines; The data lines include alternately connected first straight segments and first bent segments; the first straight segments extend along the second direction, and the first bent segments bend in a direction away from another data line in the same group of data lines; each of the fourth adapter lines is disposed between two data lines in a group of data lines; The plurality of first electrodes include a plurality of first sub-electrodes and a plurality of second sub-electrodes. In an orthographic projection onto the substrate, one first sub-electrode overlaps with two adjacent first bent segments in two adjacent groups, and one second sub-electrode is disposed between two first straight segments in one group. In the orthographic projection onto the substrate, the first adapter block and the second adapter block are arranged on both sides of the fourth adapter line, the first adapter block at least partially overlaps with the first straight line segment, the second adapter block at least partially overlaps with the fourth adapter line, and is arranged between the first bending segments on both sides of the fourth adapter line.

4. The display panel according to claim 3, wherein: The first conductive layer further includes a plurality of first power supply voltage signal lines, the plurality of first power supply voltage signal lines are divided into a plurality of groups, each group of first power supply voltage signal lines includes two first power supply voltage signal lines; the group of first power supply voltage signal lines is arranged between the two data lines included in a group of data lines, and each of the fourth adapter lines is arranged between the two first power supply voltage signal lines included in a group of first power supply voltage signal lines; In an orthographic projection onto the substrate, the first sub-electrode is disposed between two mutually distant boundaries of two mutually close first power supply voltage signal lines in two adjacent groups of first power supply voltage signal lines.

5. The display panel according to claim 3, wherein: In the orthographic projection onto the substrate, the midline of the fifth connecting line along the first direction coincides with a straight line formed by connecting the intersection of the first straight segment and the first bending segment, and the first electrode is disposed between two adjacent fifth transfer lines. The display panel according to claim 3 , wherein: In an orthographic projection onto the substrate, a portion where the first sub-electrode overlaps the data line is symmetrical about the fifth axis and / or the sixth axis; The fifth axis extends along the first direction and passes through the center of the first sub-electrode, and the sixth axis extends along the second direction and passes through the center of the first sub-electrode; the midline of the overlapping portion of the second sub-electrode and the fourth adapter line passes through the center of the second sub-electrode.

7. The display panel according to claim 2, wherein: The plurality of data lines and the plurality of fourth adapter lines are alternately distributed; The plurality of first electrodes include a plurality of third sub-electrodes, a plurality of fourth sub-electrodes, and a plurality of fifth sub-electrodes; in an orthographic projection onto the substrate, the third sub-electrode overlaps with an adjacent data line and a fourth transfer line, and the overlapping portions are symmetrical about a ninth axis and / or a tenth axis; the ninth axis extends along the first direction and passes through a center of the third sub-electrode, and the tenth axis extends along the second direction and passes through a center of the third sub-electrode; In an orthographic projection onto the substrate, the fourth sub-electrode overlaps with two data lines and two fourth transfer lines, and the overlapping portions are symmetrical about an eleventh axis and / or a twelfth axis; the eleventh axis extends along the first direction and passes through a center of the fourth sub-electrode, and the twelfth axis extends along the second direction and passes through a center of the fourth sub-electrode; In an orthographic projection onto the substrate, the fifth sub-electrode overlaps with the adjacent data line and the fourth switching line, and the overlapping portions are symmetrical about the center of the fifth sub-electrode.

8. The display panel according to claim 2, further comprising: a third conductive layer, disposed between the second conductive layer and the substrate; The plurality of first scanning signal lines are arranged in the third conductive layer; a fourth conductive layer, disposed between the third conductive layer and the second conductive layer; the plurality of first initialization signal lines are disposed in the fourth conductive layer; In an orthographic projection onto the substrate, the first initialization signal line and the first scanning signal line overlap, and the fifth transfer line is disposed within the range of the first initialization signal line.

9. The display panel according to claim 2, further comprising: a fifth conductive layer, disposed between the second conductive layer and the substrate; The plurality of first scanning signal lines are arranged on the fifth conductive layer; a sixth conductive layer, disposed between the fifth conductive layer and the second conductive layer; the plurality of first initialization signal lines are disposed in the sixth conductive layer; In an orthographic projection onto the substrate, the first initialization signal line is disposed between the first scanning signal line and the fifth switching line.

10. The display panel according to claim 9, wherein: In an orthographic projection onto the substrate, the second adapter block is disposed on a side of the fifth adapter line connected to the second adapter block that is away from the first scanning signal line.

11. The display panel according to claim 2, wherein: The fourth patch cord has a first opening, the first opening dividing the first patch cord into a first routing segment and a second routing segment, the first routing segment being arranged on a side of the second routing segment close to the fan-out area, one end of the first routing segment being connected to the fan-out area, and the other end being connected to the fifth patch cord; In an orthographic projection onto the substrate, the first opening and the first electrode are staggered.

12. The display panel according to claim 11, wherein: The second conductive layer further includes a plurality of power supply voltage blocks; the power supply voltage blocks are configured to transmit power supply voltage signals; and in an orthographic projection onto the substrate, the first opening is disposed within the range of the power supply voltage blocks.

13. The display panel according to claim 11, further comprising: a seventh conductive layer, disposed between the second conductive layer and the substrate; the seventh conductive layer comprising a plurality of spacers; In an orthographic projection onto the substrate, the first opening is disposed within the range of the spacer.

14. The display panel according to claim 2, wherein: The fifth patch cord has a second opening and a third opening; the second opening and the third opening divide the fifth patch cord into a third routing segment, a fourth routing segment, and a fifth routing segment; one end of the fourth routing segment is connected to the first adapter block, and the other end is connected to the second adapter block, and the third routing segment and the fifth routing segment are arranged on both sides of the fourth routing segment; In an orthographic projection onto the substrate, the first electrode and the second opening and / or the third opening are staggered.

15. The display panel according to claim 14, wherein: In an orthographic projection onto the substrate, the second opening and / or the third opening is / are arranged within the range of the data line.

16. The display panel according to claim 14, wherein: The first conductive layer further comprises a plurality of first power supply voltage signal lines, wherein the plurality of first power supply voltage signal lines are spaced apart along the first direction and extend along the second direction; In an orthographic projection onto the substrate, the second opening and / or the third opening is arranged within the range of the first power supply voltage signal line.

17. The display panel according to claim 2, further comprising: an eighth conductive layer, disposed between the substrate and the second conductive layer, and comprising a plurality of third initialization signal lines; the third initialization signal lines at least including a portion extending along the second direction; In an orthographic projection onto the substrate, the fourth connecting line overlaps with a portion of the third initialization signal line extending along the second direction.

18. The display panel according to any one of claims 1 to 17, wherein: The plurality of data lines include at least one second data line, the second data line including a third data line segment, a second connecting line, and a fourth data line segment connected in sequence; the third data line segment and the fourth data line segment are both arranged in the main display area; the third data line segment and the fourth data line segment both extend along the second direction and are arranged on both sides of the functional device arrangement area along the second direction; the extension direction of the third data line segment and the extension direction of the fourth data line segment coincide with each other; Wherein, the second connection line is parallel to the boundary of the functional device setting area.

19. A display device comprising the display panel according to any one of claims 1 to 18.

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