Interleaving method and communication apparatus

Abstract

An interleaving method and a communication apparatus. The method comprises: a transmitting-end device performing sub-block interleaving on a codeword sequence to be interleaved, so as to obtain a first codeword sequence (S410), wherein the codeword sequence to be interleaved and the first codeword sequence each comprise Y sub-blocks, the Y sub-blocks of the codeword sequence to be interleaved are determined on the basis of the number X of bits included in a preset sub-block, and X and Y are both integers greater than 1; and then, the transmitting-end device performing, in a corresponding sub-block group, cross-sub-block bit interleaving on bits included in at least one of L sub-block groups, so as to obtain a second codeword sequence (S420), wherein the L sub-block groups are determined on the basis of the Y sub-blocks of the first codeword sequence and the number Z of sub-blocks included in a preset sub-block group, and Z and L are both integers greater than 1. The method can reduce the hardware overheads required for interleaving, thereby increasing the throughput rate.

Description

Interleaving method and communication device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on December 22, 2023, with application number 202311788453.0 and application name “Interleaving Method and Communication Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of channel coding, and more particularly, to an interleaving method and a communication device. Background Art

[0003] To achieve randomness, current channel bit interleaving schemes typically perform extensive interleaving across the entire transmitted codeword. However, this interleaving method consumes significant hardware resources due to its large interleaving range and lack of regularity. Furthermore, this interleaving method reduces throughput, making it unsuitable for channel bit interleaving in next-generation communication systems. Summary of the Invention

[0004] The present application provides an interleaving method and a communication device, which can reduce the hardware overhead required for interleaving and improve the throughput.

[0005] On the first aspect, an interleaving method is provided, which can be executed by a transmitting device. Unless otherwise specified, the "transmitting device" in this application can refer to the transmitting device itself (for example, a network device, a terminal device), or a component in the transmitting device (for example, a processor, a chip, or a chip system, etc.), or it can also be a logical module or software that can implement all or part of the functions of the transmitting device.

[0006] The method includes: performing sub-block interleaving on a codeword sequence to be interleaved to obtain a first codeword sequence, wherein the codeword sequence to be interleaved and the first codeword sequence both include Y sub-blocks, the Y sub-blocks of the codeword sequence to be interleaved are determined based on a preset number X of bits included in a sub-block, and both X and Y are integers greater than 1; performing cross-sub-block bit interleaving on bits included in at least one sub-block group among L sub-block groups within the corresponding sub-block group to obtain a second codeword sequence, wherein the L sub-block groups are determined based on the Y sub-blocks of the first codeword sequence and a preset number Z of sub-blocks included in a sub-block group, and both Z and L are integers greater than 1.

[0007] In the above technical solution, the interleaving process of the codeword sequence to be interleaved is divided into two steps. The first step is sub-block interleaving, which disperses the originally clustered bit positions to different positions in the transmitted sequence over a large range through sub-block interleaving. The second step is to perform small-scale cross-sub-block bit interleaving within a sub-block group composed of multiple sub-blocks to break the correlation between consecutive bits. In this way, large-scale sub-block interleaving can improve parallelism (i.e., increase throughput), while small-scale cross-sub-block bit interleaving within a sub-block group can be achieved through a fixed interconnection relationship, making hardware implementation easy (i.e., requiring low hardware overhead). This solves the problem of irregular deinterleaving caused by the original interleaving of small-granularity bits over a large range, which cannot improve parallelism and has high hardware overhead.

[0008] In certain implementations of the first aspect, performing cross-subblock bit interleaving on bits included in at least one sub-block group among the L sub-block groups within the corresponding sub-block group includes: performing cross-subblock bit interleaving on bits included in a first sub-block group among the at least one sub-block group within the first sub-block group based on a first interleaving mode, wherein the first sub-block group includes a first sub-block and a second sub-block, and the first interleaving mode is used to place a first bit included in the first sub-block at a first position, wherein the first position is a position where a second bit included in the second sub-block is located.

[0009] In the above technical solution, a first bit contained in a first sub-block in a first sub-block group is swapped from a current position to a position one bit in a second sub-block, thereby implementing bit interleaving across sub-blocks within the sub-block group. In certain implementations of the first aspect, a remainder after a modulo-n operation on the position number of the first bit is the same as a remainder after a modulo-n operation on the position number of the second bit, where n is an integer greater than 1.

[0010] For example, n is a prime number greater than 1.

[0011] The above technical solution can be viewed as a first interleaving method in which bits in a sub-block group are interleaved using modulo n congruence positions. The position number of a bit (e.g., the first bit or the second bit) in the first sub-block group is S, indicating that the bit is the Sth bit among all bits in the first sub-block group.

[0012] Optionally, the offset value corresponding to each bit in the first sub-block may be the same or different, and this application does not impose any limitation on this. For example, if the remainders after a modulo-n operation on the position numbers of multiple bits in the first sub-block group are the same as the remainder after a modulo-n operation on the position number of the first bit, then the first bit may be offset to the position of any bit among the multiple bits.

[0013] In certain implementations of the first aspect, performing sub-block interleaving on the to-be-interleaved codeword sequence includes: performing sub-block interleaving on the to-be-interleaved codeword sequence based on a second interleaving method, wherein the second interleaving method is used to interleave each of the Y sub-blocks of the to-be-interleaved codeword sequence. The sub-blocks are written in columns and read out in rows to complete the sub-block interleaving. d1 is the number of written columns corresponding to the second interleaving mode. d1 is an integer greater than 1 and less than Y. Indicates rounding up.

[0014] For example, d1 is a prime number greater than 1 and less than Y, so that interleaving can mix the coupling between decoding more thoroughly.

[0015] For example, Z is equal to d1.

[0016] In the above technical solution, block interleaving is achieved by adopting a column-by-column interleaving method, which is simple to use and highly operable.

[0017] In certain implementations of the first aspect, sub-block interleaving is performed on the interleaved codeword sequence, including: sub-block interleaving is performed on the interleaved codeword sequence based on a third interleaving method, wherein the third interleaving method is used to write every d2 sub-blocks of the Y sub-blocks of the codeword sequence to be interleaved by row and read them out by column to complete the sub-block interleaving, d2 is the number of written columns corresponding to the third interleaving method, and d2 is an integer greater than 1 and less than Y.

[0018] For example, d2 is a prime number greater than 1 and less than Y, so that interleaving can mix the coupling between decoding more thoroughly.

[0019] In the above technical solution, block interleaving is achieved by adopting a row-by-row interleaving method, which is simple to use and has strong operability.

[0020] In certain implementations of the first aspect, the subblocks included in any subblock group among the L subblock groups are consecutive subblocks among the Y subblocks of the first codeword sequence.

[0021] In certain implementations of the first aspect, the third interleaving method is further used to perform sub-block interleaving of at least one of the d2 sub-block groups within the corresponding sub-block group between row-wise writing and column-wise reading, wherein the d2 sub-block groups are the sub-block groups corresponding to the d2 columns of sub-blocks after row-wise writing.

[0022] In certain implementations of the first aspect, the L sub-block groups are sub-block groups obtained by reading rows after performing sub-block interleaving within corresponding sub-block groups.

[0023] For example, Z is equal to d2.

[0024] In certain implementations of the first aspect, the third interleaving method is used to perform sub-block interleaving on at least one of the d2 sub-block groups within the corresponding sub-block group, including: the third interleaving method is used to shift the sub-blocks in the column direction within the corresponding sub-block group for at least one of the d2 sub-block groups to achieve sub-block interleaving.

[0025] In the above technical solution, no interleaving is added, so that the interleaving result is more uniform.

[0026] On the second aspect, a deinterleaving method is provided, which can be executed by a receiving device. Unless otherwise specified, the "receiving device" in this application can refer to the receiving device itself (for example, a network device, a terminal device), or a component in the receiving device (for example, a processor, a chip, or a chip system, etc.), or it can also be a logical module or software that can realize all or part of the functions of the receiving device.

[0027] The method includes: performing cross-subblock de-bit interleaving on decoding information contained in at least one sub-block group among L sub-block groups within the corresponding sub-block group to obtain a first de-interleaved sequence, wherein the L sub-block groups are determined based on Y sub-blocks of a sequence to be de-interleaved and a preset number Z of sub-blocks contained in a sub-block group, the Y sub-blocks are determined based on a preset number X of decoding information contained in a sub-block, and X, Y, Z, and L are all integers greater than 1; and performing sub-block de-interleaving on the first de-interleaved sequence to obtain a second de-interleaved sequence.

[0028] In certain implementations of the second aspect, performing cross-subblock bit deinterleaving on the decoding information contained in at least one subblock group among the L subblock groups within the corresponding subblock group includes: performing cross-subblock bit interleaving on the decoding information contained in a first subblock group among the at least one subblock group within the first subblock group based on a first deinterleaving mode, wherein the first subblock group includes a first subblock and a second subblock, and the first deinterleaving mode is used to place the first decoding information contained in the second subblock at a second position, wherein the second position is a position where the second decoding information is located in the first subblock.

[0029] In certain implementations of the second aspect, a remainder after a modulo-n operation of the position number of the first decoded information is the same as a remainder after a modulo-n operation of the position number of the second decoded information, where n is an integer greater than 1.

[0030] In certain implementations of the second aspect, performing desub-block interleaving on the first deinterleaved sequence includes:

[0031] Desubblock interleaving is performed on the first deinterleaved sequence based on a second deinterleaving method, wherein the second deinterleaving method is used to write Y subblocks of the first deinterleaved sequence by row and read them by column to complete desubblock interleaving, d1 is the number of written columns corresponding to the second deinterleaving method, and the number of subblocks written in each row is determined based on the interleaving method performed on the columns modulo d1, and d1 is an integer greater than 1 and less than Y.

[0032] In certain implementations of the second aspect, Z is equal to d1.

[0033] In certain implementations of the second aspect, de-subblock interleaving is performed on the first de-interleaved sequence, including: de-subblock interleaving is performed on the first de-interleaved sequence based on a third de-interleaving method, wherein the third de-interleaving method is used to write Y sub-blocks of the first de-interleaved sequence by column and read them out by row to complete de-subblock interleaving, d2 is the number of written columns corresponding to the third de-interleaving method, and the number of sub-blocks written in each column is determined based on the interleaving method of the row column modulo d2, and d2 is an integer greater than 1 and less than Y.

[0034] In certain implementations of the second aspect, the subblocks included in any subblock group among the L subblock groups are consecutive subblocks among the Y subblocks of the sequence to be deinterleaved.

[0035] In certain implementations of the second aspect, the third deinterleaving method is further used to desubblock interleave at least one of the d2 subblock groups within the corresponding subblock group between column-wise writing and row-wise reading, wherein the d2 subblock groups are the subblock groups corresponding to the d2 columns of subblocks after column-wise writing.

[0036] In certain implementations of the second aspect, the L sub-block groups are sub-block groups obtained by reading rows before performing de-sub-block interleaving in the corresponding sub-block groups.

[0037] For example, Z is equal to d2.

[0038] In certain implementations of the second aspect, the third deinterleaving method is used to perform desubblock interleaving on at least one of the d2 subblock groups within the corresponding subblock group, including: the third deinterleaving method is used to perform desubblock interleaving on at least one of the d2 subblock groups by shifting the subblocks in the column direction within the corresponding subblock group.

[0039] On the third aspect, an interleaving method is provided, which can be executed by a transmitting device. Unless otherwise specified, the "transmitting device" in this application can refer to the transmitting device itself (for example, a network device, a terminal device), or a component in the transmitting device (for example, a processor, a chip, or a chip system, etc.), or it can also be a logical module or software that can realize all or part of the functions of the transmitting device.

[0040] The method includes: performing cross-subblock bit interleaving on bits included in at least one subblock group among L subblock groups within the corresponding subblock group to obtain a third codeword sequence, wherein the L subblock groups are determined based on Y subblocks of the codeword sequence to be interleaved and a preset number Z of subblocks included in a subblock group, the Y subblocks are determined based on a preset number X of bits included in a subblock, and X, Y, Z, and L are all integers greater than 1; and performing subblock interleaving on the Y subblocks of the third codeword sequence to obtain a fourth codeword sequence.

[0041] In the above technical solution, the interleaving process of the codeword sequence to be interleaved is divided into two steps. The first step is to perform small-scale cross-subblock bit interleaving within the sub-block group to break the correlation between consecutive bits. The second step is sub-block interleaving, so that the originally clustered bit positions are dispersed to different positions of the transmitted sequence over a large range through block interleaving. In this way, the parallelism can be improved through large-scale sub-block interleaving, and the small-scale cross-subblock bit interleaving within the sub-block group can itself be obtained through a fixed interconnection relationship, and the hardware implementation is easy, thereby solving the problems of irregular deinterleaving caused by performing small-granularity bit interleaving over a large range, which cannot improve parallelism and has high hardware overhead.

[0042] In certain implementations of the third aspect, the bits included in at least one sub-block group among the L sub-block groups are interleaved across sub-blocks within the corresponding sub-block group, including: based on a first interleaving mode, the bits included in a first sub-block group among the at least one sub-block group are interleaved across sub-blocks within the first sub-block group, wherein the first sub-block group includes a first sub-block and a second sub-block, and the first interleaving mode is used to place a first bit included in the first sub-block at a first position, wherein the first position is a position where a second bit included in the second sub-block is located.

[0043] Regarding the beneficial effects of each implementation method of the third aspect, please refer to the description of the first aspect and will not be repeated here.

[0044] In certain implementations of the third aspect, a remainder after a modulo n operation on the position number of the first bit is the same as a remainder after a modulo n operation on the position number of the second bit, where n is an integer greater than 1.

[0045] In certain implementations of the third aspect, sub-block interleaving is performed on the Y sub-blocks of the third codeword sequence, including: performing sub-block interleaving on the Y sub-blocks of the third codeword sequence based on a third interleaving method, wherein the third interleaving method is used to write every d2 sub-blocks of the Y sub-blocks of the third codeword sequence by row and read them by column to complete the sub-block interleaving, d2 is the number of write columns corresponding to the third interleaving method, and d2 is an integer greater than 1 and less than Y.

[0046] For example, Z is equal to d2.

[0047] In certain implementations of the third aspect, performing sub-block interleaving on the Y sub-blocks of the third codeword sequence includes: performing sub-block interleaving on the Y sub-blocks of the third codeword sequence based on a second interleaving mode, wherein the second interleaving mode is used to interleave each of the Y sub-blocks of the third codeword sequence. The sub-blocks are written in columns and read out in rows to complete the sub-block interleaving, where d1 is the number of written columns corresponding to the second interleaving mode, and d1 is an integer greater than 1 and less than Y. Indicates rounding up.

[0048] In certain implementations of the third aspect, the subblocks included in any subblock group among the L subblock groups are consecutive subblocks among the Y subblocks of the to-be-interleaved codeword sequence.

[0049] Fourthly, a deinterleaving method is provided, which can be executed by a receiving device. Unless otherwise specified, the "receiving device" in this application can refer to the receiving device itself (for example, a network device, a terminal device), or a component in the receiving device (for example, a processor, a chip, or a chip system, etc.), or it can also be a logical module or software that can realize all or part of the functions of the receiving device.

[0050] The method includes: performing sub-block deinterleaving on a sequence to be deinterleaved to obtain a third deinterleaved sequence, wherein both the sequence to be deinterleaved and the third deinterleaved sequence include Y sub-blocks, the Y sub-blocks of the sequence to be deinterleaved are determined based on the number X of decoding information contained in a preset sub-block, and both X and Y are integers greater than 1; performing cross-sub-block debit interleaving on the decoding information contained in at least one sub-block group among L sub-block groups within the corresponding sub-block group to obtain a fourth deinterleaved sequence, wherein the L sub-block groups are determined based on the Y sub-blocks of the third deinterleaved sequence and the number Z of sub-blocks contained in a preset sub-block group, the Y sub-blocks are determined based on the number X of decoding information contained in the preset sub-block, and both Z and L are integers greater than 1.

[0051] In certain implementations of the fourth aspect, performing cross-subblock debit interleaving on the decoding information contained in at least one subblock group among the L subblock groups within the corresponding subblock group includes: performing cross-subblock debit interleaving on the decoding information contained in a first subblock group among the at least one subblock group within the first subblock group based on a first deinterleaving method, wherein the first subblock group includes a first subblock and a second subblock, and the first deinterleaving method is used to place the first decoding information contained in the second subblock at a second position, wherein the second position is a position where the second decoding information is located in the first subblock.

[0052] In certain implementations of the fourth aspect, a remainder after a modulo-n operation of the position number of the first decoded information is the same as a remainder after a modulo-n operation of the position number of the second decoded information, where n is an integer greater than 1.

[0053] In certain implementations of the fourth aspect, de-sub-block interleaving is performed on the sequence to be deinterleaved, including: de-sub-block interleaving is performed on the sequence to be deinterleaved based on a third deinterleaving method, wherein the third deinterleaving method is used to write Y sub-blocks of the sequence to be deinterleaved by column and read them out by row to complete de-sub-block interleaving, d2 is the number of written columns corresponding to the third deinterleaving method, and the number of sub-blocks written in each column is determined based on the interleaving method of the row column modulo d2.

[0054] In certain implementations of the fourth aspect, Z is equal to d2.

[0055] In certain implementations of the fourth aspect, de-block interleaving is performed on the sequence to be deinterleaved, including: de-block interleaving is performed on the sequence to be deinterleaved based on a second deinterleaving method, wherein the second deinterleaving method is used to write Y sub-blocks of the sequence to be deinterleaved by rows and read them out by columns to complete de-block interleaving, wherein d1 is the number of written columns corresponding to the second deinterleaving method, and the number of sub-blocks written in each row is determined based on the interleaving method performed on the columns modulo d1, and d1 is an integer greater than 1 and less than Y.

[0056] In certain implementations of the fourth aspect, the subblocks included in any subblock group among the L subblock groups are consecutive subblocks among the Y subblocks of the third deinterleaved sequence.

[0057] In the fifth aspect, an interleaving method is provided, which can be executed by a transmitting device. Unless otherwise specified, the "transmitting device" in this application can refer to the transmitting device itself (for example, a network device, a terminal device), or a component in the transmitting device (for example, a processor, a chip, or a chip system, etc.), or it can also be a logical module or software that can realize all or part of the functions of the transmitting device.

[0058] The method includes: writing each d sub-blocks of Y sub-blocks in rows, wherein the Y sub-blocks are obtained by dividing a codeword sequence to be interleaved based on a preset number X of bits contained in a sub-block, where X and Y are both integers greater than 1, and d is an integer greater than 1 and less than Y; performing sub-block interleaving on at least one sub-block group of the d sub-block groups within a corresponding sub-block group, wherein the d sub-block groups are sub-block groups corresponding to d columns of sub-blocks after writing in rows; performing cross-sub-block bit interleaving on bits contained in at least one sub-block group of L sub-block groups within the corresponding sub-block group, wherein the L sub-block groups are sub-block groups corresponding to when Y sub-blocks are read in rows after sub-block interleaving is performed in the corresponding sub-block group based on a preset number Z of sub-blocks contained in a sub-block group, where Z and L are both integers greater than 1; and obtaining a second codeword sequence, wherein the second codeword sequence is a sequence obtained by reading sub-blocks in columns.

[0059] It can be understood that in this technical solution, cross-subblock bit interleaving can be considered as being implemented during the block interleaving process. That is, based on the third interleaving method, between row-by-row writing and column-by-column reading, each column of subblocks is first interleaved as a block, and then the resulting Y subblocks are divided into L subblock groups by row-by-row reading. It should be noted that the row-by-row reading method here does not represent actual reading, but only describes a method of dividing the L subblock groups. After completing the cross-subblock bit interleaving of the L subblock groups, the Y subblocks are read out by column. This method can reduce the hardware overhead required for interleaving and improve throughput.

[0060] In certain implementations of the fifth aspect, Z is equal to d.

[0061] In certain implementations of the fifth aspect, the bits included in at least one sub-block group among the L sub-block groups are interleaved across sub-blocks within the corresponding sub-block group, including: based on a first interleaving mode, the bits included in a first sub-block group among the at least one sub-block group are interleaved across sub-blocks within the first sub-block group, wherein the first sub-block group includes a first sub-block and a second sub-block, and the first interleaving mode is used to place a first bit included in the first sub-block at a first position, wherein the first position is a position where a second bit included in the second sub-block is located.

[0062] In certain implementations of the fifth aspect, a remainder after a modulo n operation on the position number of the first bit is the same as a remainder after a modulo n operation on the position number of the second bit, where n is an integer greater than 1.

[0063] In certain implementations of the fifth aspect, performing sub-block interleaving on at least one of the d sub-block groups within the corresponding sub-block group includes: performing sub-block interleaving on at least one of the d sub-block groups by shifting sub-blocks in a column direction within the corresponding sub-block group.

[0064] In a sixth aspect, a communication device is provided, configured to execute the method provided in the first, third, or fifth aspects. Specifically, the device may include units and / or modules, such as a processing unit and / or a communication unit, configured to execute the method in any of the first, third, or fifth aspects, or any possible implementation of the first, third, or fifth aspects.

[0065] In one implementation, the apparatus is a transmitting device. When the apparatus is a transmitting device, the communication unit may be a transceiver or an input / output interface; and the processing unit may be at least one processor. Optionally, the transceiver may be a transceiver circuit. Optionally, the input / output interface may be an input / output circuit.

[0066] In another implementation, the apparatus is a chip, chip system, or circuit used in a transmitting device. When the apparatus is a chip, chip system, or circuit used in a transmitting device, the communication unit may be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; and the processing unit may be at least one processor, processing circuit, or logic circuit.

[0067] In a seventh aspect, a communication device is provided, the device being configured to execute the method provided in the second or fourth aspect. Specifically, the device may include units and / or modules, such as a processing unit and / or a communication unit, for executing the method in any of the second or fourth aspects or any possible implementation of the second or fourth aspects.

[0068] In one implementation, the apparatus is a receiving device. When the apparatus is a receiving device, the communication unit may be a transceiver or an input / output interface; and the processing unit may be at least one processor. Alternatively, the transceiver may be a transceiver circuit. Alternatively, the input / output interface may be an input / output circuit.

[0069] In another implementation, the apparatus is a chip, chip system, or circuit used in a receiving device. When the apparatus is a chip, chip system, or circuit used in a transmitting device, the communication unit may be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; and the processing unit may be at least one processor, processing circuit, or logic circuit.

[0070] In an eighth aspect, a communication device is provided, comprising: at least one processor, the at least one processor being coupled to at least one memory, the at least one memory being used to store computer programs or instructions, and the at least one processor being used to call and run the computer program or instructions from the at least one memory, so that the method in any one of the first aspect, the third aspect, or the fifth aspect, or any possible implementation of the first aspect, the third aspect, or the fifth aspect is executed.

[0071] In one implementation, the apparatus is a sending end device.

[0072] In another implementation, the apparatus is a chip, a chip system, or a circuit used in a transmitting device.

[0073] In a ninth aspect, a communication device is provided, comprising: at least one processor, the at least one processor being coupled to at least one memory, the at least one memory being used to store computer programs or instructions, and the at least one processor being used to call and run the computer program or instructions from the at least one memory, so that the method in any one of the second aspect or the fourth aspect and any possible implementation of the second aspect or the fourth aspect is executed.

[0074] In one implementation, the apparatus is a receiving device.

[0075] In another implementation, the apparatus is a chip, a chip system, or a circuit used in a receiving device.

[0076] In a tenth aspect, a processor is provided for executing the methods provided in the above aspects.

[0077] For the operations such as sending and acquiring / receiving involved in the processor, unless otherwise specified, or if they do not conflict with their actual functions or internal logic in the relevant descriptions, they can be understood as processor output, reception, input and other operations, and can also be understood as sending and receiving operations performed by the radio frequency circuit and antenna. This application does not limit this.

[0078] In the eleventh aspect, a computer-readable storage medium is provided, which stores a computer program or instruction, and when running on a computer, enables the method in any one of the above-mentioned aspects 1 to 4 or any possible implementation of the aspects 1 to 4 to be executed.

[0079] In the twelfth aspect, a computer program product comprising instructions is provided. When the computer program product is run on a computer, when the computer instructions are run on the computer, the method in any one of the above-mentioned aspects 1 to 4 and any possible implementation of the first to fourth aspects is executed.

[0080] In the thirteenth aspect, a chip is provided, which includes a processor and a communication interface. The processor reads a computer program or instruction stored in a memory through the communication interface. When the computer program or instruction is executed, the method in any one of the above-mentioned aspects 1 to 4 or any possible implementation of aspects 1 to 4 is executed.

[0081] Optionally, as an implementation manner, the chip further includes a memory.

[0082] In the fourteenth aspect, a communication system is provided, which includes the communication device shown in the eighth and ninth aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] FIG1 is a schematic diagram of the system architecture of a communication system applicable to the technical solution of the present application.

[0084] FIG2 is a flow chart of a communication system applicable to the present application.

[0085] FIG3 is a schematic diagram of row-column interleaving in existing communication standards.

[0086] FIG4 is a schematic flowchart of an interleaving method 400 provided in this application.

[0087] FIG5 is a schematic diagram showing an interleaving method of columns modulo d1.

[0088] FIG6 is a schematic diagram of an interleaving method of a marching list modulo d2.

[0089] FIG7 is a schematic diagram of implementing cross-sub-block bit interleaving based on a possible first interleaving mode.

[0090] FIG8 is a schematic diagram of implementing cross-sub-block bit interleaving based on another possible first interleaving mode.

[0091] FIG. 9 is a schematic diagram of a specific example of implementing interleaving based on method 400 .

[0092] FIG. 10 is a schematic diagram of another specific example of implementing interleaving based on method 400 .

[0093] FIG11 is a schematic flowchart of a deinterleaving method 1100 provided in the present application.

[0094] FIG12 is a schematic flowchart of an interleaving method 1200 provided in this application.

[0095] FIG. 13 is a schematic diagram of a specific example of implementing interleaving based on method 1200 .

[0096] FIG14 is a schematic flowchart of a deinterleaving method 1400 provided in the present application.

[0097] FIG15 is a schematic block diagram of a communication device 1500 provided in this application.

[0098] FIG16 is a schematic structural diagram of a communication device 1600 provided in this application. DETAILED DESCRIPTION

[0099] The technical solution in this application will be described below with reference to the accompanying drawings.

[0100] The technical solutions of the embodiments of the present application can be applied to various communication systems, including but not limited to: satellite communication systems, fifth generation (5G) systems or new radio (NR) systems, long term evolution (LTE) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, etc. The technical solutions provided in the present application can also be applied to future communication systems, such as the sixth generation mobile communication system. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), and Internet of Things (IoT) communication systems or other communication systems, etc., which are not limited in this article.

[0101] The communication system applicable to the present application may include one or more transmitting ends and one or more receiving ends. Optionally, one of the transmitting end and the receiving end may be a terminal device, and the other may be a network device. Alternatively, both the transmitting end and the receiving end may be terminal devices. The transmitting end may also be considered an encoding end or encoding device, and the receiving end may also be considered a decoding end or decoding device.

[0102] For example, a terminal device may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent, or user apparatus. The terminal device in the embodiments of the present application may refer to a device that provides voice and / or data connectivity to a user and can be used to connect people, objects, and machines, such as a handheld device with wireless connection function, a vehicle-mounted device, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, etc. Optionally, the UE can be used to act as a base station. For example, the UE can act as a scheduling entity that provides sidelink signals between UEs in V2X or D2D, etc.

[0103] In an embodiment of the present application, the device for realizing the function of the terminal may be a terminal, or a device capable of supporting the terminal to realize the function, such as a chip system or a chip, which may be installed in the terminal. In an embodiment of the present application, the chip system may be composed of a chip, or may include a chip and other discrete devices. The method provided in this application may be executed by a terminal device. Unless otherwise specified, the "terminal device" in this application may refer to the terminal device itself, or a component in the terminal device (for example, a processor, a chip, or a chip system, etc.), or a logic module or software that can realize all or part of the functions of the terminal device.

[0104] Exemplarily, the network device may be a device with wireless transceiver functions, and the network device may be a device that provides wireless communication function services, usually located on the network side, including but not limited to the next generation base station (gNodeB, gNB) in the fifth generation (5G) communication system, the base station in the sixth generation (6G) mobile communication system, the base station in the future mobile communication system or the access node in the wireless fidelity (Wi-Fi) system, the evolved node B (eNB) in the long term evolution (LTE) system, the radio network controller (RNC), the node B (NB), the base station controller (BSC), the home base station (for example, home evolved NodeB, or home Node B, HNB), the base band unit (BBU), the transmission reception point (TRP), the transmitting point (TP), the base transceiver station (BTS), etc. In a network structure, the network device may include a centralized unit (CU) node, or a distributed unit (DU) node, or a RAN device including a CU node and a DU node, or a RAN device including a control plane CU node and a user plane CU node, and a DU node, or the network device may also be a wireless controller, relay station, vehicle-mounted device, and wearable device in a cloud radio access network (CRAN) scenario. In addition, the base station may be a macro base station, a micro base station, a relay node, a donor node, or a combination thereof. The base station may also refer to a communication module, a modem, or a chip for being set in the aforementioned device or apparatus. The base station may also be a mobile switching center and a device that performs the base station function in D2D, V2X, and M2M communications, a network-side device in a 6G network, a device that performs the base station function in future communication systems, and the like. The base station can support networks with the same or different access technologies without limitation.

[0105] In an embodiment of the present application, the device for realizing the function of the network device may be a network device, or it may be a device capable of supporting the network device to realize the function, such as a chip system or a chip, and the device may be installed in the network device. In an embodiment of the present application, the chip system may be composed of chips, or may include chips and other discrete devices. The method provided in this application may be executed by a network device. Unless otherwise specified, the "network device" in this application may refer to the network device itself, or a component in the network device (for example, a processor, a chip, or a chip system, etc.), or it may be a logic module or software that can realize all or part of the functions of the network device.

[0106] Figure 1 is a schematic diagram of the system architecture of a communication system applicable to the technical solution of the present application. The communication system may include one or more network devices, and one or more terminal devices. As shown in Figure 1, the method provided by the present application can be applicable to communication between a network device and a terminal, that is, uplink or downlink communication. In this communication scenario, the transmitting end in this article can be a terminal in uplink communication or a network device in downlink communication, and the receiving end can be a network device in uplink communication or a terminal in downlink communication. In addition, optionally, the technical solution of the present application can also be applied to sidelink communication. In this communication scenario, the transmitting end is a transmitting terminal in sidelink communication, and the receiving end is a receiving terminal in sidelink communication. In addition, it can also be applied to other communication scenarios, which will not be repeated here.

[0107] Communication systems typically use channel coding to improve data transmission reliability and ensure communication quality. Channel coding and decoding is a core technology in wireless communications, and improvements in its performance directly enhance network coverage and user transmission rates. Polar codes are a channel coding scheme that has been rigorously proven to achieve Shannon channel capacity. Polar codes offer high performance and low complexity. They have been selected by the 3rd Generation Partnership Project (3GPP) as the control channel coding scheme for uplink and downlink (uplink) enhanced mobile broadband (eMBB) scenarios in the fifth generation (5G) of wireless communication.

[0108] Figure 2 is a flow chart of a communication system applicable to the present application. As shown in Figure 2, channel coding is located between source coding and modulation, and is responsible for channel coding the bits generated by the source. Channel decoding is located between demodulation and source decoding, and is responsible for recovering the source bit stream. Taking the use of Polar code for channel coding as an example, the transmitting end uses Polar code to perform channel coding on the source bit stream from the media access control (MAC), and then modulates it according to the code book, sends the modulated symbol through the noisy channel to the receiving end for demodulation, demodulates multiple bits of the symbol to obtain corresponding multiple decoding information, sends the decoding information to the Polar decoder to recover the source bit stream, and uploads it to MAC. For example, the decoding information can be a log likelihood ratio (LLR) or a log likelihood (LL).

[0109] It is understood that the interleaving method provided in this application can be considered as a channel coding scheme, which can be used in dedicated network equipment or general equipment, can be applied to the various network equipment (e.g., base station equipment) described above, and can also be applied to the various terminal devices described above. Specifically, the channel coding scheme is mainly implemented by the channel coding unit in these devices.

[0110] The method provided in the embodiments of the present application can also be implemented by an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), etc., or by software (for example, program code in a memory), without limitation.

[0111] The basic construction method for coding is based on a white Gaussian noise (AWGN) channel, assuming that the input subchannel capacity at each bit position is consistent. However, the reality is that once high-order modulation is used or a fading channel exists, the consistent capacity of the input subchannel at each bit position cannot be guaranteed. For example, when high-order modulation is demodulated, the signal energy of multiple bits within a symbol is not the same after demodulation. This can be understood as the inconsistent capacities of the subchannels in which the multiple bits within a high-order modulation are located. When consecutive bits of a codeword are mapped to a symbol, the demodulation result shows regular variations in the subchannel capacity of the codeword, which does not conform to the assumed channel environment during the coding construction, resulting in poor decoding results. Similarly, fading channels can cause similar problems, resulting in a significant difference in the capacity of some consecutive codeword positions compared to other consecutive codeword positions.

[0112] To address this issue, channel bit interleaving is proposed to randomize subchannel differences, thereby uniformizing the capacity of subchannels across the entire codeword. While the optimal interleaving scheme for channel bit interleaving would be random interleaving of the entire transmitted codeword, random interleaving is difficult to implement in practice. Therefore, feasible interleaving schemes are employed to interleave the codewords. For example, feasible interleaving schemes include row-column interleaving in existing communication standards and triangular interleaving in 5G-NR.

[0113] The following is a brief introduction to row-column interleaving in existing communication standards. In existing communication standards, Polar codes are used as the only codec for control and data channels, and a channel bit interleaving scheme is designed for Polar codes. The modulo 14 row-column interleaving scheme is used to interleave each of the E bits (i.e., E is the codeword transmission length for this transmission) contained in the codeword to be interleaved. bits are input in rows, where 14 is the fixed number of rows corresponding to row-by-row writing. A schematic diagram of row-by-row and column-by-column interleaving of modulo 14 is shown in FIG3 .

[0114] For example, the codeword sequence to be interleaved is e0,e1,e2,e3,…,e E-1 , the codeword sequence obtained after interleaving is f0,f1,f2,f3,…f E-1 , f0 is the first bit output by the interleaver corresponding to the modulo 14 row and column interleaving method. The specific pseudo code is as follows:

[0115] Current channel bit interleaving typically involves extensive interleaving over the entire length of the transmitted codeword to achieve randomness. However, this interleaving approach suffers from a large interleaving range and lacks regularity. Consequently, the interleaving and deinterleaving processes consume significant hardware resources and are difficult to achieve in parallel, making it unsuitable as a channel bit interleaving solution for next-generation communication systems.

[0116] In view of this, the present application proposes an interleaving method that can effectively solve the above technical problems. The method proposed in the present application is described in detail below.

[0117] FIG4 is a schematic flow chart of an interleaving method 400 provided by the present application. The method includes the following steps.

[0118] S410. The transmitting end device performs sub-block interleaving on a codeword sequence to be interleaved to obtain a first codeword sequence, where both the codeword sequence to be interleaved and the first codeword sequence include Y sub-blocks. The Y sub-blocks of the codeword sequence to be interleaved are determined based on a preset number X of bits included in a sub-block, where X and Y are both integers greater than 1.

[0119] Optionally, before performing sub-block interleaving, the length (ie, the number of bits included) of the to-be-interleaved codeword sequence {a0, a1, a2, a3, .... a N-2 ,a N-1} is divided into sub-blocks, and based on the preset length X of a sub-block, the Y sub-blocks {A0, A1, A2…A (Y-1)},in, It is understood that if N cannot be divided by X, then the length of one of the Y sub-blocks is less than X. For example, if the interleaved codeword sequence is divided into sub-blocks according to X starting from the first bit, the length of the last sub-block may be less than X.

[0120] After that, the Y sub-blocks obtained by dividing the interleaved codeword sequence are subjected to sub-block interleaving. For example, the block interleaving sequence is I1, and the Y sub-blocks of the interleaved codeword sequence are subjected to sub-block interleaving based on I1, and the first codeword sequence after interleaving is {B0, B1, B2…B (Y-1)}.

[0121] This application does not impose any specific restrictions on I1, as long as block interleaving can be achieved based on I1. The method for performing sub-block interleaving based on I1 can refer to the following pseudo code:

[0122] For example, the length of the interleaved codeword sequence to be divided into {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26} is 27, and the length of a preset sub-block is X=3. Therefore, after the interleaved codeword sequence is divided, Y=9 sub-blocks are obtained. In the example, the 9 sub-blocks are sub-block 0 = {0, 1, 2}, sub-block 1 = {3, 4, 5}, sub-block 2 = {6, 7, 8}, sub-block 3 = {9, 10, 11}, sub-block 4 = {12, 13, 14}, sub-block 5 = {15, 16, 17}, sub-block 6 = {18, 19, 20}, sub-block 7 = {21, 22, 23}, and sub-block 8 = {24, 25, 26}.

[0123] Then, the 9 divided sub-blocks are interleaved based on the block interleaving sequence I1. For example, the sub-block interleaving sequence I1 = {3, 6, 2, 7, 8, 1, 0, 5, 4}, where 3 means placing sub-block 3 at the position of sub-block 0, 6 means placing sub-block 6 at the position of sub-block 1, and 2 means placing sub-block 2 at the position of sub-block 2 (i.e., remaining unchanged). Details are not repeated here. The codeword sequence obtained after sub-block interleaving (i.e., the first codeword sequence) is {9, 10, 11}, {18, 19, 20}, {6, 7, 8}, {21, 22, 23}, {24, 25, 26}, {3, 4, 5}, {0, 1, 2}, {15, 16, 17}, {12, 13, 14}.

[0124] For example, in the present application, block interleaving of Y sub-blocks can be achieved through the following two possible block interleaving methods. One is a column-by-column interleaving method modulo d1 (i.e., writing by column and reading by row), and the other is a row-by-row interleaving method modulo d2 (i.e., writing by row and reading by column). Here, d1 and d2 are both integers greater than 1 and less than Y, and d1 and d2 are fixed numbers of columns or fixed numbers of rows after writing in the corresponding interleaving method. For ease of description, d1 and d2 are fixed numbers of columns after writing in the corresponding interleaving method.

[0125] For example, d1 and d2 can be prime numbers greater than 1 and less than Y. For example, if Y=34, the values ​​of d1 and d2 are 3, 5, or 7.

[0126] (1) The columns of the modulo d1 are interleaved (hereinafter referred to as the second interleaving method). This interleaving method is used for each of the Y sub-blocks. Sub-blocks are written in columns and read out in rows to complete sub-block interleaving. For example, Y = 34, d1 = 5, then the reading and writing method of sub-blocks under this interleaving method is shown in Figure 5. Specifically, sub-blocks 0 to 33 are read in columns in sequence, and the number of sub-blocks read in each column is That is, the first column reads sub-blocks 0 to 6, the second column reads sub-blocks 7 to 13, and so on. The last column reads the remaining sub-blocks 28 to 33. After that, the sub-blocks corresponding to each column are read out. The sub-blocks {0, 7, 14, 21, 28} of the first row are read out, and the sub-blocks {1, 8, 15, 22, 29} of the second row are read out, until the sub-blocks corresponding to all rows are read out. The sub-blocks read out by row are the interleaved sub-blocks.

[0127] (2) The modulo d2 row-by-row interleaving method (hereinafter referred to as the third interleaving method) is used to write every d2 sub-blocks in Y sub-blocks by row and read them out by column to complete the sub-block interleaving. For example, Y = 34, d2 = 5, and the sub-block reading and writing method under this interleaving method is shown in Figure 6. Specifically, sub-blocks 0 to 33 are read in row by row, and the number of sub-blocks read in each row is 5, that is, sub-blocks 0 to 4 are read in the first row, sub-blocks 5 to 9 are read in the first row, and so on. The remaining sub-blocks 30 to 33 are read in the last row. Then, the sub-blocks {0, 5, 10, 15, 20, 25, 30} of the first column are read out by column, and the sub-blocks {1, 6, 11, 16, 21, 26, 31} of the second column are read out, until the sub-blocks corresponding to all columns are read out. The sub-blocks read out by column are the interleaved sub-blocks.

[0128] S420: The transmitting end device performs cross-subblock bit interleaving within the corresponding subblock group on bits included in at least one subblock group among the L subblock groups to obtain a second codeword sequence, where the L subblock groups are determined based on the Y subblocks of the first codeword sequence and a preset number Z of subblocks included in a subblock group, where Z and L are both integers greater than 1.

[0129] Optionally, before performing cross-subblock bit interleaving, the first codeword sequence {B0, B1, B2…B (Y-1)} is divided into sub-block groups, and based on the number Z of sub-blocks contained in a preset sub-block group, L sub-block groups after the first codeword sequence is divided are obtained, where, It is understood that if Y cannot be divided by Z, then the number of subblocks contained in one of the L subblock groups is less than Z. For example, if the first codeword sequence is divided into subblock groups according to Z starting from the first subblock, the number of subblocks contained in the last subblock group may be less than Z.

[0130] For example, the subblocks included in any of the L subblock groups may be continuous subblocks or discontinuous subblocks, and this application does not impose any limitation on this. It can be understood that the continuous / discontinuous subblocks here refer to the continuous / discontinuous subblocks in the Y subblocks included in the first codeword sequence.

[0131] Then, the bits contained in at least one of the L divided sub-block groups are interleaved across sub-blocks to obtain the output sequence {c0,c1,c2,c3,….c N-2 ,c N-1}. Wherein, the bits contained in at least one sub-block group in the L sub-block groups are interleaved across sub-blocks within the corresponding sub-block group, including: based on the first interleaving method, the bits contained in the first sub-block group in the at least one sub-block group are interleaved across sub-blocks within the first sub-block group, wherein the first sub-block group includes a first sub-block and a second sub-block, and the first interleaving method is used to place the first bit contained in the first sub-block at a first position, wherein the first position is the position of the second bit contained in the second sub-block. That is, the first bit in the first sub-block is placed at a position in the first sub-block group that is different from a bit in the first sub-block (for example, the second sub-block, another sub-block other than the first sub-block), thereby realizing cross-sub-block bit interleaving. The present application does not limit the number of bits interleaved across sub-blocks in the first sub-block group. All bits in the first sub-block group may be interleaved across sub-blocks, or some bits may be interleaved across sub-blocks.

[0132] Optionally, when multiple sub-block groups in the L sub-block groups perform cross-sub-block bit interleaving within the corresponding sub-blocks, the cross-sub-block bit interleaving sequence I2 corresponding to each sub-block group may be the same or different. This application does not impose any specific restrictions on I2, as long as cross-sub-block bit interleaving within the group can be achieved based on I2.

[0133] For example, here, cross-subblock bit interleaving is performed within the subblock group corresponding to each subblock group in L subblocks based on the same cross-subblock bit interleaving sequence I2. The method of performing subblock interleaving based on I2 can refer to the following pseudo code:

[0134] Based on the example in S410, the codeword sequence obtained after sub-block interleaving (i.e., the first codeword sequence) {9, 10, 11}, {18, 19, 20}, {6, 7, 8}, {21, 22, 23}, {24, 25, 26}, {3, 4, 5}, {0, 1, 2}, {15, 16, 17}, {12, 13, 14} (i.e., sub-blocks {3, 6, 2, 7, 8, 1, 0, 5, 4}) is divided into sub-block groups. The number of sub-blocks contained in a preset sub-block group is Z = 3. Therefore, for the first codeword sequence, The 9 sub-blocks are divided from front to back into a sub-block group with every 3 consecutive sub-blocks as one sub-block group, resulting in L = 3 sub-block groups. The 3 sub-block groups are sub-block group 0 = {{9, 10, 11}, {18, 19, 20}, {6, 7, 8}} (i.e., sub-block {3, 6, 2}), sub-block group 1 = {{21, 22, 23}, {24, 25, 26}, {3, 4, 5}} (i.e., sub-block {7, 8, 1}), and sub-block group 2 = {{0, 1, 2}, {15, 16, 17}, {12, 13, 14}} (i.e., sub-block {0, 5, 4}).

[0135] Afterwards, the three divided sub-block groups are interleaved across sub-blocks based on the interleaving sequence I2. It can be seen that the number of bits interleaved across sub-blocks in each sub-block group is X*Z=9. For example, the interleaving sequence I2={3,8,1,6,0,2,7,5,4}, where the interleaving sequence I2={3,8,1,6,0,2,7,5,4} is performed on sub-block group 0={{9,10,11},{18,19,20},{6,7,8}} to obtain {18,8,10,6,9,11,7,20,19}, and the interleaving sequence I2={{21,22,23},{24,25,26},{3,4,5}} is performed on sub-block group 1 to obtain {24,5,22,3,21,23, 4,26,25}, and after cross-subblock bit interleaving of subblock group 2 = {{0,1,2},{15,16,17},{12,13,14}}, {15,14,1,12,0,2,13,17,16}. Therefore, the final codeword sequence (i.e., the second codeword sequence) is {18,8,10,6,9,11,7,20,19,24,5,22,3,21,23,4,26,25,15,14,1,12,0,2,13,17,16}.

[0136] Optionally, if the sub-block interleaving is performed based on the interleaving mode of the columns modulo d1 in S410, Z may be equal to d1, that is, a row of sub-blocks read out is divided into one sub-block group.

[0137] Optionally, if the sub-block interleaving is performed based on the interleaving mode of the row column modulo d2 in S410, Z may be equal to d2, that is, the read column of sub-blocks is divided into a sub-block group.

[0138] A possible specific first interleaving method is given below. In this first interleaving method, the bits in a sub-block group are offset by a modulo n congruence position. The modulo n congruence position means that the remainder after the modulo n operation of the position number of the first bit in the first sub-block of the above-mentioned first sub-block group is the same as the remainder after the modulo n operation of the position number of the second bit in the second sub-block of the first sub-block group, wherein n is an integer greater than 1. For example, n is a prime number greater than 1. The position number S of a bit (for example, the first bit or the second bit) in the first sub-block group indicates that the bit is the Sth bit among all the bits of the first sub-block group.

[0139] Optionally, the offset value corresponding to each bit in the first sub-block may be the same or different, and this application does not impose any limitation on this. For example, if the remainders after a modulo-n operation on the position numbers of multiple bits in the first sub-block group are the same as the remainder after a modulo-n operation on the position number of the first bit, then the first bit may be offset to the position of any bit among the multiple bits.

[0140] It can be understood that since the cross-sub-block bit interleaving is the bit interleaving within a sub-block group, only one sub-block group is used for explanation below. For example, the interleaving method based on the column of modulo 5 shown in Figure 5 is explained, and the sub-block group A corresponding to the sub-block {0, 7, 14, 21, 28} read in the first row is used as an example to illustrate.

[0141] For example, as shown in FIG7 , the length of each sub-block in the sub-block group A is 4 (i.e., it includes 4 bits), where 0-0, 0-1, 0-2, and 0-3 respectively represent the 0th bit to the 3rd bit of sub-block 0, and 7-0, 7-1, 7-2, and 7-3 respectively represent the 0th bit to the 3rd bit of sub-block 7, which are not repeated here. 7 shows that the modulo 3 congruence position is used for offset, and the bit of the position number in sub-block group A with a remainder of 0 after modulo 3 is offset by 0 (i.e., 0*3) bit positions (i.e., the position remains unchanged, for example, the positions of 0-0, 0-3, and 7-2 remain unchanged), the bit of the position number in sub-block group A with a remainder of 1 after modulo 3 is offset by 3 (i.e., 1*3) bit positions (for example, 0-1 is placed at position 7-0 in sub-block 7, and 7-0 is placed at position 7-3 in sub-block 7), and the bit of the position number in sub-block group A with a remainder of 2 after modulo 3 is offset by 6 (i.e., 2*3) bit positions (for example, 0-2 is placed at position 14-0 in sub-block 14, and 7-1 is placed at position 14-3 in sub-block 14).

[0142] For example, as shown in FIG8 , the length of each sub-block in sub-block group A is 4 (i.e., it includes 4 bits), where 0-0, 0-1, 0-2, and 0-3 represent the 0th to 3rd bits of sub-block 0, respectively, and 7-0, 7-1, 7-2, and 7-3 represent the 0th to 3rd bits of sub-block 7, respectively. They will not be described in detail here. FIG8 uses modulo 5 congruence positions for offsetting, and the bits with a modulo 5 remainder of 0 in the position sequence number of sub-block group A are offset by 0 (i.e., 0*5) bit positions (for example, the positions of 0-0 and 7-1 remain unchanged), the bits with a modulo 5 remainder of 1 in the position sequence number of sub-block group A are offset by 5 (1*5) bit positions (for example, 0-1 is placed at position 7-2 in sub-block 7, and 7-2 is placed at position 14-3 in sub-block 14), and the bits with a modulo 5 remainder of 2 in the position sequence number of sub-block group A are offset by 10 (2*5) bit positions (for example, 0 -2 is placed at position 21-0 in sub-block 21, and 7-3 is placed at position 28-1 in sub-block 28), the bits with a remainder of 3 after modulo 5 in the position sequence number in sub-block group A are shifted by 15 (i.e., 3*5) bit positions (for example, 0-3 is placed at position 28-2 in sub-block 28, and 14-0 is placed at position 0-3 in sub-block 0), and the bits with a remainder of 4 after modulo 5 in sub-block group A are shifted by 20 (i.e., 4*5) bit positions (i.e., equivalent to shifting by 0 bit position) (for example, the positions of 7-0 and 14-1 remain unchanged).

[0143] In the above technical solution, the interleaving process of the codeword sequence to be interleaved is divided into two steps. The first step is sub-block interleaving, which disperses the originally clustered bit positions to different positions in the transmitted sequence over a large range through sub-block interleaving. The second step is to perform small-scale cross-sub-block bit interleaving within a sub-block group composed of multiple sub-blocks, thereby breaking the correlation between consecutive bits. In this way, large-scale sub-block interleaving can improve parallelism, while small-scale cross-sub-block bit interleaving within a sub-block group can be achieved through a fixed interconnection relationship, making hardware implementation simple. This solves the problem of irregular deinterleaving caused by the existing interleaving method of performing small-granular bit interleaving over a large range, which cannot improve parallelism and has high hardware overhead.

[0144] A specific example based on method 400 is given below in conjunction with Figure 9. As shown in Figure 9, the codeword sequence to be interleaved includes a total of Y=34 sub-blocks, which are divided into sub-blocks 0 to sub-block 33, and each sub-block includes X=4 bits. As shown in Figure 9, (1) the Y sub-blocks of the codeword sequence to be interleaved are interleaved based on the interleaving method of the column modulo d1=5. Specifically, the first column reads sub-blocks 0 to sub-block 6, the second column reads sub-blocks 7 to sub-block 13, and so on. The last column reads the remaining sub-blocks 28 to sub-block 33. After that, the sub-blocks corresponding to each column are read out, the sub-blocks {0,7,14,21,28} of the first row are read out, and the sub-blocks {1,8,15,22,29} of the second row are read out, until the sub-blocks corresponding to all rows are read out to obtain the first codeword sequence; (2) Then, in this example, Z=d1=5 is taken, that is, the sub-blocks of each row read out by row are divided into Divide into a sub-block group, and obtain L=7 sub-block groups. Perform cross-sub-block bit interleaving on each sub-block group. In this example, all bits in each sub-block group are offset by modulo 3 congruence position to achieve cross-sub-block bit interleaving. The cross-sub-block bit interleaving process for the sub-blocks {0, 7, 14, 21, 28} read in the first row is described in the corresponding FIG7. The method for performing cross-sub-block bit interleaving on the sub-block groups corresponding to the second to seventh rows is the same as the method for performing cross-sub-block bit interleaving on the sub-block groups corresponding to the first row, which will not be repeated here; (3) Finally, after all sub-block groups complete cross-sub-block bit interleaving, the final second codeword sequence is obtained.

[0145] Based on the description in S420, it can be seen that the subblocks included in any of the L subblock groups can be continuous subblocks among the Y subblocks of the first codeword sequence, or they can be discontinuous subblocks. It can be understood that in Figure 9, any of the L subblock groups includes Z continuous subblocks among the Y subblocks in the first codeword sequence. The following specifically describes an implementation method in which one of the L subblock groups includes discontinuous subblocks among the Y subblocks in the first codeword sequence. By way of example, in this implementation method, the first codeword sequence can be obtained based on the second interleaving method (i.e., the column-by-column interleaving method modulo d1) or based on the third interleaving method (i.e., the row-by-row interleaving method modulo d2). For ease of description, the following explanation is given by taking the block interleaving of Y subblocks of the interleaved codeword sequence based on the third interleaving method as an example.

[0146] For example, in this implementation, the third interleaving method is further used to perform sub-block interleaving on at least one of the d2 sub-block groups within the corresponding sub-block group between writing by row and reading by column, wherein the d2 sub-block groups are the sub-block groups corresponding to the d2 columns of sub-blocks after writing by row. Then, the first codeword sequence is the sequence obtained by reading by column after performing block interleaving within the corresponding sub-block group, and the L sub-block groups can be the L sub-block groups obtained by reading by row every Z sub-blocks after performing block interleaving within the corresponding sub-block group. Therefore, any group of sub-block groups among the L sub-block groups includes discontinuous sub-blocks among the Y sub-blocks in the first codeword sequence.

[0147] Optionally, Z is equal to d2, that is, after writing in rows and performing sub-block interleaving within the sub-block group, each row of sub-blocks in the corresponding sub-blocks of each column is divided into one sub-block group.

[0148] Optionally, the third interleaving method is used to perform sub-block interleaving on at least one of the d2 sub-block groups within the corresponding sub-block group between writing in rows and reading in columns, including: the third interleaving method is used to perform sub-block interleaving on at least one of the d2 sub-block groups by shifting the sub-blocks in the column direction within the corresponding sub-block group between writing in rows and reading in columns to achieve sub-block interleaving.

[0149] The following is an example description with reference to Figure 10. As shown in Figure 10, the codeword sequence to be interleaved includes Y=34 sub-blocks, which are divided into sub-blocks 0 to 33, and each sub-block includes X=4 bits.As shown in FIG10 , (1) the Y sub-blocks of the interleaved codeword sequence are interleaved based on the interleaving method of the row column with modulo d2=5. Specifically, the number of sub-blocks read in each row is 5, that is, the first row reads sub-blocks 0 to 4, the first row reads sub-blocks 5 to 9, and so on. The last row reads the remaining sub-blocks 30 to 33. (2) Afterwards, each column of sub-blocks is shifted (i.e., interleaved) in the column direction (i.e., within a sub-block group). For example, the first column of sub-blocks remains unchanged, the second column of sub-blocks is shifted upward by 1 sub-block, the third column of sub-blocks is shifted upward by 2 sub-blocks, the fourth column of sub-blocks is shifted upward by 3 sub-blocks, and the fifth column of sub-blocks is shifted upward by 5 sub-blocks. The positions of the sub-blocks in each column after the shift are shown in FIG10 . The first codeword sequence obtained by reading out the columns is the sub-block {0, 5, 10, 15, 20, 25, 30, 31, 1, 6, 11, 16, 21, 26, 27, 32, 2, 7, 12, 17, 22, 13, 18, 23, 28, 33, 3, 8, 9, 14, 19, 24, 29, 4}; (3) In this example, Z = d2 = 5, and the sub-blocks in each column of (2) are shifted in the column direction. Each row of sub-blocks is divided into a sub-block group by reading out the sub-blocks in the row direction, and L = 7 sub-block groups are obtained. The 7 sub-block groups are sub-block group 0 = sub-block {0, 31, 27, 13, 9}, sub-block group 1 = {5, 1, 32, 18, 14}, sub-block group 2 = {10, 6, 2 ,23,19},sub-block group 3={15,11,7,28,24},sub-block group 4={20,16,12,33,29},sub-block group 5={25,21,17,3,4},sub-block group 6={30,26,22,8}, perform cross-sub-block bit interleaving on each sub-block group. In this example, all bits in each sub-block group are offset by modulo 3 congruence position to achieve cross-sub-block bit interleaving. Take the cross-sub-block bit interleaving of the bits contained in the sub-block group 0 (i.e., sub-block {0,31,27,13,9}) read in the first row as an example to illustrate. The bits with a remainder of 0 after modulo 3 in the sub-block group are offset by 0 sub-blocks (i.e., the position remains unchanged, for example, 0-0, 0-3, 31- 2 remains unchanged), the bits with a remainder of 1 after the position sequence number modulo 3 in the sub-block group are shifted by 1 sub-block (for example, 0-1 is placed at the position of 31-0 in sub-block 31, and 31-0 is placed at the position of 31-3 in sub-block 31), and the bits with a remainder of 2 after the position sequence number modulo 3 in the sub-block group are shifted by 2 sub-blocks (for example, 0-2 is placed at the position of 27-0 in sub-block 27, and 31-1 is placed at the position of 27-3 in sub-block 27). The method of performing cross-sub-block bit interleaving on the sub-block groups corresponding to the second to seventh rows is the same as the method of performing cross-sub-block bit interleaving on the sub-block groups corresponding to the first row, which will not be repeated here; (4) Finally, after all sub-block groups complete the cross-sub-block bit interleaving, the sub-blocks are read column by column to obtain the final second codeword sequence.

[0150] It can be understood that in this implementation, cross-sub-block bit interleaving can be regarded as implemented in the block interleaving process, that is, based on the third interleaving method, between row writing and column reading, each column of sub-blocks is first interleaved as a block, and then the obtained Y sub-blocks are divided into L sub-block groups in a row-by-row reading manner. It should be noted that the row-by-row reading method here is not a real reading, but only describes a method of dividing L sub-block groups. After that, after completing the cross-sub-block bit interleaving of the L sub-block groups, the Y sub-blocks are read out by column.

[0151] Optionally, the interleaving method corresponding to this implementation can also be implemented by another interleaving method. The following introduces another interleaving method. The method includes:

[0152] 1) The transmitting device writes every d2 sub-blocks of the Y sub-blocks in rows, where the Y sub-blocks are obtained by dividing the interleaved codeword sequence based on a preset number X of bits contained in a sub-block, where X and Y are both integers greater than 1, and d2 is an integer greater than 1 and less than Y.

[0153] 2) The transmitting end device performs sub-block interleaving on at least one of the d2 sub-block groups within the corresponding sub-block group, wherein the d2 sub-block groups are the sub-block groups corresponding to the d2 columns of sub-blocks after writing in rows.

[0154] 3) The transmitting end device performs cross-subblock bit interleaving within the corresponding subblock group on bits included in at least one subblock group among the L subblock groups, where the L subblock groups are subblock groups corresponding to when Y subblocks after subblock interleaving is performed within the corresponding subblock group based on a preset number Z of subblocks included in the subblock group, and Z and L are both integers greater than 1.

[0155] 4) The transmitting end device obtains a second codeword sequence, where the second codeword sequence is a sequence obtained by reading sub-blocks column by column.

[0156] The interleaving method shown in method 400 has been described in detail above. Based on the process shown in FIG2 , after obtaining the second codeword sequence, the transmitter modulates the codeword according to the codebook and transmits the modulated symbols over a noisy channel to the receiver for demodulation. Specifically, the receiver simultaneously demodulates the N bits within the symbol to obtain a to-be-deinterleaved sequence containing N decoding information. The receiver then deinterleaves the to-be-deinterleaved sequence. This deinterleaving method is described in detail below.

[0157] Figure 11 is a schematic flow chart of a deinterleaving method 1100 provided herein. It will be appreciated that, since the deinterleaving method shown in Figure 11 deinterleaves the second codeword sequence determined in method 400, corresponding to method 400, the receiving end must first perform bit deinterleaving and then perform sub-block deinterleaving. This method includes the following steps.

[0158] S1110. The receiving device performs cross-subblock debit interleaving within the corresponding subblock group on decoding information contained in at least one subblock group among the L subblock groups to obtain a first deinterleaved sequence, wherein the L subblock groups are determined based on Y subblocks of the sequence to be deinterleaved and a preset number Z of subblocks contained in a subblock group, the Y subblocks are determined based on a preset number X of decoding information contained in a subblock, and X, Y, Z, and L are all integers greater than 1.

[0159] Optionally, before performing cross-sub-block deinterleaving, first, the sequence to be deinterleaved containing N decoding information needs to be divided into sub-blocks, and based on the preset number X of decoding information contained in one sub-block, the sequence to be deinterleaved is divided into Y sub-blocks, where: It represents rounding up. Then, the Y sub-blocks obtained by dividing the deinterleaved sequence need to be divided into sub-block groups. Based on the number of sub-blocks Z contained in a preset sub-block group, the L sub-block groups after the deinterleaved sequence is divided are obtained. It should be noted that if N is not divisible by X, then the number of decoded information contained in one of the Y sub-blocks is less than X. Similarly, if Y is not divisible by Z, then the number of sub-blocks contained in one of the L sub-block groups is less than Z.

[0160] Then, the decoded information contained in at least one of the L sub-block groups obtained after division is bit-deinterleaved across sub-blocks to obtain a deinterleaved output sequence (ie, a first deinterleaved sequence), which includes Y sub-blocks.

[0161] It can be understood that the values ​​of the same parameters in the deinterleaving method 1100 and the method 400 are the same.

[0162] It can also be understood that the L sub-chunks in S1110 correspond one-to-one to the L sub-chunks in S420. Specifically, the first sub-chunk in the L sub-chunks in S1110 includes multiple decoded information corresponding to multiple bits of the first sub-chunk in the L sub-chunks in S420 after demodulation. The first sub-chunk in S420 and the first sub-chunk in S1110 are corresponding sub-chunks.

[0163] Optionally, performing cross-subblock bit deinterleaving on the decoding information contained in at least one sub-block group among the L sub-block groups within the corresponding sub-block group includes: performing cross-subblock bit interleaving on the decoding information contained in a first sub-block group among the at least one sub-block group within the first sub-block group based on a first deinterleaving method, wherein the first sub-block group includes a first sub-block and a second sub-block, and the first deinterleaving method is used to place the first decoding information contained in the second sub-block at a second position, wherein the second position is a position where the second decoding information is located in the first sub-block.

[0164] It can be understood that the first deinterleaving method is the inverse operation of the first interleaving method. That is, the transmitting end performs cross-sub-block bit interleaving on the bits in the first sub-block group in S420 based on the first interleaving method, and the transmitting end deinterleaves the decoding information obtained from the first sub-block group in S1110 based on the first deinterleaving method, that is, performs the inverse operation corresponding to the interleaving operation. Based on the description in S420, the transmitting end places the first bit from the second position to the first position based on the first interleaving method, and the receiving end places the decoding information of the first position (that is, the first decoding information corresponding to the first bit) to the second position based on the first deinterleaving method during deinterleaving. Optionally, the remainder after the modulo n operation of the position number of the first position is the same as the remainder after the modulo n operation of the position number of the second position, where n is an integer greater than 1.

[0165] S1120: The receiving end device performs de-sub-block interleaving on the first de-interleaved sequence to obtain a second de-interleaved sequence.

[0166] Specifically, sub-block deinterleaving is performed on the Y sub-blocks of the first deinterleaved sequence to obtain a second deinterleaved sequence.

[0167] It can be understood that the deblocking interleaving mode is determined based on the corresponding block interleaving mode. For example, the following describes the corresponding deblocking interleaving mode based on the interleaving mode of the columns of the modulo d1 and the interleaving mode of the rows of the modulo d2 given in S410.

[0168] (1) Second deinterleaving mode: This deinterleaving mode corresponds to the column interleaving mode modulo d1. The second deinterleaving mode is used to write the Y sub-blocks of the first deinterleaving sequence by row and read them by column to complete sub-block deinterleaving. d1 is the number of columns written corresponding to the second deinterleaving mode, and the number of sub-blocks written in each row is determined based on the column interleaving mode modulo d1.

[0169] Among them, the number of sub-blocks written in each row is determined by the interleaving method based on the columns of modulo d1. It can also be understood that the number of sub-blocks written in each row needs to be the same as the number of sub-blocks in each row after being written in the interleaving method based on the columns of modulo d1.

[0170] (2) Third deinterleaving mode: This deinterleaving mode corresponds to the interleaving mode listed in the row order modulo d2. The third deinterleaving mode is used to write the Y sub-blocks of the first deinterleaving sequence by column and read them out by row to complete sub-block deinterleaving. d2 is the number of columns written corresponding to the third deinterleaving mode, and the number of sub-blocks written in each column is determined based on the interleaving mode listed in the row order modulo d2.

[0171] Among them, the number of sub-blocks written in each column is determined based on the interleaving method of the rows and columns modulo d2. It can also be understood that the number of sub-blocks written in each column needs to be the same as the number written in each column based on the interleaving method of the rows and columns modulo d2.

[0172] It should be noted that, for the example shown in FIG10 , cross-subblock bit interleaving is implemented during block interleaving. That is, based on the third interleaving method, between row-based writing and column-based reading, each column of subblocks is first subjected to block interleaving. The resulting Y subblocks are then divided into L subblock groups using row-based reading. After cross-subblock bit interleaving is performed on the L subblock groups, the interleaved Y subblocks are read out column-by-column. Accordingly, during deinterleaving, the third deinterleaving method in S1120 is further used to perform desubblock interleaving on at least one of the d2 subblock groups within the corresponding subblock group between column-based writing and row-based reading. The d2 subblock groups are the subblock groups corresponding to the d2 columns of subblocks after column-based writing. During deinterleaving, the L subblock groups in S1110 are the subblock groups obtained by row-based reading before desubblock interleaving is performed on the d2 subblock groups within the corresponding subblock group. The remaining description of the deinterleaving method is the same as that of the above-described deinterleaving method and will not be repeated here.

[0173] The above describes in detail the interleaving method 400 and the corresponding deinterleaving method 1100. The following describes in detail another interleaving method and the corresponding deinterleaving method.

[0174] Figure 12 is a schematic flow chart of an interleaving method 1200 provided herein. In method 1200, the interleaving process for an interleaved codeword sequence is also divided into two steps. Unlike method 400, in method 1200, the first step is sub-block interleaving, and the second step is performing small-scale cross-sub-block bit interleaving within a sub-block group consisting of multiple sub-blocks. This method includes the following steps.

[0175] S1210. The transmitting end device performs cross-subblock bit interleaving within the corresponding subblock group on bits included in at least one of the L subblock groups to obtain a third codeword sequence, where the L subblock groups are determined based on Y subblocks of the codeword sequence to be interleaved and a preset number Z of subblocks included in a subblock group, the Y subblocks are determined based on a preset number X of bits included in a subblock, and X, Y, Z, and L are all integers greater than 1.

[0176] Optionally, before performing cross-subblock bit interleaving, first, it is necessary to interleave the codeword sequence {a0, a1, a2, a3, .... a N-2 ,a N-1} is divided into sub-blocks, and based on the preset length X of a sub-block, the Y sub-blocks {A0, A1, A2…A (Y-1)},in, Indicates rounding up. Then, the Y sub-blocks obtained by dividing the interleaved codeword sequence need to be divided into sub-block groups. Based on the number of sub-blocks Z contained in a preset sub-block group, the L sub-block groups after the interleaved codeword sequence is divided are obtained, where It should be noted that if N is not divisible by X, the length of one of the Y sub-blocks is less than X. Similarly, if Y is not divisible by Z, the number of sub-blocks contained in one of the L sub-block groups is less than Z.

[0177] Then, the bits contained in at least one of the L sub-block groups obtained after division are interleaved across sub-blocks to obtain an interleaved output sequence {b0, b1, b2, b3, .... b N-2 ,b N-1} (i.e., the third codeword sequence), the Y sub-blocks of the third codeword sequence are {B0, B1, B2…B (Y-1)}. Wherein, the bits contained in at least one sub-block group in the L sub-block groups are interleaved across sub-blocks in the corresponding sub-block group, including: based on the first interleaving method, the bits contained in the first sub-block group in the at least one sub-block group are interleaved across sub-blocks in the first sub-block group, wherein the first sub-block group includes a first sub-block and a second sub-block, and the first interleaving method is used to place the first bit contained in the first sub-block in a first position, wherein the first position is the position of the second bit contained in the second sub-block. That is, the first bit in the first sub-block is placed in a position in the first sub-block group that is different from a bit in the first sub-block (for example, the second sub-block), thereby realizing cross-sub-block bit interleaving. The present application does not limit the number of bits interleaved across sub-blocks in the first sub-block group, and cross-sub-block bit interleaving can be performed on all bits in the first sub-block group, or cross-sub-block bit interleaving can be performed on some bits.

[0178] Optionally, when multiple sub-block groups in the L sub-block groups perform cross-sub-block bit interleaving within the corresponding sub-blocks, the cross-sub-block bit interleaving sequence I2 corresponding to each sub-block group may be the same or different. This application does not impose any specific restrictions on I2, as long as cross-sub-block bit interleaving within the group can be achieved based on I2.

[0179] For example, here we illustrate the cross-subblock bit interleaving within the subblock group corresponding to each subblock group in L subblocks based on the same cross-subblock bit interleaving sequence I2. The pseudo code for subblock interleaving based on I2 is as follows:

[0180] The following is an illustration with reference to a specific example. For example, first, the to-be-interleaved codeword sequence {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26} of length 27 is divided into sub-blocks. The length of a preset sub-block is X=3. Therefore, after the to-be-interleaved codeword sequence is divided, Y=9 sub-blocks are obtained, wherein the 9 sub-blocks are sub-block 0={0,1,2}, sub-block 1={3,4,5}, sub-block 2={6,7,8}, sub-block 3={9,10,11}, sub-block 4={12,13,14}, sub-block 5={15,16,17}, sub-block 6={18,19, 20}, sub-block 7 = {21, 22, 23}, sub-block 8 = {24, 25, 26}, then, the 9 sub-blocks are divided into sub-block groups, and the number of sub-blocks contained in a preset sub-block group is Z = 3. Therefore, the 9 sub-blocks of the first codeword sequence are divided from the front to the back according to each consecutive 3 sub-blocks as a sub-block group to obtain L = 3 sub-block groups, and the 3 sub-block groups are sub-block group 0 = {{0, 1, 2}, {3, 4, 5}, {6, 7, 8}}, sub-block group 1 = {{9, 10, 11}, {12, 13, 14}, {15, 16, 17}}, and sub-block group 2 = {{18, 19, 20}, {21, 22, 23}, {24, 25, 26}}.

[0181] Afterwards, the three divided sub-block groups are interleaved across sub-blocks based on the interleaving sequence I2. It can be seen that the number of bits interleaved across sub-blocks in each sub-block group is X*Z=9. For example, the interleaving sequence I2={3,8,1,6,0,2,7,5,4} is used to interleave the sub-block group 0={{0,1,2},{3,4,5},{6,7,8}} across sub-blocks to obtain {3,8,1,6,0,2,7,5,4}, the sub-block group 1={{9,10,11},{12,13,14},{15,16,17}} across sub-blocks to obtain {12,17,10,15,9,11,16,14,13}, the sub-block group 2={{ The cross-subblock bit interleaving of the codes {1, 26, 19, 24, 18, 20}, {21, 22, 23}, {24, 25, 26}} is performed to obtain {21, 26, 19, 24, 18, 20, 25, 23, 22}. Therefore, the codeword sequence obtained after cross-subblock bit interleaving (i.e., the third codeword sequence) is {3, 8, 1}, {6, 0, 2}, {7, 5, 4}, {12, 17, 10}, {15, 9, 11}, {16, 14, 13}, {21, 26, 19}, {24, 18, 20}, {25, 23, 22}.

[0182] For example, in the first interleaving mode of this method, bits in a sub-block group are interleaved by shifting the modulo-n congruence positions. For details, refer to the description in S420 and the corresponding example, which will not be repeated here.

[0183] S1220: The transmitting end device performs sub-block interleaving on the Y sub-blocks of the third codeword sequence to obtain a fourth codeword sequence.

[0184] The Y sub-blocks of the third codeword sequence are {B0, B1, B2…B (Y-1)}, then the Y sub-blocks of the third codeword sequence are sub-block interleaved. For example, the block interleaving sequence is I1, and the Y sub-blocks of the third codeword sequence are sub-block interleaved based on I1, and the interleaved fourth codeword sequence is {c0,c1,c2,c3,….c N-2 ,c N-1}.

[0185] This application does not impose any specific restrictions on I1, as long as block interleaving can be achieved based on I1. The method for performing sub-block interleaving based on I1 can refer to the following pseudo code:

[0186] For example, based on the example in S1210, the 9 sub-blocks of the third codeword sequence are sub-block interleaved through the block interleaving sequence I1. If the sub-block interleaving sequence I1 = {3, 6, 2, 7, 8, 1, 0, 5, 4}, 3 means placing sub-block 3 at the position of sub-block 0, 6 means placing sub-block 6 at the position of sub-block 1, and 2 means placing sub-block 2 at the position of sub-block 2 (i.e., remaining unchanged), they will not be repeated here. The codeword sequence obtained after sub-block interleaving is {12, 17, 10}, {21, 26, 19}, {7, 5, 4}, {24, 18, 20}, {25, 23, 22}, {6, 0, 2}, {3, 8, 1}, {16, 14, 13}, {15, 9, 11}, and the final codeword sequence (i.e., the fourth codeword sequence) is {12, 17, 10, 21, 26, 19, 7, 5, 4, 24, 18, 20, 25, 23, 22, 6, 0, 2, 3, 8, 1, 16, 14, 13, 112, 9, 11}.

[0187] For example, in the present application, block interleaving of Y sub-blocks of the third codeword sequence can be achieved through the following two possible block interleaving methods. One is a column-wise interleaving method modulo d1, and the other is a row-wise interleaving method modulo d2, where d1 and d2 are both integers greater than 1 and less than Y, and d1 and d2 are fixed column numbers or fixed row numbers after the corresponding interleaving method is written. For ease of description, d1 and d2 are fixed column numbers after the corresponding interleaving method is written.

[0188] (1) The columns of the modulo d1 are interleaved (hereinafter referred to as the second interleaving method), which is used to interleave each of the Y sub-blocks of the third codeword sequence. Sub-blocks are written in columns and read out in rows to complete sub-block interleaving.

[0189] (2) A modulo d2 row-by-row interleaving method (hereinafter referred to as the third interleaving method) is used to write every d2 sub-blocks of the Y sub-blocks of the third codeword sequence in rows and read them out in columns to complete sub-block interleaving.

[0190] In the above technical solution, the interleaving process of the codeword sequence to be interleaved is divided into two steps. The first step is to perform small-scale cross-subblock bit interleaving within a sub-block group consisting of multiple sub-blocks to break the correlation between consecutive bits. The second step is sub-block interleaving, so that the originally clustered bit positions are dispersed to different positions of the transmitted sequence over a large range through block interleaving. In this way, the parallelism can be improved through large-scale sub-block interleaving, and the small-scale cross-subblock bit interleaving within the sub-block group can itself be obtained through a fixed interconnection relationship, and the hardware implementation is easy, thereby solving the problems of irregular deinterleaving caused by performing small-granularity bit interleaving over a large range of the original interleaving, which cannot improve parallelism and has high hardware overhead.

[0191] A specific example based on method 1200 is given below in conjunction with Figure 13. As shown in Figure 13, the codeword sequence to be interleaved includes Y=34 sub-blocks, which are divided into sub-blocks 0 to 33, and each sub-block includes X=4 bits. As shown in FIG13 , (1) in this example, Z=5 is taken, that is, every 5 consecutive sub-blocks in the 34 sub-blocks are divided into L=7 sub-block groups, and cross-sub-block bit interleaving is performed on each sub-block group. In this example, all bits in each sub-block group are offset by modulo 3 congruence positions to achieve cross-sub-block bit interleaving. The cross-sub-block bit interleaving of the bits contained in the sub-blocks {0,1,2,3,4} in the first sub-block group is used as an example for explanation. As shown in FIG13 , the bits with a position sequence number of 0 after modulo 3 in the sub-block group are offset by 0 sub-blocks, the bits with a position sequence number of 1 after modulo 3 in the sub-block group are offset by 1 sub-block, and the bits with a position sequence number of 2 after modulo 3 in the sub-block group are offset by 2 sub-blocks. The method of cross-sub-block bit interleaving for the remaining sub-block groups is the same as that for the first sub-block group. The bit interleaving method is the same and will not be described here in detail; (2) After all sub-block groups complete cross-sub-block bit interleaving, a third codeword sequence is obtained, and the third codeword sequence also includes Y sub-blocks; (3) The Y sub-blocks of the third codeword sequence are sub-block interleaved based on the interleaving method of the row column of modulo d2=5. Specifically, the number of sub-blocks read in each row is 5, that is, the first row reads sub-blocks 0 to sub-block 4, the first row reads sub-blocks 5 to sub-block 9, and so on. The last row reads the remaining sub-blocks 30 to sub-block 33, and the sub-blocks {0, 5, 10, 15, 20, 25, 30} of the first column are read out column by column, and the sub-blocks {1, 6, 11, 16, 21, 26, 31} of the second row are read out, and so on, until the sub-blocks corresponding to all columns are read out, and the final fourth codeword sequence is obtained.

[0192] The above scheme, in E max =8320, when the deinterleaving throughput reaches 64G, the required ASIC circuit area is only E max =8192 Yangtze-Delta interleaving solution requires 83% of the ASIC circuit area, and the throughput is 8 times that of the delta interleaving solution, with an area efficiency of 9.6 times.

[0193] The interleaving method shown in method 1200 has been described in detail above. Similarly, based on the process shown in FIG2 , after obtaining the fourth codeword sequence, the transmitter modulates the codeword according to the codebook and transmits the modulated symbols over a noisy channel to the receiver for demodulation. Specifically, the receiver simultaneously demodulates the N bits within the symbol to obtain a to-be-deinterleaved sequence containing N decoding information. The receiver then deinterleaves the to-be-deinterleaved sequence. This deinterleaving method is described in detail below.

[0194] Figure 14 is a schematic flow chart of a deinterleaving method 1400 provided herein. It will be appreciated that, since the deinterleaving method shown in Figure 14 deinterleaves the fourth codeword sequence determined by method 1200, corresponding to method 1200, the receiving end must first perform sub-block deinterleaving and then perform bit deinterleaving. This method includes the following steps.

[0195] S1410. The receiving device performs desub-block interleaving on the sequence to be deinterleaved to obtain a third deinterleaved sequence, where both the sequence to be deinterleaved and the third deinterleaved sequence include Y sub-blocks, and the Y sub-blocks of the sequence to be deinterleaved are determined based on a preset number X of decoding information contained in one sub-block, where X and Y are both integers greater than 1.

[0196] Optionally, before performing de-subblock interleaving, the sequence to be deinterleaved containing N pieces of decoding information is divided into sub-blocks, and based on a preset number X of decoding information contained in one sub-block, Y sub-blocks are obtained after the sequence to be deinterleaved is divided, wherein: It should be noted that if N cannot be divided by X, then the length of one of the Y sub-blocks is less than X.

[0197] Afterwards, sub-block deinterleaving is performed on the Y sub-blocks obtained by dividing the sequence to be deinterleaved to obtain a deinterleaved output sequence (ie, a third deinterleaved sequence), where the third deinterleaved sequence includes Y sub-blocks.

[0198] It can be understood that the values ​​of the same parameters in the deinterleaving method 1400 and the method 1200 are the same.

[0199] It can also be understood that the deblocking interleaving mode is determined based on the corresponding block interleaving mode. For example, the following describes the corresponding deblocking interleaving mode based on the interleaving mode determined by the column order of modulo d1 and the interleaving mode determined by the row order of modulo d2 given in S1220.

[0200] (1) Second deinterleaving mode: This deinterleaving mode corresponds to the column interleaving mode modulo d1. The second deinterleaving mode is used to write Y sub-blocks of the sequence to be deinterleaved by row and read them by column to complete sub-block deinterleaving. d1 is the number of columns written corresponding to the second deinterleaving mode, and the number of sub-blocks written in each row is determined based on the column interleaving mode modulo d1.

[0201] (2) Third deinterleaving mode: This deinterleaving mode corresponds to the interleaving mode listed in the row order modulo d2. The third deinterleaving mode is used to write the Y sub-blocks of the sequence to be deinterleaved by column and read them out by row to complete sub-block deinterleaving. d2 is the number of columns written corresponding to the third deinterleaving mode, and the number of sub-blocks written in each column is determined based on the interleaving mode listed in the row order modulo d2.

[0202] S1420. The receiving device performs cross-subblock debit interleaving within the corresponding subblock group on the decoding information contained in at least one subblock group among the L subblock groups, to obtain a fourth deinterleaved sequence, where the L subblock groups are determined based on the Y subblocks of the third deinterleaved sequence and a preset number Z of subblocks contained in a subblock group, the Y subblocks are determined based on a preset number X of decoding information contained in a subblock, and both Z and L are integers greater than 1.

[0203] Optionally, before performing cross-subblock deinterleaving, the Y subblocks of the third deinterleaved sequence need to be divided into subblock groups. Based on the number Z of subblocks included in a preset subblock group, L subblock groups are obtained after the Y subblocks of the third deinterleaved sequence are divided, where: It should be noted that if Y cannot be divided by Z, the number of sub-blocks contained in one of the L sub-block groups is less than Z.

[0204] It can be understood that the L sub-block groups in S1420 correspond one-to-one to the L sub-blocks in S1210. Specifically, the first sub-block group in the L sub-block groups in S1420 includes multiple decoded information corresponding to multiple bits of the first sub-block group in the L sub-block groups in S1210 after demodulation. The first sub-block group in S1210 and the first sub-block group in S1420 are corresponding sub-block groups.

[0205] Optionally, performing cross-subblock debit interleaving on the decoding information contained in at least one sub-block group among the L sub-block groups within the corresponding sub-block group includes: performing cross-subblock debit interleaving on the decoding information contained in a first sub-block group among the at least one sub-block group within the first sub-block group based on a first deinterleaving method, wherein the first sub-block group includes a first sub-block and a second sub-block, and the first deinterleaving method is used to place the first decoding information contained in the second sub-block at a second position, wherein the second position is a position where the second decoding information is located in the first sub-block.

[0206] It can be understood that the first deinterleaving method is the inverse operation of the first interleaving method. That is, the transmitting end performs cross-sub-block bit interleaving on the bits in the first sub-block group in S1210 based on the first interleaving method, and the transmitting end deinterleaves the decoding information obtained from the first sub-block group in S1420 based on the first deinterleaving method, that is, performs the inverse operation corresponding to the interleaving operation. Based on the description in S1210, the transmitting end places the first bit from the second position to the first position based on the first interleaving method, and the receiving end places the decoding information of the first position (that is, the first decoding information corresponding to the first bit) to the second position based on the first deinterleaving method during deinterleaving. Optionally, the remainder after the position number of the first position is subjected to a modulo n operation is the same as the remainder after the position number of the second position is subjected to a modulo n operation, where n is an integer greater than 1.

[0207] It is understood that the steps in the above figures are merely illustrative and not intended to be strict limitations. Furthermore, the sequence numbers of the above processes do not necessarily indicate the order in which they are to be executed. The order in which each process is to be executed should be determined by its function and inherent logic, and should not constitute any limitation on the implementation of the embodiments of this application.

[0208] It can also be understood that some optional features in the various embodiments of the present application may not depend on other features in certain scenarios, and may also be combined with other features in certain scenarios, without limitation.

[0209] It can also be understood that in the above-mentioned various method embodiments, the methods and operations implemented by a device (a transmitting device or a receiving device) can also be implemented by components of the device (such as chips or circuits), without limitation.

[0210] Corresponding to the methods provided in the above method embodiments, embodiments of the present application also provide corresponding apparatuses, which include modules for executing the corresponding methods in the above method embodiments. The modules may be software, hardware, or a combination of software and hardware. It is understood that the technical features described in the above method embodiments are also applicable to the following apparatus embodiments.

[0211] Figure 15 is a schematic block diagram of a communication device 1500 provided in an embodiment of the present application. As shown in Figure 15 , the device 1500 may include a communication unit 1510 and a processing unit 1520. The communication unit 1510 can communicate with the outside world, and the processing unit 1520 is used for data processing. The communication unit 1510 may also be referred to as a communication interface or a transceiver unit.

[0212] In one possible design, the device 1500 can implement steps or processes corresponding to those performed by the sending end device in the above method embodiment, wherein the processing unit 1520 is used to perform processing-related operations of the sending end device in the above method embodiment, and the communication unit 1510 is used to perform sending-related operations of the sending end device in the above method embodiment.

[0213] In another possible design, the device 1500 can implement steps or processes corresponding to those performed by the receiving device in the above method embodiment, wherein the communication unit 1510 is used to perform reception-related operations of the receiving device in the above method embodiment, and the processing unit 1520 is used to perform processing-related operations of the receiving device in the above method embodiment.

[0214] It can be understood that the device 1500 here is embodied in the form of a functional unit. The term "unit" here can refer to an application specific integrated circuit (ASIC), an electronic circuit, a processor (such as a shared processor, a dedicated processor or a group processor, etc.) and a memory for executing one or more software or firmware programs, a combined logic circuit and / or other suitable components that support the described functions. In an optional example, those skilled in the art can understand that the device 1500 can be specifically the sending end device in the above embodiment, and can be used to execute the various processes and / or steps corresponding to the sending end device in the above method embodiment, or the device 1500 can be specifically the receiving end device in the above embodiment, and can be used to execute the various processes and / or steps corresponding to the receiving end device in the above method embodiment. To avoid repetition, it will not be repeated here.

[0215] The apparatus 1500 of each of the above-mentioned solutions has the function of implementing the corresponding steps performed by the transmitting end device in the above-mentioned method, or the apparatus 1500 of each of the above-mentioned solutions has the function of implementing the corresponding steps performed by the receiving end device in the above-mentioned method. The functions can be implemented by hardware, or can be implemented by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-mentioned functions; for example, the communication unit can be replaced by a transceiver (for example, the transmitting unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units, such as the processing unit, can be replaced by a processor to respectively perform the transmitting and receiving operations and related processing operations in each method embodiment.

[0216] In addition, the above-mentioned communication unit can also be a transceiver circuit (for example, it can include a receiving circuit and a transmitting circuit), and the processing unit can be a processing circuit. In an embodiment of the present application, the device in Figure 15 can be a receiving end device or a transmitting end device in the aforementioned embodiment, or it can be a chip or a chip system, such as a system on chip (SoC). Among them, the communication unit can be an input and output circuit, a communication interface; the processing unit is a processor or microprocessor or integrated circuit integrated on the chip. This is not limited here.

[0217] Figure 16 is a schematic block diagram of a communication device 1600 provided in an embodiment of the present application. The device 1600 includes a processor 1610 and a transceiver 1620. The processor 1610 and the transceiver 1620 communicate with each other via an internal connection path. The processor 1610 is configured to execute instructions to control the transceiver 1620 to send and / or receive signals.

[0218] Optionally, the apparatus 1600 may further include a memory 1630, which communicates with the processor 1610 and the transceiver 1620 via an internal connection path. The memory 1630 is used to store instructions, and the processor 1610 can execute the instructions stored in the memory 1630. In one possible implementation, the apparatus 1600 is used to implement the various processes and steps corresponding to the transmitting end device in the above-mentioned method embodiment. In another possible implementation, the apparatus 1600 is used to implement the various processes and steps corresponding to the receiving end device in the above-mentioned method embodiment.

[0219] It is understood that apparatus 1600 may specifically be the transmitting device or receiving device in the above-described embodiments, or may be a chip or chip system. Correspondingly, transceiver 1620 may be the transceiver circuit of the chip, without limitation herein. Specifically, apparatus 1600 may be used to execute the various steps and / or processes corresponding to the transmitting device or receiving device in the above-described method embodiments.

[0220] Optionally, the memory 1630 may include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory may include a non-volatile random access memory. For example, the memory may also store device type information. The processor 1610 may be configured to execute instructions stored in the memory. When the processor 1610 executes the instructions stored in the memory, the processor 1610 is configured to perform the various steps and / or processes of the above-described method embodiments corresponding to the transmitting device or the receiving device.

[0221] During implementation, each step of the above method can be completed by an integrated logic circuit of the hardware in the processor or by instructions in the form of software. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it will not be described in detail here.

[0222] It should be noted that the processor in the embodiments of the present application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above-mentioned method embodiment can be completed by hardware integrated logic circuits in the processor or by software instructions. The above-mentioned processor can be a general-purpose processor, digital signal processing (DSP), ASIC, field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. The processor in the embodiments of the present application can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of the present application can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium mature in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above-mentioned method.

[0223] It is understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0224] Optionally, the memory (eg, 1630 ) in the embodiment of the present application may be integrated into the processor (eg, 1610 ).

[0225] In addition, the present application also provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed on a computer, the operations and / or processes performed by the sending device or the receiving device in each method embodiment of the present application are executed.

[0226] The present application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the sending device or the receiving device in the various method embodiments of the present application are executed.

[0227] In addition, the present application further provides a chip, the chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is configured to execute the computer program stored in the memory, so that the operations and / or processing performed by the transmitting device or the receiving device in any method embodiment are performed.

[0228] Furthermore, the chip may further include a communication interface. The communication interface may be an input / output interface, or an interface circuit, etc. Furthermore, the chip may further include a memory.

[0229] In addition, the present application also provides a communication system, including a transmitting device and a receiving device in the embodiments of the present application.

[0230] It should also be noted that the memory described herein is intended to comprise, but not be limited to, these and any other suitable types of memory.

[0231] Those skilled in the art will appreciate that the various exemplary units and algorithmic steps described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented using hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application. Those skilled in the art will clearly understand that, for ease of description and brevity, the specific operating processes of the systems, devices, and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units described is merely a logical functional division. In actual implementation, other divisions may be used, such as multiple units or components being combined or integrated into another system, or some features being omitted or not implemented. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interface, or indirect coupling or communication connection between devices or units, which may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0232] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

[0233] It should be understood that references to "embodiments" throughout this specification mean that a particular feature, structure, or characteristic associated with the embodiment is included in at least one embodiment of the present application. Therefore, various embodiments throughout this specification do not necessarily refer to the same embodiment. Furthermore, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0234] It can also be understood that in this application, "when", "if" and "if" all mean that the network element will make corresponding processing under certain objective circumstances, which is not a time limit, and does not require the network element to have a judgment action when implementing it, nor does it mean that there are other limitations.

[0235] It is also understood that in each embodiment of the present application, "A corresponds to B" means that B is associated with A, and B can be determined based on A. However, it is also understood that determining B based on A does not mean determining B based solely on A, and B can also be determined based on A and / or other information.

Claims

1. A method of interleaving, characterized in that: include: Performing sub-block interleaving on a codeword sequence to be interleaved to obtain a first codeword sequence, wherein the codeword sequence to be interleaved and the first codeword sequence both include Y sub-blocks, the Y sub-blocks of the codeword sequence to be interleaved are determined based on a preset number of bits X included in a sub-block, and both X and Y are integers greater than 1; The bits included in at least one sub-block group among the L sub-block groups are interleaved across sub-blocks in the corresponding sub-block group to obtain a second codeword sequence, wherein the L sub-block groups are determined based on the Y sub-blocks of the first codeword sequence and the number Z of sub-blocks included in a preset sub-block group, and both Z and L are integers greater than 1.

2. The method according to claim 1, characterized in that The step of performing cross-sub-block bit interleaving on bits included in at least one of the L sub-block groups within the corresponding sub-block group comprises: Based on a first interleaving method, bits contained in a first sub-block group in the at least one sub-block group are interleaved across sub-blocks within the first sub-block group, wherein the first sub-block group includes a first sub-block and a second sub-block, and the first interleaving method is used to place a first bit contained in the first sub-block in a first position, wherein the first position is the position where a second bit contained in the second sub-block is located.

3. The method according to claim 2, characterized in that The remainder after a modulo n operation on the position number of the first bit is the same as the remainder after a modulo n operation on the position number of the second bit, where n is an integer greater than 1.

4. The method according to any one of claims 1 to 3, characterized in that The sub-block interleaving of the interleaved codeword sequence comprises: The codeword sequence to be interleaved is interleaved on a sub-block basis based on a second interleaving mode, wherein the second interleaving mode is used to interleave each of the Y sub-blocks of the codeword sequence to be interleaved. The sub-blocks are written in columns and read out in rows to complete the sub-block interleaving, the d1 is the number of written columns corresponding to the second interleaving mode, and the d1 is an integer greater than 1 and less than Y. Indicates rounding up.

5. The method according to claim 4, characterized in that The Z is equal to the d1.

6. The method according to any one of claims 1 to 3, characterized in that The sub-block interleaving of the interleaved codeword sequence comprises: Sub-block interleaving is performed on the codeword sequence to be interleaved based on a third interleaving method, wherein the third interleaving method is used to write every d2 sub-blocks of the Y sub-blocks of the codeword sequence to be interleaved by row and read them out by column to complete sub-block interleaving, and d2 is the number of write columns corresponding to the third interleaving method, and d2 is an integer greater than 1 and less than Y.

7. The method according to any one of claims 1 to 6, characterized in that The subblocks included in any subblock group among the L subblock groups are consecutive subblocks among the Y subblocks of the first codeword sequence.

8. The method according to claim 6, characterized in that The third interleaving method is also used to perform sub-block interleaving of at least one of the d2 sub-block groups within the corresponding sub-block group between row writing and column reading, wherein the d2 sub-block groups are the sub-block groups corresponding to the d2 columns of sub-blocks after row writing.

9. The method according to claim 8, characterized in that The L sub-block groups are sub-block groups obtained by reading rows after sub-block interleaving is performed in the corresponding sub-block groups.

10. The method according to claim 8 or 9, characterized in that: The Z is equal to the d2.

11. The method according to any one of claims 8 to 10, characterized in that The third interleaving method is used to perform sub-block interleaving on at least one of the d2 sub-block groups within a corresponding sub-block group, including: the third interleaving method is used to perform sub-block interleaving on at least one of the d2 sub-block groups by shifting the sub-blocks in a column direction within the corresponding sub-block group to achieve sub-block interleaving.

12. A de-interleaving method, characterized in that: include: Performing cross-sub-block de-bit interleaving in the corresponding sub-block group on the decoding information included in at least one sub-block group of the L sub-block groups to obtain a first de-interleaved sequence, wherein the L sub-block groups are determined based on the Y sub-blocks of the sequence to be de-interleaved and a preset number Z of sub-blocks included in a sub-block group, the Y sub-blocks are determined based on a preset number X of decoding information included in a sub-block, and the X, the Y, the Z and the L are all integers greater than 1; Perform de-sub-block interleaving on the first de-interleaved sequence to obtain a second de-interleaved sequence.

13. The method according to claim 12, characterized in that The step of performing cross-sub-block debit interleaving on the decoding information contained in at least one of the L sub-block groups in the corresponding sub-block group comprises: Based on a first deinterleaving method, decoding information contained in a first sub-block group of the at least one sub-block group is bit-interleaved across sub-blocks within the first sub-block group, wherein the first sub-block group includes a first sub-block and a second sub-block, and the first deinterleaving method is used to place the first decoding information contained in the second sub-block at a second position, wherein the second position is a position where the second decoding information is located in the first sub-block.

14. The method according to claim 13, characterized in that A remainder after a modulo-n operation is performed on the position number of the first decoded information is the same as a remainder after a modulo-n operation is performed on the position number of the second decoded information, where n is an integer greater than 1.

15. The method according to any one of claims 12 to 14, characterized in that The performing de-sub-block interleaving on the first de-interleaved sequence comprises: The first deinterleaving sequence is de-subblock interleaved based on a second deinterleaving method, wherein the second deinterleaving method is used to write Y subblocks of the first deinterleaving sequence in rows and read them out in columns to complete the de-subblock interleaving, the number of columns written corresponding to the second deinterleaving method is d1, and the number of subblocks written in each row is determined based on the interleaving method performed modulo the columns of d1, and d1 is an integer greater than 1 and less than Y.

16. The method according to claim 15, characterized in that The Z is equal to the d1.

17. The method according to any one of claims 12 to 14, characterized in that The performing de-sub-block interleaving on the first de-interleaved sequence comprises: The first deinterleaved sequence is de-subblock interleaved based on a third deinterleaving method, wherein the third deinterleaving method is used to write Y subblocks of the first deinterleaved sequence by column and read them out by row to complete the de-subblock interleaving, the number of columns written corresponding to the third deinterleaving method is d2, and the number of subblocks written in each column is determined based on the interleaving method of the row column modulo the d2, and the d2 is an integer greater than 1 and less than Y.

18. The method according to any one of claims 12 to 17, characterized in that The sub-blocks included in any sub-block group among the L sub-block groups are continuous sub-blocks among the Y sub-blocks of the sequence to be deinterleaved.

19. The method according to claim 17, characterized in that The third deinterleaving method is also used to desubblock interleave at least one of the d2 subblock groups within the corresponding subblock group between column-based writing and row-based reading, wherein the d2 subblock groups are the subblock groups corresponding to the d2 column subblocks after column-based writing.

20. The method according to claim 19, characterized in that The L sub-block groups are sub-block groups obtained by reading rows before de-sub-block interleaving is performed in the corresponding sub-block groups.

21. The method according to claim 19 or 20, characterized in that The Z is equal to the d2.

22. The method according to any one of claims 19 to 21, characterized in that The third de-interleaving method is used to perform de-sub-block interleaving on at least one of the d2 sub-block groups within the corresponding sub-block group, including: the third de-interleaving method is used to perform de-sub-block interleaving on at least one of the d2 sub-block groups by shifting the sub-blocks in the column direction within the corresponding sub-block group.

23. A method of interleaving, characterized in that include: Performing cross-subblock bit interleaving on bits included in at least one subblock group among the L subblock groups in the corresponding subblock group to obtain a third codeword sequence, wherein the L subblock groups are determined based on Y subblocks of the to-be-interleaved codeword sequence and a preset number Z of subblocks included in a subblock group, the Y subblocks are determined based on a preset number X of bits included in a subblock, and X, Y, Z, and L are all integers greater than 1; Sub-block interleaving is performed on the Y sub-blocks of the third codeword sequence to obtain a fourth codeword sequence.

24. The method according to claim 23, characterized in that The step of performing cross-sub-block bit interleaving on bits included in at least one of the L sub-block groups within the corresponding sub-block group comprises: Based on a first interleaving method, bits contained in a first sub-block group in the at least one sub-block group are interleaved across sub-blocks within the first sub-block group, wherein the first sub-block group includes a first sub-block and a second sub-block, and the first interleaving method is used to place a first bit contained in the first sub-block in a first position, wherein the first position is the position where a second bit contained in the second sub-block is located.

25. The method according to claim 24, characterized in that The remainder after a modulo n operation on the position number of the first bit is the same as the remainder after a modulo n operation on the position number of the second bit, where n is an integer greater than 1.

26. The method according to any one of claims 23 to 25, characterized in that The performing sub-block interleaving on the Y sub-blocks of the third codeword sequence includes: Sub-block interleaving is performed on the Y sub-blocks of the third codeword sequence based on a third interleaving method, wherein the third interleaving method is used to write every d2 sub-blocks of the Y sub-blocks of the third codeword sequence by row and read them out by column to complete sub-block interleaving, and d2 is the number of write columns corresponding to the third interleaving method, and d2 is an integer greater than 1 and less than Y.

27. The method according to claim 26, characterized in that The Z is equal to the d2.

28. The method according to any one of claims 23 to 25, characterized in that The performing sub-block interleaving on the Y sub-blocks of the third codeword sequence includes: The Y sub-blocks of the third codeword sequence are interleaved based on a second interleaving mode, wherein the second interleaving mode is used to interleave each of the Y sub-blocks of the third codeword sequence. The sub-blocks are written in columns and read out in rows to complete the sub-block interleaving, wherein d1 is the number of written columns corresponding to the second interleaving mode, and d1 is an integer greater than 1 and less than Y. Indicates rounding up.

29. The method according to any one of claims 23 to 28, characterized in that The sub-blocks included in any sub-block group among the L sub-block groups are consecutive sub-blocks among the Y sub-blocks of the to-be-interleaved codeword sequence.

30. A de-interleaving method, characterized in that: include: Performing sub-block deinterleaving on a sequence to be deinterleaved to obtain a third deinterleaved sequence, wherein both the sequence to be deinterleaved and the third deinterleaved sequence include Y sub-blocks, and the Y sub-blocks of the sequence to be deinterleaved are determined based on a preset number X of decoding information contained in one sub-block, and both X and Y are integers greater than 1; De-bit interleaving is performed across sub-blocks in the corresponding sub-block group on the decoding information included in at least one sub-block group among the L sub-block groups to obtain a fourth de-interleaved sequence, wherein the L sub-block groups are determined based on the Y sub-blocks of the third de-interleaved sequence and a preset number Z of sub-blocks included in a sub-block group, the Y sub-blocks are determined based on a preset number X of decoding information included in a sub-block, and both Z and L are integers greater than 1.

31. The method according to claim 30, characterized in that The step of performing cross-sub-block debit interleaving on the decoding information contained in at least one of the L sub-block groups in the corresponding sub-block group comprises: Based on a first deinterleaving method, the decoding information contained in a first sub-block group of the at least one sub-block group is debit-interleaved across sub-blocks within the first sub-block group, wherein the first sub-block group includes a first sub-block and a second sub-block, and the first deinterleaving method is used to place the first decoding information contained in the second sub-block at a second position, wherein the second position is a position where the second decoding information is located in the first sub-block.

32. The method according to claim 31, characterized in that A remainder after a modulo-n operation is performed on the position number of the first decoded information is the same as a remainder after a modulo-n operation is performed on the position number of the second decoded information, where n is an integer greater than 1.

33. The method according to any one of claims 30 to 32, characterized in that The deblock interleaving of the sequence to be deinterleaved comprises: The de-sub-block interleaving is performed on the sequence to be de-interleaved based on a third de-interleaving method, wherein the third de-interleaving method is used to write the Y sub-blocks of the sequence to be de-interleaved by columns and read them out by rows to complete the de-sub-block interleaving, the number of columns written corresponding to the third de-interleaving method is d2, and the number of sub-blocks written in each column is determined based on the interleaving method of the row column modulo the d2.

34. The method according to claim 33, characterized in that The Z is equal to the d2.

35. The method according to any one of claims 30 to 32, characterized in that The deblock interleaving of the sequence to be deinterleaved comprises: The de-sub-block interleaving is performed on the sequence to be de-interleaved based on a second de-interleaving method, wherein the second de-interleaving method is used to write Y sub-blocks of the sequence to be de-interleaved by rows and read them out by columns to complete the de-sub-block interleaving, wherein the number of columns written corresponding to the second de-interleaving method is d1, and the number of sub-blocks written in each row is determined based on the interleaving method performed modulo the columns of d1, and d1 is an integer greater than 1 and less than Y.

36. The method according to any one of claims 30 to 35, characterized in that The sub-blocks included in any sub-block group among the L sub-block groups are consecutive sub-blocks among the Y sub-blocks of the third deinterleaved sequence.

37. A communication device, characterized in that: include: A processor for executing computer programs or instructions stored in a memory, The memory is used to store the computer program or the instruction. When the computer program or the instructions are executed, the method according to any one of claims 1 to 11 is executed, or the method according to any one of claims 12 to 22 is executed, or the method according to any one of claims 23 to 29 is executed, or the method according to any one of claims 30 to 36 is executed.

38. A computer program product, characterized in that The computer program product comprises instructions for executing the method as claimed in any one of claims 1 to 11, or the computer program product comprises instructions for executing the method as claimed in any one of claims 12 to 22, or the computer program product comprises instructions for executing the method as claimed in any one of claims 23 to 29, or the computer program product comprises instructions for executing the method as claimed in any one of claims 30 to 36.

39. A computer-readable storage medium, characterized in that: include: The computer-readable storage medium stores a computer program or instructions; when the computer program or the instructions are executed on a computer, the method as claimed in any one of claims 1 to 11 is executed, or the method as claimed in any one of claims 12 to 22 is executed, or the method as claimed in any one of claims 23 to 29 is executed, or the method as claimed in any one of claims 30 to 36 is executed.

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