Rate adjusting method and node

Abstract

Provided in the embodiments of the present disclosure are a rate adjusting method and a node. The method comprises: acquiring a target code stream in the 256B / 257B format; and adding or deleting a 257b idle code block to adjust the rate of the target code stream.

Description

A rate adjustment method and node

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The present disclosure is based on Chinese patent application CN202410009215.3 filed on January 3, 2024, entitled “A Rate Adjustment Method and Node”, and claims the priority of the patent application, and all the disclosed contents are incorporated into the present disclosure by reference. Technical Field

[0003] The present disclosure relates to the field of communications, and in particular to a rate adjustment method and node. Background Art

[0004] In the Institute of Electrical and Electronics Engineers (IEEE) 802.3 standard, high-speed services are rate-adapted based on 66b. Each Media Access Control (MAC) packet is encoded in a 64B / 66B format, including a start code block (S) and a stop code block (T). A MAC packet encoded as 64B / 66B begins with an S code block and ends with a T code block. Because there is an average of 12 bytes of inter-packet gap (IPG) between MAC packets, some IPGs are encoded as 66b idle code blocks. IEEE 802.3 currently performs rate adaptation based on adding or removing 66b idle code blocks. For example, removing 66b idle code blocks reserves space for alignment markers (AM) or Flexible Ethernet (FlexE) overhead, thereby ensuring that the overall rate remains unchanged.

[0005] The industry has also defined different service layers to carry Ethernet services, such as FlexE and Optical Transport Network (OTN). The service layer's rate is higher than that of Ethernet services. The mapping of Ethernet services to corresponding service layer containers also uses 66b idle packets for speed regulation. Because service layer containers have a high rate, when there are insufficient Ethernet services, 66b idle packets are inserted into the service layer containers.

[0006] As the rate increases, the bus width processed within the device also becomes larger. There will be more 66b data in one bus width, and the implementation of the rate adaptation mechanism based on 66b idle code blocks will become more and more complicated. This is because the 66b idle code block will appear in any of the multiple 66b data in the bus width, which will introduce complex data splicing problems.

[0007] In summary, there is no good solution to the problem in the related art that as the rate increases, the implementation complexity of the rate adaptation mechanism of high-speed Ethernet is high.

[0008] Summary of the Invention

[0009] The embodiments of the present disclosure provide a rate adjustment method and node to at least solve the problem in the related art that as the rate increases, the implementation complexity of the rate adaptation mechanism of high-speed Ethernet is high.

[0010] According to an embodiment of the present disclosure, a rate adjustment method is provided, which includes: acquiring a target code stream in a 256B / 257B format; and adjusting the rate of the target code stream by adding or deleting 257b idle code blocks.

[0011] According to another embodiment of the present disclosure, a node is provided, comprising: an acquisition module for acquiring a target code stream in a 256B / 257B format; and a rate adjustment module for adjusting the rate of the target code stream by adding or deleting 257b idle code blocks.

[0012] According to another embodiment of the present disclosure, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above method embodiments are executed.

[0013] According to another embodiment of the present disclosure, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any one of the above method embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG1 is a block diagram of a hardware structure for executing a rate adjustment method according to an embodiment of the present disclosure;

[0015] FIG2 is a flow chart of a rate adjustment method according to an embodiment of the present disclosure;

[0016] FIG3 is a processing flow chart of a source node according to an embodiment of the present disclosure;

[0017] FIG4 is a schematic diagram of a 257b idle code block according to an embodiment of the present disclosure;

[0018] FIG5 is a schematic diagram of a 257b termination code block according to an embodiment of the present disclosure;

[0019] FIG6 is a processing flow chart (I) of an intermediate node according to an embodiment of the present disclosure;

[0020] FIG7 is a processing flow chart (II) of an intermediate node according to an embodiment of the present disclosure;

[0021] FIG8 is a processing flow chart (III) of an intermediate node according to an embodiment of the present disclosure;

[0022] FIG9 is a schematic diagram of a 257b error code block according to an embodiment of the present disclosure;

[0023] FIG10 is a block diagram of a node in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and in conjunction with embodiments.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0026] The method embodiments provided in the embodiments of the present disclosure can be executed in a network node of a high-speed Ethernet, such as a host node (including a computer device, a server, etc.), a switch node, a router node or a gateway node, etc. Taking operation on a computer device as an example, FIG1 is a hardware structure block diagram for executing the rate adjustment method in the embodiment of the present disclosure. As shown in FIG1 , the hardware board may include one or more (only one is shown in FIG1 ) processors 12 (the processor 12 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device) and a memory 14 for storing data, wherein the above-mentioned mobile terminal may also include a transmission device 16 and an input and output device 18 for communication functions. It can be understood by those skilled in the art that the structure shown in FIG1 is only for illustration and does not limit the structure of the above-mentioned computer device. For example, the computer device may also include more or fewer components than those shown in FIG1 , or have a configuration different from that shown in FIG1 .

[0027] The memory 14 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the rate adjustment method in the embodiment of the present disclosure. The processor 12 executes various functional applications and the rate adjustment method by running the computer program stored in the memory 14, that is, implements the above-mentioned method. The memory 14 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 14 may further include a memory remotely located relative to the processor 12, and these remote memories can be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0028] The transmission device 16 is used to receive or send data via a network. Specific examples of the aforementioned network may include a wireless network provided by a communications provider. In one embodiment, the transmission device 16 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 16 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0029] In one embodiment of the present disclosure, a rate adjustment method is provided. FIG2 is a flow chart of the rate adjustment method according to the embodiment of the present disclosure. As shown in FIG2 , the flow chart includes the following steps:

[0030] Step S202, obtaining a target bitstream in 256B / 257B format;

[0031] Step S204: rate-adjust the target code stream by adding or deleting 257b idle code blocks.

[0032] In the embodiment of the present disclosure, through steps S202 and S204, rate adaptation can be performed based on the 257b code stream, reducing the hardware implementation complexity of rate adaptation under the high-speed interface, and can solve the problem of high implementation complexity of the rate adaptation mechanism of high-speed Ethernet as the rate increases in related technologies, thereby better supporting the development of higher-speed Ethernet technology.

[0033] In some embodiments, step S204 performs rate adjustment on the target code stream by adding or deleting 257b idle code blocks, including: inserting the 257b idle code block after the 257b termination code block or the 257b idle code block in the target code stream; or deleting the 257b idle code block from the target code stream.

[0034] In this embodiment, using 257b idle blocks as the basic unit for adjusting the bitstream rate can reduce the complexity of the rate adaptation mechanism in hardware implementation. Deleting 257b idle blocks in the target bitstream can increase the bitstream rate, while adding new 257b idle blocks in the target bitstream can decrease the bitstream rate.

[0035] In some embodiments, the target code stream in 256B / 257B format is composed of multiple 257b coding blocks, and each 257b coding block is formed by performing 256B / 257B transcoding on four 66b coding blocks.

[0036] In some embodiments, the 257b idle code block (I) is formed by transcoding 4 66b idle code blocks; the 257b termination code block is formed by transcoding a first number of 66b data code blocks (D), 1 66b termination code block (T) and a second number of 66b idle code blocks (I), wherein the first number and the second number are greater than or equal to zero, and the sum of the first number and the second number is equal to 3.

[0037] In an exemplary embodiment, each 257b code block may be represented by symbols of four 66b code blocks, wherein the combinations of the four 66b code blocks in the 257b termination code block include: TIII, DTII, DDTI, and DDDT.

[0038] In some embodiments, before rate adjusting the target code stream by adding or deleting 257b idle code blocks in step S204, the method further includes: identifying 257b idle code blocks in the target code stream by using a first pattern.

[0039] Exemplarily, the first mode includes: the first bit is 0, the second to fifth bits are 0000, and a first preset pattern; the first preset pattern includes at least one of the following: the sixth to ninth bits are 0111, the tenth to 65th bits are all 0; the sixth to 13th bits are 01110000.

[0040] In some embodiments, before adjusting the rate of the target code stream by adding or deleting 257b idle code blocks in step S204, the method further includes: identifying a 257b termination code block in the target code stream by using a second pattern.

[0041] Exemplarily, the second mode includes at least one of the following:

[0042] The first bit is 0, the second to fifth bits are 0000, and the sixth to ninth bits are the preset type;

[0043] The first bit is 0, and the second to fifth bits are 1000 or 1110;

[0044] The first bit is 0, the second to fifth bits are 1100, and the 202nd to 257th bits are all 0.

[0045] In some embodiments, the 257b code block further includes: a 257b start code block, wherein the 257b start code block is formed by transcoding one 66b start code block and three 66b data code blocks. Exemplarily, the 257b start code block can be represented as SDDD.

[0046] In some embodiments, the 257b encoding block also includes: a 257b connection code block, wherein the 257b connection code block is formed by transcoding a 66b termination code block, a 66b start code block and two 66b data code blocks, and the 66b termination code block is located before the 66b start code block.

[0047] In some embodiments, the 257b concatenated code block is formed by transcoding any combination of the following:

[0048] The 66b data code block, the 66b data code block, the 66b termination code block and the 66b start code block;

[0049] The 66b data code block, the 66b termination code block, the 66b start code block and the 66b data code block;

[0050] The 66b termination code block, the 66b start code block, the 66b data code block and the 66b data code block.

[0051] In an exemplary embodiment, the 257b connection code block can be expressed as DDTS, DTSD or TSDD. The 257b connection code block is used to connect two data packets. The T code block in the 257b connection code block is the tail of the previous data packet, and the S code block is the head of the next data packet.

[0052] In some embodiments, step S202, obtaining a target bitstream in a 256B / 257B format, includes: performing 64B / 66B encoding on an Ethernet MAC packet to obtain a first bitstream in a 64B / 66B format, and performing 256B / 257B transcoding on the first bitstream to obtain the target bitstream;

[0053] In other embodiments, step S202, obtaining a target code stream in 256B / 257B format, includes: receiving the target code stream sent by a previous node, wherein the target code stream is formed by performing 64B / 66B encoding and 256B / 257B transcoding on the Ethernet MAC packet.

[0054] In some embodiments, when the Ethernet MAC packet is 64B / 66B encoded, the interframe spacing bytes in the Ethernet MAC packet are not encoded as 66b idle code blocks, the first code stream includes a 66b start code block, a 66b data code block and a 66b end code block, and the first code stream does not include a 66b idle code block.

[0055] In this embodiment, each Ethernet MAC packet can be transcoded into a group of 66b code blocks. Each group of 66b code blocks consists of a 66b start code block (S), several 66b data code blocks (D), and a 66b termination code block (T). 66b idle code blocks (I) are not included.

[0056] For example, in the process of performing 64B / 66B encoding on the Ethernet MAC packet, eight consecutive Inter Packet Gap (IPG) bytes will not be encoded into a 66b idle code block.

[0057] In some embodiments, performing 256B / 257B transcoding on the first code stream to obtain the target code stream includes: transcoding a 66b end code block of a current MAC packet and a 66b start code block of a next MAC packet in the first code stream into a 257b connection code block, wherein the 257b connection code block does not include a 66b idle code block.

[0058] In some embodiments, performing 256B / 257B transcoding on the first code stream to obtain the target code stream includes: when the number of remaining 66b coding blocks in the current MAC packet in the first code stream is less than 4 and the next Ethernet MAC packet has not been received, inserting at least one 66b idle code block into the 66b termination code block corresponding to the current MAC packet, performing 256B / 257B transcoding to obtain a 257b termination code block in the target code stream.

[0059] In some embodiments, when the number of remaining 66b coding blocks of the current MAC packet in the first code stream is less than 4 and the next Ethernet MAC packet is received, a 257b connection code block is used to connect the two Ethernet MAC packets. The 257b connection code block can be formed by transcoding the remaining 66b coding block of the current MAC packet and the 66b coding block in the header of the next MAC packet.

[0060] In some embodiments, performing 256B / 257B transcoding on the first code stream to obtain the target code stream further includes: inserting a 257b idle code block into the target code stream if the next Ethernet MAC packet is not received within a preset first threshold after the transcoding of the current MAC packet is completed, wherein the 257b idle code block is formed by transcoding four 66b idle code blocks.

[0061] In an exemplary embodiment, the first threshold may be set based on the time required to send four 66b coded blocks.

[0062] In some embodiments, receiving the target code stream sent by the previous node includes: receiving a data stream sent by the previous node obtained by performing forward error correction encoding (FEC) on the target code stream; performing forward error correction decoding on the data stream to obtain the target code stream; and in the event of an FEC uncorrectable error, replacing all 257b code blocks in the corresponding FEC codeword in the target code stream with 257b error code blocks.

[0063] In some embodiments, the FEC codeword is 255 bytes long and consists of 239 bytes of normal data and 16 bytes of redundant overhead. If decoding of a FEC codeword fails, all 257b coded blocks in the FEC codeword need to be replaced with 257b error code blocks.

[0064] In some embodiments, the 257b error code block is formed by transcoding four 66b error code blocks.

[0065] In some embodiments, the 257b error code block can be identified by a preset third pattern. Exemplarily, the third pattern includes the first bit being 0, the second to fifth bits being 0000, and a second preset pattern; wherein the second preset pattern includes at least one of the following: the sixth to ninth bits are 0111, the tenth to 65th bits are 8 0111100; and the sixth to 13th bits are 01110111.

[0066] In some embodiments, when the current node is an intermediate node that supports 257b code block exchange, step S204 rate-adjusts the target code stream by adding or deleting 257b idle code blocks, including: performing a 257b code block-based exchange process on the target code stream to obtain a target code stream after the exchange process; and rate-adjusting the target code stream after the exchange process by adding or deleting the 257b idle code blocks.

[0067] In some embodiments, when the current node is an intermediate node that supports 66b code block exchange, step S204 rate-adjusts the target code stream by adding or deleting 257b idle code blocks, including: transcoding the target code stream to obtain a second code stream in 64B / 66B format, wherein the second code stream includes 66b idle code blocks; performing a 66b code block-based exchange process on the second code stream to obtain a second code stream after exchange; rate-adjusting the second code stream after exchange by adding or deleting the 66b idle code blocks to obtain a rate-adjusted second code stream; performing 256B / 257B transcoding on the rate-adjusted second code stream, and shifting, adding, or deleting the 66b idle code blocks in the rate-adjusted second code stream during the transcoding process to obtain a rate-adjusted target code stream in 256B / 257B format, wherein the 257b code blocks in the rate-adjusted target code stream are of the same type as the 257b code blocks in the target code stream.

[0068] In some embodiments, when the current node is an intermediate node that supports 66b code block exchange, step S204 rate-adjusts the target bitstream by adding or deleting 257b idle code blocks, including: deleting some 257b idle code blocks in the target bitstream according to a preset proportional coefficient to obtain a reduced-speed target bitstream; transcoding the reduced-speed target bitstream to obtain a second bitstream in 64B / 66B format, wherein the second bitstream includes 66b idle code blocks; performing a 66b code block-based exchange process on the second bitstream to obtain a second bitstream after exchange; performing 256B / 257B transcoding on the second bitstream after exchange to obtain a target bitstream after exchange; and rate-adjusting the target bitstream after exchange by adding or deleting the 257b idle code blocks.

[0069] Through the embodiments of the present disclosure, a rate adaptation mechanism based on a 257b code stream can be implemented, reducing the hardware implementation complexity of rate adaptation under a high-speed interface, thereby solving the problem in related technologies of high-speed Ethernet rate adaptation mechanism implementation complexity as the rate increases, and better supporting the development of high-speed Ethernet technology.

[0070] FIG3 is a processing flow chart of a source node according to an embodiment of the present disclosure. As shown in FIG3 , at the source node, the Ethernet MAC packet may be encoded into a 64B / 66B format and then transcoded into a 256B / 257B format.

[0071] In this embodiment, each Ethernet MAC packet is encoded into a 64B / 66B format consisting of a 66b start code block (S), multiple 66b data code blocks (D), and a 66b termination code block (T). The 64B / 66B code stream after the Ethernet MAC packet is encoded does not contain 66b idle code blocks. That is, during the encoding process, eight consecutive IPG bytes are not encoded as a 66b idle code block.

[0072] In this embodiment, when performing 256B / 257B transcoding, four 66b code blocks are transcoded to form one 257b code block.

[0073] In some embodiments, when performing 64B / 66B to 256B / 257B transcoding, if the number N1 of 66b code blocks remaining in the current MAC packet encoded as a 64B / 66B code block is insufficient for transcoding to 257b, and upon receiving the next MAC packet, the remaining 66b code blocks in the current MAC packet are transcoded together with M1 66b code blocks encoded in the next MAC packet into a 257b code block, where N1 + M1 = 4. For example, if one 66b termination code block (T) remains after the 256B / 257B transcoding of the 66b code block encoded in the current MAC packet, and upon receiving the next MAC packet, the remaining T code block in the current MAC packet and three 66b code blocks corresponding to the next MAC packet, i.e., one S code block and two D code blocks, are transcoded into one 257b code block. That is, when the T code block of the current MAC packet and the S code block of the next MAC packet are transcoded into a 257b code block, the four 66b code blocks transcoded into the 257b code block do not include a 66b idle code block.

[0074] In other embodiments, when the number N2 of remaining 66b code blocks in a MAC packet encoded as 64B / 66B code blocks is insufficient for transcoding to 257b code blocks and the next MAC packet has not been received, a certain number M2 of 66b idle code blocks are inserted after the T code block corresponding to the MAC packet, and these blocks are transcoded together with the remaining 66b code blocks into 257b code blocks, where the sum of the number M2 of inserted 66b idle code blocks and the number N2 of remaining 66b code blocks in the current MAC packet is 4. For example, when the 66b code blocks encoded in the current MAC packet are transcoded to 256B / 257B, two 66b code blocks, D and T, remain, where D is a data code block and T is a termination code block, and the next MAC packet has not been received, two 66b idle code blocks are inserted after the T code block corresponding to the MAC packet, and these blocks are transcoded together with the remaining D and T code blocks in the current MAC packet into a single 257b code block.

[0075] In some embodiments, after the current MAC packet is transcoded into 257B, if the next MAC packet is not received within a first threshold, four 66b idle code blocks are inserted and transcoded into one 257b idle code block. The first threshold is a fixed value. For example, the first threshold can be the transmission time corresponding to four 66b code blocks.

[0076] Through the embodiments of the present disclosure, it is possible to convert MAC packets into 256B / 257B format, laying the foundation for subsequent nodes to adjust the rate based on 257b idle code blocks to support the development of higher-speed Ethernet technology.

[0077] In some embodiments, the transcoded 257b code block includes at least one of the following types:

[0078] 257b start code block, formed by transcoding a 66b start code block (S) and three 66b data code blocks (D);

[0079] A 257b termination code block, consisting of a first number a1 of 66b data code blocks (D), one 66b termination code block (T), and a second number a2 of 66b idle code blocks (I), where a1≥0, a2≥0, and a1+a2=3;

[0080] 257-bit idle code block, formed by transcoding four 66-bit idle code blocks;

[0081] 257b data code block, formed by transcoding four 66b data code blocks;

[0082] 257b error code block, formed by transcoding four 66b error code blocks (error);

[0083] 257b ordered code block, formed by transcoding four 66b ordered code blocks (O);

[0084] The 257b connection code block is formed by transcoding a 66b termination code block (T), a 66b start code block (S) and two 66b data code blocks (D), wherein the 66b termination code block (T) is located before the 66b start code block (S).

[0085] In this embodiment, when a 257b idle code block is inserted into a data stream transcoded into 257b for rate adjustment, the 257b idle code block is inserted after the 257b termination code block or after the 257b idle code block.

[0086] FIG4 is a schematic diagram of a 257b idle code block according to an embodiment of the present disclosure. As shown in FIG4 , the 257b idle code block is formed by transcoding four 66b idle code blocks and is identified by a first mode.

[0087] In this embodiment, the first mode is 257b, wherein the first bit is 0, the 2nd to 5th bits are 0000, and a first fixed pattern; the first fixed pattern is at least one of the following: the 6th to 9th bits are 0111 (the reverse order of 0xE), the 10th to 65th bits are all 0; the 6th to 13th bits are 01110000 (the reverse order of 0x1E).

[0088] FIG5 is a schematic diagram of a 257b termination code block according to an embodiment of the present disclosure. As shown in FIG5 , there are four types of 257b termination code blocks.

[0089] In this embodiment, a 257b termination code block is composed of a first number a1 of 66b data code blocks, one 66b termination code block, and a second number a2 of 66b idle code blocks, where a1 ≥ 0, a2 ≥ 0, a1 + a2 = 3, and the 66b termination code block can be located at any position in the 257b code block, and is located after the 66b data code block and before the 66b idle code block.

[0090] In this embodiment, the combination of the four 66b code blocks in the 257b termination code block includes: TIII, DTII, DDTI, and DDDT.

[0091] In this embodiment, the 257b termination code block is identified by a second mode, where the first bit of 257B is 0, the second to fifth bits are 0000, and the sixth to ninth bits are a fixed type.

[0092] In some embodiments, the fixed Type includes any one of the following: 1001 (reverse of 0x9), 0101 (reverse of 0xA), 0010 (reverse of 0x4), 0011 (reverse of 0xC), 0100 (reverse of 0x2), 1000 (reverse of 0x1), 1111 (reverse of 0xF).

[0093] In some embodiments, the first bit of the second pattern 257b is 0, and the 2nd to 5th bits are 1000 or 1110; or the first bit of the second pattern 257b is 0, the 2nd to 5th bits are 1100, and the 202nd to 257th bits are all 0.

[0094] FIG6 is a processing flow chart (I) of an intermediate node according to an embodiment of the present disclosure. As shown in FIG6 , the process includes the following steps:

[0095] Step S602: receiving a 257b-based code stream from an upstream source;

[0096] Step S604, performing exchange processing based on 257b code blocks;

[0097] Step S606, performing rate adaptation based on 257b code blocks;

[0098] Step S608: Send the 257b-based code stream downstream.

[0099] This embodiment is applied to the scenario where the intermediate node supports 257b code block exchange. The intermediate node receives a 257b data stream from the upstream and performs 257b code block exchange. After the 257b code block exchange, the rate adaptation is performed by inserting a 257b code block after the 257b termination code block or after the 257b idle code block or removing the 257b idle code block in the 257b code stream. The 257b termination code block is identified by the second mode, and the 257b idle code block is identified by the first mode.

[0100] Through the embodiments of the present disclosure, the hardware implementation complexity of rate adaptation under high-speed interfaces can be reduced, and the problem of high implementation complexity of the rate adaptation mechanism of high-speed Ethernet as the rate increases in related technologies can be solved, thereby better supporting the development of higher-speed Ethernet technology.

[0101] FIG7 is a processing flow chart (II) of an intermediate node according to an embodiment of the present disclosure. As shown in FIG7 , the process includes the following steps:

[0102] Step S701, receiving a 257b-based code stream from an upstream;

[0103] Step S702, deleting 257b idle code blocks at a fixed ratio;

[0104] Step S703, 256B / 257B to 64B / 66B;

[0105] Step S704, performing exchange processing based on the 66b code block;

[0106] Step S705, 64B / 66B to 256B / 257B;

[0107] Step S706, performing rate adaptation based on 257b code blocks;

[0108] Step S707: Send the 257b-based code stream downstream.

[0109] This embodiment is applied to scenarios where intermediate nodes support 66b block-based switching. The intermediate node receives a 257B data stream from an upstream node and deletes idle 257B blocks from the data stream at a fixed ratio, i.e., one idle 257B block is deleted for every M 257B blocks. The fixed ratio is a statistical ratio, meaning that over a period of time, one idle block is deleted for every M 257B blocks after statistical calculation. This deleting of 257B idle blocks achieves data stream downscaling. The 257B blocks are then transcoded into 66b blocks, which are then switched based on 66b blocks. After the 66b block switching, these blocks are transcoded into 257b blocks. Rate adaptation is then performed by inserting 257b blocks after the 257b termination block or after the 257b idle blocks, or by removing 257b idle blocks from the 257B stream. The 257b termination block is identified using the second pattern, while the 257b idle blocks are identified using the first pattern.

[0110] FIG8 is a processing flow chart (III) of an intermediate node according to an embodiment of the present disclosure. As shown in FIG8 , the process includes the following steps:

[0111] Step S801, receiving a 257b-based code stream from an upstream;

[0112] Step S802, 256B / 257B to 64B / 66B;

[0113] Step S803, performing exchange processing based on 66b code blocks;

[0114] Step S804, performing rate adaptation based on 66b code blocks;

[0115] Step S805, 64B / 66B to 256B / 257B;

[0116] Step S806: Send the 257b-based code stream downstream.

[0117] This embodiment is applied to a scenario where an intermediate node supports 66b code block exchange. A 257b data stream is received from an upstream node, and the 257b code blocks are transcoded into 66b code blocks. 66b code block exchange is performed, and rate adaptation is performed after the 66b code block exchange, and the blocks are transcoded into 257b code blocks. During the 66b to 257b transcoding process, adjustment processing is performed on the 66b idle code blocks so that the type of the transcoded 257b code blocks is consistent with the type of the 257b code blocks transcoded by the source node. The adjustment processing includes one of the following: shifting, adding, and deleting.

[0118] FIG9 is a schematic diagram of a 257b error code block according to an embodiment of the present disclosure. As shown in FIG9 , the 257b error code block is formed by transcoding four 66b error code blocks.

[0119] In this embodiment, at the receiving side of any node, it is necessary to perform forward error correction (FEC) decoding processing on the 257b code block data stream. During the FEC decoding process, there may be too many bit errors, resulting in the inability of FEC to completely correct them. In this case, all 257b bits contained in the FEC codeword are marked as errors. The error marking is to replace the 257b code block with a 257b error code block.

[0120] In this embodiment, a 257b error code block is formed by transcoding four 66b error code blocks (error) and is identified by a third pattern. Exemplarily, the third pattern is that the first bit of 257b is 0, the second to fifth bits are 0000, and a second fixed pattern; the second fixed pattern is at least one of the following: the sixth to ninth bits are 0111 (the reverse order of 0xE), the tenth to 65th bits are eight 0111100 (the reverse order of 0011110), that is, 0111100 0111100 0111100 0111100 0111100 0111100 0111100 0111100; the sixth to 13th bits are 01110111 (the reverse order of 0x1E).

[0121] Another embodiment of the present disclosure provides a node for use in Ethernet, particularly high-speed Ethernet, to better support the development of higher-speed Ethernet technology.

[0122] FIG10 is a block diagram of a node in an embodiment of the present disclosure. As shown in FIG10 , the node includes:

[0123] An acquisition module 102 is configured to acquire a target bitstream in a 256B / 257B format;

[0124] The rate adjustment module 104 is configured to adjust the rate of the target code stream by adding or deleting 257b idle code blocks.

[0125] In some embodiments, the rate adjustment module 104 includes an insertion module and a deletion module; the insertion module is used to insert the 257b idle code block after the 257b termination code block or the 257b idle code block in the target code stream; the deletion module is used to delete the 257b idle code block from the target code stream.

[0126] In this embodiment, using 257b idle blocks as the basic unit for adjusting the bitstream rate can reduce the complexity of the rate adaptation mechanism in hardware implementation. Deleting 257b idle blocks in the target bitstream can increase the bitstream rate, while adding new 257b idle blocks in the target bitstream can decrease the bitstream rate.

[0127] In some embodiments, the target code stream in 256B / 257B format is composed of multiple 257b coding blocks, and each 257b coding block is formed by performing 256B / 257B transcoding on four 66b coding blocks.

[0128] In some embodiments, the 257b idle code block (I) is formed by transcoding 4 66b idle code blocks; the 257b termination code block is formed by transcoding a first number of 66b data code blocks (D), 1 66b termination code block (T) and a second number of 66b idle code blocks (I), wherein the first number and the second number are greater than or equal to zero, and the sum of the first number and the second number is equal to 3.

[0129] In an exemplary embodiment, each 257b code block may be represented by symbols of four 66b code blocks, wherein the combinations of the four 66b code blocks in the 257b termination code block include: TIII, DTII, DDTI, and DDDT.

[0130] In some embodiments, the node further includes: an identification module configured to identify 257b idle code blocks in the target code stream using a first pattern before rate adjustment is performed on the target code stream by adding or deleting 257b idle code blocks.

[0131] Exemplarily, the first mode includes: the first bit is 0, the second to fifth bits are 0000, and a first preset pattern; the first preset pattern includes at least one of the following: the sixth to ninth bits are 0111, the tenth to 65th bits are all 0; the sixth to 13th bits are 01110000.

[0132] In some embodiments, the identification module is further configured to identify a 257b termination code block in the target code stream using a second mode before rate adjusting the target code stream by adding or deleting 257b idle code blocks.

[0133] Exemplarily, the second mode includes at least one of the following:

[0134] The first bit is 0, the second to fifth bits are 0000, and the sixth to ninth bits are the preset type;

[0135] The first bit is 0, and the second to fifth bits are 1000 or 1110;

[0136] The first bit is 0, the second to fifth bits are 1100, and the 202nd to 257th bits are all 0.

[0137] In some embodiments, the 257b code block further includes: a 257b start code block, wherein the 257b start code block is formed by transcoding one 66b start code block and three 66b data code blocks. Exemplarily, the 257b start code block can be represented as SDDD.

[0138] In some embodiments, the 257b encoding block also includes: a 257b connection code block, wherein the 257b connection code block is formed by transcoding a 66b termination code block, a 66b start code block and two 66b data code blocks, and the 66b termination code block is located before the 66b start code block.

[0139] In some embodiments, the 257b concatenated code block is formed by transcoding any combination of the following:

[0140] The 66b data code block, the 66b data code block, the 66b termination code block and the 66b start code block;

[0141] The 66b data code block, the 66b termination code block, the 66b start code block and the 66b data code block;

[0142] The 66b termination code block, the 66b start code block, the 66b data code block and the 66b data code block.

[0143] In an exemplary embodiment, the 257b connection code block can be expressed as DDTS, DTSD or TSDD. The 257b connection code block is used to connect two data packets. The T code block in the 257b connection code block is the tail of the previous data packet, and the S code block is the head of the next data packet.

[0144] In some embodiments, the acquisition module 102 includes a forwarding module and a receiving module; a transcoding module, configured to perform 64B / 66B encoding on the Ethernet MAC packet to obtain a first code stream in 64B / 66B format, and perform 256B / 257B transcoding on the first code stream to obtain the target code stream; and a receiving module, configured to receive the target code stream sent by the previous node, wherein the target code stream is formed by performing 64B / 66B encoding and 256B / 257B transcoding on the Ethernet MAC packet.

[0145] In some embodiments, the first code stream is composed of multiple 66b code blocks, and the 66b code blocks include: a 66b start code block, a 66b data code block and a 66b end code block. The first code stream does not include a 66b idle code block.

[0146] In this embodiment, each Ethernet MAC packet can be transcoded into a group of 66b code blocks. Each group of 66b code blocks consists of a 66b start code block (S), several 66b data code blocks (D), and a 66b termination code block (T). 66b idle code blocks (I) are not included.

[0147] For example, in the process of performing 64B / 66B encoding on the Ethernet MAC packet, eight consecutive inter-frame gap (IPG) bytes will not be encoded into a 66b idle code block.

[0148] In this embodiment, the transcoding module is further configured to, when the number of remaining 66b coding blocks of the current MAC packet in the first code stream is less than 4 and the next Ethernet MAC packet has not been received, insert at least one 66b idle code block into the 66b termination code block corresponding to the current MAC packet, perform 256B / 257B transcoding, and obtain a 257b termination code block in the target code stream.

[0149] In some embodiments, when the number of remaining 66b coding blocks of the current MAC packet in the first code stream is less than 4 and the next Ethernet MAC packet is received, a 257b connection code block is used to connect the two Ethernet MAC packets. The 257b connection code block can be formed by transcoding the remaining 66b coding block of the current MAC packet and the 66b coding block in the header of the next MAC packet.

[0150] In some embodiments, the transcoding module is further configured to insert a 257b idle code block into the target code stream if the next Ethernet MAC packet is not received within a preset first threshold after the transcoding of the current MAC packet is completed, wherein the 257b idle code block is formed by transcoding four 66b idle code blocks.

[0151] In some embodiments, the receiving module includes a receiving unit and a decoding unit; the receiving unit is used to receive a data stream sent by a previous node and obtained by performing forward error correction encoding FEC on the target code stream; the decoding unit is used to perform forward error correction decoding processing on the data stream to obtain the target code stream; in the event that FEC cannot be corrected, all 257b coding blocks in the corresponding FEC code word in the target code stream are replaced with 257b error code blocks.

[0152] In some embodiments, the FEC codeword is 255 bytes long and consists of 239 bytes of normal data and 16 bytes of redundant overhead. If decoding of a FEC codeword fails, all 257b coded blocks in the FEC codeword need to be replaced with 257b error code blocks.

[0153] In some embodiments, the 257b error code block is formed by transcoding four 66b error code blocks.

[0154] In some embodiments, the 257b error code block can be identified by a preset third pattern. Exemplarily, the third pattern includes the first bit being 0, the second to fifth bits being 0000, and a second preset pattern; wherein the second preset pattern includes at least one of the following: the sixth to ninth bits are 0111, the tenth to 65th bits are 8 0111100; and the sixth to 13th bits are 01110111.

[0155] In some embodiments, when the current node is an intermediate node that supports 257b coding block switching, the rate adjustment module 104 includes:

[0156] a 257b exchange unit, configured to perform an exchange process on the target code stream based on the 257b coding block to obtain a target code stream after the exchange process;

[0157] The 257b rate adjustment unit is used to adjust the rate of the target code stream after the exchange process by adding or deleting the 257b idle code blocks.

[0158] In some embodiments, when the current node is an intermediate node that supports 66b coding block exchange, the rate adjustment module 104 includes:

[0159] a 66b transcoding unit, configured to transcode the target code stream to obtain a second code stream in a 64B / 66B format, wherein the second code stream includes a 66b idle code block;

[0160] a 66b exchange unit, configured to perform an exchange process on the second code stream based on the 66b coding block to obtain a second code stream after the exchange process;

[0161] a 66b rate adjustment unit, configured to perform rate adjustment on the second code stream after the exchange process by adding or deleting the 66b idle code blocks to obtain a rate-adjusted second code stream;

[0162] and a 257B transcoding unit, configured to perform 256B / 257B transcoding on the rate-adjusted second code stream, and shift, add, or delete the 66B idle code blocks in the rate-adjusted second code stream during the transcoding process to obtain a rate-adjusted target code stream in a 256B / 257B format, wherein the 257B code blocks in the rate-adjusted target code stream are of the same type as the 257B code blocks in the target code stream.

[0163] In some embodiments, when the current node is an intermediate node that supports 66b coding block exchange, the rate adjustment module 104 includes:

[0164] a deceleration unit, configured to delete some 257b idle code blocks in the target bitstream according to a preset proportional coefficient to obtain a decelerated target bitstream;

[0165] a 66b transcoding unit, configured to transcode the reduced-speed target code stream to obtain a second code stream in a 64B / 66B format, wherein the second code stream includes 66b idle code blocks;

[0166] a 66b exchange unit, configured to perform an exchange process on the second code stream based on the 66b coding block to obtain a second code stream after the exchange process;

[0167] a 256B / 257B transcoding unit, configured to perform 256B / 257B transcoding on the second bitstream after the switching process to obtain a target bitstream after the switching process;

[0168] The 257b rate adjustment unit is used to adjust the rate of the target code stream after the exchange process by adding or deleting the 257b idle code blocks.

[0169] Through the embodiments of the present disclosure, a rate adaptation mechanism based on a 257b code stream can be implemented, reducing the hardware implementation complexity of rate adaptation under a high-speed interface, thereby solving the problem in related technologies of high-speed Ethernet rate adaptation mechanism implementation complexity as the rate increases, and better supporting the development of high-speed Ethernet technology.

[0170] An embodiment of the present disclosure further provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above method embodiments are executed.

[0171] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0172] An embodiment of the present disclosure further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0173] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0174] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0175] It will be apparent to those skilled in the art that the modules or steps of the present disclosure described above can be implemented using a general-purpose computing device, centralized on a single computing device, or distributed across a network of multiple computing devices. They can be implemented using program code executable by the computing device, and thus stored in a storage device and executed by the computing device. In some cases, the steps shown or described herein can be performed in a different order than described herein, or can be implemented as separate integrated circuit modules, or multiple modules or steps can be implemented as a single integrated circuit module. Thus, the present disclosure is not limited to any particular combination of hardware and software.

[0176] The foregoing is merely an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that the present disclosure is susceptible to various modifications and variations. Any modifications, equivalent substitutions, improvements, and the like made within the principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A rate adjustment method, the method comprising: Obtaining a target bitstream in 256B / 257B format; Adjusting the rate of the target bitstream by adding or deleting 257b idle code blocks.

2. The method according to claim 1, wherein, Adjusting the rate of the target bitstream by adding or deleting 257b idle code blocks includes: Inserting the 257b idle code block after the 257b end code block or the 257b idle code block in the target bitstream; Or, deleting the 257b idle code block from the target bitstream.

3. The method according to claim 2, wherein, The 257b idle code block is transcoded from 4 66b idle code blocks; The 257b end code block is transcoded from a first number of 66b data code blocks, 1 66b end code block, and a second number of 66b idle code blocks, wherein the first number and the second number are greater than or equal to zero, and the sum of the first number and the second number is equal to 3.

4. The method according to claim 2, wherein Before adjusting the rate of the target bitstream by adding or deleting 257b idle code blocks, the method further includes: Identifying the 257b idle code block in the target bitstream through a first pattern; Wherein, the first pattern includes: the first bit is 0, the second to fifth bits are 0000, and a first preset pattern; Wherein, the first preset pattern includes at least one of the following: The sixth to ninth bits are 0111, and the tenth to sixty-fifth bits are all 0; The sixth to thirteenth bits are 01110000.

5. The method according to claim 2, wherein Before adjusting the rate of the target bitstream by adding or deleting 257b idle code blocks, the method further includes: Identifying the 257b end code block in the target bitstream through a second pattern; Wherein, the second pattern includes at least one of the following: The first bit is 0, the second to fifth bits are 0000, and the sixth to ninth bits are of a preset type; The first bit is 0, the second to fifth bits are 1000 or 1110; The first bit is 0, the second to fifth bits are 1100, and the two-hundred-and-second to two-hundred-and-fifty-seventh bits are all 0.

6. The method according to claim 1, wherein, The target bitstream is composed of multiple 257b coding blocks, and the 257b coding block further includes: a 257b start code block, wherein the 257b start code block is transcoded from 1 66b start code block and 3 66b data code blocks.

7. The method according to claim 1, wherein The target bitstream is composed of multiple 257b coding blocks, and the 257b coding block further includes: a 257b connection code block, wherein the 257b connection code block is transcoded from one 66b end code block, one 66b start code block, and 2 66b data code blocks, and the 66b end code block is located before the 66b start code block.

8. The method according to claim 1, wherein, Obtaining a target bitstream in 256B / 257B format includes: Performing 64B / 66B encoding on an Ethernet MAC packet to obtain a first bitstream in 64B / 66B format, and performing 256B / 257B transcoding on the first bitstream to obtain the target bitstream.

9. The method according to claim 1, wherein Obtain the target code stream in 256B / 257B format, including: receiving the target code stream sent by the previous node, where the target code stream is formed by performing 64B / 66B encoding and 256B / 257B transcoding on the Ethernet MAC packet.

10. The method according to claim 8, wherein, When performing 64B / 66B encoding on the Ethernet MAC packet, the inter-frame gap bytes in the Ethernet MAC packet are not encoded into 66b idle code blocks. The first code stream includes 66b start code blocks, 66b data code blocks, and 66b end code blocks, and the 66b idle code blocks are not included in the first code stream.

11. The method according to claim 8, wherein, Perform 256B / 257B transcoding on the first code stream to obtain the target code stream, including: transcoding the 66b end code block of the current MAC packet and the 66b start code block of the next MAC packet in the first code stream into a 257b connection code block, where the 257b connection code block does not contain 66b idle code blocks.

12. The method according to claim 8, wherein Perform 256B / 257B transcoding on the first code stream to obtain the target code stream, including: When the number of remaining 66b encoded blocks of the current MAC packet in the first code stream is less than 4 and the next Ethernet MAC packet has not been received, insert at least one 66b idle code block into the 66b end code block corresponding to the current MAC packet and then perform 256B / 257B transcoding.

13. The method according to claim 8, wherein Perform 256B / 257B transcoding on the first code stream to obtain the target code stream, further including: When the next Ethernet MAC packet has not been received within a preset first threshold after the transcoding of the current MAC packet in the first code stream is completed, insert 257b idle code blocks into the target code stream, where the 257b idle code blocks are formed by transcoding 4 66b idle code blocks.

14. The method according to claim 9, wherein, Receive the target code stream sent by the previous node, including: Receive the data stream obtained by performing forward error correction coding FEC on the target code stream sent by the previous node; Perform forward error correction decoding processing on the data stream to obtain the target code stream; In the case where FEC cannot correct errors, replace all 257b encoded blocks in the corresponding FEC codeword of the target code stream with 257b error code blocks.

15. According to the method described in claim 14, where The 257b error code block is formed by transcoding 4 66b error code blocks; The 257b error code block is recognized through a preset third mode, where the third mode includes that the first bit is 0, the second to fifth bits are 0000, and a second preset pattern; Where the second preset pattern includes at least one of the following: The sixth to ninth bits are 0111, and the tenth to sixty-fifth bits are 8 0111100s; The sixth to thirteenth bits are 01110111.

16. The method according to claim 1, wherein, When the current node is an intermediate node supporting 257b code block exchange, perform rate adjustment on the target code stream by adding or deleting 257b idle code blocks, including: Perform exchange processing on the target code stream based on 257b code blocks to obtain the target code stream after exchange processing; Adjust the rate of the target bitstream after the swapping process by adding or deleting the 257b idle code blocks.

17. The method according to claim 1, wherein, When the current node is an intermediate node supporting 66b coded block swapping, adjusting the rate of the target bitstream by adding or deleting 257b idle code blocks includes: Transcode the target bitstream to obtain a second bitstream in 64B / 66B format, where the second bitstream includes 66b idle code blocks; Perform a swapping process on the second bitstream based on 66b coded blocks to obtain a swapped second bitstream; Adjust the rate of the swapped second bitstream by adding or deleting the 66b idle code blocks to obtain a Second bitstream with adjusted rate; Perform 256B / 257B transcoding on the second bitstream with adjusted rate, and during the transcoding process, perform shifting, adding, or deleting operations on the 66b idle code blocks in the second bitstream with adjusted rate to obtain a target bitstream with adjusted rate in 256B / 257B format, where the 257b coded blocks in the target bitstream with adjusted rate are of the same type as the 257b coded blocks in the target bitstream.

18. The method according to claim 1, wherein When the current node is an intermediate node supporting 66b coded block swapping, adjusting the rate of the target bitstream by adding or deleting 257b idle code blocks includes: Delete some of the 257b idle code blocks in the target bitstream according to a preset proportional coefficient to obtain a target bitstream with reduced rate; Transcode the target bitstream with reduced rate to obtain a second bitstream in 64B / 66B format, where the second bitstream includes 66b idle code blocks; Perform a swapping process on the second bitstream based on 66b coded blocks to obtain a swapped second bitstream; Perform 256B / 257B transcoding on the swapped second bitstream to obtain a swapped target bitstream; Adjust the rate of the swapped target bitstream by adding or deleting the 257b idle code blocks.

19. A node, the node includes: An acquisition module for acquiring a target bitstream in 256B / 257B format; A rate adjustment module for adjusting the rate of the target bitstream by adding or deleting 257b idle code blocks.

20. A computer-readable storage medium storing a computer program therein, wherein, The computer program, when run by a processor, executes the method described in any one of claims 1 to 18.

21. An electronic device, comprising a memory and a processor, wherein, A computer program is stored in the memory, and the processor is configured to run the computer program to execute the method described in any one of claims 1 to 18.

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