Solar cell, manufacturing method therefor and photovoltaic module

Abstract

Provided in the present application are a solar cell, a manufacturing method therefor and a photovoltaic module. The solar cell comprises: an N-type substrate (1); an N-type diffusion layer (2) on a light-receiving surface of the N-type substrate (1); a patterned first passivated contact structure (3) on the N-type diffusion layer (2), the patterned first passivated contact structure (3) comprising a first dielectric layer (31) having a thickness of less than or equal to 2nm and an N-type doped polycrystalline silicon layer (32); and a second passivated contact structure (4) on a backside surface of the N-type substrate (1), the second passivated contact structure (4) comprising a second dielectric layer (41) having a thickness of greater than 2nm and a P-type heavily doped polycrystalline silicon layer (42), a PN junction being formed on the backside surface, the second dielectric layer (41) having a through hole (411), and the doping concentration of the P-type heavily doped polycrystalline silicon layer (42) being 5×1018-3×1020atom / cm3. A first functional layer (5) and a first electrode (7) are sequentially provided on the N-type diffusion layer (2) and the first passivated contact structure (3), and a second functional layer (6) and a second electrode (8) are sequentially provided on the P-type heavily doped polycrystalline silicon layer (42).

Description

Solar cell and preparation method thereof, photovoltaic module

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 5, 2024, with application number 202410017495.2 and application name “Solar cells, their preparation methods, and photovoltaic modules”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the technical field of solar cells, and in particular to a solar cell and a preparation method thereof, and a photovoltaic module. Background Art

[0003] Passivated contact solar cells (PCCs) are a type of solar cell with relatively high photoelectric conversion efficiency and are suitable for industrial application. However, when using industrial production processes to manufacture PCCs, their photoelectric conversion efficiency has reached a bottleneck, currently at approximately 25.1%. Limited by recombination losses on the light-receiving surface and current transmission losses, this type of solar cell has been difficult to further improve.

[0004] In addition, if the photoelectric conversion efficiency of this type of solar cell is to be further improved, there are still product reliability issues caused by structural or process limitations, including high and difficult to meet requirements for front surface passivation of the solar cell's light-receiving side, poor UV stability, and large lateral series resistance. Summary of the Invention

[0005] In order to solve the above technical problems, the embodiments of the present application provide a solar cell and a preparation method thereof, and a photovoltaic module to solve the problem that the passivated contact solar cells prepared by the current industrial production process are difficult to simultaneously improve the cell performance indicators and product reliability.

[0006] In a first aspect, the present application provides a solar cell, comprising:

[0007] N-type substrate;

[0008] An N-type diffusion layer is provided on the light-receiving surface of the N-type substrate;

[0009] a patterned first passivation contact structure disposed on the N-type diffusion layer, the first passivation contact structure comprising a first dielectric layer disposed proximate to the N-type diffusion layer and an N-type doped polysilicon layer disposed distally from the N-type diffusion layer; wherein the thickness of the first dielectric layer is less than or equal to 2 nm;

[0010] A second passivation contact structure is provided on the backlight surface of the N-type substrate. The second passivation contact structure includes a second dielectric layer provided close to the N-type substrate and a P-type heavily doped polysilicon layer provided away from the N-type substrate. A PN junction is formed between the P-type heavily doped polysilicon layer and the N-type substrate. The thickness of the second dielectric layer is greater than 2 nm. The second dielectric layer has a through hole connecting the N-type substrate and the P-type heavily doped polysilicon layer. The doping concentration of the P-type conductive element in the P-type heavily doped polysilicon layer is 5×10 18 atom / cm 3 ~3×10 20 atom / cm 3 ;

[0011] A first functional layer is provided on a side of the N-type diffusion layer and the N-type doped polysilicon layer away from the substrate;

[0012] A second functional layer is provided on a side of the P-type heavily doped polysilicon layer away from the N-type substrate;

[0013] a first electrode, penetrating the first functional layer and forming an ohmic contact with the N-type doped polysilicon layer; a patterned region of the first passivation contact structure and a patterned region of the first electrode being arranged correspondingly;

[0014] The second electrode penetrates the second functional layer and forms an ohmic contact with the P-type heavily doped polysilicon layer.

[0015] Furthermore, the N-type diffusion layer is a phosphorus diffusion layer, the sheet resistance of the N-type diffusion layer is 200Ω / sq to 350Ω / sq, the thickness of the N-type diffusion layer is 0.05μm to 0.5μm, and the doping concentration of the N-type conductive element in the N-type diffusion layer is 5×10 18 atoms / cm 3 ~1×10 20 atoms / cm 3 .

[0016] Furthermore, the N-type diffusion layer covered by the first passivation contact structure is 0.05 μm to 0.15 μm thicker than the N-type diffusion layer not covered by the first passivation contact structure.

[0017] Furthermore, the thickness of the N-type doped polysilicon layer is 30 nm to 200 nm, and the thickness of the P-type doped polysilicon layer is 200 nm to 400 nm.

[0018] Furthermore, the N-type doped polysilicon layer is doped with an N-type conductive element, and the N-type conductive element includes at least one of phosphorus, germanium or selenium.

[0019] The P-type conductive element includes at least one of boron, indium or gallium.

[0020] Furthermore, the diameter of the through hole is 50nm to 500nm, and the number of the through holes is 1×10 4 pieces / cm 2 ~1.6×10 8 pieces / cm 2 .

[0021] Furthermore, the width of the first passivation contact structure is 20 μm to 110 μm.

[0022] Furthermore, the ratio of the number of gate lines of the second electrode to the number of gate lines of the first electrode is 1.2-1.6:1.

[0023] Furthermore, the first functional layer includes a first passivation layer disposed close to the N-type diffusion layer, and a first anti-reflection layer disposed away from the N-type diffusion layer.

[0024] Furthermore, the second functional layer includes a second passivation layer disposed close to the P-type heavily doped polysilicon layer, and a second anti-reflection layer disposed away from the P-type heavily doped polysilicon layer.

[0025] Furthermore, the first functional layer includes the first passivation layer and the first anti-reflection layer, the first passivation layer is a silicon oxide layer, and the first anti-reflection layer is at least one of a silicon nitride layer, a silicon oxynitride layer, or a silicon oxide layer.

[0026] In a second aspect, an embodiment of the present application provides a method for preparing a solar cell as described in the first aspect above, the method for preparing a solar cell comprising the following steps:

[0027] Forming an N-type diffusion layer: performing a diffusion process of an N-type conductive element on the light-receiving surface of the N-type substrate to obtain the N-type diffusion layer;

[0028] Forming a passivation contact structure: sequentially disposing the first dielectric layer and the N-type doped amorphous silicon layer on the side of the N-type diffusion layer away from the N-type substrate, and sequentially disposing the second dielectric layer and the P-type doped amorphous silicon layer on the backlight side of the N-type substrate;

[0029] Patterning processing: after printing a patterned slurry in a predetermined area of ​​the N-type doped amorphous silicon layer, performing etching and cleaning to remove the first dielectric layer and the N-type doped amorphous silicon layer not covering the predetermined area, and then removing the slurry to retain the first dielectric layer and the N-type doped amorphous silicon layer covering the predetermined area;

[0030] Annealing: annealing the patterned N-type substrate to transform the N-type doped amorphous silicon layer into an N-type doped polysilicon layer, and the P-type doped amorphous silicon layer into a P-type heavily doped polysilicon layer, wherein the first dielectric layer and the N-type doped polysilicon layer form the first passivation contact structure, the second dielectric layer and the P-type heavily doped polysilicon layer form the second passivation contact structure, and the PN junction is formed between the N-type substrate and the P-type heavily doped polysilicon layer;

[0031] Post-processing: forming the first functional layer on the N-type diffusion layer and the patterned N-type doped polysilicon layer, forming the second functional layer on the P-type heavily doped polysilicon, manufacturing the first electrode on the first functional layer so that the first electrode penetrates the first functional layer to form an ohmic contact with the N-type doped polysilicon layer, and manufacturing the second electrode on the second functional layer so that the second electrode penetrates the second functional layer to form an ohmic contact with the P-type heavily doped polysilicon layer.

[0032] Furthermore, the step of forming the N-type diffusion layer is: using nitrogen gas carrying a gas source containing the N-type conductive element and oxygen to diffuse the N-type conductive element on the light-receiving surface of the N-type substrate to form the N-type diffusion layer with a thickness of 0.05 μm to 0.5 μm, the sheet resistance of the N-type diffusion layer is 200 Ω / sq to 350 Ω / sq, and the doping concentration of the N-type conductive element in the N-type diffusion layer is 5×10 18 atoms / cm 3 ~1×10 20 atoms / cm 3 .

[0033] Furthermore, the step of forming a passivation contact structure includes:

[0034] Pickling, using a first acid agent to pickle the N-type substrate that has been diffused, to remove the silicon glass doped with the N-type conductive element formed on the light-receiving surface and the backlight surface of the N-type substrate;

[0035] Depositing the first dielectric layer, a front intrinsic layer, a front doping layer doped with the N-type conductive element, and a front mask layer in sequence on the N-type diffusion layer;

[0036] Alkali polishing, using a second acid agent to remove the front mask layer plated around the backlight surface, and then using a first alkaline agent to polish the backlight surface of the N-type substrate, and remove the front doped layer, the front intrinsic layer and the first dielectric layer plated around the backlight surface and the edge;

[0037] Depositing the second dielectric layer, the back intrinsic layer, the back doped layer doped with a P-type conductive element, and the back mask layer in sequence on the backlight surface;

[0038] The N-type conductive element includes at least one of boron, indium or gallium, and the P-type conductive element includes at least one of phosphorus, germanium or selenium.

[0039] Furthermore, the front doped layer includes a first front doped sublayer and a second front doped sublayer, and both the first front doped sublayer and the second front doped sublayer are doped with the N-type conductive element.

[0040] Furthermore, the back doped layer includes a first back doped sublayer and a second back doped sublayer, and both the first back doped sublayer and the second back doped sublayer are doped with the P-type conductive element.

[0041] The N-type conductive element is phosphorus, and the P-type conductive element is boron.

[0042] Furthermore, the step of graphical processing includes:

[0043] Printing: Printing a patterned acid-resistant paste on the front mask layer, wherein the patterned area of ​​the acid-resistant paste corresponds to the preset area, and drying to solidify the acid-resistant paste;

[0044] Cleaning: first use a third acid to etch and remove the front mask layer that is not covered by the preset area in the light-receiving surface, then use a second alkaline agent to etch and remove the acid-resistant slurry, and remove the front doped layer, the front intrinsic layer and the first dielectric layer that are not covered by the preset area in the light-receiving surface, and then use a fourth acid to remove the front mask layer and the back mask layer.

[0045] Furthermore, in the printing step, the width of the printed patterned acid-resistant paste is 20 μm to 110 μm, the drying temperature after printing is 150° C. to 250° C., and the drying time is 8s to 12s.

[0046] Furthermore, in the annealing step, the annealing conditions are: annealing at a temperature of 850° C. to 1000° C. for 90 min to 150 min in an atmosphere with a volume ratio of nitrogen to oxygen of 1:1 to 8:1.

[0047] Furthermore, in the post-processing step, the post-processing step includes: sequentially forming a silicon oxide layer as a first passivation layer, and depositing a silicon nitride layer and / or a silicon oxynitride layer as a first anti-reflection layer on the N-type diffusion layer and the patterned N-type doped polysilicon layer, so that the first passivation layer and the first anti-reflection layer constitute the first functional layer;

[0048] An aluminum oxide layer is sequentially formed on the P-type heavily doped polysilicon layer as a second passivation layer, and a silicon nitride layer and / or a silicon oxynitride layer is deposited as a second anti-reflection layer, so that the second passivation layer and the second anti-reflection layer constitute the second functional layer.

[0049] In a third aspect, an embodiment of the present application provides a photovoltaic module, which includes the solar cell as described in the first aspect, or the photovoltaic module includes a solar cell produced by the method for producing a solar cell as described in the second aspect.

[0050] Compared with the prior art, the present invention has the following beneficial effects:

[0051] This application provides a novel solar cell structure that simultaneously features a double-sided passivated contact structure, a PN junction structure on the entire backlight side, a partially passivated contact structure on the light-receiving side, and an N-type diffusion layer on the light-receiving side as a front surface field. The combined effect of these structural features not only overcomes the current bottleneck in the photoelectric conversion efficiency of passivated contact solar cells, increasing the photoelectric conversion efficiency of solar cells to over 25.8%, but also effectively improves product reliability when the PN junction structure is provided on the backlight side.

[0052] The improvement in photoelectric conversion efficiency is due, firstly, to the fact that the backlight side of the solar cell has a full-surface passivation contact PN junction structure (the second passivation contact structure on the backside is composed of a second dielectric layer and a P-type heavily doped polysilicon layer, with the P-type heavily doped polysilicon layer and the N-type substrate forming the passivation contact PN junction structure), and the thickness of the second dielectric layer is greater than 2nm. This decouples the contact layer system from the light absorber, thereby resolving the problem of high Auger recombination in the PN junction on the light-receiving side. Secondly, the light-receiving side of the solar cell is a patterned first passivation contact structure, which is only arranged below the first electrode. This allows it to work together with the passivation contact PN junction structure on the backlight side to overcome the problems of high Auger recombination and metal recombination caused by boron diffusion doping on the front side of the light-receiving side. Third, thanks to the different thicknesses of the dielectric layers on the light-receiving and backlight sides, and the heavily doped P-type polysilicon layer on the backlight side, this structural feature allows the thinner first dielectric layer on the light-receiving side to achieve good electron transmission through the quantum tunneling effect, while the thicker second dielectric layer on the backlight side uses its through-holes that penetrate the thickness of its own film layer as carrier transmission channels. This, combined with the electron repulsion of the P-type heavily doped polysilicon layer, selectively allows larger holes to be effectively transmitted through the through-holes. As a result, the double-sided passivated contact structure with a PN junction on the backside can not only play a good carrier transmission and passivation role, but also assist in the decoupling of the PN junction. Through the combined effect of the above-mentioned multiple structures, the photoelectric conversion efficiency of the solar cell is improved.

[0053] The PN junction structure on the back side of the solar cell places higher demands on its product reliability, especially on the passivation quality of the light-receiving surface of the N-type substrate. This application achieves the goal of adding a front surface field to the light-receiving surface by adding an N-type diffusion layer to the light-receiving surface of the N-type substrate. This front surface field not only reduces the passivation requirements of the light-receiving surface, but also improves the stability of the solar cell against ultraviolet radiation and reduces the lateral series resistance, thereby improving the product reliability of the solar cell from multiple perspectives. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0055] FIG1 is a schematic structural diagram of a solar cell according to an embodiment of the present application;

[0056] FIG2 is an enlarged schematic diagram of the structure at point A in FIG1 ;

[0057] FIG3 is a process flow chart of the method for preparing the solar cell of Example 1.

[0058] Description of the drawings: 1. N-type substrate; 2. N-type diffusion layer; 3. First passivation contact structure; 31. First dielectric layer; 32. N-type doped polysilicon layer; 4. Second passivation contact structure; 41. Second dielectric layer; 411. Through hole; 42. P-type heavily doped polysilicon layer; 5. First functional layer; 51. First passivation layer; 52. First anti-reflection layer; 6. Second functional layer; 61. Second passivation layer; 62. Second anti-reflection layer; 7. First electrode; 8. Second electrode. DETAILED DESCRIPTION

[0059] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0060] In the present invention, terms such as "upper," "lower," "left," "right," "front," "back," "top," "bottom," "inner," "outer," "center," "vertical," "horizontal," "transverse," and "longitudinal" indicate positions or locations based on the positions or locations shown in the accompanying drawings. These terms are primarily intended to better describe the present invention and its embodiments and are not intended to limit the devices, elements, or components indicated to having a specific orientation, or to being constructed or operated in a specific orientation.

[0061] Furthermore, some of the above terms may be used to express other meanings besides indicating a position or location. For example, the term "on" may also be used to express a dependency or connection in certain circumstances. Those skilled in the art will understand the specific meanings of these terms in the present invention based on the specific circumstances.

[0062] Furthermore, the terms "installed," "disposed," "provided with," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral structures; mechanical connections or electrical connections; direct connections or indirect connections through an intermediary; or internal communication between two devices, elements, or components. Those skilled in the art will understand the specific meanings of these terms in the present invention based on specific circumstances.

[0063] Furthermore, the terms "first," "second," etc., are primarily used to distinguish between different devices, elements, or components (which may or may not be of the same type and configuration), and are not intended to indicate or imply the relative importance or quantity of the devices, elements, or components indicated. Unless otherwise specified, "plurality" means two or more.

[0064] The technical solution of the present invention will be described below with reference to embodiments and drawings.

[0065] The passivated contact solar cell in the related art uses a boron-diffused emitter on the light-receiving side and a tunneling layer and N-type doped polysilicon layer on the backlight side. Although passivated contact solar cells for industrial mass production have excellent high-temperature resistance, their photoelectric conversion efficiency has reached a certain bottleneck and is difficult to break through, remaining at approximately 25.1%. This is mainly because the emitter on the light-receiving side of the passivated contact solar cell needs to balance the effects of Auger recombination and current transmission losses.

[0066] Among them, because the light-receiving surface of the passivated contact solar cell is a boron-diffused emitter, if the current transmission loss is reduced by reducing the boron diffusion square resistance of the light-receiving surface, the Auger recombination loss of the light-receiving surface will also be greatly increased. If the resistance and thus the current transmission loss are reduced by adding metallized gate lines, the metallized gate lines will block more sunlight, resulting in the light not being absorbed by the silicon wafer, which will still affect the improvement of the photoelectric conversion efficiency. Therefore, it is difficult for current passivated contact solar cells to simultaneously achieve the reduction of current transmission loss and recombination loss, and thus restrict the further improvement of the photoelectric conversion efficiency of passivated contact solar cells.

[0067] Improving passivated contact solar cells by combining a double-sided passivated contact structure with a backlit PN junction can help overcome the bottleneck in photoelectric conversion efficiency for this type of cell. This structural improvement involves providing passivated contact structures on both the light-receiving and backlit sides of the N-type substrate. Furthermore, the boron-diffused emitter, originally located on the light-receiving side of the solar cell, is modified to be located on the backlit side of the solar cell, forming a backlit PN junction. This reduces doping on the light-receiving side and lowers surface recombination, while also minimizing minority carrier transmission losses. Furthermore, the current transmission capacity of the backlit side can be increased by increasing the number of backlit electrode grid lines, without having to worry about the number of grid lines affecting shading.

[0068] However, for solar cells with a double-sided passivated contact structure and a PN junction on the backlight side, since minority carriers are mainly generated on the light-receiving side of the N-type substrate (i.e., the side where sunlight is incident), the minority carriers must diffuse through the N-type substrate to the backlight side before they can be collected by the PN junction on the backlight side. This mechanism determines that the product reliability of this type of solar cell is not easy to achieve, mainly due to the following three problems:

[0069] First, this type of cell requires very high surface passivation quality. In solar cells with a PN junction on the backlight side, most photocarriers are generated on the light-receiving surface of the N-type substrate. If the surface passivation quality of the light-receiving side is not high, the photocarriers are easily lost due to recombination when passing through the poorly passivated film layer, and thus cannot successfully reach the PN junction on the backlight side of the N-type substrate. The selection of materials with high surface passivation quality is very limited, which is not conducive to the mass production of solar cells.

[0070] Second, the UV stability is poor. Since the PN junction is set on the backlight side, it is difficult to balance the UV resistance and PID (Potential Induced Degradation) resistance when setting a passivation layer on the light-receiving side of the N-type substrate. In particular, solar cells using silicon oxide as the passivation layer on the light-receiving side will show a significant performance degradation when exposed to UV light. Specifically, after UV irradiation, the surface saturation current density (Jo) drops from 48fA / cm 2 Increased to 446fA / cm 2 In ultraviolet exposure and light injection experiments, it was found that when the energy of ultraviolet light was greater than 3.1eV (corresponding to light with a wavelength less than 400nm), the interface state density on the silicon dioxide passivation surface increased significantly, resulting in a decrease in the surface recombination velocity (S front )Increase.

[0071] Third, the lateral series resistance is high. Because the PN junction in the double-sided passivated contact structure is located on the backlight side, the light-receiving side uses an N-type doped polysilicon layer containing positively charged N-type conductive elements such as phosphorus. However, the N-type doping level in this N-type doped polysilicon layer is limited, resulting in a large square resistance, making lateral carrier movement difficult and resulting in high lateral series resistance.

[0072] Based on the above analysis, the applicant believes that in order to ensure the product reliability of such solar cells on the basis of improving the photoelectric conversion efficiency of passivated contact solar cells, so that the improved passivated contact solar cells can adapt to mass production with more reliable and stable product characteristics, it is necessary to further improve the structure of such solar cells so that they can not only break through the bottleneck of the photoelectric conversion efficiency of existing passivated contact solar cells, but also have good product reliability.

[0073] In a first aspect, an embodiment of the present application provides a solar cell, as shown in FIG1 , which is a schematic structural diagram of a solar cell according to an embodiment of the present application, the solar cell includes:

[0074] N-type substrate 1;

[0075] N-type diffusion layer 2, provided on the light-receiving surface of N-type substrate 1;

[0076] A patterned first passivation contact structure 3 is provided on the N-type diffusion layer 2. The first passivation contact structure 3 includes a first dielectric layer 31 disposed near the N-type diffusion layer 2 and an N-type doped polysilicon layer 32 disposed away from the N-type diffusion layer 2. The thickness of the first dielectric layer 31 is less than or equal to 2 nm.

[0077] The entire second passivation contact structure 4 is provided on the backlit surface of the N-type substrate 1. The second passivation contact structure includes a second dielectric layer 41 provided close to the N-type substrate 1 and a P-type heavily doped polysilicon layer 42 provided away from the N-type substrate 1. A PN junction is formed between the P-type heavily doped polysilicon layer 42 and the N-type substrate 1. The thickness of the second dielectric layer 41 is greater than 2 nm. The second dielectric layer has a through hole 411 connecting the N-type substrate 1 and the P-type heavily doped polysilicon layer 42. The doping concentration of the P-type conductive element in the P-type heavily doped polysilicon layer 42 is 5×10 18 atom / cm 3 ~3×10 20 atom / cm 3 ;

[0078] The first functional layer 5 is provided on a side of the N-type diffusion layer 2 and the N-type doped polysilicon layer 32 away from the substrate;

[0079] The second functional layer is provided on the side of the P-type heavily doped polysilicon layer 42 away from the N-type substrate 1;

[0080] The first electrode 7 penetrates the first functional layer 5 and forms an ohmic contact with the N-type doped polysilicon layer 32; the patterned area of ​​the first passivation contact structure 3 is arranged corresponding to the patterned area of ​​the first electrode 7;

[0081] The second electrode 8 penetrates the second functional layer and forms an ohmic contact with the P-type heavily doped polysilicon layer 42 .

[0082] The materials of the first and second dielectric layers may include a variety of dielectric materials, such as at least one of silicon oxide, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. Specifically, the dielectric layer may be composed of a silicon oxide layer containing silicon oxide. This is because the silicon oxide layer has excellent passivation properties, can minimize the recombination loss of minority carriers on the surface of the semiconductor substrate, and is a film with excellent durability for subsequent high-temperature processes.

[0083] The thickness of the first dielectric layer 31 is less than or equal to 2 nm, preferably less than or equal to 1.5 nm. At such a thin thickness, electrons generated by light irradiating the light-receiving surface can act as carriers and tunnel through the first dielectric layer 31 via a tunneling mechanism, thereby achieving electron collection. It is understood that during the fabrication process, the first dielectric layer 31 of this thickness may produce some cracked pinholes due to annealing. These pinholes can also serve as channels for electron transmission, allowing electrons to be transmitted and conducted via both tunneling and direct conduction mechanisms. The thickness of the first dielectric layer 31 is 0.8 nm to 2.0 nm, including any value within this thickness range. For example, the thickness of the first dielectric layer 31 is 0.8 nm, 0.9 nm, 1.0 nm, 1.2 nm, 1.5 nm, 1.6 nm, 1.8 nm, or 2.0 nm. Furthermore, the first dielectric layer 31 can also serve as a diffusion barrier to prevent dopants in the N-type doped polysilicon layer (i.e., the N-type conductive element used to dope the N-type doped polysilicon layer) from diffusing into the semiconductor substrate.

[0084] The thickness of the second dielectric layer 41 is greater than 2 nm. Under this thickness condition, it is difficult for electrons to pass through the film layer through the tunneling mechanism. As holes are larger than electrons, it is even more difficult for them to pass through the film layer through the tunneling mechanism. Therefore, the present application realizes the transmission of holes on the backlight side by opening a through hole 411 in the second dielectric layer 41 that runs through the film thickness direction and adopts a heavily doped P-type doped polysilicon layer. In addition, the above-mentioned second dielectric layer 41 can also serve as a diffusion barrier to prevent the dopant of the P-type doped polysilicon layer (i.e., the P-type conductive element used to dope the P-type doped polysilicon layer) from diffusing into the semiconductor substrate.

[0085] The doping concentration of the P-type conductive element in the P-type heavily doped polysilicon layer is 5×10 18 atom / cm 3 ~3×10 20 atom / cm 3 . Within this doping concentration range, the P-type heavily doped polysilicon layer has a high doping content of P-type conductive elements, which is a case of heavy doping. The present application found that when a thicker second dielectric layer with a thickness greater than 2 nm is provided on the back side, it works together with the P-type heavily doped polysilicon layer with the above doping concentration to have a good selectivity effect on holes, and solves the problem that small-volume electrons always have a higher probability of passing through than large-volume holes. Exemplarily, the above doping concentration includes any point value within the above numerical range, for example, the doping concentration of the P-type conductive element in the P-type heavily doped polysilicon layer is 5×10 18 atom / cm 3 , 6×10 18 atom / cm 3 , 8×10 18 atom / cm3 , 1×10 19 atom / cm 3 , 5×10 19 atom / cm 3 , 8×10 19 atom / cm 3 , 1×10 20 atom / cm 3 or 3×10 20 atom / cm 3 .

[0086] The entire second passivation contact structure 4 means that, unlike the patterned first passivation contact structure 3 , the second passivation contact structure 4 covers the backlight surface of the N-type substrate 1 , thereby forming a relatively complete film structure rather than a partially passivated patterned structure.

[0087] Among them, the patterned area of ​​the first passivation contact structure is set corresponding to the patterned area of ​​the first electrode, which means that the patterned area of ​​the first passivation contact structure and the patterned area of ​​the first electrode are set correspondingly in position, and the line width dimensions are the same or similar. For example, the patterned line widths of the two can be set to be the same, or can be set to the line width of the first passivation contact structure slightly larger than the line width of the first electrode, thereby ensuring that the first electrode mainly made of metal material only contacts the first passivation contact structure, and does not contact the silicon wafer, while also ensuring the alignment effect of the first electrode and the first passivation contact structure.

[0088] The present invention provides a novel solar cell structure, which simultaneously features a double-sided passivated contact structure, a PN junction structure on the entire backlight side, a partial passivated contact structure on the light-receiving side, and an N-type diffusion layer 2 on the light-receiving side. These structural features work together to overcome the current bottleneck in the photoelectric conversion efficiency of passivated contact solar cells, raising the solar cell's photoelectric conversion efficiency to over 25.8%. Furthermore, they improve product reliability when the PN junction structure is provided on the backlight side.

[0089] The structural characteristics and performance advantages of the solar cell are described in detail below.

[0090] In terms of photoelectric conversion efficiency, since the solar cell of the embodiment of the present application has a double-sided passivation contact structure with a local passivation contact on the light-receiving side and a full-surface passivation contact on the backlight side, as well as structural characteristics such as a decoupled PN junction on the backlight side, the solar cell can simultaneously have low light-receiving side recombination loss and current transmission loss, so that the photoelectric conversion efficiency of the solar cell can be increased to more than 25.8%.

[0091] First, the solar cell of the embodiment of the present application has a passivated contact PN junction structure on the entire backlight side. Because the solar cell of the embodiment of the present application has a first passivated contact structure 3 and a second passivated contact structure 4 on the light-receiving and backlight sides of the N-type substrate 1, respectively, and the second passivated contact structure 4 located on the backlight side includes a P-type heavily doped polysilicon layer 42, it not only realizes the passivation contact function with the second dielectric layer 41, but also forms a PN junction with respect to the N-type substrate 1. This is equivalent to simultaneously forming a passivated contact structure and a PN junction structure—a passivated contact PN junction structure—on the backlight side of the solar cell. Thus, because this passivated contact PN junction structure can decouple the contact layer system from the light absorber, unlike the prior art method in which the light-receiving side boron diffusion PN junction is formed near the surface of the N-type substrate 1, it can effectively solve the problem of high Auger recombination of the light-receiving side PN junction, thereby avoiding the contradiction between the boron diffusion resistance and Auger recombination loss of the light-receiving side PN junction. It should be noted that although in the related art, when a tunneling layer and an N-type doped polysilicon layer 32 are formed on the backlit side of an N-type substrate 1 (for example, a polysilicon layer doped with phosphorus is formed on the backlit side), the tunneling layer and the N-type doped polysilicon layer 32 can form a passivation contact structure, there is still strong electronic and chemical interaction between this structure and the N-type substrate 1, which can cause band bending and diffusion effects. Therefore, the doped polysilicon layer in this structure is not decoupled from the N-type substrate 1, but rather remains strongly connected.

[0092] In addition to the advantageous feature of decoupling, since the present application sets a passivated contact PN junction structure on the backlight surface, there is no shading problem, so the current transmission loss can be further reduced by increasing the number of metallized grid lines on the backlight surface. It can be seen that compared to setting a PN junction on the light-receiving surface, which requires considering many restrictions such as the number and area of ​​metallized grid lines, the embodiment of the present application sets a passivated contact PN junction structure on the backlight surface. In addition to having advantages in reducing Auger recombination losses, it also has the advantage of further reducing current transmission losses without affecting light absorption. That is: by setting a passivated contact PN junction structure on the backlight surface, the embodiment of the present application can simultaneously reduce Auger recombination losses and current transmission losses, thereby further improving the photoelectric conversion efficiency of the solar cell.

[0093] Secondly, while forming a passivation contact PN junction structure on the backlight surface of the solar cell, the embodiment of the present application forms a local passivation contact structure on the light-receiving surface of the solar cell. The solar cell of the embodiment of the present application forms a first passivation contact structure 3 on the light-receiving surface that corresponds only to the metallization area, that is, a first dielectric layer 31 and an N-type doped polysilicon layer 32 are provided under the first electrode 7. By forming a local passivation contact structure on the light-receiving surface in this way, the problem of high Auger recombination caused by boron diffusion doping, especially heavy doping, on the entire light-receiving surface in the related art is overcome, as well as the problem of metal recombination caused by metallization of the light-receiving surface is reduced. Not only that, since the light-receiving surface adopts a local passivation contact structure, it can also effectively reduce the parasitic absorption caused by the N-type doped polysilicon layer 32 in the first passivation contact structure 3 and the problem of reduced battery short-circuit current, thereby improving the short-circuit current performance of the solar cell and optimizing the photoelectric conversion efficiency of the solar cell.

[0094] In this way, since a local passivation contact structure is formed on the light-receiving surface of the solar cell, the cell performance can be optimized from the two aspects of overcoming recombination loss and reducing the backlight surface resistance, thereby improving the photoelectric conversion efficiency of the solar cell; since a full-surface passivation contact PN junction structure is formed on the backlight surface of the solar cell, it can not only reduce the recombination loss of the light-receiving surface, but also conduct electricity through the entire surface of the N-type substrate 1, thereby reducing the minority carrier transmission loss toward the local metal contact at the front end, improving the fill factor, and further promoting the improvement of the photoelectric conversion efficiency of the solar cell.

[0095] Finally, and most importantly, the solar cell of the embodiment of the present application, based on the PN junction set on the backlight side, can better collect carriers on the light-receiving side and the backlight side by adopting the structural setting of dielectric layers of different thicknesses for the double-sided passivation contact structure and the combined effect of using a P-type heavily doped polysilicon layer 42 on the back. Specifically, because the solar cell of the embodiment of the present application sets the PN junction on the backlight side, the backlight side is to collect holes as carriers, and the light-receiving side is to collect electrons as carriers. However, the volume of holes is much larger than that of electrons. Using quantum tunneling, the tunneling probability of electrons is always greater than the tunneling probability of holes. Therefore, achieving effective hole transmission on the backlight side is not achievable through conventional quantum tunneling mechanisms. To this end, the present application adopts a combined structure of a relatively thin first dielectric layer 31 and an N-type doped polysilicon layer 32 on the light-receiving surface, wherein the thickness of the first dielectric layer 31 is less than or equal to 2 nm. Under this thickness condition, the first dielectric layer 31 can allow very small electrons to tunnel through the film structure of the first dielectric layer 31, and can also use the openings in the first dielectric layer 31 as conductive channels to complete the transmission of electrons as carriers. The backlight surface uses a combined structure of a thicker second dielectric layer 41 and a P-type heavily doped polysilicon layer 42. Although the thickness of the second dielectric layer 41 is greater than 2nm, which exceeds the ideal tunneling layer thickness, and the large volume of the holes makes it difficult to selectively transmit holes using the tunneling mechanism, the present application opens a through hole 411 through the thicker second dielectric layer 41 and uses a P-type heavily doped polysilicon layer 42. Through the synergistic effect of the two, the repulsive effect of the P-type heavily doped polysilicon layer 42 on electrons is utilized to block the passage of electrons, thereby selectively allowing holes to pass through the through hole 411 for carrier transmission, completing the transmission of holes as carriers.

[0096] In summary, the solar cell of the embodiment of the present application can further improve the photoelectric conversion efficiency of the solar cell through the interaction of the above-mentioned structures.

[0097] In terms of product reliability, since the PN junction structure on the backlight side requires that holes as carriers can reach the backlight side and be collected, high requirements are placed on the surface passivation quality of the light-receiving surface of the N-type substrate 1 to ensure product reliability. The solar cell of the present embodiment adds an N-type diffusion layer 2 between the N-type substrate 1 and the first dielectric layer 31 on the light-receiving surface. That is, on the basis of the PN junction structure on the backlight side, a front surface field is added on the light-receiving surface.

[0098] On the one hand, the efficiency of the back junction structure with the light-receiving surface N-type diffusion layer 2 is relatively wide in the front surface recombination velocity (S 0,front)) range (<500cm / s), it can still maintain a very high level. This property allows the addition of the N-type diffusion layer 2 to reduce the requirements for surface passivation of the light-receiving surface. The use of materials with conventional passivation properties can also reduce surface recombination, which is beneficial for the selection of passivation materials during mass production. On the other hand, the addition of the N-type diffusion layer 2 to the light-receiving surface also makes the solar cell of the embodiment of the present application have good ultraviolet irradiation stability. The doped region of the N-type diffusion layer 2 reduces the minority carrier density and reduces the occurrence of surface recombination. On the other hand, since the provision of the N-type diffusion layer 2 can repel minority carriers on the light-receiving surface and reduce surface recombination, and the doped region of the N-type diffusion layer 2 can serve as a parallel low-resistance channel for the majority carriers on the light-receiving surface to reach the metal contact, it is also beneficial to reduce the lateral series resistance.

[0099] The specific structure of the solar cell in the embodiment of the present application is further explained below.

[0100] The N-type substrate 1 may be, for example, an N-type silicon wafer, and the light-receiving surface of the N-type silicon wafer serves as a light incident surface for receiving irradiation from sunlight to generate carriers in the form of electrons and holes.

[0101] The N-type diffusion layer 2 is provided on the light-receiving surface of the N-type substrate 1 and can be an N-type diffusion layer 2 formed by doping an N-type conductive element such as a phosphorus diffusion layer, a germanium diffusion layer, or a selenium diffusion layer into the N-type substrate 1. Preferably, the N-type diffusion layer 2 is a phosphorus diffusion layer, the sheet resistance of the N-type diffusion layer 2 is 200Ω / sq to 350Ω / sq, the thickness of the N-type diffusion layer 2 is 0.05μm to 0.5μm, and the doping concentration of the N-type conductive element in the N-type diffusion layer 2 is 5×10 18 atoms / cm 3 ~1×10 20 atoms / cm 3 Using the aforementioned phosphorus diffusion layer as the diffusion layer near the N-type substrate 1 can reduce intrinsic recombination, SRH (Shockley-Read-Hall) recombination, and electron-bulk resistance losses. This is because the enhanced internal electric field promotes the separation of electrons and holes, shortens carrier transport time, and ultimately suppresses overall bulk recombination. In particular, when the sheet resistance of the N-type diffusion layer 2 is within the aforementioned impedance level range, the recombination of the N-type diffusion layer 2 is low, which helps further suppress overall bulk recombination.

[0102] The square resistance of the N-type diffusion layer 2 is 200Ω / sq to 350Ω / sq, including any value within this numerical range. For example, the square resistance of the N-type diffusion layer 2 is 200Ω / sq, 210Ω / sq, 220Ω / sq, 230Ω / sq, 240Ω / sq, 250Ω / sq, 260Ω / sq, 270Ω / sq, 280Ω / sq, 290Ω / sq, or 300Ω / sq. The thickness of the N-type diffusion layer 2 is 0.05μm to 0.5μm, including any value within this numerical range. For example, the thickness of the N-type diffusion layer 2 is 0.05μm, 0.08μm, 0.1μm, 0.15μm, 0.2μm, 0.3μm, 0.4μm, or 0.5μm. The doping concentration of the N-type conductive element in the N-type diffusion layer 2 is 5×10 18 atoms / cm 3 ~1×10 20 atoms / cm 3 Including any point value within this numerical range, for example, the doping concentration of the N-type conductive element in the N-type diffusion layer 2 is 5×10 18 atoms / cm 3 , 1×10 19 atoms / cm 3 , 2×10 19 atoms / cm 3 , 4×10 19 atoms / cm 3 , 5×10 19 atoms / cm 3 , 8×10 19 atoms / cm 3 or 1×10 20 atoms / cm 3 .

[0103] Further referring to FIG. 2 , which is an enlarged schematic diagram of the structure at point A in FIG. 1 , the thickness of the N-type diffusion layer 2 varies in different regions. The N-type diffusion layer 2 covered by the first passivation contact structure 3 is 0.05 μm to 0.15 μm thicker than the N-type diffusion layer 2 not covered by the first passivation contact structure 3 . In other words, the thickness of the N-type diffusion layer 2 in the region not covered by the first passivation contact structure 3 is relatively thinner. This structural arrangement ensures that when patterning the first passivation contact structure 3, the regions of the first passivation contact structure 3 that do not need to be retained can be fully etched away, preventing the first passivation contact structure 3 from remaining on the N-type diffusion layer 2 and absorbing light, thereby affecting the photoelectric conversion efficiency. This ensures that the patterning effect of the first passivation contact structure 3 is maintained.

[0104] The patterned first passivation contact structure 3 is disposed above the N-type diffusion layer 2 and only below the position corresponding to the first electrode 7, thereby achieving local passivation contact on the light-receiving surface. The width of the first passivation contact structure 3 is 20 μm to 110 μm, which is slightly wider than the line width of the first electrode 7, ensuring good ohmic contact between the first electrode 7 and the first passivation contact structure 3. Within the above-mentioned width range, the first passivation contact structure 3 can not only play a certain role in carrier transport and passivation, but also reduce the doping amount on the light-receiving surface of the substrate by reducing the front-side doping to doping similar to the gate line pattern, thereby better overcoming the Auger recombination problem caused by doping diffusion. It can be understood that the line width of the first dielectric layer 31 and the line width of the N-type doped polysilicon layer 32 in the first passivation contact structure 3 are both within the above-mentioned line width range.

[0105] In the first passivation contact structure 3, the thickness of the N-type doped polysilicon layer 32 is 30 nm to 200 nm. The N-type conductive element doped in the N-type doped polysilicon layer 32 includes at least one of phosphorus, germanium, or selenium, preferably phosphorus. The thickness of the N-type doped polysilicon layer 32 is 30 nm to 200 nm, including any value within this numerical range. For example, the thickness of the N-type doped polysilicon layer 32 is 30 nm, 50 nm, 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, or 200 nm.

[0106] The second passivation contact structure 4 is disposed on the backlit surface of the N-type substrate 1. This is not a patterned passivation contact structure, but rather a full-surface passivation contact structure. The structure used to transmit carriers in the second passivation contact structure 4 is a second dielectric layer 41. This second dielectric layer 41 has a through-hole 411 extending through it. This structural feature, combined with the P-type heavily doped polysilicon layer 42, allows the through-hole 411 to selectively allow holes to pass through while blocking electrons.

[0107] The diameter of the through holes 411 on the second dielectric layer 41 is 50 nm to 500 nm, and the number of the through holes 411 is 1×10 4 pieces / cm 2 ~1.6×10 8 pieces / cm 2The above-mentioned aperture and number of through holes 411 are conducive to better control of the passivation effect and direct carrier transport effect of the second dielectric layer 41, which can achieve both better direct carrier transport and good passivation effect, and reduce the influence of too many through holes 411 or too large aperture on the passivation effect, or too few through holes 411 or too small aperture on the direct transport of holes. The diameter of the through hole 411 is 50nm to 500nm, including any point value within the diameter range, for example, the diameter of the through hole 411 is 50nm, 80nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm or 500nm. The number of through holes 411 is 1×10 4 pieces / cm 2 ~1.6×10 8 pieces / cm 2 Including any point value within this number range, for example, the number of through holes 411 is 1×10 4 pieces / cm 2 , 2×10 4 pieces / cm 2 , 5×10 4 pieces / cm 2 , 8×10 4 pieces / cm 2 , 1×10 5 pieces / cm 2 , 2×10 5 pieces / cm 2 , 5×10 5 pieces / cm 2 , 8×10 5 pieces / cm 2 or 1×10 6 pieces / cm 2 .

[0108] In the second passivation contact structure 4, the thickness of the P-type heavily doped polysilicon layer 42 is 200 nm to 400 nm. The P-type conductive element doped in the P-type heavily doped polysilicon layer 42 includes at least one of boron, indium, or gallium, preferably boron. The thickness of the P-type heavily doped polysilicon layer 42 is 200 nm to 400 nm, including any value within this numerical range. For example, the thickness of the P-type heavily doped polysilicon layer 42 is 200 nm, 250 nm, 300 nm, 350 nm, or 400 nm.

[0109] In the double-sided passivation contact structure of the present application, the thickness of the P-type doped polysilicon layer on the backlight side is set to be thicker than the thickness of the N-type doped polysilicon layer 32 on the light-receiving side to achieve the same or similar square resistance. Taking the doping of phosphorus in the N-type doped polysilicon layer 32 on the light-receiving side and the doping of boron in the P-type heavily doped polysilicon layer 42 on the backlight side as an example, the solid solubility of phosphorus in the N-type doped polysilicon layer 32 is much higher than the solid solubility of boron in the P-type heavily doped polysilicon layer 42. Therefore, the thickness of the P-type doped polysilicon layer is set to be thicker, which is conducive to doping more boron, so that the square resistance of the backlight side and the light-receiving side reaches the same or similar level.

[0110] The first functional layer 5 is disposed on the N-type diffusion layer 2 and the first passivation contact structure 3. Specifically, because the first passivation contact structure 3 is a localized passivation contact structure, the first functional layer 5 is disposed above the N-type diffusion layer 2 in areas where the first electrode 7 is not disposed. In areas where the first electrode 7 is disposed, the first functional layer 5 is disposed above the N-type doped polysilicon layer 32 of the first passivation contact structure 3. The first electrode 7 penetrates the first functional layer 5 and forms an ohmic contact with the N-type doped polysilicon layer 32. The first functional layer 5 may be solely the first passivation layer 51 or solely the first anti-reflection layer 52. It may also include the first passivation layer 51 disposed proximate to the N-type diffusion layer 2 and the first anti-reflection layer 52 disposed distally from the N-type diffusion layer 2. The thickness of the first passivation layer 51 is 3 nm to 5 nm, for example, 3 nm, 4 nm, or 5 nm. The thickness of the first anti-reflection layer 52 is 75 nm to 85 nm, for example, 75 nm, 78 nm, 80 nm, 82 nm, or 85 nm, and the refractive index of the first anti-reflection layer 52 is 1.95 to 2.00. The first passivation layer 51 may be a composite of one or more sub-layers, and the first passivation layer 51 is preferably a silicon oxide layer. The first anti-reflection layer 52 may be a composite of one or more sub-layers, for example, a single silicon nitride layer, or a composite of multiple silicon nitride layers. Preferably, the first anti-reflection layer 52 comprises a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, sequentially disposed from the inside out (i.e., from the direction close to the substrate toward the direction away from the substrate).

[0111] Unlike the practice of using aluminum oxide as a passivation layer, the present embodiment of the present application uses silicon oxide as the first passivation layer 51 on the light-receiving surface. Silicon oxide passivation layers have better PID resistance but poorer UV resistance. However, because the present embodiment of the present application includes an N-type diffusion layer 2 on the light-receiving surface of the solar cell, the N-type diffusion layer 2 improves the UV resistance of the silicon oxide passivation layer as the first passivation layer 51 and reduces the occurrence of surface recombination. Therefore, the combined effect of the N-type diffusion layer 2 and the silicon oxide layer as the first passivation layer 51 improves the solar cell's PID resistance and ensures good UV stability.

[0112] The second functional layer is disposed on the backlight side of the P-type heavily doped polysilicon layer 42, facing away from the N-type substrate 1. The second electrode 8 penetrates the second functional layer and forms an ohmic contact with the P-type heavily doped polysilicon layer 42. The second functional layer can be solely the second passivation layer 61 or solely the second anti-reflection layer 62. Alternatively, the second functional layer includes the second passivation layer 61 disposed proximate to the P-type heavily doped polysilicon layer 42 and the second anti-reflection layer 62 disposed distally therefrom. Preferably, the second functional layer includes the second passivation layer 61 disposed proximate to the P-type heavily doped polysilicon layer 42 and the second anti-reflection layer 62 disposed distally therefrom. The thickness of the second passivation layer 61 is 3 nm to 5 nm, for example, 3 nm, 4 nm, or 5 nm. The thickness of the second anti-reflection layer 62 is 75 nm to 80 nm, for example, 75 nm, 76 nm, 77 nm, 78 nm, 79 nm, or 80 nm. The refractive index of the second anti-reflection layer 62 is 2.10 to 2.15. The second passivation layer 61 can be a composite of one or more sublayers. For example, the second passivation layer 61 can be an aluminum oxide layer or a composite of multiple aluminum oxide sublayers. Providing the second passivation layer 61 on the backlight side of the N-type substrate 1 can provide passivation protection for the PN junction located on the backlight side. The second anti-reflection layer 62 can be a composite of one or more sublayers. For example, the second anti-reflection layer 62 can be a silicon nitride layer or a composite of multiple silicon nitride layers.

[0113] After penetrating the first functional layer 5, the first electrode 7 forms an ohmic contact with the N-type doped polysilicon layer 32. The line width of the first electrode 7 is equal to or slightly smaller than the line width of the N-type doped polysilicon layer 32, ensuring a good and reliable ohmic connection between the first electrode 7 and the N-type doped polysilicon layer 32. When the first functional layer 5 comprises several different layer structures, for example, when the first functional layer 5 comprises a first passivation layer 51 and a first anti-reflection layer 52 arranged from the inside out, the first electrode 7 sequentially penetrates the first anti-reflection layer 52 and the first passivation layer 51, forming an ohmic contact with the N-type doped polysilicon layer 32. The second electrode 8 penetrates the second functional layer 6 and forms an ohmic contact with the P-type heavily doped polysilicon layer 42. When the second functional layer comprises several different layer structures, for example, when the second functional layer comprises a second passivation layer 61 and a second anti-reflection layer 62 arranged from the inside out, the second electrode 8 sequentially penetrates the second anti-reflection layer 62 and the second passivation layer 61, forming an ohmic contact with the P-type heavily doped polysilicon layer 42.

[0114] Furthermore, because the PN junction of the embodiment of the present application is formed on the backlight side, the present application can provide more electrode grid lines on the backlight side, so that the ratio of the number of grid lines of the second electrode 8 to the number of grid lines of the first electrode 7 is 1.2 to 1.6:1. In this way, by increasing the number of grid lines on the backlight side, the current transmission capacity can be further improved without causing light blocking problems, thereby further improving the photoelectric conversion efficiency of the solar cell.

[0115] In a second aspect, an embodiment of the present application provides a method for preparing a solar cell according to the first aspect, comprising the following steps:

[0116] Forming an N-type diffusion layer: performing a diffusion process of an N-type conductive element on the light-receiving surface of the N-type substrate to obtain an N-type diffusion layer;

[0117] Forming a passivation contact structure: sequentially disposing a first dielectric layer and an N-type doped amorphous silicon layer on the side of the N-type diffusion layer away from the N-type substrate, and sequentially disposing a second dielectric layer and a P-type doped amorphous silicon layer on the backlight side of the N-type substrate;

[0118] Patterning: After printing a patterned slurry in a predetermined area of ​​the N-type doped amorphous silicon layer, etching and cleaning are performed to remove the first dielectric layer and the N-type doped amorphous silicon layer that are not covered in the predetermined area, and then the slurry is removed to retain the first dielectric layer and the N-type doped amorphous silicon layer that cover the predetermined area;

[0119] Annealing: Annealing the patterned N-type substrate to transform the N-type doped amorphous silicon layer into an N-type doped polysilicon layer, and the P-type doped amorphous silicon layer into a P-type heavily doped polysilicon layer. The first dielectric layer and the N-type doped polysilicon layer form a first passivation contact structure, the second dielectric layer and the P-type heavily doped polysilicon layer form a second passivation contact structure, and a PN junction is formed between the N-type substrate and the P-type heavily doped polysilicon layer.

[0120] Post-processing: forming a first functional layer on the N-type diffusion layer and the patterned N-type doped polysilicon layer, forming a second functional layer on the P-type heavily doped polysilicon, fabricating a first electrode on the first functional layer so that the first electrode penetrates the first functional layer to form an ohmic contact with the N-type doped polysilicon layer, and fabricating a second electrode on the second functional layer so that the second electrode penetrates the second functional layer to form an ohmic contact with the P-type heavily doped polysilicon layer.

[0121] The following is a further explanation of each step.

[0122] The steps of forming the N-type diffusion layer are as follows: using nitrogen gas containing a source gas containing N-type conductive elements and oxygen to diffuse the N-type conductive elements on the light-receiving surface of the N-type substrate to form an N-type diffusion layer with a thickness of 0.05μm to 0.5μm, a sheet resistance of 200Ω / sq to 350Ω / sq, and a doping concentration of the N-type conductive elements in the N-type diffusion layer of 5×10 18 atoms / cm 3 ~1×10 20 atoms / cm 3 .

[0123] As a preferred embodiment, the N-type conductive element in the above steps is phosphorus, and the gas source containing the N-type conductive element is phosphorus oxychloride.

[0124] An N-type diffusion layer is formed on the surface of an N-type substrate as a front surface field by diffusion advancement. This process has strong compatibility with existing processes and is conducive to industrial application.

[0125] The steps of forming a passivation contact structure include:

[0126] Pickling, using a first acid agent to pickle the N-type substrate after the diffusion treatment to remove the silicon glass doped with N-type conductive elements formed on the light-receiving surface and the backlight surface of the N-type substrate;

[0127] Depositing a first dielectric layer, a front intrinsic layer, a front doping layer doped with an N-type conductive element, and a front mask layer in sequence on the N-type diffusion layer;

[0128] Alkali polishing, using a second acid agent to remove the front mask layer that is plated around the backlight surface, and then using the first alkaline agent to polish the backlight surface of the N-type substrate, and remove the front doped layer, the front intrinsic layer and the first dielectric layer that are plated around the backlight surface and the edge;

[0129] Depositing a second dielectric layer, a back intrinsic layer, a back doped layer doped with a P-type conductive element, and a back mask layer in sequence on the backlight surface;

[0130] The N-type conductive element includes at least one of boron, indium or gallium, and the P-type conductive element includes at least one of phosphorus, germanium or selenium.

[0131] In the above-mentioned step of forming a passivation contact structure, the first acid used for pickling can be a hydrofluoric acid solution with a volume percentage of 4% to 6%. Taking the N-type diffusion layer as a phosphorus diffusion layer as an example, the use of this first acid can remove the phosphorus silicate glass formed on the light-receiving surface and the backlight surface during the formation of the N-type diffusion layer. In the step of alkali polishing, the second acid can be a hydrofluoric acid solution with a volume percentage of 4% to 6%, and the first alkali can be an alkali metal hydroxide and an alkali polishing additive with a volume ratio of 2:1 to 4:1. The temperature of the alkali polishing is 70°C to 90°C, and the texturing time is 5min to 8min. By using the above-mentioned reagents to perform corresponding treatment on the doped silicate glass formed by making the N-type diffusion layer and the wrap-around coating layer formed by making the double-sided passivation contact structure, the effects of polishing and removing wrap-around coating can be better achieved.

[0132] Furthermore, the front doping layer can be one or more layers, for example, the front doping layer includes a first front doping sublayer and a second front doping sublayer, and each layer is doped with an N-type conductive element, and the N-type conductive element is preferably a phosphorus element. Compared with setting only one front doping layer, the method of setting the front doping layer in two or more layers can reduce the doping concentration of the N-type conductive element in each layer while ensuring that the total doping concentration reaches a certain level, thereby reducing the probability of lattice distortion caused by the high doping concentration. Similarly, the back doping layer can be one or more layers, for example, the back doping layer includes a first back doping sublayer and a second back doping sublayer, and each layer is doped with a P-type conductive element, and the P-type conductive element is preferably a boron element. When the back doping layer is arranged in layers, it also has similar effects to the layered arrangement of the front doping layer.

[0133] The deposition process for the first dielectric layer, the N-type doped amorphous silicon layer, the second dielectric layer, and the P-type doped amorphous silicon layer can be PECVD (Plasma Enhanced Chemical Vapor Deposition), LPCVD (Low Pressure Chemical Vapor Deposition), or ALD (Atomic Layer Deposition). Preferably, the PECVD process is used to deposit the above-mentioned film layers.

[0134] The steps of graphical processing include:

[0135] Printing: Printing a patterned acid-resistant paste on the front mask layer, with the patterned area of ​​the acid-resistant paste corresponding to the preset area, and drying to solidify the acid-resistant paste;

[0136] Cleaning: First, use the third acid to etch and remove the front mask layer that is not covered in the preset area of ​​the light-receiving surface, then use the second alkaline agent to etch and remove the acid-resistant slurry, and remove the front doped layer, front intrinsic layer and first dielectric layer that are not covered in the preset area of ​​the light-receiving surface, and then use the fourth acid to remove the front mask layer and the back mask layer.

[0137] Furthermore, in the printing step, the width of the printed patterned acid-resistant paste is 20 μm to 110 μm, and the drying temperature after printing is 150° C. to 250° C. for 8 to 12 seconds. In the cleaning step, the third acid agent can be a hydrofluoric acid solution with a mass percentage of 4% to 6%, and the first alkaline agent can be an alkali metal hydroxide and a texturing additive in a volume ratio of 1:1 to 3:1. The cleaning temperature is 70° C. to 90° C., and the texturing time is 1 to 3 minutes.

[0138] In the above-mentioned patterning process, a patterned acid-resistant paste is first printed in a preset area of ​​the front mask layer on the light-receiving surface and cured. The acid-resistant paste can resist the corrosion of acidic reagents and protect the first doped amorphous silicon layer and the tunneling layer in the preset area. In this way, a third acid agent can be used to etch away the front mask layer except for the area covered by the acid-resistant paste, so that only the patterned front mask layer that is not etched due to the protection of the acid-resistant paste remains on the light-receiving surface; then a second alkaline agent is used to etch away the front doped layer, the front intrinsic layer, and the first dielectric layer located below the remaining front mask layer because they are protected from etching, and the remaining front doped layer, the front intrinsic layer, and the first dielectric layer that are not protected by the front mask layer are all etched away, and the acid-resistant paste on the front is removed by alkaline cleaning; finally, a third acid agent is used to remove the front mask layer on the light-receiving surface and the back mask layer on the backlight surface. Finally, through the combined use of the above three reagents, the light-receiving surface forms a local first dielectric layer and an N-type doped amorphous silicon layer corresponding only to the first electrode, and the backlight surface forms the entire second dielectric layer and a P-type doped polysilicon layer.

[0139] Furthermore, because the second alkaline etching agent is used to remove a portion of the N-type diffusion layer, leaving this portion of the N-type diffusion layer 0.05 μm to 0.15 μm thinner than the N-type diffusion layer within the predetermined region, the excess N-type doped amorphous silicon layer and the first dielectric layer are fully etched away, thereby ensuring that only the N-type doped amorphous silicon layer and the first dielectric layer within the predetermined region are protected, ultimately forming an effective patterned first passivation contact structure. This avoids light absorption caused by residual first passivation contact structure on the N-type diffusion layer. For example, in an optional embodiment, the N-type diffusion layer 2 may be 0.2 μm thick, and the portion of the N-type diffusion layer 2 covered by the first passivation contact structure 3 may be 0.05 μm thicker than the portion of the N-type diffusion layer 2 not covered by the first passivation contact structure 3, i.e., approximately 0.05 μm of the N-type diffusion layer is removed by etching.

[0140] The annealing step involves annealing at 850°C to 1000°C for 90 to 150 minutes in an atmosphere with a nitrogen to oxygen volume ratio of 1:1 to 8:1. These conditions transform the N-type doped amorphous silicon layer into an N-type doped polycrystalline silicon layer, and the P-type doped amorphous silicon layer into a heavily P-type doped polycrystalline silicon layer. A PN junction is formed between the N-type substrate and the heavily P-type doped polycrystalline silicon layer. Furthermore, ruptured through-holes are created in both the first and second dielectric layers for carrier transmission.

[0141] The post-processing step includes: forming a silicon oxide layer as a first passivation layer, and depositing a silicon nitride layer and / or a silicon oxynitride layer as a first anti-reflection layer on the N-type diffusion layer and the patterned N-type doped polysilicon layer, so that the first passivation layer and the first anti-reflection layer constitute a first functional layer;

[0142] An aluminum oxide layer is sequentially formed on the P-type heavily doped polysilicon layer as a second passivation layer, and a silicon nitride layer and / or a silicon oxynitride layer is deposited as a second anti-reflection layer, so that the second passivation layer and the second anti-reflection layer constitute a second functional layer.

[0143] In a third aspect, embodiments of the present application further provide a photovoltaic module, comprising the solar cell of the first aspect, or comprising the solar cell produced by the preparation method of the second aspect. The photovoltaic module is formed by connecting a plurality of the aforementioned solar cells in series and / or in parallel and encapsulating them.

[0144] The solar cell prepared in this application and its performance will be further described below in conjunction with the examples, drawings and test data.

[0145] Example 1

[0146] This embodiment provides a solar cell, as shown in FIG3 , which is a process flow chart of the solar cell of Example 1. The preparation method of the solar cell includes the following steps:

[0147] Provide an N-type substrate: an N-type 182-size M10 silicon wafer is used as the N-type substrate, with a resistivity of 0.4Ω·cm to 1.6Ω·cm and a minority carrier lifetime of >0.5ms; the N-type substrate has a light-receiving surface and a backlight surface disposed opposite to each other, with the light-receiving surface being the light incident surface;

[0148] Texturing: In a tank-type equipment, the light-receiving surface of the N-type substrate is texturized using sodium hydroxide and the texturing additive TS40 in a volume ratio of 7:1 at 80°C for 7 minutes, with a thickness reduction of 5μm.

[0149] Phosphorus diffusion: The texturized N-type substrate is placed in a phosphorus diffusion furnace. Phosphorus oxychloride gas and oxygen are carried by nitrogen gas to deposit a phosphorus source on the light-receiving surface of the N-type substrate and form a phosphorus diffusion layer.

[0150] Tank pickling: Immerse the N-type substrate with the phosphorus diffusion layer in a tank machine and use a 5% by volume hydrofluoric acid solution to remove the phosphorus silicon glass layer on the light-receiving and backlight surfaces of the N-type substrate;

[0151] Deposition of the first passivation contact structure: A tubular PECVD device is used to deposit a composite film on the light-receiving surface after pickling. Five thin film layers are deposited at a pressure of 2500mTorr to 3500mTorr and a temperature of 350℃ to 450℃.

[0152] Film layer 1: Using PECVD, 8SLM to 15SLM of N2O was introduced, and the deposition time was 140s to deposit the first dielectric layer SiO with a thickness of 1.5nm. x ;

[0153] Layer 2: PECVD is used to deposit SiH4 and H2 at a volume ratio of 1:2.5 for 40s to 90s to deposit a front intrinsic layer as an amorphous thin film layer with a thickness of 5nm to 40nm.

[0154] Layer 3: PECVD is used to deposit a first front-side doped sublayer of phosphorus-doped amorphous silicon thin film with a thickness of 5nm to 40nm, using SiH4, PH3, and H2 in a volume ratio of 1:0.4:2.5 for 40s to 90s.

[0155] Layer 4: PECVD is used to deposit a second front-side doped sublayer of phosphorus-doped amorphous silicon thin film with a thickness of 20 nm to 80 nm, using SiH4, PH3, and H2 in a volume ratio of 1:0.8:2.5 for 250 to 350 seconds.

[0156] Layer 5: Using PECVD, SiH4, NH3, and N2O in a volume ratio of 1:4:7, the deposition time is 60 seconds, and a silicon oxynitride film is deposited as the front mask layer with a thickness of 5nm to 40nm.

[0157] Alkali polishing: A chain HF machine is used to remove the front mask layer that has been plated to the backlight side using a 5% by volume hydrofluoric acid solution. The substrate is then transferred to a tank alkali polishing machine and the backlight side of the N-type substrate is polished using a 3:1 by volume mixture of sodium hydroxide and alkali polishing additive BP31 at a temperature of 80°C for 7 minutes. The second front doped sublayer, the first front doped sublayer, the front intrinsic layer, and the first dielectric layer that have been plated to the backlight side and the edge are simultaneously removed.

[0158] Deposition of the second passivation contact structure: A composite film is deposited on the backlit side of the N-type substrate using a tubular PECVD device. Five thin film layers are deposited at a pressure of 2500mTorr to 3500mTorr and a temperature of 350°C to 450°C.

[0159] Film layer 1: Using PECVD, 8SLM to 15SLM of N2O was introduced, and the deposition time was 240s to deposit a second dielectric layer of SiO with a thickness of 2.5nm. x ;

[0160] Layer 2: PECVD is used to deposit an amorphous film layer on the back side with a thickness of 5nm to 40nm by introducing SiH4 and H2 at a volume ratio of 1:2.5 for a deposition time of 40s to 90s.

[0161] Layer 3: Using PECVD, SiH4, TMB, and H2 in a volume ratio of 1:0.3:2.5, the deposition time is 80s to 300s, and a first back-doped sublayer doped with boron is deposited as an amorphous silicon film with a thickness of 10nm to 80nm.

[0162] Layer 4: PECVD is used to deposit a second back-light-side doped sublayer doped with boron to a thickness of 150 nm to 350 nm, using SiH4, TMB, and H2 in a volume ratio of 1:0.6:2.5 for a deposition time of 1500 to 3000 seconds.

[0163] Layer 5: Using PECVD, SiH4, NH3, and N2O in a volume ratio of 1:4:7, the deposition time is 60 seconds, and a silicon oxynitride film is deposited as the back mask layer with a thickness of 5nm to 40nm.

[0164] Printing: Screen-printing a patterned acid-resistant paste in a preset area of ​​the front mask layer, where the pattern is similar to or identical to the pattern of the screen-printed first electrode, and the line width of the printed acid-resistant paste is 20μm to 110μm, which is slightly wider than the width of the screen-printed first electrode pattern; after printing, drying at 150°C to 250°C for 10 seconds; wherein the acid-resistant paste can protect the first dielectric layer and N-type doped amorphous silicon layer (i.e., the front mask layer, the front intrinsic layer, the first front doped sublayer, the second front doped sublayer, and other amorphous silicon thin film layers) located thereunder; wherein the preset area corresponds to the area where the first electrode is provided in the solar cell;

[0165] Cleaning: First, pass through a chain device and use a 5% by mass hydrofluoric acid solution to remove the front mask layer, so that only the patterned part that has not been etched due to the protection of the acid-resistant slurry remains on the light-receiving surface, and then enter the tank texturing machine, use sodium hydroxide and texturing additive TS40 with a volume ratio of 2:1 at a temperature of 80°C, and etch for 2 minutes to remove the first dielectric layer, N-type doped amorphous silicon layer, and acid-resistant slurry that are not covered in the preset area of ​​the light-receiving surface; then enter the acid tank and use a 5% by volume hydrofluoric acid solution to etch away the back mask layer located on the backlight side and the front mask layer located in the preset area of ​​the light-receiving surface, so that the light-receiving surface of the N-type substrate is sequentially the patterned first dielectric layer and the N-type doped amorphous silicon layer, and the backlight surface of the N-type substrate is sequentially the entire second dielectric layer and the P-type doped amorphous silicon layer;

[0166] Annealing: Annealing is performed in a tubular annealing furnace at 850°C for 120 minutes in a nitrogen atmosphere of 10 SLM and an oxygen atmosphere of 5 SLM, so that the N-type doped amorphous silicon layer is transformed into an N-type doped polycrystalline silicon layer, and the P-type doped amorphous silicon layer is transformed into a P-type heavily doped polycrystalline silicon layer. The first dielectric layer and the N-type doped polycrystalline silicon layer form a first passivation contact structure, the second dielectric layer and the P-type heavily doped polycrystalline silicon layer form a second passivation contact structure, and a PN junction is formed between the N-type substrate and the P-type heavily doped polycrystalline silicon layer. Due to the introduction of the oxygen atmosphere, a silicon oxide layer is formed on the N-type diffusion layer on the light-receiving surface and the first passivation contact structure as a first passivation layer;

[0167] Deposition of the second passivation layer: A 5 nm thick aluminum oxide layer is deposited on the P-type heavily doped polysilicon layer using atomic layer deposition (ALD).

[0168] Depositing a first anti-reflection layer: using PECVD to sequentially deposit silicon nitride and silicon oxynitride films on the first passivation layer as a composite first anti-reflection layer for anti-reflection. The total thickness of the first anti-reflection layer is controlled to be 75 nm to 85 nm, and the refractive index is 1.95 to 2.00.

[0169] Deposition of the second anti-reflection layer: using PECVD to deposit silicon nitride on the second passivation layer as a protective layer for back film hydrogen passivation, with a thickness of 75nm to 80nm and a refractive index of 2.10 to 2.15;

[0170] Screen printing: Silver paste is sequentially printed on the backlight side as the first electrode, and silver paste is printed on the light-receiving side as the second electrode. The electrodes are then sintered at 840°C to complete the process. The second electrode penetrates the first anti-reflection layer and the first passivation layer, forming an ohmic contact with the N-type doped polysilicon layer in a predetermined area. The first electrode penetrates the second anti-reflection layer and the second passivation layer, forming an ohmic contact with the P-type heavily doped polysilicon layer in a predetermined area. Light is injected into the cell at a process temperature of 700°C. The number of gate lines on the second electrode is 1.4 times that of the first electrode.

[0171] In the solar cell of this embodiment, the film parameters of the N-type diffusion layer and the passivation contact structure (including film thickness, doping concentration, through-hole parameters, etc.) are specifically shown in Table 1 below.

[0172] The differences between Example 2 to Example 16 and Example 1 are detailed in Table 1 below.

[0173] Comparative Example 1

[0174] This comparative example provides a solar cell. The only difference between the solar cell in this comparative example and that in Example 1 is that, in terms of the structure of the solar cell, no phosphorus diffusion layer is provided on the light-receiving surface of the N-type substrate; in terms of the preparation method, after texturing, the phosphorus diffusion and trough pickling steps are not performed, and the first passivation contact structure is directly deposited.

[0175] Comparative Example 2

[0176] This comparative example provides an N-type passivated contact solar cell, the preparation method of which comprises the following steps:

[0177] Providing an N-type substrate: using an N-type 182 size M10 silicon wafer as the N-type substrate, the N-type substrate having a light-receiving surface and a backlight surface disposed opposite to each other, the light-receiving surface being the light incident surface;

[0178] Texturing: In a tank-type equipment, the light-receiving surface of the N-type substrate is texturized using sodium hydroxide and the texturing additive TS40 in a volume ratio of 7:1 at 80°C for 7 minutes, with a thickness reduction of 5μm.

[0179] Boron diffusion: Place the textured N-type substrate into a boron diffusion furnace. Use boron trichloride gas and oxygen at a volume ratio of 3:1 to deposit a boron source on the light-receiving surface of the N-type substrate at 830°C. Then, heat it at 1030°C for 1 hour to form a PN junction. The sheet resistance after diffusion is controlled at 120Ω / sq~140Ω / sq.

[0180] Alkali polishing: A chain HF machine is used with a 50% by volume hydrofluoric acid solution to remove the borosilicate glass (BSG) with boron expansion on the backlight side. Then, the backlight side of the N-type substrate is polished in a tank-type alkali polishing machine using a 3:1 volume ratio of sodium hydroxide and alkali polishing additive BP31 at a temperature of 80°C for 7 minutes to remove the PN junction that was plated around the backlight side and the edge during the boron expansion step.

[0181] The first dielectric layer and poly-Si passivation film on the backlight side: A tubular PECVD device is used to deposit the composite film on the backlight side of the N-type substrate. Four thin film layers are deposited at a pressure of 2500mTorr to 3500mTorr and a temperature of 350℃ to 450℃.

[0182] Film layer 1: Using PECVD, 8SLM to 15SLM of N2O was introduced, and the deposition time was 140s to deposit the first dielectric layer SiO with a thickness of 1nm. x ;

[0183] Layer 2: PECVD was used to deposit an intrinsic amorphous layer with a thickness of 20 nm using SiH4 and H2 at a volume ratio of 1:2.5 for 65 seconds.

[0184] Layer 3: PECVD was used to deposit a 100 nm thick phosphorus-doped amorphous silicon layer using SiH4, PH3, and H2 in a volume ratio of 1:0.8:2.5 for 500 s.

[0185] Film layer 4: PECVD was used to introduce SiH4 and N2O with a volume ratio of 1:4.5, and the deposition time was 60s to deposit SiO x layer, thickness of 20 nm;

[0186] Annealing: A tubular annealing furnace is used to anneal the silicon wafers in a nitrogen atmosphere with a nitrogen flow rate of 5 SLM at a temperature of 850°C to 950°C for 120 minutes and an annealing time of 2700 seconds, so that the crystal structure of the deposited amorphous silicon layer is transformed to form a phosphorus-doped polysilicon layer.

[0187] Cleaning: First, the oxide layer on the light-receiving surface is removed from one side of the surface by using a chain-type device with a mass concentration of 5% hydrofluoric acid. Then, the surface is transferred to a tank-type alkaline polishing machine, using a volume ratio of 2:1 sodium hydroxide and an alkaline polishing additive BP31. The temperature is maintained at 80°C for about 2 minutes to remove the polysilicon thin film layer that was deposited on the light-receiving surface during the annealing step. Finally, the surface is transferred to an acid tank with a mass concentration of 5% hydrofluoric acid to remove the BSG layer on the light-receiving surface.

[0188] Aluminum oxide film and silicon nitride film deposition on the light-receiving surface: A 5nm thick aluminum oxide film is deposited by atomic layer deposition (ALD) for passivation. Then, silicon nitride, silicon oxynitride, and silicon oxide films are sequentially deposited on the light-receiving surface by PECVD for anti-reflection. The total thickness is controlled at 75nm to 85nm, and the refractive index is 1.95-2.00.

[0189] Backlight side silicon nitride film deposition: PECVD is used to deposit silicon nitride film for back film hydrogen passivation, with a thickness of 75nm to 80nm and a refractive index of 2.10 to 2.15;

[0190] Screen printing: Print the silver paste on the backlight side and the silver-aluminum paste on the light-receiving side in sequence, and complete the electrode production at a sintering process temperature of 840°C; complete the light injection into the battery at a process temperature of 700°C.

[0191] That is to say, the preparation method of Comparative Example 2 is to first form a PN junction on the light-receiving surface of the N-type substrate through boron diffusion, and then form a passivation contact structure composed of a tunneling layer and a phosphorus-doped polysilicon layer on the backlight side of the N-type substrate through PECVD and annealing operations, so that Comparative Example 2 becomes a passivation contact solar cell with a PN junction on the light-receiving surface and a passivation contact on the backlight side.

[0192] The differences between Comparative Examples 3 to 5 and Example 1 are detailed in Table 1 below.

[0193] Performance testing:

[0194] Doping concentration: obtained by conventional ECV equipment testing (i.e., using the electrochemical capacitance-voltage method to measure the doping concentration distribution).

[0195] Diameter and number of through holes: First, the sample is corroded with TMAH (tetramethylammonium hydroxide) solution to remove the doped polysilicon. The sample with the doped polysilicon removed is then placed under a SEM for observation to test the diameter and number of holes. The number is then divided by the area of ​​observation to obtain the number of holes per unit area.

[0196] Table 1. Film parameters of N-type diffusion layer and passivation contact structure in solar cells

[0197] <Electrical performance test>

[0198] The solar cells of the above examples and comparative examples were tested for performance, including open circuit voltage, short circuit current, and fill factor, using a Halm test and sorting device. The Halm machine is a device that simulates sunlight and is equipped with an electronic load, data acquisition, and computing equipment to test the electrical performance of photovoltaic devices (including solar cells). The silicon wafers used in the control test were 182 mm in size and the calibrated light intensity was 1000 ± 5 W / m 2 ,The experimental test results are shown in Table 2 below.

[0199] Table 2. Performance test results of solar cells

[0200] From the performance test results analysis in Table 2, we can see that:

[0201] Comparing Example 1, Comparative Example 1, and Comparative Example 2, it can be seen that compared to the solar cell in Comparative Example 2, which uses a back-light-side passivated contact structure, Example 1 and Comparative Example 1, due to the use of a double-sided passivated contact structure and a back-light-side PN junction structure, not only does the metallization of the light-receiving surface significantly reduce, resulting in a significant increase in open-circuit voltage, but also allows for electrical conduction through the entire silicon wafer, reducing minority carrier transmission losses toward the local metal contact at the front end, thereby improving the fill factor and resulting in a higher photoelectric conversion efficiency. Furthermore, because Example 1 of the present application further adds a front surface field of a phosphorus diffusion layer on the basis of Comparative Example 1, while enhancing the passivation effect on the light-receiving surface of the solar cell, the phosphorus diffusion layer also reduces the lateral transmission resistance of the light-receiving surface, thereby improving the open-circuit voltage and fill factor. Taking these two aspects into consideration, the photoelectric conversion efficiency of the solar cell in Example 1 of the present application is more significantly improved, further reducing the cost per watt of the solar cell.

[0202] Furthermore, by comparing Examples 1, 7, and 8, it can be seen that indicators such as the solar cell's photoelectric conversion efficiency first increase and then decrease with increasing thickness of the first dielectric layer, with the highest photoelectric conversion efficiency achieved when the first dielectric layer is 1.5 nm thick. Further comparison with Comparative Example 3 shows that when the thickness of the first dielectric layer exceeds 2 nm, the open-circuit voltage, fill factor, and photoelectric conversion efficiency all decrease significantly. This shows that a first dielectric layer thickness of less than or equal to 2 nm significantly improves indicators such as photoelectric conversion efficiency, particularly when the first dielectric layer is 1.5 nm thick, achieving a greater improvement.

[0203] By comparing Example 1, Example 11, Example 12 with Comparative Example 4, it can be seen that the thickness of the second dielectric layer in Comparative Example 4 is 1.7 nm, but its corresponding photoelectric conversion efficiency is low. Therefore, it can be seen that the thickness of the second dielectric layer must be greater than 2 nm to effectively improve the photoelectric conversion efficiency of the solar cell. When the thickness of the second dielectric layer in Example 1 is 2.5 nm, a better photoelectric conversion efficiency improvement effect is achieved.

[0204] By comparing Example 1 with Comparative Example 5, it can be seen that the doping concentration of the P-type conductive element in the P-type doped polysilicon layer will also have a significant impact on the performance of the solar cell, such as the photoelectric conversion efficiency. In Comparative Example 5, the doping concentration of the P-type conductive element in the P-type doped polysilicon layer is low, which cannot effectively select electrons and holes, affecting the transmission effect of holes as majority carriers on the backlight surface, thereby affecting the improvement of the photoelectric conversion efficiency. Further comparison with Example 15 shows that when the doping concentration of the P-type element is a larger 1×10 19 atoms / cm 3 It is more helpful to improve the photoelectric conversion efficiency.

[0205] A further comparison of Examples 1 to 5 shows that indicators such as the solar cell's photoelectric conversion efficiency first increase and then decrease as the sheet resistance of the N-type diffusion layer increases. The highest photoelectric conversion efficiency is achieved when the sheet resistance of the N-type diffusion layer is between 250Ω / sq and 300Ω / sq. Furthermore, a comparison of Examples 1 and 6 shows that the photoelectric conversion efficiency decreases when the thickness of the N-type diffusion layer increases from 0.2μm to 0.3μm, indicating that a preferred thickness for the N-type diffusion layer is 0.2μm.

[0206] Comparisons of Example 1, Example 9, and Example 10, and of Example 1, Example 13, and Example 14 show that different thicknesses of N-type doped polysilicon layers and P-type doped polysilicon layers affect the photovoltaic conversion efficiency of solar cells to varying degrees, with the thickness of the N-type doped polysilicon layer having a particularly significant effect. Preferably, an N-type doped polysilicon layer with a thickness of 100 nm and a P-type doped polysilicon layer with a thickness of 300 nm exhibit a superior photovoltaic conversion efficiency improvement.

[0207] By comparing Example 1, Example 16 and Example 17, it can be seen that the number of through holes in the second dielectric layer also affects the photoelectric conversion efficiency of the solar cell. In this application, the number of through holes is preferably 1×10 6 pieces / cm 3 When the hole transport effect and the passivation effect are better taken into account,

[0208] <UV attenuation performance test>

[0209] The solar cells of Example 1, Comparative Example 1 and Comparative Example 2 were subjected to UV attenuation tests. After the cells were encapsulated, they were placed in a UV box and irradiated with ultraviolet light at 70°C. After a cumulative irradiation of 60 kW, the attenuation value after ultraviolet irradiation was tested. The photoelectric conversion efficiency performance of the cells before and after attenuation was tested using a halm test and sorting device.

[0210] Table 3. UV60 UV attenuation test results of solar cells

[0211] From the performance test results analysis in Table 3, we can see that:

[0212] Compared to the solar cell in Comparative Example 1, which does not have an N-type diffusion layer on the light-receiving surface, Example 1 significantly reduces the UV60 ultraviolet attenuation rate due to the N-type diffusion layer on the light-receiving surface. Compared to the passivated contact solar cell in Comparative Example 2, Example 1 also has a lower UV60 ultraviolet attenuation rate. This shows that even though Comparative Example 2 uses an aluminum oxide film with good UV resistance as the passivation layer on the light-receiving surface, its UV attenuation resistance is not as good as that of Example 1 of this solution. This shows that the synergistic effect of the N-type diffusion layer and the silicon oxide layer can bring about better UV attenuation resistance. It can be seen that the embodiments of the present application can not only improve the photoelectric conversion efficiency of the solar cell, but also have better UV resistance stability, which is conducive to improving the product reliability of the solar cell.

[0213] The solar cells, preparation methods, and photovoltaic modules disclosed in the embodiments of the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A solar cell, characterized in that, The solar cell includes: an N-type substrate; an N-type diffusion layer disposed on the light-receiving surface of the N-type substrate; a patterned first passivated contact structure disposed on the N-type diffusion layer, the first passivated contact structure including a first dielectric layer disposed close to the N-type diffusion layer and an N-type doped polysilicon layer disposed away from the N-type diffusion layer; wherein, the thickness of the first dielectric layer is less than or equal to 2 nm; The second passivation contact structure covering the whole surface is disposed on the backlight surface of the N-type substrate. The second passivation contact structure includes a second dielectric layer disposed close to the N-type substrate and a P-type heavily doped polysilicon layer disposed away from the N-type substrate. A PN junction is formed between the P-type heavily doped polysilicon layer and the N-type substrate. Among them, the thickness of the second dielectric layer is greater than 2 nm. The second dielectric layer has a through hole connecting the N-type substrate and the P-type heavily doped polysilicon layer. The doping concentration of the P-type conductive element in the P-type heavily doped polysilicon layer is 5×10 18 atom / cm 3 ~3×10 20 atom / cm 3 ; a first functional layer disposed on a side of the N-type diffusion layer and the N-type doped polysilicon layer away from the substrate; a second functional layer disposed on a side of the P-type heavily doped polysilicon layer away from the N-type substrate; a first electrode penetrating the first functional layer to form an ohmic contact with the N-type doped polysilicon layer; the patterned area of the first passivated contact structure and the patterned area of the first electrode are correspondingly disposed; a second electrode penetrating the second functional layer to form an ohmic contact with the P-type heavily doped polysilicon layer.

2. The solar cell according to claim 1, characterized in that, The sheet resistance of the N-type diffusion layer is 200 Ω / sq to 350 Ω / sq.

3. The solar cell according to claim 1, characterized in that The thickness of the N-type diffusion layer is 0.05 μm to 0.5 μm.

4. The solar cell according to claim 1, wherein The doping concentration of the N-type conductive element in the N-type diffusion layer is 5×10 18 atoms / cm 3 ~1×10 20 atoms / cm 3 .

5. The solar cell according to claim 1, wherein, The N-type diffusion layer covered by the first passivated contact structure is 0.05 μm to 0.15 μm thicker than the N-type diffusion layer not covered by the first passivated contact structure.

6. The solar cell according to claim 1, wherein The thickness of the N-type doped polysilicon layer is 30 nm to 200 nm.

7. The solar cell according to claim 1, wherein The thickness of the P-type heavily doped polysilicon layer is 200 nm to 400 nm.

8. The solar cell according to claim 1, characterized in that, The diameter of the via hole is 50 nm to 500 nm.

9. The solar cell according to claim 1, characterized in that, The number of the through holes is 1×10 4 holes / cm 2 ~1.6×10 8 holes / cm 2 .

10. The solar cell according to claim 1, wherein The width of the first passivated contact structure is 20 μm to 110 μm.

11. The solar cell according to claim 1, characterized in that, The ratio of the number of grid lines of the second electrode to the number of grid lines of the first electrode is 1.2 to 1.6:

1.

12. The solar cell according to any one of claims 1 to 11, characterized in that, The first functional layer includes a first passivation layer disposed close to the N-type diffusion layer and a first antireflection layer disposed away from the N-type diffusion layer.

13. The solar cell according to claim 12, wherein, The first passivation layer is a silicon oxide layer, and the first antireflection layer is at least one of a silicon nitride layer, a silicon oxynitride layer or a silicon oxide layer.

14. The solar cell according to any one of claims 1 to 11, characterized in that, The second functional layer includes a second passivation layer disposed close to the P-type heavily doped polysilicon layer and a second antireflection layer disposed away from the P-type heavily doped polysilicon layer.

15. The solar cell according to claim 14, wherein The second passivation layer is an aluminum oxide layer, and the second antireflection layer is at least one of a silicon nitride layer, a silicon oxynitride layer.

16. A method for preparing a solar cell according to any one of claims 1 to 15, characterized in that, The method for preparing the solar cell includes the following steps: Forming an N-type diffusion layer: performing a diffusion treatment of N-type conductive elements on the light-receiving surface of the N-type substrate to obtain the N-type diffusion layer; Forming a passivated contact structure: sequentially disposing the first dielectric layer and the N-type doped amorphous silicon layer on a side of the N-type diffusion layer away from the N-type substrate, and sequentially disposing the second dielectric layer and the P-type doped amorphous silicon layer on the backlight surface of the N-type substrate; Patterned processing: after printing a patterned paste in a preset area of the N-type doped amorphous silicon layer, performing etching and cleaning to remove the first dielectric layer and the N-type doped amorphous silicon layer not covered by the preset area, and then removing the paste, and retaining the first dielectric layer and the N-type doped amorphous silicon layer covered by the preset area; Annealing: Anneal the N-type substrate after patterning, so that the N-type doped amorphous silicon layer is transformed into an N-type doped polycrystalline silicon layer, and the P-type doped amorphous silicon layer is transformed into a P-type heavily doped polycrystalline silicon layer. The first dielectric layer and the N-type doped polycrystalline silicon layer form the first passivated contact structure, the second dielectric layer and the P-type heavily doped polycrystalline silicon layer form the second passivated contact structure, and a PN junction is formed between the N-type substrate and the P-type heavily doped polycrystalline silicon layer; Post-treatment: Form the first functional layer on the N-type diffusion layer and the patterned N-type doped polycrystalline silicon layer, form the second functional layer on the P-type heavily doped polycrystalline silicon, fabricate the first electrode on the first functional layer, so that the first electrode penetrates the first functional layer to form an ohmic contact with the N-type doped polycrystalline silicon layer, fabricate the second electrode on the second functional layer, so that the second electrode penetrates the second functional layer to form an ohmic contact with the P-type heavily doped polycrystalline silicon layer.

17. The manufacturing method of the solar cell according to claim 16, characterized in that, The steps of forming the N-type diffusion layer are as follows: Using nitrogen gas carrying a gas source containing the N-type conductive element and oxygen to perform diffusion propulsion of the N-type conductive element on the light-receiving surface of the N-type substrate, forming the N-type diffusion layer with a thickness of 0.05 μm to 0.5 μm, the sheet resistance of the N-type diffusion layer being 200 Ω / sq to 350 Ω / sq, and the doping concentration of the N-type conductive element in the N-type diffusion layer being 5×10 18 atoms / cm 3 ~1×10 20 atoms / cm 3 .

18. The manufacturing method of the solar cell according to claim 17, characterized in that, The step of forming the passivated contact structure includes: Pickling: Use a first acid agent to pickle the N-type substrate after diffusion treatment to remove the silicon glass doped with the N-type conductive element formed on the light-receiving surface and the backlight surface of the N-type substrate; Deposit the first dielectric layer, the front intrinsic layer, the front doping layer doped with the N-type conductive element, and the front mask layer on the N-type diffusion layer in sequence; Alkaline polishing: Use a second acid agent to remove the front mask layer plated around to the backlight surface, then use a first alkaline agent to polish the backlight surface of the N-type substrate, and remove the front doping layer, the front intrinsic layer, and the first dielectric layer plated around to the backlight surface and the edge; Deposit the second dielectric layer, the back intrinsic layer, the back doping layer doped with a P-type conductive element, and the back mask layer on the backlight surface in sequence.

19. The method for manufacturing a solar cell according to claim 18, wherein The front doping layer includes a first front doping sub-layer and a second front doping sub-layer, and both the first front doping sub-layer and the second front doping sub-layer are doped with the N-type conductive element.

20. The manufacturing method of the solar cell according to claim 18, characterized in that, The back doping layer includes a first back doping sub-layer and a second back doping sub-layer, and both the first back doping sub-layer and the second back doping sub-layer are doped with the P-type conductive element.

21. The manufacturing method of the solar cell according to claim 18, wherein, The step of patterning includes: Printing: Print a patterned acid-resistant slurry on the front mask layer, and the patterned area of the acid-resistant slurry corresponds to the preset area, and dry it to cure the acid-resistant slurry; Cleaning: First use a third acid agent to etch and remove the front mask layer not covered by the preset area, then use a second alkaline agent to etch and remove the acid-resistant slurry, and remove the front doping layer, the front intrinsic layer, and the first dielectric layer not covered by the preset area in the light-receiving surface, and then use a fourth acid agent to remove the front mask layer and the back mask layer.

22. The manufacturing method of the solar cell according to claim 21, characterized in that, In the step of printing, the width of the printed patterned acid-resistant slurry is 20 μm to 110 μm, the drying temperature after printing is 150 °C to 250 °C, and the drying time is 8 s to 12 s.

23. The method for preparing a solar cell according to claim 16, wherein, In the annealing step, the annealing conditions are as follows: in an atmosphere with a volume ratio of nitrogen to oxygen of 1:1 to 8:1, at a temperature of 850 °C to 1000 °C, and annealed for 90 min to 150 min.

24. The method for preparing a solar cell according to claim 16, wherein, In the post-treatment step, the post-treatment step includes: sequentially forming a silicon oxide layer as the first passivation layer and depositing a silicon nitride layer and / or a silicon oxynitride layer as the first antireflection layer on the N-type diffusion layer and the patterned N-type doped polysilicon layer, so that the first passivation layer and the first antireflection layer form the first functional layer; Sequentially forming an aluminum oxide layer as the second passivation layer and depositing a silicon nitride layer and / or a silicon oxynitride layer as the second antireflection layer on the P-type heavily doped polysilicon layer, so that the second passivation layer and the second antireflection layer form the second functional layer.

25. A photovoltaic module, characterized in that, The photovoltaic module includes the solar cell according to any one of claims 1 to 15, or the photovoltaic module includes the solar cell prepared by the preparation method of the solar cell according to any one of claims 16 to 24.

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