Communication method, apparatus, device, and storage medium

Abstract

The present application provides a communication method, an apparatus, a device, and a storage medium. The method comprises: on the basis of a 16*32 base matrix, determining a check matrix corresponding to a target code length, and sending first information obtained by encoding on the basis of the check matrix, wherein a first base matrix supporting a first code length is associated with a second base matrix supporting a second code length, for example, the position of a cyclic shift matrix represented by a first element of the first base matrix is the same as the position of a cyclic shift matrix represented by a first element in the second base matrix. For determination of a check matrix by a communication device, the processing complexity is reduced, thereby improving the data transmission reliability of a system. Further, in embodiments of the present application, in the check matrix determined on the basis of the 16*32 base matrix, the first element in the 17th column is zero, and the xth element and the 16th element in the 17th column are the same non-zero element, x being an integer greater than 1 and less than 16, thereby improving the encoding flexibility.

Description

Communication methods, devices, equipment and storage media

[0001] This application claims priority to Chinese Patent Application No. 202410042932.6, filed on January 10, 2024, entitled "Communication Method, Apparatus, Device and Storage Medium", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a communication method, apparatus, device, and storage medium. Background Technology

[0003] The Institute of Electrical and Electronics Engineers (IEEE) 802.11n / ac / ax / be and other wireless local area network (WLAN) transmission standards primarily focus on improving user experience in high-bandwidth scenarios (such as 60 GHz), including increasing average user throughput and energy efficiency of battery-powered devices. High-bandwidth scenarios require high-speed and reliable transmission of data, video, and other services on limited frequency and power resources, thus necessitating highly reliable and efficient channel coding and decoding schemes.

[0004] In the field of channel coding, concatenated codes (such as Turbo codes) and low-density parity-check (LDPC) codes are currently the two most mature and widely used channel coding methods, both of which have performance close to the Shannon limit. Compared with concatenated codes, LDPC codes have the following advantages: good error performance without the need for a deep interleaver; better frame error rate performance; significantly reduced error levels; decoding is not grid-based; supports parallel decoding; and has low decoding latency. Therefore, LDPC codes have become the standard channel coding scheme for low-frequency short-range WLAN communication systems such as IEEE 802.11n / ac / ax.

[0005] How to further improve the decoding performance of LDPC codes is an urgent problem to be solved. Summary of the Invention

[0006] This application provides a communication method, apparatus, device, and storage medium to improve the decoding performance of LDPC codes, thereby improving the transmission reliability of wireless transmission systems.

[0007] Firstly, this application provides a communication method. The subject executing this method may be a first communication device, which may include a Wi-Fi device, or a chip or functional module disposed in the Wi-Fi device, etc.

[0008] For example, the method includes: a first communication device determining a parity check matrix corresponding to a target code length based on a 16*32 base matrix, and sending first information encoded based on the parity check matrix, wherein the first base matrix supporting the first code length is associated with the second base matrix supporting the second code length, such that the position of the cyclic displacement matrix represented by the first element of the first base matrix is ​​the same as the position of the cyclic displacement matrix represented by the first element of the second base matrix. For the communication device to determine the parity check matrix, the processing complexity is reduced, thereby improving the data transmission reliability of the system.

[0009] Furthermore, in the embodiments of this application, in the parity check matrix determined based on the 16*32 base matrix, the first element in the 17th column is zero, the xth element in the 17th column and the 16th element are the same non-zero element, and x is an integer greater than 1 and less than 16, which improves the flexibility of encoding.

[0010] Secondly, this application provides a communication method. The subject executing this method may be a second communication device, which may include a Wi-Fi device, or a chip or functional module disposed in the Wi-Fi device, etc.

[0011] For example, the method includes: a second communication device receiving first information, the first information being encoded based on a parity check matrix of a target code length, and determining a parity check matrix based on a 16*32 base matrix, the base matrix including multiple first elements, the first elements corresponding to a cyclic shift matrix, the position of the first element in the first base matrix being the same as the position of the first element in the second base matrix, the first base matrix being used to determine the parity check matrix corresponding to the first code length, the second base matrix being used to determine the parity check matrix corresponding to the second code length, the target code length including the first code length or the second code length, the first element in the 17th column of the base matrix being zero, the xth element in the 17th column of the base matrix being the same non-zero element as the 16th element, and x being an integer greater than 1 and less than 16.

[0012] Combining the first or second aspect, in one possible implementation, the basis matrix can be represented as:

[0013] or

[0014] Where 'a' indicates that the corresponding element position has a z*z cyclic shift identity matrix, z is the expansion factor, and '-' indicates a matrix of all zeros.

[0015] In the two examples of the first element position above, the row weight and column weight of the basis matrix are different. When the row weight and column weight are different, the decoding complexity is different. Therefore, in this implementation, the above two possible basis matrices are proposed for different decoding complexities.

[0016] Combining the first or second aspect, in one possible implementation, z is 10, and the basis matrix can be represented as:

[0017] or

[0018] Combining the first or second aspect, in one possible implementation, z is 20, and the basis matrix can be represented as:

[0019] or

[0020] Combining the first or second aspect, in one possible implementation, z is 40, and the basis matrix can be represented as:

[0021] or

[0022] Combining the first or second aspect, in one possible implementation, z is 60, and the basis matrix can be represented as:

[0023] or

[0024] Combining the first or second aspect, in one possible implementation, z is 80, and the basis matrix can be represented as:

[0025] or

[0026] Thirdly, embodiments of this application provide a first communication device for executing the method in the first aspect or any possible implementation. The first communication device includes a module for executing the method in the first aspect or any possible implementation.

[0027] Fourthly, embodiments of this application provide a second communication device for executing the method in the second aspect or any possible implementation. The second communication device includes a module for executing the method in the second aspect or any possible implementation.

[0028] Fifthly, embodiments of this application provide a first communication device, which includes a processor for executing the method described in the first aspect or any possible implementation thereof. The processor executes a program stored in a memory, and when the program is executed, the method described in the first aspect or any possible implementation thereof is executed.

[0029] In one possible implementation, the memory is located outside the aforementioned first communication device.

[0030] In one possible implementation, the memory is located within the aforementioned first communication device.

[0031] In this embodiment, the processor and memory can also be integrated into a single device, that is, the processor and memory can be integrated together. For example, the first communication device can be a chip.

[0032] In one possible implementation, the first communication device further includes a transceiver for receiving or sending information.

[0033] Sixthly, embodiments of this application provide a second communication device, which includes a processor for executing the methods described in the second aspect or any possible implementation thereof. The processor executes a program stored in a memory, and when the program is executed, the methods described in the second aspect or any possible implementation thereof are executed.

[0034] In one possible implementation, the memory is located outside the aforementioned second communication device.

[0035] In one possible implementation, the memory is located within the aforementioned second communication device.

[0036] In this embodiment, the processor and memory can also be integrated into a single device, i.e., the processor and memory can be integrated together. For example, the second communication device can be a chip.

[0037] In one possible implementation, the second communication device further includes a transceiver for receiving or sending information.

[0038] In a seventh aspect, embodiments of this application provide a first communication device, the first communication device including a logic circuit and an interface, the logic circuit and the interface being coupled; the interface is used for inputting and / or outputting information, and the logic circuit is used for performing the method as described in the first aspect or any possible implementation.

[0039] Eighthly, embodiments of this application provide a second communication device, the second communication device including logic circuitry and an interface, the logic circuitry and the interface being coupled; the interface being used for inputting and / or outputting information, and the logic circuitry being used for performing the method described in the second aspect or any possible implementation thereof.

[0040] Ninthly, embodiments of this application provide a computer-readable storage medium for storing a computer program that, when run on a computer, causes the methods shown in any of the first to second aspects or any possible implementation thereof to be executed.

[0041] In a tenth aspect, embodiments of this application provide a computer program product that, when run on a computer, causes the methods shown in any of the first to second aspects or any possible implementations described above to be executed.

[0042] In one aspect, embodiments of this application provide a computer program that, when run on a computer, executes the methods shown in any of the first to second aspects or any possible implementations described above.

[0043] In a twelfth aspect, embodiments of this application provide a communication system comprising a first communication device and / or a second communication device, wherein the first communication device is configured to perform the method shown in the first aspect or any possible implementation thereof, and the second communication device is configured to perform the method shown in the second aspect or any possible implementation thereof.

[0044] The beneficial effects of the contents of the second to twelfth aspects and their possible implementations can be found in the first aspect and the beneficial effects of its possible implementations, and will not be repeated here. Attached Figure Description

[0045] Figure 1a is a schematic diagram of a matrix prototype of a reference verification matrix provided in an embodiment of this application;

[0046] Figure 1b is a schematic diagram of a CPM provided in an embodiment of this application;

[0047] Figure 2a is a schematic diagram of the architecture of a communication system provided in an embodiment of this application;

[0048] Figure 2b is a schematic diagram of the architecture of a communication system provided in an embodiment of this application;

[0049] Figure 2c is a schematic diagram of the architecture of a communication system provided in an embodiment of this application;

[0050] Figure 3 is a schematic diagram of the interaction flow of a communication method provided in an embodiment of this application;

[0051] Figure 4 is a partial schematic diagram of a shortening operation in LDPC encoding provided in an embodiment of this application;

[0052] Figure 5a is a schematic diagram of the position of a base matrix element provided in an embodiment of this application;

[0053] Figure 5b is a schematic diagram of another basis matrix element position provided in an embodiment of this application;

[0054] Figure 6a is a schematic diagram of a verification matrix provided in an embodiment of this application;

[0055] Figure 6b is a schematic diagram of a factor graph provided in an embodiment of this application;

[0056] Figure 7a is a schematic diagram of decoding performance provided in an embodiment of this application;

[0057] Figure 7b is a schematic diagram of decoding performance provided in an embodiment of this application;

[0058] Figure 7c is a schematic diagram of a decoding performance provided in an embodiment of this application;

[0059] Figure 7d is a schematic diagram of a decoding performance provided in an embodiment of this application;

[0060] Figure 8a is a schematic diagram of decoding performance provided in an embodiment of this application;

[0061] Figure 8b is a schematic diagram of a decoding performance provided by an embodiment of this application;

[0062] Figure 8c is a schematic diagram of a decoding performance provided in an embodiment of this application;

[0063] Figure 9a is a schematic diagram comparing the performance of a verification matrix provided in an embodiment of this application;

[0064] Figure 9b is a schematic diagram comparing the performance of a verification matrix provided in an embodiment of this application;

[0065] Figure 9c is a schematic diagram showing the performance comparison of a verification matrix provided in an embodiment of this application;

[0066] Figure 9d is a schematic diagram showing the performance comparison of a verification matrix provided in an embodiment of this application;

[0067] Figure 10 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0068] Figure 11 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0069] Figure 12 is a schematic diagram of the structure of a communication device provided in an embodiment of this application. Detailed Implementation

[0070] To facilitate understanding of the technical solution of this application, the application will be further described below with reference to the accompanying drawings.

[0071] The terms "first" and "second," etc., used in the specification, claims, and drawings of this application are used only to distinguish different objects and not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0072] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0073] In this application, "at least one (item)" refers to one or more, "more than one" refers to two or more, "at least two (items)" refers to two or three or more, and "and / or" is used to describe the relationship between related objects, indicating that there can be three relationships. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. "Or" indicates that there can be two relationships, such as only A exists and only B exists; when A and B are not mutually exclusive, it can also mean that there are three relationships, such as only A exists, only B exists, and both A and B exist simultaneously. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items. For example, at least one (item) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c".

[0074] The LDPC code used in the IEEE 802.11ac / ax standard is a quasi-cyclic (QC) LDPC (QC-LDPC) code. QC-LDPC codes are a widely used type of structured LDPC code. Due to the unique structure of its parity-check matrix, encoding can be implemented using a simple feedback shift register, which can effectively solve the encoding complexity problem of LDPC codes.

[0075] Currently, the standard adopts 12 LDPC code parity-check matrices, with three code lengths N: N=648, N=1296, or N=1944. Each code length supports four different coding rates: 1 / 2, 2 / 3, 3 / 4, and 5 / 6. The matrix prototypes of the parity-check matrices are different for each code length and code rate. The parity bit portion (the matrix corresponding to the parity bits, or parity square matrix, shown below) of the 12 parity-check matrices with different code lengths and codes has the same structure. For example, the code rate can be determined by the modulation and coding scheme (MCS) adaptively selected by the transmission system based on the link. Therefore, in traditional WLANs, the communication device can select one parity-check matrix from the 12 matrices based on the given code length and code rate. The aforementioned identical structure can be understood as the parity bit portion in the matrix prototypes of different parity-check matrices in Figure 1a having all elements in the first row and first column being 1, and all elements in the last row and first column being 1.

[0076] Figure 1a shows the matrix prototypes of the LDPC code parity-check matrix at different code rates with a code length N = 1944. In Figure 1a, "-" represents a Z*Z all-zero matrix, "0" represents a Z*Z identity matrix, and the non-zero elements represent the circulant permutation matrix (CPM) of the Z*Z identity matrix. For example, if CPM is represented by P... i The expression 'i' represents the cyclic shift value, the number of bits in the identity matrix cyclically shifted to the right, the CPM coefficient, or an element greater than or equal to 0 in the matrix prototype of the parity check matrix. The specific name of 'i' is not limited in this application. 'i' is a non-negative integer, such as 0 ≤ i ≤ Z-1. When i = 0, the CPM can be understood as a Z*Z identity matrix, or a CPM with a cyclic shift value of 0. For example, Z = N / 24. The aforementioned "24" can be the same as the number of columns in the matrix prototype of the parity check matrix in the IEEE 802.11ac / ax standard. For IEEE 801.11ac / ax, regardless of whether the code length N = 648, N = 1296, or N = 1944, the number of columns in the matrix prototype of the parity check matrix is ​​always 24.

[0077] For example, taking element "1" (i.e., i = 1) in Figure 1a as an example, element 1 can be expanded into a CPM of 81*81 (1944 / 24 = 81). This CPM can be obtained by cyclically shifting the identity matrix one bit to the right, as shown below:

[0078] For example, taking a 4*4 CPM as an example, Figure 1b shows the CPM when i=0, i=1, i=2, and i=3, respectively. The CPM shown in Figure 1b is only an example. The CPM of other Z*Z identity matrices in this application embodiment can be obtained by referring to the principle shown in Figure 1a or 1b to obtain the final P. i This will not be elaborated upon here.

[0079] As mentioned earlier, LDPC codes have been widely used in WLAN standards to improve the transmission reliability of wireless transmission systems. The new IEEE 802.15ab standard, compared to the IEEE 802.15.az standard, can introduce new LDPC coding techniques to further enhance the data transmission reliability of the system. For example, UWB systems may simultaneously transmit short, medium, and long packets, such as 20, 100, and 1500 bytes. If the IEEE 802.11n LDPC code is reused in a UWB system, three different LDPC parity-check matrices are needed for a single code rate (e.g., 1 / 2 code rate) to achieve three code lengths (e.g., 648, 1296, and 1944 bits). Simultaneously implementing three parity-check matrices would result in high complexity of the system's channel coding module, failing to meet the high requirements of low power consumption, low latency, and low implementation complexity for LDPC channel coding in next-generation UWB transmission.

[0080] Therefore, this application provides a new LDCP code that can support different code lengths. In this application, a first base matrix supporting a first code length is associated with a second base matrix supporting a second code length. For example, the position of the cyclic shift matrix represented by "0" or non-zero elements in the first base matrix is ​​the same as the position of the cyclic shift matrix represented by "0" or non-zero elements in the second base matrix. This reduces the processing complexity for communication devices in determining the parity check matrix, thereby improving the data transmission reliability of the system.

[0081] Furthermore, in the embodiments of this application, in the parity check matrix determined based on the 16*32 base matrix, the first element in the 17th column is zero, the xth element in the 17th column and the 16th element are the same non-zero element, and x is an integer greater than 1 and less than 16, which improves the flexibility of encoding.

[0082] In this application embodiment, the matrices shown below can be referred to as parity-matrices prototypes, matrix prototypes of the parity-matrices, matrix prototypes for codeword block length N, parent matrix, or base matrix, etc. The specific names of the matrices involved in this application embodiment are not limited. Generally, a matrix including elements 0 and 1 after expansion based on Z and the cyclic shift value i is called a parity-matrices. Therefore, the matrices shown below can also be called matrices before CPM expansion, etc. The matrices shown in Example 1 or Example 2 below can be called base matrices of the parity-matrices, and the matrices expanded based on the elements of the matrices shown in Example 1 or Example 2 can be called parity-matrices. For the specific expansion method, please refer to the above description regarding Figure 1a. The specific content of the expanded parity-matrices will not be listed in detail in this application embodiment.

[0083] The code length in this application embodiment can also be called a codeword block length, etc. The specific name for the code length is not limited in this application embodiment. Z in this application embodiment can be called a subblock size, a spread factor, or a lift factor, etc. The specific name for Z is not limited in this application embodiment. For ease of description, Z will be referred to as the spread factor in the following explanation.

[0084] Generally, Z = N / 24. However, as standards evolve, the method for calculating Z may change, and this application does not limit this. For ease of understanding, different letter parameters are used to represent different meanings in this application, such as N representing code length, Z representing the spreading factor, R representing the code rate, K representing the number of information bits, and E representing the number of parity bits. However, the letter parameters shown in this application are merely examples and should not be construed as limiting the application.

[0085] The following describes the communication system involved in the embodiments of this application.

[0086] The technical solutions provided in this application can be applied to wireless local area network (WLAN) systems, such as Wi-Fi. The methods provided in this application can also be applied to the IEEE 802.11 series of protocols, such as the 802.11be protocol, the 802.11bn protocol, or next-generation protocols of the 802.11bn protocol, etc., and will not be listed exhaustively. The technical solutions provided in this application can also be applied to wireless personal area networks (WPANs) based on millimeter wave (MMW) and ultra-wideband (UWB) technologies. The methods provided in this application can also be applied to the IEEE 802.15 series of protocols, such as the 802.15.4a protocol, the 802.15.4z protocol, or the 802.15.4ab protocol, or a future generation of UWB WPAN protocols, etc., and will not be listed exhaustively. The technical solutions provided in this application can also be applied to the following communication systems, such as Internet of Things (IoT) systems, vehicle-to-everything (V2X, where X can represent anything), device-to-device (D2D), narrowband Internet of Things (NB-IoT) systems, long-term evolution (LTE) systems, 5th-generation (5G) communication systems, and new communication systems emerging in future communication development. For example, V2X can include vehicle-to-vehicle (V2V), vehicle-to-infrastructure (V2I), vehicle-to-pedestrian (V2P), or vehicle-to-network (V2N) communication.

[0087] WLAN systems can provide high-speed, low-latency transmission. As WLAN application scenarios continue to evolve, WLAN systems will be applied to more scenarios or industries, such as the Internet of Things industry, the Internet of Vehicles industry, the banking industry, enterprise offices, stadiums and exhibition halls, concert halls, hotel rooms, dormitories, hospital wards, classrooms, shopping malls, squares, streets, production workshops and warehouses, etc. Of course, devices that support WLAN communication or sensing (such as access points or sites) can be sensor nodes in smart cities (such as smart water meters, smart electricity meters, and smart air monitoring nodes), smart devices in smart homes (such as smart cameras, projectors, displays, televisions, speakers, refrigerators, and washing machines), nodes in the Internet of Things (IoT), entertainment terminals (such as wearable devices for augmented reality (AR) and virtual reality (VR), smart devices in smart offices (such as printers, projectors, loudspeakers, and speakers), vehicle-to-everything (V2X) devices, infrastructure in daily life scenarios (such as vending machines, self-service navigation kiosks in supermarkets, self-service checkout machines, and self-service ordering machines), and equipment in large sports and music venues.

[0088] UWB technology boasts advantages such as low system complexity, low transmitted signal power spectral density, insensitivity to channel fading, low interception capability, and high positioning accuracy, making it particularly suitable for high-speed wireless access in dense multipath environments such as indoor spaces. The method provided in this application can be implemented by a communication device in a wireless communication system. This communication device can be any device involved in the UWB system. For example, the communication device can include, but is not limited to, communication servers, routers, switches, bridges, computers, and mobile phones that support UWB technology. Alternatively, the communication device can include user equipment (UE), which may include various handheld devices, in-vehicle devices (such as automobiles or components installed in automobiles), wearable devices, Internet of Things (IoT) devices, computing devices, or other processing devices connected to a wireless modem that support UWB technology, etc., and will not be listed exhaustively here. Another example is that the communication device can include a central control point, such as a personal area network (PAN) or a PAN coordinator. The PAN coordinator or PAN can be a mobile phone, in-vehicle device, anchor, tag, or smart home device. For example, the communication device may include a chip, which may be located in a communication server, router, switch or terminal device, etc., and will not be listed here.

[0089] In one possible implementation, the method provided in this application embodiment can be implemented by a communication device in a communication system. For example, the communication device can be an access point (AP) or a station (STA).

[0090] An Access Point (AP) is a device with wireless communication capabilities that supports communication or sensing using WLAN protocols. It has the ability to communicate or sense other devices in a WLAN network (such as non-access point stations (non-AP STAs) or other access points), and can also communicate or sense other devices. Alternatively, an access point acts as a bridge connecting wired and wireless networks, primarily connecting various wireless network clients together and then connecting the wireless network to an Ethernet network. In a WLAN system, an access point can be called an Access Point Station (AP STA). This wireless communication device can be a complete device or a chip, processing system, or functional module installed within a complete device. Devices with these chips, processing systems, or functional modules can implement the methods and functions of the embodiments described in this application under the control of the chips, processing systems, or functional modules. The AP in the embodiments of this application is a device that provides services to non-AP STAs and can support 802.11 series protocols or subsequent protocols. For example, an access point can be an access point for a terminal (such as a mobile phone) to enter a wired (or wireless) network, mainly deployed in homes, buildings, and parks, with a typical coverage radius of tens to hundreds of meters. Of course, it can also be deployed outdoors. Another example is that an AP can be a communication entity such as a communication server, router, switch, or bridge; APs can include various forms of macro base stations, micro base stations, and repeater stations. Of course, an AP can also be a chip, processing system, or module within the above-mentioned devices, thereby implementing the methods and functions of the embodiments of this application.

[0091] A Station-Style (STA) is a device with wireless communication capabilities that supports communication or sensing using the WLAN protocol. It has the ability to communicate or sense other non-AP STAs or access points in a WLAN network. In a WLAN system, a station can be called a non-access point station (non-AP STA). For example, an STA is any user communication device that allows a user to communicate or sense with an AP and thus communicate with the WLAN. This wireless communication device can be a complete device, or it can be a chip, processing system, or functional module installed in a complete device. Devices with these chips, processing systems, or functional modules can implement the methods and functions of the embodiments of this application under the control of the chips, processing systems, or functional modules. For example, an STA can be a wireless communication chip, a wireless sensor, or a wireless communication terminal, and can also be referred to as a user. Furthermore, an STA can be a mobile phone supporting Wi-Fi communication, a tablet computer supporting Wi-Fi communication, a set-top box supporting Wi-Fi communication, a smart TV supporting Wi-Fi communication, a smart wearable device supporting Wi-Fi communication, an in-vehicle communication device supporting Wi-Fi communication, and a computer supporting Wi-Fi communication. Of course, STA can also be a chip, processing system, or module in the various types of devices described above, thereby implementing the methods and functions of the embodiments of this application.

[0092] For example, the communication systems to which the methods provided in this application can be applied may include access points and stations. For instance, this application can be applied to scenarios of communication or sensing between APs and STAs, between APs, or between STAs in a WLAN, and this application does not limit this. Optionally, an AP can communicate or sense with a single STA, or an AP can communicate or sense with multiple STAs simultaneously. Specifically, communication or sensing between an AP and multiple STAs can be further divided into downlink transmission where the AP simultaneously sends signals to multiple STAs, and uplink transmission where multiple STAs send signals to the AP. The communication protocols between APs and STAs, between APs, and between STAs can support WLAN communication protocols, which may include IEEE 802.11 series protocols, such as the 802.11bn protocol, and of course, protocols after 802.11bn are also applicable.

[0093] Figure 2a is a schematic diagram of the architecture of a communication system provided in an embodiment of this application. The communication system may include one or more APs and one or more STAs. Figure 2a shows two access points, such as AP1 and AP2, and three stations, such as STA1, STA2, and STA3. As an example, the method provided in this embodiment can be applied to data communication or sensing between an AP and one or more STAs, such as the communication between AP1 and STA1 shown in Figure 2a, the communication between AP and STA shown in Figure 2b, the communication between AP1 and STA1 and STA2 shown in Figure 2a, and the communication between AP and STA1, STA2, and STA3 shown in Figure 2c. As another example, the method provided in this embodiment can be applied to communication between APs, such as the communication between AP1 and AP2 shown in Figure 2a. As yet another example, the method provided in this embodiment can be applied to communication between STAs, such as the communication between STA2 and STA3 shown in Figure 2a.

[0094] Figures 2a-2c use STA (Mobile Phone) and AP (Router) as examples and do not imply limitation on the types of APs and STAs in the embodiments of this application. Furthermore, the number of APs and STAs shown in Figures 2a-2c is merely an example; in actual implementations, the number of APs or STAs may be more or less, and this application does not limit this.

[0095] From the perspectives of transmitting and receiving signals, the first communication device described below can be understood as a communication device that transmits signals, and the second communication device can be understood as a communication device that receives signals. Alternatively, the first communication device can also be called a transmitter, and the second communication device can also be called a receiver. In the embodiments of this application, the signal can be a signal obtained after processing the encoded sequence. From the perspective of different devices, as an example, the first communication device and the second communication device can be Wi-Fi chips, functional modules, or processing systems, etc., installed in different Wi-Fi devices. As another example, the first communication device can be an AP, and the second communication device can be a non-AP STA. As yet another example, the first communication device and the second communication device can both be non-AP STAs or both be APs. As yet another example, the first communication device can be a non-AP STA, and the second communication device can be an AP. As yet another example, at least one of the first communication device and the second communication device can be a multi-link device (MLD), etc., which will not be listed one by one in the embodiments of this application. For example, a multi-link device (MLD) refers to a device that simultaneously has multiple stations (such as APs or non-AP STAs), each operating on different frequency bands or channels. A multi-link device includes multiple affiliated stations, which can be physical or logical stations. Each station can operate on a link, a frequency band, or a channel, etc. The aforementioned affiliated stations can be APs or non-AP STAs. A multi-link device (such as a non-AP MLD or AP MLD) can be a communication device with wireless communication capabilities. This communication device can be a complete device, or it can be a chip, processing system, or module installed in a complete device. Devices with these chips, processing systems, or modules installed can implement the methods and functions of the embodiments of this application under the control of these chips, processing systems, or modules. A multi-link device can implement wireless communication by following the 802.11 series of protocols, thereby enabling communication with other devices. Other devices shown herein may or may not be multi-link devices. The frequency bands in which multi-link devices can operate may include, but are not limited to, sub 1GHz, 2.4GHz, 5GHz, 6GHz, etc., which will not be listed here.

[0096] This application describes the method provided by the first communication device and the second communication device from both sides. However, during the transmission of signals, the first communication device and the second communication device can also forward the signals through other devices, such as forwarding the signals between the first communication device and the second communication device through a forwarding device. This application does not limit other devices besides the first communication device and the second communication device.

[0097] The communication method provided in the embodiments of this application will now be described with reference to the accompanying drawings.

[0098] Figure 3 is a schematic diagram of the interaction flow of a communication method provided in an embodiment of this application. Referring to Figure 3, the method 300 includes at least some of the following steps S310 to S340:

[0099] S310, the first communication device acquires the information bit sequence.

[0100] This information bit sequence can be a bit sequence containing information. For example, the length of the information bit sequence is N², or the number of bits in the information bit sequence is N². N² is a positive integer. These N² bits can include K information bits, also called K data bits or K payload bits. K is a positive integer. N² can be an integer greater than or equal to K. For example, when N² is greater than K, the information bit sequence can also include (N²-K) zeros. For a related explanation of the "0" shown here, please refer to the description of the shortening operation in Figure 4 below; it will not be detailed here.

[0101] The value of N2 mentioned above can be related to the code length and code rate. If the length of the encoded sequence in step 302 below is N1, then N2 = N1 * R, where R is the encoding code rate of the information bit sequence. N1 shown here can also be called the code length corresponding to the parity check matrix.

[0102] In one possible implementation, the method shown in Figure 3 may also include:

[0103] The first communication device acquires the code length N1. Optionally, the code length N1 can be 320, 640, 1280, 1920, 2560 bits, etc.

[0104] In one possible implementation, the method shown in Figure 3 may also include:

[0105] The first communication device acquires the code rate R.

[0106] In a WLAN system, different code lengths and code rates can correspond to different parity check matrices. Therefore, the code rate R can be obtained before the first communication device performs LDPC encoding. After obtaining the code rate R, the first communication device can select the parity check matrix based on the code rate R and the code length N1. The code rate R can be determined based on the link adaptive selection MCS. For example, the code rate R can be determined based on the current channel information. The specific method for determining the code rate R is not limited in the embodiments of this application. As an example, the MCS can be issued by the AP. As another example, the MCS can be determined by the first communication device, etc. For example, the first communication device sends the MCS to the second communication device, and the second communication device receives the MCS and obtains the code rate R based on the MCS. Or, the second communication device sends the MCS to the first communication device, and the first communication device receives the MCS and obtains the code rate R based on the MCS. The specific interaction process of the MCS is not limited in the embodiments of this application.

[0107] For example, the bit rate R can be preset, such as by a protocol or stored in the first communication device; or the bit rate R can be pre-configured, such as issued by the AP; or the bit rate R can be a basic bit rate, for example, in a UWB system, the basic bit rate is 1 / 2, and other bit rates can be obtained by shortening or punching.

[0108] For example, R can be any of the following: 1 / 2, 2 / 3, 3 / 4, 5 / 6. Of course, as standards evolve, R may take other values, and this application embodiment does not limit this.

[0109] S320, the first communication device performs LDPC encoding on the information bit sequence based on the parity check matrix to obtain the first information.

[0110] The parity check matrix is ​​determined based on a 16*32 basis matrix. This basis matrix includes multiple first elements, each corresponding to a z*z cyclic shift matrix, meaning elements in the basis matrix with values ​​of zero or non-zero. The basis matrix also includes multiple second elements, which do not correspond to the cyclic shift matrix; in other words, the second elements represent a z*z all-zero matrix, where z is a positive integer. This application does not limit the expression of the second elements; for example, the second elements can be expressed using "-", "0", or other symbols or values. Since the second elements represent a z*z all-zero matrix, second elements at different positions in the basis matrix can have the same expression; for example, each second element in the basis matrix can be represented as "-".

[0111] As previously mentioned, even with the same code rate, the base matrices corresponding to parity check matrices of different code lengths are different, including the position and value of the first element in the base matrix. However, in this embodiment, when the base matrix is ​​used to determine the parity check matrix corresponding to different code lengths, the position of the first element in the base matrix remains unchanged. For example, the first base matrix is ​​used to determine the parity check matrix of the first code length, and the second base matrix is ​​used to determine the parity check matrix of the second code length. The first element in the first base matrix and the first element in the second base matrix have the same position. For example, the positions of the first elements in both the first and second base matrices can be seen in Example 1 below, and in Example 2 below. The dimensions z of the cyclic shift matrices corresponding to the first elements at the same position in the first and second base matrices are different. In other words, the first base matrix is ​​expanded based on a z1*z1 cyclic shift matrix to obtain the parity check matrix of the first code length, and the second base matrix is ​​expanded based on a z2*z2 cyclic shift matrix to obtain the parity check matrix of the second code length. z1 and z2 are unequal positive integers. Optionally, the values ​​of the first elements at the same position in the first and second base matrices can be different or the same. For example, the first code length could be 320 bits as described below, and the second code length could be 640 bits as described below.

[0112] For example, in order to improve the flexibility of encoding, in this embodiment of the application, the first element in the 17th column of the base matrix is ​​zero, and the xth element in the 17th column of the base matrix and the 16th element are the same non-zero element, where x is an integer greater than 1 and less than 16.

[0113] The following two examples illustrate the positions of the first and second elements in the basis matrix. Here, 'a' indicates that the corresponding element's position exists within a z*z cyclic shift identity matrix; that is, 'a' indicates the position of the first element in the basis matrix. 'a' should not be interpreted as the value of the element; the values ​​of the first element represented by 'a' can be the same or different. '-' indicates a matrix of all zeros; that is, '-' represents the second element. '-' can also be replaced with '-1' or other representations.

[0114] Example 1,

[0115] Example 2,

[0116] The R corresponding to the base matrix of the parity check matrix shown in Examples 1 and 2 above can be equal to 1 / 2, and the R corresponding to the parity check matrix is ​​also equal to 1 / 2.

[0117] The first X columns of the base matrix correspond to the information bits, so it can be called the square matrix corresponding to the information bits, or the information square matrix. X = 32 * R. When R equals 1 / 2, the X columns are the left 16 * 16 part of the base matrix. The last Y columns of the base matrix correspond to the parity bits, so it can be called the square matrix corresponding to the parity bits, or the parity square matrix. Y = 32 * (1 - R). When R equals 1 / 2, the Y columns are the right 16 * 16 part of the base matrix.

[0118] In Examples 1 and 2 above, the basis matrices have different row weights in at least one row and different column weights in at least one column. Row weight refers to the number of elements in a row of the basis matrix corresponding to a non-zero matrix, and column weight refers to the number of elements in a column of the basis matrix corresponding to a non-weighted zero matrix. Different row and / or column weights in the basis matrices result in different decoding complexities. The decoding complexity can be related to the average variable node degree η, and therefore can be represented by η. In Example 1, η is smaller than in Example 2. Optionally, η = 3.1 for Example 1 and η = 3.47 for Example 2.

[0119] The position of the first element in the base matrix in Example 1 above can also be seen in the first column of Figure 5a: the mother matrix. Here, "0, 3, 7, 11, 15, 16, 17" indicates that the first element is located in the 0th row and the 0th, 3rd, 7th, 11th, 15th, 16th, and 17th columns of the mother matrix; "0, 3, 6, 11, 16th, 17th, 18" indicates that the first element is located in the 0th row and the 0th, 3rd, 6th, 11th, 16th, 17th, and 18th columns of the mother matrix; and so on.

[0120] In Example 2 above, the position of the first element in the base matrix can also be seen in the first column of Figure 5b: the mother matrix. Here, "0, 3, 4, 9, 15, 16, 17" indicates that the first element is located in the 0th row and the 0th, 3rd, 4th, 9th, 15th, 16th, and 17th columns of the mother matrix; "1, 2, 4, 8, 16, 17, 18" indicates that the first element is located in the 1st row and the 1st, 2nd, 4th, 8th, 16th, 17th, and 18th columns of the mother matrix...

[0121] In Example 1 above, to obtain parity-check matrices corresponding to different code lengths, the expansion factor z takes different values, and the cyclic shift values ​​(i.e., the values ​​of the first elements) in the base matrix also differ. The following examples illustrate the base matrix using expansion factors z = 10, z = 20, z = 40, z = 60, and z = 80.

[0122] In Implementation 1 of Example 1 above, when the expansion factor z is 10, the basis matrix can be expanded into a parity-check matrix corresponding to N1 being 320 bits. For example, the basis matrix can be represented as:

[0123] In Implementation Method 1 of Example 1 above, the basis matrix can also be represented as shown in column 6 (N1 = 320, z = 10) of Figure 5a. Here, "3, 8, 9, 0, 5, 0, 0" indicates that the value of the first element in row 0 of the parent matrix is ​​3, 8, 9, 0, 5, 0, 0 in sequence; "4, 1, 5, 8, 2, 0, 0" indicates that the value of the first element in row 1 of the parent matrix is ​​4, 1, 5, 8, 2, 0, 0... in sequence.

[0124] In implementation method 1 above, any first element, such as element i (where i is the value corresponding to the element), can be expanded into a CPM, which is obtained by cyclically shifting the identity matrix to the right by i positions. For example, element 0 in implementation method 1 can be expanded into a 10*10 identity matrix, and elements i greater than 0 (e.g., i is greater than 0) can be cyclically shifted to the right by i positions based on the identity matrix to obtain a 10*10 CPM. The base matrix shown in implementation method 1 includes 16 rows and 32 columns, so the parity check matrix expanded based on the expansion factor z can include 16*10 rows and 32*10 columns. The relevant explanation regarding the expansion factor z here also applies to the other implementation methods in Example 1 below, the only difference being the value of z, which will not be repeated for the sake of brevity.

[0125] In implementation method 2 of Example 1 above, when the expansion factor z is 20, the basis matrix can be expanded into a parity check matrix corresponding to N1 being 640 bits. For example, the basis matrix can be represented as:

[0126] In implementation method 2 of Example 1 above, the basis matrix can also be represented as shown in column 5 (N1 = 640, z = 20) of Figure 5a. Here, "17, 8, 15, 17, 11, 0, 0" indicates that the values ​​of the first element in row 0 of the parent matrix are 17, 8, 15, 17, 11, 0, 0 in sequence; "5, 11, 14, 10, 14, 0, 0" indicates that the values ​​of the first element in row 1 of the parent matrix are 5, 11, 14, 10, 14, 0, 0... in sequence.

[0127] In implementation method 3 of Example 1 above, when the expansion factor z is 40, the basis matrix can be expanded into a parity check matrix corresponding to N1 being 1280 bits. For example, the basis matrix can be represented as:

[0128] In implementation method 3 of Example 1 above, the basis matrix can also be represented as shown in column 4 (N1 = 1280, z = 40) of Figure 5a. Here, "27, 13, 33, 33, 0, 0, 0" indicates that the value of the first element in row 0 of the parent matrix is ​​27, 13, 33, 33, 0, 0, 0; "26, 4, 7, 36, 27, 0, 0" indicates that the value of the first element in row 1 of the parent matrix is ​​26, 4, 7, 36, 27, 0, 0...

[0129] In implementation method 4 of Example 1 above, when the expansion factor z is 60, the basis matrix can be expanded into a parity check matrix corresponding to N1 being 1920 bits. For example, the basis matrix can be represented as:

[0130] In implementation method 4 of Example 1 above, the basis matrix can also be represented as shown in column 3 (N1 = 1920, z = 60) of Figure 5a. Here, "3, 43, 17, 49, 54, 0, 0" indicates that the values ​​of the first element in row 0 of the parent matrix are 3, 43, 17, 49, 54, 0, 0 in sequence; "10, 39, 19, 32, 22, 0, 0" indicates that the values ​​of the first element in row 1 of the parent matrix are 10, 39, 19, 32, 22, 0, 0... in sequence.

[0131] In implementation method 5 of Example 1 above, when the expansion factor z is 80, the basis matrix can be expanded into a parity check matrix corresponding to N1 being 2560 bits. For example, the basis matrix can be represented as:

[0132] In implementation method 5 of Example 1 above, the basis matrix can also be represented as shown in column 2 (N1 = 2560, z = 80) of Figure 5a. Here, "56, 16, 36, 45, 17, 0, 0" indicates that the values ​​of the first element in row 0 of the parent matrix are 56, 16, 36, 45, 17, 0, 0 in sequence; "75, 70, 54, 14, 15, 0, 0" indicates that the values ​​of the first element in row 1 of the parent matrix are 75, 70, 54, 14, 15, 0, 0... in sequence.

[0133] Similar to Example 1 above, in Example 2, the values ​​of the expansion factor z are different, and the cyclic shift values ​​(i.e., the values ​​of the first elements) in the basis matrix also differ. The following examples illustrate the basis matrix using expansion factors z = 10, z = 20, z = 40, z = 60, and z = 80.

[0134] In Implementation Method 1 of Example 2 above, when the expansion factor z is 10, the basis matrix can be expanded into a parity check matrix corresponding to N1 being 320 bits. For example, the basis matrix can be represented as:

[0135] In Implementation Method 1 of Example 2 above, the basis matrix can also be represented as shown in column 6 (N1 = 320, z = 10) of Figure 5b. Here, "2, 7, 6, 4, 6, 0, 0" indicates that the values ​​of the first element in row 0 of the parent matrix are 2, 7, 6, 4, 6, 0, 0 in sequence; "5, 3, 7, 8, 2, 0, 0" indicates that the values ​​of the first element in row 1 of the parent matrix are 5, 3, 7, 8, 2, 0, 0... in sequence.

[0136] In implementation method 2 of Example 2 above, when the expansion factor z is 20, the basis matrix can be expanded into a parity check matrix corresponding to N1 being 640 bits. For example, the basis matrix can be represented as:

[0137] In implementation method 2 of Example 2 above, the basis matrix can also be represented as shown in column 5 (N1 = 640, z = 20) of Figure 5b. Here, "5, 15, 4, 15, 10, 0, 0" indicates that the value of the first element in row 0 of the parent matrix is ​​5, 15, 4, 15, 10, 0, 0 in sequence; "5, 13, 9, 19, 2, 0, 0" indicates that the value of the first element in row 1 of the parent matrix is ​​5, 13, 9, 19, 2, 0, 0... in sequence.

[0138] In implementation method 3 of Example 2 above, when the expansion factor z is 40, the basis matrix can be expanded into a parity check matrix corresponding to N1 being 1280 bits. For example, the basis matrix can be represented as:

[0139] In implementation method 3 of Example 2 above, the basis matrix can also be represented as shown in column 4 (N1 = 1280, z = 40) of Figure 5b. Here, "22, 6, 17, 29, 2, 0, 0" indicates that the values ​​of the first element in row 0 of the parent matrix are 22, 6, 17, 29, 2, 0, 0 in sequence; "27, 34, 2, 7, 13, 0, 0" indicates that the values ​​of the first element in row 1 of the parent matrix are 27, 34, 2, 7, 13, 0, 0... in sequence.

[0140] In implementation method 4 of Example 2 above, when the expansion factor z is 60, the basis matrix can be expanded into a parity check matrix corresponding to N1 being 1920 bits. For example, the basis matrix can be represented as:

[0141] In implementation method 4 of Example 2 above, the basis matrix can also be represented as shown in column 3 (N1 = 1920, z = 60) of Figure 5b. Here, "35, 34, 28, 0, 15, 0, 0" indicates that the values ​​of the first element in row 0 of the parent matrix are 35, 34, 28, 0, 15, 0, 0 in sequence; "5, 30, 44, 19, 43, 0, 0" indicates that the values ​​of the first element in row 1 of the parent matrix are 5, 30, 44, 19, 43, 0, 0... in sequence.

[0142] In implementation 5 of Example 2 above, when the expansion factor z is 80, the basis matrix can be expanded into a parity check matrix corresponding to N1 being 2560 bits. For example, the basis matrix can be represented as:

[0143] In implementation method 5 of Example 2 above, the basis matrix can also be represented as shown in column 2 (N1 = 2560, z = 80) of Figure 5b. Here, "67, 10, 55, 5, 55, 0, 0" indicates that the values ​​of the first element in row 0 of the parent matrix are 67, 10, 55, 5, 55, 0, 0 in sequence; "28, 22, 11, 41, 59, 0, 0" indicates that the values ​​of the first element in row 1 of the parent matrix are 28, 22, 11, 41, 59, 0, 0... in sequence.

[0144] For the possible implementations of Example 2 above, the relevant explanations of the expansion factor z can be found in the description in Example 1, and will not be repeated here.

[0145] The base matrices of the parity-check matrix shown in the various possible implementations of Examples 1 and 2 above are merely examples and do not constitute any limitation on this application. Furthermore, the value of z in any of the above implementations is only an example; the value of z can also be greater than the values ​​in the examples above. For instance, in implementation 5 of Example 2 above, z can also be greater than 80, and the corresponding base matrix N1 of the parity-check matrix is ​​equal to 32*z.

[0146] In S320 above, the first communication device can perform LDPC encoding using an encoding module (such as an LDPC encoding module) to obtain the encoded sequence, and then output the encoded sequence from the encoding module. The length of the encoded sequence can be N1 as described above. The encoded sequence can include K information bits and E parity bits. Alternatively, the encoded sequence can be composed of an information bit sequence and a parity bit sequence, where the length of the information bit sequence can be N2, and the length of the parity bit sequence can be E. N1 = N2 + E. The value of E is related to N1 and R. For example, if N1 = 320 and R = 1 / 2, then E = 160.

[0147] In one possible implementation, the first communication device may perform a shortening operation after outputting the encoded sequence. An example is given below.

[0148] Typically, the encoded information bit sequence needs to be placed into an integer number of orthogonal frequency division multiplexing (OFDM) symbols, and the encoded sequence also needs to be placed into an exact integer number of LDPC codewords. Therefore, before the first communication device performs LDPC encoding, it needs to determine the minimum number of OFDM symbols N required for this transmission. SYM Then based on N SYM Calculate the total number of coded bits N that can be stored in all OFDM symbols, based on the current coding and modulation scheme (such as the modulation order indicated by the MCS). TCB =N CBPS *N SYM , where N CBPS The number of encoded bits that can be stored for each OFDM symbol. Next, the first communication device can calculate the LDPC code length (i.e., the code length shown in the embodiments of this application) and the required number of codewords N based on the above results. CWFor example, when there are not enough information bits (as shown in Examples 1 to 3 below, where K is less than 1944) to fill the information bit portion of the LDPC codeword, the first communication device can perform a shortening operation before performing LDPC encoding (also known as generating parity bits). The shortening operation refers to filling the information bit portion with a certain number of 0s before generating the parity bits through LDPC encoding, and then deleting these 0s after encoding the parity bits. Figure 4 is a partial schematic diagram of a shortening operation in LDPC encoding provided by an embodiment of this application. As shown in Figure 4, step 401 indicates that the first communication device can obtain the payload bits to be encoded (as shown in the embodiments of this application, K information bits). Step 402 indicates that the first communication device can calculate the LDPC code length and the number of codewords. Figure 4 exemplarily shows three LDPC codewords. The length (i.e., code length) of each LDPC codeword can be equal to the code length. Step 403 indicates that the first communication device can perform a shortening operation on the information bits. Figure 4 shows a codeword containing payload bits and shortened zero bits. Step 404 indicates that the first communication device can generate parity bits using the load bits and shortened bits. Figure 4 shows a codeword containing load bits, shortened 0 bits, and parity bits. Step 405 indicates that the first communication device discards these shortened 0 bits. Figure 4 shows a codeword containing data bits and parity bits. The above descriptions regarding shortening operations are merely examples. Further explanations regarding shortening operations can be found in relevant standards or protocols, and this application does not limit the scope of the embodiments.

[0149] The first information in S320 above can be an encoded sequence, or in other words, the first information is a signal that can be transmitted through the channel obtained by processing the encoded sequence. For example, the first communication device can also perform at least one of the following processes on the encoded sequence: stream parsing, constellation mapping, LDPC subcarrier mapping, stream cyclic shifting, space-frequency mapping, inverse discrete fourier transform (IDFT), insertion of cyclic prefix, and windowing.

[0150] For example, the first communication device can also perform rate matching on the encoded sequence, and the rate matching method includes puncturing, repetition, and shortening. For instance, the first communication device can also puncture the parity bits in the encoded sequence to obtain a higher code rate or a shorter code length. Other processing of the encoded sequence by the first communication device can also be referenced to relevant standards or protocols, and this application embodiment does not limit this.

[0151] S330, the first communication device sends first information to the second communication device, and correspondingly, the second communication device receives the first information sent by the first communication device.

[0152] For example, after receiving the first information, the second communication device can perform corresponding processing on the first information to obtain the information to be decoded. When the second communication device receives the first information, it can perform at least one of the following processes: removing cyclic prefixes, performing a discrete Fourier transform (DFT), spatial and frequency demapping, deinterleaving, and constellation decoupling. The corresponding processing performed by the second communication device before obtaining the information to be decoded can also refer to relevant standards or protocols, etc., and this application embodiment does not limit this. The length of the information to be decoded can be N1.

[0153] S340, the second communication device performs LDPC decoding on the information to be decoded based on the parity check matrix to obtain the information bit sequence.

[0154] For example, the decoding methods that the second communication device may employ include, but are not limited to, hard-decision decoding, soft-decision decoding, or hybrid decoding methods. The specific decoding process will not be described in detail in the embodiments of this application.

[0155] For example, the second communication device can also use a method similar to Figure 4 to determine the code length N1, etc. For the relevant explanation of how the second communication device obtains the code length N1 and code rate R, please refer to the description of the first communication device above, which will not be detailed here.

[0156] The methods by which the first communication device learns N1 and R, and the methods by which the second communication device learns N1 and R, can be referred to relevant standards or protocols, and the embodiments of this application do not limit them.

[0157] In this embodiment, steps S310 and S320 can be implemented by an encoding module, and step 340 can be implemented by a decoding module. In specific implementations, the method shown in Figure 3 can also be divided into an encoding method or a decoding method. For example, the first communication device may include an encoding module, and the second communication device may include a decoding module. Optionally, in addition to the encoding module, the first communication device may also include an acquisition module, which can be used to acquire code length and code rate, etc. Optionally, the first communication device may also include a shortening module or a segmentation module, etc. Optionally, in addition to the decoding module, the second communication device may also include an acquisition module, which can be used to acquire information to be decoded.

[0158] In this embodiment, the first base matrix supporting the first code length is associated with the second base matrix supporting the second code length. For example, the position of the cyclic displacement matrix represented by the first element of the first base matrix is ​​the same as the position of the cyclic displacement matrix represented by the first element of the second base matrix. This reduces the processing complexity for the communication device to determine the parity matrix, thereby improving the data transmission reliability of the system.

[0159] Furthermore, in the embodiments of this application, in the parity check matrix determined based on the 16*32 base matrix, the first element in the 17th column is zero, the xth element in the 17th column and the 16th element are the same non-zero element, and x is an integer greater than 1 and less than 16, which improves the flexibility of encoding.

[0160] The following describes the method for determining the verification matrix involved in the embodiments of this application.

[0161] The method for determining the parity check matrix shown in this application is merely an example. In specific implementations, the determination method described below can be defined by a standard. Alternatively, in specific implementations, the communicating parties can save the base matrix of the parity check matrix, or save the cyclic shift value, or save the position of the first element, etc.

[0162] The first communication device can determine the parity check matrix corresponding to the target code length based on a 16*32 base matrix. This 16*32 base matrix can be described in either of the aforementioned implementations in Example 1 and Example 2. In some embodiments, the first communication device can select the base matrix based on the target code length. For example, when the code length is 320 bits, it can select the base matrix in implementation 1 of Example 1 or implementation 1 of Example 2; or, when the code length is 640 bits, it can select the base matrix in implementation 1 of Example 1 or implementation 2 of Example 2, and so on. In other embodiments, the first communication device can obtain the position information of the first element in the base matrix and determine the value (i.e., the cyclic shift value) of each first element in the base matrix according to the target code length. For example, when the target code length is 320 bits, in Example 1 above, the first communication device can obtain the information in column 1 and column 6 of Figure 5a to determine the base matrix.

[0163] Furthermore, the first communication device expands the base matrix to obtain the parity check matrix of LDPC codes with different code lengths. The process of expanding the base matrix to obtain the parity check matrix has been explained above and will not be repeated for the sake of brevity.

[0164] The method by which the second communication device determines the parity check matrix is ​​similar to that of the first communication device, and will not be repeated here for the sake of brevity.

[0165] The method for determining the parity check matrix described above can be for a specific code rate, such as a 1 / 2 code rate. The first communication device can perform rate matching on the encoded sequence through processing operations such as punching, repetition, and shortening to obtain encoded sequences with other code rates.

[0166] The parity-check matrix of an LDPC code can also be represented by a factor graph (tanner graph). The factor graph and the parity-check matrix are in one-to-one correspondence. The factor graph consists of two types of nodes: variable nodes, representing information bits, and parity nodes, representing parity constraints. Each parity node represents a parity constraint. Figure 6a shows the parity-check matrix H of the LDPC code. In Figure 6a, {Vi} represents the set of variable nodes, and {Cj} represents the set of parity nodes. i = 1, 2, ..., 8. j = 1, 2, 3, 4. Each row of the parity-check matrix H corresponds to a parity equation, and each column corresponds to an information bit. In Figure 6a, there are 8 variable nodes and 4 parity nodes. If an information bit is included in the corresponding parity equation, a line connects the involved variable nodes and parity nodes to obtain the factor graph. Figure 6b shows the factor graph of the parity-check matrix H of the LDPC code. Other explanations regarding factor graphs can be found in relevant standards or protocols, and are not limited in this embodiment.

[0167] In this embodiment, the parity check matrix is ​​designed according to quasi-rule parity, meaning that the weight of all rows in the base matrix (i.e., the number of non-zero items in a row) has only two values: d and d+1. For example, in Example 1, the row weight of rows 0 to 2 is 7, and the row weight of rows 3 to 15 is 6; similarly, in Example 2, the row weight of rows 0 to 14 is 7, and the row weight of row 15 is 6. This characteristic of the base matrix can improve the efficiency of parity check node processing in the LDPC decoding process, avoid resource waste, and further minimize the maximum degree of the parity check node (i.e., the aforementioned d+1) to reduce resource waste.

[0168] To balance the performance, decoding convergence speed, and decoding complexity of LDPC codes, this application aims to make the LDPC code (or parity check matrix) effectively applicable to transmission systems such as UWB, which have stringent requirements for latency and decoding convergence speed. In this embodiment, the basis matrix is ​​obtained by adjusting some or all of the parameters in the control variables: average node degree (η), slope, and stability factor. For example, the position and value of the first element in the basis matrix are determined.

[0169] The decoding complexity is related to the node degree η mentioned above. In some embodiments, the decoding complexity can be represented by the node degree η. The decoding complexity can also be related to the average number of iterations; for example, the iterative decoding complexity can be expressed by the average number of iterations n. it The product representation of decoding complexity, such as C∝η·n it .

[0170] The following examples, with reference to Figures 7a to 7d, illustrate the impact of the basis matrix on decoding performance when using different control variables.

[0171] Referring to Figure 7a, taking a code length of 320 bits and 8 decoding iterations as an example, the first column in Figure 7a represents the slope, and the column labels in the first row describe the average column weight of the parity check matrix. Each item in the table of Figure 7a represents the slope (row) and average column weight of the response reaching 10. -2 The SNR difference (or SNR loss value) between the signal-to-noise ratio (SNR) required for the frame error rate (FER) and the response channel capacity (SNR) is represented by the last row: Grand Total, which shows the small SNR loss value under different average column weights. Figure 8a represents the table data shown in Figure 7a with decoding complexity on the x-axis and SNR loss value on the y-axis.

[0172] Figure 7b is similar to Figure 7a, except that the parity-check matrix in the table shown in Figure 7b has a code length of 640 bits. Figure 8b represents the table data shown in Figure 7b with decoding complexity on the x-axis and SNR loss on the y-axis. Figure 7c is similar to Figure 7a, except that the parity-check matrix in the table shown in Figure 7c has a code length of 1280 bits. Figure 8c represents the table data shown in Figure 7c with decoding complexity on the x-axis and SNR loss on the y-axis. Figure 7d is similar to Figure 7a, except that the parity-check matrix in the table shown in Figure 7d has a code length of 2560 bits.

[0173] Referring to Figures 7a to 7d and Figures 8a to 8c, in order to achieve a balance between performance and decoding complexity, the verification matrix implemented at decoding complexity η = 3.1 and decoding complexity η = 3.47 is selected as the verification matrix of the embodiment of this application.

[0174] The following describes the simulation results of the verification matrix provided in the embodiments of this application.

[0175] The following sections present the parity check matrices of the aforementioned LDPC codes and compare their performance with that of a reference parity check matrix. The reference parity check matrix can be the parity check matrix of an LDPC code with a classless WiFi coding structure. In Figures 9a to 9d, the horizontal axis represents SNR in dB, and the vertical axis represents FER. The numbers 1 to 8 in Figures 9a to 9d are for ease of distinguishing different curves and should not be construed as limiting the embodiments of this application.

[0176] Figure 9a shows the FER performance comparison of the parity check matrix provided in this application embodiment, such as the parity check matrix with decoding complexity η = 3.47 and dual diagonal (DD), with the parity check matrix of non-WiFi-like coding of the same code length (such as the parity check matrix with eta = 3.5 and no dual diagonal), under 8 decoding iterations. Here, eta refers to the complexity, which is expressed as the average column weight of the code parity check matrix. Figure 9a shows a comparison of the FER performance of the following parity-check matrices: DD 320, 3.47 and C320, eta = 3.5 (320-bit code length); DD 640, 3.47 and C640, eta = 3.5 (640-bit code length); DD 1280, 3.47 and C1280, eta = 3.5 (1280-bit code length); and C2560, 3.47 and C2560, eta = 3.5 (2560-bit code length). R = 1 / 2. C320, C640, C1280, and C2560 are all parity-check matrices without double diagonals.

[0177] Figure 9b shows a comparison of the FER performance of the parity check matrix provided in this application embodiment, such as the parity check matrix with decoding complexity η = 3.47 (DD), with the parity check matrix (eta = 3.5) of the same code length for 25 decoding iterations.

[0178] Figure 9c shows a comparison of the FER performance of the parity check matrix provided in this application embodiment, such as the parity check matrix with decoding complexity η = 3.09 (DD), with the parity check matrix of non-WiFi-like encoding with the same code length (eta = 3.2), under 8 decoding iterations.

[0179] Figure 9d shows the FER performance comparison between the parity check matrix provided in this application embodiment, such as the parity check matrix with decoding complexity η = 3.09 (DD), and the parity check matrix (eta = 3.2) of the same code length for 25 decoding iterations.

[0180] As can be seen from Figures 9a to 9d, the parity check matrix obtained by expanding the parity check matrix using the base matrix with the same first element position in the embodiment of this application has excellent decoding performance, while achieving a good balance between decoding performance and decoding complexity.

[0181] The following describes the communication device provided in the embodiments of this application.

[0182] This application divides the communication device into functional modules according to the above method embodiments. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one processing module. The integrated modules can be implemented in hardware or as software functional modules. It should be noted that the module division in this application is illustrative and only represents one logical functional division; other division methods may be used in actual implementation. The communication device of the embodiments of this application will be described in detail below with reference to Figures 10 to 101.

[0183] Figure 10 is a schematic diagram of the structure of a communication device 500 provided in an embodiment of this application. As shown in Figure 10, the communication device includes a processing module 510 and a transceiver module 520. The transceiver module 520 can implement corresponding communication functions, and the processing module 510 is used to implement corresponding processing functions. For example, the transceiver module 520 can also be called an interface, a communication interface, or a communication module, etc.

[0184] In some embodiments of this application, the communication device can be used to perform the actions performed by the first communication device in the above method embodiments. In this case, the first communication device can be the Wi-Fi device itself or a chip or functional module configurable in the device. The transceiver module 520 is used to perform the transmission and reception related operations of the first communication device in the above method embodiments, and the processing module 510 is used to perform the processing related operations of the first communication device in the above method embodiments.

[0185] For example, processing module 510 can be used to determine the parity check matrix corresponding to the target code length based on a 16*32 base matrix. The base matrix includes multiple first elements, each corresponding to a cyclic shift matrix. The position of the first element in the first base matrix is ​​the same as its position in the second base matrix. The first base matrix is ​​used to determine the parity check matrix corresponding to the first code length, and the second base matrix is ​​used to determine the parity check matrix corresponding to the second code length. The target code length includes either the first code length or the second code length. The first element in the 17th column of the base matrix is ​​zero, and the x-th element in the 17th column of the base matrix and the 16th element are the same non-zero element. Transceiver module 520 can be used to send first information, which is obtained by encoding based on the parity check matrix.

[0186] For example, the processing module 510 can also be used to perform LDPC encoding on the information bit sequence and to perform other processing on the encoded sequence to obtain the first information; the transceiver module 520 can also be used to send or output the signal after other processing.

[0187] For example, the processing module 510 may include an encoding module. The processing module 510 may also include an acquisition module, a shortening module, or a segmentation module. For example, the processing module 510 may also include at least one of the following modules: a constellation mapping module, a stream cyclic shifting module, a space-frequency mapping module, an IDFT module, and a cyclic prefix insertion and windowing module. For example, the transceiver module 520 may include a radio frequency module, an antenna module, etc. For example, the transceiver module 502 may include a pin module, etc.

[0188] Reusing Figure 10, in some other embodiments of this application, the communication device 500 can be used to perform the actions performed by the second communication device in the above method embodiments. In this case, the communication device can be the Wi-Fi device itself or a chip or functional module configurable in the device. The transceiver module 520 is used to perform the transceiver-related operations of the second communication device in the above method embodiments, and the processing module 510 is used to perform the processing-related operations of the second communication device in the above method embodiments.

[0189] For example, the transceiver module 520 can be used to receive first information, which is encoded based on a parity check matrix of the target code length; the processing module 510 can be used to determine the parity check matrix based on a 16*32 base matrix, the base matrix including multiple first elements, the first elements corresponding to a cyclic shift matrix, the position of the first element in the first base matrix being the same as the position of the first element in the second base matrix, the first base matrix being used to determine the parity check matrix corresponding to the first code length, the second base matrix being used to determine the parity check matrix corresponding to the second code length, the target code length including the first code length or the second code length, the first element in the 17th column of the base matrix being zero, and the xth element in the 17th column of the base matrix being the same non-zero element as the 16th element.

[0190] For example, the transceiver module 520 can also be used to input information to be decoded; the processing module 510 can also perform LDPC decoding on the information to be decoded based on the parity check matrix to obtain the information bit sequence.

[0191] For example, the processing module 510 may include a decoding module. The processing module 510 may also include an acquisition module, etc. For example, the processing module 510 may also include at least one of the following components: a cyclic prefix removal module, a DFT module, a deinterleaving module, a deconstellation module, and a descrambling module. For example, the transceiver module 520 may include a radio frequency module, an antenna module, etc. For example, the transceiver module 520 may include a pin module, etc.

[0192] Optionally, in the above embodiments, the communication device may further include a storage module, which can be used to store instructions and / or data. The processing unit 510 can read the instructions and / or data in the storage module so that the communication device can implement the aforementioned method embodiments.

[0193] The specific descriptions of the transceiver module and processing module shown in the above embodiments are merely examples. For the specific functions or execution steps of the transceiver module and processing module, please refer to the above method embodiments, which will not be described in detail here.

[0194] The communication device according to the embodiments of this application has been described above. The following describes possible product forms of the communication device. Any product possessing the functions of the communication device described in FIG10 above falls within the protection scope of the embodiments of this application. The following description is merely illustrative and does not limit the product form of the communication device according to the embodiments of this application to this extent.

[0195] In one possible implementation, in the communication device shown in FIG10, the processing module 510 may be one or more processors, and the transceiver module 520 may be a transceiver, or the transceiver module 520 may also be a transmitting module and a receiving module. The transmitting module may be a transmitter, and the receiving module may be a receiver. The transmitting module and the receiving module are integrated into one device, such as a transceiver. In the embodiments of this application, the processor and the transceiver may be coupled, etc., and the connection method of the processor and the transceiver is not limited in the embodiments of this application. In the process of executing the above method, the process of sending information in the above method may be the process of the processor outputting the above information. When outputting the above information, the processor outputs the above information to the transceiver so that the transceiver can transmit it. After the above information is output by the processor, it may need to undergo other processing before reaching the transceiver. Similarly, the process of receiving information in the above method may be the process of the processor receiving the input above information. When the processor receives the input information, the transceiver receives the above information and inputs it into the processor. Furthermore, after the transceiver receives the above information, the above information may need to undergo other processing before being input into the processor.

[0196] As shown in Figure 11, the communication device 600 includes one or more processors 620 and transceivers 610.

[0197] In some embodiments of this application, the communication device can be used to execute the steps, methods, or functions executed by the first communication device or network management server described above. For example, the processor 620 can be used to execute the functions or steps implemented by the processing module 510 shown in FIG. 10, and the transceiver 610 can be used to execute the functions or steps implemented by the transceiver module 520 shown in FIG. 10. Detailed descriptions of the processor 620 and transceiver 610 can be found in FIG. 10 or the method embodiments shown above, and will not be elaborated further here.

[0198] In other embodiments of this application, the communication device is used to execute the steps, methods, or functions performed by the second communication device or terminal device described above. For example, the processor 620 can be used to execute the functions or steps implemented by the processing module 510 shown in FIG. 10, and the transceiver 610 can be used to execute the functions or steps implemented by the transceiver module 520 shown in FIG. 10. Detailed descriptions of the processor 620 and transceiver 610 can be found in FIG. 10 or the method embodiments shown above, and will not be elaborated further here.

[0199] In various implementations of the communication device shown in Figure 11, the transceiver may include a receiver for performing a receiving function (or operation) and a transmitter for performing a transmitting function (or operation). The transceiver is also used to communicate with other devices / appliances via a transmission medium.

[0200] Optionally, the communication device 600 may further include one or more memories 630 for storing program instructions and / or data. The memory 630 is coupled to the processor 620. The coupling in this embodiment is an indirect coupling or communication connection between communication devices, units, or modules, and can be electrical, mechanical, or other forms, used for information exchange between the communication devices, units, or modules. The processor 620 may operate in conjunction with the memory 630. The processor 620 can execute program instructions stored in the memory 630. Optionally, at least one of the above-mentioned memories may be included in the processor.

[0201] This embodiment does not limit the specific connection medium between the transceiver 610, processor 620, and memory 630. In Figure 11, the memory 630, processor 620, and transceiver 610 are connected via a bus 640, indicated by a thick line. The connection methods between other components are merely illustrative and not intended to be limiting. The bus can be an address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used in Figure 11, but this does not indicate that there is only one bus or one type of bus.

[0202] In the embodiments of this application, the processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or being executed by a combination of hardware and software modules within the processor.

[0203] In this application embodiment, the memory may include, but is not limited to, non-volatile memory such as hard disk drive (HDD) or solid-state drive (SSD), random access memory (RAM), erasable programmable read-only memory (EPROM), read-only memory (ROM), or compact disc read-only memory (CD-ROM), etc. Memory is any storage medium capable of carrying or storing program code having instruction or data structure forms, and capable of being read and / or written by a computer (such as the communication device shown in this application), but is not limited to this. The memory in this application embodiment may also be a circuit or any other device capable of implementing storage functions, used to store program instructions and / or data.

[0204] The processor 620 is primarily used to process communication protocols and data, control the entire communication device, execute software programs, and process the data from those programs. The memory 630 is primarily used to store software programs and data. The transceiver 610 may include control circuitry and an antenna. The control circuitry is primarily used for converting baseband signals to radio frequency signals and processing radio frequency signals. The antenna is primarily used for transmitting and receiving radio frequency signals in the form of electromagnetic waves. Input / output devices, such as touchscreens, displays, and keyboards, are primarily used to receive user input data and output data to the user.

[0205] When the communication device is powered on, the processor 620 can read the software program in the memory 630, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be transmitted wirelessly, the processor 620 performs baseband processing on the data to be transmitted and outputs the baseband signal to the radio frequency (RF) circuit. The RF circuit then performs RF processing on the baseband signal and transmits the RF signal outward in the form of electromagnetic waves through the antenna. When data is sent to the communication device, the RF circuit receives the RF signal through the antenna, converts the RF signal into a baseband signal, and outputs the baseband signal to the processor 620. The processor 620 converts the baseband signal back into data and processes the data.

[0206] In another implementation, the radio frequency circuitry and antenna can be set up independently of the processor performing baseband processing. For example, in a distributed scenario, the radio frequency circuitry and antenna can be arranged remotely, independent of the communication device.

[0207] The communication device shown in this application embodiment may also have more components than those in Figure 11, and this application embodiment does not limit this. The methods executed by the processor and transceiver shown above are only examples, and the specific steps executed by the processor and transceiver can be referred to the methods described above.

[0208] In another possible implementation, in the communication device shown in FIG10, the processing module 510 can be one or more logic circuits, and the transceiver module 520 can be an input / output interface, or a communication interface, or an interface circuit, or an interface, etc. Alternatively, the transceiver module 520 can also be a transmitting module and a receiving module. The transmitting module can be an output interface, and the receiving module can be an input interface. The transmitting module and the receiving module are integrated into one module, such as an input / output interface. As shown in FIG12, the communication device 700 shown in FIG12 includes a logic circuit 710 and an interface 720. That is, the above-mentioned processing module 510 can be implemented using the logic circuit 710, and the transceiver module 520 can be implemented using the interface 720. Among them, the logic circuit 710 can be a chip, a processing circuit, an integrated circuit, or a system on chip (SoC) chip, etc., and the interface 720 can be a communication interface, an input / output interface, a pin, etc. For example, FIG12 uses the above-mentioned communication device 700 as a chip, which includes a logic circuit 710 and an interface 720.

[0209] In this embodiment, the logic circuit and the interface can also be coupled to each other. The specific connection method of the logic circuit and the interface is not limited in this embodiment. For example, the logic circuit 710 can be used to execute the functions or steps implemented by the processing module 510 shown in FIG. 10, and the interface 720 can be used to execute the functions or steps implemented by the transceiver module 520 shown in FIG. 10. For a detailed description of the logic circuit 710 and the interface 720, please refer to FIG. 10 or the method embodiment shown above, which will not be detailed here.

[0210] The communication device shown in the embodiments of this application can implement the method provided in the embodiments of this application in hardware form, or it can implement the method provided in the embodiments of this application in software form, etc., and the embodiments of this application do not limit it in this way.

[0211] This application also provides a communication system, which includes a first communication device and a second communication device, which can be used to perform the methods in any of the foregoing embodiments.

[0212] In addition, this application also provides a computer program for implementing the operations and / or processes performed by various communication devices in the method provided in this application.

[0213] This application also provides a computer-readable storage medium storing computer code that, when executed on a computer, causes the computer to perform the operations and / or processes performed by various communication devices in the methods provided in this application.

[0214] This application also provides a computer program product comprising computer code or a computer program that, when run on a computer, causes the operations and / or processes performed by various entities in the method provided in this application to be executed.

[0215] In the embodiments provided in this application, it should be understood that the disclosed systems, communication devices, and methods can be implemented in other ways. For example, the communication device embodiments described above are merely illustrative. For instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, communication devices, or modules, or it may be an electrical, mechanical, or other form of connection.

[0216] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the technical effects of the solutions provided in the embodiments of this application.

[0217] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0218] If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0219] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A communication method characterized by comprising: include: The parity check matrix corresponding to the target code length is determined based on a 16*32 base matrix. The base matrix includes multiple first elements, each corresponding to a cyclic shift matrix. The position of the first element in the first base matrix is ​​the same as its position in the second base matrix. The first base matrix is ​​used to determine the parity check matrix corresponding to the first code length, and the second base matrix is ​​used to determine the parity check matrix corresponding to the second code length. The target code length includes either the first code length or the second code length. The first element in the 17th column of the base matrix is ​​zero, and the x-th element and the 16th element in the 17th column of the base matrix are the same non-zero element, where x is an integer greater than 1 and less than 16. Send the first message, which is encoded based on the check matrix.

2. The method of claim 1, wherein, The base matrix can be represented as: or ,in, The 'a' indicates that the corresponding element position has a z*z cyclic shift identity matrix, where z is the expansion factor, and the '-' indicates an all-zero matrix.

3. The method according to claim 1 or 2, characterized in that, The z is 10, the base matrix can be represented as: or 4. The method according to claim 1 or 2, characterized in that, The z is 20, the base matrix can be represented as: or 5. The method according to claim 1 or 2, characterized in that, The z is 40, the base matrix can be represented as: or 6. The method according to claim 1 or 2, characterized in that, The z is 60, the base matrix can be represented as: or 7. The method according to claim 1 or 2, characterized in that, The z is 80, the base matrix can be represented as: or 8. A communication method characterized by comprising: include: Receive first information, which is encoded based on a check matrix of target code length; The parity check matrix is ​​determined based on a 16*32 base matrix. The base matrix includes multiple first elements, each corresponding to a cyclic shift matrix. The position of the first element in the first base matrix is ​​the same as its position in the second base matrix. The first base matrix is ​​used to determine the parity check matrix corresponding to a first code length, and the second base matrix is ​​used to determine the parity check matrix corresponding to a second code length. The target code length includes either the first code length or the second code length. The first element in the 17th column of the base matrix is ​​zero, and the x-th element and the 16th element in the 17th column of the base matrix are the same non-zero element, where x is an integer greater than 1 and less than 16.

9. The method of claim 8, wherein, The base matrix can be represented as: or ,in, The 'a' indicates that the corresponding element position has a z*z cyclic shift identity matrix, where z is the expansion factor, and the '-' indicates an all-zero matrix.

10. The method according to claim 8 or 9, characterized in that, The z is 10, the base matrix can be represented as: or 11. The method according to claim 8 or 9, characterized in that, The z is 20, the base matrix can be represented as: or 12. The method of claim 8 or 9, wherein, The z is 40, the base matrix can be represented as: or 13. The method of claim 8 or 9, wherein, The z is 60, the base matrix can be represented as: or 14. The method according to claim 8 or 9, characterized in that, The z is 80, the base matrix can be represented as: or 15. A communications device, characterized by It includes a module for performing the method as described in any one of claims 1 to 7, or a module for performing the method as described in any one of claims 8 to 14.

16. A communications device, characterized by Includes a processor for performing the method as claimed in any one of claims 1 to 14.

17. A communications device, characterized by Includes logic circuits and interfaces, wherein the logic circuits and interfaces are coupled; The interface is used for inputting and / or outputting information, and the logic circuit is used for performing the method as described in any one of claims 1 to 14.

18. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store a computer program, which, when executed, performs the method as described in any one of claims 1 to 14.

19. A computer program product, characterised in that, When the computer program product is executed, the method described in any one of claims 1 to 14 is performed.

20. A communication system, characterized by The communication system includes a first communication device and a second communication device, wherein the first communication device is used to perform the method as described in any one of claims 1 to 7, and the second communication device is used to perform the method as described in any one of claims 8 to 14.

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