Scrambling code sequence generation method and device, and storage medium

Abstract

A scrambling code sequence generation method and device, and a storage medium. The method comprises: on the basis of a preset degree of parallelism, state relationship matrices of two pseudo-random sequences, and an initial value of a scrambling code recursive sequence of the two pseudo-random sequences in a fixed time delay state, determining scrambling code sequences corresponding to the two pseudo-random sequences, wherein the values of the preset degree of parallelism are different in different communication systems; and obtaining a parallel scrambling code sequence on the basis of the scrambling code sequences respectively corresponding to the two pseudo-random sequences.

Description

Scrambling Sequence Generation Method, Apparatus, and Storage Medium This application claims the priority of the Chinese patent application with the application number 202410047557.4 and the application title "Scrambling Sequence Generation Method, Apparatus, and Storage Medium" submitted to the National Intellectual Property Administration on January 11, 2024. The entire content is incorporated herein by reference. Technical Field The present disclosure relates to the technical fields of communication and signal processing, and in particular, to a scrambling sequence generation method, apparatus, and storage medium. Background Art With the wide application and development of wireless communication technologies, the air interface bandwidths of 2G, 3G, 4G, 5G, and 6G are continuously increasing. As a result, the amount of data that communication devices need to process and transmit is constantly increasing, and the processing speeds required for channel scrambling and descrambling in communication systems are also continuously increasing. Moreover, as users, cells, etc. change continuously, it is required that the scrambling sequences can distinguish different cells, users, and channels. However, the existing communication scrambling methods cannot balance the processing speeds and resource consumption of scrambling or descrambling, and have poor flexibility. Summary of the Invention On the one hand, a scrambling sequence generation method is provided. The method includes: first, based on a preset parallelism, the state relationship matrices of two pseudo-random sequences respectively, and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in a fixed time-delay state, determining the scrambling sequences corresponding to the two pseudo-random sequences respectively; then, obtaining a parallel scrambling sequence based on the scrambling sequences corresponding to the two pseudo-random sequences respectively; where the preset parallelism has different values under different communication systems. In some embodiments, when the preset parallelism is greater than a preset value, the above-mentioned step of determining the scrambling sequences corresponding to the two pseudo-random sequences respectively based on the preset parallelism, the state relationship matrices of the two pseudo-random sequences respectively, and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in a fixed time-delay state includes: decomposing the preset parallelism into N first parallelisms and a second parallelism; where the value of the first parallelism is the preset value; the second parallelism is the difference between the preset parallelism and N first parallelisms; N is an integer greater than or equal to 1; obtaining N first recurrence relationship matrices of the two pseudo-random sequences respectively based on the N first parallelisms and the state relationship matrices of the two pseudo-random sequences respectively; obtaining second recurrence relationship matrices of the two pseudo-random sequences respectively based on the second parallelism and the state relationship matrices of the two pseudo-random sequences respectively; obtaining the scrambling sequences corresponding to the two pseudo-random sequences respectively based on the N first recurrence relationship matrices of the two pseudo-random sequences respectively, the second recurrence relationship matrices of the two pseudo-random sequences respectively, and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in a fixed time-delay state. In some other embodiments, when the preset parallelism is less than or equal to a preset value, determining the scrambling sequences corresponding to the two pseudo-random sequences respectively based on the preset parallelism, the state relationship matrices of the two pseudo-random sequences respectively, and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in the fixed delay state includes: obtaining the recurrence relationship matrices of the two pseudo-random sequences respectively based on the preset parallelism and the state relationship matrices of the two pseudo-random sequences respectively; and obtaining the scrambling sequences corresponding to the two pseudo-random sequences respectively based on the recurrence relationship matrices of the two pseudo-random sequences respectively and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in the fixed delay state. In some other embodiments, the method further includes: obtaining the initial vectors of the two pseudo-random sequences respectively; determining the fixed delay state relationship matrices of the two pseudo-random sequences respectively according to the state relationship matrices of the two pseudo-random sequences respectively and the fixed delay; and obtaining the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in the fixed delay state according to the initial vectors of the two pseudo-random sequences respectively and the fixed delay state relationship matrices of the two pseudo-random sequences respectively. In some other embodiments, the initial vector value of one of the two pseudo-random sequences is a constant, and the initial vector value of the other pseudo-random sequence is a variable. In some other embodiments, obtaining the parallel scrambling sequence based on the scrambling sequences corresponding to the two pseudo-random sequences respectively includes: performing an exclusive OR operation on the scrambling sequences corresponding to the two pseudo-random sequences respectively to obtain the parallel scrambling sequence. In some other embodiments, the method further includes: obtaining the data to be scrambled; and scrambling the data to be scrambled based on the parallel scrambling sequence to obtain the scrambled data. In some other embodiments, the method further includes: obtaining the data to be descrambled; and descrambling the data to be descrambled based on the parallel scrambling sequence to obtain the descrambled data. On the other hand, a scrambling sequence generation device is provided, which includes: a generation module, configured to determine the scrambling sequences corresponding to the two pseudo-random sequences respectively based on the preset parallelism, the state relationship matrices of the two pseudo-random sequences respectively, and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in the fixed delay state; wherein the preset parallelism has different values in different communication systems; and the generation module is further configured to obtain the parallel scrambling sequence based on the scrambling sequences corresponding to the two pseudo-random sequences respectively. In some embodiments, when the preset parallelism is greater than a preset value, the generating module is specifically configured to decompose the preset parallelism into N first parallelisms and a second parallelism; wherein, the value of the first parallelism is the preset value; the second parallelism is the difference between the preset parallelism and N first parallelisms; N is an integer greater than or equal to 1; based on the state relation matrices of the N first parallelisms and the two pseudo-random sequences respectively, obtain N first recurrence relation matrices of the two pseudo-random sequences respectively; based on the second parallelism and the state relation matrices of the two pseudo-random sequences respectively, obtain the second recurrence relation matrices of the two pseudo-random sequences respectively; based on the N first recurrence relation matrices of the two pseudo-random sequences respectively, the second recurrence relation matrices of the two pseudo-random sequences respectively, and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in the fixed delay state, obtain the scrambling sequences corresponding to the two pseudo-random sequences respectively. In other embodiments, when the preset parallelism is less than or equal to the preset value, the generating module is specifically configured to obtain the recurrence relation matrices of the two pseudo-random sequences respectively based on the preset parallelism and the state relation matrices of the two pseudo-random sequences respectively; based on the recurrence relation matrices of the two pseudo-random sequences respectively and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in the fixed delay state, obtain the scrambling sequences corresponding to the two pseudo-random sequences respectively. In other embodiments, the above scrambling sequence generating device further includes: an obtaining module, configured to obtain the initial vectors of the two pseudo-random sequences respectively; the generating module is further configured to determine the fixed delay state relation matrices of the two pseudo-random sequences respectively according to the state relation matrices of the two pseudo-random sequences respectively and the fixed delay; obtain the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in the fixed delay state according to the initial vectors of the two pseudo-random sequences respectively and the fixed delay state relation matrices of the two pseudo-random sequences respectively. In other embodiments, the initial vector value of one of the two pseudo-random sequences is a constant, and the initial vector value of the other pseudo-random sequence is a variable. In other embodiments, the above generating module is specifically configured to perform a bitwise exclusive OR operation on the scrambling sequences corresponding to the two pseudo-random sequences respectively to obtain a parallel scrambling sequence. In other embodiments, the above obtaining module is further configured to obtain the data to be scrambled; the above generating module is further configured to scramble the data to be scrambled based on the parallel scrambling sequence to obtain scrambled data. In other embodiments, the above obtaining module is further configured to obtain the data to be descrambled; the above generating module is further configured to descramble the data to be descrambled based on the parallel scrambling sequence to obtain descrambled data. In another aspect, a scrambling sequence generation device is provided. The device includes a memory and a processor; the memory and the processor are coupled; the memory is used for storing computer program code, and the computer program code includes computer instructions. When the processor executes the computer instructions, the device is caused to execute the scrambling sequence generation method described in any of the above embodiments. In another aspect, a computer-readable storage medium is provided. The computer-readable storage medium stores computer program instructions, and when the computer program instructions run on a processor, the processor is caused to execute one or more steps of the scrambling sequence generation method described in any of the above embodiments. In another aspect, a computer program product is provided. The computer program product includes computer program instructions, and when the computer program instructions are executed on a computer, the computer program instructions cause the computer to execute one or more steps of the scrambling sequence generation method described in any of the above embodiments. In another aspect, a computer program is provided. When the computer program is executed on a computer, the computer program causes the computer to execute one or more steps of the scrambling sequence generation method described in any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for some embodiments of the present disclosure will be briefly introduced below. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure, and those of ordinary skill in the art can also obtain other drawings based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limitations on the actual sizes of the products, the actual processes of the methods, the actual timings of the signals, etc. involved in the embodiments of the present disclosure. FIG. 1 is a schematic structural diagram of a communication system according to some embodiments; FIG. 2 is a schematic structural diagram of a scrambling device and a descrambling device according to some embodiments; FIG. 3 is a first flowchart of a scrambling sequence generation method according to some embodiments; FIG. 4 is a second flowchart of a scrambling sequence generation method according to some embodiments; FIG. 5 is a first matrix schematic diagram according to some embodiments; FIG. 6 is a second matrix schematic diagram according to some embodiments; FIG. 7 is a third flowchart of a scrambling sequence generation method according to some embodiments; FIG. 8 is a fourth flowchart of a scrambling sequence generation method according to some embodiments; FIG. 9 is a fifth flowchart of a scrambling sequence generation method according to some embodiments; FIG. 10 is a sixth flowchart of a scrambling sequence generation method according to some embodiments; FIG. 11 is a schematic diagram of a scrambling process according to some embodiments; FIG. 12 is a seventh flowchart of a method for generating a scrambling sequence according to some embodiments; FIG. 13 is a first schematic diagram of a descrambling process according to some embodiments; FIG. 14 is a second schematic diagram of a descrambling process according to some embodiments; FIG. 15 is a third schematic diagram of a matrix according to some embodiments; FIG. 16 is a fourth schematic diagram of a matrix according to some embodiments; FIG. 17 is a fifth schematic diagram of a matrix according to some embodiments; FIG. 18 is a structural diagram of a device for generating a scrambling sequence according to some embodiments. DETAILED DESCRIPTION OF THE EMBODIMENTS The technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the scope of protection of the present disclosure. Unless otherwise required by the context, the term "comprise" and its other forms, such as the third-person singular form "comprises" and the present participle form "comprising", are interpreted in an open, inclusive sense throughout the specification and claims, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" etc. are intended to indicate that specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner. Hereinafter, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "a plurality" is two or more. "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C. "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B. As used herein, depending on the context, the term "if" is optionally interpreted to mean "when", "at the time of", "in response to determining", or "in response to detecting". Similarly, depending on the context, the phrase "if it is determined that..." or "if [the stated condition or event] is detected" is optionally interpreted to mean "when it is determined that...", "in response to determining...", "at the time of detecting [the stated condition or event]", or "in response to detecting [the stated condition or event]". The use of "is applicable to" or "is configured to" herein means open and inclusive language, which does not exclude a device that is applicable to or configured to perform additional tasks or steps. In addition, the use of "based on" means open and inclusive because a process, step, calculation, or other action "based on" one or more of the stated conditions or values can, in practice, be based on additional conditions or values beyond the stated ones. As used herein, "about" or "approximately" includes the stated value and an average value within an acceptable deviation range of the specific value, where the acceptable deviation range is determined by a person of ordinary skill in the art considering the measurement being discussed and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). As described in the background art, with the wide application and development of wireless communication technologies, the air interface bandwidths of 2G, 3G, 4G, 5G, and 6G are continuously increasing, thus requiring the communication devices to process and transmit an increasing amount of data, and the processing speed of channel scrambling and descrambling required in the communication system is also continuously increasing. And with the continuous changes of users, cells, etc., it is required that the scrambling sequences can distinguish different cells, users, and channels. The existing communication scrambling technologies mainly include: serial scrambling technology and parallel scrambling technology. Among them, the serial scrambling technology scrambles one bit of data for each clock, so the processing speed of serial scrambling is usually relatively low, but it consumes less resources. The parallel scrambling technology scrambles multiple data together for each clock, so the processing speed of parallel scrambling is fast. In theory, with a parallelism of the data length, it only takes one clock to complete scrambling, but it consumes more resources. The existing communication scrambling methods mainly include: the storage method and the real-time generation method. Among them, the storage method uses memory or storage boards to store the scrambling sequence. When scrambling is required, the scrambling sequence is read out from the memory and the data is scrambled. It can be seen that although the storage method is simple to implement, it consumes a large amount of memory. Moreover, with the increase in the communication system rate and the different scrambling sequence requirements of different users, the consumption of memory resources is increasing. The real-time generation method means that the scrambling sequence is generated in real time according to the clock. One or a group of data of the scrambling sequence is generated at each clock, and the entire scrambling sequence is obtained by clock recursion. It can be seen that this implementation method consumes less memory, and the scrambling sequences of different lengths or different users do not increase the memory. However, in order to ensure the accuracy and real-time performance of the scrambling sequence, an accurate clock source needs to be used, which may increase the hardware complexity and cost of the system. In summary, it can be seen that the communication scrambling methods in the prior art cannot balance the processing speed and resource consumption of scrambling or descrambling, and have poor flexibility. In view of the above technical problems, the embodiments of the present application provide a method for generating a scrambling sequence. The method includes: determining the scrambling sequences corresponding to two pseudo-random sequences respectively based on a preset parallelism, the state relationship matrices of the two pseudo-random sequences respectively, and the initial values of the scrambling recursion sequences of the two pseudo-random sequences in the fixed-delay state; then, obtaining a parallel scrambling sequence based on the scrambling sequences corresponding to the two pseudo-random sequences respectively; where the preset parallelism has different values under different communication systems. It can be understood that based on the method provided by the embodiments of the present application, different parallelisms can be adopted for different communication systems during the generation of the scrambling sequence to obtain a parallel scrambling sequence suitable for the communication system. In this way, the processing rate of scrambling or descrambling can be improved, the consumption of hardware resources can be reduced, the system processing time can be reduced, and the system communication delay can be reduced. As shown in FIG. 1, the embodiments of the present disclosure provide a schematic structural diagram of a communication system. The communication system includes: a first node 10 and a second node 20. Among them, the first node 10 and the second node 20 are wirelessly connected. It should be noted that the first node 10 can be a data sender or receiver; correspondingly, the second node 20 can be a data receiver or sender, and the embodiments of the present application do not limit this. Exemplarily, the first node 10 may be an access network device. For example, in LTE, it may be an evolved Node B (eNB), or in a 5G network or a future evolved public land mobile network (PLMN), it may be a base station, a broadband network gateway (BNG), an aggregation switch, or a non-3GPP access device; alternatively, the access network device in the embodiments of the present application may also be a radio controller in a cloud radio access network (CRAN); or a transmission and reception point (TRP), or a device including a TRP, etc. The embodiments of the present application do not make specific limitations thereto. Optionally, the base station in the embodiments of the present application may include various forms of base stations, such as: macro base stations, micro base stations (also known as small stations), relay stations, access points, etc. The embodiments of the present application do not make specific limitations thereto. Exemplarily, the second node 20 may be a terminal device with wireless transceiver functions. For example, it may be a mobile phone, a tablet computer (Pad), a computer with wireless transceiver functions, a virtual reality (VR) terminal, an augmented reality (AR) terminal, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, and so on. The embodiments of the present application do not limit the application scenarios. Sometimes, the terminal device may also be referred to as a user, a user equipment (UE), an access terminal, a UE unit, a UE station, a mobile station, a mobile device, a remote station, a remote terminal, a mobile device, a UE terminal, a wireless communication device, a UE agent, or a UE device, etc. The embodiments of the present application do not limit this. In some embodiments, the first node 10 includes a scrambling device, which is used to generate a scrambling code sequence according to parameter configuration, and then scramble the source data with the scrambling code sequence to obtain scrambled data; further, the first node 10 sends the scrambled data to the second node 20. Exemplarily, as shown in Fig. 2 (a), the source signal successively passes through the data serial-to-parallel conversion module, data and scrambling code scrambling module, modulation mapping module, filtering module, digital-to-analog conversion module, and carrier shift module of the scrambling device to obtain the final signal to be output. Among them, the data serial-to-parallel conversion module is a module used for converting between serial protocols and parallel protocols, which can convert the received serial data into parallel data. The data and scrambling code scrambling module is used to scramble the source data with a scrambling code sequence to obtain scrambled data. The modulation mapping module is used to map the scrambled data onto the signal waveform. The filtering module is used to filter out the noise in the signal. The digital-to-analog conversion module is used to convert digital signals into analog signals. The carrier shift module is used to shift the frequency of the input signal to another frequency while keeping the phase and amplitude of the signal unchanged. In some embodiments, the second node 20 includes a descrambling device, which is used to generate a scrambling code sequence according to parameter configuration, and then uses the scrambling code sequence to descramble the received scrambled data to obtain the source data. Exemplarily, as shown in Fig. 2 (b), the signal received by the second node successively passes through the carrier shift module, analog-to-digital conversion module, filtering module, synchronization module, demodulation mapping module, data parallel descrambling module, and data parallel-to-serial conversion module of the descrambling device to obtain the source signal. Among them, the analog-to-digital conversion module is used to convert analog signals into digital signals. The filtering module is used to filter out the noise in the signal. The synchronization module is used to achieve synchronous reception of the signal and clock extraction. The demodulation mapping module is used to map the received signal from one modulation mode to another modulation mode. The data parallel descrambling module is used to perform parallel descrambling on the scrambled data with a scrambling code sequence to obtain descrambled data. The data parallel-to-serial conversion module is used to convert the received parallel data into serial data. In some embodiments, the first node 10 may further include a descrambling device, and the second node 20 may further include a scrambling device. The embodiments of the present application do not limit this. It can be understood that the application scenarios of the embodiments of the present application are not limited. The system architecture and service scenarios described in the embodiments of the present application are for more clearly explaining the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those of ordinary skill in the art know that with the evolution of the network architecture and the emergence of new service scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems. It can be understood that in the embodiments of the present application, the first node 10 and / or the second node 20 may execute some or all of the steps in the embodiments of the present application. These steps or operations are only examples, and the embodiments of the present application may also execute other operations or various deformations of the operations. In addition, each step may be executed in a different order presented in the embodiments of the present application, and it is possible not to execute all the operations in the embodiments of the present application. It should be noted that the execution subject of the scrambling sequence generation method provided in the embodiments of the present application is not limited. For example, this method can be applied to the communication system shown in FIG. 1 and executed by the first node 10 or the second node 20. The following specifically introduces the scrambling sequence generation method provided in the embodiments of the present application. As shown in FIG. 3, the scrambling sequence generation method provided in the embodiments of the present application can be implemented as the following steps: S101. Based on a preset parallelism, the state relationship matrices of the two pseudo-random sequences respectively, and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in a fixed delay state, determine the scrambling sequences corresponding to the two pseudo-random sequences respectively. Among them, the preset parallelism has different values in different communication systems. Exemplarily, the preset parallelism can be determined according to the processing rate requirements of the communication system. For example, if the communication system has high requirements for the processing rate, the value of the preset parallelism is also high; if the communication system has low requirements for the processing rate, the value of the preset parallelism is also low. Exemplarily, assuming that the preset parallelism is P, in the case where P is equal to 1, it is serial scrambling, and in the case where P is greater than 1, it is parallel scrambling. In some embodiments, the state relationship matrices of the two pseudo-random sequences are respectively determined according to the generation polynomials of the two pseudo-random sequences. Exemplarily, the upper right corner of the state relationship matrix of the pseudo-random sequence is an identity matrix of order n - 1 of the generation polynomial of the pseudo-random sequence, the bottom row is the coefficient of the generation polynomial, and the rest of the positions are all 0. Exemplarily, assume that the two pseudo-random sequences are sequence 1 and sequence 2; among them, the generation polynomial of sequence 1 is x1(n + 31) = (x1(n + 3) + x1(n)), and the generation polynomial of sequence 2 is x2(n + 31) = (x2(n + 3) + x2(n + 2) + x2(n + 1) + x2(n)). Then the state relationship matrix T1 of sequence 1 can be represented by the following formula (1); the state relationship matrix T2 of sequence 2 can be represented by the following formula (2). In some embodiments, before the above step S101, the method further includes: determining the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in a fixed delay state. For example, as shown in FIG. 4, it can be determined according to the following steps S201 - S203. S201. Obtain the initial vectors of the two pseudo-random sequences respectively. Among them, the initial vector value of one of the two pseudo-random sequences is a constant, and the initial vector value of the other pseudo-random sequence is a variable. It can be understood that the embodiments of the present application can limit the functions of the pseudo-random sequences by the different vector values included in the pseudo-random sequences. One pseudo-random sequence has a constant initial vector value, and the other pseudo-random sequence has a variable initial vector value, which can enable the scrambling sequences generated by the communication system to be applied to both scenarios with relatively low randomness and scenarios with relatively high randomness. Exemplarily, assuming that the two pseudo-random sequences are sequence 1 and sequence 2, the initial vector can be expressed as: A = (a0, a1, a2, a3, a4, …, a 29 , a 30 ). Then, according to the 5G protocol, the initial vector value of sequence 1 is determined to be A10 = (1, 0, 0, …, 0), and the initial vector value of sequence 2 is A20 = (a0, a1, a2, …, a 30 ). It can be seen that the initial vector value of sequence 2 is a variable and can take different values according to different application scenarios. S202. Determine the fixed-delay state relationship matrices of the two pseudo-random sequences according to the state relationship matrices and fixed delays of the two pseudo-random sequences respectively. In some embodiments, the modulo-2 operation rule is adopted to determine the fixed-delay state relationship matrices of the two pseudo-random sequences according to the state relationship matrices and fixed delays of the two pseudo-random sequences respectively. Exemplarily, assuming that the fixed delay is represented as NC, the fixed-delay state relationship matrix of the pseudo-random sequence determined according to the modulo-2 operation rule can be represented as T NC . For example, assuming NC = 1600, the fixed-delay state relationship matrix T1 1600 of sequence 1 can be represented in the form shown in FIG. 5, and the fixed-delay state relationship matrix T2 1600 of sequence 2 can be represented in the form shown in FIG. 6. It can be understood that, compared with the prior art where a clock is set for recursion (for example, if the fixed delay is 1600, 1600 clocks need to be set) to obtain the recursive sequence of the fixed delay, the embodiments of the present application adopt the modulo-2 operation rule, combine the fixed delay and the state relationship matrix, and can obtain the fixed-delay state relationship matrix through one operation, which can accelerate the scrambling or descrambling processing speed of the wireless communication system, reduce the consumption of hardware resources, reduce the system processing time, and reduce the system communication delay. S203. Obtain the initial values of the scrambling recursive sequences of the two pseudo-random sequences in the fixed-delay state according to the initial vectors of the two pseudo-random sequences and the fixed-delay state relationship matrices of the two pseudo-random sequences respectively. In some embodiments, according to the product of the transpose of the initial vector of the pseudo-random sequence and the fixed-delay state relation matrix of the pseudo-random sequence, determine the initial value of the scrambling recurrence sequence of the pseudo-random sequence in the fixed-delay state. Exemplarily, when the value of the fixed delay is 1600, the initial value A of the scrambling recurrence sequence of the pseudo-random sequence in the fixed-delay state 1600 can be expressed by the following formula (3): Exemplarily, the initial value of the scrambling recurrence sequence of sequence 1 in the fixed-delay state is The initial value of the scrambling recurrence sequence of sequence 2 in the fixed-delay state is In some embodiments, as shown in FIG. 7, when the preset parallelism is greater than the preset value, the above step S101 can be implemented as the following steps Sa1-Sa4. Wherein, the preset value is determined according to the order of the generating polynomial of the pseudo-random sequence. For example, if the highest order of the generating polynomial of the pseudo-random sequence is 31, the preset value can be 31. Sa1. Decompose the preset parallelism into N first parallelisms and a second parallelism. Wherein, the value of the first parallelism is the preset value; the second parallelism is the difference between the preset parallelism and N first parallelisms; N is an integer greater than or equal to 1. Exemplarily, assume that the preset parallelism is represented as P and the preset value is 31, then the preset parallelism P can be decomposed into P = 31n + x, where n is a non-negative integer and x is an integer less than 31. Wherein, the first parallelism is 31 and the second parallelism is P - 31n = x. Sa2. Based on N first parallelisms and the state relation matrices of the two pseudo-random sequences respectively, obtain N first recurrence relation matrices of the two pseudo-random sequences respectively. In some embodiments, with the state relation matrix of the pseudo-random sequence as the base and the first parallelism as the exponent, after N operations, obtain N first recurrence relation matrices. Exemplarily, assume that the first parallelism is 31, then the first recurrence relation matrix can be obtained by calculating T 31 to obtain. Exemplarily, assume that the first parallelism is 31, the state relation matrix of sequence 1 is T1, and the state relation matrix of sequence 2 is T2, then the first recurrence relation matrix of sequence 1 is T1 31 , and the first recurrence relation matrix of sequence 2 is T2 31 . Sa3. Based on the second parallelism and the state relation matrices of the two pseudo-random sequences respectively, obtain second recurrence relation matrices of the two pseudo-random sequences respectively. In some embodiments, a second recurrence relation matrix is obtained by using the state relation matrix of a pseudo-random sequence as the base number and the second parallelism as the exponent. Exemplarily, assuming the second parallelism is x, the second recurrence relation matrix can be calculated by T x is obtained. Exemplarily, assuming the second parallelism is x, the state relation matrix of sequence 1 is T1, and the state relation matrix of sequence 2 is T2, then the second recurrence relation matrix of sequence 1 is T1 x , and the second recurrence relation matrix of sequence 2 is T2 x . Sa4. Based on the N first recurrence relation matrices of the two pseudo-random sequences respectively, the second recurrence relation matrices of the two pseudo-random sequences respectively, and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in the fixed time-delay state, the scrambling sequences corresponding to the two pseudo-random sequences are obtained. In some embodiments, the N first recurrence relation matrices of the two pseudo-random sequences respectively and the second recurrence relation matrices of the two pseudo-random sequences respectively are concatenated to obtain the recurrence relation matrices with parallelism P of the two pseudo-random sequences respectively; then, based on the products of the recurrence relation matrices with parallelism P and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in the fixed time-delay state respectively, the scrambling sequences corresponding to the two pseudo-random sequences are obtained. Exemplarily, the recurrence relation matrix with parallelism P can be expressed as TP, TP = T 31n *T x = T 31n+x . For example, the recurrence relation matrix TP1 with parallelism P of sequence 1 = T1 31n *T1 x = T1 31n+x ; the recurrence relation matrix TP2 with parallelism P of sequence 2 = T2 31n *T2 x = T2 31n+x . Assume that the initial value of the scrambling recurrence sequence of the pseudo-random sequence in the fixed time-delay state is represented as A i (where i represents the fixed time-delay), then the scrambling sequence corresponding to the pseudo-random sequence can be expressed as TP * A i . Exemplarily, the recurrence relation matrix with parallelism P of sequence 1 can be expressed as TP1, and the initial value of the scrambling recurrence sequence of sequence 1 in the fixed time-delay state is represented as A1 i , then the scrambling sequence corresponding to sequence 1 can be expressed as TP1 * A1 i . The recurrence relation matrix with parallelism P of sequence 2 can be expressed as TP2, and the initial value of the scrambling recurrence sequence of sequence 2 in the fixed time-delay state is represented as A2 i , then the scrambling sequence corresponding to sequence 2 can be expressed as TP2 * A2i 。 It can be seen that when the value of the preset parallelism P is greater than 31, the dimension of the recurrence relation matrix with parallelism P is TP P×31 , that is, P rows and 31 columns. It can be understood that the method provided by the embodiments of the present application can disassemble the parallelism and perform multiple operations when the parallelism is greater than 31, so as to avoid the limitation of the number of generated polynomial terms. In this way, it can meet the requirements of high processing rates of some communication systems, improve the processing rate of scrambling or descrambling, reduce the consumption of hardware resources, reduce the system processing time, and reduce the system communication delay. In some embodiments, as shown in FIG. 8, when the preset parallelism is less than or equal to the preset value, the above step S101 can be implemented as the following steps: Sc1. Obtain the recurrence relation matrices of the two pseudo-random sequences respectively based on the preset parallelism and the state relation matrices of the two pseudo-random sequences. In some embodiments, taking the state relation matrix of the pseudo-random sequence as the base number and the preset parallelism as the exponent, the recurrence relation matrix of the pseudo-random sequence is obtained. Exemplarily, assuming that the preset parallelism is P, the recurrence relation matrix of the pseudo-random sequence can be calculated by T P is obtained. Exemplarily, assuming that the preset parallelism is P, the state relation matrix of sequence 1 is T1, and the state relation matrix of sequence 2 is T2, then the recurrence relation matrix of sequence 1 is T1 P , and the recurrence relation matrix of sequence 2 is T2 P 。 Sc2. Obtain the scrambling sequences corresponding to the two pseudo-random sequences respectively based on the recurrence relation matrices of the two pseudo-random sequences and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in the fixed delay state. In some embodiments, the products of the recurrence relation matrices of the two pseudo-random sequences and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in the fixed delay state are respectively calculated to obtain the scrambling sequences corresponding to the two pseudo-random sequences. Exemplarily, assuming that the initial value of the scrambling recurrence sequence of the pseudo-random sequence in the fixed delay state is represented as A i (where i represents the fixed delay), then the scrambling sequence corresponding to the pseudo-random sequence can be represented as T P *A i 。Exemplarily, the recurrence relation matrix of sequence 1 can be represented as T1 P , and the initial value of the scrambling recurrence sequence of sequence 1 in the fixed delay state is represented as A1 i , then the scrambling sequence corresponding to sequence 1 can be represented as T1 P *A1 i。The recurrence relation matrix of Sequence 2 can be expressed as T2 P ,The initial value of the scrambling recurrence sequence of Sequence 2 in the fixed time delay state is expressed as A2 i ,Then the scrambling sequence corresponding to Sequence 2 can be expressed as T2 P *A2 i 。 It can be understood that the embodiments of the present application provide a processing method in the case where the parallelism is less than or equal to 31, which can meet the requirements of different communication systems for different parallelisms, provides a processing method in the case where the parallelism is less than or equal to 31, and improves the applicability and flexibility of the scrambling sequence. S102. Obtain a parallel scrambling sequence based on the scrambling sequences corresponding to two pseudo-random sequences respectively. In some embodiments, the above step S102 can be implemented as: performing a bitwise exclusive OR operation on the scrambling sequences corresponding to two pseudo-random sequences respectively to obtain a parallel scrambling sequence. It can be understood that the bitwise exclusive OR operation can improve security and increase randomness. Exemplarily, assume that the scrambling sequence corresponding to Sequence 1 is T1 P *A1 i ,The scrambling sequence corresponding to Sequence 2 is T2 P *A2 i 。Then perform a bitwise exclusive OR operation on T1 P *A1 i and T2 P *A2 i to obtain a parallel scrambling sequence. It can be understood that based on the scrambling sequence generation method provided by the embodiments of the present application, the scrambling sequences corresponding to two pseudo-random sequences can be determined based on a preset parallelism, the state relation matrices of the two pseudo-random sequences respectively, and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in the fixed time delay state; then, a parallel scrambling sequence is obtained based on the scrambling sequences corresponding to the two pseudo-random sequences respectively; wherein, the preset parallelism has different values under different communication systems to obtain a parallel scrambling sequence applicable to the communication system. In this way, the processing rate of scrambling or descrambling can be improved, the consumption of hardware resources can be reduced, the system processing time can be reduced, and the system communication delay can be reduced. For ease of understanding, the scrambling sequence generation method provided by the embodiments of the present application will be described below by way of example. Exemplarily, as shown in FIG. 9, the process of obtaining a parallel scrambling sequence based on pseudo-random sequence 1 and pseudo-random sequence 2 is as follows: First, based on the generating polynomial 1 of pseudo-random sequence 1, the state relation matrix T1 of pseudo-random sequence 1 is obtained; then, based on the generating polynomial of pseudo-random sequence 1 and a fixed time delay, the fixed-time-delay state relation matrix of pseudo-random sequence 1 is obtained; then, the initial vector of pseudo-random sequence 1 and the fixed-time-delay state relation matrix T1 of pseudo-random sequence 1 1600 , to obtain the initial value A1 of the scrambled recurrence sequence of pseudo-random sequence 1 in the fixed-time-delay state 1600 ; Further, based on a preset parallelism and the state relation matrix of pseudo-random sequence 1, the recurrence relation matrix T of pseudo-random sequence 1 is obtained P ; Finally, based on the recurrence relation matrix of pseudo-random sequence 1 and the initial value of the scrambled recurrence sequence of pseudo-random sequence 1 in the fixed-time-delay state, the scrambled sequence of pseudo-random sequence 1 is obtained. Based on the same processing method, the scrambled sequence of pseudo-random sequence 2 is obtained, and then the scrambled sequences of pseudo-random sequence 1 and pseudo-random sequence 2 are subjected to a bitwise exclusive OR operation to obtain a parallel scrambling sequence. In some embodiments, as shown in FIG. 10, the process of scrambling based on the parallel scrambling sequence can be implemented as the following steps: S301. Obtain the data to be scrambled. S302. Based on the parallel scrambling sequence, scramble the data to be scrambled to obtain scrambled data. In some embodiments, as shown in FIG. 11, when scrambling, first, the data to be scrambled needs to be converted into parallel data with the same parallelism as the scrambling sequence through data serial-to-parallel conversion, and then the parallel data of the data to be scrambled and the parallel scrambling sequence are subjected to an exclusive OR operation according to the corresponding bit positions, and finally the scrambled data is obtained. It can be understood that the embodiments of the present application can scramble according to the parallel scrambling sequence generated by the above steps S101-S102 to improve the scrambling rate. In some embodiments, as shown in FIG. 12, the process of descrambling based on the parallel scrambling sequence can be implemented as the following steps: S401. Obtain the data to be descrambled. It can be understood that the data to be descrambled can be the scrambled data. S402. Based on the parallel scrambling sequence, descramble the data to be descrambled to obtain descrambled data. In some embodiments, during descrambling, different descrambling methods are used for data with different demodulation methods. For example, as shown in FIG. 13, for the parallel bit data after hard demodulation, the descrambling and scrambling processes are the same, and the descrambled data can be obtained by performing an exclusive OR operation on the corresponding bit positions; as shown in FIG. 14, for the soft demodulation multi-channel parallel data, it is necessary to determine whether the soft demodulated data needs to be inverted through the scrambling sequence, that is, if the corresponding bit of the scrambling code is 0, the descrambled data remains unchanged, and if the corresponding bit of the scrambling code is 1, the descrambled data is inverted. It can be understood that the embodiments of the present application can perform descrambling according to the parallel scrambling sequence generated in the above steps S101 - S102 to improve the descrambling rate. For ease of understanding, the following uses communication scenarios with different values of the preset parallelism as examples to illustrate the scrambling sequence generation method provided by the embodiments of the present application. Scenario 1: The preset parallelism P = 1, that is, serial scrambling or descrambling. In some embodiments, when the preset parallelism P = 1 and running at a 200M clock, a processing rate of 200Mbps can be achieved. Exemplarily, in Scenario 1, the above scrambling sequence generation method can be implemented as the following steps: Step d1: Obtain the initial vectors of the two pseudo - random sequences respectively. Among them, the initial vector value of Sequence 1 is A10 = (1, 0, 0,..., 0), and the initial vector value of Sequence 2 is a variable, which can take different values according to different usage scenarios. To maintain generality in the system, the initial vector value of Sequence 2 can be represented by a variable as A20 = (a0, a1, a2,..., a 30 ) Step d2: Determine the fixed - delay state - relation matrices of the two pseudo - random sequences respectively according to the state - relation matrices and fixed delays of the two pseudo - random sequences. Among them, the state - relation matrix T of the above pseudo - random sequence needs to be determined according to the generating polynomial of the pseudo - random sequence. Step d3: Obtain the initial values of the scrambling recurrence sequences of the two pseudo - random sequences in the fixed - delay state according to the initial vectors of the two pseudo - random sequences and the fixed - delay state - relation matrices of the two pseudo - random sequences. Exemplarily, for Sequence 1, through the formula A1 1600 = T1 1600 * A10 T , calculate the initial value A1 of the scrambling recurrence sequence of Sequence 1 in the fixed - delay state 1600=(0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 0 0 0 0 1 0 0 1 0 0 1 1 1 1 0 1). In the implementation of a Field-Programmable Gate Array (FPGA), the recursive initial register corresponding to sequence 1 is: seq1_scrb = 31’b1011110010010000101100001000000. For sequence 2, through formula A2 1600 = T2 1600 * A20 T , the initial value A2 of the scrambling recursive sequence of sequence 2 in the fixed time-delay state is calculated 1600 It can be expressed in the form shown in Figure 15. In the FPGA implementation, the recursive initial register corresponding to sequence 2 is: seq2_scrb(0) <= a1 ^ a2 ^ a3 ^ a8 ^ a12 ^ a16 ^ a19 ^ a20 ^ a23; seq2_scrb(1) <= a2 ^ a3 ^ a4 ^ a9 ^ a13 ^ a17 ^ a20 ^ a21 ^ a24; seq2_scrb(2) <= a3 ^ a4 ^ a5 ^ a10 ^ a14 ^ a18 ^ a21 ^ a22 ^ a25; seq2_scrb(3) <= a4 ^ a5 ^ a6 ^ a11 ^ a15 ^ a19 ^ a22 ^ a23 ^ a26; seq2_scrb(4) <= a5 ^ a6 ^ a7 ^ a12 ^ a16 ^ a20 ^ a23 ^ a24 ^ a27; seq2_scrb(5) <= a6 ^ a7 ^ a8 ^ a13 ^ a17 ^ a21 ^ a24 ^ a25 ^ a28; seq2_scrb(6) <= a7 ^ a8 ^ a9 ^ a14 ^ a18 ^ a22 ^ a25 ^ a26 ^ a29; seq2_scrb(7) <= a8 ^ a9 ^ a10 ^ a15 ^ a19 ^ a23 ^ a26 ^ a27 ^ a30; seq2_scrb(8) <= a0 ^ a1 ^ a2 ^ a3 ^ a9 ^ a10 ^ a11 ^ a16 ^ a20 ^ a24 ^ a27 ^ a28; seq2_scrb(9) <= a1 ^ a2 ^ a3 ^ a4 ^ a10 ^ a11 ^ a12 ^ a17 ^ a21 ^ a25 ^ a28 ^ a29; seq2_scrb(10) <= a2 ^ a3 ^ a4 ^ a5 ^ a11 ^ a12 ^ a13 ^ a18 ^ a22 ^ a26 ^ a29 ^ a30; seq2_scrb(11) <= a0 ^ a1 ^ a2 ^ a4 ^ a5 ^ a6 ^ a12 ^ a13 ^ a14 ^ a19 ^ a23 ^ a27 ^ a30; seq2_scrb(12) <= a0 ^ a5 ^ a6 ^ a7 ^ a13 ^ a14 ^ a15 ^ a20 ^ a24 ^ a28; seq2_scrb(13) <= a1 ^ a6 ^ a7 ^ a8 ^ a14 ^ a15 ^ a16 ^ a21 ^ a25 ^ a29; seq2_scrb(14) <= a2 ^ a7 ^ a8 ^ a9 ^ a15 ^ a16 ^ a17 ^ a22 ^ a26 ^ a30; seq2_scrb(15) <= a0 ^ a1 ^ a2 ^ a8 ^ a9 ^ a10 ^ a16 ^ a17 ^ a18 ^ a23 ^ a27; seq2_scrb(16) <= a1 ^ a2 ^ a3 ^ a9 ^ a10 ^ a11 ^ a17 ^ a18 ^ a19 ^ a24 ^ a28; seq2_scrb(17) <= a2 ^ a3 ^ a4 ^ a10 ^ a11 ^ a12 ^ a18 ^ a19 ^ a20 ^ a25 ^ a29; seq2_scrb(18) <= a3 ^ a4 ^ a5 ^ a11 ^ a12 ^ a13 ^ a19 ^ a20 ^ a21 ^ a26 ^ a30; seq2_scrb(19) <= a0 ^ a1 ^ a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a12 ^ a13 ^ a14 ^ a20 ^ a21 ^ a22 ^ a27; seq2_scrb(20) <= a1 ^ a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a13 ^ a14 ^ a15 ^ a21 ^ a22 ^ a23 ^ a28; seq2_scrb(21) <= a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a14 ^ a15 ^ a16 ^ a22 ^ a23 ^ a24 ^ a29; seq2_scrb(22) <= a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a15 ^ a16 ^ a17 ^ a23 ^ a24 ^ a25 ^ a30; seq2_scrb(23) <= a0 ^ a1 ^ a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a16 ^ a17 ^ a18 ^ a24 ^ a25 ^ a26; seq2_scrb(24) <= a1 ^ a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a17 ^ a18 ^ a19 ^ a25 ^ a26 ^ a27; seq2_scrb(25) <= a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a18 ^ a19 ^ a20 ^ a26 ^ a27 ^ a28; seq2_scrb(26) <= a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a13 ^ a19 ^ a20 ^ a21 ^ a27 ^ a28 ^ a29; seq2_scrb(27) <= a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a13 ^ a14 ^ a20 ^ a21 ^ a22 ^ a28 ^ a29 ^ a30; seq2_scrb(28) <= a0 ^ a1 ^ a2 ^ a3 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a13 ^ a14 ^ a15 ^ a21 ^ a22 ^ a23 ^ a29 ^ a30; seq2_scrb(29) <= a0 ^ a4 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a13 ^ a14 ^ a15 ^ a16 ^ a22 ^ a23 ^ a24 ^ a30; seq2_scrb(30) <= a0 ^ a2 ^ a3 ^ a5 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a13 ^ a14 ^ a15 ^ a16 ^ a17 ^ a23 ^ a24 ^ a25. Step d4: According to the initial values of the scrambling code recurrence sequences of the two pseudo-random sequences in the fixed time delay state, the scrambling code sequences corresponding to the two pseudo-random sequences are recursively deduced in real time in parallel. Exemplarily, for the case of parallelism P = 1, TP in the formula TP * Ai is TP = T, and then the scrambling code sequence can be obtained based on T * Ai. For sequence 1, the recurrence vector formula is: A1 i+1 = T1 * A1 i T . The implementation relationship of sequence 1 in FPGA is: seq1_scrb[29:0] <= seq1_scrb[30:1]; seq1_scrb

[0030] <= seq1_scrb[0] ^ seq1_scrb[3]. For sequence 2, the recurrence vector formula is: A2 i+1= T2 * A2 i T For the implementation relationship of Sequence 2 in FPGA: seq2_scrb[29:0] <= seq2_scrb[30:1]; seq2_scrb

[0030] <= seq2_scrb[0] ^ seq2_scrb[1] ^ seq2_scrb[2] ^ seq2_scrb[3]. Step d5: Exclusive - OR the scrambling sequences corresponding to the two pseudo - random sequences bit - by - bit to obtain a parallel scrambling sequence. Exemplarily, for the case where the parallelism P is 1, the real - time scrambling sequence of Sequence 1 is seq1_scrb[0]; the real - time scrambling sequence of Sequence 2 is seq2_scrb[0]. Then, the parallel scrambling sequence is obtained through exclusive - OR operation. The FPGA implementation of the parallel scrambling sequence is: seq_scrb <= seq1_scrb[0] ^ seq2_scrb[0]. Step d6: Perform scrambling and descrambling based on the parallel scrambling sequence. Exemplarily, for scrambling with parallelism P = 1, the scrambled data is obtained by exclusive - OR operation of the data to be scrambled and the parallel scrambling sequence. The FPGA implementation of the scrambled data is: data_scrb <= seq_scrb ^ data. For descrambling with parallelism 1, during hard demodulation, the descrambled data is obtained by exclusive - OR operation of the data and the scrambling code. The FPGA implementation of the descrambled data is: data <= seq_scrb ^ data_scrb. For soft - demodulated data, it is determined whether the soft - demodulated data needs to be inverted through the scrambling sequence, that is, when the corresponding bit of the scrambling code is 0, the descrambled data remains unchanged; when the corresponding bit of the scrambling code is 1, the descrambled data is inverted. Scenario 2: Preset parallelism P = 2. In some embodiments, in the case of preset parallelism P = 2 and running at a 200M clock, a processing rate of 400Mbps can be achieved, and 2 - way parallelism can be directly used for a communication system with a Quadrature Phase Shift Keying (QPSK) modulation method. Exemplarily, in Scenario 2, the above scrambling sequence generation method can be implemented as the following steps: Step e1: Obtain the initial vectors of the two pseudo - random sequences respectively. Among them, the initial vector value of Sequence 1 is A10 = (1, 0, 0, …, 0), and the initial vector value of Sequence 2 is a variable, which can take different values according to different usage scenarios. To maintain generality in the system, the initial vector value of Sequence 2 can be represented by a variable as A20 = (a0, a1, a2, …, a 30 ). Step e2: Determine the fixed-delay state relationship matrices of the two pseudo-random sequences according to the state relationship matrices and fixed delays of the two pseudo-random sequences respectively. Among them, the state relationship matrix T of the above pseudo-random sequence needs to be determined according to the generating polynomial of the pseudo-random sequence. Step e3: Obtain the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in the fixed-delay state according to the initial vectors of the two pseudo-random sequences and the fixed-delay state relationship matrices of the two pseudo-random sequences respectively. Exemplarily, for Sequence 1, through the formula A1 1600 = T1 1600 * A10 T , calculate the initial value A1 1600 = (0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 0 0 0 0 1 0 0 1 0 0 1 1 1 1 0 1) of the scrambling recurrence sequence of Sequence 1 in the fixed-delay state. In the FPGA implementation, the corresponding recurrence initial register for Sequence 1 is: seq1_scrb = 31’b1011110010010000101100001000000. For Sequence 2, through the formula A2 1600 = T2 1600 * A20 T , calculate the initial value A2 1600 of the scrambling recurrence sequence of Sequence 2 in the fixed-delay state, which can be represented in the form shown in Figure 15. In the FPGA implementation, the corresponding recurrence initial register for Sequence 2 is: seq2_scrb(0) <= a1^a2^a3^a8^a12^a16^a19^a20^a23; seq2_scrb(1) <= a2^a3^a4^a9^a13^a17^a20^a21^a24; seq2_scrb(2) <= a3^a4^a5^a10^a14^a18^a21^a22^a25; seq2_scrb(3) <= a4^a5^a6^a11^a15^a19^a22^a23^a26; seq2_scrb(4) <= a5 ^ a6 ^ a7 ^ a12 ^ a16 ^ a20 ^ a23 ^ a24 ^ a27; seq2_scrb(5) <= a6 ^ a7 ^ a8 ^ a13 ^ a17 ^ a21 ^ a24 ^ a25 ^ a28; seq2_scrb(6) <= a7 ^ a8 ^ a9 ^ a14 ^ a18 ^ a22 ^ a25 ^ a26 ^ a29; seq2_scrb(7) <= a8 ^ a9 ^ a10 ^ a15 ^ a19 ^ a23 ^ a26 ^ a27 ^ a30; seq2_scrb(8) <= a0 ^ a1 ^ a2 ^ a3 ^ a9 ^ a10 ^ a11 ^ a16 ^ a20 ^ a24 ^ a27 ^ a28; seq2_scrb(9) <= a1 ^ a2 ^ a3 ^ a4 ^ a10 ^ a11 ^ a12 ^ a17 ^ a21 ^ a25 ^ a28 ^ a29; seq2_scrb(10) <= a2 ^ a3 ^ a4 ^ a5 ^ a11 ^ a12 ^ a13 ^ a18 ^ a22 ^ a26 ^ a29 ^ a30; seq2_scrb(11) <= a0 ^ a1 ^ a2 ^ a4 ^ a5 ^ a6 ^ a12 ^ a13 ^ a14 ^ a19 ^ a23 ^ a27 ^ a30; seq2_scrb(12) <= a0 ^ a5 ^ a6 ^ a7 ^ a13 ^ a14 ^ a15 ^ a20 ^ a24 ^ a28; seq2_scrb(13) <= a1 ^ a6 ^ a7 ^ a8 ^ a14 ^ a15 ^ a16 ^ a21 ^ a25 ^ a29; seq2_scrb(14) <= a2 ^ a7 ^ a8 ^ a9 ^ a15 ^ a16 ^ a17 ^ a22 ^ a26 ^ a30; seq2_scrb(15) <= a0 ^ a1 ^ a2 ^ a8 ^ a9 ^ a10 ^ a16 ^ a17 ^ a18 ^ a23 ^ a27; seq2_scrb(16) <= a1 ^ a2 ^ a3 ^ a9 ^ a10 ^ a11 ^ a17 ^ a18 ^ a19 ^ a24 ^ a28; seq2_scrb(17) <= a2 ^ a3 ^ a4 ^ a10 ^ a11 ^ a12 ^ a18 ^ a19 ^ a20 ^ a25 ^ a29; seq2_scrb(18) <= a3 ^ a4 ^ a5 ^ a11 ^ a12 ^ a13 ^ a19 ^ a20 ^ a21 ^ a26 ^ a30; seq2_scrb(19) <= a0 ^ a1 ^ a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a12 ^ a13 ^ a14 ^ a20 ^ a21 ^ a22 ^ a27; seq2_scrb(20) <= a1 ^ a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a13 ^ a14 ^ a15 ^ a21 ^ a22 ^ a23 ^ a28; seq2_scrb(21) <= a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a14 ^ a15 ^ a16 ^ a22 ^ a23 ^ a24 ^ a29; seq2_scrb(22) <= a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a15 ^ a16 ^ a17 ^ a23 ^ a24 ^ a25 ^ a30; seq2_scrb(23) <= a0 ^ a1 ^ a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a16 ^ a17 ^ a18 ^ a24 ^ a25 ^ a26; seq2_scrb(24) <= a1 ^ a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a17 ^ a18 ^ a19 ^ a25 ^ a26 ^ a27; seq2_scrb(25) <= a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a18 ^ a19 ^ a20 ^ a26 ^ a27 ^ a28; seq2_scrb(26) <= a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a13 ^ a19 ^ a20 ^ a21 ^ a27 ^ a28 ^ a29; seq2_scrb(27) <= a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a13 ^ a14 ^ a20 ^ a21 ^ a22 ^ a28 ^ a29 ^ a30; seq2_scrb(28) <= a0 ^ a1 ^ a2 ^ a3 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a13 ^ a14 ^ a15 ^ a21 ^ a22 ^ a23 ^ a29 ^ a30; seq2_scrb(29) <= a0 ^ a4 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a13 ^ a14 ^ a15 ^ a16 ^ a22 ^ a23 ^ a24 ^ a30; seq2_scrb(30) <= a0 ^ a2 ^ a3 ^ a5 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a13 ^ a14 ^ a15 ^ a16 ^ a17 ^ a23 ^ a24 ^ a25. Step e4: According to the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in the fixed time delay state, the scrambling sequences of the two pseudo-random sequences are recursively derived in real time in parallel. Exemplarily, for the case of parallelism P = 2, the recurrence vector formula of sequence 1 is: A1 i+1 = T1 2 * A1 i T . The implementation relationship of sequence 1 in FPGA is: seq1_scrb[28:0] <= seq1_scrb[30:2]; seq1_scrb

[0029] <= seq1_scrb[0] ^ seq1_scrb[3]; seq1_scrb

[0030] <= seq1_scrb[1] ^ seq1_scrb[4]. The recurrence vector formula of sequence 2 is: A2 i+1 = T2 2 * A2 i T . For the implementation relationship of sequence 2 in FPGA: seq2_scrb[28:0] <= seq2_scrb[30:2]; seq2_scrb

[0029] <= seq2_scrb[0] ^ seq2_scrb[1] ^ seq2_scrb[2] ^ seq2_scrb[3]; seq2_scrb

[0030] <= seq2_scrb[1] ^ seq2_scrb[2] ^ seq2_scrb[3] ^ seq2_scrb[4]. Step e5: Bitwise XOR the scrambling sequences corresponding to the two pseudo-random sequences to obtain the parallel scrambling sequence. Exemplarily, for the case of parallelism P = 1, the real-time scrambling sequence of sequence 1 is seq1_scrb[1:0]; the real-time scrambling sequence of sequence 2 is seq2_scrb[1:0], and then the parallel scrambling sequence is obtained through bitwise XOR operation. The FPGA implementation of the parallel scrambling sequence is: seq_scrb <= seq1_scrb[1:0] ^ seq2_scrb[1:0]. Step e6: Perform scrambling and descrambling based on the parallel scrambling sequence. Exemplarily, for scrambling with a parallelism P of 2, the scrambled data is obtained by performing a bitwise exclusive OR operation on the data to be scrambled and the parallel scrambling code sequence. The FPGA implementation of the scrambled data is: data_scrb <= seq_scrb ^ data. For descrambling with a parallelism of 2, during hard demodulation, the descrambled data is obtained by performing a bitwise exclusive OR operation on the data and the scrambling code. The FPGA implementation of the descrambled data is: data <= seq_scrb ^ data_scrb. For soft demodulation data, it is determined whether the soft demodulation data needs to be inverted through the scrambling code sequence, that is, when the corresponding bit of the scrambling code is 0, the descrambled data remains unchanged, and when the corresponding bit of the scrambling code is 1, the descrambled data is inverted. Scenario three: The preset parallelism P is 16. In some embodiments, in the case where the preset parallelism P = 16 and running at a 200M clock, a processing rate of 3200Mbps can be achieved, which can meet the transmission rates of most communication systems. Exemplarily, in scenario three, the above scrambling code sequence generation method can be implemented as the following steps: Step f1: Obtain the initial vectors of the two pseudo-random sequences respectively. Among them, the initial vector value of sequence 1 is A10 = (1, 0, 0,..., 0), and the initial vector value of sequence 2 is a variable, which can take different values according to different usage scenarios. To maintain generality in the system, the initial vector value of sequence 2 can be represented by a variable as A20 = (a0, a1, a2,..., a 30 ). Step f2: Determine the fixed-delay state relationship matrices of the two pseudo-random sequences respectively according to the state relationship matrices and fixed delays of the two pseudo-random sequences. Among them, the state relationship matrix T of the above pseudo-random sequence needs to be determined according to the generating polynomial of the pseudo-random sequence. Step f3: Obtain the initial values of the scrambling code recurrence sequences of the two pseudo-random sequences in the fixed-delay state according to the initial vectors of the two pseudo-random sequences and the fixed-delay state relationship matrices of the two pseudo-random sequences. Exemplarily, for sequence 1, through the formula A1 1600 = T1 1600 * A10 T , the initial value A1 of the scrambling code recurrence sequence of sequence 1 in the fixed-delay state is calculated 1600 = (0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 0 0 0 0 1 0 0 1 0 0 1 1 1 1 0 1). In the FPGA implementation, the recurrence initial register corresponding to sequence 1 is: seq1_scrb = 31’b1011110010010000101100001000000。 For sequence 2, through formula A2 1600 = T2 1600 * A20 T , the initial value A2 of the scrambling code recurrence sequence of sequence 2 in the fixed time delay state is calculated 1600 It can be expressed in the form shown in Figure 15. In the FPGA implementation, the recurrence initial register corresponding to sequence 2 is as follows: seq2_scrb(0) <= a1 ^ a2 ^ a3 ^ a8 ^ a12 ^ a16 ^ a19 ^ a20 ^ a23; seq2_scrb(1) <= a2 ^ a3 ^ a4 ^ a9 ^ a13 ^ a17 ^ a20 ^ a21 ^ a24; seq2_scrb(2) <= a3 ^ a4 ^ a5 ^ a10 ^ a14 ^ a18 ^ a21 ^ a22 ^ a25; seq2_scrb(3) <= a4 ^ a5 ^ a6 ^ a11 ^ a15 ^ a19 ^ a22 ^ a23 ^ a26; seq2_scrb(4) <= a5 ^ a6 ^ a7 ^ a12 ^ a16 ^ a20 ^ a23 ^ a24 ^ a27; seq2_scrb(5) <= a6 ^ a7 ^ a8 ^ a13 ^ a17 ^ a21 ^ a24 ^ a25 ^ a28; seq2_scrb(6) <= a7 ^ a8 ^ a9 ^ a14 ^ a18 ^ a22 ^ a25 ^ a26 ^ a29; seq2_scrb(7) <= a8 ^ a9 ^ a10 ^ a15 ^ a19 ^ a23 ^ a26 ^ a27 ^ a30; seq2_scrb(8) <= a0 ^ a1 ^ a2 ^ a3 ^ a9 ^ a10 ^ a11 ^ a16 ^ a20 ^ a24 ^ a27 ^ a28; seq2_scrb(9) <= a1 ^ a2 ^ a3 ^ a4 ^ a10 ^ a11 ^ a12 ^ a17 ^ a21 ^ a25 ^ a28 ^ a29; seq2_scrb(10) <= a2 ^ a3 ^ a4 ^ a5 ^ a11 ^ a12 ^ a13 ^ a18 ^ a22 ^ a26 ^ a29 ^ a30; seq2_scrb(11) <= a0 ^ a1 ^ a2 ^ a4 ^ a5 ^ a6 ^ a12 ^ a13 ^ a14 ^ a19 ^ a23 ^ a27 ^ a30; seq2_scrb(12) <= a0 ^ a5 ^ a6 ^ a7 ^ a13 ^ a14 ^ a15 ^ a20 ^ a24 ^ a28; seq2_scrb(13) <= a1 ^ a6 ^ a7 ^ a8 ^ a14 ^ a15 ^ a16 ^ a21 ^ a25 ^ a29; seq2_scrb(14) <= a2 ^ a7 ^ a8 ^ a9 ^ a15 ^ a16 ^ a17 ^ a22 ^ a26 ^ a30; seq2_scrb(15) <= a0 ^ a1 ^ a2 ^ a8 ^ a9 ^ a10 ^ a16 ^ a17 ^ a18 ^ a23 ^ a27; seq2_scrb(16) <= a1 ^ a2 ^ a3 ^ a9 ^ a10 ^ a11 ^ a17 ^ a18 ^ a19 ^ a24 ^ a28; seq2_scrb(17) <= a2 ^ a3 ^ a4 ^ a10 ^ a11 ^ a12 ^ a18 ^ a19 ^ a20 ^ a25 ^ a29; seq2_scrb(18) <= a3 ^ a4 ^ a5 ^ a11 ^ a12 ^ a13 ^ a19 ^ a20 ^ a21 ^ a26 ^ a30; seq2_scrb(19) <= a0 ^ a1 ^ a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a12 ^ a13 ^ a14 ^ a20 ^ a21 ^ a22 ^ a27; seq2_scrb(20) <= a1 ^ a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a13 ^ a14 ^ a15 ^ a21 ^ a22 ^ a23 ^ a28; seq2_scrb(21) <= a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a14 ^ a15 ^ a16 ^ a22 ^ a23 ^ a24 ^ a29; seq2_scrb(22) <= a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a15 ^ a16 ^ a17 ^ a23 ^ a24 ^ a25 ^ a30; seq2_scrb(23) <= a0 ^ a1 ^ a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a16 ^ a17 ^ a18 ^ a24 ^ a25 ^ a26; seq2_scrb(24) <= a1 ^ a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a17 ^ a18 ^ a19 ^ a25 ^ a26 ^ a27; seq2_scrb(25) <= a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a18 ^ a19 ^ a20 ^ a26 ^ a27 ^ a28; seq2_scrb(26) <= a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a13 ^ a19 ^ a20 ^ a21 ^ a27 ^ a28 ^ a29; seq2_scrb(27) <= a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a13 ^ a14 ^ a20 ^ a21 ^ a22 ^ a28 ^ a29 ^ a30; seq2_scrb(28) <= a0 ^ a1 ^ a2 ^ a3 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a13 ^ a14 ^ a15 ^ a21 ^ a22 ^ a23 ^ a29 ^ a30; seq2_scrb(29) <= a0 ^ a4 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a13 ^ a14 ^ a15 ^ a16 ^ a22 ^ a23 ^ a24 ^ a30; seq2_scrb(30) <= a0 ^ a2 ^ a3 ^ a5 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a13 ^ a14 ^ a15 ^ a16 ^ a17 ^ a23 ^ a24 ^ a25. Step f4: According to the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in the fixed delay state, the scrambling sequences of the two pseudo-random sequences are recursively derived in real time in parallel. Exemplarily, for the case of parallelism P = 16, the recurrence vector formula of sequence 1 is: A1 i+1 = T1 16 * A1 i T . The implementation relationship of sequence 1 in FPGA is: seq1_scrb[14:0] <= seq1_scrb[30:16]; seq1_scrb

[0015] <= seq1_scrb[0] ^ seq1_scrb[3]; seq1_scrb

[0016] <= seq1_scrb[1] ^ seq1_scrb[4]; seq1_scrb

[0017] <= seq1_scrb[2] ^ seq1_scrb[5]; seq1_scrb

[0018] <= seq1_scrb[3] ^ seq1_scrb[6]; seq1_scrb

[0019] <= seq1_scrb[4] ^ seq1_scrb[7]; seq1_scrb

[0020] <= seq1_scrb[5] ^ seq1_scrb[8]; seq1_scrb

[0021] <= seq1_scrb[6] ^ seq1_scrb[9]; seq1_scrb

[0022] <= seq1_scrb[7] ^ seq1_scrb

[0010] ; seq1_scrb

[0023] <= seq1_scrb[8] ^ seq1_scrb

[0011] ; seq1_scrb

[0024] <= seq1_scrb[9] ^ seq1_scrb

[0012] ; seq1_scrb

[0025] <= seq1_scrb

[0010] ^ seq1_scrb

[0013] ; seq1_scrb

[0026] <= seq1_scrb

[0011] ^ seq1_scrb

[0014] ; seq1_scrb

[0027] <= seq1_scrb

[0012] ^ seq1_scrb

[0015] ; seq1_scrb

[0028] <= seq1_scrb

[0013] ^ seq1_scrb

[0016] ; seq1_scrb

[0029] <= seq1_scrb

[0014] ^ seq1_scrb

[0017] ; seq1_scrb

[0030] <= seq1_scrb

[0015] ^ seq1_scrb

[0018] . The recurrence vector formula for Sequence 2 is: A2 i+1 = T2 16 * A2 i T . For the implementation relationship of Sequence 2 in FPGA: seq2_scrb[14:0] <= seq2_scrb[30:16]; seq2_scrb

[0015] <= seq2_scrb[0] ^ seq2_scrb[1] ^ seq2_scrb[2] ^ seq2_scrb[3]; seq2_scrb

[0016] <= seq2_scrb[1] ^ seq2_scrb[2] ^ seq2_scrb[3] ^ seq2_scrb[4]; seq2_scrb

[0017] <= seq2_scrb[2] ^ seq2_scrb[3] ^ seq2_scrb[4] ^ seq2_scrb[5]; seq2_scrb

[0018] <= seq2_scrb[3] ^ seq2_scrb[4] ^ seq2_scrb[5] ^ seq2_scrb[6]; seq2_scrb

[0019] <= seq2_scrb[4] ^ seq2_scrb[5] ^ seq2_scrb[6] ^ seq2_scrb[7]; seq2_scrb

[0020] <= seq2_scrb[5] ^ seq2_scrb[6] ^ seq2_scrb[7] ^ seq2_scrb[8]; seq2_scrb

[0021] <= seq2_scrb[6] ^ seq2_scrb[7] ^ seq2_scrb[8] ^ seq2_scrb[9]; seq2_scrb

[0022] <= seq2_scrb[7] ^ seq2_scrb[8] ^ seq2_scrb[9] ^ seq2_scrb

[0010] ; seq2_scrb

[0023] <= seq2_scrb[8] ^ seq2_scrb[9] ^ seq2_scrb

[0010] ^ seq2_scrb

[0011] ; seq2_scrb

[0024] <= seq2_scrb[9] ^ seq2_scrb

[0010] ^ seq2_scrb

[0011] ^ seq2_scrb

[0012] ; seq2_scrb

[0025] <= seq2_scrb

[0010] ^ seq2_scrb

[0011] ^ seq2_scrb

[0012] ^ seq2_scrb

[0013] ; seq2_scrb

[0026] <= seq2_scrb

[0011] ^ seq2_scrb

[0012] ^ seq2_scrb

[0013] ^ seq2_scrb

[0014] ; seq2_scrb

[0027] <=seq2_scrb

[0012] ^seq2_scrb

[0013] ^seq2_scrb

[0014] ^seq2_scrb

[0015] ; seq2_scrb

[0028] <=seq2_scrb

[0013] ^seq2_scrb

[0014] ^seq2_scrb

[0015] ^seq2_scrb

[0016] ; seq2_scrb

[0029] <=seq2_scrb

[0014] ^seq2_scrb

[0015] ^seq2_scrb

[0016] ^seq2_scrb

[0017] ; seq2_scrb

[0030] <=seq2_scrb

[0015] ^seq2_scrb

[0016] ^seq2_scrb

[0017] ^seq2_scrb

[0018] . Step f5: Bitwise XOR the scrambling sequences corresponding to the two pseudo-random sequences to obtain a parallel scrambling sequence. Exemplarily, for the case where the parallelism P is 16, the real-time scrambling sequence of sequence 1 is seq1_scrb[15:0]; the real-time scrambling sequence of sequence 2 is seq2_scrb[15:0], and then the parallel scrambling sequence is obtained through bitwise XOR operation. The FPGA implementation of the parallel scrambling sequence is: seq_scrb<=seq1_scrb[15:0]^seq2_scrb[15:0]. Step f6: Perform scrambling and descrambling based on the parallel scrambling sequence. Exemplarily, for the scrambling with a parallelism P of 16, the data to be scrambled is XORed with the parallel scrambling sequence bitwise to obtain the scrambled data. The FPGA implementation of the scrambled data is: data_scrb<=seq_scrb^data. For the descrambling with a parallelism of 16, during hard demodulation, the descrambled data is obtained by XORing the data with the scrambling code bitwise. The FPGA implementation of the descrambled data is: data<=seq_scrb^data_scrb. For soft demodulation data, it is determined whether the soft demodulation data needs to be inverted through the scrambling sequence, that is, when the corresponding bit of the scrambling code is 0, the data after descrambling remains unchanged; when the corresponding bit of the scrambling code is 1, the data after descrambling is inverted. Scenario 4: The preset parallelism P is greater than 31. In some embodiments, for the scenario where the preset parallelism P is greater than 31, the embodiments of the present application take the preset parallelism P = 32 as an example for illustration. In the case of P = 32 and running at a 200M clock, a processing rate of 6400 Mbps can be achieved, which can meet the transmission rates of most communication systems. Exemplarily, in Scenario 4, the above scrambling sequence generation method can be implemented as the following steps: Step g1, obtain the initial vectors of the two pseudo-random sequences respectively. Among them, the initial vector value of Sequence 1 is A10 = (1, 0, 0,..., 0), and the initial vector value of Sequence 2 is a variable, which can take different values according to different usage scenarios. To maintain generality in the system, the initial vector value of Sequence 2 can be represented by a variable as A20 = (a0, a1, a2,..., a 30 ). Step g2, determine the fixed-delay state relationship matrices of the two pseudo-random sequences respectively according to the state relationship matrices and fixed delays of the two pseudo-random sequences. Among them, the state relationship matrix T of the above pseudo-random sequence needs to be determined according to the generation polynomial of the pseudo-random sequence. Step g3, obtain the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in the fixed-delay state according to the initial vectors of the two pseudo-random sequences and the fixed-delay state relationship matrices of the two pseudo-random sequences respectively. Exemplarily, for Sequence 1, through the formula A1 1600 = T1 1600 * A10 T , calculate the initial value A1 of the first group of scrambling recurrence sequences of Sequence 1 in the fixed-delay state 1600 = (0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 0 0 0 0 1 0 0 1 0 0 1 1 1 1 0 1); Since A1 1600 only includes 31 sequence values after the fixed delay of 1600 for the scrambling recurrence sequence, therefore, it is also necessary to calculate through the formula A1 1601 = T1 1601 * A10 T , calculate the initial value A1 of the second group of scrambling recurrence sequences of Sequence 1 in the fixed-delay state 1601 = (0 0 0 0 0 1 0 0 0 0 1 1 0 1 0 0 0 0 1 0 0 1 0 0 1 1 1 1 0 1 0), A1 1601 includes 31 sequence values after the fixed delay of 1601 for the scrambling recurrence sequence; then add all the sequence values of A1 1600 to A1 1601The last value of the sequence is obtained to get 32 scrambler recurrence sequences with a complete parallelism of 32. In the FPGA implementation, the 32-bit recurrence initial register corresponding to sequence 1 is: seq1_scrb = 32’b01011110010010000101100001000000. For sequence 2, through formula A2 1600 = T2 1600 * A20 T , the initial value A2 of the first group of scrambler recurrence sequences of sequence 2 in the fixed delay state is calculated 1600 ; through formula A2 1601 = T2 1601 * A20 T , the initial value A2 of the second group of scrambler recurrence sequences of sequence 2 in the fixed delay state is obtained 1601 ; then the last value in A2 1601 is concatenated after the A2 1600 sequence to obtain the 32-bit scrambler recurrence sequence of sequence 2. In the FPGA implementation, the 32-bit recurrence initial register corresponding to sequence 2 is: seq2_scrb(0) <= a1^a2^a3^a8^a12^a16^a19^a20^a23; seq2_scrb(1) <= a2^a3^a4^a9^a13^a17^a20^a21^a24; seq2_scrb(2) <= a3^a4^a5^a10^a14^a18^a21^a22^a25; seq2_scrb(3) <= a4^a5^a6^a11^a15^a19^a22^a23^a26; seq2_scrb(4) <= a5^a6^a7^a12^a16^a20^a23^a24^a27; seq2_scrb(5) <= a6^a7^a8^a13^a17^a21^a24^a25^a28; seq2_scrb(6) <= a7^a8^a9^a14^a18^a22^a25^a26^a29; seq2_scrb(7) <= a8^a9^a10^a15^a19^a23^a26^a27^a30; seq2_scrb(8) <= a0^a1^a2^a3^a9^a10^a11^a16^a20^a24^a27^a28; seq2_scrb(9) <= a1 ^ a2 ^ a3 ^ a4 ^ a10 ^ a11 ^ a12 ^ a17 ^ a21 ^ a25 ^ a28 ^ a29; seq2_scrb(10) <= a2 ^ a3 ^ a4 ^ a5 ^ a11 ^ a12 ^ a13 ^ a18 ^ a22 ^ a26 ^ a29 ^ a30; seq2_scrb(11) <= a0 ^ a1 ^ a2 ^ a4 ^ a5 ^ a6 ^ a12 ^ a13 ^ a14 ^ a19 ^ a23 ^ a27 ^ a30; seq2_scrb(12) <= a0 ^ a5 ^ a6 ^ a7 ^ a13 ^ a14 ^ a15 ^ a20 ^ a24 ^ a28; seq2_scrb(13) <= a1 ^ a6 ^ a7 ^ a8 ^ a14 ^ a15 ^ a16 ^ a21 ^ a25 ^ a29; seq2_scrb(14) <= a2 ^ a7 ^ a8 ^ a9 ^ a15 ^ a16 ^ a17 ^ a22 ^ a26 ^ a30; seq2_scrb(15) <= a0 ^ a1 ^ a2 ^ a8 ^ a9 ^ a10 ^ a16 ^ a17 ^ a18 ^ a23 ^ a27; seq2_scrb(16) <= a1 ^ a2 ^ a3 ^ a9 ^ a10 ^ a11 ^ a17 ^ a18 ^ a19 ^ a24 ^ a28; seq2_scrb(17) <= a2 ^ a3 ^ a4 ^ a10 ^ a11 ^ a12 ^ a18 ^ a19 ^ a20 ^ a25 ^ a29; seq2_scrb(18) <= a3 ^ a4 ^ a5 ^ a11 ^ a12 ^ a13 ^ a19 ^ a20 ^ a21 ^ a26 ^ a30; seq2_scrb(19) <= a0 ^ a1 ^ a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a12 ^ a13 ^ a14 ^ a20 ^ a21 ^ a22 ^ a27; seq2_scrb(20) <= a1 ^ a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a13 ^ a14 ^ a15 ^ a21 ^ a22 ^ a23 ^ a28; seq2_scrb(21) <= a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a14 ^ a15 ^ a16 ^ a22 ^ a23 ^ a24 ^ a29; seq2_scrb(22) <= a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a15 ^ a16 ^ a17 ^ a23 ^ a24 ^ a25 ^ a30; seq2_scrb(23) <= a0 ^ a1 ^ a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a16 ^ a17 ^ a18 ^ a24 ^ a25 ^ a26; seq2_scrb(24) <= a1 ^ a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a17 ^ a18 ^ a19 ^ a25 ^ a26 ^ a27; seq2_scrb(25) <= a2 ^ a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a18 ^ a19 ^ a20 ^ a26 ^ a27 ^ a28; seq2_scrb(26) <= a3 ^ a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a13 ^ a19 ^ a20 ^ a21 ^ a27 ^ a28 ^ a29; seq2_scrb(27) <= a4 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a13 ^ a14 ^ a20 ^ a21 ^ a22 ^ a28 ^ a29 ^ a30; seq2_scrb(28) <= a0 ^ a1 ^ a2 ^ a3 ^ a5 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a13 ^ a14 ^ a15 ^ a21 ^ a22 ^ a23 ^ a29 ^ a30; seq2_scrb(29) <= a0 ^ a4 ^ a6 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a13 ^ a14 ^ a15 ^ a16 ^ a22 ^ a23 ^ a24 ^ a30; seq2_scrb(30) <= a0 ^ a2 ^ a3 ^ a5 ^ a7 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a13 ^ a14 ^ a15 ^ a16 ^ a17 ^ a23 ^ a24 ^ a25; seq2_scrb(31) <= a1 ^ a3 ^ a4 ^ a6 ^ a8 ^ a9 ^ a10 ^ a11 ^ a12 ^ a13 ^ a14 ^ a15 ^ a16 ^ a17 ^ a18 ^ a24 ^ a25 ^ a26. Step g4: According to the initial values of the scrambling code recurrence sequences of the two pseudo-random sequences in the fixed time delay state, the scrambling code sequences corresponding to the two pseudo-random sequences are recursively deduced in real time in parallel. Exemplarily, when the parallelism P = 32, for sequence 1, first, through the recurrence vector formula: A1 i+1 = T1 31 * A1 i T , the vector A is obtainedi0 That is the recurrence relation of the first 31 bits of the recurrence sequence, and then through the formula A1 i+1 = T1 32 * A1 i T to obtain the vector A1 i+1 , which is the recurrence relation of 31 bits starting from the second number. Therefore, the 32-bit recurrence vector is (A i0 , A1 i+1 (31)), and the new recurrence initial vector is A1 i+1 . According to the above operations, it can be known that the scrambling sequence TP1 32×31 of sequence 1 has the first 31 rows as T1 31 , and the 32nd row is the last row T1 32 of T1 32 (31, 1:31). As shown in Figure 16, it is the specific value of the scrambling sequence TP1 32×31 of sequence 1. The implementation relationship of the scrambling sequence of sequence 1 in FPGA is: seq1_scrb[0] <= seq1_scrb[1] ^ seq1_scrb[4]; seq1_scrb[1] <= seq1_scrb[2] ^ seq1_scrb[5]; seq1_scrb[2] <= seq1_scrb[3] ^ seq1_scrb[5]; seq1_scrb[3] <= seq1_scrb[4] ^ seq1_scrb[7]; seq1_scrb[4] <= seq1_scrb[5] ^ seq1_scrb[8]; seq1_scrb[5] <= seq1_scrb[6] ^ seq1_scrb[9]; seq1_scrb[6] <= seq1_scrb[7] ^ seq1_scrb

[0010] ; seq1_scrb[7] <= seq1_scrb[8] ^ seq1_scrb

[0011] ; seq1_scrb[8] <= seq1_scrb[9] ^ seq1_scrb

[0012] ; seq1_scrb[9] <= seq1_scrb

[0010] ^ seq1_scrb

[0013] ; seq1_scrb

[0010] <= seq1_scrb

[0011] ^ seq1_scrb

[0014] ; seq1_scrb

[0011] <=seq1_scrb

[0012] ^seq1_scrb

[0015] ; seq1_scrb

[0012] <=seq1_scrb

[0013] ^seq1_scrb

[0015] ; seq1_scrb

[0013] <=seq1_scrb

[0014] ^seq1_scrb

[0017] ; seq1_scrb

[0014] <=seq1_scrb

[0015] ^seq1_scrb

[0018] ; seq1_scrb

[0015] <=seq1_scrb

[0016] ^seq1_scrb

[0019] ; seq1_scrb

[0016] <=seq1_scrb

[0017] ^seq1_scrb

[0020] ; seq1_scrb

[0017] <=seq1_scrb

[0018] ^seq1_scrb

[0021] ; seq1_scrb

[0018] <=seq1_scrb

[0019] ^seq1_scrb

[0022] ; seq1_scrb

[0019] <=seq1_scrb

[0020] ^seq1_scrb

[0023] ; seq1_scrb

[0020] <=seq1_scrb

[0021] ^seq1_scrb

[0024] ; seq1_scrb

[0021] <=seq1_scrb

[0022] ^seq1_scrb

[0025] ; seq1_scrb

[0022] <=seq1_scrb

[0023] ^seq1_scrb

[0025] ; seq1_scrb

[0023] <=seq1_scrb

[0024] ^seq1_scrb

[0027] ; seq1_scrb

[0024] <=seq1_scrb

[0025] ^seq1_scrb

[0028] ; seq1_scrb

[0025] <=seq1_scrb

[0026] ^seq1_scrb

[0029] ; seq1_scrb

[0026] <=seq1_scrb

[0027] ^seq1_scrb

[0030] ; seq1_scrb

[0027] <=seq1_scrb

[0028] ^seq1_scrb

[0031] ; seq1_scrb

[0028] <=seq1_scrb[1]^seq1_scrb[4]^seq1_scrb

[0029] ; seq1_scrb

[0029] <=seq1_scrb[2]^seq1_scrb[5]^seq1_scrb

[0030] ; seq1_scrb

[0030] <=seq1_scrb[3]^seq1_scrb[6]^seq1_scrb

[0031] ; seq1_scrb

[0031] <=seq1_scrb[1]^seq1_scrb[7]. For sequence 2, the TP2 of sequence 2 can be obtained in the same way as the above-mentioned sequence 1 32×31 ; Specifically, the scrambling sequence TP2 of sequence 2 32×31 can be in the form shown in Figure 17. The implementation relationship of the scrambling sequence of sequence 2 in FPGA is as follows: seq2_scrb[0]<=seq2_scrb[1]^seq2_scrb[2]^seq2_scrb[3]^seq2_scrb[4]; seq2_scrb[1]<=seq2_scrb[2]^seq2_scrb[3]^seq2_scrb[4]^seq2_scrb[5]; seq2_scrb[2]<=seq2_scrb[3]^seq2_scrb[4]^seq2_scrb[5]^seq2_scrb[6]; seq2_scrb[3]<=seq2_scrb[4]^seq2_scrb[5]^seq2_scrb[6]^seq2_scrb[7]; seq2_scrb[4]<=seq2_scrb[5]^seq2_scrb[6]^seq2_scrb[7]^seq2_scrb[8]; seq2_scrb[5]<=seq2_scrb[6]^seq2_scrb[7]^seq2_scrb[8]^seq2_scrb[9]; seq2_scrb[6]<=seq2_scrb[7]^seq2_scrb[8]^seq2_scrb[9]^seq2_scrb

[0010] ; seq2_scrb[7] <= seq2_scrb[8] ^ seq2_scrb[9] ^ seq2_scrb

[0010] ^ seq2_scrb

[0011] ; seq2_scrb[8] <= seq2_scrb[9] ^ seq2_scrb

[0010] ^ seq2_scrb

[0011] ^ seq2_scrb

[0012] ; seq2_scrb[9] <= seq2_scrb

[0010] ^ seq2_scrb

[0011] ^ seq2_scrb

[0012] ^ seq2_scrb

[0013] ; seq2_scrb

[0010] <= seq2_scrb

[0011] ^ seq2_scrb

[0012] ^ seq2_scrb

[0013] ^ seq2_scrb

[0014] ; seq2_scrb

[0011] <= seq2_scrb

[0012] ^ seq2_scrb

[0013] ^ seq2_scrb

[0014] ^ seq2_scrb

[0015] ; seq2_scrb

[0012] <= seq2_scrb

[0013] ^ seq2_scrb

[0014] ^ seq2_scrb

[0015] ^ seq2_scrb

[0016] ; seq2_scrb

[0013] <= seq2_scrb

[0014] ^ seq2_scrb

[0015] ^ seq2_scrb

[0016] ^ seq2_scrb

[0017] ; seq2_scrb

[0014] <= seq2_scrb

[0015] ^ seq2_scrb

[0016] ^ seq2_scrb

[0017] ^ seq2_scrb

[0018] ; seq2_scrb

[0015] <= seq2_scrb

[0016] ^ seq2_scrb

[0017] ^ seq2_scrb

[0018] ^ seq2_scrb

[0019] ; seq2_scrb

[0016] <= seq2_scrb

[0017] ^ seq2_scrb

[0018] ^ seq2_scrb

[0019] ^ seq2_scrb

[0020] ; seq2_scrb

[0017] <= seq2_scrb

[0018] ^ seq2_scrb

[0019] ^ seq2_scrb

[0020] ^ seq2_scrb

[0021] ; seq2_scrb

[0018] <= seq2_scrb

[0019] ^ seq2_scrb

[0020] ^ seq2_scrb

[0021] ^ seq2_scrb

[0022] ; seq2_scrb

[0019] <= seq2_scrb

[0020] ^ seq2_scrb

[0021] ^ seq2_scrb

[0022] ^ seq2_scrb

[0023] ; seq2_scrb

[0020] <= seq2_scrb

[0021] ^ seq2_scrb

[0022] ^ seq2_scrb

[0023] ^ seq2_scrb

[0024] ; seq2_scrb

[0021] <= seq2_scrb

[0022] ^ seq2_scrb

[0023] ^ seq2_scrb

[0024] ^ seq2_scrb

[0025] ; seq2_scrb

[0022] <= seq2_scrb

[0023] ^ seq2_scrb

[0024] ^ seq2_scrb

[0025] ^ seq2_scrb

[0026] ; seq2_scrb

[0023] <= seq2_scrb

[0024] ^ seq2_scrb

[0025] ^ seq2_scrb

[0026] ^ seq2_scrb

[0027] ; seq2_scrb

[0024] <= seq2_scrb

[0025] ^ seq2_scrb

[0026] ^ seq2_scrb

[0027] ^ seq2_scrb

[0028] ; seq2_scrb

[0025] <= seq2_scrb

[0026] ^ seq2_scrb

[0027] ^ seq2_scrb

[0028] ^ seq2_scrb

[0029] ; seq2_scrb

[0026] <= seq2_scrb

[0027] ^ seq2_scrb

[0028] ^ seq2_scrb

[0029] ^ seq2_scrb

[0030] ; seq2_scrb

[0027] <= seq2_scrb

[0028] ^ seq2_scrb

[0029] ^ seq2_scrb

[0030] ^ seq2_scrb

[0031] ; seq2_scrb

[0028] <= seq2_scrb[1] ^ seq2_scrb[2] ^ seq2_scrb[3] ^ seq2_scrb[4] ^ seq2_scrb

[0029] ^ seq2_scrb

[0030] ^ seq2_scrb

[0031] ; seq2_scrb

[0029] <= seq2_scrb[1] ^ seq2_scrb[5] ^ seq2_scrb

[0030] ^ seq2_scrb

[0031] ; seq2_scrb

[0030] <= seq2_scrb[1] ^ seq2_scrb[3] ^ seq2_scrb[4] ^ seq2_scrb[6] ^ seq2_scrb

[0031] ; seq2_scrb

[0031] <= seq2_scrb[1] ^ seq2_scrb[3] ^ seq2_scrb[5] ^ seq2_scrb[7]. Step g5: Bitwise XOR the scrambling sequences corresponding to the two pseudo-random sequences to obtain a parallel scrambling sequence. Exemplarily, for the case where the parallelism P is 32, the real-time scrambling sequence of Sequence 1 is seq1_scrb[31:0]; the real-time scrambling sequence of Sequence 2 is seq2_scrb[31:0], and then the parallel scrambling sequence is obtained through bitwise XOR operation. The FPGA implementation of the parallel scrambling sequence is: seq_scrb <= seq1_scrb[31:0] ^ seq2_scrb[31:0]. Step g6: Perform scrambling and descrambling based on the parallel scrambling sequence. Exemplarily, for the scrambling with a parallelism P of 32, the data to be scrambled is bitwise XORed with the parallel scrambling sequence to obtain the scrambled data. The FPGA implementation of the scrambled data is: data_scrb <= seq_scrb ^ data. For descrambling with a parallelism of 32, during hard demodulation, the descrambled data is obtained by performing a bitwise exclusive OR operation on the data and the scrambling code. The FPGA implementation of the descrambled data is: data[31:0]<=seq_scrb[31:0]^data_scrb[31:0]. For soft demodulation data, it is determined whether the soft demodulation data needs to be inverted through the scrambling code sequence, that is, when the corresponding bit of the scrambling code is 0, the data after descrambling remains unchanged, and when the corresponding bit of the scrambling code is 1, the data after descrambling is inverted. The above mainly introduces the solution provided by the embodiments of the present disclosure from the perspective of methods. To implement the above functions, it includes the corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should easily realize that, combining the units and algorithm steps of each example described in the embodiments disclosed herein, the present disclosure can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the way of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present disclosure. The embodiments of the present disclosure also provide a scrambling code sequence generation device. As shown in FIG. 18, the scrambling code sequence generation device 500 may include: a generation module 501. In some embodiments, the above scrambling code sequence generation device 500 may further include: an acquisition module 502. The generation module 501 is configured to determine the scrambling code sequences corresponding to the two pseudo-random sequences respectively based on a preset parallelism, the state relationship matrices of the two pseudo-random sequences respectively, and the initial values of the scrambling code recurrence sequences of the two pseudo-random sequences in a fixed delay state; wherein, the preset parallelism has different values in different communication systems; the generation module 501 is further configured to obtain a parallel scrambling code sequence based on the scrambling code sequences corresponding to the two pseudo-random sequences respectively. In some embodiments, when the preset parallelism is greater than a preset value, the generation module 501 is specifically configured to decompose the preset parallelism into N first parallelisms and a second parallelism; wherein, the value of the first parallelism is the preset value; the second parallelism is the difference between the preset parallelism and N first parallelisms; N is an integer greater than or equal to 1; based on the N first parallelisms and the state relationship matrices of the two pseudo-random sequences respectively, obtain N first recurrence relationship matrices of the two pseudo-random sequences respectively; based on the second parallelism and the state relationship matrices of the two pseudo-random sequences respectively, obtain second recurrence relationship matrices of the two pseudo-random sequences respectively; based on the N first recurrence relationship matrices of the two pseudo-random sequences respectively, the second recurrence relationship matrices of the two pseudo-random sequences respectively, and the initial values of the scrambling code recurrence sequences of the two pseudo-random sequences in a fixed delay state, obtain the scrambling code sequences corresponding to the two pseudo-random sequences respectively. In some other embodiments, when the preset parallelism is less than or equal to a preset value, the generating module 501 is specifically configured to obtain the recurrence relation matrices of the two pseudo-random sequences respectively based on the preset parallelism and the state relation matrices of the two pseudo-random sequences respectively; and obtain the scrambling sequences corresponding to the two pseudo-random sequences respectively based on the recurrence relation matrices of the two pseudo-random sequences respectively and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in the fixed-delay state. In some other embodiments, the above scrambling sequence generating device further includes: an obtaining module 502, configured to obtain the initial vectors of the two pseudo-random sequences respectively; the generating module 501 is further configured to determine the fixed-delay state relation matrices of the two pseudo-random sequences respectively according to the state relation matrices of the two pseudo-random sequences respectively and the fixed delay; and obtain the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in the fixed-delay state according to the initial vectors of the two pseudo-random sequences respectively and the fixed-delay state relation matrices of the two pseudo-random sequences respectively. In some other embodiments, the initial vector value of one of the two pseudo-random sequences is a constant, and the initial vector value of the other pseudo-random sequence is a variable. In some other embodiments, the above generating module 501 is specifically configured to perform a bitwise exclusive OR operation on the scrambling sequences corresponding to the two pseudo-random sequences respectively to obtain a parallel scrambling sequence. In some other embodiments, the above obtaining module 502 is further configured to obtain the data to be scrambled; the above generating module is further configured to scramble the data to be scrambled based on the parallel scrambling sequence to obtain scrambled data. In some other embodiments, the above obtaining module 502 is further configured to obtain the data to be descrambled; the above generating module is further configured to descramble the data to be descrambled based on the parallel scrambling sequence to obtain descrambled data. Some embodiments of the present disclosure provide a computer-readable storage medium (for example, a non-transitory computer-readable storage medium), in which computer program instructions are stored. When the computer program instructions run on a processor, the processor is caused to execute one or more steps in the scrambling sequence generating method described in any one of the above embodiments. Exemplarily, the above computer-readable storage medium may include, but is not limited to: magnetic storage devices (such as hard disks, floppy disks, or magnetic tapes, etc.), optical discs (such as CDs (Compact Disks), DVDs (Digital Versatile Disks), etc.), smart cards, and flash memory devices (such as EPROMs (Erasable Programmable Read-Only Memories), cards, sticks, or key drives, etc.). The various computer-readable storage media described in this disclosure may represent one or more devices and / or other machine-readable storage media for storing information. The term "machine-readable storage medium" may include, but is not limited to, wireless channels and various other media capable of storing, containing, and / or carrying instructions and / or data). Some embodiments of the present disclosure also provide a computer program product. The computer program product includes computer program instructions. When the computer program instructions are executed on a computer, the computer program instructions cause the computer to execute one or more steps in the scrambling sequence generation method as described in the above embodiments. Some embodiments of the present disclosure also provide a computer program. When the computer program is executed on a computer, the computer program causes the computer to execute one or more steps in the scrambling sequence generation method as described in the above embodiments. The beneficial effects of the above computer-readable storage medium, computer program product, and computer program are the same as those of the scrambling sequence generation method described in some of the above embodiments, and will not be elaborated here. As described above, only the specific embodiments of the present disclosure are provided, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure, thinking of changes or substitutions, should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A scrambling sequence generation method, characterized in that, The above includes: Determine the scrambling sequences corresponding to the two pseudo-random sequences respectively based on a preset parallelism, the state relationship matrices of the two pseudo-random sequences respectively, and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in a fixed delay state; wherein, the preset parallelism has different values in different communication systems; Obtain a parallel scrambling sequence based on the scrambling sequences corresponding to the two pseudo-random sequences respectively.

2. The method according to claim 1, characterized in that, When the preset parallelism is greater than a preset value, the step of determining the scrambling sequences corresponding to the two pseudo-random sequences respectively based on a preset parallelism, the state relationship matrices of the two pseudo-random sequences respectively, and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in a fixed delay state includes: Decompose the preset parallelism into N first parallelisms and a second parallelism; wherein, the value of the first parallelism is the preset value; the second parallelism is the difference between the preset parallelism and N first parallelisms; N is an integer greater than or equal to 1; Obtain N first recurrence relationship matrices of the two pseudo-random sequences respectively based on the N first parallelisms and the state relationship matrices of the two pseudo-random sequences respectively; Obtain second recurrence relationship matrices of the two pseudo-random sequences respectively based on the second parallelism and the state relationship matrices of the two pseudo-random sequences respectively; Obtain the scrambling sequences corresponding to the two pseudo-random sequences respectively based on the N first recurrence relationship matrices of the two pseudo-random sequences respectively, the second recurrence relationship matrices of the two pseudo-random sequences respectively, and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in a fixed delay state.

3. The method according to claim 1, wherein When the preset parallelism is less than or equal to the preset value, the step of determining the scrambling sequences corresponding to the two pseudo-random sequences respectively based on a preset parallelism, the state relationship matrices of the two pseudo-random sequences respectively, and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in a fixed delay state includes: Obtain recurrence relationship matrices of the two pseudo-random sequences respectively based on the preset parallelism and the state relationship matrices of the two pseudo-random sequences respectively; Obtain the scrambling sequences corresponding to the two pseudo-random sequences respectively based on the recurrence relationship matrices of the two pseudo-random sequences respectively and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in a fixed delay state.

4. The method according to claim 1, wherein The method further includes: Obtain the initial vectors of the two pseudo-random sequences respectively; Determine the fixed delay state relationship matrices of the two pseudo-random sequences respectively according to the state relationship matrices of the two pseudo-random sequences respectively and the fixed delay; Obtain the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in a fixed delay state according to the initial vectors of the two pseudo-random sequences respectively and the fixed delay state relationship matrices of the two pseudo-random sequences respectively.

5. The method according to claim 4, wherein The initial vector value of one of the two pseudo-random sequences is a constant, and the initial vector value of the other pseudo-random sequence is a variable.

6. The method according to claim 1, wherein The step of obtaining a parallel scrambling sequence based on the scrambling sequences corresponding to the two pseudo-random sequences respectively includes: Perform a bitwise exclusive OR operation on the scrambling sequences corresponding to the two pseudo-random sequences respectively to obtain the parallel scrambling sequence.

7. The method according to claim 1, wherein The method further includes: Obtain the data to be scrambled. Based on the parallel scrambling sequence, scramble the data to be scrambled to obtain scrambled data.

8. The method according to claim 1, wherein The method further includes: Obtain the data to be descrambled. Based on the parallel scrambling sequence, descramble the data to be descrambled to obtain descrambled data.

9. A scrambling sequence generation device, characterized in that, Includes: A generation module, configured to determine the scrambling sequences corresponding to the two pseudo-random sequences respectively based on a preset parallelism, the state relationship matrices of the two pseudo-random sequences respectively, and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in a fixed delay state; wherein, the preset parallelism has different values in different communication systems. The generation module is further configured to obtain a parallel scrambling sequence based on the scrambling sequences corresponding to the two pseudo-random sequences respectively.

10. The device according to claim 9, characterized in that, When the preset parallelism is greater than a preset value, the generation module is specifically configured to decompose the preset parallelism into N first parallelisms and a second parallelism; wherein, the value of the first parallelism is the preset value; the second parallelism is the difference between the preset parallelism and N first parallelisms; N is an integer greater than or equal to 1; based on N first parallelisms and the state relationship matrices of the two pseudo-random sequences respectively, obtain N first recurrence relationship matrices of the two pseudo-random sequences respectively; based on the second parallelism and the state relationship matrices of the two pseudo-random sequences respectively, obtain second recurrence relationship matrices of the two pseudo-random sequences respectively; based on N first recurrence relationship matrices of the two pseudo-random sequences respectively, second recurrence relationship matrices of the two pseudo-random sequences respectively, and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in a fixed delay state, obtain the scrambling sequences corresponding to the two pseudo-random sequences respectively.

11. The device according to claim 9, characterized in that, When the preset parallelism is less than or equal to the preset value, the generation module is specifically configured to obtain recurrence relationship matrices of the two pseudo-random sequences respectively based on the preset parallelism and the state relationship matrices of the two pseudo-random sequences respectively; based on the recurrence relationship matrices of the two pseudo-random sequences respectively and the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in a fixed delay state, obtain the scrambling sequences corresponding to the two pseudo-random sequences respectively.

12. The device according to claim 9, characterized in that, The scrambling sequence generation device further includes: an acquisition module, configured to acquire the initial vectors of the two pseudo-random sequences respectively; the generation module is further configured to determine the fixed delay state relationship matrices of the two pseudo-random sequences respectively according to the state relationship matrices of the two pseudo-random sequences respectively and the fixed delay; and obtain the initial values of the scrambling recurrence sequences of the two pseudo-random sequences in a fixed delay state according to the initial vectors of the two pseudo-random sequences respectively and the fixed delay state relationship matrices of the two pseudo-random sequences respectively.

13. The device according to claim 12, characterized in that, The initial vector value of one of the two pseudo-random sequences is a constant, and the initial vector value of the other pseudo-random sequence is a variable.

14. The device according to claim 9, characterized in that, The generating module is specifically configured to perform a bitwise exclusive OR operation on the scrambling sequences corresponding to the two pseudo-random sequences respectively to obtain the parallel scrambling sequence.

15. The device according to claim 9, characterized in that, The obtaining module is further configured to obtain the data to be scrambled; the generating module is further configured to scramble the data to be scrambled based on the parallel scrambling sequence to obtain scrambled data.

16. The device according to claim 9, characterized in that, The obtaining module is further configured to obtain the data to be descrambled; the generating module is further configured to descramble the data to be descrambled based on the parallel scrambling sequence to obtain descrambled data.

17. A scrambling sequence generation device, characterized in that, The apparatus includes a memory and a processor; The memory and the processor are coupled; the memory is used to store computer program code, and the computer program code includes computer instructions; Wherein, when the processor executes the computer instructions, the apparatus is caused to execute the scrambling sequence generation method according to any one of claims 1-8.

18. A non-transitory computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program; wherein, when the computer program runs on the scrambling sequence generation apparatus, the scrambling sequence generation apparatus is caused to implement the scrambling sequence generation method according to any one of claims 1-8.

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