Display panel, display device and driving method

Abstract

Provided are a display panel, a display device and a driving method. A pixel circuit comprises: a light-emitting device (L); a drive transistor (M0) which is configured to generate, on the basis of a data voltage signal, a drive current for driving the light-emitting device (L) to emit light; a first control circuit (10) which is configured to provide, in response to a signal on a first control signal line (CS1), a signal on a first reference voltage signal line (Vref1) to a first electrode of the drive transistor (M0), and which is configured to connect, in response to signals on a second control signal line (CS2) and a third control signal line (CS3), a gate and a second electrode of the drive transistor (M0); a second control circuit (20) which is configured to provide, in response to a signal on a fourth control signal line (CS4), a signal on a second reference voltage signal line (Vref2) to a first node (N1); a data writing circuit (30) for providing a data voltage signal on a data signal line (DA) to the first node (N1); and a light emission control circuit (50) for providing a signal on a first power signal line (EM1) to the first electrode of the drive transistor (M0), and connecting the second electrode of the drive transistor to the light-emitting device (L) so as to drive the light-emitting device (L) to emit light.

Description

Display panel, display device and driving method Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to display panels, display devices, and driving methods. Background Technology

[0002] Organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), micro light-emitting diodes (Micro LEDs), and mini light-emitting diodes (Mini LEDs) are among the light-emitting devices that possess advantages such as self-illumination and low energy consumption, making them a hot topic in current display device application research. Generally, pixel circuits are used in display devices to drive the light-emitting devices to emit light.

[0003] Summary of the Invention

[0004] The display panel and substrate provided in this embodiment include a plurality of sub-pixels, each of the plurality of sub-pixels including a pixel circuit.

[0005] The pixel circuit includes:

[0006] Light-emitting devices;

[0007] A driving transistor, coupled to the light-emitting device, is configured to generate a driving current that drives the light-emitting device to emit light according to a data voltage signal;

[0008] A first control circuit, coupled to the driving transistor, is configured to provide a signal on the first reference voltage signal line to the first terminal of the driving transistor in response to a signal on the first control signal line, and to turn on the gate and second terminal of the driving transistor in response to signals on the second and third control signal lines.

[0009] The second control circuit, coupled to the first node, is configured to provide a signal on the second reference voltage signal line to the first node in response to a signal on the fourth control signal line.

[0010] The data writing circuit, coupled to the first node, is configured to provide the data voltage signal on the data signal line to the first node in response to a signal on the scan signal line;

[0011] A coupling control circuit, coupled to the gate of the driving transistor and the first node, is configured to couple the data voltage signal of the first node to the gate of the driving transistor and to stabilize the voltage of the first node.

[0012] A light-emitting control circuit, coupled to the driving transistor and the light-emitting device, is configured to provide a signal on the first power supply signal line to the first terminal of the driving transistor in response to a signal on the first light-emitting control signal line, and to connect the second terminal of the driving transistor to the light-emitting device in response to a signal on the second light-emitting control signal line, thereby driving the light-emitting device to emit light.

[0013] Optionally, in some embodiments of this disclosure, it further includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially stacked on the substrate.

[0014] The first semiconductor layer and the second semiconductor layer are made of different materials.

[0015] Optionally, in some embodiments of this disclosure, the first control circuit includes: a first transistor, a second transistor, and a third transistor;

[0016] The gate of the first transistor is coupled to the first control signal line, the first terminal of the first transistor is coupled to the first terminal of the driving transistor, and the second terminal of the first transistor is coupled to the first reference voltage signal line.

[0017] The gate of the second transistor is coupled to the second control signal line, the first terminal of the second transistor is coupled to the second terminal of the third transistor, and the second terminal of the second transistor is coupled to the second terminal of the driving transistor;

[0018] The gate of the third transistor is coupled to the third control signal line, and the first electrode of the third transistor is coupled to the gate of the driving transistor.

[0019] Optionally, in some embodiments of this disclosure, the first semiconductor layer includes the active layer of the driving transistor, the active layer of the first transistor, and the active layer of the second transistor; the second semiconductor layer includes the active layer of the third transistor.

[0020] The first conductive layer includes the gate of the driving transistor, the gate of the first transistor, and the gate of the second transistor; the second conductive layer and the third conductive layer include the gate of the third transistor.

[0021] Optionally, in some embodiments of this disclosure, the second control circuit includes: a fourth transistor;

[0022] The gate of the fourth transistor is coupled to the fourth control signal line, the first terminal of the fourth transistor is coupled to the first node, and the second terminal of the fourth transistor is coupled to the second reference voltage signal line.

[0023] Optionally, in some embodiments of this disclosure, the second semiconductor layer includes the active layer of the fourth transistor; the second conductive layer and the third conductive layer include the gate of the fourth transistor.

[0024] Optionally, in some embodiments of this disclosure, the data writing circuit includes: a fifth transistor;

[0025] The gate of the fifth transistor is coupled to the scan signal line, the first electrode of the fifth transistor is coupled to the data signal line, and the second electrode of the fifth transistor is coupled to the first node.

[0026] Optionally, in some embodiments of this disclosure, the second semiconductor layer includes the active layer of the fifth transistor; the second conductive layer and the third conductive layer include the gate of the fifth transistor.

[0027] Optionally, in some embodiments of this disclosure, the coupling control circuit includes: a first capacitor and a second capacitor;

[0028] The first plate of the first capacitor is coupled to the gate of the driving transistor, and the second plate of the first capacitor is coupled to the first node.

[0029] The first plate of the second capacitor is coupled to the first power signal line, and the second plate of the second capacitor is coupled to the first node.

[0030] Optionally, in some embodiments of this disclosure, the first conductive layer includes a first electrode of the first capacitor and a first electrode of the second capacitor; the second conductive layer includes a second electrode of the first capacitor and a second electrode of the second capacitor; and the third conductive layer includes a first electrode of the second capacitor.

[0031] The first plate of the first capacitor and the first plate of the second capacitor located on the first conductive layer are spaced apart from each other; the second plate of the first capacitor and the second plate of the second capacitor located on the second conductive layer are a single unit.

[0032] The orthographic projection of the first electrode of the first capacitor on the first conductive layer onto the substrate overlaps with the orthographic projection of the second electrode of the first capacitor on the second conductive layer onto the substrate.

[0033] The orthographic projection of the first electrode of the second capacitor on the first conductive layer onto the substrate overlaps with the orthographic projection of the second electrode of the second capacitor on the second conductive layer onto the substrate.

[0034] The orthographic projection of the first electrode of the second capacitor on the third conductive layer onto the substrate completely overlaps with the orthographic projection of the second electrode of the second capacitor on the second conductive layer onto the substrate.

[0035] The orthographic projection of the first electrode of the second capacitor on the third conductive layer onto the substrate overlaps with the orthographic projection of the first electrode of the first capacitor on the first conductive layer onto the substrate.

[0036] Optionally, in some embodiments of this disclosure, the light-emitting control circuit includes a sixth transistor and a seventh transistor;

[0037] The gate of the sixth transistor is coupled to the first light-emitting control signal line, the first electrode of the sixth transistor is coupled to the first power supply signal line, and the second electrode of the sixth transistor is coupled to the first electrode of the driving transistor.

[0038] The gate of the seventh transistor is coupled to the second light-emitting control signal line, the first terminal of the seventh transistor is coupled to the second terminal of the driving transistor, and the second terminal of the seventh transistor is coupled to the light-emitting device.

[0039] Optionally, in some embodiments of this disclosure, the first semiconductor layer includes the active layer of the sixth transistor and the active layer of the seventh transistor; the first conductive layer includes the gate of the sixth transistor and the gate of the seventh transistor.

[0040] Optionally, in some embodiments of this disclosure, the pixel circuit further includes: a first reset circuit coupled to the first control circuit and configured to provide a signal on the first initialization signal line to the first control circuit in response to a signal on the fifth control signal line;

[0041] A second reset circuit, coupled to the light-emitting device, is configured to provide a signal on either the first initialization signal line or the second initialization signal line to the light-emitting device in response to a signal on the first control signal line.

[0042] Optionally, the first reset circuit includes: an eighth transistor;

[0043] The gate of the eighth transistor is coupled to the fifth control signal line, the first terminal of the eighth transistor is coupled to the second terminal of the third transistor, and the second terminal of the eighth transistor is coupled to the first initialization signal line.

[0044] The second reset circuit includes: a ninth transistor;

[0045] The gate of the ninth transistor is coupled to the first control signal line, the first electrode of the ninth transistor is coupled to the light-emitting device, and the second electrode of the ninth transistor is coupled to the first initialization signal line or the second initialization signal line.

[0046] Optionally, in some embodiments of this disclosure, the first semiconductor layer includes the active layer of the eighth transistor; the first conductive layer includes the gate of the eighth transistor;

[0047] The first semiconductor layer includes the active layer of the ninth transistor; the first conductive layer includes the gate of the ninth transistor.

[0048] Optionally, in some embodiments of this disclosure, the signal lines in the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer extend along a first direction; the signal lines in the fifth conductive layer extend along a second direction.

[0049] Optionally, in some embodiments of this disclosure, the first conductive layer includes the first control signal line and the fifth control signal line;

[0050] The second conductive layer includes a first initialization signal line, a second light emission control signal line, and at least two first reference voltage signal lines;

[0051] The third conductive layer includes a first light-emitting control signal line;

[0052] The fourth conductive layer includes the scan signal line, the fourth control signal line, the second reference voltage signal line, the first power signal line, the third control signal line, the second control signal line, and the second initialization signal line;

[0053] The fifth conductive layer includes the data signal line, the first power signal line, and the second reference voltage signal line, with the first power signal line located between the data signal line and the second reference voltage signal line.

[0054] Optionally, in some embodiments of this disclosure, the fourth conductive layer further includes a second power signal line; the second power signal line provides a second power signal to the light-emitting device;

[0055] The fifth conductive layer further includes the first initialization signal line, the second initialization signal line, the first reference voltage signal line, and the second power supply signal line.

[0056] Optionally, in some embodiments of this disclosure, the substrate further includes: a plurality of pixel units; the pixel unit includes three sub-pixels;

[0057] The orthographic projections of the first sub-pixel and the second sub-pixel in the pixel unit onto the substrate are symmetrical about the orthographic projection of the second reference voltage signal line onto the substrate, and the first sub-pixel and the second sub-pixel in the pixel unit share the second reference voltage signal line.

[0058] The data signal line and the second reference voltage signal line are projected onto the substrate in the orthographic projection of the substrate between the second sub-pixel and the third sub-pixel in the pixel unit.

[0059] Two adjacent pixel units along the first direction are connected by either the first initialization signal line, the second initialization signal line, the first reference voltage signal line, or the second power supply signal line.

[0060] Optionally, in some embodiments of this disclosure, the first initialization signal line, the second initialization signal line, the first reference voltage signal line, and the second power supply signal line are arranged alternately along the first direction.

[0061] The driving method for the display panel provided in this embodiment includes:

[0062] When using the first frequency display, it includes:

[0063] During the reset phase, the first control circuit responds to the signal on the first control signal line by providing the signal on the first reference voltage signal line to the first terminal of the driving transistor; the first reset circuit responds to the signal on the fifth control signal line by providing the signal on the first initialization signal line to the first control circuit; the second reset circuit responds to the signal on the first control signal line by providing the signal on the second initialization signal line to the light-emitting device.

[0064] During the threshold voltage compensation phase, the first control circuit responds to the signals on the second and third control signal lines by turning on the gate and second terminal of the driving transistor; the second control circuit responds to the signal on the fourth control signal line by providing the signal on the second reference voltage signal line to the first node; and the light emission control circuit responds to the signal on the first light emission control signal line by providing the signal on the first power supply signal line to the first terminal of the driving transistor.

[0065] During the data writing phase, the data writing circuit responds to the signal on the scan signal line by providing the data voltage signal on the data signal line to the first node; the second reset circuit responds to the signal on the first control signal line by providing the signal on the second initialization signal line to the light-emitting device; and the first control circuit responds to the signal on the first control signal line by providing the signal on the first reference voltage signal line to the first electrode of the driving transistor.

[0066] During the biasing phase, the second reset circuit responds to the signal on the first control signal line by providing the signal on the second initialization signal line to the light-emitting device; the first control circuit responds to the signal on the first control signal line by providing the signal on the first reference voltage signal line to the first terminal of the driving transistor.

[0067] During the light-emitting stage, the light-emitting control circuit responds to the signal on the first light-emitting control signal line by providing the signal on the first power signal line to the first terminal of the driving transistor, and responds to the signal on the second light-emitting control signal line by connecting the second terminal of the driving transistor to the light-emitting device, thereby driving the light-emitting device to emit light.

[0068] Optionally, in some embodiments of this disclosure, the following are also included:

[0069] When using a second frequency display, including:

[0070] During the biasing phase, the second reset circuit responds to the signal on the first control signal line by providing the signal on the second initialization signal line to the light-emitting device; the first control circuit responds to the signal on the first control signal line by providing the signal on the first reference voltage signal line to the first terminal of the driving transistor.

[0071] During the light-emitting stage, the light-emitting control circuit responds to the signal on the first light-emitting control signal line by providing the signal on the first power signal line to the first terminal of the driving transistor, and responds to the signal on the second light-emitting control signal line by connecting the second terminal of the driving transistor to the light-emitting device, thereby driving the light-emitting device to emit light.

[0072] The second frequency is less than the first frequency.

[0073] The display device provided in this disclosure includes the display panel described above. Attached Figure Description

[0074] Figure 1 is a schematic diagram of some structures of the pixel circuit provided in the embodiments of this disclosure;

[0075] Figure 2 is a schematic diagram of some other structures of the pixel circuit provided in the embodiments of this disclosure;

[0076] Figure 3 is a schematic diagram of some of the pixel circuit structures provided in the embodiments of this disclosure;

[0077] Figure 4 is a schematic diagram of some of the pixel circuit structures provided in the embodiments of this disclosure;

[0078] Figure 5 is a schematic diagram of some structures of the display panel provided in the embodiments of this disclosure;

[0079] Figure 6 is a schematic diagram of some other structures of the display panel provided in the embodiments of this disclosure;

[0080] Figure 7 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0081] Figure 8 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0082] Figure 9 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0083] Figure 10 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0084] Figure 11 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0085] Figure 12 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0086] Figure 13 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0087] Figure 14 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0088] Figure 15 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0089] Figure 16 is a flowchart of some driving methods provided in the embodiments of this disclosure;

[0090] Figure 17 is a flowchart of some other driving methods provided in the embodiments of this disclosure;

[0091] Figure 18 is a signal timing diagram provided in an embodiment of this disclosure;

[0092] Figure 19 shows some other signal timing diagrams provided in the embodiments of this disclosure. Detailed Implementation

[0093] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0094] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0095] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0096] The display device provided in this disclosure includes a display panel, wherein the display area of ​​the display panel includes a plurality of pixel units arranged in an array. Exemplarily, each pixel unit includes a plurality of sub-pixels. For example, a pixel unit may include red sub-pixels, green sub-pixels, and blue sub-pixels, so that red, green, and blue can be mixed to achieve color display. Alternatively, a pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, so that red, green, blue, and white can be mixed to achieve color display. Of course, in practical applications, the emission color of the sub-pixels in a pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0097] In this embodiment, each sub-pixel includes a pixel circuit, which includes a driving transistor and a light-emitting device to drive the light-emitting device to emit light, thereby enabling the display panel to display an image. Due to process technology and device aging, the threshold voltage Vth of the driving transistor may be non-uniform, which causes the current flowing through different light-emitting devices to change, resulting in uneven display brightness and affecting the overall image display effect.

[0098] Furthermore, due to the current market's high demand for display quality, high frame rate displays have become a future trend in the display industry. However, high frame rate displays consume more power, leading to reduced battery life. Introducing variable refresh rate (VRR) technology can improve power consumption and extend battery life. However, at low frame rates, the hysteresis effect of the driving transistors causes image retention, affecting display quality; and flickering occurs during frame transitions, further impacting the display effect.

[0099] The display panel provided in this embodiment of the present disclosure, as shown in FIG1, includes: a substrate 100, including a plurality of sub-pixels spx, each of the plurality of sub-pixels spx including a pixel circuit 200;

[0100] Pixel circuit 200 includes:

[0101] Light-emitting device L;

[0102] The driving transistor M0 is coupled to the light-emitting device L and is configured to generate a driving current to drive the light-emitting device L to emit light according to the data voltage signal.

[0103] The first control circuit 10, coupled to the driving transistor M0, is configured to provide the signal on the first reference voltage signal line Vref1 to the first terminal of the driving transistor M0 in response to the signal on the first control signal line CS1, and to turn on the gate and the second terminal of the driving transistor M0 in response to the signals on the second control signal line CS2 and the third control signal line CS3.

[0104] The second control circuit 20, coupled to the first node N1, is configured to provide the signal on the second reference voltage signal line Vref2 to the first node N1 in response to the signal on the fourth control signal line CS4.

[0105] The data writing circuit 30, coupled to the first node N1, is configured to provide the data voltage signal on the data signal line DA to the first node N1 in response to a signal on the scan signal line SS.

[0106] The coupling control circuit 40 is coupled to the gate of the driving transistor M0 and the first node N1, and is configured to couple the data voltage signal of the first node N1 to the gate of the driving transistor M0, and to stabilize the voltage of the first node N1.

[0107] The light-emitting control circuit 50, coupled to the driving transistor M0 and the light-emitting device L, is configured to provide the signal on the first power supply signal line VDD to the first terminal of the driving transistor M0 in response to the signal on the first light-emitting control signal line EM1, and to connect the second terminal of the driving transistor M0 to the light-emitting device L in response to the signal on the second light-emitting control signal line EM2, thereby driving the light-emitting device L to emit light.

[0108] This embodiment of the present disclosure achieves the separation of threshold voltage compensation and data voltage signal writing for the driving transistor by the cooperation of the first control circuit, the second control circuit, the data writing circuit, the coupling control circuit, and the light emission control circuit. As a result, the threshold voltage compensation time of the driving transistor is not limited by the data voltage signal writing, and the threshold voltage compensation process can be carried out for a longer time, which is beneficial to the stability of the threshold voltage of the driving transistor. This enables high frame rate display and avoids the impact of threshold voltage drift of the driving transistor on the light emission of the light emission device, thereby improving the image quality of high frame rate display.

[0109] Furthermore, by cooperating with the first control circuit, the second control circuit, the data writing circuit, the coupling control circuit, and the light-emitting control circuit, the driving transistor is strongly biased, which can improve the hysteresis effect of the driving transistor, thereby avoiding image retention and flickering problems and improving the display effect.

[0110] For example, as shown in Figure 1, the driving transistor M0 can be configured as a P-type transistor; wherein, the first terminal of the driving transistor M0 can be its source, and the second terminal of the driving transistor M0 can be its drain. Of course, the driving transistor M0 can also be configured as an N-type transistor, which is not limited here.

[0111] For example, as shown in Figure 1, the second electrode of the driving transistor M0 is coupled to the anode of the light-emitting device L, and the cathode of the light-emitting device L is coupled to the second power signal line VSS. For example, the light-emitting device L may include at least one of a micro light-emitting diode (Micro LED), an organic light-emitting diode (OLED), and a quantum dot light-emitting diode (QLED). For example, the light-emitting device L may include an anode, a light-emitting layer, and a cathode stacked together. Further, the light-emitting layer may also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. In practical applications, the specific structure of the light-emitting device can be designed and determined according to the actual application environment, and is not limited here.

[0112] In some embodiments of this disclosure, as shown in FIG2, the first control circuit 10 includes: a first transistor M1, a second transistor M2, and a third transistor M3; wherein, the gate of the first transistor M1 is coupled to a first control signal line CS1, the first terminal of the first transistor M1 is coupled to the first terminal of the driving transistor M0, and the second terminal of the first transistor M1 is coupled to a first reference voltage signal line Vref1; the gate of the second transistor M2 is coupled to a second control signal line CS2, the first terminal of the second transistor M2 is coupled to the second terminal of the third transistor M3, and the second terminal of the second transistor M2 is coupled to the second terminal of the driving transistor M0; the gate of the third transistor M3 is coupled to a third control signal line CS3, and the first terminal of the third transistor M3 is coupled to the gate of the driving transistor M0.

[0113] For example, the first transistor M1 can be turned on under the control of the effective level of the first control signal transmitted on the first control signal line CS1, and can be turned off under the control of the ineffective level of the first control signal. For example, if the first transistor M1 is configured as a P-type transistor, then the effective level of the first control signal is low, and the ineffective level of the first control signal is high. Alternatively, if the first transistor M1 is configured as an N-type transistor, then the effective level of the first control signal is high, and the ineffective level of the first control signal is low.

[0114] For example, the second transistor M2 can be turned on under the control of the effective level of the second control signal transmitted on the second control signal line CS2, and can be turned off under the control of the ineffective level of the second control signal. For example, if the second transistor M2 is configured as a P-type transistor, then the effective level of the second control signal is low, and the ineffective level of the second control signal is high. Alternatively, if the second transistor M2 is configured as an N-type transistor, then the effective level of the second control signal is high, and the ineffective level of the second control signal is low.

[0115] For example, the third transistor M3 can be turned on under the control of the effective level of the third control signal transmitted on the third control signal line CS3, and can be turned off under the control of the ineffective level of the third control signal. For example, if the third transistor M3 is set as a P-type transistor, then the effective level of the third control signal is low and the ineffective level of the third control signal is high. Alternatively, if the third transistor M3 is set as an N-type transistor, then the effective level of the third control signal is high and the ineffective level of the third control signal is low.

[0116] In some embodiments of this disclosure, as shown in FIG2, the second control circuit 20 includes: a fourth transistor M4; wherein the gate of the fourth transistor M4 is coupled to a fourth control signal line CS4, the first terminal of the fourth transistor M4 is coupled to a first node N1, and the second terminal of the fourth transistor M4 is coupled to a second reference voltage signal line Vref2.

[0117] For example, the fourth transistor M4 can be turned on under the control of the effective level of the fourth control signal transmitted on the fourth control signal line CS4, and can be turned off under the control of the ineffective level of the fourth control signal. For example, if the fourth transistor M4 is configured as a P-type transistor, then the effective level of the fourth control signal is low, and the ineffective level of the fourth control signal is high. Alternatively, if the fourth transistor M4 is configured as an N-type transistor, then the effective level of the fourth control signal is high, and the ineffective level of the fourth control signal is low.

[0118] In some embodiments of this disclosure, as shown in FIG2, the data writing circuit 30 includes: a fifth transistor M5; the gate of the fifth transistor M5 is coupled to the scan signal line SS, the first terminal of the fifth transistor M5 is coupled to the data signal line DA, and the second terminal of the fifth transistor M5 is coupled to the first node N1.

[0119] For example, the fifth transistor M5 can be turned on under the control of the effective level of the scan signal transmitted on the scan signal line SS, and can be turned off under the control of the ineffective level of the scan signal. For example, if the fifth transistor M5 is set as a P-type transistor, then the effective level of the scan signal is low and the ineffective level of the scan signal is high. Alternatively, if the fifth transistor M5 is set as an N-type transistor, then the effective level of the scan signal is high and the ineffective level of the scan signal is low.

[0120] In some embodiments of this disclosure, as shown in FIG2, the coupling control circuit 40 includes: a first capacitor C1 and a second capacitor C2; wherein, the first plate of the first capacitor C1 is coupled to the gate of the driving transistor M0, and the second plate of the first capacitor C1 is coupled to the first node N1; the first plate of the second capacitor C2 is coupled to the first power signal line, and the second plate of the second capacitor C2 is coupled to the first node N1.

[0121] In some embodiments of this disclosure, as shown in FIG2, the light-emitting control circuit 50 includes a sixth transistor M6 and a seventh transistor M7; wherein, the gate of the sixth transistor M6 is coupled to the first light-emitting control signal line EM1, the first terminal of the sixth transistor M6 is coupled to the first power supply signal line, and the second terminal of the sixth transistor M6 is coupled to the first terminal of the driving transistor M0; the gate of the seventh transistor M7 is coupled to the second light-emitting control signal line EM2, the first terminal of the seventh transistor M7 is coupled to the second terminal of the driving transistor M0, and the second terminal of the seventh transistor M7 is coupled to the light-emitting device L.

[0122] For example, the sixth transistor M6 can be turned on under the control of the effective level of the first light-emitting control signal transmitted on the first light-emitting control signal line EM1, and can be turned off under the control of the ineffective level of the first light-emitting control signal. For example, if the sixth transistor M6 is set as a P-type transistor, then the effective level of the first light-emitting control signal is low, and the ineffective level of the first light-emitting control signal is high. Alternatively, if the sixth transistor M6 is set as an N-type transistor, then the effective level of the first light-emitting control signal is high, and the ineffective level of the first light-emitting control signal is low.

[0123] For example, the seventh transistor M7 can be turned on under the control of the effective level of the second light-emitting control signal transmitted on the second light-emitting control signal line EM2, and can be turned off under the control of the ineffective level of the second light-emitting control signal. For example, if the seventh transistor M7 is set as a P-type transistor, then the effective level of the second light-emitting control signal is low, and the ineffective level of the second light-emitting control signal is high. Alternatively, if the seventh transistor M7 is set as an N-type transistor, then the effective level of the second light-emitting control signal is high, and the ineffective level of the second light-emitting control signal is low.

[0124] In some embodiments of this disclosure, as shown in FIG1, the pixel circuit 200 further includes: a first reset circuit 60, coupled to the first control circuit 10, configured to provide a signal on the first initialization signal line Vinit1 to the first control circuit 10 in response to a signal on the fifth control signal line CS5.

[0125] In some embodiments of this disclosure, as shown in FIG2, the first reset circuit 60 includes: an eighth transistor M8; wherein the gate of the eighth transistor M8 is coupled to the fifth control signal line CS5, the first terminal of the eighth transistor M8 is coupled to the second terminal of the third transistor M3, and the second terminal of the eighth transistor M8 is coupled to the first initialization signal line Vinit1.

[0126] For example, the eighth transistor M8 can be turned on under the control of the effective level of the fifth control signal transmitted on the fifth control signal line CS5, and can be turned off under the control of the ineffective level of the fifth control signal. For example, if the eighth transistor M8 is configured as a P-type transistor, then the effective level of the fifth control signal is low, and the ineffective level of the fifth control signal is high. Alternatively, if the eighth transistor M8 is configured as an N-type transistor, then the effective level of the fifth control signal is high, and the ineffective level of the fifth control signal is low.

[0127] In some embodiments of this disclosure, as shown in FIG1, the pixel circuit 200 further includes: a second reset circuit 70, coupled to the light-emitting device L, configured to provide a signal on the second initialization signal line Vinit2 to the light-emitting device L in response to a signal on the first control signal line CS1.

[0128] In some embodiments of this disclosure, as shown in FIG2, the second reset circuit 70 includes: a ninth transistor M9; wherein, the gate of the ninth transistor M9 is coupled to the first control signal line CS1, the first electrode of the ninth transistor M9 is coupled to the light-emitting device L, and the second electrode of the ninth transistor M9 is coupled to the second initialization signal line Vinit2.

[0129] This disclosure, by coupling the first reset circuit 60 to the first initialization signal line Vinit1 and the second reset circuit 70 to the second initialization signal line Vinit2, can reset the gate of the driving transistor M0 and the anode of the light-emitting device L respectively, thereby further improving image quality.

[0130] For example, the ninth transistor M9 can be turned on under the control of the effective level of the first control signal transmitted on the first control signal line CS1, and can be turned off under the control of the ineffective level of the first control signal. For example, if the ninth transistor M9 is configured as a P-type transistor, then the effective level of the first control signal is low, and the ineffective level of the first control signal is high. Alternatively, if the ninth transistor M9 is configured as an N-type transistor, then the effective level of the first control signal is high, and the ineffective level of the first control signal is low.

[0131] This disclosure provides other schematic diagrams of pixel circuit structures, as shown in Figures 3 and 4, which are modifications of the implementation methods described above. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0132] In other embodiments of this disclosure, as shown in FIG3, the pixel circuit 200 further includes: a second reset circuit 70, coupled to the light-emitting device L, configured to provide a signal on the first initialization signal line Vinit1 to the light-emitting device L in response to a signal on the first control signal line CS1.

[0133] In some other embodiments of this disclosure, as shown in FIG4, the second reset circuit 70 includes: a ninth transistor M9; wherein the gate of the ninth transistor M9 is coupled to the first control signal line CS1, the first electrode of the ninth transistor M9 is coupled to the light-emitting device L, and the second electrode of the ninth transistor M9 is coupled to the first initialization signal line Vinit1.

[0134] This disclosure reduces the number of signal lines and simplifies circuit layout by coupling both the first reset circuit 60 and the second reset circuit 70 to the first initialization signal line Vinit1.

[0135] For example, the first electrode of the transistor described above can be its source, and the second electrode can be its drain. Alternatively, the first electrode can be its drain, and the second electrode can be its source. No limitation is made here.

[0136] For example, the first power signal line VDD can be configured to carry a constant first power supply voltage vdd, which is generally positive. Similarly, the second power signal line VSS can carry a constant second power supply voltage vss, which is generally ground voltage or negative. In practical applications, the specific values ​​of the first power supply voltage vdd and the second power supply voltage vss can be designed and determined according to the actual application environment, and are not limited here.

[0137] In some embodiments of this disclosure, as shown in Figures 5 to 13, the material further includes: a first semiconductor layer 110, a first conductive layer 120, a second conductive layer 130, a second semiconductor layer 140, a third conductive layer 150, a fourth conductive layer 160, and a fifth conductive layer 170 sequentially stacked on a substrate 100; wherein the first semiconductor layer 110 and the second semiconductor layer 140 are made of different materials.

[0138] It should be noted that the first semiconductor layer and the second semiconductor layer are used to form the active layers of each transistor in the pixel circuit. The active layer includes a channel region, and source and drain regions located on both sides of the channel region. By setting the first semiconductor layer and the second semiconductor layer to be made of different materials, this disclosure enables the active layers of each transistor in the pixel circuit to be made of different materials, thereby reducing the leakage current of the pixel circuit and improving the display effect and display quality of the display panel.

[0139] For example, as shown in FIG6, an auxiliary conductive layer 101 is also included, located between the substrate 100 and the first semiconductor layer 110.

[0140] In some embodiments of this disclosure, the first semiconductor layer 110 is made of low-temperature polycrystalline silicon, and the second semiconductor layer 140 is made of oxide.

[0141] Transistors that typically use low-temperature polysilicon (LTPS) as the active layer have high mobility, can be made thinner and smaller, and consume less power. In practical implementations, the active layer material of the aforementioned transistors can also be set to low-temperature polysilicon. This allows the transistors to be configured as LTPS type transistors, enabling pixel circuits to achieve high mobility, thinner and smaller designs, and lower power consumption.

[0142] Transistors that typically use metal-oxide-semiconductor (MODS) materials as their active layers generally have low leakage current. Therefore, to reduce leakage current, in some embodiments of this disclosure, the active layer of the transistor can be made of MODS materials, such as IGZO (Indium Gallium Zinc Oxide). Of course, other MODS materials can also be used, and this is not limited thereto. This allows the transistor to be configured as an oxide thin-film transistor, thereby reducing the leakage current of the pixel circuit.

[0143] For example, some transistors in the pixel circuit of this disclosure can be configured as oxide transistors, while others can be configured as LTPS transistors. For instance, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are configured as oxide transistors, while the driving transistor M0, the first transistor M1, the second transistor M2, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are configured as LTPS transistors; thereby reducing the leakage current of the pixel circuit and improving display quality. By utilizing the low leakage current characteristic of oxide transistors, embodiments of this disclosure can ensure that the gate voltage value of the driving transistor M0 is maintained under low frame rate displays, thereby preventing display panel flicker.

[0144] For example, the materials of the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be conductive materials. For example, conductive materials can include metal materials or alloy materials such as aluminum, molybdenum, and titanium, or metal oxides such as indium tin oxide (ITO). The embodiments of this disclosure do not specifically limit the materials of each conductive layer, and can be set according to requirements.

[0145] For example, the above-described patterning process can be used to form various structures in the first conductive layer, second conductive layer, third conductive layer, fourth conductive layer, and fifth conductive layer. It should be noted that the patterning process may include only photolithography, or it may include photolithography and etching steps, and may also include other processes for forming predetermined patterns such as printing and inkjet printing; photolithography refers to a process that uses photoresist, photomasks, and exposure machines to form patterns, including processes such as film deposition, exposure, and development. In specific implementations, the appropriate patterning process can be selected according to the structure formed in this disclosure.

[0146] In some embodiments of this disclosure, as shown in Figures 7 to 13, the first semiconductor layer 110 includes an active layer for driving transistor M0, an active layer for first transistor M1, and an active layer for second transistor M2; the second semiconductor layer 140 includes an active layer for third transistor M3; the first conductive layer 120 includes the gate for driving transistor M0, the gate for first transistor M1, and the gate for second transistor M2; the second conductive layer 130 and the third conductive layer 150 include the gate for third transistor M3.

[0147] In some embodiments of this disclosure, as shown in Figures 7 to 13, the second semiconductor layer 140 further includes an active layer of the fourth transistor M4; the second conductive layer 130 and the third conductive layer 150 further include the gate of the fourth transistor.

[0148] In some embodiments of this disclosure, as shown in Figures 7 to 13, the second semiconductor layer 140 further includes an active layer of the fifth transistor M5; the second conductive layer 130 and the third conductive layer 150 further include the gate of the fifth transistor.

[0149] In some embodiments of this disclosure, as shown in Figures 7 to 13, the first semiconductor layer 110 further includes an active layer of the sixth transistor M6 and an active layer of the seventh transistor M7; the first conductive layer 120 further includes the gate of the sixth transistor M6 and the gate of the seventh transistor M7.

[0150] In some embodiments of this disclosure, as shown in Figures 7 to 13, the first semiconductor layer 110 further includes an active layer of the eighth transistor M8; the first conductive layer 120 further includes the gate of the eighth transistor M8.

[0151] In some embodiments of this disclosure, as shown in Figures 7 to 13, the first semiconductor layer 110 further includes an active layer of the ninth transistor M9; the first conductive layer 120 further includes the gate of the ninth transistor M9.

[0152] In some embodiments of this disclosure, as shown in Figures 7 to 13, the first conductive layer 120 further includes a first electrode plate of the first capacitor C1 and a first electrode plate of the second capacitor C2; the second conductive layer 130 further includes a second electrode plate of the first capacitor C1 and a second electrode plate of the second capacitor C2; and the third conductive layer 150 further includes a first electrode plate of the second capacitor C2.

[0153] The first plates of the first capacitor C1 and the second capacitor C2 located on the first conductive layer 120 are spaced apart from each other; the second plates of the first capacitor C1 and the second capacitor C2 located on the second conductive layer 130 are a single unit.

[0154] The orthographic projection of the first electrode of the first capacitor C1 on the first conductive layer 120 onto the substrate overlaps with the orthographic projection of the second electrode of the first capacitor C1 on the second conductive layer 130 onto the substrate.

[0155] The orthographic projection of the first electrode of the second capacitor C2 on the first conductive layer 120 onto the substrate overlaps with the orthographic projection of the second electrode of the second capacitor C2 on the second conductive layer 130 onto the substrate.

[0156] The orthographic projection of the first electrode of the second capacitor C2 on the third conductive layer 150 onto the substrate completely overlaps with the orthographic projection of the second electrode of the second capacitor C2 on the second conductive layer 130 onto the substrate.

[0157] The orthographic projection of the first electrode of the second capacitor C2 on the third conductive layer 150 onto the substrate partially overlaps with the orthographic projection of the first electrode of the first capacitor C1 on the first conductive layer 120 onto the substrate.

[0158] For example, as shown in FIG8, the first plate of the first capacitor C1 on the first conductive layer 120 extends along the first direction X, and the second capacitor C2 on the first conductive layer 120 is arranged at intervals with each other in the first direction X.

[0159] For example, as shown in Figure 9, the second plate of the first capacitor C1 and the second plate of the second capacitor C2 in each sub-pixel (e.g., spx1, spx2, spx3 in Figure 9) are a whole, that is, the second plate of the first capacitor C1 and the second plate of the second capacitor C2 in each sub-pixel (e.g., spx1, spx2, spx3 in Figure 9) are connected to each other.

[0160] For example, as shown in FIG11, the first plates of the second capacitor C2 on the third conductive layer 150 are connected to each other in the first direction X, that is, the first plate of the second capacitor C2 in sub-pixel spx1 is connected to the first plate of the second capacitor C2 in sub-pixel spx2, and the first plate of the second capacitor C2 in sub-pixel spx2 is connected to the first plate of the second capacitor C2 in sub-pixel spx3.

[0161] For example, the orthographic projection of the first electrode plate of the first capacitor C1 located on the first conductive layer 120 onto the substrate 100 overlaps with the orthographic projection of the second electrode plate of the first capacitor C1 located on the second conductive layer 130 onto the substrate 100. That is, the first electrode plate of the first capacitor C1 located on the first conductive layer 120 and the second electrode plate of the first capacitor C1 located on the second conductive layer 130 have facing areas, thereby forming the first capacitor C1.

[0162] For example, the orthographic projection of the first electrode of the second capacitor C2 located on the first conductive layer 120 onto the substrate 100 overlaps with the orthographic projection of the second electrode of the second capacitor C2 located on the second conductive layer 130 onto the substrate 100. That is, the first electrode of the second capacitor C2 located on the first conductive layer 120 and the second electrode of the second capacitor C2 located on the second conductive layer 130 have facing areas to form one sub-capacitor of the second capacitor. The orthographic projection of the first electrode of the second capacitor C2 located on the third conductive layer 150 onto the substrate 100 overlaps with the orthographic projection of the second electrode of the second capacitor C2 located on the second conductive layer 130 onto the substrate 100. That is, the first electrode of the second capacitor C2 located on the third conductive layer 150 and the second electrode of the second capacitor C2 located on the second conductive layer 130 have facing areas to form another sub-capacitor of the second capacitor C2. By connecting these two sub-capacitors in series to form the second capacitor C2, the capacitance value of the second capacitor C2 is increased. While ensuring the capacitance value of the second capacitor C2, the area occupied by the second capacitor C2 can be reduced, thereby saving space occupied by the second capacitor C2 and improving the space utilization of the display panel.

[0163] It should be noted that, as shown in Figure 8, the first plate of the first capacitor C1 located on the first conductive layer 120 can be reused as the gate of the driving transistor M0, thereby saving space and improving the space utilization of the display panel.

[0164] For example, the third conductive layer 130 can act as a shielding layer to shield the parasitic capacitance between the data signal line DA and the gate node of the driving transistor M0 and the first node N1, thereby avoiding the adverse effects of signal crosstalk and improving display quality.

[0165] In some embodiments of this disclosure, as shown in Figures 7 to 13, signal lines in the first conductive layer 120, the second conductive layer 130, the third conductive layer 150, and the fourth conductive layer 160 extend along a first direction X; signal lines in the fifth conductive layer 170 extend along a second direction Y.

[0166] In some embodiments of this disclosure, as shown in Figures 7 to 13, the first conductive layer 120 includes a first control signal line CS1 and a fifth control signal line CS5;

[0167] The second conductive layer 130 includes a first initialization signal line Vinit1, a second light emission control signal line EM2, and at least two first reference voltage signal lines Vref1;

[0168] The third conductive layer 150 includes a first light-emitting control signal line EM1;

[0169] The fourth conductive layer 160 includes a scan signal line SS, a fourth control signal line CS4, a second reference voltage signal line Vref2, a first power supply signal line VDD, a third control signal line CS3, a second control signal line CS2, and a second initialization signal line Vinit2;

[0170] The fifth conductive layer 170 includes a data signal line DA, a first power signal line VDD, and a second reference voltage signal line Vref2, with the first power signal line VDD located between the data signal line DA and the second reference voltage signal line Vref2.

[0171] For example, as shown in FIG2, the fourth conductive layer 160 further includes: a first connecting portion Z1, a second connecting portion Z2, a third connecting portion Z3, a fourth connecting portion Z4, a fifth connecting portion Z5, a sixth connecting portion Z6, a seventh connecting portion Z7, an eighth connecting portion Z8, a ninth connecting portion Z9, a tenth connecting portion Z10, and an eleventh connecting portion Z11; wherein, the first connecting portion Z1 is used to electrically connect the fifth transistor M5 to the data signal line DA; the second connecting portion Z2 is used to electrically connect the fourth transistor M4, the fifth transistor M5 to the second plate of the first capacitor C1 and the second plate of the second capacitor C2 on the second conductive layer 130 (it should be noted that the second connecting portion Z2 is equivalent to the first node N1); the third connecting portion Z3 is used to electrically connect the first plate of the second capacitor C2 in the first conductive layer 120 to the first plate of the second capacitor C2 in the third conductive layer 150; the fourth connecting portion Z4 is used to connect the gate of the driving transistor M0, the third transistor M3, and the first capacitor C1 in the second conductive layer 130 to the second plate of the second capacitor C2 in the third conductive layer 150. The second plate of capacitor C1 is electrically connected (it should be noted that the fourth connection part Z4 is equivalent to the second node N2); the fifth connection part Z5 is used to electrically connect the second transistor M2, the eighth transistor M8, and the third transistor M3 (it should be noted that the fifth connection part Z5 is equivalent to the third node N3); the sixth connection part Z6 is used to electrically connect the eighth transistor M8 to the first initialization signal line Vinit1; the seventh connection part Z7 is used to electrically connect the sixth transistor M6 to the first power supply signal line VDD in the fifth conductive layer 170; the eighth connection part Z8 is used to electrically connect the sixth transistor M6 to the first light emission control signal line EM1 in the third conductive layer 150; the ninth connection part Z9 is used to electrically connect the seventh transistor M7 to the second light emission control signal line EM2 in the second conductive layer 130; the tenth connection part Z10 is used to electrically connect the seventh transistor M7 and the ninth transistor M9 to the anode of the light-emitting device; the eleventh connection part Z11 is used to electrically connect the first transistor M1 to the first reference voltage signal line Vref1 in the second conductive layer 130.

[0172] The third connection part Z3 and the first power signal line VDD in the fourth conductive layer 160 are integral structures. Since the third connection part Z3 is connected to the first plate of the second capacitor C2 in the first conductive layer 120 and the first plate of the second capacitor C2 in the third conductive layer 150, the signal on the first power signal line VDD can be provided to the first plate of the second capacitor C2 in the first conductive layer 120 and the first plate of the second capacitor C2 in the third conductive layer 150. This configuration can increase the capacitance of the second capacitor C2. Furthermore, the orthographic projection of the first plate of the second capacitor C2 in the third conductive layer 150 onto the substrate overlaps with the orthographic projection of the first plate of the first capacitor C1 on the first conductive layer 120 onto the substrate, which can stabilize the voltage on the first node N1. As a result, the data signal provided to the first node N1 by the fifth transistor M5 will be more stable. Furthermore, the orthographic projection of the first power signal line VDD in the fifth conductive layer 170 onto the substrate overlaps with the orthographic projections of the second connection portion Z2, the fourth connection portion Z4, and the fifth connection portion Z5 onto the substrate, thereby stabilizing the voltage of the signals at the first node N1, the second node N2, and the third node N3, making the voltage of the signals at the first node N1, the second node N2, and the third node N3 more stable. Moreover, the first power signal line VDD in the fourth conductive layer 160 extends along the first direction X, and the first power signal line VDD in the fifth conductive layer 170 extends along the second direction Y, so that the orthographic projection of the first power signal line VDD onto the substrate is in a grid pattern. The signal lines extending along the first direction X in the first conductive layer 120, the third conductive layer 150, and the fourth conductive layer 160 are connected to the signal lines extending along the second direction Y in the fifth conductive layer 170, which can further reduce the voltage drop.

[0173] For example, as shown in FIG8, the first control signal line CS1 is integrated with the gate of the first transistor M1 and the gate of the ninth transistor M9; the fifth control signal line CS5 is integrated with the gate of the eighth transistor M8; then, the first control signal line CS1 in the first conductive layer 120 is multiplexed as the gate of the first transistor M1 and the ninth transistor M9, and the fifth control signal line CS5 in the first conductive layer 120 is multiplexed as the gate of the eighth transistor M8, thereby saving space and improving the space utilization of the display panel.

[0174] For example, as shown in Figures 8 and 9, the second light-emitting control signal line EM2 in the second conductive layer 130 is connected to the gate of the seventh transistor M7 in the first conductive layer 120.

[0175] In some embodiments of this disclosure, as shown in Figures 7 to 13, the fourth conductive layer 160 further includes a second power signal line VSS; the second power signal line VSS provides a second power signal to the light-emitting device L.

[0176] The fifth conductive layer 170 also includes a first initialization signal line Vinit1, a second initialization signal line Vinit2, a first reference voltage signal line Vref1, and a second power supply signal line VSS.

[0177] For example, the second initialization signal line Vinit2 in the fifth conductive layer 170 is electrically connected to the second initialization signal line Vinit2 in the fourth conductive layer 160; the second power signal line VSS in the fifth conductive layer 170 is electrically connected to the second power signal line VSS in the fourth conductive layer 160; the first initialization signal line Vinit1 in the fifth conductive layer 170 is electrically connected to the first initialization signal line Vinit1 in the second conductive layer 130; and the first reference voltage signal line Vref1 in the fifth conductive layer 170 is electrically connected to the first reference voltage signal line Vref1 in the second conductive layer 130. Thus, the first initialization signal line Vinit1, the second initialization signal line Vinit2, the first reference voltage signal line Vref1, and the second power signal line VSS are all arranged in a grid pattern when projected onto the substrate.

[0178] In some embodiments of this disclosure, as shown in Figures 5 to 15, the substrate 100 further includes: a plurality of pixel units SPX; each pixel unit SPX includes three sub-pixels (e.g., spx1, spx2, and spx3 in Figure 5).

[0179] The orthographic projections of the first sub-pixel spx1 and the second sub-pixel spx2 in the pixel unit onto the substrate 100 are symmetrical about the orthographic projection of the second reference voltage signal line Vref2 onto the substrate 100, and the first sub-pixel spx1 and the second sub-pixel spx2 in the pixel unit share the second reference voltage signal line Vref2.

[0180] The orthographic projection of the data signal line DA and the second reference voltage signal line Vref2 onto the substrate 100 lies between the orthographic projections of the second sub-pixel spx2 and the third sub-pixel spx3 in the pixel unit onto the substrate 100.

[0181] Two adjacent pixel units along the first direction X have a first initialization signal line Vinit1 or a second initialization signal line Vinit2 or a first reference voltage signal line Vref1 or a second power supply signal line VSS.

[0182] In some embodiments of this disclosure, as shown in Figures 14 and 15, the first initialization signal line Vinit1, the second initialization signal line Vinit2, the first reference voltage signal line Vref1, and the second power supply signal line VSS are arranged alternately along the first direction X.

[0183] For example, by setting the first initialization signal line Vinit1, the second initialization signal line Vinit2, the first reference voltage signal line Vref1, and the second power signal line VSS to a grid-like wiring, the power consumption of the pixel circuit can be further reduced and the stability of the current and voltage of the pixel circuit can be improved, thereby improving the display effect of the display panel.

[0184] The display panel driving method provided in this embodiment, as shown in FIG16, includes the following steps when displaying at a first frequency:

[0185] S100, Reset Phase: The first control circuit responds to the signal on the first control signal line by providing the signal on the first reference voltage signal line to the first terminal of the driving transistor; the first reset circuit responds to the signal on the fifth control signal line by providing the signal on the first initialization signal line to the first control circuit; the second reset circuit responds to the signal on the first control signal line by providing the signal on the second initialization signal line to the light-emitting device.

[0186] S200, Threshold voltage compensation stage: the first control circuit responds to the signals on the second and third control signal lines and turns on the gate and second terminal of the driving transistor; the second control circuit responds to the signal on the fourth control signal line and provides the signal on the second reference voltage signal line to the first node; the light emission control circuit responds to the signal on the first light emission control signal line and provides the signal on the first power supply signal line to the first terminal of the driving transistor.

[0187] S300, during the data writing phase, the data writing circuit responds to the signal on the scan signal line and provides the data voltage signal on the data signal line to the first node; the second reset circuit responds to the signal on the first control signal line and provides the signal on the second initialization signal line to the light-emitting device; the first control circuit responds to the signal on the first control signal line and provides the signal on the first reference voltage signal line to the first terminal of the driving transistor.

[0188] S400, during the biasing phase, the second reset circuit responds to the signal on the first control signal line by providing the signal on the second initialization signal line to the light-emitting device; the first control circuit responds to the signal on the first control signal line by providing the signal on the first reference voltage signal line to the first terminal of the driving transistor.

[0189] S500, Light-emitting stage: In response to the signal on the first light-emitting control signal line, the light-emitting control circuit provides the signal on the first power signal line to the first terminal of the driving transistor. In response to the signal on the second light-emitting control signal line, the second terminal of the driving transistor is connected to the light-emitting device, driving the light-emitting device to emit light.

[0190] For example, the first frequency can be 120Hz, 180Hz, or 240Hz, etc., and is not limited here.

[0191] In some embodiments of this disclosure, as shown in FIG17, when a second frequency is used for display, wherein the second frequency is less than the first frequency, the following steps are included:

[0192] S600, during the biasing phase, the second reset circuit responds to the signal on the first control signal line by providing the signal on the second initialization signal line to the light-emitting device; the first control circuit responds to the signal on the first control signal line by providing the signal on the first reference voltage signal line to the first terminal of the driving transistor.

[0193] S700, during the light-emitting stage, the second control circuit responds to the signal on the fourth control signal line by providing the signal on the second reference voltage signal line to the first node; the light-emitting control circuit responds to the signal on the first light-emitting control signal line by providing the signal on the first power supply signal line to the first electrode of the driving transistor, and responds to the signal on the second light-emitting control signal line by connecting the second electrode of the driving transistor to the light-emitting device, thereby driving the light-emitting device to emit light.

[0194] For example, the second frequency can be 1Hz or the like, and is not limited here.

[0195] The following description uses the pixel circuit shown in Figure 4 as an example, and refers to the signal timing diagram shown in Figure 18, to describe the working process of the pixel circuit provided in the embodiments of this disclosure.

[0196] In some embodiments of this disclosure, as shown in FIG18, ss represents the scan signal on the scan signal line SS, cs1 represents the first control signal on the first control signal line CS1, cs2 represents the second control signal on the second control signal line CS2, cs3 represents the third control signal on the third control signal line CS3, cs4 represents the fourth control signal on the fourth control signal line CS4, cs5 represents the fifth control signal on the fifth control signal line CS5, em1 represents the first light emission control signal on the first light emission control signal line EM1, and em2 represents the second light emission control signal on the second light emission control signal line EM2.

[0197] Furthermore, select the reset phase F1, threshold voltage compensation phase F2, data writing phase F3, bias phase F4, and light emission phase F5 in a display frame 1H.

[0198] During the reset phase F1, the first transistor M1 is turned on under the control of the low level of the first control signal CS1. The second transistor M2 is turned off under the control of the high level of the second control signal CS2. The third transistor M3 is turned on under the control of the high level of the third control signal CS3. The fourth transistor M4 is turned off under the control of the low level of the fourth control signal CS4. The fifth transistor M5 is turned off under the control of the low level of the scan signal SS. The sixth transistor M6 is turned off under the control of the high level of the first light emission control signal EM1. The seventh transistor M7 is turned off under the control of the high level of the second light emission control signal EM2. The eighth transistor M8 is turned on under the control of the low level of the fifth control signal CS5. The ninth transistor M9 is turned on under the control of the low level of the first control signal CS1. The first transistor M1, when turned on, provides the signal on the first reference voltage signal line Vref1 to the first terminal of the driving transistor M0; the eighth transistor M8, when turned on, provides the signal on the first initialization signal line Vinit1 to the second terminal of the third transistor M3 in the first control circuit 10; the third transistor M3, when turned on, connects its second terminal to the gate of the driving transistor M0, thereby providing the signal on the first initialization signal line Vinit1 to the gate of the driving transistor M0, resetting the gate of the driving transistor M0, and then V... g =V init1 , where V g V represents the gate voltage of the driving transistor M0. init1 This represents the voltage on the first initialization signal line Vinit1; the conducting ninth transistor M9 provides the signal on the second initialization signal line Vinit2 to the anode of the light-emitting device L, resetting the anode of the light-emitting device L. Therefore, V L =V init2 , where V L V represents the voltage at the anode of the light-emitting device L. init2 This represents the voltage on the second initialization signal line, Vinit2.

[0199] In the first stage F21 of the threshold voltage compensation stage F2, the first transistor M1 is turned off under the control of the high level of the first control signal cs1. The second transistor M2 is turned on under the control of the low level of the second control signal cs2. The third transistor M3 is turned on under the control of the high level of the third control signal cs3. The fourth transistor M4 is turned on under the control of the high level of the fourth control signal cs4. The fifth transistor M5 is turned off under the control of the low level of the scan signal ss. The sixth transistor M6 is turned on under the control of the low level of the first light emission control signal em1. The seventh transistor M7 is turned off under the control of the high level of the second light emission control signal em2. The eighth transistor M8 is turned off under the control of the high level of the fifth control signal cs5. The ninth transistor M9 is turned off under the control of the high level of the first control signal cs1. The turned-on sixth transistor M6 provides the signal on the first power supply signal line VDD to the first terminal of the driving transistor M0; the turned-on second transistor M2 and third transistor M3 connect the gate and second terminal of the driving transistor M0, compensating for the threshold voltage Vth of the driving transistor. Therefore, V... g = Vdd + Vth, where Vdd represents the voltage on the first power supply signal line VDD, and Vth represents the threshold voltage of the driving transistor; the conducting fourth transistor M4 provides the signal on the second reference voltage signal line Vref2 to the first node N1, then V N1 =V ref2 , where V N1 V represents the voltage across the first node N1. ref2 This represents the voltage on the second reference voltage signal line Vref2.

[0200] In the second stage F22 of the threshold voltage compensation stage F2, the first transistor M1 is turned off under the control of the high level of the first control signal cs1. The second transistor M2 is turned off under the control of the high level of the second control signal cs2. The third transistor M3 is turned on under the control of the high level of the third control signal cs3. The fourth transistor M4 is turned off under the control of the low level of the fourth control signal cs4. The fifth transistor M5 is turned off under the control of the low level of the scan signal ss. The sixth transistor M6 is turned on under the control of the low level of the first light emission control signal em1. The seventh transistor M7 is turned off under the control of the high level of the second light emission control signal em2. The eighth transistor M8 is turned on under the control of the low level of the fifth control signal cs5. The ninth transistor M9 is turned off under the control of the high level of the first control signal cs1. The conducting sixth transistor M6 provides the signal on the first power supply signal line VDD to the first terminal of the driving transistor M0; the conducting eighth transistor M8 provides the signal on the first initialization signal line Vinit1 to the second terminal of the third transistor M3 in the first control circuit 10; the conducting third transistor M3 connects its second terminal to the gate of the driving transistor M0, thereby providing the signal on the first initialization signal line Vinit1 to the gate of the driving transistor M0.

[0201] During the data writing phase F3, the first transistor M1 is turned on under the control of the low level of the first control signal CS1. The second transistor M2 is turned off under the control of the high level of the second control signal CS2. The third transistor M3 is turned off under the control of the low level of the third control signal CS3. The fourth transistor M4 is turned off under the control of the low level of the fourth control signal CS4. The fifth transistor M5 is turned on under the control of the high level of the scan signal SS. The sixth transistor M6 is turned off under the control of the high level of the first light emission control signal EM1. The seventh transistor M7 is turned off under the control of the high level of the second light emission control signal EM2. The eighth transistor M8 is turned off under the control of the high level of the fifth control signal CS5. The ninth transistor M9 is turned on under the control of the low level of the first control signal CS1. The turned-on first transistor M1 provides the signal on the first reference voltage signal line Vref1 to the first terminal of the driving transistor M0; the turned-on fifth transistor M5 provides the data voltage signal Vda on the data signal line DA to the first node N1, then V N1 =V da , where V da The first capacitor C1 couples the data voltage signal Vda of the first node N1 to the gate of the driving transistor M0, and the second capacitor C2 stabilizes the voltage on the first node N1 and the gate of the driving transistor M0; the conducting ninth transistor M9 provides the signal on the second initialization signal line Vref2 to the light-emitting device L.

[0202] During the biasing phase F4, the first transistor M1 is turned on under the control of the low level of the first control signal CS1. The second transistor M2 is turned off under the control of the high level of the second control signal CS2. The third transistor M3 is turned off under the control of the low level of the third control signal CS3. The fourth transistor M4 is turned off under the control of the low level of the fourth control signal CS4. The fifth transistor M5 is turned off under the control of the low level of the scan signal SS. The sixth transistor M6 is turned off under the control of the high level of the first light emission control signal EM1. The seventh transistor M7 is turned off under the control of the high level of the second light emission control signal EM2. The eighth transistor M8 is turned off under the control of the high level of the fifth control signal CS5. The ninth transistor M9 is turned on under the control of the low level of the first control signal CS1. The turned-on first transistor M1 provides the signal on the first reference voltage signal line Vref1 to the first terminal of the driving transistor M0, then V... g =Vdd + Vth + V da -V ref1 , where V ref1 The voltage on the first reference voltage signal line Vref1 is represented; the conducting ninth transistor M9 provides the signal on the second initialization signal line Vref2 to the light-emitting device L.

[0203] During the light-emitting phase F5, the first transistor M1 is turned off under the control of the high level of the first control signal CS1. The second transistor M2 is turned off under the control of the high level of the second control signal CS2. The third transistor M3 is turned off under the control of the low level of the third control signal CS3. The fourth transistor M4 is turned off under the control of the low level of the fourth control signal CS4. The fifth transistor M5 is turned off under the control of the low level of the scan signal SS. The sixth transistor M6 is turned on under the control of the low level of the first light-emitting control signal EM1. The seventh transistor M7 is turned on under the control of the low level of the second light-emitting control signal EM2. The eighth transistor M8 is turned off under the control of the high level of the fifth control signal CS5. The ninth transistor M9 is turned off under the control of the high level of the first control signal CS1. The turned-on sixth transistor M6 provides the signal on the first power supply signal line VDD to the first terminal of the driving transistor M0; the turned-on seventh transistor M7 connects the second terminal of the driving transistor M0 to the light-emitting device L, providing the driving current generated by the driving transistor M0 to the anode of the light-emitting device L. This driving current charges the anode of the light-emitting device L until the light-emitting device L emits light stably. If the driving transistor M0 is in saturation operation, then V g =Vdd + Vth + V da -V ref1 V gs =Vth+V da -V ref1 , where V gsThis represents the voltage difference between the gate and source of the driving transistor M0. The resulting drive current I... oled =β*(Vgs-Vth) 2 =β*(V da -V ref1 ) 2 , Where l represents the length of the channel of driving transistor M0, w represents the width of the channel of driving transistor M0, and C ox μ represents the capacitance per unit area of ​​the gate insulating layer of the driving transistor M0, and μ represents the mobility of the driving transistor M0.

[0204] The following description uses the pixel circuit shown in Figure 4 as an example, and refers to the signal timing diagram shown in Figure 19, to describe the working process of the pixel circuit provided in the embodiments of this disclosure.

[0205] In some embodiments of this disclosure, as shown in FIG19, ss represents the scan signal on the scan signal line SS, cs1 represents the first control signal on the first control signal line CS1, cs2 represents the second control signal on the second control signal line CS2, cs3 represents the third control signal on the third control signal line CS3, cs4 represents the fourth control signal on the fourth control signal line CS4, cs5 represents the fifth control signal on the fifth control signal line CS5, em1 represents the first light emission control signal on the first light emission control signal line EM1, and em2 represents the second light emission control signal on the second light emission control signal line EM2.

[0206] Furthermore, select the reset phase F1, threshold voltage compensation phase F2, data writing phase F3, bias phase F4, and light emission phase F5 in a display frame 1H.

[0207] During the biasing phase F4, the first transistor M1 is turned on under the control of the low level of the first control signal CS1. The second transistor M2 is turned off under the control of the high level of the second control signal CS2. The third transistor M3 is turned off under the control of the low level of the third control signal CS3. The fourth transistor M4 is turned off under the control of the low level of the fourth control signal CS4. The fifth transistor M5 is turned off under the control of the low level of the scan signal SS. The sixth transistor M6 is turned off under the control of the high level of the first light emission control signal EM1. The seventh transistor M7 is turned off under the control of the high level of the second light emission control signal EM2. The eighth transistor M8 is turned off under the control of the high level of the fifth control signal CS5. The ninth transistor M9 is turned on under the control of the low level of the first control signal CS1. The turned-on first transistor M1 provides the signal on the first reference voltage signal line Vref1 to the first terminal of the driving transistor M0, then V... g =Vdd + Vth + V da -V ref1The conducting ninth transistor M9 provides the signal on the second initialization signal line Vref2 to the light-emitting device L.

[0208] During the light-emitting phase F5, the first transistor M1 is turned off under the control of the high level of the first control signal CS1. The second transistor M2 is turned off under the control of the high level of the second control signal CS2. The third transistor M3 is turned off under the control of the low level of the third control signal CS3. The fourth transistor M4 is turned off under the control of the low level of the fourth control signal CS4. The fifth transistor M5 is turned off under the control of the low level of the scan signal SS. The sixth transistor M6 is turned on under the control of the low level of the first light-emitting control signal EM1. The seventh transistor M7 is turned on under the control of the low level of the second light-emitting control signal EM2. The eighth transistor M8 is turned off under the control of the high level of the fifth control signal CS5. The ninth transistor M9 is turned off under the control of the high level of the first control signal CS1. The turned-on sixth transistor M6 provides the signal on the first power supply signal line VDD to the first terminal of the driving transistor M0; the turned-on seventh transistor M7 connects the second terminal of the driving transistor M0 to the light-emitting device L, providing the driving current generated by the driving transistor M0 to the anode of the light-emitting device L. This driving current charges the anode of the light-emitting device L until the light-emitting device L emits light stably. If the driving transistor M0 is in saturation operation, then V g =Vdd + Vth + V da -V ref1 V gs =Vth+V da -V ref1 The generated drive current I oled =β*(Vgs-Vth) 2 =β*(V da -V ref1 ) 2 ,

[0209] This disclosure also provides a display device, including the display panel described above. The principle by which this display device solves the problem is similar to that of the aforementioned display panel; therefore, the implementation of this display device can refer to the implementation of the aforementioned display panel, and the repetitions will not be repeated here.

[0210] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with a display function, such as a mobile phone, electronic watch, tablet computer, television set, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0211] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0212] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, wherein, include: A substrate comprising a plurality of sub-pixels, each of the plurality of sub-pixels comprising a pixel circuit; The pixel circuit includes: Light-emitting devices; A driving transistor, coupled to the light-emitting device, is configured to generate a driving current that drives the light-emitting device to emit light according to a data voltage signal; A first control circuit, coupled to the driving transistor, is configured to provide a signal on the first reference voltage signal line to the first terminal of the driving transistor in response to a signal on the first control signal line, and to turn on the gate and second terminal of the driving transistor in response to signals on the second and third control signal lines. The second control circuit, coupled to the first node, is configured to provide a signal on the second reference voltage signal line to the first node in response to a signal on the fourth control signal line. The data writing circuit, coupled to the first node, is configured to provide the data voltage signal on the data signal line to the first node in response to a signal on the scan signal line; A coupling control circuit, coupled to the gate of the driving transistor and the first node, is configured to couple the data voltage signal of the first node to the gate of the driving transistor and to stabilize the voltage of the first node. A light-emitting control circuit, coupled to the driving transistor and the light-emitting device, is configured to provide a signal on the first power supply signal line to the first terminal of the driving transistor in response to a signal on the first light-emitting control signal line, and to connect the second terminal of the driving transistor to the light-emitting device in response to a signal on the second light-emitting control signal line, thereby driving the light-emitting device to emit light.

2. The display panel as claimed in claim 1, wherein, Also includes: A first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer are sequentially stacked on the substrate. The first semiconductor layer and the second semiconductor layer are made of different materials.

3. The display panel as described in claim 2, wherein, The first control circuit includes: a first transistor, a second transistor, and a third transistor; The gate of the first transistor is coupled to the first control signal line, the first terminal of the first transistor is coupled to the first terminal of the driving transistor, and the second terminal of the first transistor is coupled to the first reference voltage signal line. The gate of the second transistor is coupled to the second control signal line, the first terminal of the second transistor is coupled to the second terminal of the third transistor, and the second terminal of the second transistor is coupled to the second terminal of the driving transistor; The gate of the third transistor is coupled to the third control signal line, and the first electrode of the third transistor is coupled to the gate of the driving transistor.

4. The display panel as claimed in claim 3, wherein, The first semiconductor layer includes the active layer of the driving transistor, the active layer of the first transistor, and the active layer of the second transistor; the second semiconductor layer includes the active layer of the third transistor. The first conductive layer includes the gate of the driving transistor, the gate of the first transistor, and the gate of the second transistor; the second conductive layer and the third conductive layer include the gate of the third transistor.

5. The display panel as described in any one of claims 2-4, wherein, The second control circuit includes: a fourth transistor; The gate of the fourth transistor is coupled to the fourth control signal line, the first terminal of the fourth transistor is coupled to the first node, and the second terminal of the fourth transistor is coupled to the second reference voltage signal line.

6. The display panel as claimed in claim 5, wherein, The second semiconductor layer includes the active layer of the fourth transistor; the second conductive layer and the third conductive layer include the gate of the fourth transistor.

7. The display panel according to any one of claims 2-6, wherein, The data writing circuit includes: a fifth transistor; The gate of the fifth transistor is coupled to the scan signal line, and the first of the fifth transistor... The second terminal of the fifth transistor is coupled to the data signal line, and the second terminal of the fifth transistor is coupled to the first node.

8. The display panel as claimed in claim 7, wherein, The second semiconductor layer includes the active layer of the fifth transistor; the second conductive layer and the third conductive layer include the gate of the fifth transistor.

9. The display panel according to any one of claims 2-8, wherein, The coupling control circuit includes: a first capacitor and a second capacitor; The first plate of the first capacitor is coupled to the gate of the driving transistor, and the second plate of the first capacitor is coupled to the first node. The first plate of the second capacitor is coupled to the first power signal line, and the second plate of the second capacitor is coupled to the first node.

10. The display panel as claimed in claim 9, wherein, The first conductive layer includes the first electrode of the first capacitor and the first electrode of the second capacitor; the second conductive layer includes the second electrode of the first capacitor and the second electrode of the second capacitor; the third conductive layer includes the first electrode of the second capacitor. The first plate of the first capacitor and the first plate of the second capacitor, located on the first conductive layer, are spaced apart from each other. The second plate of the first capacitor and the second plate of the second capacitor located on the second conductive layer are a single unit; The orthographic projection of the first electrode of the first capacitor on the first conductive layer onto the substrate overlaps with the orthographic projection of the second electrode of the first capacitor on the second conductive layer onto the substrate. The orthographic projection of the first electrode of the second capacitor on the first conductive layer onto the substrate overlaps with the orthographic projection of the second electrode of the second capacitor on the second conductive layer onto the substrate. The orthographic projection of the first electrode of the second capacitor on the third conductive layer onto the substrate completely overlaps with the orthographic projection of the second electrode of the second capacitor on the second conductive layer onto the substrate. The orthographic projection of the first electrode of the second capacitor on the third conductive layer onto the substrate overlaps with the orthographic projection of the first electrode of the first capacitor on the first conductive layer onto the substrate.

11. The display panel according to any one of claims 2-10, wherein, The light-emitting control circuit includes: a sixth transistor and a seventh transistor; The gate of the sixth transistor is coupled to the first light-emitting control signal line, the first electrode of the sixth transistor is coupled to the first power supply signal line, and the second electrode of the sixth transistor is coupled to the first electrode of the driving transistor. The gate of the seventh transistor is coupled to the second light-emitting control signal line, the first terminal of the seventh transistor is coupled to the second terminal of the driving transistor, and the second terminal of the seventh transistor is coupled to the light-emitting device.

12. The display panel as claimed in claim 11, wherein, The first semiconductor layer includes the active layer of the sixth transistor and the active layer of the seventh transistor; the first conductive layer includes the gate of the sixth transistor and the gate of the seventh transistor.

13. The display panel according to any one of claims 2-12, wherein, The pixel circuit further includes: a first reset circuit, coupled to the first control circuit, configured to provide a signal on the first initialization signal line to the first control circuit in response to a signal on the fifth control signal line; A second reset circuit, coupled to the light-emitting device, is configured to provide a signal on either the first initialization signal line or the second initialization signal line to the light-emitting device in response to a signal on the first control signal line.

14. The display panel as claimed in claim 13, wherein, The first reset circuit includes: an eighth transistor; The gate of the eighth transistor is coupled to the fifth control signal line, the first terminal of the eighth transistor is coupled to the second terminal of the third transistor, and the second terminal of the eighth transistor is coupled to the first initialization signal line. The second reset circuit includes: a ninth transistor; The gate of the ninth transistor is coupled to the first control signal line, the first electrode of the ninth transistor is coupled to the light-emitting device, and the second electrode of the ninth transistor is coupled to the first initialization signal line or the second initialization signal line.

15. The display panel as claimed in claim 14, wherein, The first semiconductor layer includes the active layer of the eighth transistor; the first conductive layer includes the gate of the eighth transistor; The first semiconductor layer includes the active layer of the ninth transistor; the first conductive layer includes The gate of the ninth transistor.

16. The display panel according to any one of claims 2-15, wherein, The signal lines in the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer extend along a first direction; the signal lines in the fifth conductive layer extend along a second direction.

17. The display panel as claimed in claim 16, wherein, The first conductive layer includes the first control signal line and the fifth control signal line; The second conductive layer includes a first initialization signal line, a second light emission control signal line, and at least two first reference voltage signal lines; The third conductive layer includes a first light-emitting control signal line; The fourth conductive layer includes the scan signal line, the fourth control signal line, the second reference voltage signal line, the first power signal line, the third control signal line, the second control signal line, and the second initialization signal line; The fifth conductive layer includes the data signal line, the first power signal line, and the second reference voltage signal line, with the first power signal line located between the data signal line and the second reference voltage signal line.

18. The display panel as claimed in claim 17, wherein, The fourth conductive layer further includes a second power signal line; the second power signal line provides a second power signal to the light-emitting device. The fifth conductive layer further includes the first initialization signal line, the second initialization signal line, the first reference voltage signal line, and the second power supply signal line.

19. The display panel as claimed in claim 18, wherein, The substrate further includes: a plurality of pixel units; each pixel unit includes three sub-pixels; The orthographic projections of the first sub-pixel and the second sub-pixel in the pixel unit onto the substrate are symmetrical about the orthographic projection of the second reference voltage signal line onto the substrate, and the first sub-pixel and the second sub-pixel in the pixel unit share the second reference voltage signal line. The data signal line and the second reference voltage signal line are projected onto the substrate in the orthographic projection of the substrate between the second sub-pixel and the third sub-pixel in the pixel unit. Two adjacent pixel units along the first direction are connected by either the first initialization signal line, the second initialization signal line, the first reference voltage signal line, or the second power supply signal line.

20. The display panel as claimed in claim 18, wherein, The first initialization signal line, the second initialization signal line, the first reference voltage signal line, and the second power supply signal line are arranged alternately along the first direction.

21. A driving method for a display panel as described in any one of claims 1-20, wherein, include: When using the first frequency display, it includes: During the reset phase, the first control circuit responds to the signal on the first control signal line by providing the signal on the first reference voltage signal line to the first terminal of the driving transistor; the first reset circuit responds to the signal on the fifth control signal line by providing the signal on the first initialization signal line to the first control circuit; the second reset circuit responds to the signal on the first control signal line by providing the signal on the second initialization signal line to the light-emitting device. During the threshold voltage compensation phase, the first control circuit responds to the signals on the second and third control signal lines by turning on the gate and second terminal of the driving transistor; the second control circuit responds to the signal on the fourth control signal line by providing the signal on the second reference voltage signal line to the first node; and the light emission control circuit responds to the signal on the first light emission control signal line by providing the signal on the first power supply signal line to the first terminal of the driving transistor. During the data writing phase, the data writing circuit responds to the signal on the scan signal line by providing the data voltage signal on the data signal line to the first node; the second reset circuit responds to the signal on the first control signal line by providing the signal on the second initialization signal line to the light-emitting device; and the first control circuit responds to the signal on the first control signal line by providing the signal on the first reference voltage signal line to the first electrode of the driving transistor. During the biasing phase, the second reset circuit responds to the signal on the first control signal line by providing the signal on the second initialization signal line to the light-emitting device; the first control circuit responds to the signal on the first control signal line by providing the signal on the first reference voltage signal line to the first terminal of the driving transistor. During the light-emitting stage, the light-emitting control circuit responds to the signal on the first light-emitting control signal line by providing the signal on the first power signal line to the first terminal of the driving transistor, and responds to the signal on the second light-emitting control signal line by connecting the second terminal of the driving transistor to the light-emitting device, thereby driving the light-emitting device to emit light.

22. The driving method for a display panel as described in claim 21, wherein, Also includes: When using a second frequency display, including: During the biasing phase, the second reset circuit responds to the signal on the first control signal line by providing the signal on the second initialization signal line to the light-emitting device; the first control circuit responds to the signal on the first control signal line by providing the signal on the first reference voltage signal line to the first terminal of the driving transistor. During the light-emitting stage, the light-emitting control circuit responds to the signal on the first light-emitting control signal line by providing the signal on the first power signal line to the first terminal of the driving transistor, and responds to the signal on the second light-emitting control signal line by connecting the second terminal of the driving transistor to the light-emitting device, thereby driving the light-emitting device to emit light. The second frequency is less than the first frequency.

23. A display device, wherein, The display panel as described in any one of claims 1-20.

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