Back-contact cell and preparation method therefor, and cell module

Abstract

A back-contact cell and a preparation method therefor, and a cell module, which belong to the technical field of back-contact cells. The back-contact cell comprises: a silicon wafer, which has a front surface and a back surface; and first semiconductor layers and second semiconductor layers, which are disposed on the back surface and are alternately arranged in the Y-axis direction of the silicon wafer. The back-contact cell further comprises a silicon alloy layer and a metal conductive layer, which are sequentially disposed outwards in the Z-axis direction of the silicon wafer, wherein the silicon alloy layer is disposed on the outer surfaces of the second semiconductor layers and extends to the outer surfaces of adjacent first doped silicon crystal layers; and the sheet resistance of the silicon alloy layer is 60-100 Ω / □, and the sheet resistance of the metal conductive layer is 3-50 Ω / □. In the back-contact cell, it is unnecessary to additionally provide a transparent conductive film layer, fingers and busbars, and the manufacture procedure is simpler; in addition, the use of expensive low-temperature silver paste and transparent conductive film layers is not required, thereby significantly reducing the production costs of the cell, and also ensuring excellent cell conversion efficiency.

Description

Back contact battery, preparation method thereof, and battery assembly

[0001] Cross-references to related publications

[0002] The present disclosure claims priority to Chinese patent application No. 2024100775066, filed with the Patent Office of China on January 19, 2024, entitled “A back-contact battery, a method for preparing the same, and a battery assembly”, and Chinese patent application No. 2024100775032, filed with the Patent Office of China on January 19, 2024, entitled “A back-contact battery, a method for preparing the same, and a battery assembly”, the entire contents of which are incorporated by reference into the present disclosure. Technical Field

[0003] The present disclosure belongs to the technical field of back-contact batteries, and particularly relates to a back-contact battery, a preparation method thereof, and a battery assembly. Background Art

[0004] Existing back-contact solar cells require the deposition of a transparent conductive film on the outer surfaces of the first and second semiconductor layers on the back of a silicon wafer. Currently, this transparent conductive film is typically made of ITO (indium tin oxide) or TCO (tantalum conductive oxide). Etching is then used to form an insulating trench between the first and second semiconductor openings, and metal gate electrodes are formed on the first and second semiconductor openings on the silicon wafer as fine gates. A main gate is also provided, typically using low-temperature silver paste to form the silver gate lines.

[0005] Therefore, the existing technology uses expensive transparent conductive films and low-temperature silver paste, which makes the battery cost high.

[0006] It should be noted that this part of the present disclosure only provides background technology related to the present disclosure and does not necessarily constitute prior art or public known technology.

[0007] Summary of the Invention

[0008] The purpose of the present disclosure is to overcome the defect of the back-contact battery in the prior art that while ensuring excellent battery conversion efficiency, it is necessary to use expensive transparent conductive film layers and low-temperature silver paste, which makes the battery cost high. A back-contact battery and its preparation method and battery assembly are provided. The back-contact battery does not require the additional setting of a transparent conductive film layer, fine grid and main grid, and the process is simpler. At the same time, there is no need to use expensive low-temperature silver paste and transparent conductive film layers (such as ITO), which greatly reduces the production cost of the battery while ensuring excellent battery conversion efficiency.

[0009] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0010] 1. In the first aspect, the present disclosure proposes a back-contact battery, comprising a silicon wafer having a front side and a back side, a first semiconductor layer and a second semiconductor layer arranged on the back side and alternately arranged along the Y-axis direction of the silicon wafer, the first semiconductor layer comprising a first doped silicon crystal layer, the second semiconductor layer comprising a second doped silicon crystal layer, and the end of the second semiconductor layer extends to the outer surface of the adjacent end of the first semiconductor layer to form a transition region, the back-contact battery also comprises a silicon alloy layer and a metal conductive layer arranged in sequence outward along the Z-axis direction of the silicon wafer, the silicon alloy layer is arranged on the outer surface of the second semiconductor layer and extends to the outer surface of the adjacent first doped silicon crystal layer, and an insulating groove is provided on a portion of the silicon alloy layer corresponding to the transition region and its corresponding metal conductive layer; wherein the silicon alloy layer contains metal silicide and the square resistance of the silicon alloy layer is 60-100Ω□, and the square resistance of the metal conductive layer is 3-50Ω□.

[0011] 2. The back-contact battery according to technical solution 1, wherein the metal elements contained in the metal silicide and the metal conductive layer independently include at least one of nickel, aluminum, platinum, cobalt, titanium, and tungsten.

[0012] 3. The back-contact battery according to Technical Solution 2, wherein the metal elements contained in the metal silicide and the metal conductive layer are the same.

[0013] 4. The back contact battery according to technical solution 2, wherein the metal silicide comprises at least one of nickel silicide, aluminum silicide, and platinum silicide;

[0014] and / or,

[0015] The metal conductive layer includes at least one of a nickel layer, an aluminum layer, and a platinum layer.

[0016] 5. The back-contact battery according to technical solution 1, wherein the thickness ratio of the silicon alloy layer to the metal conductive layer is 1:1-15;

[0017] and / or,

[0018] The thickness of the silicon alloy layer is 2-7 nm, and the thickness of the metal conductive layer is 5-30 nm.

[0019] 6. The back-contact battery according to Technical Solution 1, wherein the silicon alloy layer further contains doping elements, and the doping elements include boron or phosphorus.

[0020] 7. The back-contact battery according to technical solution 6, wherein the ratio of the surface doping index of the silicon alloy layer to the first doped silicon crystal layer and the second doped silicon crystal layer is 1:30-1000:150-8000, wherein the surface doping index is the ratio of the effective doping concentration of the corresponding doped silicon layer to the thickness of the doped silicon layer.

[0021] In this disclosure, the unit of the surface doping index is cm<-3> / nm. That is, the unit of the effective doping concentration of the corresponding doped silicon crystal layer is cm<-3>, and the thickness is nm.

[0022] 8. The back contact cell according to technical solution 7, wherein the effective doping concentration of the doping element in the silicon alloy layer is 5e15cm-3-5e17cm-3;

[0023] and / or,

[0024] The thickness ratio of the silicon alloy layer to the second doped silicon crystal layer is 0.04-0.6:1;

[0025] and / or,

[0026] The thickness of the first doped silicon crystal layer is 50-300 nm, and the effective doping concentration is 1e19 cm-3-4e20 cm-3. The thickness of the second doped silicon crystal layer is 10-50 nm, and the effective doping concentration is 1e19 cm-3-4e20 cm-3.

[0027] 9. A back-contact battery according to technical solution 1, wherein the first semiconductor layer further comprises a first passivation layer arranged on the back side of the silicon wafer, and at least a portion of the first passivation layer is located between the back side of the silicon wafer and the first doped silicon crystal layer.

[0028] 10. The back-contact cell according to technical solution 9, wherein the second semiconductor layer further comprises a second passivation layer disposed on the back side of the silicon wafer, the second passivation layer being located between the back side of the silicon wafer and the second doped silicon crystal layer; the second passivation layer comprises a second intrinsic amorphous silicon layer or a second tunneling oxide layer, the second intrinsic amorphous silicon layer having a thickness of 5-15 nm, and the second tunneling oxide layer having a thickness of 1.5-2.5 nm;

[0029] or,

[0030] The first passivation layer is set to fully cover the back side of the silicon wafer, the first doped silicon crystal layer and the second doped silicon crystal layer are both located on the side of the first passivation layer away from the back side of the silicon wafer, the second doped silicon crystal layer and the part of the first passivation layer covered by it form a second semiconductor layer, and the first doped silicon crystal layer and the second doped silicon crystal layer are both doped polycrystalline layers.

[0031] 11. The back contact cell according to technical solution 9, wherein the first passivation layer comprises a first tunneling oxide layer, and the first doped silicon crystal layer is a first doped polycrystalline layer;

[0032] The ratio of the thickness of the silicon alloy layer to the thickness of the first tunneling oxide layer is 1:0.05-1.25, and / or the thickness of the first tunneling oxide layer is 1.5-2.5 nm.

[0033] 12. The back-contact battery according to Technical Solution 1, wherein the extended end of the second semiconductor layer is in direct contact with the first semiconductor layer in the thickness direction or a mask layer is provided.

[0034] Optionally in some other technical solutions, the width of the insulating groove is 0.05-0.3 mm.

[0035] 13. The back-contact battery according to technical solution 1, wherein the back-contact battery is not provided with a fine grid and a main grid.

[0036] In some other technical solutions, optionally, the back-contact battery also includes a front passivation layer arranged outward from the front of the silicon wafer, wherein the front passivation layer is any one of a third intrinsic amorphous silicon, a third intrinsic amorphous silicon superimposed with doped amorphous silicon, a third intrinsic amorphous silicon superimposed with doped microcrystalline silicon, tunneling silicon oxide, and tunneling silicon oxide superimposed with doped polycrystalline silicon.

[0037] 14. In a second aspect, the present disclosure provides a method for preparing a back-contact battery, comprising the following steps:

[0038] S1. Forming a first semiconductor layer on the back side of a silicon wafer and defining first openings in the first semiconductor layer at intervals along the Y-axis of the silicon wafer; then forming a second semiconductor layer on the back side and defining second openings in a portion of the second semiconductor layer that covers an outer surface of the first semiconductor layer; wherein the first semiconductor layer comprises a first doped silicon crystal layer, and the second semiconductor layer comprises a second doped silicon crystal layer;

[0039] S2. Forming a silicon alloy layer and a metal conductive layer in sequence on the back surface obtained in S1 by a magnetron sputtering process, wherein the sputtering power when forming the silicon alloy layer is controlled to be 5-12 kW, optionally 5-10 kW, and the sputtering power when forming the metal conductive layer is controlled to be 1-4 kW, and the sheet resistance of the obtained silicon alloy layer is 60-100 Ω / □, and the sheet resistance of the metal conductive layer is 3-50 Ω / □;

[0040] S3. After the sputtering, performing a third etching directly on the portion of the silicon alloy layer and the metal conductive layer located between the first opening area and the second opening area to form an insulating groove.

[0041] 15. The method for preparing a back-contact battery according to technical solution 14, wherein the conditions of the magnetron sputtering process in S2 include: a vacuum degree of 5×10-3 Pa to 5×10-1 Pa, a sputtering time of 10-60 s when forming a silicon alloy layer, and a sputtering time of 30-300 s when forming a metal conductive layer;

[0042] and / or,

[0043] The metal target material used is at least one of nickel metal, aluminum metal, platinum metal, cobalt metal, titanium metal, tungsten metal, nickel-containing alloy, aluminum-containing alloy, platinum-containing alloy, cobalt-containing alloy, titanium-containing alloy, and tungsten-containing alloy.

[0044] 16. The method for preparing a back-contact battery according to technical solution 14, wherein the third etching in S3 adopts laser technology, and the laser used is a laser with a pulse width of picoseconds.

[0045] 17. The method for preparing a back-contact battery according to technical solution 14, wherein the process of S1 specifically includes:

[0046] S101, providing silicon wafers;

[0047] S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer, wherein the first semiconductor layer includes a first passivation layer and a first doped silicon crystal layer in sequence formed on the back side;

[0048] S103, performing a first etching on the first semiconductor layer and the mask layer in the preset area on the back side obtained in S102 to form first opening areas distributed at intervals;

[0049] S104, then removing all remaining mask layers;

[0050] S105, then forming a second semiconductor layer on the back surface obtained in S104, wherein the second semiconductor layer includes a second passivation layer and a second doped silicon crystal layer sequentially formed on the back surface;

[0051] S106 , performing a second etching on the area on the back side obtained in S105 where the first semiconductor layer remains, so as to expose the first semiconductor layer and form a second opening area spaced apart from the first opening area.

[0052] 18. The method for preparing a back-contact battery according to technical solution 14, wherein the process of S1 specifically includes:

[0053] S11, provide silicon wafer;

[0054] S12, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer, wherein the first semiconductor layer includes a first passivation layer and a first doped silicon crystal layer in sequence formed on the back side;

[0055] S13, performing a first etching on the first doped silicon crystal layer and the mask layer in the preset area on the back side obtained in S12 to form first opening areas distributed at intervals;

[0056] S14, then removing all remaining mask layers;

[0057] S15, then forming a second doped silicon crystal layer on the back surface obtained in S14, the second doped silicon crystal layer and a portion of the first passivation layer covered by the second doped silicon crystal layer forming a second semiconductor layer;

[0058] S16, then performing a second etching on the area on the back side obtained in S15 where the first semiconductor layer remains, to expose a portion of the first semiconductor layer, thereby forming a second opening area spaced apart from the first opening area.

[0059] 19. In a third aspect, the present disclosure proposes a back-contact battery, which is prepared by the preparation method of a back-contact battery as described in any one of technical solutions 14 to 18.

[0060] 20. In a fourth aspect, the present disclosure proposes a battery assembly, which includes a back-contact battery as described in any one of technical solutions 1 to 13, or a back-contact battery as described in technical solution 19, and a welding strip directly arranged on the surface of the silicon alloy layer corresponding to different conductive areas in the back-contact battery. Beneficial effects:

[0061] The present disclosure adopts the above-mentioned technical solution, especially adopts a silicon alloy layer and a metal conductive layer with a specific suitable high conductivity (i.e., low square resistance) as an electrode lead-out method, replacing the electrode lead-out method of the conventional back-contact battery in which the transparent conductive film layer is combined with the silver metal fine grid line and the main grid line. There is no need to set up additional fine grids and main grids, the process is simpler, and there is no need to use expensive low-temperature silver paste and transparent conductive film layers (such as ITO), which greatly reduces the production cost of the battery and ensures excellent battery conversion efficiency. Among them, the silicon alloy layer can not only achieve good ohmic contact between silicon and metal, ensuring good ohmic contact between the semiconductor layer and the metal conductive layer, but also has a suitable high conductivity (i.e., low square resistance), so it can directly replace the transparent conductive film, silver fine grid and main grid in the back-contact battery of the prior art. In particular, the stacking of silicon alloy layers and metal conductive layers can not only form good ohmic contact at the interfaces of each layer, but also utilize the metal conductive layer to improve the conductivity of the overall material, which is more conducive to the conduction of current. At the same time, the surface of the metal conductive layer has high hardness and wear resistance, which is more conducive to the welding of solder strips on its surface during component packaging.

[0062] In the preparation method disclosed herein, by controlling magnetron sputtering to deposit metal, high-energy particles (usually argon ions) are used to bombard the surface of the metal target material to cause it to sputter. In the sputtering process under suitable sputtering power conditions, a relatively uniform and dense silicon alloy layer with high crystallinity can be formed. In the process of the subsequent metal conductive layer, the surface of the silicon alloy layer will not be damaged due to the high ion energy, which is conducive to forming a relatively firm interface between the silicon alloy layer and the metal conductive layer, thereby reducing contact resistance and interface loss and improving the transmission efficiency of the current. Moreover, during the sputtering process, the metal atoms flying out from the surface of the metal target material will be deposited on the surface of the first semiconductor layer and the second semiconductor layer, react with the silicon atoms on its surface to form a silicon alloy layer, and with the continued sputtering under suitable sputtering power conditions, a metal conductive layer without silicon is formed, wherein after the silicon alloy layer is sputtered, there is no need to perform annealing treatment, but directly sputtering to form a metal conductive layer, reducing the subsequent annealing process steps of the silicon alloy layer, both forming a higher quality silicon alloy layer and simplifying the process flow. Among them, the reasons for forming a higher quality silicon alloy layer include at least the following: when using a suitable high sputtering power magnetron sputtering to form a silicon alloy layer, 1. high-energy metal target ions (such as nickel ions) bombard the silicon surface, causing the rearrangement and activation of the silicon surface, which can enhance the bonding between silicon and nickel and form a stronger, higher-quality interface; 2. Improved crystal quality. The magnetron sputtering atomic activation process can make the sputtered atoms more uniformly deposited on the surface, and may introduce defects that are conducive to bonding, thereby improving the overall performance of the silicon alloy layer; magnetron sputtering atomic activation helps to reduce interface defects and improve the quality and performance of silicon-nickel alloys through more uniform atomic deposition and interface activation. 3. Control of alloy component distribution: Magnetron sputtering atomic activation can more accurately control the distribution of silicon and metal elements (such as nickel) on the surface of the corresponding semiconductor layer, thereby forming a uniform silicon alloy layer.

[0063] In the optional solution disclosed herein, especially for the combined passivated back contact cell, the third back etching using laser grooving is easier, which simplifies the process flow. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0065] FIG1 is a schematic structural diagram of a back contact battery in the prior art in which a first main grid, a second main grid and an insulating layer are arranged.

[0066] FIG2 is a schematic structural diagram of an implementation of a back contact battery in this embodiment.

[0067] FIG3 is a schematic structural diagram of a first opening area in Example 1;

[0068] FIG4 is a schematic structural diagram of a second semiconductor layer formed on FIG3 ;

[0069] FIG5 is a schematic structural diagram of a second opening area in FIG4;

[0070] FIG6 is a schematic structural diagram of a silicon alloy layer and a metal conductive layer formed on FIG5 ;

[0071] FIG7 is a schematic structural diagram of a back contact battery having another structure formed by opening an insulating groove in FIG6 .

[0072] Explanation of the accompanying symbols: 1. Silicon wafer, 2. First tunneling oxide layer, 3. Front stack, 4. First doped polycrystalline layer, 5. Second intrinsic amorphous silicon layer, 6. Second doped silicon crystal layer, 7. Silicon alloy layer, 8. Metal conductive layer, 9. Insulation groove, 10. First main gate, 11. Second main gate, 12. Insulation layer, 13. First fine gate, 14. Second fine gate. DETAILED DESCRIPTION

[0073] In this disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0074] In the present disclosure, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0075] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. Among them, the terms "optional" and "optional" all mean that they may be included or not (or may be present or not).

[0076] In the present disclosure, the sheet resistance of the corresponding layer refers to the surface of the structure where the layer is located after the deposition of the layer, which is tested by the four-point probe (4PP) method. For example, the sheet resistance of the metal conductive layer is obtained by testing the surface coated with a silicon alloy layer and a metal conductive layer. The working principle of the four-point probe method is to contact the material with four equidistant and collinear probes for measurement. This method is called the four-point probe method. Direct current (DC) is driven between the two outer probes, and the voltage is measured between the two inner probes. When measuring small samples or near the edge, a geometric correction factor is usually required because the current path is affected by the geometric structure of the sample. The most accurate value can be obtained in the center area of ​​the sample. In the present disclosure, the sheet resistance of the corresponding layer is obtained by performing the same test in the center area of ​​the sample to be measured.

[0077] In the first aspect, the present disclosure provides a back-contact battery, comprising a silicon wafer having a front side and a back side, a first semiconductor layer and a second semiconductor layer arranged on the back side and alternately arranged along the Y-axis direction of the silicon wafer, the first semiconductor layer comprising a first doped silicon crystal layer, the second semiconductor layer comprising a second doped silicon crystal layer, and the end of the second semiconductor layer extends to the outer surface of the adjacent end of the first semiconductor layer to form a transition region, the back-contact battery also comprises a silicon alloy layer and a metal conductive layer arranged in sequence outward along the Z-axis direction of the silicon wafer, the silicon alloy layer is arranged on the outer surface of the second semiconductor layer and extends to the outer surface of the adjacent first doped silicon crystal layer, and an insulating groove is provided on a portion of the silicon alloy layer corresponding to the transition region and its corresponding metal conductive layer; wherein the silicon alloy layer contains metal silicide and the square resistance of the silicon alloy layer is 60-100Ω / □, and the square resistance of the metal conductive layer is 3-50Ω / □.

[0078] In the present disclosure, the metal conductive layer does not contain silicon. The metal conductive layer may be composed of one or more metal elements.

[0079] In some optional embodiments of the present disclosure, the metal elements contained in the metal silicide and the metal conductive layer independently include at least one of nickel, aluminum, platinum, cobalt, titanium, and tungsten.

[0080] In the present disclosure, a silicon alloy layer and a metal conductive layer are provided on the outer surfaces of the first semiconductor layer and the second semiconductor layer (corresponding to the preparation method, silicon and metal are magnetron sputtered on the silicon surfaces of the two semiconductor layers to react to obtain metal silicide, which can form a silicon alloy layer with high conductivity). The silicon alloy layer can form a good current channel between the semiconductor layer and the metal conductive layer, allowing electrons and holes inside the silicon wafer to escape to the battery surface and conduct to the external circuit. The reason why the silicon alloy layer can form a good ohmic contact is that, taking metal nickel as an example, it is reflected in at least the following aspects:

[0081] 1. Compatibility: Silicon and nickel have similar lattice structures, with similar lattice parameters and crystal structures, which makes them highly compatible when forming the SiNi2 alloy phase. Compatibility means having a similar arrangement in the crystal structure, which facilitates interaction and diffusion between atoms.

[0082] 2. Chemical affinity: Silicon and nickel have a certain chemical affinity. When adsorbed on the silicon surface, nickel metal forms a strong chemical bond with silicon, forming a Si-Ni bond, which helps form a stable SiNi2 alloy phase. This chemical affinity helps increase the fluctuation boundary diffusion rate and promotes the interaction between silicon and nickel.

[0083] 3. Conductivity: The SiNi2 alloy phase has a high conductivity. Due to the high conductivity of the SiNi2 alloy phase, the current can be effectively conducted between the metal and the semiconductor, thereby forming a good ohmic contact.

[0084] Moreover, metal silicide can significantly reduce the direct contact resistance between silicon and metal (forming excellent ohmic contact between silicon and metal), and the formation of metal silicide requires a certain temperature, such as WSix, TiSix, CoSix, PtSix, NiSix, where x is a natural number that satisfies the valence balance. Their formation temperatures decrease in sequence, among which nickel silicide (NiSix) requires the lowest formation temperature, especially the lattice symmetry and crystal silicon constant of the single crystal NiSi2 phase are close to those of single crystal silicon. Therefore, the formation of the NiSi2 phase requires the least driving force, that is, the required temperature is the lowest, and it can even be formed when metal nickel is plated on the surface of single crystal silicon and heated to 150°C. In the preparation method disclosed herein, a suitable metal silicide silicon alloy layer can be selected based on the temperature characteristics of the passivation structure of each semiconductor layer. For example, nickel silicide, aluminum silicide, and platinum silicide have relatively low formation temperatures and are suitable for configuring heterojunction structures with intrinsic amorphous silicon passivation and low-temperature processes for combined passivation structures. The relatively high temperatures required for W, Ti, and Co to form silicon alloys with silicon make them suitable for configuring Topcon cell structures with tunneling oxide passivation. The present disclosure can be widely applied in the production of solar cells and semiconductor chips.

[0085] Optionally, the metal silicide and the metal conductive layer contain the same metal element.

[0086] Optionally, the metal elements contained in the silicon alloy layer (including metal silicide) and the metal conductive layer independently include at least one of nickel, aluminum, and platinum.

[0087] In the present disclosure, the silicon alloy layer includes metal silicide and may also inevitably contain metal elements or metal alloys. This is because when the metal target is magnetron sputtered during preparation, part of the sputtered metal will react with the silicon on the surface of the semiconductor layer to form metal silicide, and it may also be doped with unreacted metal elements and their alloy forms with silicon.

[0088] In some optional embodiments of the present disclosure, the metal silicide includes at least one of nickel silicide, aluminum silicide, and platinum silicide, which are more suitable for being configured into a heterojunction battery structure and a back contact battery structure with a combined passivation structure, and can be prepared under a low-temperature process.

[0089] In the present disclosure, there is no limitation on the specific forms (or specific compound compositions) of various metal silicides. As long as the products are the products of the reaction of raw material elements containing silicon and metal, the objectives and technical effects of the present disclosure can be achieved. For example, the nickel silicide can be in the form of NiSi2, NiSi, and Ni2Si.

[0090] In some optional embodiments of the present disclosure, the metal conductive layer includes at least one of a nickel layer, an aluminum layer, and a platinum layer.

[0091] In some optional embodiments of the present disclosure, the thickness ratio of the silicon alloy layer to the metal conductive layer is 1:1-15, for example, 1:1, 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, 1:10, 1:11, 1:12, 1:13, 1:14, 1:15, etc., with 1:3-10 being an option. Using an appropriate thickness ratio allows for good ohmic contact between the silicon interface and the metal conductive layer while achieving sufficient conductivity, further balancing the overall material conductivity and good contact at each interface.

[0092] In some optional embodiments of the present disclosure, the thickness of the silicon alloy layer is 2-7 nm, with an optional thickness of 2-6 nm. The thin, high-quality silicon alloy layer required by the present disclosure, combined with the metal conductive layer, facilitates the formation of a good current path, allowing electrons and holes within the silicon wafer to escape to the battery surface and conduct to the external circuit, thereby improving battery conversion efficiency.

[0093] Optionally, the thickness of the metal conductive layer is 5-30 nm, for example, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 20, 25, 28, 30, etc. The thickness is appropriate to provide suitable conductivity for conducting current and a surface suitable for soldering with a soldering ribbon during packaging, which is more conducive to balancing the requirements of conductivity, soldering with a soldering ribbon, and cost reduction.

[0094] In some optional embodiments of the present disclosure, the silicon alloy layer further contains a doping element, and the doping element includes boron or phosphorus.

[0095] It can be understood that, in the present disclosure, one of the first doped silicon crystal layer and the second doped silicon crystal layer is N-type and the other is P-type.

[0096] In some optional embodiments of the present disclosure, the ratio of the surface doping index of the silicon alloy layer to the first doped silicon crystal layer and the second doped silicon crystal layer is 1:30-1000:150-8000; wherein, 1:50-800:400-7000 is optional; wherein, 1:50-600:400-6000 is optional, wherein the surface doping index is the ratio of the effective doping concentration of the corresponding doped silicon layer to the thickness of the doped silicon layer. In the scheme of the present disclosure using the above-mentioned optional surface doping index ratio of the silicon alloy layer to the first doped silicon crystal layer and the second doped silicon crystal layer, the thickness and doping concentration of each layer are matched, which can better control the concentration of carriers, improve electron mobility and reduce resistance, and is more conducive to improving the stability of the preparation process and the overall performance of the battery.

[0097] In some optional embodiments of the present disclosure, the effective doping concentration of the doping element in the silicon alloy layer is 5e15cm-3 to 5e17cm-3. The effective doping concentration of the doping element in the silicon alloy layer of the present disclosure is suitably low, allowing for a suitably thin thickness, thereby improving battery conversion efficiency while taking into account cost and process requirements.

[0098] In some optional embodiments of the present disclosure, the thickness ratio of the silicon alloy layer to the second doped silicon crystal layer is 0.04-0.6:1, for example, 0.04:1, 0.1:1, 0.2:1, 0.3:1, 0.4:1, 0.5:1, 0.6:1, etc. This suitable thickness ratio of the specific structural layers can reduce the consumption of silicon and doping elements in the second doped silicon crystal layer, while also establishing good contact at the interface between the second doped silicon crystal layer and the metal conductive layer, forming a good current transmission channel, and further improving current transmission efficiency, thereby enhancing battery performance.

[0099] In some optional embodiments of the present disclosure, the thickness of the first doped silicon crystal layer is 50-300 nm, and the effective doping concentration is 1e19 cm-3-4e20 cm-3.

[0100] The second doped silicon crystal layer may be a doped amorphous layer or a doped microcrystalline layer.

[0101] In some optional embodiments of the present disclosure, the thickness of the second doped silicon crystal layer is 10-50 nm, and the effective doping concentration is 1e19 cm-3-4e20 cm-3. The thickness of the second doped silicon crystal layer of the present disclosure is thicker than that of the prior art to provide an appropriate amount of silicon for the formation of the silicon alloy layer.

[0102] In some optional embodiments of the present disclosure, the first semiconductor layer further includes a first passivation layer disposed on the back side of the silicon wafer, at least a portion of the first passivation layer being located between the back side of the silicon wafer and the first doped silicon crystal layer. The first passivation layer may include a first intrinsic amorphous silicon layer or a first tunneling oxide layer.

[0103] In some optional embodiments of the present disclosure, the second semiconductor layer also includes a second passivation layer arranged on the back side of the silicon wafer, and the second passivation layer is located between the back side of the silicon wafer and the second doped silicon crystal layer; the second passivation layer includes a second intrinsic amorphous silicon layer or a second tunneling oxide layer.

[0104] In the back-contact battery disclosed in the present invention, the passivation structure of the first semiconductor layer and the second semiconductor layer can be one of a combined passivation structure (i.e., the first passivation layer and the second passivation layer are tunneling oxide layer and intrinsic amorphous silicon respectively), a heterojunction passivation structure (i.e., the passivation layers of the two semiconductor layers are both intrinsic amorphous silicon), and a tunneling polycrystalline structure (i.e., the passivation layers of the two semiconductor layers are both tunneling oxide layers, and the corresponding doped layers are both polycrystalline layers).

[0105] Optionally, the thickness of the second intrinsic amorphous silicon layer is 5-15 nm, and the thickness of the second tunneling oxide layer is 1.5-2.5 nm;

[0106] In some optional embodiments of the present disclosure, the first passivation layer is disposed to fully cover the back side of the silicon wafer. The first doped silicon crystal layer and the second doped silicon crystal layer are both located on a side of the first passivation layer away from the back side of the silicon wafer. The second doped silicon crystal layer and the portion of the first passivation layer it covers form a second semiconductor layer. The first doped silicon crystal layer and the second doped silicon crystal layer are both doped polycrystalline layers. Optionally, the first passivation layer may be a first intrinsic amorphous silicon layer or a first tunneling oxide layer.

[0107] In the above structure, the second doped silicon crystal layer shares part of the first passivation layer to form a second semiconductor layer. The first doped silicon crystal layer and the second doped silicon crystal layer are both doped polycrystalline layers. Because polycrystalline silicon is composed of many grains, there are grain boundaries between the grains. This structure makes polycrystalline silicon have higher crystallinity and grain boundary density than the amorphous layer, which is conducive to the formation of the silicon alloy layer. It can enable the metal to form a better bond at the grain boundary of the polycrystalline silicon to form a stable silicon alloy layer, which is more conducive to the formation of a high-quality silicon alloy layer, while improving the consistency of the silicon alloy layer in the first doped silicon crystal layer region and the second doped silicon crystal layer region.

[0108] In some optional embodiments of the present disclosure, the first passivation layer comprises a first tunneling oxide layer, and the first doped silicon crystal layer is a first doped polycrystalline layer. Optionally, the second passivation layer is a second intrinsic amorphous silicon layer, and the second doped silicon crystal layer can be a doped amorphous layer or a doped microcrystalline layer. In this solution, the back-contact cell has a combined passivation structure, which has higher cell conversion efficiency than other passivation structures.

[0109] Optionally, the thickness ratio of the silicon alloy layer to the first tunneling oxide layer is 1:0.05-1.25. The thickness ratio of the silicon alloy layer to the first tunneling oxide layer is appropriate, which can balance the electron mobility and the tunneling effect to a certain extent, and is more conducive to improving the conductivity of the silicon alloy layer while maintaining the stability of the battery.

[0110] Optionally, the thickness of the first tunnel oxide layer is 1.5-2.5 nm.

[0111] In some optional embodiments of the present disclosure, the extended end of the second semiconductor layer is in direct contact with the first semiconductor layer in the thickness direction or a mask layer is provided. Of course, in some optional embodiments of the present disclosure, a mask layer may not be provided between the two semiconductor layers. Compared with the method of providing a mask layer between the first semiconductor layer and the second semiconductor layer, this method is more conducive to reducing impurities or surface scattering introduced by the mask layer, and helps to improve the carrier migration performance in the device.

[0112] In some optional embodiments of the present disclosure, the width of the insulating groove is 0.05-0.3 mm.

[0113] Optionally, the width of the insulating groove is 0.05-0.15 mm. The present disclosure matches the insulating layer with an appropriate width to a specific silicon alloy layer, which can prevent electron migration between the silicon alloy layers, avoid unnecessary electron loss, and is more conducive to the isolation of the first semiconductor layer and the second semiconductor layer, and better lead-out electrodes.

[0114] In some optional embodiments of the present disclosure, the back-contact cell further includes a front passivation layer disposed outwardly on the front side of the silicon wafer.

[0115] Optionally, the front passivation layer is any one of third intrinsic amorphous silicon, third intrinsic amorphous silicon superimposed with doped amorphous silicon, third intrinsic amorphous silicon superimposed with doped microcrystalline silicon, tunneling silicon oxide, and tunneling silicon oxide superimposed with doped polycrystalline silicon.

[0116] In the present disclosure, an anti-reflection layer may or may not be provided on the outer surface of the front passivation layer according to requirements.

[0117] The thickness of the front passivation layer, the effective doping concentration when containing doped amorphous silicon or doped polycrystalline silicon, and the specific composition and thickness of the anti-reflection layer can all be determined according to prior art practices and can be configured as disclosed herein. For example, the thickness of the front passivation layer is 5-30 nm, the effective doping concentration of the doped amorphous silicon or doped polycrystalline silicon is 1e19 cm⁻³ to 1e20 cm⁻³, and the thickness of the anti-reflection layer is 50-150 nm. The anti-reflection layer can be made of, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0118] The silicon alloy layer and metal conductive layer disclosed in the present invention have high conductivity and form excellent ohmic contact. They can be directly used as electrode lead-out lines without the need for additional transparent conductive film layers, fine grids, and main grids. Instead, they can directly conduct current, with a short manufacturing process. At the same time, there is no need to use expensive low-temperature silver paste and transparent conductive film layers, which greatly reduces the production cost of the battery while ensuring excellent battery conversion efficiency.

[0119] In a second aspect, the present disclosure provides a method for preparing a back-contact battery, comprising the following steps:

[0120] S1. Forming a first semiconductor layer on the back side of a silicon wafer and defining first openings in the first semiconductor layer at intervals along the Y-axis of the silicon wafer; then forming a second semiconductor layer on the back side and defining second openings in a portion of the second semiconductor layer that covers an outer surface of the first semiconductor layer; wherein the first semiconductor layer comprises a first doped silicon crystal layer, and the second semiconductor layer comprises a second doped silicon crystal layer;

[0121] S2. Forming a silicon alloy layer and a metal conductive layer in sequence on the back surface obtained in S1 by a magnetron sputtering process, wherein the sputtering power when forming the silicon alloy layer is controlled to be 5-12 kW (optionally 6-10 kW), and the sputtering power when forming the metal conductive layer is controlled to be 1-4 kW, and the sheet resistance of the obtained silicon alloy layer is 60-100 Ω / □, and the sheet resistance of the metal conductive layer is 3-50 Ω / □;

[0122] S3. After the sputtering, performing a third etching directly on the portion of the silicon alloy layer and the metal conductive layer located between the first opening area and the second opening area to form an insulating groove.

[0123] The present disclosure adopts an appropriate sputtering power range to form the silicon alloy layer and the metal conductive layer respectively, which can provide appropriate energy and heat for different thin film depositions, is more conducive to the formation of the silicon alloy layer and the metal conductive layer that match the silicon interface, and improves the overall performance of the battery.

[0124] In the preparation method disclosed herein, when the metal in the target material reacts with the silicon in the corresponding semiconductor layer in contact with it to form a silicon alloy layer containing metal silicide, doping elements other than silicon in the corresponding semiconductor layer are inevitably doped. The doping concentration of the doping element can be adjusted by the sputtering conditions for forming the silicon alloy layer and the doping concentration of the corresponding semiconductor layer.

[0125] In some optional embodiments of the present disclosure, the conditions of the magnetron sputtering process in S2 include: a vacuum degree of 5×10-3Pa-5×10-1Pa.

[0126] The present disclosure may select a sputtering time according to the desired layer thickness. In some optional embodiments of the present disclosure, the sputtering time for forming the silicon alloy layer is 10-60 seconds.

[0127] The present disclosure may select a sputtering time according to the desired layer thickness. In some optional embodiments of the present disclosure, the sputtering time for forming the metal conductive layer is 30-300 seconds.

[0128] In some optional embodiments of the present disclosure, the metal target material used in the magnetron sputtering process is at least one of nickel metal, aluminum metal, platinum metal, cobalt metal, titanium metal, tungsten metal, nickel-containing alloy, aluminum-containing alloy, platinum-containing alloy, cobalt-containing alloy, titanium-containing alloy, and tungsten-containing alloy.

[0129] The third etching of S4 of the present disclosure may only etch the silicon alloy layer, or may penetrate part of the second semiconductor layer (such as the second doped silicon crystal layer) or the entire layer (i.e., penetrate the second passivation layer) in terms of depth, forming insulating grooves of different depths or thicknesses.

[0130] The inventors of the present disclosure have also found that the existing back-contact battery still needs to remove the conductive film layer between the first opening area and the second opening area to form an insulating groove; the third etching laser groove on the back side is selectively grooved on the transparent conductive film layer or the transparent conductive film layer and the P-type (or transparent N-type) amorphous silicon passivation layer. Because the material is light-transmitting, the laser cannot be resonantly absorbed, resulting in great difficulty in laser grooves; and the wet etching method is more complicated and has a greater impact on the battery cell; it increases the difficulty of large-scale mass production of back-contact batteries. The silicon alloy layer specially set in the present disclosure can form a good ohmic contact with the corresponding doped silicon crystal layer. It is difficult to directionally groove by wet etching. Even if the groove is opened by wet etching, it may have a certain impact on other structures. In this regard, in some optional embodiments of the present disclosure, the third etching described in S3 adopts laser technology.

[0131] Optionally, the laser used is a laser with a pulse width of picoseconds. Picosecond lasers, firstly, can achieve very fine processing due to the extremely short pulses produced by picosecond lasers. Secondly, due to the very short pulse duration of picosecond lasers, the heat-affected zone produced in the material is relatively small, which helps to avoid thermal damage caused during the processing. Thirdly, the pulse energy produced by picosecond lasers is relatively low, so the material is less thermally affected during the laser irradiation process. This is more conducive to reducing the thermal impact of the laser irradiation process, avoiding thermal damage that may be caused during the processing, and minimizing deformation, cracking or other thermal effects of the material.

[0132] Optionally, the pulse width of the laser is 1-10 picoseconds.

[0133] In some optional implementations of the present disclosure, the process of S1 specifically includes:

[0134] S101, providing silicon wafers;

[0135] S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer, wherein the first semiconductor layer includes a first passivation layer and a first doped silicon crystal layer in sequence formed on the back side;

[0136] S103, performing a first etching on the first semiconductor layer and the mask layer in the preset area on the back side obtained in S102 to form first opening areas distributed at intervals;

[0137] S104, then removing all remaining mask layers;

[0138] S105, then forming a second semiconductor layer on the back surface obtained in S104, wherein the second semiconductor layer includes a second passivation layer and a second doped silicon crystal layer sequentially formed on the back surface;

[0139] S106 , performing a second etching on the area on the back side obtained in S105 where the first semiconductor layer remains, so as to expose the first semiconductor layer and form a second opening area spaced apart from the first opening area.

[0140] In some other optional implementations of the present disclosure, the process of S1 specifically includes:

[0141] S11, provide silicon wafer;

[0142] S12, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer, wherein the first semiconductor layer includes a first passivation layer and a first doped silicon crystal layer in sequence formed on the back side;

[0143] S13, performing a first etching on the first doped silicon crystal layer and the mask layer in the preset area on the back side obtained in S12 to form first opening areas distributed at intervals;

[0144] S14, then removing all remaining mask layers;

[0145] S15, then forming a second doped silicon crystal layer on the back surface obtained in S14, the second doped silicon crystal layer and a portion of the first passivation layer covered by the second doped silicon crystal layer forming a second semiconductor layer;

[0146] S16, then performing a second etching on the area on the back side obtained in S15 where the first semiconductor layer remains, to expose a portion of the first semiconductor layer, thereby forming a second opening area spaced apart from the first opening area.

[0147] The back-contact cell disclosed herein may further include the steps of sequentially forming a front passivation layer and an optional anti-reflection layer on the front side of the silicon wafer. This step may be performed after forming the second semiconductor layer and then performing a second etching step, or before or after forming the first passivation layer. The compositions of the front passivation layer and anti-reflection layer are the same as those described in the first aspect above and are not further described here.

[0148] The present disclosure also provides a back-contact battery, which is prepared by the above-mentioned back-contact battery preparation method. The structure and composition of the back-contact battery prepared by this preparation method are the same as those of the above-mentioned back-contact battery, and will not be repeated here.

[0149] The back contact battery disclosed in the present invention does not have a main grid and a fine grid. When it is used for assembly, the electrode wires can be directly welded. Specifically, the electrode is referenced when the component is packaged, that is, the outer surfaces of the P-pole region formed in the area of ​​the first semiconductor opening area and the N-pole region formed in the area of ​​the second semiconductor opening area are respectively soldered with solder strips using tin paste. The solder strips are copper strips, aluminum strips, etc.

[0150] The present disclosure also provides a battery assembly, which includes the back-contact battery described in any of the above items, and a welding strip directly provided on the surface of the silicon alloy layer corresponding to different conductive areas in the back-contact battery.

[0151] The embodiments of the present disclosure are described in detail below, which are exemplary and are only configured to explain the present disclosure but are not to be construed as limiting the present disclosure.

[0152] Example 1

[0153] A back contact cell as shown in FIG7 is prepared according to the following method:

[0154] S1 includes:

[0155] S101, providing a silicon wafer 1;

[0156] S102. First, a front passivation layer (specifically, a third intrinsic amorphous silicon layer with a thickness of 6 nm, a doped amorphous silicon layer with a thickness of 10 nm and an effective doping concentration of 5e19 cm-3) and a 100 nm thick anti-reflection layer (specifically, silicon nitride) are formed on the front surface to form a front stack 3. Then, a first semiconductor layer and a mask layer (specifically, silicon nitride with a thickness of 50 nm) are formed on the back surface of the silicon wafer 1. The first semiconductor layer includes a first tunneling oxide layer 2 and an N-type first doped polycrystalline layer 4, which are sequentially formed on the back surface. The first doped polycrystalline layer 4 has a thickness of 80 nm and an effective doping concentration of 1e20 cm-3. The first tunneling oxide layer 2 has a thickness of 2 nm.

[0157] S103, as shown in FIG3, performing a first etching on the first semiconductor layer and the mask layer on the back surface obtained in S102 to form first opening regions Wp with a width of 500 μm and distributed at intervals;

[0158] S104, then removing all remaining mask layers;

[0159] S105. Then, a second semiconductor layer is formed on the back surface obtained in S104. As shown in FIG4 , the second semiconductor layer includes a second intrinsic amorphous silicon layer 5 and a P-type second doped silicon crystal layer 6 (specifically, a microcrystalline layer) sequentially formed on the back surface. The second doped silicon crystal layer 6 has a thickness of 10 nm and an effective doping concentration of 1e20 cm-3. The second intrinsic amorphous silicon layer 5 has a thickness of 10 nm.

[0160] S106 , performing a second etching on the area on the back side where the first semiconductor layer remains obtained in S105 , as shown in FIG5 , to expose the first semiconductor layer and form a second opening area Wn with a width of 150 μm spaced apart from the first opening area Wp.

[0161] S2. Sputtering the back surface obtained in S106 by magnetron sputtering, controlling sputtering process parameters, so that a silicon alloy layer 7 and a metal conductive layer 8 containing no silicon are formed in sequence at positions in contact with silicon on the outer surfaces of the first semiconductor layer and the second semiconductor layer.

[0162] Specifically, the battery cell obtained in S106 is placed in a magnetron sputtering device, evacuated to a vacuum degree of 5×10-2Pa, and the sputtering power of the nickel target is set to 8kW; sputtering is performed for 10s; a silicon alloy layer 7 containing nickel silicide with a thickness of 4nm is obtained; the square resistance of the silicon alloy layer 7 is 80Ω / □, and it contains nickel silicide (NiSi2, NiSi) and doped element phosphorus with an effective doping concentration of 1e16cm-3.

[0163] The sputtering power was then adjusted to 3 kW, and sputtering was continued for 150 seconds. This resulted in a 20 nm thick silicon-free metal conductive layer 8 (specifically, a nickel layer). The silicon alloy layer 7 and the silicon-free metal conductive layer 8 formed a laminated conductive film, as shown in FIG6 . The sheet resistance of the metal conductive layer 8 was 25 Ω / □.

[0164] S3. Then, laser scribing is used to scribe the portion of the laminated conductive film (i.e., the silicon-free metal conductive layer 8 and the silicon alloy layer 7) located between the second opening area and the first opening area on the back side obtained in S2 to form an insulating groove. As shown in Figure 7, an insulating groove 9 with a width of 0.05 mm is formed; the third etching uses laser technology, and the laser pulse width is 5 picoseconds.

[0165] Example 2

[0166] The method of Example 1 was followed, except that the magnetron sputtering process parameters for the silicon alloy layer in S2 were modified. Specifically, the sputtering power of the nickel target was set to 12 kW, the sputtering was continued for 10 seconds, and a 7 nm thick silicon alloy layer containing nickel silicide was obtained. The sheet resistance of the silicon alloy layer was 70 Ω / □, and the effective doping concentration was 5e16 cm⁻³. The sputtering process for the metal conductive layer and subsequent steps were then performed according to Example 1.

[0167] Example 3

[0168] The method of Example 1 was followed, except that the magnetron sputtering process in S2 was different. Specifically, the cell obtained in S106 was placed in a magnetron sputtering apparatus, evacuated to a vacuum of 5×10-2 Pa, and the sputtering power of the nickel target was set to 5 kW. Sputtering was performed for 23 seconds to obtain a silicon alloy layer containing nickel silicide with a thickness of 6 nm. The silicon alloy layer had a sheet resistance of 70 Ω / □ and an effective doping concentration of 2e16 cm-3.

[0169] Then, the sputtering power was adjusted to 2 W, and sputtering was continued for 130 s to obtain a silicon-free metal conductive layer (specifically, a nickel layer) with a thickness of 15 nm and a sheet resistance of 35 Ω / □.

[0170] Example 4

[0171] The method of Example 1 was followed, except that the magnetron sputtering process in S2 was different. Specifically, the cell obtained in S106 was placed in a magnetron sputtering apparatus, evacuated to a vacuum of 5×10-2 Pa, and the sputtering power of the nickel target was set to 5 kW. Sputtering was performed for 15 seconds to obtain a silicon alloy layer containing nickel silicide with a thickness of 4 nm. The silicon alloy layer had a sheet resistance of 82 Ω / □ and an effective doping concentration of 1e16 cm-3.

[0172] Then, sputtering was continued for 220 seconds at a sputtering power of 3 kW to obtain a silicon-free metal conductive layer (specifically, a nickel layer) having a thickness of 28 nm and a sheet resistance of 20 Ω / □.

[0173] Example 5

[0174] The method of Example 1 is referred to, except that the metal nickel targets of the silicon alloy layer and the metal conductive layer in S2 are replaced by aluminum targets, and the thickness of the formed aluminum-silicon alloy layer remains unchanged (the same as the silicon alloy layer in Example 1, and the same applies to other examples), the square resistance is 90Ω / □, and the effective doping concentration is 5e15cm-3; the thickness of the formed aluminum metal conductive layer remains unchanged, and the square resistance is 22Ω / □.

[0175] Example 6

[0176] The method of Example 1 is referred to, except that the metal nickel targets of the silicon alloy layer and the metal conductive layer in S2 are replaced by platinum, and the thickness of the formed platinum-silicon alloy layer remains unchanged, the square resistance is 85Ω / □, and the effective doping concentration is 1e16cm-3; the thickness of the formed platinum metal conductive layer remains unchanged, and the square resistance is 32Ω / □.

[0177] Example 7

[0178] The method of Example 1 is referred to, except that the thickness of the metal conductive layer in S2 is adjusted to 30 nm. After calculation, the ratio of the thickness of the metal nickel target replaced by the silicon alloy layer and the metal conductive layer is 1:7.5; in order to meet the thickness of the metal conductive layer, the process parameters that need to be adjusted accordingly are: the sputtering time is adjusted to 225 s.

[0179] Example 8

[0180] The method of Example 1 is referred to, except that the effective doping concentration of the silicon alloy layer in S2 is adjusted to 5e15 cm-3. After calculation, the ratio of the surface doping index of the silicon alloy layer to the first doped silicon crystal layer and the second doped silicon crystal layer is 1:1000:8000. In order to meet the effective doping concentration of the silicon alloy layer, the process parameters that need to be adjusted accordingly are: the sputtering power is adjusted to 5 kW, and the sputtering time is adjusted to 18 s.

[0181] Example 9

[0182] The method of Example 1 is referred to, except that the thickness of the silicon alloy layer in S2 is adjusted to 6 nm. After calculation, the ratio of the surface doping index of the silicon alloy layer to the first doped silicon crystal layer and the second doped silicon crystal layer is 1:750:6000. After calculation, the ratio of the thickness of the silicon alloy layer to the second doped silicon crystal layer is 0.6:1. In order to meet the thickness of the silicon alloy layer, the process parameters that need to be adjusted accordingly are: the sputtering time is adjusted to 15 s.

[0183] Example 10

[0184] The method of Example 1 is referred to, except that the thickness of the first tunneling oxide layer in S102 is adjusted to 1 nm, so that the ratio of the thickness of the silicon alloy layer to the first tunneling oxide layer is 1:0.25.

[0185] Example 11

[0186] The method of Example 1 is referred to, except that the passivation structure is different. Specifically, the first semiconductor layer is replaced by a first intrinsic amorphous silicon layer and an N-type first doped amorphous silicon layer formed in sequence on the back side; the thickness of the first intrinsic amorphous silicon layer and the N-type first doped amorphous silicon layer are both 10 nm, and the effective doping concentration of the first doped amorphous silicon layer is 1e19 cm-3.

[0187] Example 12

[0188] The method of Example 1 is referred to, except that the structure of the second semiconductor layer in S1 is different, and is formed by the second doped silicon crystal layer 6 and the first tunneling oxide layer 2 in the corresponding region, as shown in FIG2 . Specifically, S1 is:

[0189] S11, provide silicon wafer;

[0190] S12, sequentially forming a first semiconductor layer on the back side of the silicon wafer 1, the first semiconductor layer including a first tunneling oxide layer 2 and a first doped polycrystalline layer 4 sequentially formed on the back side;

[0191] S13, performing a first etching on the first doped polycrystalline layer 4 in the preset area on the back side obtained in S12 to form first opening areas distributed at intervals;

[0192] S14, then forming a second doped silicon crystal layer 6 on the back surface obtained in S13, the second doped silicon crystal layer 6 and the portion of the first tunnel oxide layer 2 covered by the second doped silicon crystal layer 6 forming a second semiconductor layer;

[0193] S15. Then, a second etching is performed on the area of ​​the back surface obtained in S14 where the first semiconductor layer remains, to expose a portion of the first semiconductor layer, thereby forming a second opening region spaced apart from the first opening region. The thickness (or doping concentration) of each corresponding layer is the same as in Example 1, with only the structure being different.

[0194] Example 13

[0195] The method of Example 1 is referred to, except that the third etching described in S3 is wet etching. The specific process of wet etching is: using printed protective ink to form an insulating groove mask pattern on the back side to expose the area where the insulating groove is required to be formed, and then using a corrosive solution to corrode the exposed conductive film layer to form an insulating groove, and then using an alkaline solution (whose composition is specifically sodium hydroxide solution with a concentration of 2wt%) to remove the protective ink.

[0196] Example 14

[0197] The method of Example 12 is referred to, except that the metal nickel targets of the silicon alloy layer and the metal conductive layer in S2 are replaced by cobalt, the thickness of the formed silicon alloy layer remains unchanged, the square resistance is 85Ω / □, and the effective doping concentration is 5e17cm-3; the thickness of the formed metal conductive layer remains unchanged, and the square resistance is 40Ω / □.

[0198] Example 15

[0199] The method of Example 1 is referred to, except that the width of the insulating groove in S3 is 0.15 mm.

[0200] Example 16

[0201] The method of Example 1 is referred to, except that S104 is not performed, that is, part of the mask layer is retained.

[0202] Comparative Example 1

[0203] The method of Example 1 is referred to, except that S2-S3 are not performed, but a traditional conductive film layer and metal fine grid lines are used, specifically:

[0204] S01. After S1, a transparent conductive film layer (ITO) is laid on the first semiconductor layer and the second semiconductor layer in sequence to fully cover the outside. The thickness of the transparent conductive film layer is 100 nm.

[0205] S02. Then, a third etching is performed on the transparent conductive film layer portion on the back side located in the transition area between the second opening area and the first opening area by wet etching to form an insulating groove 9 (the width is the same as that in Example 1), that is, wet grooving; the specific process of wet etching is: using printed protective ink to form an insulating groove mask pattern on the back side to expose the area where the insulating groove is required to be formed, and then using a corrosive solution to corrode the exposed conductive film layer to form an insulating groove 9, and then using an alkaline solution (whose composition is specifically sodium hydroxide solution with a concentration of 2wt%) to remove the protective ink.

[0206] S03, forming metal fine gate lines (i.e., first fine gate 13 and second fine gate 14) on the second opening region and the corresponding region of the first opening region, respectively. The metal fine gate lines are arranged parallel to the first semiconductor layer and the second semiconductor layer and parallel to the X-axis direction of the silicon wafer;

[0207] Then proceed to the following steps S5-S6:

[0208] S5. Alternately prepare an insulating layer 12 on the surface of the first opening area and the surface of the second opening area; the insulating layer 12 is prepared by printing insulating ink in a screen printing manner.

[0209] S6. Prepare the first busbar 10 and the second busbar 11 along the Y-axis direction in the lateral direction where the insulating layer 12 is provided, as shown in FIG1 . The preparation process is screen printing of silver busbars.

[0210] Comparative Example 2

[0211] The method of Example 1 was followed, except that the magnetron sputtering process in S2 was different. Specifically, the cell obtained in S106 was placed in a magnetron sputtering apparatus, evacuated to a vacuum of 5×10-2 Pa, and the sputtering power of the nickel target was set to 8 kW. Sputtering was performed for 10 seconds to obtain a 4 nm thick silicon alloy layer containing nickel silicide. Sputtering was then continued for 50 seconds at a sputtering power of 8 kW to obtain a 20 nm thick silicon-free metal conductive layer (specifically, a nickel layer). The silicon alloy layer had a sheet resistance of 55 Ω / □ and an effective doping concentration of 1e16 cm-3. The silicon-free metal conductive layer (specifically, the nickel layer) had a sheet resistance of 30 Ω / □. In this comparative example, continuing to deposit a metal conductive layer at high power on the surface of the silicon alloy layer would destroy the interface between the formed silicon alloy layer and silicon, making the silicon alloy layer closer to a metallic state, resulting in a smaller sheet resistance. However, this would affect the contact resistance of the interface, resulting in poorer performance.

[0212] Comparative Example 3

[0213] The method of Example 1 was followed, except that the magnetron sputtering process in S2 was different. Specifically, the cell obtained in S106 was placed in a magnetron sputtering apparatus, evacuated to a vacuum of 5×10-2 Pa, and the sputtering power of the nickel target was set to 3 kW. Sputtering was performed for 30 seconds to obtain a silicon alloy layer containing nickel silicide with a thickness of 4 nm. The silicon alloy layer had a sheet resistance of 50 Ω / □ and an effective doping concentration of 1e16 cm-3.

[0214] Then, the sputtering power was 8 kW and the sputtering was continued for 50 seconds to obtain a silicon-free metal conductive layer (specifically, a nickel layer) with a thickness of 20 nm and a sheet resistance of 26 Ω / □.

[0215] Comparative Example 4

[0216] The method of Example 1 is referred to, except that in S2, only low-power nickel plating of the metal conductive layer is used, and the power is relatively low so that almost no silicon alloy layer is formed; specifically, the battery cell obtained in S106 is placed in a magnetron sputtering device, and evacuated to a vacuum degree of 5×10-2Pa, and the sputtering power of the nickel target is set to 2kW, and sputtering is performed for 100s; a silicon-free metal conductive layer (specifically a nickel layer) with a thickness of 10nm is obtained, and the square resistance of the metal conductive layer is 50Ω / □.

[0217] Test Case

[0218] The back-contact cells obtained in the above examples and comparative examples were subjected to battery performance testing after welding electrode wires. Specifically, the outer surfaces of the P-pole conductive region formed in the region of the first semiconductor opening and the N-pole conductive region formed in the region of the second semiconductor opening were soldered with solder paste using the same method as used in component packaging. The soldering tape can be copper or aluminum (copper was used in this test example). The results of the performance tests are shown in Table 1.

[0219] Comparison of process flow (also called manufacturing process):

[0220] The process flow (7 steps) adopted in the embodiment is: texturing and cleaning to form a double-sided polished silicon wafer → first semiconductor layer deposition → first etching opening → second semiconductor layer deposition → second etching opening → deposition of silicon alloy layer and metal conductive layer → second etching to form insulating grooves.

[0221] Comparative Example 1 process flow (10 steps): texturing and cleaning to form a double-sided polished silicon wafer → deposition of the first semiconductor layer → first etching opening → deposition of the second semiconductor layer → second etching opening → deposition of the conductive film layer ITO → grooving of the insulating groove → screen printing of fine grid → brushing of insulating ink → screen printing of the main grid.

[0222] Non-silicon costs refer to the costs of cell production other than silicon wafers, specifically including silver paste, target materials, chemicals, gases, depreciation, and others. The calculation was based on a preliminary estimate of the non-silicon costs of conventional back-contact cell production in Comparative Example 1. In Comparative Example 1, silver paste accounted for 39% of the non-silicon costs, and target materials accounted for 7%. Because the common metal targets used in this disclosure are cheaper and used in lower quantities than ITO targets, the target material costs in this disclosure are calculated as 4% of the non-silicon costs.

[0223] Table 1

[0224] The above results show that, compared to the comparative example, the back-contact cell using the embodiment of the present disclosure does not require the additional transparent conductive film layer, fine grid, and busbar, resulting in a simpler manufacturing process. It also eliminates the need for expensive low-temperature silver paste and transparent conductive film layers (such as ITO), significantly reducing cell production costs while maintaining excellent cell conversion efficiency. The comparative example, however, fails to balance cost, manufacturing process, and cell conversion efficiency.

[0225] Optionally, according to Example 1 and Examples 2-16, it can be seen that the use of the optional back-contact battery structure disclosed in the present invention can be more conducive to improving battery conversion efficiency while ensuring low cost and simple process.

[0226] The above describes in detail the optional embodiments of the present disclosure, but the present disclosure is not limited thereto. Within the technical concept of the present disclosure, various simple variations of the technical solution of the present disclosure can be made, including combining the various technical features in any other appropriate manner. These simple variations and combinations should also be regarded as the contents disclosed by the present disclosure and fall within the scope of protection of the present disclosure. Industrial Applicability

[0227] The present disclosure adopts the above-mentioned technical solution, especially adopts a silicon alloy layer and a metal conductive layer with specific suitable high conductivity (i.e., low square resistance) as the electrode lead-out method, replacing the transparent conductive film layer combined with silver metal fine grid lines and main grid lines of conventional back-contact batteries. There is no need to set up additional fine grids and main grids, the process is simpler, and there is no need to use expensive low-temperature silver paste and transparent conductive film layers (such as ITO), which greatly reduces the production cost of the battery while ensuring excellent battery conversion efficiency.

Claims

1. A back-contact battery, comprising a silicon wafer having a front side and a back side, a first semiconductor layer and a second semiconductor layer disposed on the back side and alternately arranged along the Y-axis direction of the silicon wafer, the first semiconductor layer including a first doped silicon crystal layer, the second semiconductor layer including a second doped silicon crystal layer, and an end portion of the second semiconductor layer extending to an outer surface of an end portion of an adjacent first semiconductor layer to form a transition region, characterized in that, The back contact cell further comprises a silicon alloy layer and a metal conductive layer sequentially arranged outwardly along the Z-axis direction of the silicon wafer, wherein the silicon alloy layer is arranged on the outer surface of the second semiconductor layer and extends to the outer surface of the adjacent first doped silicon crystal layer, and an insulating groove is provided on a portion of the silicon alloy layer corresponding to the transition region and the corresponding metal conductive layer; wherein the silicon alloy layer contains metal silicide and the square resistance of the silicon alloy layer is And the sheet resistance of the metal conductive layer is 2. The back-contact battery according to claim 1, characterized in that, The metal elements contained in the metal silicide and the metal conductive layer respectively independently include at least one of nickel, aluminum, platinum, cobalt, titanium, and tungsten.

3. The back contact battery according to claim 2, characterized in that, The metal elements contained in the metal silicide and the metal conductive layer are the same.

4. The back-contact battery according to claim 2, wherein The metal silicide includes at least one of nickel silicide, aluminum silicide, and platinum silicide; and / or, The metal conductive layer includes at least one of a nickel layer, an aluminum layer, and a platinum layer.

5. The back-contact battery according to any one of claims 1 to 4, characterized in that, The thickness ratio of the silicon alloy layer to the metal conductive layer is 1:1 - 15; and / or, The thickness of the silicon alloy layer is 2 - 7 nm, and the thickness of the metal conductive layer is 5 - 30 nm.

6. The back-contact battery according to any one of claims 1 to 5, characterized in that The silicon alloy layer further contains a doping element, and the doping element includes boron or phosphorus.

7. The back contact battery according to claim 6, characterized in that, The surface doping index ratio of the silicon alloy layer to the first doped silicon crystal layer and the second doped silicon crystal layer is 1:30 - 1000:150 - 8000, where the surface doping index is the ratio of the effective doping concentration of the corresponding doped silicon layer to the thickness of the doped silicon layer.

8. The back-contact battery according to claim 7, characterized in that, The effective doping concentration of the doping element in the silicon alloy layer is 5e15 cm-3 - 5e17 cm-3; and / or, The thickness ratio of the silicon alloy layer to the second doped silicon crystal layer is 0.04 - 0.6:1; and / or, The thickness of the first doped silicon crystal layer is 50 - 300 nm, and the effective doping concentration is 1e19 cm-3 - 4e20 cm-3. The thickness of the second doped silicon crystal layer is 10 - 50 nm, and the effective doping concentration is 1e19 cm-3 - 4e20 cm-3.

9. The back-contact battery according to any one of claims 1 to 8, characterized in that, The first semiconductor layer further includes a first passivation layer provided on the back surface of the silicon wafer, and at least a part of the first passivation layer is located between the back surface of the silicon wafer and the first doped silicon crystal layer.

10. The back-contact battery according to claim 9, wherein, The second semiconductor layer further includes a second passivation layer provided on the back surface of the silicon wafer. The second passivation layer is located between the back surface of the silicon wafer and the second doped silicon crystal layer; the second passivation layer includes a second intrinsic amorphous silicon layer or a second tunneling oxide layer. The thickness of the second intrinsic amorphous silicon layer is 5 - 15 nm, and the thickness of the second tunneling oxide layer is 1.5 - 2.5 nm; Or, The first passivation layer is provided to completely cover the back surface of the silicon wafer. The first doped silicon crystal layer and the second doped silicon crystal layer are both located on the side of the first passivation layer away from the back surface of the silicon wafer. The second doped silicon crystal layer and the covered part of the first passivation layer form the second semiconductor layer. The first doped silicon crystal layer and the second doped silicon crystal layer are both doped polycrystalline layers.

11. The back-contact battery according to claim 9, characterized in that, The first passivation layer includes a first tunneling oxide layer, and the first doped silicon crystal layer is a first doped polycrystalline layer; where The thickness ratio of the silicon alloy layer to the first tunneling oxide layer is 1:0.05 - 1.25, and / or, the thickness of the first tunneling oxide layer is 1.5 - 2.5 nm.

12. The back contact battery according to any one of claims 1 to 11, characterized in that, The extension end of the second semiconductor layer is in direct contact with the first semiconductor layer in the thickness direction or a mask layer is provided; and / or, the width of the insulating groove is 0.05 - 0.3 mm.

13. The back contact battery according to any one of claims 1 to 12, characterized in that, The back contact battery does not have fine grids and main grids; and / or, The back-contact battery further includes a front passivation layer disposed outwardly on the front surface of the silicon wafer, where the front passivation layer is any one of a third intrinsic amorphous silicon, a doped amorphous silicon superimposed on the third intrinsic amorphous silicon, a doped microcrystalline silicon superimposed on the third intrinsic amorphous silicon, a tunneling oxide silicon, and a doped polysilicon superimposed on the tunneling oxide silicon.

14. A method for preparing a back-contact battery, characterized in that, It includes the following steps: S1. Form a first semiconductor layer on the back surface of the silicon wafer, and form first opening regions at intervals along the Y-axis direction of the silicon wafer on the first semiconductor layer; then form a second semiconductor layer on the back surface, and form second opening regions on the portion of the second semiconductor covering the outer surface of the first semiconductor; wherein, the first semiconductor layer includes a first doped silicon crystal layer, and the second semiconductor layer includes a second doped silicon crystal layer; S2. By means of a magnetron sputtering process, a silicon alloy layer and a metal conductive layer are sequentially formed on the obtained back surface in S1. Among them, when forming the silicon alloy layer, the sputtering power is controlled to be 5 - 12 kW, and when forming the metal conductive layer, the sputtering power is 1 - 4 kW. The sheet resistance of the obtained silicon alloy layer is The sheet resistance of the metal conductive layer is S3. After the sputtering, directly perform a third etching on the portion of the silicon alloy layer and the metal conductive layer located between the first opening region and the second opening region to form an insulating groove.

15. The method for preparing a back-contact battery according to claim 14, wherein, The conditions of the magnetron sputtering process in S2 include: the vacuum degree is 5×10−3 Pa - 5×10−1 Pa, the sputtering time for forming the silicon alloy layer is 10 - 60 s, and the sputtering time for forming the metal conductive layer is 30 - 300 s; and / or The metal target used is at least one of nickel metal, aluminum metal, platinum metal, cobalt metal, titanium metal, tungsten metal, nickel-containing alloy, aluminum-containing alloy, platinum-containing alloy, cobalt-containing alloy, titanium-containing alloy, and tungsten-containing alloy.

16. The method for preparing a back-contact battery according to claim 14 or 15, characterized in that, The third etching in S3 uses a laser technology, and the laser used is a laser with a pulse width in the picosecond level.

17. The method for preparing a back contact battery according to any one of claims 14 to 16, characterized in that, The process of S1 specifically includes: S101. Provide a silicon wafer; S102. Sequentially form a first semiconductor layer and a mask layer on the back surface of the silicon wafer. The first semiconductor layer includes a first passivation layer and a first doped silicon crystal layer formed sequentially on the back surface; S103. Perform a first etching on the first semiconductor layer and the mask layer in a preset region on the back surface obtained in S102 to form first opening regions distributed at intervals; S104. Then remove all the remaining mask layers; S105. Then form a second semiconductor layer on the back surface obtained in S104. The second semiconductor layer includes a second passivation layer and a second doped silicon crystal layer formed sequentially on the back surface; S106. Then perform a second etching on the region of the back surface obtained in S105 where the first semiconductor layer remains to expose the first semiconductor layer and form second opening regions arranged at intervals with the first opening regions.

18. The method for preparing a back-contact battery according to any one of claims 14 to 17, characterized in that, The process of S1 specifically includes: S11. Provide a silicon wafer; S12. Sequentially form a first semiconductor layer and a mask layer on the back surface of the silicon wafer. The first semiconductor layer includes a first passivation layer and a first doped silicon crystal layer formed sequentially on the back surface; S13. Perform a first etching on the first doped silicon crystal layer and the mask layer in a preset region on the back surface obtained in S12 to form first opening regions distributed at intervals; S14. Then remove all the remaining mask layers; S15. Then form a second doped silicon crystal layer on the back surface obtained in S14. The second doped silicon crystal layer and the portion of the first passivation layer covered by it form a second semiconductor layer; S16. Then, perform a second etching on the region of the back surface obtained in S15 where the first semiconductor layer remains, to expose a part of the first semiconductor layer, and form a second opening region arranged at intervals with the first opening region.

19. A back-contact battery, characterized in that, It is obtained by the method for manufacturing a back-contact battery according to any one of claims 14 to 18.

20. A battery assembly, characterized in that, It includes a back-contact battery according to any one of claims 1 to 13, or includes the back-contact battery according to claim 19, and a solder strip directly disposed on the surface of the silicon alloy layer corresponding to different conductive regions in the back-contact battery.

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