Display panel and driving method therefor and display device

Abstract

Provided are a display panel and a driving method therefor, and a display device, relating to the technical field of display. The display panel comprises: a substrate having a display area and peripheral areas; a plurality of display pixels located in the display area; and light-emitting control circuits located in the peripheral areas. The display pixels can emit light under the driving of signals provided by signal lines, and each signal line comprises a pull-up power line and a pull-down power line. The light-emitting control circuits can control on / off of the pull-up power lines or the pull-down power lines and the display pixels in response to light-emitting control signals provided by light-emitting control lines. In this way, the light-emitting control signals can be flexibly set, so that the light-emitting control circuits can flexibly control the conduction duration of the pull-up power lines or the pull-down power lines and the display pixels, and then the light-emitting duration of the display pixels is flexibly controlled. Therefore, the display panel has relatively good flexibility in driving the display pixels.

Description

Display panel and its driving method, display device

[0001] This disclosure claims priority to Chinese Patent Application No. 202410063895.7, filed on January 16, 2024, entitled “Display Panel and Driving Method Thereof, Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to a display panel and its driving method and display device. Background Technology

[0003] A display panel typically includes multiple pixels. Each pixel includes interconnected pixel circuitry and light-emitting units. The pixel circuitry can drive the light-emitting units to emit light, thereby enabling the display panel to display images.

[0004] In related technologies, pixel circuits typically include a data writing circuit and a light-emitting driving circuit. The data writing circuit is connected to the gate line, data line, and light-emitting driving circuit, and is used to control the data line to transmit data signals to the light-emitting driving circuit in response to the gate driving signal provided by the gate line. The light-emitting driving circuit is also connected to the pull-up power line and the light-emitting unit, and is used to transmit a light-emitting driving signal to the light-emitting unit based on the data signal and the pull-up power signal provided by the pull-up power line. The light-emitting unit is also connected to the pull-down power line, and the light-emitting unit can emit light under the drive of the light-emitting driving signal and the pull-down power signal provided by the pull-down power line.

[0005] Summary of the Invention

[0006] A display panel, its driving method, and a display device are provided. The technical solution is as follows:

[0007] On one hand, a display panel is provided, the display panel comprising:

[0008] A substrate having a display area and a peripheral area at least partially surrounding the display area;

[0009] Multiple display pixels arranged in an array are located in the display area. Each display pixel includes: a data writing circuit, a light-emitting driving circuit, an external compensation circuit, and a light-emitting unit. The data writing circuit is connected to a gate line, a data line, and an input node. The external compensation circuit is connected to a compensation line, a sensing line, and an output node. The light-emitting driving circuit is connected to the input node, the output node, and a pull-up power line. The light-emitting unit is connected to the output node and a pull-down power line.

[0010] Multiple sets of light-emitting control circuits are located in the peripheral area. Each set of light-emitting control circuits corresponds to at least one row of display pixels in the multiple rows of display pixels, and each set of light-emitting control circuits corresponds to different rows of display pixels. Each set of light-emitting control circuits includes: a light-emitting control circuit located on at least one side of the at least one row of display pixels in the row direction. Each light-emitting control circuit is connected between a target power line and the at least one row of display pixels, and is also connected to a light-emitting control line. It is used to control the on / off state of the target power line and the at least one row of display pixels in response to the light-emitting control signal provided by the light-emitting control line.

[0011] The target power line is either the pull-down power line or the pull-up power line.

[0012] Optionally, each set of the light-emitting control circuits corresponds to each pair of adjacent rows of display pixels.

[0013] Optionally, each of the light-emitting control circuits includes: an active layer, a gate metal layer, and a source / drain metal layer stacked sequentially on one side of the substrate;

[0014] Each of the light-emitting control circuits is connected to the at least one row of display pixels via the source / drain metal layer through a via; and each of the light-emitting control circuits is connected to two display pixels in the same column of the two adjacent rows of display pixels via the same via.

[0015] Optionally, the thickness and width of the source / drain metal layers satisfy: I_t / (t*b)≤a;

[0016] Wherein, I_t refers to the sum of the pixel currents of the multiple display pixels connected to each of the light-emitting control circuits; t refers to the thickness of the source / drain metal layer; b refers to the width of the source / drain metal layer; and a refers to the maximum withstand current density of the portion of the source / drain metal layer located in the transition via.

[0017] Optionally, each group of the light-emitting control circuits includes: one light-emitting control circuit on each side of the at least one row of display pixels in the row direction.

[0018] Optionally, one of the light-emitting control circuits located on one of the two sides is connected to a portion of the display pixels in the at least one row of display pixels, and the other light-emitting control circuit located on the other side of the two sides is connected to another portion of the display pixels in the at least one row of display pixels, excluding the portion of display pixels mentioned above.

[0019] Optionally, the light-emitting control circuit includes: a light-emitting control transistor;

[0020] The gate of the light-emitting control transistor is connected to the light-emitting control line, the first electrode of the light-emitting control transistor is connected to the target power line, and the second electrode of the light-emitting control transistor is connected to the at least one row of display pixels.

[0021] Optionally, the light-emitting control transistor is an N-type transistor.

[0022] Optionally, the light-emitting control transistor is a dual-gate transistor.

[0023] Optionally, the data writing circuit includes: a data writing transistor;

[0024] The gate of the data writing transistor is connected to the gate line, the first terminal of the data writing transistor is connected to the data line, and the second terminal of the data writing transistor is connected to the input node.

[0025] Optionally, the external compensation circuit includes: a compensation transistor;

[0026] The gate of the compensation transistor is connected to the compensation line, the first electrode of the compensation transistor is connected to the sensing line, and the second electrode of the compensation transistor is connected to the output node.

[0027] Optionally, the light-emitting driving circuit includes: a driving transistor;

[0028] When the target power line is the pull-up power line, the gate of the driving transistor is connected to the input node, the first terminal of the driving transistor is connected to the adapter node, the second terminal of the driving transistor is connected to the first terminal of the light-emitting unit, and the second terminal of the light-emitting unit is connected to the pull-down power line.

[0029] When the target power line is the pull-down power line, the gate of the driving transistor is connected to the input node, the first terminal of the driving transistor is connected to the pull-up power line, the second terminal of the driving transistor is connected to the first terminal of the light-emitting unit, and the second terminal of the light-emitting unit is connected to the adapter node.

[0030] The light-emitting control circuit is connected to the transfer node.

[0031] Optionally, any one of the following transistors—the data writing transistor in the data writing circuit, the compensation transistor in the external compensation circuit, and the driving transistor in the light-emitting driving circuit—is an N-type transistor or a P-type transistor.

[0032] Optionally, each of the display pixels further includes: a storage capacitor;

[0033] When the driving transistor is a P-type transistor, the target power line is the pull-down power line, and the storage capacitor is connected in series between the input node and the pull-up power line;

[0034] When the driving transistor is an N-type transistor, the target power line is the pull-up power line, and the storage capacitor is connected in series between the input node and the output node.

[0035] Optionally, the display panel further includes:

[0036] Multiple dummy pixels are located in the display area and between the multiple rows of display pixels and the multiple sets of light-emitting control circuits.

[0037] Optionally, the material of the N-type transistor in the display panel includes: oxide material; the material of the P-type transistor in the display panel includes: low-temperature polycrystalline silicon material.

[0038] On the other hand, a method for driving a display panel is provided, for driving a display panel as described in the above aspect; the method includes:

[0039] During the writing phase, the potential of the light emission control signal provided by the light emission control line is the first potential. The light emission control circuit responds to the light emission control signal at the first potential and controls the target power line to disconnect from the display pixel.

[0040] During the light-emitting stage, the potential of the light-emitting control signal provided by the light-emitting control line is the second potential. The light-emitting control circuit responds to the light-emitting control signal at the second potential and controls the target power line to conduct with the display pixel.

[0041] Wherein, the target power line is either a pull-up power line connected to the light-emitting driving circuit in the display pixel, or a pull-down power line connected to the light-emitting unit in the display pixel.

[0042] In another aspect, a display device is provided, the display device comprising: a light-emitting control driving circuit, and a display panel as described in the preceding aspect;

[0043] The light-emitting control driving circuit is connected to multiple light-emitting control lines that are connected to multiple light-emitting control circuits in the display panel, and is used to transmit light-emitting control signals to the multiple light-emitting control lines.

[0044] Optionally, the light emission control driving circuit is located in the peripheral area of ​​the substrate in the display panel, and the light emission control driving circuit includes a plurality of cascaded light emission control driving units, which are connected one-to-one with the plurality of light emission control lines and are used to transmit light emission control signals to the plurality of light emission control lines in sequence.

[0045] Optionally, the light emission control driving circuit is independent of the display panel, and the light emission control driving circuit is used to transmit light emission control signals to the multiple light emission control lines simultaneously. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of this disclosure;

[0048] Figure 2 is a schematic diagram of a display pixel and light emission control circuit provided in an embodiment of this disclosure;

[0049] Figure 3 is a schematic diagram of another display pixel and light emission control circuit provided in an embodiment of this disclosure;

[0050] Figure 4 is a schematic diagram of another display panel provided in an embodiment of this disclosure;

[0051] Figure 5 is a schematic diagram of the circuit structure in a display panel provided in an embodiment of this disclosure;

[0052] Figure 6 is a schematic diagram of the circuit structure in another display panel provided in an embodiment of this disclosure;

[0053] Figure 7 is a schematic diagram of the circuit structure in another display panel provided in an embodiment of this disclosure;

[0054] Figure 8 is a schematic diagram of the circuit structure in another display panel provided in an embodiment of the present disclosure;

[0055] Figure 9 is a schematic structural layout of a display panel provided in an embodiment of this disclosure;

[0056] Figure 10 is a schematic structural layout of another display panel provided in an embodiment of this disclosure;

[0057] Figure 11 is a schematic diagram of the characteristic curves of a light-emitting control circuit provided in an embodiment of this disclosure;

[0058] Figure 12 is a schematic flowchart of a display panel driving method provided in an embodiment of this disclosure;

[0059] Figure 13 is a schematic diagram of signal timing in a display panel provided in an embodiment of this disclosure;

[0060] Figure 14 is a schematic diagram of signal timing in another display panel provided in an embodiment of this disclosure;

[0061] Figure 15 is a schematic diagram of signal timing in another display panel provided in an embodiment of the present disclosure;

[0062] Figure 16 is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure;

[0063] Figure 17 is a schematic diagram of another display device provided in an embodiment of this disclosure. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0065] It should be noted that the transistors used in all embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, their sources and drains are interchangeable. The source is referred to as the first electrode, and the drain as the second electrode, or vice versa. As shown in the accompanying drawings, the middle terminal of the transistor is the gate, the signal input terminal is the source, and the signal output terminal is the drain. Furthermore, the transistors used in the embodiments of this disclosure can include any one or a combination of P-type and N-type transistors. Specifically, a P-type transistor conducts when the gate voltage is low and is cut off when the gate voltage is high, while an N-type transistor conducts when the gate voltage is high and is cut off when the gate voltage is low. Additionally, the multiple signals in each embodiment correspond to a first potential and a second potential. The first potential and the second potential only represent two different states of the signal's potential and do not represent specific numerical values ​​for either the first potential or the second potential.

[0066] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure. As shown in Figure 1, the display panel includes: a substrate 01, the substrate 01 having a display area AA and a peripheral area BB that at least partially surrounds the display area AA.

[0067] For example, the display area AA shown in Figure 1 is rectangular, and the peripheral area BB is located on the left and right sides of the display area AA, partially surrounding the display area AA. Of course, in some other embodiments, the display area AA may also be other shapes, such as circular; and the peripheral area BB may be located on each side of the display area AA, that is, surrounding the display area AA.

[0068] It is understandable that the display area AA can display the image, while the surrounding area BB cannot; the surrounding area BB can also be called the non-display area. Furthermore, the area of ​​the display area AA is generally much larger than the area of ​​the non-display area BB; the attached diagram is for illustrative purposes only.

[0069] Referring again to Figure 1, the display panel also includes a plurality of display pixels 02 arranged in an array, which are located in the display area AA. The array arrangement can refer to a row and column arrangement, meaning the display panel includes multiple rows and columns of display pixels 02.

[0070] Based on Figure 1, and referring to Figure 2, it can be seen that each display pixel 02 includes: a data writing circuit 021, a light-emitting driving circuit 022, an external compensation circuit 023, and a light-emitting unit 024. The data writing circuit 021, the light-emitting driving circuit 022, and the external compensation circuit 023 can be collectively referred to as the pixel circuit.

[0071] Among them, the data writing circuit 021 is connected to the gate line Gate_A, the data line Data and the input node N1 respectively; the external compensation circuit 023 is connected to the compensation line Gate_B, the sensing line SENS and the output node N2 respectively; the light-emitting driving circuit 022 is connected to the input node N1, the output node N2 and the pull-up power line VDD respectively; and the light-emitting unit 024 is connected to the output node N2 and the pull-down power line VSS respectively.

[0072] Optionally, the light-emitting unit 024 can be an organic light-emitting diode (OLED). Also, referring to Figure 2, the first electrode (e.g., anode) of the light-emitting unit 024 can be connected to the output node N2, and the second electrode (e.g., cathode) of the light-emitting unit 024 can be connected to the pull-down power line VSS.

[0073] The data writing circuit 021 can control the connection and disconnection of the data line Data and the input node N1 in response to the gate drive signal provided by the gate line Gate_A. For example, the data writing circuit 021 can disconnect the data line Data from the input node N1 when the potential of the gate drive signal is a first potential; and can connect the data line Data to the input node N1 when the potential of the gate drive signal is a second potential, so that the data signal provided by the data line Data can be transmitted to the input node N1.

[0074] The light-emitting driving circuit 022 can transmit a light-emitting driving signal (e.g., pixel current) to the output node N2 based on the potential of the input node N1 and the pull-up power signal provided by the pull-up power line VDD, so that the light-emitting unit 024 can emit light based on the light-emitting driving signal and the pull-down power signal provided by the pull-down power line VSS.

[0075] The external compensation circuit 023 can control the connection and disconnection of the sensing line SENS and the output node N2 in response to the compensation signal provided by the compensation line Gate_B. Furthermore, referring to FIG2, it can be seen that the sensing line SENS can be connected to the external compensation device 10. For example, the external compensation circuit 023 can disconnect the sensing line SENS from the output node N2 when the compensation signal potential is a first potential; and can connect the sensing line SENS to the output node N2 when the compensation signal potential is a second potential, so that the sensing line SENS transmits the reference signal provided by the external compensation device 10 to the output node N2 to reset the output node N2, or causes the sensing line SENS to acquire the potential of the output node N2 and transmit it to the external compensation device 10, so that the external compensation device 10 extracts the threshold voltage Vth of the driving transistor in the light-emitting driving circuit 022 and the pixel current transmitted from the light-emitting driving circuit 022 to the light-emitting unit 024, and performs external compensation on the data signal provided by the data line Data based on the extracted sensing signals to ensure that the light-emitting unit 024 can reliably emit light.

[0076] Referring again to Figure 1, the display panel further includes: multiple sets of light-emitting control circuits 03Z, located in the peripheral area BB. Each set of light-emitting control circuits 03Z corresponds to at least one row of display pixels 02 among multiple rows of display pixels 02, and each set of light-emitting control circuits 03Z corresponds to different rows of display pixels 02. Each set of light-emitting control circuits 03Z includes a light-emitting control circuit 03 located on at least one side of the corresponding at least one row of display pixels 02 in the row direction X. Each light-emitting control circuit 03 is connected between the target power line and at least one row of display pixels 02, and is also connected to a light-emitting control line EM, and is used to control the on / off state of the target power line and at least one row of display pixels 02 in response to a light-emitting control signal provided by the light-emitting control line EM.

[0077] For example, each light-emitting control circuit 03 can disconnect the target power line from at least one row of display pixels 02 when the potential of the light-emitting control signal provided by the light-emitting control line EM is at a first potential; and can connect the target power line to at least one row of display pixels 02 when the potential of the light-emitting control signal is at a second potential, so that the power signal provided by the target power line can be transmitted to the display pixels 02 to drive the display pixels 02 to reliably emit light. The target power line is either a pull-down power line VSS or a pull-up power line VDD. Figure 1 shows a pull-up power line VDD.

[0078] That is, referring to Figure 2, in one implementation, the target power line is the pull-up power line VDD. The light-emitting drive circuit 022 in display pixel 02 can be indirectly connected to the pull-up power line VDD through the light-emitting control circuit 03, and the connection point is also called the transition node N3. The light-emitting control circuit 03 can control the connection and disconnection of the pull-up power line VDD and the light-emitting drive circuit 022 under the control of the light-emitting control signal provided by the light-emitting control line EM. As described above, when the light-emitting control circuit 03 controls the pull-up power line VDD to be on and the light-emitting drive circuit 022 is conducting, the light-emitting drive circuit 022 can transmit a light-emitting drive signal to the first pole of the light-emitting unit 024 based on the potential of the input node N1 and the pull-up power signal provided by the pull-up power line VDD, thereby driving the light-emitting unit 024 to emit light.

[0079] Alternatively, referring to Figure 3, in another implementation, the target power line can be a pull-down power line VSS. That is, the second electrode of the light-emitting unit 024 in display pixel 02 can be indirectly connected to the pull-down power line VSS through the light-emitting control circuit 03, and the connection point is also called the transition node N3. The light-emitting control circuit 03 can control the connection and disconnection between the pull-down power line VSS and the second electrode of the light-emitting unit 024 under the control of the light-emitting control signal provided by the light-emitting control line EM. As described above, when the light-emitting control circuit 03 controls the pull-down power line VSS to be connected to the second electrode of the light-emitting unit 024, the light-emitting unit 024 can emit light based on the light-emitting driving signal transmitted by the light-emitting driving circuit 022 and the pull-down power signal provided by the pull-down power line VSS.

[0080] Therefore, by flexibly setting the light emission control signal, the light emission control circuit 03 can flexibly control the duration of the power signal transmitted from the pull-up power line VDD or the pull-down power line VSS to the display pixel 02, thereby achieving the purpose of flexibly controlling the light emission duration (duty) of the light emission unit 024. On this basis, display abnormalities such as ghosting can be effectively improved, ensuring a better display effect of the display panel.

[0081] Furthermore, in this embodiment, for the display pixel 02 with external compensation function, the light-emitting control circuit 03 is located in the peripheral area BB rather than the display area AA. That is, the light-emitting control circuit 03 is an external / attached circuit relative to the pixel circuit included in the display pixel 02. Therefore, compared to implementations where the display pixel 02 also includes a light-emitting control circuit located in the display area AA, the solution provided in this embodiment does not increase the size (i.e., pixel pitch) of the display pixel 02, and thus does not cause a decrease in the PPI of the display area AA. In other words, it also facilitates the design of a high PPI display panel. PPI (pixels per inch) refers to the number of pixels that can be set in one inch of a display panel, used to characterize resolution.

[0082] Optionally, the first potential may refer to an invalid potential, and the second potential may refer to an effective potential. For the N-type transistors included in each circuit, the invalid potential may be a low potential relative to the effective potential; for the P-type transistors included in each circuit, the invalid potential may be a high potential relative to the effective potential.

[0083] In summary, this disclosure provides a display panel. The display panel includes: a substrate having a display area and a peripheral area, a plurality of display pixels located in the display area, and a light-emitting control circuit located in the peripheral area. The display pixels are capable of emitting light under the drive of signals provided by various signal lines, each signal line including a pull-up power line and a pull-down power line. The light-emitting control circuit is capable of controlling the on / off state of the pull-up power line or pull-down power line with the display pixel in response to the light-emitting control signal provided by the light-emitting control line. Thus, by flexibly setting the light-emitting control signal, the light-emitting control circuit can flexibly control the duration of conduction of the pull-up power line or pull-down power line with the display pixel, thereby flexibly controlling the light-emitting duration of the display pixel. Therefore, this display panel exhibits good driving flexibility for the display pixels.

[0084] Optionally, Figure 4 is a schematic diagram of another display panel structure provided in an embodiment of this disclosure. As shown in Figure 4, each group of light-emitting control circuits 03Z can correspond to each pair of adjacent rows of display pixels 02.

[0085] Referring to Figure 4, from top to bottom, adjacent first row display pixels 02 and second row display pixels 02 can be connected to each of the same group of light-emitting control circuits 03Z. Similarly, adjacent third row display pixels 02 and fourth row display pixels 02 can be connected to each of the same group of light-emitting control circuits 03Z. And so on. This not only simplifies wiring but also requires only a smaller number of light-emitting control circuits 03, thus facilitating narrow bezel designs for the display panel.

[0086] Optionally, referring to Figures 1 and 4, it can also be seen that in this embodiment of the present disclosure, each group of light-emitting control circuits 03Z may include: one light-emitting control circuit 03 located on each side of at least one row of display pixels 02 in the row direction X. That is, each group of light-emitting control circuits 03Z may include: one light-emitting control circuit 03 located on the left side of the display area AA as shown in the figure, and another light-emitting control circuit 03 located on the right side of the display area AA as shown in the figure, for a total of two light-emitting control circuits 03.

[0087] Furthermore, one light-emitting control circuit 03 located on one of the two sides can be connected to a portion of the display pixels 02 in at least one row of display pixels 02, and the other light-emitting control circuit 03 located on the other side of the two sides can be connected to another portion of the display pixels 02 in at least one row of display pixels 02, excluding a portion of the display pixels 02.

[0088] Thus, in the horizontal direction X, for display pixels 02 near the left and right sides of display area AA, the light-emitting control circuit 03 can timely control the connection and disconnection of the target power lines, such as the pull-up power line VDD or pull-down power line VSS, with the display pixels 02. Furthermore, since the longer the trace connecting the light-emitting control circuit 03 to the display pixels 02, the greater its impedance, the more reliable the power signal transmitted from the target power line to the display pixels 02 becomes. Therefore, by setting one light-emitting control circuit 03 on each of the left and right sides in the horizontal direction X, the length of the trace connected to each light-emitting control circuit 03 can be reduced, thereby reducing the impedance on the trace and ensuring reliable transmission of the power signal provided by the target power line to the display pixels 02. In some embodiments, for scenarios with high impedance, increasing the trace width is also considered to reduce impedance. However, the solution of this embodiment does not require increasing the trace width, which is beneficial for high PPI design of the display panel.

[0089] Optionally, referring to Figures 2 and 5, a schematic diagram of the circuit structure in one display panel is shown. Figure 6 shows a schematic diagram of the circuit structure in another display panel. Referring to Figure 3, Figure 7 shows a schematic diagram of the circuit structure in yet another display panel. Figure 8 shows a schematic diagram of the circuit structure in yet yet another display panel. Referring to Figures 5 to 8, it can be seen that the light-emitting control circuit 03 may include: a light-emitting control transistor M0.

[0090] The gate of the light-emitting control transistor M0 can be connected to the light-emitting control line EM, the first terminal of the light-emitting control transistor M0 can be connected to the target power line, and the second terminal of the light-emitting control transistor M0 can be connected to at least one row of display pixels 02, i.e., connected to the transition node N3. For example, the target power line shown in Figures 5 and 6 is the pull-up power line VDD; the target power line shown in Figures 7 and 8 is the pull-down power line VSS.

[0091] Optionally, as shown in FIG5, the light-emitting control transistor M0 can be an N-type transistor. Of course, in other embodiments, as shown in FIG6 to FIG8, the light-emitting control transistor M0 can be a P-type transistor.

[0092] Optionally, in this embodiment of the disclosure, the light-emitting control transistor M0 can also be a dual-gate transistor. That is, the light-emitting control transistor M0 can have two gates.

[0093] Since P-type transistors generally have a large leakage current, setting the light-emitting control transistor M0 to an N-type transistor can reduce the leakage current of M0, ensuring reliable power signal transmission to display pixel O2. Furthermore, setting the light-emitting control transistor M0 to a dual-gate transistor can stabilize the threshold voltage Vth of M0, further ensuring reliable power signal transmission to display pixel O2.

[0094] Optionally, referring further to Figures 5 through 8, the data writing circuit 021 may include a data writing transistor M1. The external compensation circuit 023 may include a compensation transistor M2. The light-emitting driving circuit 022 may include a driving transistor M3.

[0095] The gate of the data writing transistor M1 can be connected to the gate line Gate_A, the first terminal of the data writing transistor M1 can be connected to the data line Data, and the second terminal of the data writing transistor M1 can be connected to the input node N1.

[0096] The gate of the compensation transistor M2 can be connected to the compensation line Gate_B, the first terminal of the compensation transistor M2 can be connected to the sensing line SENS, and the second terminal of the compensation transistor M2 can be connected to the output node N2.

[0097] When the target power line is the pull-up power line VDD, as shown in Figures 5 and 6, the gate of the driving transistor M3 can be connected to the input node N1, the first terminal of the driving transistor M3 can be connected to the transition node N3, the second terminal of the driving transistor M3 can be connected to the first terminal of the light-emitting unit 024, and the second terminal of the light-emitting unit 024 can be connected to the pull-down power line VSS.

[0098] When the target power line is the pull-down power line VSS, as shown in Figures 7 and 8, the gate of the driving transistor M3 can be connected to the input node N1, the first terminal of the driving transistor M3 can be connected to the pull-up power line VDD, the second terminal of the driving transistor M3 can be connected to the first terminal of the light-emitting unit 024, and the second terminal of the light-emitting unit 024 can be connected to the transition node N3.

[0099] The light-emitting control circuit 03 can be connected to the transition node N3. That is, as described above, the second terminal of the light-emitting control transistor M0 can be connected to the display pixel 02 by connecting to the transition node N3.

[0100] Optionally, any one of the following transistors can be an N-type transistor or a P-type transistor: the data writing transistor M1 included in the data writing circuit 021, the compensation transistor M2 included in the external compensation circuit 023, and the driving transistor M3 included in the light-emitting driving circuit 022.

[0101] For example, referring to Figure 5, the circuit structure shown therein has N-type transistors for data writing transistor M1, compensation transistor M2, and driving transistor M3. Referring to Figure 6, the circuit structure shown therein has P-type transistor for data writing transistor M1, and N-type transistors for compensation transistor M2 and driving transistor M3. Referring to Figure 7, the circuit structure shown therein has P-type transistors for data writing transistor M1 and driving transistor M3, and N-type transistor for compensation transistor M2. Referring to Figure 8, the circuit structure shown therein has P-type transistors for data writing transistor M1, compensation transistor M2, and driving transistor M3.

[0102] Optionally, in this embodiment of the disclosure, the material of the P-type transistors in the display panel may include low-temperature polysilicon (LTPS) material. The material of the N-type transistors in the display panel may include oxide material. Based on this, the circuit structure shown in FIG5 can be referred to as a pixel circuit with an all-N-type oxide architecture. The circuit structures shown in FIG6 and FIG7 can be referred to as a pixel circuit with a low-temperature polysilicon oxide (LTPO) architecture that includes both P-type and N-type transistors. The circuit structure shown in FIG8 can be referred to as a pixel circuit with an all-P-type LTPS architecture.

[0103] Among them, the LTPO architecture shown in Figures 6 and 7 takes advantage of the low leakage current of the oxide N-type transistor and the high mobility of the LTPS P-type transistor, resulting in good operational reliability.

[0104] Optionally, each transistor described in the embodiments of this disclosure may be a metal oxide semiconductor (MOS) field-effect transistor.

[0105] Optionally, referring to Figures 5 and 8, it can also be seen that each display pixel 02 may further include a storage capacitor Cst. The storage capacitor Cst can be used to store signals.

[0106] When the driving transistor M3 is a P-type transistor, as shown in Figures 7 and 8, the target power line can be a pull-down power line VSS. That is, the first terminal of the light-emitting control transistor M0 can be connected to the pull-down power line VSS, and the second terminal of the light-emitting control transistor M0 can be connected to the second terminal of the light-emitting unit 024 to the transition node N3. Furthermore, the storage capacitor Cst can be connected in series between the input node N1 and the pull-up power line VDD.

[0107] When the driving transistor M3 is an N-type transistor, as shown in Figures 5 and 6, the target power supply line can be the pull-up power supply line VDD. That is, the first terminal of the light-emitting control transistor M0 can be connected to the pull-up power supply line VDD, and the second terminal of the light-emitting control transistor M0 can be connected to the first terminal of the driving transistor M3 to the transition node N3. Furthermore, the storage capacitor Cst can be connected in series between the input node N1 and the output node N2.

[0108] In the embodiment where the driving transistor M3 is a P-type transistor, by setting the target power line as a pull-down power line VSS, that is, by setting the light-emitting control transistor M0 to indirectly connect the pull-down power line VSS to the second terminal of the light-emitting unit 024, the light-emitting duration can be flexibly controlled, and the current difference caused by voltage drop (IR drop) at the source of the driving transistor M3 can be reduced, ensuring that the driving transistor M3 can reliably transmit the light-emitting driving signal to the light-emitting unit 024 so as to drive the light-emitting unit 024 to emit light reliably.

[0109] It is understood that in the circuit structures shown in Figures 5 to 8, the pixel circuits included in display pixel 02 can all be considered as a 3T1C structure circuit including 3 transistors and 1 storage capacitor. Of course, in some other embodiments, it can also be a 2T1C structure circuit.

[0110] Optionally, referring to Figures 5 to 8, it can also be seen that the external compensation device 10 described above may further include: switch K1 and switch K2.

[0111] The switch K1 can be connected between the reference signal terminal V_REF and the sensing line SENS, and can also be connected to the switch control terminal S_REF. It can be used to control the on / off state of the reference signal terminal V_REF and the sensing line SENS in response to the switch control signal provided by the switch control terminal S_REF.

[0112] For example, switch K1 can control the reference signal terminal V_REF and the sensing line SENS to conduct when the potential of the switch control signal provided by the switch control terminal S_REF is an effective potential, so that the reference signal terminal V_REF transmits the reference signal described above to the output node N2 through the sensing line SENS; and can control the reference signal terminal V_REF and the sensing line SENS to disconnect when the potential of the switch control signal provided by the switch control terminal S_REF is an invalid potential.

[0113] Switch K2 can be connected between the test terminal VSENS and the sensing line SENS, and can also be connected to the switch control terminal S_SAMP. It can be used to control the on / off state of the test terminal VSENS and the sensing line SENS in response to the switch control signal provided by the switch control terminal S_SAMP.

[0114] For example, switch K2 can control the test terminal VSENS and the sensing line SENS to conduct when the potential of the switch control signal provided by the switch control terminal S_SAMP is an effective potential, so that the test terminal VSENS can collect the sensing signal described above through the sensing line SENS; and it can control the test terminal VSENS and the sensing line SENS to disconnect when the potential of the switch control signal provided by the switch control terminal S_SAMP is an invalid potential.

[0115] Optionally, as shown in Figures 5 to 8, switches K1 and K2 can both be single-pole single-throw switches. For either switch, it can be closed when the potential of the switch control signal it receives is an effective potential; and it can be opened when the potential of the switch control signal it receives is an ineffective potential. Of course, in some other embodiments, switches K1 and / or K2 can also be transistors as described above.

[0116] Optionally, in conjunction with the structure shown in Figure 4, Figure 9 illustrates a structural layout of a display panel. Referring to Figure 9, it can be seen that each light-emitting control circuit 03 (i.e., the light-emitting control transistor M0 externally attached to the peripheral region BB) may include: an active (ACT) layer ACT1, a gate metal layer GATE1, and a source & drain (SD) metal layer SD1, which are located on one side of the substrate 01 and stacked sequentially.

[0117] Each light-emitting control circuit 03 can be connected to at least one row of display pixels 02 via the source / drain metal layer SD1 and the transition via K0. Furthermore, each light-emitting control circuit 03 can be connected to two display pixels 02 located in the same column of two adjacent rows of display pixels 02 via the same transition via K0. This ensures reliable connection between the light-emitting control circuit 03 and the display pixels 02, while also simplifying the manufacturing process and reducing costs.

[0118] For example, in an implementation where the target power line is a pull-up power line VDD, i.e., the first terminal of the light-emitting control transistor M0 is connected to the driving transistor M3 in display pixel 02, as shown in FIG9, the source-drain metal layer SD1 of the light-emitting control transistor M0 can be connected to the active layer ACT1 of the driving transistor M3. That is, the active layer ACT1 of the driving transistor M3 in two adjacent up and down rows of display pixels can be connected to the source-drain metal layer SD1 of the light-emitting control transistor M0 through the same connecting via K0.

[0119] For example, in an embodiment where the target power line is a pull-down power line VSS, i.e., the light-emitting control transistor M0 is connected to the second electrode of the light-emitting unit 024 in the display pixel 02, assuming the second electrode of the light-emitting unit 024 is the cathode, it can be considered that the source / drain metal layer SD1 of the light-emitting control transistor M0 is connected to the cathode of the light-emitting unit 024. That is, the cathodes of the light-emitting units 024 in adjacent upper and lower rows of display pixels can be connected to the source / drain metal layer SD1 of the light-emitting control transistor M0 through the same connecting via K0.

[0120] Furthermore, referring to Figure 9, it can be seen that the light-emitting control transistor M0 shown therein has two gates, making it a dual-gate transistor.

[0121] Optionally, referring to Figure 9, it can also be seen that the display panel may further include a plurality of dummy pixels 04, which may be located in the display area AA and between the multiple rows of display pixels 02 and the multiple sets of light-emitting control circuits 03Z (i.e., external light-emitting control transistors M0). This ensures better etching uniformity during the fabrication of the display panel. Optionally, based on the layout shown in Figure 9, Figure 10 also schematically shows a structural layout including multiple rows of display pixels 02.

[0122] Understandably, since the pull-up power line VDD or pull-down power line VSS is connected to multiple display pixels 02 via a light-emitting transistor M0 to transmit power signals to the multiple display pixels 02, it is known that the on-state current of the light-emitting transistor M0 needs to be relatively large. Therefore, it is understood that the width and film thickness of the metal trace at the transition node N3 (i.e., the trace formed by the source and drain metal layers SD1 of the light-emitting transistor M0) need to meet the maximum current density required for high current handling to reduce the heat generation problem of the trace.

[0123] Thus, in this embodiment of the present disclosure, the thickness and width of the source and drain metal layers SD1 of the light-emitting control transistor M0 can satisfy: I_t / (t*b)≤a.

[0124] Where I_t can refer to the total pixel current of the multiple display pixels 02 connected to each light-emitting control circuit 03. t can refer to the thickness of the source / drain metal layer SD1. b can refer to the width of the source / drain metal layer SD1. a can refer to the maximum withstand current density of the portion of the source / drain metal layer SD1 located at the transition via K0 (i.e., transition node N3).

[0125] Assume that the unit of I_t is microampere (μA) and the unit of a is milliampere per square micrometer (mA / μm). 2Since the units of b and t are both μm, after converting the units, it can be deduced that the trace width b formed by the source and drain metal layers SD1 can satisfy: b≥I_t / 1000 / (t*a).

[0126] Furthermore, it is understood that the on-state current of the light-emitting control transistor M0 should also be greater than or equal to I_t, that is, the sum of the maximum currents of all display pixels under control. In some embodiments, the on-state current of the light-emitting control transistor M0 can be increased by increasing the width-to-length ratio W / L of the light-emitting control transistor M0 or the source-drain current Vds of the light-emitting control transistor M0.

[0127] For example, assuming the pixel current of each display pixel is Id (μA), each light-emitting control transistor M0 is connected to n rows of display pixels 02 to control the target power line to transmit power signals to the n rows of display pixels 02. Each row of display pixels 02 includes m display pixels. Then I_t can satisfy: I_t=Id*n*m.

[0128] Where n is an integer greater than or equal to 1 and less than the number of rows of display pixel 02, and m is an integer greater than 1 and less than the number of columns of display pixel 02.

[0129] Taking an OLED display product as an example, assuming its horizontal resolution H = 2000, meaning the display panel includes 2000 columns of display pixels 02, Id = 150 nanoamps (nA), and a set of light-emitting control circuits 03Z includes one light-emitting control circuit 03 on each of the left and right sides, with each light-emitting control circuit 03 connected to one row of display pixels 02, i.e., n = 1, n = H / 2 = 500, then we can calculate: I_t = 150μA. That is, the on-state current of the light-emitting control transistor M0 in each light-emitting control circuit 03 must be at least 150μA.

[0130] Optionally, Figure 11 schematically shows the characteristic curves of the light-emitting control transistor M0 under different on-state currents (e.g., 1, 2.1, 4.1, etc.). The horizontal axis represents current, and the vertical axis represents voltage.

[0131] It is understood that the light-emitting control transistor M0 described in this disclosure is applicable not only to OLED display products where the light-emitting unit 024 is an OLED, but also to MLED display products where the light-emitting unit 024 is a miniature light-emitting diode (MLED). Since the pixel current required by MLED is in the μA range compared to OLED, which is approximately 100 times larger, it can be known that the aspect ratio W / L of the light-emitting control transistor M0 in an MLED display product can be much larger than that in an OLED display product, requiring a larger current supply.

[0132] In summary, this disclosure provides a display panel. The display panel includes: a substrate having a display area and a peripheral area, a plurality of display pixels located in the display area, and a light-emitting control circuit located in the peripheral area. The display pixels are capable of emitting light under the drive of signals provided by various signal lines, each signal line including a pull-up power line and a pull-down power line. The light-emitting control circuit is capable of controlling the on / off state of the pull-up power line or pull-down power line with the display pixel in response to the light-emitting control signal provided by the light-emitting control line. Thus, by flexibly setting the light-emitting control signal, the light-emitting control circuit can flexibly control the duration of conduction of the pull-up power line or pull-down power line with the display pixel, thereby flexibly controlling the light-emitting duration of the display pixel. Therefore, this display panel exhibits good driving flexibility for the display pixels.

[0133] Figure 12 is a flowchart of a driving method for a display panel according to an embodiment of this disclosure. This method is used to drive a display panel as described above. As shown in Figure 12, the method includes:

[0134] Step 1201, Writing Stage: The potential of the light emission control signal provided by the light emission control line is the first potential. The light emission control circuit responds to the light emission control signal at the first potential and controls the target power line to disconnect from the display pixel.

[0135] Step 1202, the light emission stage: the potential of the light emission control signal provided by the light emission control line is the second potential. The light emission control circuit responds to the light emission control signal at the second potential and controls the target power line to conduct with the display pixel.

[0136] The target power line is either a pull-up power line connected to the light-emitting driving circuit in the display pixel, or a pull-down power line connected to the light-emitting unit in the display pixel.

[0137] Optionally, for multiple light-emitting control lines connected to multiple light-emitting control circuits, in one implementation, the required light-emitting control signal can be provided to each of the multiple light-emitting control lines individually; alternatively, in another implementation, the required light-emitting control signal can be provided to all the multiple light-emitting control lines uniformly. In both implementations, with the structure shown in Figure 5, Figures 13 and 14 respectively illustrate a signal sequence diagram in a display panel. Referring to the timing diagram, it can be seen that within one frame period, a display phase T1 and a sensing phase T2 can be executed sequentially. The display phase T1 can include a writing phase T11 and a light-emitting phase T12 executed sequentially, and the sensing phase T2 can include a reset phase T21, a compensation phase T22, and an extraction phase T23 executed sequentially.

[0138] In the writing phase T11, Gate_A provides a high-potential gate drive signal, Gate_B provides a high-potential compensation signal, and EM provides a low-potential light-emitting control signal. In the structure shown in Figure 5, the high potential is the effective potential, and the low potential is the ineffective potential. Correspondingly, both the data writing transistor M1 and the compensation transistor M2 can be turned on, while the light-emitting control transistor M0 can be turned off. Furthermore, the data line Data can transmit a data signal to the input node N1 via the turned-on data writing transistor M1 to charge the input node N1; and the sensing line SENS can transmit a reference signal to the output node N2 via the turned-on compensation transistor M2 to reset the output node N2. The storage capacitor Cst stores the data signal transmitted to the input node N1.

[0139] During the light-emitting stage T12, the gate line Gate_A can provide a low-potential gate drive signal, the compensation line Gate_B can provide a low-potential compensation signal, and the light-emitting control line EM can provide a high-potential light-emitting control signal. Correspondingly, the data writing transistor M1 and the compensation transistor M2 can both be turned off, while the light-emitting control transistor M0 can be turned on. Furthermore, the pull-up power line VDD can transmit a pull-up power signal to the transfer node N3 via the turned-on light-emitting control transistor M0, enabling the light-emitting drive transistor M3 to transmit a light-emitting drive signal to the anode of the light-emitting unit 024 based on this pull-up power signal and the data signal from the input node N1. This allows the light-emitting unit 024 to emit light based on the light-emitting drive signal and the pull-down power signal provided by the cathode-connected pull-down power line VSS. The light-emitting duration is positively correlated with the duration of the high-potential light-emitting control signal. That is, the longer the duration of the high-potential light-emitting control signal, the longer the light-emitting duration of the light-emitting unit 024. This allows for flexible control of the light-emitting duration of the display pixel 02.

[0140] During the reset phase T21 to the extraction phase T23, the gate line Gate_A can provide a high-level gate drive signal, the compensation line Gate_B can provide a high-level compensation signal, and the light emission control line EM can provide a high-level light emission control signal. Correspondingly, the data writing transistor M1, the compensation transistor M2, and the light emission control transistor M0 can all be turned on.

[0141] Furthermore, during the reset phase T21, in the external compensation device 10, the switch control terminal S_REF connected to switch K1 can provide a switch control signal with an effective potential (e.g., low potential), and the switch control terminal S_SAMP connected to switch K2 can provide a switch control signal with an invalid potential (e.g., high potential), causing switch K1 to turn on and switch K2 to turn off. This allows the reference signal terminal V_REF to conduct with the sensing line SENS, and transmits a reference signal to the output node N2 via the sensing line SENS and the turned-on compensation transistor M2, thereby resetting the output node N2, i.e., the anode of the light-emitting unit 024.

[0142] During the compensation phase T22, in the external compensation device 10, the switch control terminal S_REF connected to switch K1 can provide an invalid potential switch control signal, and the switch control terminal S_SAMP connected to switch K2 can also provide an invalid potential switch control signal, so that both switches K1 and K2 are closed.

[0143] In the extraction stage T23, in the external compensation device 10, the switch control terminal S_REF connected to switch K1 can provide an invalid potential switch control signal, and the switch control terminal S_SAMP connected to switch K2 can provide an valid potential switch control signal, causing switch K1 to close and switch K2 to open. This allows the test terminal VSENS and the sensing line SENS to be connected. The sensing line SENS can extract the signal from the output node N2 as a sensing signal and transmit it to the test terminal VSENS, so that the external compensation device 10 can perform external compensation on the data signal based on this sensing signal.

[0144] It is understandable that, referring to Figure 14, the multiple gate lines Gate_A connected to the multi-row display pixels 02 can provide gate drive signals with effective potentials to the multi-row display pixels 02 row by row. In the timing diagram shown in Figure 13, the multiple switch control lines EM can be switch control signals that provide effective potentials to each row, that is, the light-emitting control transistors M0 connected to each row of display pixels 02 can be turned on row by row. In the timing diagram shown in Figure 14, the multiple switch control lines EM can be light-emitting control signals that provide effective potentials to all row display pixels 02 after the multiple gate lines Gate_A provide gate drive signals with effective potentials, so that the data signals provided by the data lines Data are written to all row display pixels 02, and then provide light-emitting control signals with effective potentials uniformly, that is, the light-emitting control transistors M0 connected to each row of display pixels 02 can be turned on simultaneously. In addition, similar to the multiple gate lines Gate_A, as shown in Figure 14, the multiple compensation lines Gate_B connected to the multi-row display pixels 02 can also provide compensation signals with effective potentials to the multi-row display pixels 02 row by row. The figures are illustrated using an example of a display panel including n rows of display pixels 02.

[0145] Optionally, Figure 15 also uses the structure shown in Figure 8 as an example to illustrate a signal sequence diagram in a display panel. Comparing Figures 13 and 14, it can be seen that, unlike the structure shown in Figure 5, since the data writing transistor M1, the compensation transistor M2, and the light-emitting control transistor M0 are all P-type transistors, the effective potentials of the gate drive signal, the compensation signal, and the light-emitting control signal all become low potentials, while the ineffective potentials all become high potentials.

[0146] It is understood that since the driving method has essentially the same technical effect as the aforementioned display panel embodiment, the technical effect of the driving method will not be described again here for the sake of brevity.

[0147] Figure 16 is a schematic diagram of a display device provided in an embodiment of this disclosure. As shown in Figure 16, the display device includes: a light-emitting control driving circuit 20, and a display panel as described above.

[0148] As shown in Figure 1, the light-emitting control driving circuit 20 is connected to multiple light-emitting control lines EM that are connected to multiple light-emitting control circuits 03 in the display panel, and is used to transmit light-emitting control signals to the multiple light-emitting control lines EM.

[0149] Optionally, as an alternative implementation, as shown in Figure 16, the light-emitting control driving circuit 20 and the display panel can be independent of each other. The light-emitting control driving circuit 20 can be used to simultaneously transmit light-emitting control signals to multiple light-emitting control lines EM. That is, it transmits light-emitting control signals that satisfy the timing shown in Figure 14.

[0150] For example, the light emission control driving circuit 20 can be an external integrated circuit (IC).

[0151] It is understood that Figure 16 schematically shows the display area AA and the 3T1C pixel circuit + light-emitting unit located in the display area AA, the peripheral area BB and the light-emitting control circuit located in the peripheral area BB.

[0152] Alternatively, as another optional implementation, as shown in Figure 17, the light-emitting control driving circuit 20 can be located in the peripheral area BB of the substrate 01 in the display panel. For example, the light-emitting control driving circuit 20 can be disposed on the substrate 01 using gate driver on array (GOA) technology. Accordingly, the light-emitting control driving circuit 20 can also be called an EM GOA circuit. Furthermore, the light-emitting control driving circuit 20 can include multiple cascaded light-emitting control driving units EM GOA, which can be connected one-to-one with multiple light-emitting control lines EM and used to sequentially transmit light-emitting control signals to the multiple light-emitting control lines EM. That is, transmitting light-emitting control signals that satisfy the timing shown in Figure 13.

[0153] It is understood that Figure 17 also schematically shows multiple rows of display pixels 02 located in display area AA, each of which can be connected to a row of display pixels 02 via a light-emitting control circuit 03. A power supply 30 is also shown, connected to both the light-emitting control circuit 03 and the display pixels 02, and used to supply power to both. Furthermore, the display device may also include a gate drive circuit, i.e., a Gate GOA circuit, located in peripheral area BB, for transmitting a gate drive signal to gate line Gate_A. The provision of the compensation signal is similar and will not be described further here.

[0154] Optionally, the display device can be any type of display device, such as an OLED display device or an MLED display device. Furthermore, the display device includes any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, and virtual reality (VR). In particular, because VR display devices produce a tail-like effect when moving quickly or rapidly changing perspectives, two images simultaneously displayed to the viewer's brain can cause motion blur, affecting the viewing experience. In this embodiment, by flexibly controlling the emission duration, this motion blur can be effectively mitigated.

[0155] It should be understood that the terminology used in the embodiments of this disclosure is for the purpose of explaining the embodiments of this disclosure and is not intended to limit this disclosure. Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains.

[0156] For example, in embodiments of this disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "connection" can refer to an electrical connection. The term "multiple" refers to two or more unless otherwise expressly defined. Similarly, words such as "a" or "one" do not indicate a quantity limitation, but rather indicate the presence of at least one. Words such as "comprising" or "including" mean that the element or object preceding "comprising" covers the element or object listed after "comprising" or "including" and its equivalents, and do not exclude other elements or objects. Terms such as "upper," "lower," "left," or "right" are used only to indicate relative positional relationships, and the relative positional relationship may also change accordingly when the absolute position of the described object changes.

[0157] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A display panel, the display panel comprising: A substrate having a display area and a peripheral area at least partially surrounding the display area; Multiple display pixels arranged in an array are located in the display area. Each display pixel includes: a data writing circuit, a light-emitting driving circuit, an external compensation circuit, and a light-emitting unit. The data writing circuit is connected to a gate line, a data line, and an input node. The external compensation circuit is connected to a compensation line, a sensing line, and an output node. The light-emitting driving circuit is connected to the input node, the output node, and a pull-up power line. The light-emitting unit is connected to the output node and a pull-down power line. Multiple sets of light-emitting control circuits are located in the peripheral area. Each set of light-emitting control circuits corresponds to at least one row of display pixels in the multiple rows of display pixels, and each set of light-emitting control circuits corresponds to different rows of display pixels. Each set of light-emitting control circuits includes: a light-emitting control circuit located on at least one side of the at least one row of display pixels in the row direction. Each light-emitting control circuit is connected between a target power line and the at least one row of display pixels, and is also connected to a light-emitting control line. It is used to control the on / off state of the target power line and the at least one row of display pixels in response to the light-emitting control signal provided by the light-emitting control line. The target power line is either the pull-down power line or the pull-up power line.

2. The display panel according to claim 1, wherein, Each group of light-emitting control circuits corresponds to each pair of adjacent rows of display pixels.

3. The display panel according to claim 2, wherein, Each of the light-emitting control circuits includes: an active layer, a gate metal layer, and a source / drain metal layer stacked sequentially on one side of the substrate; Each of the light-emitting control circuits is connected to the at least one row of display pixels via the source / drain metal layer through a via; and each of the light-emitting control circuits is connected to two display pixels in the same column of the two adjacent rows of display pixels via the same via.

4. The display panel according to claim 3, wherein, The thickness and width of the source / drain metal layer satisfy: I_t / (t*b)≤a; Where I_t refers to the sum of the pixel currents of the multiple display pixels connected to each of the light-emitting control circuits; t refers to the thickness of the source / drain metal layer; b refers to the width of the source / drain metal layer; a refers to the distance the source / drain metal layer is located in the... The maximum current density withstand capability of the portion of the adapter via is described.

5. The display panel according to any one of claims 1 to 4, wherein, Each group of the light-emitting control circuits includes: one light-emitting control circuit on each side of the at least one row of display pixels in the row direction.

6. The display panel according to claim 5, wherein, One of the two sides is a light-emitting control circuit connected to a portion of the display pixels in the at least one row of display pixels, and the other of the two sides is a light-emitting control circuit connected to another portion of the display pixels in the at least one row of display pixels, excluding the portion of display pixels.

7. The display panel according to any one of claims 1 to 6, wherein, The light-emitting control circuit includes: a light-emitting control transistor; The gate of the light-emitting control transistor is connected to the light-emitting control line, the first electrode of the light-emitting control transistor is connected to the target power line, and the second electrode of the light-emitting control transistor is connected to the at least one row of display pixels.

8. The display panel according to claim 7, wherein, The light-emitting control transistor is an N-type transistor.

9. The display panel according to claim 7 or 8, wherein, The light-emitting control transistor is a dual-gate transistor.

10. The display panel according to any one of claims 1 to 9, wherein, The data writing circuit includes: a data writing transistor; The gate of the data writing transistor is connected to the gate line, the first terminal of the data writing transistor is connected to the data line, and the second terminal of the data writing transistor is connected to the input node.

11. The display panel according to any one of claims 1 to 10, wherein, The external compensation circuit includes: a compensation transistor; The gate of the compensation transistor is connected to the compensation line, and the first electrode of the compensation transistor is connected to the compensation line. The sensing line is connected, and the second electrode of the compensation transistor is connected to the output node.

12. The display panel according to any one of claims 1 to 11, wherein, The light-emitting driving circuit includes: a driving transistor; When the target power line is the pull-up power line, the gate of the driving transistor is connected to the input node, the first terminal of the driving transistor is connected to the adapter node, the second terminal of the driving transistor is connected to the first terminal of the light-emitting unit, and the second terminal of the light-emitting unit is connected to the pull-down power line. When the target power line is the pull-down power line, the gate of the driving transistor is connected to the input node, the first terminal of the driving transistor is connected to the pull-up power line, the second terminal of the driving transistor is connected to the first terminal of the light-emitting unit, and the second terminal of the light-emitting unit is connected to the adapter node. The light-emitting control circuit is connected to the transfer node.

13. The display panel according to any one of claims 10 to 12, wherein, The data writing circuit includes a data writing transistor, the external compensation circuit includes a compensation transistor, and the light-emitting driving circuit includes a driving transistor, any one of which is an N-type transistor or a P-type transistor.

14. The display panel according to claim 13, wherein, Each of the display pixels further includes: a storage capacitor; When the driving transistor is a P-type transistor, the target power line is the pull-down power line, and the storage capacitor is connected in series between the input node and the pull-up power line; When the driving transistor is an N-type transistor, the target power line is the pull-up power line, and the storage capacitor is connected in series between the input node and the output node.

15. The display panel according to any one of claims 1 to 14, wherein, The display panel also includes: Multiple dummy pixels are located in the display area and between the multiple rows of display pixels and the multiple sets of light-emitting control circuits.

16. The display panel according to any one of claims 1 to 15, wherein, The N-type transistors in the display panel are made of oxide materials; the P-type transistors in the display panel are made of low-temperature polycrystalline silicon materials.

17. A method for driving a display panel, used to drive the display panel as described in any one of claims 1 to 16; the method comprising: During the writing phase, the potential of the light emission control signal provided by the light emission control line is the first potential. The light emission control circuit responds to the light emission control signal at the first potential and controls the target power line to disconnect from the display pixel. During the light-emitting stage, the potential of the light-emitting control signal provided by the light-emitting control line is the second potential. The light-emitting control circuit responds to the light-emitting control signal at the second potential and controls the target power line to conduct with the display pixel. Wherein, the target power line is either a pull-up power line connected to the light-emitting driving circuit in the display pixel, or a pull-down power line connected to the light-emitting unit in the display pixel.

18. A display device, the display device comprising: A light-emitting control driving circuit, and a display panel as described in any one of claims 1 to 16; The light-emitting control driving circuit is connected to multiple light-emitting control lines that are connected to multiple light-emitting control circuits in the display panel, and is used to transmit light-emitting control signals to the multiple light-emitting control lines.

19. The display device according to claim 18, wherein, The light emission control driving circuit is located in the peripheral area of ​​the substrate in the display panel, and the light emission control driving circuit includes multiple cascaded light emission control driving units. The multiple light emission control driving units are connected one-to-one with the multiple light emission control lines and are used to transmit light emission control signals to the multiple light emission control lines in sequence.

20. The display device according to claim 18, wherein, The light emission control driving circuit is independent of the display panel, and the light emission control driving circuit is used to transmit light emission control signals to the multiple light emission control lines simultaneously.

Images