Shift register unit, gate drive circuit, and display panel

Abstract

Provided are a shift register unit, a gate drive circuit, and a display panel. The shift register unit comprises: a plurality of output circuits and a plurality of isolation circuits, wherein each output circuit comprises a first node and one or more signal output ends, and the output circuit is used for inputting a shift signal to a signal output end in response to a signal of the first node; and the isolation circuits and the output circuits are arranged corresponding to each other, each isolation circuit is connected to a pull-up node and the first node of the output circuit corresponding to the isolation circuit, and the isolation circuit is used for reducing a leakage current from the first node to the pull-up node.

Description

Shift register unit, gate drive circuit, display panel Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register unit, a gate driving circuit, and a display panel. Background Art

[0002] The shift register unit is used to provide a gate drive signal to the pixel drive circuit. The shift register unit can be integrated into the border area of ​​the display panel. However, in the related art, the structure of the shift register unit is complex, and it is not easy to achieve a narrow border design for the display panel.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] According to one aspect of the present disclosure, a shift register unit is provided, comprising:

[0006] a plurality of output circuits, each comprising a first node and one or more signal output terminals, wherein the output circuit is configured to input a shift signal to the signal output terminal in response to a signal at the first node;

[0007] Multiple isolation circuits are provided corresponding to the output circuits, the isolation circuits connect the pull-up node and the first node of the output circuit corresponding thereto, and the isolation circuits are used to reduce leakage current from the first node to the pull-up node.

[0008] In an exemplary embodiment of the present disclosure, the output circuit includes a plurality of signal output terminals, and the output circuit is used to sequentially input shift signals to the plurality of signal output terminals in response to a signal of a first node, and the shift signals on the plurality of signal output terminals in the plurality of output circuits are not output simultaneously.

[0009] In an exemplary embodiment of the present disclosure, the output circuit further includes:

[0010] One or more first capacitors, each of the first capacitors and the signal output terminal is provided correspondingly, and each of the first capacitors is connected between the corresponding signal output terminal and the first node.

[0011] In an exemplary embodiment of the present disclosure, the output circuit is further connected to one or more first clock signal terminals, the first clock signal terminals are used to provide the shift signal, the first clock signal terminals and the signal output terminals are correspondingly arranged, and the output circuit is used to respond to the signal of the first node to transmit the signal of the first clock signal terminal to the signal output terminal corresponding to the first clock signal terminal;

[0012] Wherein, all the first clock signal terminals in the plurality of output circuits are respectively used to output different clock signals.

[0013] In an exemplary embodiment of the present disclosure, the output circuit includes:

[0014] One or more first transistors, the first transistors and the signal output terminal are arranged correspondingly, the first electrode of the first transistor is connected to the corresponding signal output terminal, the second electrode is connected to the corresponding first clock signal terminal, and the gate is connected to the first node, wherein the first transistor corresponding to the same signal output terminal and the first clock signal terminal are arranged correspondingly.

[0015] In an exemplary embodiment of the present disclosure, the output circuit is further connected to a second clock signal terminal and one or more first clock signal terminals, the first clock signal terminals are used to provide the shift signal, the first clock signal terminals and the signal output terminals are correspondingly arranged, and the output circuit is used to respond to a signal of a first node and a second clock signal terminal connected thereto to transmit the signal of the first clock signal terminal to the signal output terminal corresponding to the first clock signal terminal;

[0016] Wherein, different output circuits are connected to the same group of first clock signal terminals, and the second clock signal terminals connected to different output circuits are at least used to output valid levels respectively in different time periods.

[0017] In an exemplary embodiment of the present disclosure, the output circuit includes:

[0018] One or more first transistors, each of the first transistors and the signal output terminal being provided correspondingly, a first electrode of the first transistor being connected to the corresponding signal output terminal, and a gate electrode being connected to the first node;

[0019] One or more second transistors, the second transistors are arranged corresponding to the signal output terminal, the first electrode of the second transistor is connected to the second electrode of the corresponding first transistor, the second electrode is connected to the corresponding first clock signal terminal, and the gate is connected to the second clock signal terminal, and the first transistor and the second transistor corresponding to the same signal output terminal are arranged correspondingly, and the second transistor corresponding to the same signal output terminal is arranged correspondingly to the first clock signal terminal.

[0020] In an exemplary embodiment of the present disclosure, the output circuit is further connected to a second clock signal terminal and one or more first clock signal terminals, the first clock signal terminals and the signal output terminals are correspondingly arranged, and the output circuit is configured to respond to a signal of a first node and a first clock signal terminal connected thereto to transmit a signal of the second clock signal terminal to a signal output terminal corresponding to the first clock signal terminal;

[0021] Wherein, different output circuits are connected to the same group of first clock signal terminals, and the second clock signal terminals connected to different output circuits are at least used to output valid levels respectively in different time periods.

[0022] In an exemplary embodiment of the present disclosure, the output circuit includes:

[0023] One or more first transistors, each of the first transistors and the signal output terminal being provided correspondingly, a first electrode of the first transistor being connected to the corresponding signal output terminal, and a gate electrode being connected to the first node;

[0024] One or more second transistors, the second transistors are arranged corresponding to the signal output terminal, the first electrode of the second transistor is connected to the second electrode of the corresponding first transistor, the second electrode is connected to the second clock signal terminal, and the gate is connected to the corresponding first clock signal terminal, and the first transistor and the second transistor corresponding to the same signal output terminal are arranged correspondingly, and the second transistor corresponding to the same signal output terminal is arranged correspondingly to the first clock signal terminal.

[0025] In an exemplary embodiment of the present disclosure, the output circuit is further connected to a pull-down node, and the output circuit is further configured to respond to a signal of the pull-down node to input an invalid level to each of the signal output terminals.

[0026] In an exemplary embodiment of the present disclosure, the output circuit further includes:

[0027] One or more third transistors, the third transistors and the signal output terminal are correspondingly arranged, the first electrode of the third transistor is connected to the first power supply terminal, the second electrode is connected to the corresponding signal output terminal, the gate is connected to the pull-down node, and the first power supply terminal is used to output an invalid level.

[0028] In an exemplary embodiment of the present disclosure, the isolation circuit includes:

[0029] A fourth transistor, wherein a first electrode of the fourth transistor is connected to the pull-up node, a second electrode is connected to the first node, and a gate is connected to the second power supply terminal.

[0030] In an exemplary embodiment of the present disclosure, the fourth transistor is an N-type transistor, the effective level output by the pull-up node is V1, the voltage of the second power supply terminal is V2, and V2-V1 is less than the threshold voltage of the fourth transistor.

[0031] In an exemplary embodiment of the present disclosure, the shift register unit includes two output circuits and two isolation circuits.

[0032] In an exemplary embodiment of the present disclosure, the shift register unit further includes:

[0033] a first input circuit connected to a first signal input terminal and a pull-up node, wherein the first input circuit is configured to input a valid level to the pull-up node in response to a signal from the first signal input terminal;

[0034] a first pull-up circuit connected to a third power supply terminal, a pull-down node, and a second node, configured to respond to an active level of the third power supply terminal to transmit the active level of the third power supply terminal to the second node, and to respond to a signal of the second node to transmit the active level of the third power supply terminal to the pull-down node;

[0035] a first pull-down circuit connected to the pull-up node, the pull-down node, and the second node, the first pull-down circuit being configured to input an invalid level to the second node in response to a signal from the pull-up node, and to input an invalid level to the pull-down node in response to a signal from the pull-up node;

[0036] a second pull-down circuit connected to the pull-up node and the pull-down node, wherein the second pull-down circuit is configured to respond to a signal of the pull-down node to input an invalid level to the pull-up node;

[0037] The first reset circuit is connected to the first reset signal terminal and the pull-up node, and is used for responding to the signal of the first reset signal terminal to input an invalid level to the pull-up node.

[0038] In an exemplary embodiment of the present disclosure, the shift register unit further includes:

[0039] a second input circuit connected to the first signal input terminal and a pull-down node, the second input circuit being configured to input an invalid level to the pull-down node in response to a signal from the first signal input terminal;

[0040] a cascade circuit connected to the pull-up node, the pull-down node, the third clock signal terminal, and the cascade output terminal, the cascade circuit being configured to respond to a signal from the pull-up node to transmit a signal from the third clock signal terminal to the cascade output terminal, and to respond to a signal from the pull-down node to input an invalid level to the cascade output terminal;

[0041] a second reset circuit connected to the second reset signal terminal and the pull-up node, wherein the second reset circuit is configured to input an invalid level to the pull-up node in response to a signal from the second reset signal terminal;

[0042] a first gating circuit connected to the second signal input terminal, the gating signal terminal, the third node, the fourth clock signal terminal, and the pull-up node, the first gating circuit being configured to transmit the signal of the second signal input terminal to the third node in response to a signal of the gating signal terminal, and to input a valid level to the pull-up node in response to signals of the third node and the fourth clock signal terminal;

[0043] The second gating circuit is connected to the pull-down node, the third node, the pull-down node, and the fourth clock signal terminal. The second gating circuit is used to respond to the signals of the third node and the fourth clock signal terminal to input an invalid level to the pull-down node.

[0044] In an exemplary embodiment of the present disclosure, the first input circuit is configured to input a valid level to the pull-up node via the first signal input terminal in response to a signal from the first signal input terminal;

[0045] The first pull-down circuit is further connected to a fourth power supply terminal and a fifth power supply terminal, and is configured to respond to a signal from the pull-up node by using the fifth power supply terminal to input an invalid level to the second node, and respond to a signal from the pull-up node by using the fourth power supply terminal to input an invalid level to the pull-down node;

[0046] The second pull-down circuit is further connected to the fourth power supply terminal, and the second pull-down circuit is used to input an invalid level to the pull-up node using the fourth power supply terminal in response to a signal of the pull-down node;

[0047] The first reset circuit is further connected to the fourth power supply terminal, and the first reset circuit is used to respond to the signal of the first reset signal terminal and input an invalid level to the pull-up node using the fourth power supply terminal;

[0048] The second input circuit is further connected to the fourth power supply terminal, and is configured to respond to a signal from the first signal input terminal and input an invalid level to the pull-down node using the fourth power supply terminal;

[0049] The cascade circuit is further connected to the fourth power supply terminal, and the cascade circuit is configured to input an invalid level to the cascade output terminal using the fourth power supply terminal in response to a signal from the pull-down node;

[0050] The second reset circuit is further connected to the fourth power supply terminal, and the second reset circuit is used to respond to the signal of the second reset signal terminal and input an invalid level to the pull-up node using the fourth power supply terminal;

[0051] The first gating circuit is used for responding to the signals of the third node and the fourth clock signal terminal and inputting a valid level to the pull-up node by using the fourth clock signal terminal;

[0052] The first signal input terminal is multiplexed as the second signal input terminal;

[0053] The second gating circuit is further connected to the fourth power supply terminal, and is configured to respond to signals from the third node and the fourth clock signal terminal and input an invalid level to the pull-down node using the fourth power supply terminal.

[0054] In an exemplary embodiment of the present disclosure, the first input circuit includes:

[0055] a fifth transistor, having a first electrode connected to the first signal input terminal, a second electrode connected to the fourth node, and a gate connected to the first signal input terminal;

[0056] a sixth transistor, having a first electrode connected to the fourth node, a second electrode connected to the pull-up node, and a gate connected to the first signal input terminal;

[0057] The first pull-up circuit comprises:

[0058] a seventh transistor, a first electrode connected to the third power supply terminal, and a gate connected to the third power supply terminal;

[0059] an eighth transistor, having a first electrode connected to the second electrode of the seventh transistor, a second electrode connected to the second node, and a gate connected to the third power supply terminal;

[0060] a ninth transistor, having a first electrode connected to the third power supply terminal, a second electrode connected to the pull-down node, and a gate connected to the second node;

[0061] The first pull-down circuit comprises:

[0062] a tenth transistor, having a first electrode connected to the fifth power supply terminal, a second electrode connected to the second node, and a gate connected to the pull-up node;

[0063] an eleventh transistor, having a first electrode connected to the fourth power supply terminal, a second electrode connected to the pull-down node, and a gate connected to the pull-up node;

[0064] The second pull-down circuit includes:

[0065] a twelfth transistor, having a first electrode connected to the pull-up node, a second electrode connected to the fifth node, and a gate connected to the pull-down node;

[0066] a thirteenth transistor, having a first electrode connected to the fourth power supply terminal, a second electrode connected to the fifth node, and a gate connected to the pull-down node;

[0067] The second input circuit includes:

[0068] a fourteenth transistor, having a first electrode connected to the fourth power supply terminal, a second electrode connected to the pull-down node, and a gate connected to the first signal input terminal;

[0069] The cascade circuit comprises:

[0070] a fifteenth transistor, having a first electrode connected to the third clock signal terminal, a second electrode connected to the cascade output terminal, and a gate connected to the pull-up node;

[0071] a sixteenth transistor, having a first electrode connected to the fourth power supply terminal, a second electrode connected to the cascade output terminal, and a gate connected to the pull-down node;

[0072] a second capacitor, a first electrode of which is connected to the pull-up node, and a second electrode of which is connected to the cascade output terminal;

[0073] The first reset circuit includes:

[0074] a seventeenth transistor, having a first electrode connected to the pull-up node, a second electrode connected to the sixth node, and a gate connected to the first reset signal terminal;

[0075] an eighteenth transistor, having a first electrode connected to the fourth power supply terminal, a second electrode connected to the sixth node, and a gate connected to the first reset signal terminal;

[0076] The second reset circuit includes:

[0077] a nineteenth transistor, having a first electrode connected to the pull-up node, a second electrode connected to the seventh node, and a gate connected to the second reset signal terminal;

[0078] a twentieth transistor, having a first electrode connected to the fourth power supply terminal, a second electrode connected to the seventh node, and a gate connected to the second reset signal terminal;

[0079] The first gating circuit includes:

[0080] A twenty-first transistor, having a first electrode connected to the second signal input terminal, a second electrode connected to the eighth node, and a gate connected to the selection signal terminal;

[0081] a twenty-second transistor, having a first electrode connected to the eighth node, a second electrode connected to the third node, and a gate connected to the selection signal terminal;

[0082] A twenty-third transistor, having a first electrode connected to the fourth clock signal terminal and a gate connected to the third node;

[0083] a twenty-fourth transistor, having a first electrode connected to the second electrode of the twenty-third transistor, a second electrode connected to the ninth node, and a gate connected to the fourth clock signal terminal;

[0084] A twenty-fifth transistor, having a first electrode connected to the ninth node, a second electrode connected to the pull-up node, and a gate connected to the fourth clock signal terminal;

[0085] a third capacitor, wherein the first electrode is connected to the third node, and the second electrode is connected to a stable voltage terminal;

[0086] The second gating circuit includes:

[0087] A twenty-sixth transistor, having a first electrode connected to the pull-down node and a gate connected to the fourth clock signal terminal;

[0088] The twenty-seventh transistor has a first electrode connected to the second electrode of the twenty-sixth transistor, a second electrode connected to the fourth power supply terminal, and a gate connected to the third node.

[0089] In an exemplary embodiment of the present disclosure, the shift register unit further includes:

[0090] a first node control circuit connected to the pull-up node, the fourth node, the fifth node, the sixth node, the seventh node, and the ninth node, and configured to respond to a signal from the pull-up node to input a valid level to the fourth node, the fifth node, the sixth node, the seventh node, and the ninth node;

[0091] The second node control circuit is connected to the eighth node and the third node, and is configured to respond to a signal from the third node to input a valid level to the eighth node.

[0092] In an exemplary embodiment of the present disclosure, the first node control circuit includes:

[0093] A twenty-eighth transistor, having a first electrode connected to the seventh power supply terminal, a second electrode connected to the fourth node, the fifth node, the sixth node, the seventh node, and the ninth node, and a gate connected to the pull-up node;

[0094] The second node control circuit includes:

[0095] a twenty-ninth transistor, having a first electrode connected to the sixth power supply terminal, a second electrode connected to the eighth node, and a gate connected to the third node;

[0096] The sixth power supply terminal and the seventh power supply terminal are used to output a valid electrical level.

[0097] According to one aspect of the present disclosure, a gate driving circuit is provided, wherein the gate driving circuit includes a plurality of the above-mentioned shift register units, and the plurality of shift register units are cascaded.

[0098] According to one aspect of the present disclosure, a gate driving circuit is provided, wherein the gate driving circuit comprises a plurality of the above-mentioned shift register units, wherein the plurality of the shift register units are cascaded;

[0099] The first signal input terminal and the second signal input terminal of the n-th shift register unit are connected to the cascade output terminal of the nm-th shift register unit, and the first reset signal terminal of the n-th shift register unit is connected to the cascade output terminal of the n+p-th shift register unit.

[0100] Wherein, n, m, and p are integers greater than or equal to 1, and nm is greater than or equal to 1.

[0101] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes the above-mentioned gate driving circuit.

[0102] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0103] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0104] FIG1 is a schematic structural diagram of an exemplary embodiment of a shift register unit disclosed herein;

[0105] FIG2 is a schematic structural diagram of another exemplary embodiment of a shift register unit disclosed herein;

[0106] FIG3 is a schematic structural diagram of an exemplary embodiment of a gate driving circuit disclosed herein;

[0107] FIG4 is a timing diagram of various signals in a driving method of the shift register unit in the gate driving circuit shown in FIG3 ;

[0108] FIG5 is a schematic structural diagram of another exemplary embodiment of a shift register unit disclosed herein;

[0109] FIG6 is a schematic structural diagram of an exemplary embodiment of a gate driving circuit disclosed herein;

[0110] FIG7 is a timing diagram of various signals in a driving method of the shift register unit in the gate driving circuit shown in FIG6 ;

[0111] FIG8 is a schematic structural diagram of another exemplary embodiment of the gate driving circuit disclosed herein;

[0112] FIG9 is a timing diagram of various signals in a driving method of the shift register unit in the gate driving circuit shown in FIG8 ;

[0113] FIG10 is a schematic structural diagram of another exemplary embodiment of a shift register unit disclosed herein. DETAILED DESCRIPTION

[0114] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0115] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0116] As shown in Figure 1, a schematic diagram of the structure of an exemplary embodiment of a shift register unit of the present disclosure is provided. The shift register unit includes: multiple output circuits 1 and multiple isolation circuits 3. The output circuits 1 include a first node N1 and one or more signal output terminals G. The output circuits 1 are configured to input a shift signal to the signal output terminals G in response to a signal at the first node N1. The isolation circuits 3 are provided corresponding to the output circuits 1. The isolation circuits 3 connect the pull-up node Q and the corresponding first node N1 of the output circuits 1. The isolation circuits 3 are configured to reduce leakage current from the first node N1 to the pull-up node Q.

[0117] The shift register unit provided in this exemplary embodiment can provide gate drive signals to multiple rows of pixel drive circuits through multiple signal output terminals G of multiple output circuits, thereby facilitating a narrow-frame design for the display panel, and can also reduce the instability of the pull-up node Q voltage caused by too many signal output terminals G.

[0118] It should be noted that the shift register unit shown in Figure 1 only exemplarily shows two output circuits 1 and two isolation circuits 3, and each output circuit 1 includes four signal output terminals. It should be understood that in other exemplary embodiments, the shift register unit may also include other numbers of output circuits 1 and isolation circuits 3, and the output circuit 1 may include other numbers of signal output terminals, and the number of signal output terminals in different output circuits may be the same or different.

[0119] In this exemplary embodiment, the output circuit 1 may include multiple signal output terminals G. The output circuit 1 is configured to sequentially input shift signals to the multiple signal output terminals G in response to a signal at the first node N1, and the shift signals at all the signal output terminals G in the multiple output circuits 1 are not output simultaneously. For example, the shift signals at all the signal output terminals G in the multiple output circuits 1 are output sequentially, so that the multiple signal output terminals G of the shift register can respectively provide gate drive signals to pixel drive circuits in different rows. It should be noted that the sequentially output shift signals may partially overlap or may not overlap at all.

[0120] FIG2 is a schematic diagram of another exemplary embodiment of a shift register unit according to the present disclosure. The shift register unit includes two output circuits: output circuits 11 and 12, and two isolation circuits: isolation circuits 31 and 32. Output circuit 11 and isolation circuit 31 are provided in correspondence with each other, and output circuit 12 and isolation circuit 32 are provided in correspondence with each other. Output circuit 11 includes four signal output terminals: G1, G2, G3, and G4, and output circuit 12 includes four signal output terminals: G5, G6, G7, and G8.

[0121] In this exemplary embodiment, the output circuit further includes: one or more first capacitors, each of which is provided in correspondence with the signal output terminal and is connected between the corresponding signal output terminal and the first node. For example, as shown in FIG2 , the output circuit 11 further includes four first capacitors: C11, C12, C13, and C14, and the output circuit 12 further includes four first capacitors: C15, C16, C17, and C18. The first capacitor C11 is provided in correspondence with the signal output terminal G1 and is connected between the signal output terminal G1 and the first node N1. Similarly, the first capacitor C12 is provided in correspondence with the signal output terminal G2, and the first capacitor C18 is provided in correspondence with the signal output terminal G8.

[0122] In this exemplary embodiment, as shown in FIG1 , the output circuit 1 is further connected to one or more first clock signal terminals CLKE. The first clock signal terminal CLKE is used to provide a shift signal. The first clock signal terminal CLKE is correspondingly provided to the signal output terminal G. The output circuit 1 is configured to respond to a signal at a first node N1 to transmit the signal of the first clock signal terminal CLKE to the signal output terminal G corresponding to the first clock signal terminal CLKE. For example, as shown in FIG2 , the output circuit 11 is connected to the first clock signal terminals CLKE1, CLKE2, CLKE3, and CLKE4, and the output circuit 12 is connected to the first clock signal terminals CLKE5, CLKE6, CLKE7, and CLKE8. The first clock signal terminal CLKE1 is correspondingly provided to the signal output terminal G1. The output circuit 11 is configured to respond to a signal at the first node N1 to transmit the signal of the first clock signal terminal CLKE1 to the signal output terminal G1. Similarly, the first clock signal terminal CLKE2 is correspondingly provided to the signal output terminal G2, and the first clock signal terminal CLKE8 is correspondingly provided to the signal output terminal G8. In this exemplary embodiment, all first clock signal terminals CLKE in the plurality of output circuits 1 are respectively used to output different clock signals.

[0123] In this exemplary embodiment, the output circuit 1 includes one or more first transistors, each of which is configured to correspond to a signal output terminal. The first electrode of the first transistor is connected to the corresponding signal output terminal, the second electrode is connected to the corresponding first clock signal terminal, and the gate is connected to the first node N1. The first transistors corresponding to the same signal output terminal are configured to correspond to the first clock signal terminal. For example, as shown in FIG2 , the output circuit 11 includes four first transistors T101, T102, T103, and T104, and the output circuit 12 includes four first transistors T105, T106, T107, and T108. The first transistor T101 is configured to correspond to the signal output terminal G1. The first electrode of the first transistor T1 is connected to the signal output terminal G1, and the second electrode is connected to the first clock signal terminal CLKE1. Similarly, the first transistor T102 is configured to correspond to the signal output terminal G2, and the first transistor T108 is configured to correspond to the signal output terminal G8. The eight first clock signal terminals can output shift signals to the respective signal output terminals in sequence through the corresponding first transistors.

[0124] In this exemplary embodiment, the effective level of the shift signal can be a high level. When each first clock signal terminal sequentially outputs a high-level pulse signal, the voltage of the first node N1 is pulled high due to the first capacitive coupling. The pulled-up first node N1 facilitates conduction of the output circuit. Furthermore, the isolation circuit 3 can alleviate the problem of leakage caused by the pulled-up first node N1 pulling up the node Q.

[0125] In this exemplary embodiment, the output circuit is further connected to a pull-down node QB and is further configured to respond to a signal at the pull-down node QB to input an inactive level to each signal output terminal. For example, as shown in FIG2 , the output circuit 11 further includes four third transistors T31, T32, T33, and T34, and the output circuit 12 further includes four third transistors T35, T36, T37, and T38. The third transistor T31 is provided corresponding to the signal output terminal G1. The first electrode of the third transistor T31 is connected to the first power supply terminal VGL1, the second electrode is connected to the corresponding signal output terminal G1, and the gate is connected to the pull-down node QB. The first power supply terminal VGL1 is configured to output an inactive level. Similarly, the third transistor T32 is provided corresponding to the signal output terminal G2, and the third transistor T38 is provided corresponding to the signal output terminal G8. The first power supply terminal VGL1 can reset each signal output terminal to an inactive level via each of the third transistors.

[0126] The effective level is a potential that can drive the target circuit to work normally. For example, the effective level for driving an N-type transistor is a high level, and the effective level for driving a P-type transistor is a low level.

[0127] In this exemplary embodiment, the isolation circuit 3 includes a fourth transistor, wherein a first electrode of the fourth transistor is connected to the pull-up node Q, a second electrode is connected to the first node N1, and a gate is connected to the second power supply terminal VDD2. For example, as shown in FIG2 , the isolation circuit 31 includes a fourth transistor T41, and the isolation circuit 32 includes a fourth transistor T42. The fourth transistor may be an N-type transistor, wherein the effective voltage level outputted by the pull-up node Q is V1, the voltage of the second power supply terminal VDD2 is V2, and V2-V1 is less than the threshold voltage of the fourth transistor. That is, when the voltage of the first node N1 is greater than the voltage of the pull-up node Q, the gate-source voltage difference of the fourth transistor is less than its threshold voltage, and the fourth transistor is non-conductive, thereby reducing leakage current from the first node N1 to the pull-up node Q.

[0128] It should be understood that in other exemplary embodiments, the isolation circuit 3 may also have other structures. For example, the isolation circuit 3 may include a unidirectionally conducting diode, with the input end of the diode connected to the pull-up node and the output end connected to the first node.

[0129] In this exemplary embodiment, as shown in FIG2 , the shift register unit may further include: a first input circuit 21, a first pull-up circuit 22, a first pull-down circuit 23, a second pull-down circuit 24, and a first reset circuit 25. The first input circuit 21 is connected to the first signal input terminal IN1 and the pull-up node Q, and the first input circuit 21 is used to input an effective level to the pull-up node Q in response to the signal of the first signal input terminal IN1; the first pull-up circuit 22 is connected to the third power supply terminal VDD3, the pull-down node QB, and the second node N2, and is used to respond to the effective level of the third power supply terminal VDD3 to transmit the effective level of the third power supply terminal VDD3 to the second node N2, and is used to respond to the signal of the second node N2 to transmit the effective level of the third power supply terminal VDD3 to the pull-down node QB; the first pull-down circuit 23 is connected to the pull-up node Point Q, the pull-down node QB, and the second node N2, the first pull-down circuit 23 is used to respond to the signal of the pull-up node Q to input an invalid level to the second node N2, and is used to respond to the signal of the pull-up node Q to input an invalid level to the pull-down node QB; the second pull-down circuit 24 is connected to the pull-up node Q and the pull-down node QB, the second pull-down circuit 24 is used to respond to the signal of the pull-down node QB to input an invalid level to the pull-up node Q; the first reset circuit 25 is connected to the first reset signal terminal Re1 and the pull-up node Q, and is used to respond to the signal of the first reset signal terminal Re1 to input an invalid level to the pull-up node Q.

[0130] In this exemplary embodiment, as shown in FIG2 , the shift register unit further includes: a second input circuit 26, a cascade circuit 27, a second reset circuit 28, a first gating circuit 29, and a second gating circuit 210. The second input circuit 26 is connected to the first signal input terminal and the pull-down node QB, and is used to respond to the signal of the first signal input terminal IN1 to input an invalid level to the pull-down node QB; the cascade circuit 27 is connected to the pull-up node Q, the pull-down node QB, the third clock signal terminal CLKD, and the cascade output terminal CR, and is used to respond to the signal of the pull-up node Q to transmit the signal of the third clock signal terminal CLKD to the cascade output terminal CR, and is used to respond to the signal of the pull-down node QB to input an invalid level to the cascade output terminal CR; the second reset circuit 28 is connected to the second reset signal terminal Re2 and the pull-up node Q, and is used to respond to the signal of the second reset signal terminal Re2 to pull up the node Q inputs an invalid level; the first gating circuit 29 is connected to the second signal input terminal IN2, the gating signal terminal OE, the third node N3, the fourth clock signal terminal CLKA, and the pull-up node Q. The first gating circuit 29 is used to respond to the signal of the gating signal terminal OE to transmit the signal of the second signal input terminal to the third node N3, and to respond to the signals of the third node N3 and the fourth clock signal terminal CLKA to input a valid level to the pull-up node Q; the second gating circuit 210 is connected to the pull-down node QB, the third node N3, the pull-down node QB, and the fourth clock signal terminal CLKA. The second gating circuit 210 is used to respond to the signals of the third node N3 and the fourth clock signal terminal CLKA to input an invalid level to the pull-down node QB.

[0131] In this exemplary embodiment, as shown in Figure 2, the first input circuit 21 is used to respond to the signal of the first first signal input terminal IN1 and use the first signal input terminal IN1 to pull up the node Q to input a valid level; the first pull-down circuit 23 is also connected to the fourth power supply terminal VGL4 and the fifth power supply terminal VGL5. The first pull-down circuit 23 is used to respond to the signal of the pull-up node Q and use the fifth power supply terminal VGL5 to input an invalid level to the second node N2, and is used to respond to the signal of the pull-up node Q and use the fourth power supply terminal VGL4 to input an invalid level to the pull-down node QB; the second pull-down circuit 24 is also connected to the fourth power supply terminal VGL4. The second pull-down circuit 24 is used to respond to the signal of the pull-down node QB and use the fourth power supply terminal VGL4 to input an invalid level to the pull-up node Q; the first reset circuit 25 is also connected to the fourth power supply terminal VGL4. The first reset circuit 25 is used to respond to the signal of the first reset signal terminal Re1 and use the fourth power supply terminal VGL4 to input an invalid level to the pull-up node Q; the second input circuit 26 is also connected to the fourth power supply terminal VGL4. The second input The circuit 26 is configured to respond to a signal from the first signal input terminal IN1 and utilize the fourth power supply terminal VGL4 to pull down the node QB and input an invalid level. The cascade circuit 27 is further connected to the fourth power supply terminal VGL4 and is configured to respond to a signal from the pull-down node QB and utilize the fourth power supply terminal VGL4 to input an invalid level to the cascade output terminal CR. The second reset circuit 28 is further connected to the fourth power supply terminal VGL4 and is configured to respond to a signal from the second reset signal terminal Re2 and utilize the fourth power supply terminal VGL4 to pull up the node Q and input an invalid level. The first selection circuit 29 is configured to respond to signals from the third node N3 and the fourth clock signal terminal CLKA and utilize the fourth clock signal terminal CLKA to pull up the node Q and input an invalid level. The first signal input terminal IN1 is multiplexed as the second signal input terminal IN2. The second selection circuit 210 is further connected to the fourth power supply terminal VGL4 and is configured to respond to signals from the third node N3 and the fourth clock signal terminal CLKA and utilize the fourth power supply terminal VGL4 to pull down the node QB and input an invalid level.

[0132] It should be noted that the above-mentioned valid level and invalid level can also be provided through other power signal terminals or clock signal terminals.

[0133] In this exemplary embodiment, as shown in FIG2 , the first input circuit 21 includes a fifth transistor T5 and a sixth transistor T6. The fifth transistor T5 has a first electrode connected to the first signal input terminal IN1, a second electrode connected to the fourth node N4, and a gate connected to the first signal input terminal IN1. The sixth transistor T6 has a first electrode connected to the fourth node N4, a second electrode connected to the pull-up node Q, and a gate connected to the first signal input terminal IN1. The first pull-up circuit 22 includes a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. The seventh transistor T7 has a first electrode connected to the third power supply terminal VDD3 and a gate connected to the third power supply terminal VDD3. The eighth transistor T8 has a first electrode connected to the second electrode of the seventh transistor, a second electrode connected to the second node N2, and a gate connected to the third power supply terminal VDD3. The ninth transistor T9 has a first electrode connected to the third power supply terminal VDD3, a second electrode connected to the pull-down node QB, and a gate connected to the second node N2. The first pull-down circuit 23 includes a tenth transistor T10 and an eleventh transistor T11. The tenth transistor T10 has a first electrode connected to the fifth power supply terminal VGL5, a second electrode connected to the second node N2, and a gate connected to the pull-up node Q. The eleventh transistor T11 has a first electrode connected to the fourth power supply terminal VGL4, a second electrode connected to the pull-down node QB, and a gate connected to the pull-up node Q. The second pull-down circuit 24 includes a twelfth transistor T12 and a thirteenth transistor T13. The twelfth transistor T12 has a first electrode connected to the pull-up node Q, a second electrode connected to the fifth node N5, and a gate connected to the pull-down node QB. The thirteenth transistor T13 has a first electrode connected to the fourth power supply terminal VGL4, a second electrode connected to the fifth node N5, and a gate connected to the pull-down node QB. The second input circuit 26 includes a fourteenth transistor T14. The fourteenth transistor T14 has a first electrode connected to the fourth power supply terminal VGL4, a second electrode connected to the pull-down node QB, and a gate connected to the first signal input terminal IN1. The cascade circuit 27 includes a fifteenth transistor T15, a sixteenth transistor T16, and a second capacitor C2. The fifteenth transistor T15 has a first electrode connected to the third clock signal terminal CLKD, a second electrode connected to the cascade output terminal CR, and a gate connected to the pull-up node Q. The sixteenth transistor T16 has a first electrode connected to the fourth power supply terminal VGL4, a second electrode connected to the cascade output terminal CR, and a gate connected to the pull-down node QB. The second capacitor C2 has a first electrode connected to the pull-up node Q, and a second electrode connected to the cascade output terminal CR. The first reset circuit 25 includes a seventeenth transistor T17 and an eighteenth transistor T18. The seventeenth transistor T17 has a first electrode connected to the pull-up node Q, a second electrode connected to the sixth node N6, and a gate connected to the first reset signal terminal Re1. The eighteenth transistor T18 has a first electrode connected to the fourth power supply terminal VGL4, a second electrode connected to the sixth node N6, and a gate connected to the first reset signal terminal Re1.The second reset circuit 28 includes: a nineteenth transistor T19 and a twentieth transistor T20, wherein a first electrode of the nineteenth transistor T19 is connected to the pull-up node Q, a second electrode is connected to the seventh node N7, and a gate is connected to the second reset signal terminal Re2; a first electrode of the twentieth transistor T20 is connected to the fourth power supply terminal VGL4, a second electrode is connected to the seventh node N7, and a gate is connected to the second reset signal terminal Re2. The first gating circuit 29 includes: a twenty-first transistor T21, a twenty-second transistor T22, a twenty-third transistor T23, a twenty-fourth transistor T24, a twenty-fifth transistor T25, and a third capacitor C3. The twenty-first transistor T21 has a first electrode connected to the second signal input terminal IN2, a second electrode connected to the eighth node N8, and a gate connected to the gating signal terminal OE. The twenty-second transistor T22 has a first electrode connected to the eighth node N8, a second electrode connected to the third node N3, and a gate connected to the gating signal terminal OE. The twenty-third transistor T23 has a first electrode connected to the fourth clock signal terminal CLKA, and a gate connected to the third node N3. The twenty-fourth transistor T24 has a first electrode connected to the second electrode of the twenty-third transistor T23, a second electrode connected to the ninth node N9, and a gate connected to the fourth clock signal terminal CLKA. The twenty-fifth transistor T25 has a first electrode connected to the ninth node N9, a second electrode connected to the pull-up node Q, and a gate connected to the fourth clock signal terminal CLKA. The third capacitor C3 has a first electrode connected to the third node N3, and a second electrode connected to a stable voltage terminal. For example, the second electrode of the third capacitor C3 may be connected to the fourth power supply terminal VGL4. The second gating circuit 210 includes: a twenty-sixth transistor T26 and a twenty-seventh transistor T27, wherein a first electrode of the twenty-sixth transistor T26 is connected to the pull-down node QB, and a gate thereof is connected to the fourth clock signal terminal CLKA; a first electrode of the twenty-seventh transistor T27 is connected to the second electrode of the twenty-sixth transistor, a second electrode thereof is connected to the fourth power supply terminal VGL4, and a gate thereof is connected to the third node N3.

[0134] In this exemplary embodiment, as shown in Figure 2, the shift register unit also includes: a first node control circuit 211 and a second node control circuit 212. The first node control circuit 211 is connected to the pull-up node Q, the fourth node N4, the fifth node N5, the sixth node N6, the seventh node N7, and the ninth node N9, and is used to respond to the signal of the pull-up node Q to input a valid level to the fourth node N4, the fifth node N5, the sixth node N6, the seventh node N7, and the ninth node N9; the second node control circuit 212 is connected to the eighth node N8 and the third node N3, and is used to respond to the signal of the third node N3 to input a valid level to the eighth node N8.

[0135] In this exemplary embodiment, as shown in FIG2 , the first node control circuit 211 includes a 28th transistor T28, whose first electrode is connected to the seventh power supply terminal VDD7, whose second electrode is connected to the fourth node N4, the fifth node N5, the sixth node N6, the seventh node N7, and the ninth node N9, and whose gate is connected to the pull-up node Q. The second node control circuit 212 includes a 29th transistor T29, whose first electrode is connected to the sixth power supply terminal VDD6, whose second electrode is connected to the eighth node N8, and whose gate is connected to the third node N3. The sixth power supply terminal VDD6 and the seventh power supply terminal VDD7 are used to output a valid voltage level. The first node control circuit 211 inputs a valid voltage level to the fourth node N4, the fifth node N5, the sixth node N6, the seventh node N7, and the ninth node N9, thereby reducing leakage current from the pull-up node Q to the fourth node N4, the fifth node N5, the sixth node N6, the seventh node N7, and the ninth node N9. Similarly, the second node control circuit 212 can reduce leakage current from the third node N3 to the eighth node N8.

[0136] The first to twenty-ninth transistors can all be N-type transistors, the first power supply terminal VGL1, the fourth power supply terminal VGL4, and the fifth power supply terminal VGL5 are low-level power supply terminals, and the second power supply terminal VDD2, the third power supply terminal VDD3, the sixth power supply terminal VDD6, and the seventh power supply terminal VDD7 are high-level power supply terminals.

[0137] FIG3 is a schematic diagram of the structure of an exemplary embodiment of a gate drive circuit of the present disclosure, which may include multiple cascaded shift register units GOA. The first signal input terminal IN1 and the second signal input terminal IN2 of the shift register unit GOA at this stage may be connected to the cascade output terminal CR of the adjacent previous stage shift register unit, and the first reset signal terminal Re1 of the shift register unit GOA at this stage may be connected to the cascade output terminal CR of the adjacent next stage shift register unit.

[0138] The gate drive circuit may further include 16 first clock signal lines: LCLKE1-LCLKE16, and 8 first clock signal lines LCLKE1-LCLKE8 are respectively connected to 8 first clock signal terminals CLKE1-CLKE8 in the odd-numbered shift register unit GOA, wherein the first clock signal line LCLKE1 is connected to the first clock signal terminal CLKE1, the first clock signal line LCLKE2 is connected to the first clock signal terminal CLKE2, the first clock signal line LCLKE3 is connected to the first clock signal terminal CLKE3, the first clock signal line LCLKE4 is connected to the first clock signal terminal CLKE4, the first clock signal line LCLKE5 is connected to the first clock signal terminal CLKE5, the first clock signal line LCLKE6 is connected to the first clock signal terminal CLKE6, the first clock signal line LCLKE7 ​​is connected to the first clock signal terminal CLKE7, and the first clock signal line LCLKE8 is connected to the first clock signal terminal CLKE8. Connected to the first clock signal terminal CLKE8. The eight first clock signal lines LCLKE9-LCLKE16 are respectively connected to the eight first clock signal terminals CLKE1-CLKE8 in the even-numbered stage shift register unit GOA, wherein the first clock signal line LCLKE9 is connected to the first clock signal terminal CLKE1, the first clock signal line LCLKE10 is connected to the first clock signal terminal CLKE2, the first clock signal line LCLKE11 is connected to the first clock signal terminal CLKE3, the first clock signal line LCLKE12 is connected to the first clock signal terminal CLKE4, the first clock signal line LCLKE13 is connected to the first clock signal terminal CLKE5, the first clock signal line LCLKE14 is connected to the first clock signal terminal CLKE6, the first clock signal line LCLKE15 is connected to the first clock signal terminal CLKE7, and the first clock signal line LCLKE16 is connected to the first clock signal terminal CLKE8.

[0139] As shown in FIG3 , eight first clock signal lines LCLKE1-LCLKE8 form one first clock signal line group, and eight first clock signal lines LCLKE9-LCLKE16 form another first clock signal line group. The two first clock signal line groups are alternately connected to the cascaded shift register units. It should be understood that in other exemplary embodiments, the gate drive circuit may include other numbers of first clock signal line groups, and multiple first clock signal line groups may be alternately connected to the cascaded shift register units. Accordingly, the timing on the first clock signal lines needs to be adjusted accordingly.

[0140] As shown in FIG3 , the gate drive circuit may further include two third clock signal lines: LCLKD1 and LCLKD2. The third clock signal line LCLKD1 is connected to the third clock signal terminal CLKD in the odd-numbered shift register unit, and the third clock signal line LCLKD2 is connected to the third clock signal terminal CLKD in the even-numbered shift register unit.

[0141] This exemplary embodiment uses the driving method of the second-stage shift register unit in FIG3 as an example to illustrate. FIG4 shows a timing diagram of various signals in a driving method for the shift register unit in the gate drive circuit shown in FIG3 . LCLKE1-LCLKE16 are timing diagrams of the first clock signal lines LCLKE1-LCLKE16, respectively; LCLKD1 is a timing diagram of the third clock signal line LCLKD1; LCLKD2 is a timing diagram of the third clock signal line LCLKD2; Re2 is a timing diagram of the second reset signal terminal; OE is a timing diagram of the select signal terminal; CLKA is a timing diagram of the fourth clock signal terminal; and Q is a timing diagram of the pull-up node.

[0142] The driving method of the shift register unit may include: an initial stage before display (not shown in the figure), a display stage, and a frame in the display stage includes a scanning stage ts and a blank stage tb.

[0143] In the initial stage, the selection signal terminal OE and the second reset signal terminal Re2 output a high level, the nineteenth transistor T19 and the twentieth transistor T20 are turned on, the second reset circuit 28 transmits a low level signal from the fourth power supply terminal VGL4 to the pull-up node Q, the first pull-up circuit 22 inputs a high level signal to the pull-down node QB, and the output circuits 11 and 12 transmit a low level signal from the first power supply terminal VGL1 to each signal output terminal in response to the signal from the pull-down node QB. Simultaneously, the twenty-first transistor T22 and the twenty-second transistor T23 are turned on, and the second signal input terminal IN2 inputs a low level signal to the third node N3. In the initial stage, the pull-up nodes and the third nodes in all shift register units can be initialized.

[0144] The scanning phase ts includes a first phase t1, a second phase t2, and a third phase t3. In the first phase t1, the third clock signal line LCLKD1 outputs a high-level signal, the cascade output terminal CR of the first-stage shift register unit outputs a high-level signal to the first signal input terminal IN1 and the second signal input terminal IN2 of the second-stage shift register unit, the fifth transistor T5 and the sixth transistor T6 are turned on, the first input circuit 21 transmits the high-level signal of the first signal input terminal IN1 to the pull-up node Q, the fourteenth transistor T14 is turned on, the second input circuit 26 transmits the low-level signal of the fourth power supply terminal VGL4 to the pull-down node QB, the tenth transistor T10 and the eleventh transistor T11 are turned on, the first pull-down circuit 23 transmits the low-level signal of the fourth power supply terminal VGL4 to the pull-down node QB, and transmits the low-level signal of the fifth power supply terminal VGL5 to the second node N2. In the second stage t2: the high-level signal of the pull-up node Q is transmitted to the first node N1 in the two output circuits through the two fourth transistors T41 and T42 respectively. Under the action of the first node N1, all the first transistors T101-T108 in the output circuit are turned on, and the first clock signal lines LCLKE9-LCLKE16 output shift signals in sequence. The first clock signal terminals CLKE1-CLKE8 in the second-stage shift register unit output shift signals in sequence, so that the signal output terminals G1-G8 output shift signals in sequence. In the third stage t3: the third clock signal line LCLKD1 outputs a high-level signal again, the cascade output terminal CR of the third-stage shift register unit outputs a high-level signal to the first reset signal terminal Re1 of the second-stage shift register unit, the seventeenth transistor T17 and the eighteenth transistor T18 are turned on, the first reset circuit 25 transmits the low-level signal of the fourth power supply terminal VGL4 to the pull-up node Q, the first pull-up circuit 22 transmits the high-level signal of the third power supply terminal VDD3 to the pull-down node QB, and under the action of the pull-down node QB, the output circuit transmits the low-level signal of the first power supply terminal VGL1 to each signal output terminal G1-G8. At the same time, the twelfth transistor T12 and the thirteenth transistor T13 are turned on, and the second pull-down circuit 24 transmits the low-level signal of the fourth power supply terminal VGL4 to the pull-up node Q.

[0145] During the blank phase tb, the display panel can sense the threshold and / or mobility of the driving transistors in the pixel driving circuits of some rows. The gate driving circuit can select the pixel driving circuit to be sensed through the selection signal terminal OE. For example, when the gate driving circuit needs to select the pixel driving circuit driven by the second-stage shift register unit, the selection signal line can input a high-level signal to the selection signal terminal OE of the second-stage shift register unit during the first phase t1 of the second-stage shift register unit, so as to input a high-level signal to the third node N3 through the first selection circuit 29. During the blank phase, the fourth clock signal terminal CLKA outputs a high-level signal, the twenty-third transistor T23, the twenty-fourth transistor T24, and the twenty-fifth transistor T25 in the second-stage shift register unit are turned on, the fourth clock signal terminal CLKA inputs a high-level signal to the pull-up node Q, the twenty-sixth transistor T26 and the twenty-seventh transistor T27 are turned on, the second gating circuit 210 transmits the low-level signal of the fourth power supply terminal VGL4 to the pull-down node QB, and the output circuits 11 and 12, under the action of the pull-up node Q, sequentially transmit the shift signals of the first clock signal lines LCLKE9-LCLKE16 to the signal output terminals G1-G8, thereby sensing the driving transistors in the pixel driving circuit. For the unselected shift register units, since the third node N3 is at a low level, the first gating circuit 29 cannot write a high level to the pull-up node Q, and the second gating circuit 210 cannot write a low level to the pull-down node QB. Therefore, the unselected shift register units cannot output shift signals.

[0146] It should be noted that the selection signal line can select the shift register unit at any time during the shift register unit is in the scanning phase. When the first signal input terminal IN1 is not multiplexed as the second signal input terminal IN2, the signal on the second signal input terminal IN2 can be different from the signal on the first signal input terminal IN1. The second signal input terminal IN2 can be connected to the signal output terminal of the adjacent previous-stage shift register unit. The time period during which the selection signal line outputs a valid level needs to at least partially overlap with the time period during which the second signal input terminal IN2 outputs a valid level.

[0147] In other exemplary embodiments, the output circuit 1 may also be connected to a second clock signal terminal and one or more first clock signal terminals, the first clock signal terminal being used to provide a shift signal, the first clock signal terminal and the signal output terminal being provided correspondingly, and the output circuit being used to respond to a signal from the first node N1 and the second clock signal terminal connected thereto to transmit the signal from the first clock signal terminal to the signal output terminal corresponding to the first clock signal terminal; wherein different output circuits are connected to the same group of first clock signal terminals, and the second clock signal terminals connected to different output circuits are used to output valid levels at least in different time periods. For example, as shown in FIG5 , a schematic diagram of the structure of another exemplary embodiment of the shift register unit disclosed herein is provided. The output circuit 11 is connected to the second clock signal terminal CLKB1 and the four first clock signal terminals CLKE1-CLKE4, and the first clock signal terminals CLKE1-CLKE4 are respectively arranged to correspond to the signal output terminals G1-G4. The output circuit 12 is connected to the second clock signal terminal CLKB2 and the four first clock signal terminals CLKE1-CLKE4, and the first clock signal terminals CLKE1-CLKE4 are respectively arranged to correspond to the signal output terminals G5-G8. The output circuit is used to respond to the signal of the first node N1 and the second clock signal terminal connected thereto to transmit the signal of the first clock signal terminal to the signal output terminal corresponding to the first clock signal terminal.

[0148] In this exemplary embodiment, the second clock signal terminal CLKB1 and the second clock signal terminal CLKB2 can each output an active level at different time periods. When the second clock signal terminal CLKB1 outputs an active level, the first clock signal terminals CLKE1-CLKE4 respectively output an active level to the signal output terminals G1-G4; when the second clock signal terminal CLKB2 outputs an active level, the first clock signal terminals CLKE1-CLKE4 respectively output an active level to the signal output terminals G5-G8. This shift register unit can achieve normal driving with fewer first clock signal terminals and fewer first clock signal lines.

[0149] In this exemplary embodiment, the output circuit 1 includes: one or more first transistors and one or more second transistors, wherein the first transistors are arranged corresponding to the signal output terminal, the first electrode of the first transistor is connected to the corresponding signal output terminal, and the gate is connected to the first node N1; the second transistors are arranged corresponding to the signal output terminal, the first electrode of the second transistor is connected to the second electrode of the corresponding first transistor, the second electrode is connected to the corresponding first clock signal terminal, and the gate is connected to the second clock signal terminal, and the first transistors and second transistors corresponding to the same signal output terminal are arranged correspondingly, and the second transistors corresponding to the same signal output terminal are arranged correspondingly to the first clock signal terminal. For example, as shown in FIG5, the output circuit 1 may include: eight first transistors T101-T108 and eight second transistors T201-T208, wherein the first transistor T101 is arranged correspondingly to the signal output terminal G1 and the second transistor T201, and so on, the first transistor T102 is arranged correspondingly to the signal output terminal G2 and the second transistor T202, and the first transistor T108 is arranged correspondingly to the signal output terminal G8 and the second transistor T208. The first transistor and the second transistor may be N-type transistors, and other structures of the shift register unit shown in FIG5 may be the same as those of the shift register unit shown in FIG2 .

[0150] As shown in FIG6 , it is a structural diagram of an exemplary embodiment of the gate drive circuit of the present disclosure. The gate drive circuit may include a plurality of cascaded shift register units shown in FIG5 . The gate drive circuit may also include 8 first clock signal lines: LCLKE1-LCLKE8, and the 4 first clock signal lines LCLKE1-LCLKE4 are respectively connected to the 4 first clock signal terminals CLKE1-CLKE4 in the odd-numbered shift register units GOA, wherein the first clock signal line LCLKE1 is connected to the first clock signal terminal CLKE1, the first clock signal line LCLKE2 is connected to the first clock signal terminal CLKE2, the first clock signal line LCLKE3 is connected to the first clock signal terminal CLKE3, and the first clock signal line LCLKE4 is connected to the first clock signal terminal CLKE4. The 4 first clock signal lines LCLKE5-LCLKE8 are respectively connected to the 4 first clock signal terminals CLKE1-CLKE4 in the even-numbered shift register units GOA, wherein, The first clock signal line LCLKE5 is connected to the first clock signal terminal CLKE1 , the first clock signal line LCLKE6 is connected to the first clock signal terminal CLKE2 , the first clock signal line LCLKE7 ​​is connected to the first clock signal terminal CLKE3 , and the first clock signal line LCLKE8 is connected to the first clock signal terminal CLKE4 .

[0151] As shown in FIG6 , four first clock signal lines LCLKE1-LCLKE4 form one first clock signal line group, and four first clock signal lines LCLKE5-LCLKE8 form another first clock signal line group. The two first clock signal line groups are alternately connected to the cascaded shift register units. It should be understood that in other exemplary embodiments, the gate drive circuit may further include other numbers of first clock signal line groups, and multiple first clock signal line groups may be alternately connected to the cascaded shift register units. Accordingly, the timing on the first clock signal lines needs to be adjusted accordingly.

[0152] As shown in FIG6 , the gate drive circuit may further include two third clock signal lines: LCLKD1 and LCLKD2. The third clock signal line LCLKD1 is connected to the third clock signal terminal CLKD in the odd-numbered shift register unit, and the third clock signal line LCLKD2 is connected to the third clock signal terminal CLKD in the even-numbered shift register unit.

[0153] 6 , the gate drive circuit may further include two second clock signal lines: LCLKB1 and LCLKB2. The second clock signal line LCLKB1 is connected to the second clock signal terminal CLKB1 in the shift register unit, and the second clock signal line LCLKB2 is connected to the second clock signal terminal CLKB2 in the shift register unit.

[0154] This exemplary embodiment uses the driving method of the second-stage shift register unit in FIG6 as an example for description. FIG7 shows a timing diagram of various signals in a driving method for the shift register unit in the gate drive circuit shown in FIG6 . LCLKE1-LCLKE8 are timing diagrams of the first clock signal lines LCLKE1-LCLKE8, respectively; LCLKD1 is a timing diagram of the third clock signal line LCLKD1; LCLKD2 is a timing diagram of the third clock signal line LCLKD2; LCLKB1 is a timing diagram of the second clock signal line LCLKB1; LCLKB2 is a timing diagram of the second clock signal line LCLKB2; Re2 is a timing diagram of the second reset signal terminal; OE is a timing diagram of the select signal terminal; CLKA is a timing diagram of the fourth clock signal terminal; and Q is a timing diagram of the pull-up node.

[0155] The driving method of the shift register unit may also include: an initial stage before display (not shown in the figure), a display stage, and a frame in the display stage includes a scanning stage ts and a blank stage tb.

[0156] In the initial stage, the selection signal terminal OE and the second reset signal terminal Re2 output a high level, the nineteenth transistor T19 and the twentieth transistor T20 are turned on, the second reset circuit 28 transmits the low level signal of the fourth power supply terminal VGL4 to the pull-up node Q, the first pull-up circuit 22 inputs a high level signal to the pull-down node QB, and the output circuits 11 and 12 transmit the low level signal of the first power supply terminal VGL1 to each signal output terminal in response to the signal of the pull-down node QB. At the same time, the twenty-first transistor T22 and the twenty-second transistor T22 are turned on, and the second signal input terminal IN2 inputs a low level signal to the third node N3.

[0157] The scanning phase ts includes: a first phase t1, a second phase t2, and a third phase t3. The second phase t2 includes a first sub-phase t21 and a second sub-phase t22. In the first phase t1, the third clock signal line LCLKD1 outputs a high-level signal, the cascade output terminal CR of the first-stage shift register unit outputs a high-level signal to the first signal input terminal IN1 and the second signal input terminal IN2 of the second-stage shift register unit, the fifth transistor T5 and the sixth transistor T6 are turned on, the first input circuit 21 transmits the high-level signal of the first signal input terminal IN1 to the pull-up node Q, the fourteenth transistor T14 is turned on, the second input circuit 26 transmits the low-level signal of the fourth power supply terminal VGL4 to the pull-down node QB, the tenth transistor T10 and the eleventh transistor T11 are turned on, the first pull-down circuit 23 transmits the low-level signal of the fourth power supply terminal VGL4 to the pull-down node QB, and transmits the low-level signal of the fifth power supply terminal VGL5 to the second node N2. In the first sub-phase t21: the high-level signal of the pull-up node Q is transmitted to the first node N1 in the two output circuits through the two fourth transistors respectively. Under the action of the first node N1, all the first transistors T101-T104 in the output circuit 11 are turned on, the first clock signal lines LCLKE5-LCLKE8 output shift signals in sequence, and the first clock signal terminals CLKE1-CLKE4 in the second-stage shift register unit output shift signals in sequence. At the same time, the second clock signal line LCLKB1 outputs a high level, and the second transistors T201-T204 are turned on, so that the signal output terminals G1-G4 output shift signals in sequence. In the second sub-phase t22: the high-level signal of the pull-up node Q is transmitted to the first node N1 in the two output circuits through the two fourth transistors respectively. Under the action of the first node N1, all the first transistors T105-T108 in the output circuit 12 are turned on, the first clock signal lines LCLKE5-LCLKE8 output shift signals in sequence, the first clock signal terminals CLKE1-CLKE4 in the second-stage shift register unit output shift signals in sequence, and at the same time, the second clock signal line LCLKB2 outputs a high level, the second transistors T205-T208 are turned on, and the signal output terminals G5-G8 output shift signals in sequence.In the third stage t3: the third clock signal line LCLKD1 outputs a high-level signal again, the cascade output terminal CR of the third-stage shift register unit outputs a high-level signal to the first reset signal terminal Re1 of the second-stage shift register unit, the seventeenth transistor T17 and the eighteenth transistor T18 are turned on, the first reset circuit 25 transmits the low-level signal of the fourth power supply terminal VGL4 to the pull-up node Q, the first pull-up circuit 22 transmits the high-level signal of the third power supply terminal VDD3 to the pull-down node QB, and under the action of the pull-down node QB, the output circuit transmits the low-level signal of the first power supply terminal VGL1 to each signal output terminal G1-G8. At the same time, the twelfth transistor T12 and the thirteenth transistor T13 are turned on, and the second pull-down circuit 24 transmits the low-level signal of the fourth power supply terminal VGL4 to the pull-up node Q.

[0158] During the blank phase tb, the display panel can sense the threshold and / or mobility of the driving transistors in the pixel driving circuits of some rows. The gate driving circuit can select the pixel driving circuit to be sensed through the selection signal terminal OE. For example, when the gate driving circuit needs to select the pixel driving circuit driven by the second-stage shift register unit, the selection signal line can input a high-level signal to the selection signal terminal OE of the second-stage shift register unit during the first phase t1 of the second-stage shift register unit, so as to input a high-level signal to the third node N3 through the first selection circuit 29. During the blank phase, the fourth clock signal terminal CLKA outputs a high-level signal, the twenty-third transistor T23, the twenty-fourth transistor T24, and the twenty-fifth transistor T25 in the second-stage shift register unit are turned on, the fourth clock signal terminal CLKA inputs a high-level signal to the pull-up node, the twenty-sixth transistor T26 and the twenty-seventh transistor T27 are turned on, the second gating circuit 210 transmits the low-level signal of the fourth power supply terminal VGL4 to the pull-down node QB, and the output circuits 11 and 12 sequentially output shift signals through the signal output terminals G1-G8, thereby sensing the driving transistors in the pixel driving circuit. Simultaneously, for the unselected shift register units, since the third node N3 is at a low level, the first gating circuit 29 cannot write a high level to the pull-up node Q, and the second gating circuit 210 cannot write a low level to the pull-down node QB. Consequently, the unselected shift register units cannot output shift signals.

[0159] It should be noted that the selection signal line can select the shift register unit at any time during the shift register unit is in the scanning phase. When the first signal input terminal IN1 is not multiplexed as the second signal input terminal IN2, the signal on the second signal input terminal IN2 can be different from the signal on the first signal input terminal IN1. The second signal input terminal IN2 can be connected to the signal output terminal of the adjacent previous-stage shift register unit. The time period during which the selection signal line outputs a valid level needs to at least partially overlap with the time period during which the second signal input terminal IN2 outputs a valid level.

[0160] As shown in Figure 8, it is a structural schematic diagram of another exemplary embodiment of the gate drive circuit of the present invention, which includes multiple cascaded shift register units shown in Figure 5. The gate drive circuit shown in Figure 8 differs from the gate drive circuit shown in Figure 6 in that the gate drive circuit shown in Figure 8 includes four second clock signal lines LCLKB1-LCLKB4. The second clock signal line LCLKB1 is connected to the second clock signal terminal CLKB1 in the odd-numbered shift register unit, and the second clock signal line LCLKB2 is connected to the second clock signal terminal CLKB2 in the odd-numbered shift register unit; the second clock signal line LCLKB3 is connected to the second clock signal terminal CLKB1 in the even-numbered shift register unit, and the second clock signal line LCLKB4 is connected to the second clock signal terminal CLKB2 in the even-numbered shift register unit. As shown in Figure 9, it is a timing diagram of each signal in a driving method for the shift register unit in the gate drive circuit shown in Figure 8. The driving method is the same as the driving method shown in Figure 7.

[0161] In other exemplary embodiments, the output circuit is further connected to the second clock signal terminal and one or more first clock signal terminals, the first clock signal terminal and the signal output terminal are correspondingly arranged, and the output circuit is used to respond to the signal of the first node and the first clock signal terminal connected thereto to transmit the signal of the second clock signal terminal to the signal output terminal corresponding to the first clock signal terminal; wherein different output circuits are connected to the same group of first clock signal terminals, and the second clock signal terminals connected to different output circuits are at least used to output valid levels respectively in different time periods. For example, as shown in Figure 10, it is a structural schematic diagram of another exemplary embodiment of the shift register unit disclosed in the present invention. The output circuit 11 is connected to the second clock signal terminal CLKB1 and the four first clock signal terminals CLKE1-CLKE4, and the first clock signal terminals CLKE1-CLKE4 are respectively corresponding to the signal output terminals G1-G4. The output circuit 12 is connected to the second clock signal terminal CLKB2 and the four first clock signal terminals CLKE1-CLKE4, and the first clock signal terminals CLKE1-CLKE4 are respectively corresponding to the signal output terminals G5-G8.

[0162] In this exemplary embodiment, the second clock signal terminal CLKB1 and the second clock signal terminal CLKB2 can each output an active level at different time periods. When the second clock signal terminal CLKB1 outputs an active level, the output circuit 11 responds to the signals of the first clock signal terminals CLKE1-CLKE4 to sequentially transmit the active level of the second clock signal terminal CLKB1 to the signal output terminals G1-G4. When the second clock signal terminal CLKB2 outputs an active level, the output circuit 12 responds to the signals of the first clock signal terminals CLKE1-CLKE4 to sequentially transmit the active level of the second clock signal terminal CLKB2 to the signal output terminals G5-G8.

[0163] In this exemplary embodiment, the output circuit includes: one or more first transistors and one or more second transistors, wherein the first transistors are arranged corresponding to the signal output terminal, the first electrode of the first transistor is connected to the corresponding signal output terminal, and the gate is connected to the first node; the second transistors are arranged corresponding to the signal output terminal, the first electrode of the second transistor is connected to the second electrode of the corresponding first transistor, the second electrode is connected to the second clock signal terminal, and the gate is connected to the corresponding first clock signal terminal; the first transistors and the second transistors corresponding to the same signal output terminal are arranged correspondingly, and the second transistors corresponding to the same signal output terminal are arranged correspondingly to the first clock signal terminal. For example, as shown in FIG10, the output circuit 11 includes four first transistors T101-T104 and four second transistors T201-T204, wherein the first transistor T101, the second transistor T201, and the signal output terminal G1 are arranged correspondingly, and so on, the first transistor T102, the second transistor T202, and the signal output terminal G2 are arranged correspondingly, and the first transistor T104, the second transistor T204, and the signal output terminal G4 are arranged correspondingly. The output circuit 12 includes four first transistors T105-T108 and four second transistors T205-T208. The first transistor T105, the second transistor T205, and the signal output terminal G5 are correspondingly provided. Similarly, the first transistor T106, the second transistor T206, and the signal output terminal G6 are correspondingly provided. The first transistor T108, the second transistor T208, and the signal output terminal G8 are correspondingly provided. The first transistor and the second transistor can be N-type transistors.

[0164] The other structures of the shift register unit shown in Figure 10 may be the same as those of the shift register unit shown in Figure 2. The gate driving circuit formed by the shift register unit shown in Figure 10 may be as shown in Figures 6 and 8, and the driving method of the shift register unit shown in Figure 10 may be as shown in Figure 7.

[0165] It should be noted that, in other exemplary embodiments, the gate drive circuit may also have other cascade modes, for example, the first signal input terminal and the second signal input terminal of the n-th shift register unit are connected to the cascade output terminal of the nm-th shift register unit, and the first reset signal terminal of the n-th shift register unit is connected to the cascade output terminal of the n+p-th shift register unit; wherein n, m, and p are integers greater than or equal to 1, and nm is greater than or equal to 1.

[0166] This exemplary embodiment also provides a display panel, which may include the above-mentioned gate driving circuit. The display panel can be used in computers, mobile phones, tablet computers, televisions, etc.

[0167] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0168] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0169] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A shift register unit, wherein, The shift register unit includes: A plurality of output circuits, the output circuits including a first node and one or more signal output terminals, and the output circuits being configured to input a shift signal to the signal output terminals in response to a signal of the first node; A plurality of isolation circuits, the isolation circuits being provided corresponding to the output circuits, the isolation circuits connecting a pull-up node and the first node of the corresponding output circuit, and the isolation circuits being configured to reduce the leakage current from the first node to the pull-up node.

2. The shift register unit according to claim 1, wherein, The output circuits include a plurality of the signal output terminals, the output circuits being configured to output a shift signal to the plurality of signal output terminals in response to a signal of the first node, and the shift signals of the plurality of signal output terminals in the plurality of output circuits are not output simultaneously.

3. The shift register unit according to claim 1, wherein, The output circuits further include: One or more first capacitors, the first capacitors being provided corresponding to the signal output terminals, and the first capacitors being connected between the corresponding signal output terminals and the first node.

4. The shift register unit according to claim 1, wherein, The output circuits are further connected to one or more first clock signal terminals, the first clock signal terminals being configured to provide the shift signal, the first clock signal terminals being provided corresponding to the signal output terminals, and the output circuits being configured to transmit the signal of the first clock signal terminals to the signal output terminals corresponding to the first clock signal terminals in response to a signal of the first node; Wherein, all the first clock signal terminals in the plurality of output circuits are respectively configured to output different clock signals.

5. The shift register unit according to claim 4, wherein, The output circuits include: One or more first transistors, the first transistors being provided corresponding to the signal output terminals, a first pole of the first transistors being connected to the corresponding signal output terminals, a second pole being connected to the corresponding first clock signal terminals, and gates being connected to the first node, wherein, the first transistors and the first clock signal terminals corresponding to the same signal output terminal are provided corresponding to each other.

6. The shift register unit according to claim 1, wherein The output circuits are further connected to a second clock signal terminal and one or more first clock signal terminals, the first clock signal terminals being configured to provide the shift signal, the first clock signal terminals being provided corresponding to the signal output terminals, and the output circuits being configured to transmit the signal of the first clock signal terminals to the signal output terminals corresponding to the first clock signal terminals in response to the signal of the first node and the signal of the second clock signal terminal connected thereto; Wherein, different output circuits are connected to the same group of the first clock signal terminals, and the second clock signal terminals connected to different output circuits are at least configured to output valid levels at different time periods respectively.

7. The shift register unit according to claim 6, wherein, The output circuits include: One or more first transistors, the first transistors being provided corresponding to the signal output terminals, a first pole of the first transistors being connected to the corresponding signal output terminals, and gates being connected to the first node; One or more second transistors, the second transistors and the signal output terminals are correspondingly arranged, a first pole of the second transistor is connected to a second pole of the corresponding first transistor, a second pole is connected to the corresponding first clock signal terminal, a gate is connected to the second clock signal terminal, the first transistor and the second transistor corresponding to the same signal output terminal are correspondingly arranged, and the second transistor and the first clock signal terminal corresponding to the same signal output terminal are correspondingly arranged.

8. The shift register unit according to claim 1, wherein, The output circuit is further connected to the second clock signal terminal and one or more first clock signal terminals, the first clock signal terminals and the signal output terminals are correspondingly arranged, and the output circuit is configured to respond to signals of a first node therein and the first clock signal terminals connected thereto to transmit the signal of the second clock signal terminal to the signal output terminal corresponding to the first clock signal terminal; Wherein, different output circuits are connected to the same group of the first clock signal terminals, and the second clock signal terminals connected to different output circuits are at least configured to output valid levels at different time periods respectively.

9. The shift register unit according to claim 8, wherein, The output circuit includes: One or more first transistors, the first transistors and the signal output terminals are correspondingly arranged, a first pole of the first transistor is connected to the corresponding signal output terminal, and a gate is connected to the first node; One or more second transistors, the second transistors and the signal output terminals are correspondingly arranged, a first pole of the second transistor is connected to a second pole of the corresponding first transistor, and the second pole is connected to the second clock signal terminal, a gate is connected to the corresponding first clock signal terminal, the first transistor and the second transistor corresponding to the same signal output terminal are correspondingly arranged, and the second transistor and the first clock signal terminal corresponding to the same signal output terminal are correspondingly arranged.

10. The shift register unit according to claim 1, wherein, The output circuit is further connected to a pull-down node, and the output circuit is further configured to respond to the signal of the pull-down node to input an invalid level to each signal output terminal.

11. The shift register unit according to claim 10, wherein The output circuit further includes: One or more third transistors, the third transistors and the signal output terminals are correspondingly arranged, a first pole of the third transistor is connected to a first power supply terminal, a second pole is connected to the corresponding signal output terminal, and a gate is connected to the pull-down node, and the first power supply terminal is configured to output an invalid level.

12. The shift register unit according to any one of claims 1-11, wherein, The isolation circuit includes: A fourth transistor, a first pole of the fourth transistor is connected to the pull-up node, a second pole is connected to the first node, and a gate is connected to a second power supply terminal.

13. The shift register unit according to claim 12, wherein, The fourth transistor is an N-type transistor, the valid level output by the pull-up node is V1, the voltage of the second power supply terminal is V2, and V2 - V1 is less than the threshold voltage of the fourth transistor.

14. The shift register unit according to any one of claims 1-11, wherein, The shift register unit includes two of the output circuits and two of the isolation circuits.

15. The shift register unit according to any one of claims 1-11, wherein, The shift register unit further includes: A first input circuit, connected to a first signal input terminal and the pull-up node, and the first input circuit is configured to respond to the signal of the first signal input terminal to input a valid level to the pull-up node; A first pull-up circuit, connected to a third power supply terminal, a pull-down node, and a second node, for responding to the valid level of the third power supply terminal to transmit the valid level of the third power supply terminal to the second node, and for responding to the signal of the second node to transmit the valid level of the third power supply terminal to the pull-down node; A first pull-down circuit, connected to the pull-up node, the pull-down node, and the second node, the first pull-down circuit for responding to the signal of the pull-up node to input an invalid level to the second node, and for responding to the signal of the pull-up node to input an invalid level to the pull-down node; A second pull-down circuit, connected to the pull-up node and the pull-down node, the second pull-down circuit for responding to the signal of the pull-down node to input an invalid level to the pull-up node; A first reset circuit, connected to a first reset signal terminal and the pull-up node, for responding to the signal of the first reset signal terminal to input an invalid level to the pull-up node.

16. The shift register unit according to claim 15, wherein, The shift register unit further includes: A second input circuit, connected to the first signal input terminal and the pull-down node, the second input circuit for responding to the signal of the first signal input terminal to input an invalid level to the pull-down node; A cascade circuit, connected to the pull-up node, the pull-down node, a third clock signal terminal, and a cascade output terminal, the cascade circuit for responding to the signal of the pull-up node to transmit the signal of the third clock signal terminal to the cascade output terminal, and for responding to the signal of the pull-down node to input an invalid level to the cascade output terminal; A second reset circuit, connected to a second reset signal terminal and the pull-up node, the second reset circuit for responding to the signal of the second reset signal terminal to input an invalid level to the pull-up node; A first gating circuit, connected to a second signal input terminal, a gating signal terminal, a third node, a fourth clock signal terminal, and the pull-up node, the first gating circuit for responding to the signal of the gating signal terminal to transmit the signal of the second signal input terminal to the third node, and for responding to the signals of the third node and the fourth clock signal terminal to input a valid level to the pull-up node; A second gating circuit, connected to the pull-down node, the third node, the pull-down node, and the fourth clock signal terminal, the second gating circuit for responding to the signals of the third node and the fourth clock signal terminal to input an invalid level to the pull-down node.

17. The shift register unit according to claim 16, wherein, The first input circuit is for responding to the signal of the first signal input terminal to input a valid level to the pull-up node using the first signal input terminal; The first pull-down circuit is further connected to a fourth power supply terminal and a fifth power supply terminal, the first pull-down circuit for responding to the signal of the pull-up node to input an invalid level to the second node using the fifth power supply terminal, and for responding to the signal of the pull-up node to input an invalid level to the pull-down node using the fourth power supply terminal; The second pull-down circuit is further connected to the fourth power supply terminal, the second pull-down circuit for responding to the signal of the pull-down node to input an invalid level to the pull-up node using the fourth power supply terminal; The first reset circuit is also connected to the fourth power supply terminal, and the first reset circuit is configured to input an invalid level to the pull-up node by using the fourth power supply terminal in response to a signal of the first reset signal terminal; The second input circuit is also connected to the fourth power supply terminal, and the second input circuit is configured to input an invalid level to the pull-down node by using the fourth power supply terminal in response to a signal of the first signal input terminal; The cascade circuit is also connected to the fourth power supply terminal, and the cascade circuit is configured to input an invalid level to the cascade output terminal by using the fourth power supply terminal in response to a signal of the pull-down node; The second reset circuit is also connected to the fourth power supply terminal, and the second reset circuit is configured to input an invalid level to the pull-up node by using the fourth power supply terminal in response to a signal of the second reset signal terminal; The first gating circuit is configured to input a valid level to the pull-up node by using the fourth clock signal terminal in response to signals of the third node and the fourth clock signal terminal; The first signal input terminal is multiplexed as the second signal input terminal; The second gating circuit is also connected to the fourth power supply terminal, and the second gating circuit is configured to input an invalid level to the pull-down node by using the fourth power supply terminal in response to signals of the third node and the fourth clock signal terminal.

18. The shift register unit according to claim 17, wherein, The first input circuit includes: A fifth transistor, with its first pole connected to the first signal input terminal, its second pole connected to the fourth node, and its gate connected to the first signal input terminal; A sixth transistor, with its first pole connected to the fourth node, its second pole connected to the pull-up node, and its gate connected to the first signal input terminal; The first pull-up circuit includes: A seventh transistor, with its first pole connected to the third power supply terminal and its gate connected to the third power supply terminal; An eighth transistor, with its first pole connected to the second pole of the seventh transistor, its second pole connected to the second node, and its gate connected to the third power supply terminal; A ninth transistor, with its first pole connected to the third power supply terminal, its second pole connected to the pull-down node, and its gate connected to the second node; The first pull-down circuit includes: A tenth transistor, with its first pole connected to the fifth power supply terminal, its second pole connected to the second node, and its gate connected to the pull-up node; An eleventh transistor, with its first pole connected to the fourth power supply terminal, its second pole connected to the pull-down node, and its gate connected to the pull-up node; The second pull-down circuit includes: A twelfth transistor, with its first pole connected to the pull-up node, its second pole connected to the fifth node, and its gate connected to the pull-down node; A thirteenth transistor, with its first pole connected to the fourth power supply terminal, its second pole connected to the fifth node, and its gate connected to the pull-down node; The second input circuit includes: A fourteenth transistor, with its first pole connected to the fourth power supply terminal, its second pole connected to the pull-down node, and its gate connected to the first signal input terminal; The cascade circuit includes: A fifteenth transistor, with its first pole connected to the third clock signal terminal, its second pole connected to the cascade output terminal, and its gate connected to the pull-up node; A sixteenth transistor, with its first pole connected to the fourth power supply terminal, its second pole connected to the cascade output terminal, and its gate connected to the pull-down node; A second capacitor, with the first electrode connected to the pull-up node and the second electrode connected to the cascaded output terminal; The first reset circuit includes: A seventeenth transistor, with the first pole connected to the pull-up node, the second pole connected to the sixth node, and the gate connected to the first reset signal terminal; An eighteenth transistor, with the first pole connected to the fourth power supply terminal, the second pole connected to the sixth node, and the gate connected to the first reset signal terminal; The second reset circuit includes: A nineteenth transistor, with the first pole connected to the pull-up node, the second pole connected to the seventh node, and the gate connected to the second reset signal terminal; A twentieth transistor, with the first pole connected to the fourth power supply terminal, the second pole connected to the seventh node, and the gate connected to the second reset signal terminal; The first gating circuit includes: A twenty-first transistor, with the first pole connected to the second signal input terminal, the second pole connected to the eighth node, and the gate connected to the gating signal terminal; A twenty-second transistor, with the first pole connected to the eighth node, the second pole connected to the third node, and the gate connected to the gating signal terminal; A twenty-third transistor, with the first pole connected to the fourth clock signal terminal and the gate connected to the third node; A twenty-fourth transistor, with the first pole connected to the second pole of the twenty-third transistor, the second pole connected to the ninth node, and the gate connected to the fourth clock signal terminal; A twenty-fifth transistor, with the first pole connected to the ninth node, the second pole connected to the pull-up node, and the gate connected to the fourth clock signal terminal; A third capacitor, with the first electrode connected to the third node and the second electrode connected to a stable voltage terminal; The second gating circuit includes: A twenty-sixth transistor, with the first pole connected to the pull-down node and the gate connected to the fourth clock signal terminal; A twenty-seventh transistor, with the first pole connected to the second pole of the twenty-sixth transistor, the second pole connected to the fourth power supply terminal, and the gate connected to the third node.

19. The shift register unit according to claim 18, wherein, The shift register unit further includes: A first node control circuit, connected to the pull-up node, the fourth node, the fifth node, the sixth node, the seventh node, and the ninth node, for responding to the signal of the pull-up node to input an effective level to the fourth node, the fifth node, the sixth node, the seventh node, and the ninth node; A second node control circuit, connected to the eighth node and the third node, for responding to the signal of the third node to input an effective level to the eighth node.

20. The shift register unit according to claim 19, wherein, The first node control circuit includes: A twenty-eighth crystal, with the first pole connected to the seventh power supply terminal, the second pole connected to the fourth node, the fifth node, the sixth node, the seventh node, and the ninth node, and the gate connected to the pull-up node; The second node control circuit includes: A twenty-ninth transistor, with the first pole connected to the sixth power supply terminal, the second pole connected to the eighth node, and the gate connected to the third node; The sixth power supply terminal and the seventh power supply terminal are used to output an effective level.

21. A gate driving circuit, wherein, The gate driving circuit includes a plurality of shift register units according to any one of claims 1-20, and a plurality of the shift register units are cascaded.

22. A gate driving circuit, wherein, The gate driving circuit includes a plurality of shift register units according to any one of claims 16-20, and a plurality of the shift register units are cascaded; Among them, the first signal input terminal and the second signal input terminal of the nth-stage shift register unit are connected to the cascaded output terminal of the (n - m)th-stage shift register unit, and the first reset signal terminal of the nth-stage shift register unit is connected to the cascaded output terminal of the (n + p)th-stage shift register unit; Among them, n, m, and p are integers greater than or equal to 1, and n - m is greater than or equal to 1.

23. A display panel, wherein, The display panel includes the gate driving circuit according to claim 21 or 22.

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