Display device and method for driving same

Abstract

The present invention achieves partial driving without causing display failure in a display device provided with a pixel circuit having a configuration in which an N-type transistor and a P-type transistor are mixed.　A first scanning signal line connected to the control terminal of an initialization transistor within a pixel circuit 15 and a second scanning signal line connected to the control terminal of a threshold value compensation transistor within the pixel circuit 15 are driven by mutually different shift registers. A scanning-signal-line-driving circuit drives the first scanning signal line and the second scanning signal line so that the initialization transistor and the threshold value compensation transistor are kept in an OFF state in a pixel circuit included in a row set in a data maintenance row.

Description

Display device and driving method thereof

[0001] The following disclosure relates to a display device using a display element driven by a current and a driving method thereof.

[0002] In recent years, organic EL display devices equipped with pixel circuits containing organic EL elements have been put to practical use. The pixel circuits of organic EL display devices include multiple transistors, such as a drive transistor for controlling the supply of current to the organic EL element and a write control transistor for controlling the writing of data voltages to the pixel circuit. These transistors are typically thin-film transistors (TFTs). However, thin-film transistors are prone to variations in their characteristics. Specifically, variations in threshold voltage are likely to occur. Variations in the threshold voltage of the drive transistors described above result in variations in luminance, thereby degrading display quality. Therefore, various compensation processes (compensation processes) have been proposed to compensate for variations in threshold voltage. Known compensation processes include an internal compensation process, which involves providing a storage capacitor within the pixel circuit to retain information about the threshold voltage of the drive transistor, and an external compensation process, which involves measuring the magnitude of the current flowing through the drive transistor under specified conditions using a circuit external to the pixel circuit and correcting the video signal based on the measurement results.

[0003] As a pixel circuit for an organic EL display device employing an internal compensation method for compensation processing, a pixel circuit has been proposed that combines thin-film transistors (hereinafter referred to as "oxide TFTs") using an oxide semiconductor as the channel layer material and thin-film transistors (hereinafter referred to as "LTPS-TFTs") using low-temperature polysilicon as the channel layer material. This pixel circuit utilizes the advantages of oxide TFTs, such as low leakage current, and LTPS-TFTs, such as high mobility, enabling high-resolution image display with low power consumption. Thin-film transistors (hereinafter referred to as "IGZO-TFTs") containing indium gallium zinc oxide (InGaZnO) are typically used as oxide TFTs. Typically, IGZO-TFTs are N-type transistors, while LTPS-TFTs are P-type transistors. Therefore, pixel circuits that combine oxide TFTs and LTPS-TFTs typically contain a mixture of N-type and P-type transistors.

[0004] In order to effectively reduce power consumption, organic EL display devices equipped with the pixel circuits described above employ a driving method called a "variable refresh rate," which varies the frame rate depending on the type of displayed image. Furthermore, in order to further reduce power consumption, partial driving, which is a driving method that rewrites data for only some rows when refreshing a displayed image, is expected to be realized. Regarding partial driving, it is envisioned that, for example, when a moving image and a still image are displayed simultaneously, data is rewritten only for the moving image portion.

[0005] The following prior art documents are known in relation to this case. U.S. Patent No. 11,049,451 describes, with respect to an organic EL display device, dividing input image data into a plurality of partial image data corresponding to a plurality of partial panel zones, and determining a drive frequency for each partial panel zone. Japanese Patent Application Laid-Open No. 2008-180804 describes, with respect to an organic EL display device, performing partial display updating by enabling only the output of a selection driver in an area set to update the display and supplying data to pixels.

[0006] US Patent No. 11049451 Japanese Patent Application Laid-Open No. 2008-180804

[0007] However, partial driving has not yet been realized for organic EL display devices equipped with pixel circuits configured with a mixture of N-type and P-type transistors. The reason for this is explained below. Note that, hereinafter, with respect to the plurality of pixel circuits that make up a pixel matrix of multiple rows and multiple columns, the pixel circuit located in the i-th row and j-th column will also be referred to as the "i-th row, j-th column pixel circuit."

[0008] 26 shows an example configuration of a pixel circuit 95(i,j) in the ith row and jth column. The pixel circuit 95(i,j) includes an organic EL element OL, seven transistors T1 to T7 (initialization transistor T1, threshold compensation transistor T2, write control transistor T3, drive transistor T4, first light-emission control transistor T5, second light-emission control transistor T6, and reset transistor T7), and a holding capacitor Cst. The transistors T1, T2, and T7 are N-type transistors. The transistors T3 to T6 are P-type transistors.

[0009] FIG. 27 shows the configuration of the main components involved in driving the pixel circuit 95. Note that components for controlling the light emission of the organic EL element OL are omitted. Although a large number of pixel circuits exist in the display section, FIG. 27 schematically shows only the pixel circuit 95(i-1,j) in the (i-1)th row and jth column, the pixel circuit 95(i,j) in the i-th row and jth column, and the pixel circuit 95(i+1,j) in the (i+1)th row and jth column. Each pixel circuit 95 receives an NS signal for controlling the states of the initialization transistor T1 and the threshold compensation transistor T2, and a PS signal for controlling the state of the write control transistor T3. More specifically, the pixel circuit 95(i,j) in the i-th row and j-th column receives an NS signal NS(i-2) for controlling the state of the initialization transistor T1, an NS signal NS(i) for controlling the state of the threshold compensation transistor T2, and a PS signal PS(i) for controlling the state of the write control transistor T3.

[0010] The display includes a first shift register 901L that drives the NS signal line and the PS signal line from the left side of the display, and a second shift register 901R that drives the NS signal line and the PS signal line from the right side of the display. The first shift register 901L is composed of a plurality of unit circuits 9L, and the second shift register 901R is composed of a plurality of unit circuits 9R. Note that the term "unit circuit" used herein refers to a bistable circuit that constitutes each stage of the shift register. The unit circuits 9L and 9R have the same configuration. The first output signal OUT1 output from each unit circuit 9L, 9R is applied as an NS signal to the corresponding NS signal line. More specifically, the first output signal OUT1 output from each unit circuit 9L, 9R is applied to the control terminal of the threshold compensation transistor T2 in the pixel circuit 95 in the corresponding row and to the control terminal of the initialization transistor T1 in the pixel circuit 95 in the row two rows after the corresponding row. The second output signal OUT2 output from each unit circuit 9L, 9R is provided to the corresponding PS signal line as a PS signal. Focusing on the pixel circuit 95(i,j) in the ith row and jth column in FIG. 27 , for example, the NS signal NS(i-2), the NS signal NS(i), and the PS signal PS(i) are all provided from both the first shift register 901L and the second shift register 901R. Note that, in a case where pause driving (a driving method that provides a period during which the writing operation of data voltages to pixel circuits is stopped) is employed, the control signals GVDDL and GVDDR are used to distinguish between write frames in which data voltages are written and pause frames in which data voltages are not written.

[0011] Fig. 28 shows ideal waveforms when partial driving is performed with the above configuration to prevent data rewriting only in the i-th row. Note that in Fig. 28, the signals denoted by reference numerals 991, 992, 993, 994, and 995 are signals provided to the pixel circuits 95 in the (i-2)th, (i-1)th, i-th, (i+1)th, and (i+2)th rows, respectively (the same applies to Fig. 29). If the pixel circuits 95 were driven based on signals having waveforms such as those shown in Fig. 28, the pixel circuits 95 in rows other than the i-th row would be initialized (the voltage at the control terminal of the drive transistor T4 would be initialized), and then a data voltage would be written to each pixel circuit 95 while performing internal compensation.

[0012] However, in reality, when an organic EL display device is operated so that data rewriting is not performed only in the i-th row by controlling the waveforms of the control signals GVDDL and GVDDR, waveform changes such as those shown in FIG. 29 appear for the NS signal and PS signal. Comparing FIG. 28 with FIG. 29 reveals the following: In the (i-2)th row, initialization is performed, but data voltage is not written to the pixel circuits 95 because the NS signal NS(i-2) is maintained at a low level. In the (i-1)th row, initialization is insufficient because the NS signal NS(i-3) is maintained at a high level for a short period of time, and data voltage is not written to the pixel circuits 95 because the NS signal NS(i-1) is maintained at a low level. In the (i+1)th and (i+2)th rows, data voltage is written to the pixel circuits 95, but initialization is not performed, which may result in insufficient display quality. As described above, display defects are caused.

[0013] Therefore, the following disclosure aims to achieve partial driving without causing display defects in a display device (a display device using display elements driven by current) that has a pixel circuit configured with a mixture of N-type transistors and P-type transistors.

[0014] A display device according to some embodiments of the present disclosure is a display device using a display element driven by a current, comprising: a display section including a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of third scanning signal lines, a plurality of light emission control lines, an initialization power supply line that supplies an initialization voltage, and a plurality of pixel circuits that form a pixel matrix of a plurality of rows and a plurality of columns; a data side drive circuit that applies a data voltage to the plurality of data signal lines; a light emission control circuit that selectively drives the plurality of light emission control lines; and a scan side drive circuit that includes a plurality of shift registers and is composed of a scan signal line drive circuit that selectively drives the plurality of first scanning signal lines, the plurality of second scanning signal lines, and the plurality of third scanning signal lines, each of the plurality of pixel circuits corresponding to one of the plurality of data signal lines, one of the plurality of first scanning signal lines, one of the plurality of second scanning signal lines, one of the plurality of third scanning signal lines, and one of the plurality of light emission control lines; a drive transistor having a control terminal, a first conduction terminal, and a second conduction terminal, and arranged in series with the display element; a storage capacitor having one end connected to the control terminal of the drive transistor; an initialization transistor as a switching element, having a control terminal connected to a corresponding first scanning signal line, a first conduction terminal connected to the initialization power supply line, and a second conduction terminal connected to the control terminal of the drive transistor; a threshold compensation transistor as a switching element, having a control terminal connected to a corresponding second scanning signal line, a first conduction terminal connected to the first conduction terminal of the drive transistor, and a second conduction terminal connected to the control terminal of the drive transistor; a write control transistor as a switching element, having a control terminal connected to a corresponding third scanning signal line, a first conduction terminal connected to the second conduction terminal of the drive transistor, and a second conduction terminal connected to a corresponding data signal line; and at least one emission control transistor as a switching element, having a control terminal connected to a corresponding emission control line, and arranged in series with the display element and the drive transistor, wherein the initialization transistor and the threshold compensation transistor are N-type transistors,the write control transistor is a P-type transistor; the plurality of first scanning signal lines and the plurality of second scanning signal lines are driven by different shift registers included in the scanning signal line drive circuit; and for each frame period, each row of the pixel matrix is ​​set as either a data update row in which the data voltage is written to the pixel circuit or a data maintenance row in which the data voltage is not written to the pixel circuit; and the scanning signal line drive circuit drives the plurality of first scanning signal lines, the plurality of second scanning signal lines, and the plurality of third scanning signal lines so that, in each frame period, in pixel circuits included in rows set as the data update rows, the initialization transistor is maintained in an on state for a first predetermined period during a period in which the write control transistor and the threshold compensation transistor are maintained in an off state, and then the threshold compensation transistor is maintained in an on state for a second predetermined period and the write control transistor is maintained in an on state for a third predetermined period that is a part of the second predetermined period; and so that, in pixel circuits included in rows set as the data maintenance rows, the initialization transistor and the threshold compensation transistor are maintained in an off state.

[0015] A driving method (of a display device) according to some embodiments of the present disclosure is a driving method of a display device using a display element driven by a current, the display device comprising: a display unit including a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of third scanning signal lines, a plurality of light emission control lines, an initialization power supply line that supplies an initialization voltage, and a plurality of pixel circuits that form a pixel matrix of a plurality of rows and a plurality of columns; a data side driving circuit that applies a data voltage to the plurality of data signal lines; a light emission control circuit that selectively drives the plurality of light emission control lines; and a scanning side driving circuit that includes a plurality of shift registers and is composed of a scanning signal line driving circuit that selectively drives the plurality of first scanning signal lines, the plurality of second scanning signal lines, and the plurality of third scanning signal lines, each of the plurality of pixel circuits corresponding to one of the plurality of data signal lines, one of the plurality of first scanning signal lines, one of the plurality of second scanning signal lines, one of the plurality of third scanning signal lines, and one of the plurality of light emission control lines, a drive transistor having a control terminal, a first conduction terminal, and a second conduction terminal, and arranged in series with the display element; a storage capacitor having one end connected to the control terminal of the drive transistor; an initialization transistor as a switching element, having a control terminal connected to a corresponding first scanning signal line, a first conduction terminal connected to the initialization power supply line, and a second conduction terminal connected to the control terminal of the drive transistor; a threshold compensation transistor as a switching element, having a control terminal connected to a corresponding second scanning signal line, a first conduction terminal connected to the first conduction terminal of the drive transistor, and a second conduction terminal connected to the control terminal of the drive transistor; a write control transistor as a switching element, having a control terminal connected to a corresponding third scanning signal line, a first conduction terminal connected to the second conduction terminal of the drive transistor, and a second conduction terminal connected to a corresponding data signal line; and at least one emission control transistor as a switching element, having a control terminal connected to a corresponding emission control line, and arranged in series with the display element and the drive transistor,the initialization transistor and the threshold compensation transistor are N-type transistors, the write control transistor is a P-type transistor, the plurality of first scanning signal lines and the plurality of second scanning signal lines are driven by different shift registers included in the scanning signal line drive circuit, and the driving method comprises: a write setting step of setting, for each frame period, each row of the pixel matrix to either a data update row in which the data voltage is written to a pixel circuit or a data maintenance row in which the data voltage is not written to a pixel circuit; and a scanning signal line driving step of driving the plurality of first scanning signal lines, the plurality of second scanning signal lines, and the plurality of third scanning signal lines so that, in each frame period, in pixel circuits included in a row set to the data update row in the write setting step, during a period in which the write control transistor and the threshold compensation transistor are maintained in an off state, the initialization transistor is maintained in an on state for a first predetermined period, and then the threshold compensation transistor is maintained in an on state for a second predetermined period and the write control transistor is maintained in an on state for a third predetermined period that is a part of the second predetermined period, and so that, in pixel circuits included in a row set to the data maintenance row in the write setting step, the initialization transistor and the threshold compensation transistor are maintained in an off state.

[0016] According to some embodiments of the present disclosure, each row of a pixel matrix is ​​set as either a data update row in which a data voltage is written or a data maintenance row in which a data voltage is not written. The scanning signal line drive circuit drives a first scanning signal line connected to a control terminal of the initialization transistor and a second scanning signal line connected to a control terminal of the threshold compensation transistor so that the initialization transistor and the threshold compensation transistor are maintained in an off state in pixel circuits included in the data maintenance row. Here, the first scanning signal line and the second scanning signal line are driven by different shift registers. Therefore, the first scanning signal line and the second scanning signal line can be driven so that a data voltage is not written in the data maintenance row without affecting the operation of the pixel circuits included in the data update row. As a result, partial driving can be achieved without causing display defects in a display device including pixel circuits configured with a mixture of N-type and P-type transistors.

[0017] 1 is a diagram for explaining the relationship between first to third scanning signals given to a pixel circuit and a unit circuit in one embodiment. FIG. 2 is a block diagram showing the overall configuration of a display device according to the embodiment. FIG. 3 is a circuit diagram showing the configuration of a pixel circuit in the embodiment. FIG. 4 is a timing chart showing the operation of a pixel circuit in the embodiment. FIG. 5 is a block diagram showing a schematic configuration of a scanning side drive circuit in the embodiment. FIG. 6 is a block diagram showing the configuration of a first scanning signal line drive circuit in the embodiment. FIG. 7 is a block diagram showing the configuration of a second scanning signal line drive circuit in the embodiment. FIG. 8 is a circuit diagram showing the configuration of a unit circuit in the embodiment. FIG. 9 is a timing chart showing the operation of a unit circuit corresponding to a data update row in the embodiment. FIG. 10 is a timing chart showing the operation of a unit circuit corresponding to a data maintenance row in the embodiment. FIG. 11 is a timing chart showing the overall operation when normal drive is performed in the embodiment. FIG. 12 is a timing chart showing the overall operation when partial drive is performed in the embodiment. FIG. 13 is a timing chart showing the overall operation when partial drive is performed in the first modified example of the embodiment. FIG. 14 is a timing chart showing the overall operation when partial drive is performed in the second modified example of the embodiment. FIG. 15 is a diagram for explaining a configuration for realizing a driving method of the second modified example. FIG. 16 is a diagram for explaining the operation when an enable signal is at a high level in the second modified example. FIG. 1 is a diagram for explaining the operation when the enable signal is at a low level in the second modified example. FIG. 2 is a circuit diagram showing the configuration of a unit circuit in a third modified example of the embodiment. FIG. 3 is a timing chart for explaining the operation of the unit circuit in the third modified example. FIG. 4 is a circuit diagram showing the configuration of a unit circuit in a fourth modified example of the embodiment. FIG. 5 is a timing chart for explaining the operation of the unit circuit in the fourth modified example. FIG. 6 is a circuit diagram showing the configuration of a unit circuit in a fifth modified example of the embodiment. FIG. 7 is a timing chart for explaining the operation of the unit circuit in the fifth modified example.Fig. 10 is a circuit diagram showing the configuration of a unit circuit in a sixth modified example of the embodiment. Fig. 11 is a timing chart for explaining the operation of the unit circuit in the sixth modified example. Fig. 12 is a circuit diagram showing an example of the configuration of a pixel circuit in which N-type transistors and P-type transistors are mixed. Fig. 13 is a diagram showing an example of the configuration of a main part related to driving of a pixel circuit. Fig. 14 is a diagram showing ideal signal waveforms when partial driving is performed with a conventional configuration. Fig. 15 is a diagram showing signal waveforms that actually appear when an organic EL display device with a conventional configuration is operated so that data is not rewritten only for some rows.

[0018] An embodiment will now be described with reference to the accompanying drawings. In the following, it is assumed that i and j are integers equal to or greater than 2. A low level corresponds to a first logic level, and a high level corresponds to a second logic level.

[0019] 2 is a block diagram showing the overall configuration of a display device 10 according to one embodiment. This display device 10 is an organic EL display device that performs internal compensation. That is, in this display device 10, each pixel circuit 15 has a function of compensating for variations and fluctuations in the threshold voltage of its internal drive transistor. Furthermore, this display device 10 is capable of partial driving, in which data is rewritten only for some rows of a pixel matrix of multiple rows and multiple columns when refreshing a displayed image.

[0020] As shown in FIG. 2 , the display device 10 includes a display unit 11, a display control circuit 20, a data-side drive circuit 30, a scanning-side drive circuit 40, and a power supply circuit 50. The data-side drive circuit 30 functions as a data signal line drive circuit (source driver). The scanning-side drive circuit 40 functions as a scan signal line drive circuit (gate driver) and a light-emitting control circuit (emission driver). The scanning-side drive circuit 40 is composed of a first scanning-side drive circuit 40L located to the left of the display unit 11 in FIG. 2 and a second scanning-side drive circuit 40R located to the right of the display unit 11 in FIG. 2 . At least a portion of the data-side drive circuit 30 and the scanning-side drive circuit 40 may be formed integrally with the display unit 11. The power supply circuit 50 generates a high-level power supply voltage ELVDD, a low-level power supply voltage ELVSS, and an initialization voltage Vini to be supplied to the display unit 11, as well as power supply voltages (not shown) to be supplied to the display control circuit 20, the data-side drive circuit 30, and the scanning-side drive circuit 40.

[0021] The display unit 11 is provided with m (m is an integer of 2 or greater) data signal lines D(1) to D(m), and n (n is an integer of 2 or greater) first scanning signal lines NSL(-1) to NSL(n-2), n second scanning signal lines NSR(1) to NSR(n), n third scanning signal lines PS(1) to PS(n), and n light-emission control lines EM(1) to EM(n) that intersect with the data signal lines D(1) to D(m). The display unit 11 also has n×m pixel circuits 15. These n×m pixel circuits 15 form a pixel matrix of n rows and m columns. Each of the n×m pixel circuits 15 corresponds to one of the m data signal lines D(1) to D(m), one of the n first scanning signal lines NSL(-1) to NSL(n-2), one of the n second scanning signal lines NSR(1) to NSR(n), one of the n third scanning signal lines PS(1) to PS(n), and one of the n light emission control lines EM(1) to EM(n). Hereinafter, as necessary, the data signals respectively supplied to the data signal lines D(1) to D(m) will also be assigned the symbols D(1) to D(m), the first scanning signals respectively supplied to the first scanning signal lines NSL(-1) to NSL(n-2) will also be assigned the symbols NSL(-1) to NSL(n-2), the second scanning signals respectively supplied to the second scanning signal lines NSR(1) to NSR(n) will also be assigned the symbols NSR(1) to NSR(n), the third scanning signals respectively supplied to the third scanning signal lines PS(1) to PS(n) will also be assigned the symbols PS(1) to PS(n), and the light emission control signals respectively supplied to the light emission control lines EM(1) to EM(n) will also be assigned the symbols EM(1) to EM(n).

[0022] Furthermore, the display unit 11 is provided with power supply lines (not shown) that are common to each pixel circuit 15. More specifically, a power supply line (hereinafter referred to as a "high-level power supply line") that supplies a high-level power supply voltage ELVDD for driving the organic EL elements, a power supply line (hereinafter referred to as a "low-level power supply line") that supplies a low-level power supply voltage ELVSS for driving the organic EL elements, and a power supply line (hereinafter referred to as an "initialization power supply line") that supplies an initialization voltage Vini for initializing each pixel circuit 15 are provided. The low-level power supply line corresponds to the first power supply line, and the high-level power supply line corresponds to the second power supply line.

[0023] The display control circuit 20 receives an input signal Sin from outside the display device 10, the input signal Sin including image information representing an image to be displayed and timing control information for image display, and outputs a data control signal Scd that controls the operation of the data drive circuit 30 and a scanning control signal Scs that controls the operation of the scanning drive circuit 40. The data drive circuit 30 applies data signals to the data signal lines D(1) to D(m) based on the data control signal Scd output from the display control circuit 20. The scanning drive circuit 40 applies a first scanning signal to the first scanning signal lines NSL(-1) to NSL(n-2), a second scanning signal to the second scanning signal lines NSR(1) to NSR(n), a third scanning signal to the third scanning signal lines PS(1) to PS(n), and a light-emission control signal to the light-emission control lines EM(1) to EM(n), based on the scanning control signal Scs output from the display control circuit 20.

[0024] As described above, a data signal is applied to the data signal lines D(1) to D(m), a first scanning signal is applied to the first scanning signal lines NSL(-1) to NSL(n-2), a second scanning signal is applied to the second scanning signal lines NSR(1) to NSR(n), a third scanning signal is applied to the third scanning signal lines PS(1) to PS(n), and a light emission control signal is applied to the light emission control lines EM1(1) to EM1(n), whereby an image based on the input signal Sin is displayed on the display unit 11.

[0025] 3 is a circuit diagram showing the configuration of pixel circuit 15 in this embodiment. Note that attention is focused here on pixel circuit 15(i,j) corresponding to third scanning signal line PS(i) and data signal line D(j) (i.e., pixel circuit in the i-th row and j-th column). The configuration of pixel circuit 15 shown here is an example and is not limited to this.

[0026] The pixel circuit 15(i,j) is connected to the first scanning signal line NSL(i-2), the second scanning signal line NSR(i), the third scanning signal line PS(i), the light-emitting control line EM(i), the data signal line D(j), the high-level power supply line, the low-level power supply line, and the initialization power supply line. Hereinafter, when focusing on the pixel circuit 15(i,j) in the i-th row and j-th column, the first scanning signal line NSL(i-2) will also be referred to as the "corresponding first scanning signal line," the second scanning signal line NSR(i) will also be referred to as the "corresponding second scanning signal line," the third scanning signal line PS(i) will also be referred to as the "corresponding third scanning signal line," the light-emitting control line EM(i) will also be referred to as the "corresponding light-emitting control line," and the data signal line D(j) will also be referred to as the "corresponding data signal line."

[0027] Each pixel circuit 15(i,j) includes one organic EL element (organic light-emitting diode) OL as a display element, seven transistors (typically thin-film transistors) T1 to T7 (initialization transistor T1, threshold compensation transistor T2, write control transistor T3, drive transistor T4, first light-emission control transistor T5, second light-emission control transistor T6, and reset transistor T7), and one storage capacitor Cst. The transistors T1, T2, and T7 are N-type transistors. The transistors T3 to T6 are P-type transistors. The N-type transistors T1, T2, and T7 are, for example, IGZO-TFTs, and the P-type transistors T3 to T6 are, for example, LTPS-TFTs. However, this is not a limitation. The storage capacitor Cst is a capacitive element consisting of two electrodes (a first electrode and a second electrode). As can be seen from FIG. 3, the first light-emission control transistor T5, the drive transistor T4, the second light-emission control transistor T6, and the organic EL element OL are arranged in series. In the pixel circuit 15(i, j), the transistors T1 to T3 and T5 to T7 other than the drive transistor T4 function as switching elements.

[0028] The initialization transistor T1 has a control terminal connected to the corresponding first scanning signal line NSL(i-2), a first conduction terminal connected to the second conduction terminal of the threshold compensation transistor T2, the control terminal of the drive transistor T4, and the second electrode of the hold capacitor Cst, and a second conduction terminal connected to the initialization power supply line. The threshold compensation transistor T2 has a control terminal connected to the corresponding second scanning signal line NSR(i), a first conduction terminal connected to the first conduction terminal of the drive transistor T4 and the second conduction terminal of the second light-emitting control transistor T6, and a second conduction terminal connected to the first conduction terminal of the initialization transistor T1, the control terminal of the drive transistor T4, and the second electrode of the hold capacitor Cst. The write control transistor T3 has a control terminal connected to the corresponding third scanning signal line PS(i), a first conduction terminal connected to the second conduction terminal of the drive transistor T4 and the first conduction terminal of the first light-emitting control transistor T5, and a second conduction terminal connected to the corresponding data signal line D(j). As for the driving transistor T4, the control terminal is connected to the first conduction terminal of the initialization transistor T1, the second conduction terminal of the threshold compensation transistor T2, and the second electrode of the holding capacitor Cst, the first conduction terminal is connected to the first conduction terminal of the threshold compensation transistor T2 and the second conduction terminal of the second light-emitting control transistor T6, and the second conduction terminal is connected to the first conduction terminal of the write control transistor T3 and the first conduction terminal of the first light-emitting control transistor T5.

[0029] The first light-emitting control transistor T5 has a control terminal connected to the corresponding light-emitting control line EM(i), a first conduction terminal connected to the first conduction terminal of the write control transistor T3 and the second conduction terminal of the drive transistor T4, and a second conduction terminal connected to the high-level power supply line. The second light-emitting control transistor T6 has a control terminal connected to the corresponding light-emitting control line EM(i), a first conduction terminal connected to the first conduction terminal of the reset transistor T7 and the anode electrode of the organic EL element OL, and a second conduction terminal connected to the first conduction terminal of the threshold compensation transistor T2 and the first conduction terminal of the drive transistor T4. The reset transistor T7 has a control terminal connected to the corresponding light-emitting control line EM(i), a first conduction terminal connected to the first conduction terminal of the second light-emitting control transistor T6 and the anode electrode of the organic EL element OL, and a second conduction terminal connected to the initialization power supply line.

[0030] The first electrode of the storage capacitor Cst is connected to the high-level power supply line, and the second electrode is connected to the first conduction terminal of the initialization transistor T1, the second conduction terminal of the threshold compensation transistor T2, and the control terminal of the drive transistor T4. The anode electrode of the organic EL element OL is connected to the first conduction terminal of the second light-emission control transistor T6 and the first conduction terminal of the reset transistor T7, and the cathode electrode is connected to the low-level power supply line.

[0031] Next, the operation of the pixel circuit 15(i,j) in the i-th row and j-th column will be described with reference to the timing chart shown in Figure 4. Just before time t1, the light-emission control signal EM(i) is at a low level, and the first light-emission control transistor T5 and the second light-emission control transistor T6 are in an on state. Therefore, a current flows through the organic EL element OL, and the pixel circuit 15(i,j) is in an emitting state.

[0032] When the light-emission control signal EM(i) changes from low to high at time t1, the first light-emission control transistor T5 and the second light-emission control transistor T6 change from an on state to an off state. While the light-emission control signal EM(i) is maintained at a high level, the first light-emission control transistor T5 and the second light-emission control transistor T6 are maintained in an off state. Therefore, during periods t1 to t8, no current flows through the organic EL element OL, and the pixel circuit 15(i,j) is in a non-light-emitting state. Furthermore, during periods t1 to t8 when the pixel circuit 15(i,j) is in a non-light-emitting state (non-light-emitting period), the reset transistor T7 is maintained in an on state, thereby initializing the anode voltage of the organic EL element OL.

[0033] When the first scanning signal NSL(i-2) changes from low to high at time t2, the initialization transistor T1 changes from off to on. While the first scanning signal NSL(i-2) is maintained at high level, the initialization transistor T1 is maintained in the on state. During the period (initialization period) t2 to t3 when the initialization transistor T1 is in the on state, the holding capacitor Cst is initialized, and the voltage Vg (hereinafter referred to as the "gate voltage") of the control terminal (gate terminal) of the drive transistor T4 becomes the initialization voltage Vini.

[0034] After the first scanning signal NSL(i-2) changes from high to low at time t3, the second scanning signal NSR(i) changes from low to high at time t4. This causes the threshold compensation transistor T2 to change from an off state to an on state. While the second scanning signal NSR(i) is maintained at a high level, the threshold compensation transistor T2 is maintained in an on state, and the drive transistor T4 is in a diode-connected state.

[0035] When the third scanning signal PS(i) changes from high to low at time t5, the write control transistor T3 changes from an off state to an on state. While the third scanning signal PS(i) is maintained at a low level, the write control transistor T3 is maintained in an on state. During the period from t5 to t6 when the write control transistor T3 is in an on state (hereinafter referred to as the "data write period"), the voltage of the data signal D(j) is applied as a data voltage to the holding capacitor Cst via the diode-connected driving transistor T4. As a result, the threshold-compensated data voltage is written to the holding capacitor Cst, and the gate voltage Vg (the voltage at the control terminal of the driving transistor T4) is maintained at the voltage of the second electrode of the holding capacitor Cst. If the data voltage is represented by Vdata and the threshold voltage of the driving transistor T4 is represented by Vth (<0), the gate voltage Vg at this time is expressed by the following equation (1): Vg=Vdata+Vth (1) In this way, during the data writing period t5 to t6, the data voltage is written to the pixel circuit 15(i, j) while performing internal compensation.

[0036] When the second scanning signal NSR(i) changes from high to low at time t7, the threshold compensation transistor T2 changes from on to off. When the light-emission control signal EM(i) changes from high to low at time t8, the first light-emission control transistor T5 and the second light-emission control transistor T6 change from off to on. This starts the light-emission period.

[0037] 5 is a block diagram showing a schematic configuration of the scanning side driving circuit 40 in this embodiment. As described above, the scanning side driving circuit 40 is made up of a first scanning side driving circuit 40L and a second scanning side driving circuit 40R. The first scanning side driving circuit 40L includes a first shift register 401L and a third shift register 409L. The second scanning side driving circuit 40R includes a second shift register 401R and a fourth shift register 409R.

[0038] The first shift register 401L applies a first scanning signal to the first scanning signal lines NSL(-1) to NSL(n-2) and applies a third scanning signal to the third scanning signal lines PS(1) to PS(n). The second shift register 401R applies a second scanning signal to the second scanning signal lines NSR(1) to NSR(n) and applies a third scanning signal to the third scanning signal lines PS(1) to PS(n). In this way, the first shift register 401L and the second shift register 401R constitute a scanning signal line drive circuit (gate driver).

[0039] The third shift register 409L and the fourth shift register 409R apply light emission control signals to the light emission control lines EM(1) to EM(n), respectively. In this manner, the third shift register 409L and the fourth shift register 409R constitute a light emission control circuit (emission driver).

[0040] <3.2 Scanning Signal Line Drive Circuit> The configuration of the scanning signal line drive circuit (first shift register 401L and second shift register 401R) will be described in detail. Note that, since a known configuration can be adopted for the light emission control circuit (third shift register 409L and fourth shift register 409R), detailed description of the configuration of the light emission control circuit will be omitted.

[0041] <3.2.1 First Shift Register> Figure 6 is a block diagram showing the configuration of the first shift register 401L. The first shift register 401L is composed of a plurality of unit circuits 4L. Note that, assuming that i is an even number, Figure 6 only shows the unit circuits 4L(i-2), 4L(i-1), 4L(i), 4L(i+1), and 4L(i+2) in the (i-2)th, (i-1)th, i-th, (i+1)th, and (i+2)th stages.

[0042] The first shift register 401L receives a gate start pulse signal and two-phase clock signals (first gate clock signal GCK1 and second gate clock signal GCK2) as scanning-side control signals Scs sent from the display control circuit 20 to control the first shift register 401L. A gate low voltage VGL and a gate high voltage VGH are also supplied to the first shift register 401L. The gate low voltage VGL is a voltage level that turns N-type transistors off and P-type transistors on. The gate high voltage VGH is a voltage level that turns N-type transistors on and P-type transistors off. Furthermore, update control signals GVDDL1 and GVDDL2 for controlling the rewriting (updating) of data for each row during partial driving are also supplied to the first shift register 401L. The gate start pulse signal is a signal that is supplied as a set signal S to the −1st-stage unit circuit 4L(−1) and is omitted from FIG. 6 . The first gate clock signal GCK1 corresponds to the first clock signal, and the second gate clock signal GCK2 corresponds to the second clock signal.

[0043] Each unit circuit 4L includes input terminals for respectively receiving the first control clock signal CK1, the second control clock signal CK2, the mode signal VM, the gate high voltage VGH, the gate low voltage VGL, and the set signal S, and output terminals for respectively outputting the first output signal OUT1 and the second output signal OUT2. The first output signal OUT1 is a signal for controlling the state of the N-type transistor in the pixel circuit 15, and the second output signal OUT2 is a signal for controlling the state of the P-type transistor in the pixel circuit 15.

[0044] For the even-numbered unit circuits 4L, the first gate clock signal GCK1 is applied as the first control clock signal CK1, the second gate clock signal GCK2 is applied as the second control clock signal CK2, and the update control signal GVDDL2 is applied as the mode signal VM. For the odd-numbered unit circuits 4L, the second gate clock signal GCK2 is applied as the first control clock signal CK1, the first gate clock signal GCK1 is applied as the second control clock signal CK2, and the update control signal GVDDL1 is applied as the mode signal VM. The gate high voltage VGH and the gate low voltage VGL are applied in common to all the unit circuits 4L. Furthermore, the second output signal OUT2 output from the previous unit circuit 4L is applied as the set signal S to the unit circuit 4L of each stage. The first output signal OUT1 output from the unit circuit 4L of each stage is applied to the corresponding first scanning signal line NSL as the first scanning signal. The second output signal OUT2 output from the unit circuit 4L of each stage is given as a set signal S to the unit circuit 4L of the next stage, and is given as a third scanning signal to the corresponding third scanning signal line PS.

[0045] <3.2.2 Second Shift Register> Figure 7 is a block diagram showing the configuration of the second shift register 401R. The second shift register 401R is composed of a plurality of unit circuits 4R. Note that, assuming that i is an even number, Figure 7 shows only the unit circuits 4R(i-2), 4R(i-1), 4R(i), 4R(i+1), and 4R(i+2) in the (i-2)th, (i-1)th, i-th, (i+1)th, and (i+2)th stages.

[0046] 6 and 7, the second shift register 401R has a configuration substantially similar to that of the first shift register 401L. However, the first output signal OUT1 output from each unit circuit 4R is provided to the corresponding second scanning signal line NSR as a second scanning signal. Furthermore, an update control signal GVDDR1 or GVDDR2 is provided to each unit circuit 4R. The unit circuit 4L corresponds to the first unit circuit, and the unit circuit 4R corresponds to the second unit circuit.

[0047] Hereinafter, when there is no need to distinguish between the (n+2) unit circuits 4L(-1) to 4L(n) included in the first shift register 401L and the n unit circuits 4R(1) to 4R(n) included in the second shift register 401R, the unit circuits will be denoted by the symbol 4.

[0048] 1, the relationship between the first to third scanning signals provided to the pixel circuit 15 and the unit circuit 4 will be described. Here, attention is focused on the pixel circuit 15(i,j) in the i-th row and j-th column. The first output signal OUT1 output from the unit circuit 4L(i-2) included in the first shift register 401L is provided to the pixel circuit 15(i,j) as the first scanning signal NSL(i-2). The first output signal OUT1 output from the unit circuit 4R(i) included in the second shift register 401R is provided to the pixel circuit 15(i,j) as the second scanning signal NSR(i). The second output signal OUT2 output from the unit circuit 4L(i) included in the first shift register 401L and the second output signal OUT2 output from the unit circuit 4R(i) included in the second shift register 401R are supplied to the pixel circuit 15(i,j) as the third scanning signal PS(i). In this way, to each pixel circuit 15, the first scanning signal NSL is supplied from the first shift register 401L, the second scanning signal NSR is supplied from the second shift register 401R, and the third scanning signal PS is supplied from the first shift register 401L and the second shift register 401R.

[0049] <3.2.4 Unit Circuit> FIG. 8 is a circuit diagram showing the configuration of a unit circuit 4 in this embodiment. As shown in FIG. 8, the unit circuit 4 includes seven transistors M1 to M7 and one capacitor C1. The transistors M1 to M4 and M6 are P-type transistors, and the transistors M5 and M7 are N-type transistors. The unit circuit 4 also includes an input terminal to which a gate low voltage VGL is applied and an input terminal to which a gate high voltage VGH is applied, as well as four input terminals 41 to 44 and two output terminals 48 and 49. In FIG. 8, the input terminal for receiving the set signal S is labeled 41, the input terminal for receiving the first control clock signal CK1 is labeled 42, the input terminal for receiving the second control clock signal CK2 is labeled 43, the input terminal for receiving the mode signal VM is labeled 44, the output terminal for outputting the first output signal OUT1 is labeled 48, and the output terminal for outputting the second output signal OUT2 is labeled 49. The output control clock signal is realized by the second control clock signal CK2 supplied to the input terminal 43. Note that, hereinafter, the output terminal for outputting the first output signal OUT1 will be referred to as the "first output terminal," and the output terminal for outputting the second output signal OUT2 will be referred to as the "second output terminal."

[0050] The control terminal of transistor M1, the second conduction terminal of transistor M3, the control terminal of transistor M4, the control terminal of transistor M5, the control terminal of transistor M6, the control terminal of transistor M7, and one end of capacitor C1 are connected to one another. The node where these are connected to one another is called a "first internal node." The first internal node is denoted by the symbol N1. The second conduction terminal of transistor M6, the first conduction terminal of transistor M7, and the control terminal of transistor M2 are connected to one another. The node where these are connected to one another is called a "second internal node." The second internal node is denoted by the symbol N2.

[0051] The unit circuit 4 includes a first control circuit 411 that controls the voltage of a first internal node N1, a first output circuit 423 that controls the output of a first output signal OUT1, a second control circuit 421 that controls the voltage of a second internal node N2, and a second output circuit 422 that controls the output of a second output signal OUT2. The first control circuit 411 includes a transistor M3. The second control circuit 421 includes a transistor M6 and a transistor M7. The first output circuit 423 includes a transistor M4 and a transistor M5. The second output circuit 422 includes a transistor M1, a transistor M2, and a capacitor C1.

[0052] For transistor M1, the control terminal is connected to the first internal node N1, the first conduction terminal is connected to the input terminal 43, and the second conduction terminal is connected to the second output terminal 49. For transistor M2, the control terminal is connected to the second internal node N2, the first conduction terminal is connected to the input terminal for the gate high voltage VGH, and the second conduction terminal is connected to the second output terminal 49. For transistor M3, the control terminal is connected to the input terminal 42, the first conduction terminal is connected to the input terminal 41, and the second conduction terminal is connected to the first internal node N1. For transistor M4, the control terminal is connected to the first internal node N1, the first conduction terminal is connected to the input terminal 44, and the second conduction terminal is connected to the first output terminal 48. For transistor M5, the control terminal is connected to the first internal node N1, the first conduction terminal is connected to the first output terminal 48, and the second conduction terminal is connected to the input terminal for the gate low voltage VGL. The transistor M6 has a control terminal connected to the first internal node N1, a first conduction terminal connected to the input terminal for the gate high voltage VGH, and a second conduction terminal connected to the second internal node N2. The transistor M7 has a control terminal connected to the first internal node N1, a first conduction terminal connected to the second internal node N2, and a second conduction terminal connected to the input terminal for the gate low voltage VGL. The capacitor C1 has one end connected to the first internal node N1 and the other end connected to the second output terminal 49.

[0053] 4. Driving Method Next, a driving method when partial driving is performed in the display device 10 according to this embodiment will be described. For convenience, a row that is the target of data rewriting is referred to as a "data update row," and a row that is not the target of data rewriting is referred to as a "data maintenance row." In this embodiment, for each frame period, each row of the pixel matrix is ​​set as either a data update row in which a data voltage is written to the pixel circuit 15, or a data maintenance row in which a data voltage is not written to the pixel circuit 15. For example, when a moving image and a still image are displayed simultaneously, a row corresponding to the moving image portion is set as a data update row, and a row corresponding to the still image portion is set as a data maintenance row.

[0054] 9, the operation of the unit circuit 4 corresponding to the data update row (operation in a period around the time when the set signal S becomes active) will be described. During the period before time t11, the voltage of the first internal node N1 is maintained at a high level, the voltage of the second internal node N2 is maintained at a low level, the first output signal OUT1 is maintained at a low level, and the second output signal OUT2 is maintained at a high level. Note that since the voltage of the second internal node N2 is maintained at a low level, the transistor M2 is maintained in an on state.

[0055] At time t11, the first control clock signal CK1 changes from high to low. This turns on transistor M3. Also at time t11, the set signal S changes from high to low. This causes the voltage at the first internal node N1 to drop to low, turning on transistors M1, M4, and M6 and turning off transistors M5 and M7. With transistor M6 turned on and transistor M7 turned off, the voltage at the second internal node N2 changes from low to high. Furthermore, since the mode signal VM is maintained at high, transistor M4 turns on and transistor M5 turns off, causing the first output signal OUT1 to change from low to high.

[0056] At time t12, the first control clock signal CK1 changes from low to high, turning off the transistor M3. Also at time t12, the set signal S changes from low to high.

[0057] At time t13, the second control clock signal CK2 changes from high to low. At this time, because the transistor M1 is in the ON state, the voltage at the input terminal 43 drops, and the voltage at the second output terminal 49 (the voltage of the second output signal OUT2) drops. Because the capacitor C1 is provided between the first internal node N1 and the second output terminal 49, the voltage at the first internal node N1 also drops as the voltage at the second output terminal 49 drops (the first internal node N1 is in a boosted state). As a result, a large negative voltage is applied to the control terminal of the transistor M1, and the voltage of the second output signal OUT2 drops to a level sufficient to turn on the write control transistor T3 connected to the second output terminal 49.

[0058] At time t14, the second control clock signal CK2 changes from low to high, causing the voltage at the input terminal 43 to rise, and the voltage at the second output terminal 49 (the voltage of the second output signal OUT2) to rise. When the voltage at the second output terminal 49 rises, the voltage at the first internal node N1 also rises via the capacitor C1.

[0059] At time t15, the first control clock signal CK1 changes from high to low. This turns on the transistor M3. At this time, the set signal S is maintained at high. This causes the voltage of the first internal node N1 to rise to high, turning off the transistors M1, M4, and M6, and turning on the transistors M5 and M7. This causes the first output signal OUT1 to change from high to low, and the voltage of the second internal node N2 also changes from high to low. The voltage change of the second internal node N2 from high to low turns on the transistor M2.

[0060] During the period after time t15, as in the period before time t11, the voltage of the first internal node N1 is maintained at a high level, the voltage of the second internal node N2 is maintained at a low level, the first output signal OUT1 is maintained at a low level, and the second output signal OUT2 is maintained at a high level.

[0061] As described above, the first output signal OUT1 is maintained at a high level during the period t11 to t15, and the second output signal OUT2 is maintained at a low level during the period t13 to t14, thereby rewriting data in the pixel circuits 15 included in the data update row.

[0062] 10 , the operation of the unit circuit 4 corresponding to the data maintenance row (operation in the period around the time when the set signal S becomes active) will be described. In the period before time t11 and the period after time t15, the unit circuit 4 performs the same operation as the unit circuit 4 included in the data update row. Note that if the row two rows before this data maintenance row is also set as a data maintenance row, the mode signal VM is also low for a predetermined period immediately before time t11. Furthermore, if the row two rows after this data maintenance row is also set as a data maintenance row, the mode signal VM is also low for a predetermined period immediately after time t11.

[0063] At time t11, the first control clock signal CK1 changes from high to low. This turns on transistor M3. Also at time t11, the set signal S changes from high to low. This causes the voltage at the first internal node N1 to drop to low, turning on transistors M1, M4, and M6, and turning off transistors M5 and M7. With transistor M6 turned on and transistor M7 turned off, the voltage at the second internal node N2 changes from low to high. In the first output circuit 423, transistor M5 turns off, but the mode signal VM is at low. Therefore, regardless of the state of transistor M4, the first output signal OUT1 is maintained at low.

[0064] At time t12, the first control clock signal CK1 changes from low to high, turning off the transistor M3. Also at time t12, the set signal S changes from low to high.

[0065] At time t13, the second control clock signal CK2 changes from high to low. At this time, similar to the operation of the unit circuit 4 included in the data update row, a large negative voltage is applied to the control terminal of the transistor M1, and the voltage of the second output signal OUT2 drops to a level sufficient to turn on the write control transistor T3 connected to the second output terminal 49. At this time, in the first output circuit 423, the transistor M4 is on and the transistor M5 is off, but because the mode signal VM is low, the first output signal OUT1 is maintained at low.

[0066] At time t14, the second control clock signal CK2 changes from low to high, causing the voltage at the input terminal 43 to rise, and the voltage at the second output terminal 49 (the voltage of the second output signal OUT2) to rise. When the voltage at the second output terminal 49 rises, the voltage at the first internal node N1 also rises via the capacitor C1.

[0067] As described above, in the unit circuits 4 corresponding to the data retention rows, even if an active set signal S (a low-level set signal S) is input, the first output signal OUT1 is maintained at a low level during the period t11 to t15, unlike the unit circuits 4 included in the data update rows. Therefore, in the pixel circuits 15 included in the data retention rows, the initialization transistor T1 and the threshold compensation transistor T2 are maintained in an off state. Therefore, even if the write control transistor T3 in the pixel circuit 15 is turned on, no data voltage is written to the pixel circuit 15.

[0068] 4.3 Overall Operation First, the operation during normal driving (driving in which data for all rows is rewritten when a display image is refreshed) will be described with reference to Fig. 11. Note that, with reference to Fig. 11, signals denoted by reference numerals 71, 72, 73, 74, and 75 are signals provided to pixel circuits 15 in the (i-2)th, (i-1)th, i-th, (i+1)th, and (i+2)th rows, respectively (the same applies to Figs. 12 to 14).

[0069] During normal driving, the update control signals GVDDL1, GVDDL2, GVDDR1, and GVDDR2 are maintained at a high level. Therefore, the mode signal VM is maintained at a high level in all unit circuits 4. Therefore, in the pixel circuits 15 of each row, the waveforms of the first to third scanning signals change during a desired period as shown in FIG. 4. As a result, data voltages are written sequentially to the pixel circuits 15 in the display unit 11, row by row.

[0070] Next, with reference to FIG. 12 , the operation when partial driving is performed will be described. Here, attention is focused on the case where the i-th row and the (i+1)-th row are set as data-sustaining rows. As described above, when normal driving is performed, the update control signals GVDDL1, GVDDL2, GVDDR1, and GVDDR2 are maintained at a high level. In contrast, when partial driving is performed, the update control signals GVDDL1, GVDDL2, GVDDR1, and GVDDR2 are each maintained at a low level for a predetermined period depending on the row set as the data-sustaining row. As described above, in this embodiment, the levels of the update control signals GVDDL1, GVDDL2, GVDDR1, and GVDDR2 can be changed at different timings. The update control signal GVDDL1 corresponds to the first mode signal, the update control signal GVDDL2 corresponds to the second mode signal, the update control signal GVDDR1 corresponds to the third mode signal, and the update control signal GVDDR2 corresponds to the fourth mode signal.

[0071] In this case, when normal driving is performed, the update control signal GVDDL2 is maintained at a low level during the period when the first scanning signal NSL(i-2) is maintained at a high level, when normal driving is performed, the update control signal GVDDL1 is maintained at a low level during the period when the first scanning signal NSL(i-1) is maintained at a high level, when normal driving is performed, the update control signal GVDDR2 is maintained at a low level during the period when the second scanning signal NSR(i) is maintained at a high level, and when normal driving is performed, the update control signal GVDDR1 is maintained at a low level during the period when the second scanning signal NSR(i+1) is maintained at a high level. As a result, when partial driving is performed, the first scanning signal NSL(i-2) is maintained at a low level during a period when the first scanning signal NSL(i-2) is maintained at a high level during a period when the normal driving is performed, the first scanning signal NSL(i-1) is maintained at a low level during a period when the first scanning signal NSL(i-1) is maintained at a high level during a period when the normal driving is performed, the second scanning signal NSR(i) is maintained at a low level during a period when the second scanning signal NSR(i+1) is maintained at a high level during a period when the normal driving is performed, and the second scanning signal NSR(i+1) is maintained at a low level during a period when the second scanning signal NSR(i+1) is maintained at a high level during a period when the second scanning signal NSR(i+1) is maintained at a low level. Therefore, data voltages are not written to the pixel circuits 15 included in the nth row and the (n+1)th row that are set as data maintenance rows. In the pixel circuits 15 included in the data update rows (rows other than the nth row and the (n+1)th row), the waveforms of the first to third scanning signals change during the desired period as shown in FIG. 4. This causes data voltages to be written to the pixel circuits 15 included in the data update rows. In this embodiment, partial driving is performed in the manner described above.

[0072] 12 (the period during which data voltages are written to the pixel circuits 15 in the i-th or (i+1)-th row when normal driving is performed), the data signal line D is set to a high impedance state. That is, the data-side drive circuit 30 in this embodiment maintains the data signal line D in a high impedance state during the period during which the write control transistors T3 are maintained in the on state in the pixel circuits 15 included in the data maintenance row.

[0073] As described above, in this embodiment, the scanning signal line drive circuit constituted by the first shift register 401L and the second shift register 401R drives the first to third scanning signal lines so that, during each frame period, in the pixel circuits 15 included in the data update row, the initialization transistor T1 is maintained in the on state for a first predetermined period (period t2 to t3 in FIG. 4) while the write control transistor T3 and the threshold compensation transistor T2 are maintained in the off state, and then the threshold compensation transistor T2 is maintained in the on state for a second predetermined period (period t4 to t7 in FIG. 4) and the write control transistor T3 is maintained in the on state for a third predetermined period (period t5 to t6 in FIG. 4) which is a part of the second predetermined period, and so that in the pixel circuits 15 included in the data maintenance row, the initialization transistor T1 and the threshold compensation transistor T2 are maintained in the off state. In this way, the scanning signal line driving step is realized by the operation of driving the first to third scanning signal lines, and the write setting step is realized by the operation of setting each row of the pixel matrix to either a data update row or a data maintenance row for each frame period.

[0074] The scanning signal line drive circuit also drives the third scanning signal line so that the write control transistor T3 is maintained in the on state in all of the n×m pixel circuits 15 for the third predetermined period, regardless of whether each of the n×m pixel circuits 15 is included in a data update row or a data maintenance row, during each frame period.

[0075] 5. Effects According to this embodiment, each row of the pixel matrix is ​​set as either a data update row to which a data voltage is written or a data maintenance row to which no data voltage is written. A scanning signal line drive circuit including a first shift register 401L and a second shift register 401R drives a first scanning signal line NSL connected to the control terminal of the initialization transistor T1 and a second scanning signal line NSR connected to the control terminal of the threshold compensation transistor T2 so that the initialization transistor T1 and the threshold compensation transistor T2 are maintained in an off state in the pixel circuits 15 included in the data maintenance row. Here, the first scanning signal line NSL and the second scanning signal line NSR are driven by different shift registers (the first scanning signal line NSL is driven by the first shift register 401L, and the second scanning signal line NSR is driven by the second shift register 401R). Therefore, the first scanning signal line NSL and the second scanning signal line NSR can be driven to prevent writing of a data voltage in the data maintenance row without affecting the operation of the pixel circuits 15 included in the data update row. As described above, according to this embodiment, in an organic EL display device including pixel circuits 15 configured with a mixture of N-type transistors and P-type transistors, partial driving can be achieved without causing display defects.

[0076] 12, the data signal line D is set to a high impedance state. This reduces the charging / discharging power of the data signal line D and the driving power of the data-side driving circuit 30. Furthermore, in a system such as a host that transmits data to the display device 10, the power required for data transfer is reduced because it is no longer necessary to transmit data corresponding to the data maintenance rows to the display device 10. As described above, it is possible to achieve partial driving while significantly reducing power consumption.

[0077] 6. Modifications Modifications of the above embodiment will be described below, focusing mainly on the differences from the above embodiment.

[0078] <6.1 Modifications Regarding Driving Method> Two modifications (first and second modifications) regarding driving method will be described below.

[0079] 6.1.1 First Modification In the above embodiment, the data signal line D is in a high impedance state during a period in which a data voltage is written to the pixel circuits 15 included in the data maintenance row when normal driving is performed. In contrast, in this modification, during this period (the period indicated by the arrow with reference numeral 77 in FIG. 13 ), an on-bias voltage Vob, which will be described later, is applied to the data signal line D from the data-side drive circuit 30 instead of the data voltage.

[0080] The thin-film transistor serving as the drive transistor T4 in the pixel circuit 15 has a hysteresis characteristic. Here, the voltage stress applied to the drive transistor T4 in the pixel circuit 15 included in the data update row is different from the voltage stress applied to the drive transistor T4 in the pixel circuit 15 included in the data maintenance row, and since the drive transistor T4 has a hysteresis characteristic, the luminance change differs between the data update row and the data maintenance row. This can cause visible flicker. Therefore, in order to suppress the occurrence of flicker due to the hysteresis characteristic of the drive transistor T4, it has been customary to intentionally apply a voltage stress to the drive transistor T4. The bias voltage for applying the voltage stress to the drive transistor T4 is the on-bias voltage Vob.

[0081] The write control transistor T3 is turned on for a predetermined period in the pixel circuits 15 included in the data maintenance rows, as in the pixel circuits 15 included in the data update rows. Therefore, according to this modification, in the pixel circuits 15 included in the data maintenance rows, the on-bias voltage Vob is applied to the drive transistor T4 via the write control transistor T3. This reduces the difference in luminance change between the data update rows and the data maintenance rows due to the hysteresis characteristics of the drive transistor T4, thereby suppressing the occurrence of flicker. This achieves partial drive with good display quality.

[0082] <6.1.2 Second Modification> In this modification, during a period in which a data voltage is written to pixel circuits 15 included in a data maintenance row when normal driving is performed (a period indicated by an arrow with reference numeral 78 in FIG. 14 ), an on-bias voltage Vob is applied to the data signal line D, and then the data signal line D is set to a high-impedance state.

[0083] Here, a configuration for realizing the driving method of this modified example will be described. In this modified example, as shown in FIG. 15 , a voltage switching circuit 60 is provided between the data-side driving circuit 30 and the display unit 11 to switch the voltage applied to the data signal line D between a normal data voltage and an on-bias voltage Vob. The data-side driving circuit 30 includes a data signal line driving circuit 310 that outputs the normal data voltage and an on-bias voltage output circuit 320 that outputs the on-bias voltage Vob. The voltage switching circuit 60 includes transistors 61 as switching elements corresponding to each data signal line D. The transistors 61 have a control terminal that receives an enable signal ENA output from the data-side driving circuit 30, a first conduction terminal that receives the on-bias voltage Vob output from the output buffer (amplifier) ​​321 of the on-bias voltage output circuit 320, and a second conduction terminal that is connected to the corresponding data signal line D. The transistors 61 function as connection control transistors.

[0084] In the above configuration, the enable signal ENA is maintained at a high level during a period when a data voltage is to be written to the pixel circuits 15 included in a data update row. At this time, the transistor 61 is in an off state, and the data voltage output from the output buffer (amplifier) ​​311 of the data signal line drive circuit 310 is applied to the data signal line D in the display unit 11, as indicated by the thick solid line labeled with reference numeral 66 in FIG.

[0085] In contrast, during the period in which data voltages are written to the pixel circuits 15 included in the data maintenance row when normal driving is performed, the enable signal ENA is maintained at a low level for a predetermined period and then maintained at a high level. At this time, the output buffer 311 of the data signal line drive circuit 310 is maintained in a high impedance state. During the period in which the enable signal ENA is maintained at a low level, the transistor 61 is in an on state, and the on-bias voltage Vob output from the output buffer 321 of the on-bias voltage output circuit 320 is applied to the data signal line D in the display unit 11, as indicated by the thick solid line labeled 67 in FIG. 17 .

[0086] According to this modification, as in the first modification, the occurrence of flicker due to the hysteresis characteristic of the drive transistor T4 is suppressed, and partial driving with good display quality is achieved. Furthermore, the more rows that are set as data retention rows (i.e., the more rows that do not rewrite the display image), the longer the period during which the data signal line D is maintained in a high impedance state. This effectively reduces power consumption. Furthermore, unlike the first modification, the on-bias voltage Vob can be output from one output buffer 321 to multiple data signal lines D, which also effectively reduces power consumption from this perspective.

[0087] <6.2 Modifications of the Configuration of the Unit Circuit> Four modifications (third to sixth modifications) of the configuration of the unit circuit 4 will be described below.

[0088] 6.2.1 Third Modification Figure 18 is a circuit diagram showing the configuration of a unit circuit 4 in this modification. In addition to a first control circuit 411, a second control circuit 421, a first output circuit 423, and a second output circuit 422 configured in the same manner as in the above embodiment (see Figure 8), the unit circuit 4 in this modification includes a third control circuit 412 that controls the voltage of the first internal node N1. The third control circuit 412 includes a stabilization circuit 430 and a transistor M10. The stabilization circuit 430 includes transistors M8 and M9. The transistors M8 to M10 are P-type transistors.

[0089] As shown in FIG. 18, the first conduction terminal of transistor M10 and the control terminal of transistor M1 are connected to each other. The node where these are connected is called the "third internal node." The third internal node is denoted by the symbol N3. Furthermore, the first conduction terminal of transistor M8 and the second conduction terminal of transistor M9 are connected to each other. The node where these are connected is called the "fourth internal node." The fourth internal node is denoted by the symbol N4.

[0090] The transistor M8 has a control terminal connected to the input terminal 43, a first conduction terminal connected to the fourth internal node N4, and a second conduction terminal connected to the first internal node N1. The transistor M9 has a control terminal connected to the second internal node N2, a first conduction terminal connected to the input terminal for the gate high voltage VGH, and a second conduction terminal connected to the fourth internal node N4. The transistor M10 has a control terminal connected to the input terminal for the gate low voltage VGL, a first conduction terminal connected to the third internal node N3, and a second conduction terminal connected to the first internal node N1.

[0091] The operation of the unit circuit 4 corresponding to the data update row (the operation in the period around the time when the set signal S becomes active) will be described with reference to FIG.

[0092] At time t11, as in the above embodiment, transistors M4 and M6 are turned on, and transistors M5 and M7 are turned off. Here, even if the voltage of the first internal node N1 drops to a low level, the third control circuit 412 maintains transistor M10 in an on state. Therefore, the voltage of the third internal node N3 also drops from a high level to a low level. This causes transistor M1 to turn on. At time t12, as in the above embodiment, transistor M3 is turned off.

[0093] At time t13, the second control clock signal CK2 changes from high to low, causing the voltage at the second output terminal 49 (the voltage of the second output signal OUT2) to decrease. Furthermore, as the voltage at the second output terminal 49 decreases, the voltage at the third internal node N3 also decreases. As a result, a large negative voltage is applied to the control terminal of the transistor M1, causing the voltage of the second output signal OUT2 to decrease sufficiently. However, when the voltage at the third internal node N3 decreases at time t13, the voltage at the first conduction terminal of the transistor M10 becomes lower than the voltage at the control terminal. This causes the transistor M10 to enter an off state. Therefore, the voltage at the first internal node N1 does not change at time t13.

[0094] At time t14, the second control clock signal CK2 changes from low to high, causing the voltage at the second output terminal 49 (the voltage of the second output signal OUT2) to rise, and the voltage at the third internal node N3 also rises, turning on the transistor M10.

[0095] At time t15, as in the above embodiment, the transistors M4 and M6 are turned off, and the transistors M5 and M7 are turned on. Furthermore, the voltage of the second internal node N2 changes from high to low, causing the transistors M2 and M9 to turn on. With the transistor M9 turned on, the voltage of the fourth internal node N4 rises. Furthermore, since the transistor M10 is on, the voltage of the third internal node N3 also rises to high. This causes the transistor M1 to turn off.

[0096] As described above, the first output signal OUT1 is maintained at a high level during the period t11 to t15, and the second output signal OUT2 is maintained at a low level during the period t13 to t14, thereby rewriting data in the pixel circuits 15 included in the data update row.

[0097] In contrast, in the unit circuits 4 corresponding to the data retention rows, the mode signal VM is maintained at a low level at least during the periods t11 to t15. Therefore, the first output signal OUT1 is maintained at a low level during the periods t11 to t15. Therefore, similar to the above embodiment, no data voltage is written to the pixel circuits 15 included in the data retention rows.

[0098] According to this modification, the unit circuit 4 includes the transistor M10, which maintains the voltage of the first internal node N1 even when the voltage of the third internal node N3 drops due to bootstrap operation. This reduces the amplitude of the voltage of the first internal node N1 compared to when the transistor M10 is not included. This reduces the voltage stress on the control terminals of the transistors M4 to M7 and the voltage stress on the second conduction terminal of the transistor M3. This results in improved reliability. Furthermore, the unit circuit 4 includes the stabilization circuit 430, which reliably maintains the voltages of the first internal node N1 and the third internal node N3 at a high level during the period when the first output signal OUT1 should be maintained at a low level, even if noise occurs due to the clock operation of the second control clock signal CK2. This prevents problems such as display defects caused by the clock operation of the second control clock signal CK2.

[0099] 6.2.2 Fourth Modification Figure 20 is a circuit diagram showing the configuration of a unit circuit 4 in this modification. In this modification, the configuration of the second control circuit 421 differs from that of the above embodiment (see Figure 8). With regard to transistor M6, the control terminal is connected to the first internal node N1, the first conduction terminal is connected to the input terminal 42, and the second conduction terminal is connected to the second internal node N2. With regard to transistor M7, the control terminal is connected to the input terminal 42, the first conduction terminal is connected to the second internal node N2, and the second conduction terminal is connected to the input terminal for the gate low voltage VGL. Note that transistors M6 and M7 are P-type transistors.

[0100] The operation of the unit circuit 4 corresponding to the data update row (the operation in the period around the time when the set signal S becomes active) will be described with reference to FIG.

[0101] At time t11, the voltage of the first internal node N1 drops to low level, as in the above embodiment. However, to be precise, the low level voltage of the first internal node N1 at this time is higher than the gate low voltage VGL, which is a constant voltage, by the absolute value of the threshold voltage (<0) of the transistor M3. As the voltage of the first internal node N1 drops to low level, the transistor M4 is turned on and the transistor M5 is turned off. Furthermore, since the voltage of the second internal node N2 is low level, the first control clock signal CK1 changes from high level to low level, and the transistor M6 is turned off.

[0102] At time t12, the first control clock signal CK1 changes from low to high. At this time, the voltage of the first internal node N1 is low, so the transistor M6 is turned on, and the voltage of the second internal node N2 changes from low to high. At time t13, as in the above embodiment, the voltage of the first internal node N1 drops, and the voltage of the second output signal OUT2 drops to a level sufficient to turn on the write control transistor T3 connected to the second output terminal 49. At time t14, as in the above embodiment, the voltage of the second output terminal 49 (the voltage of the second output signal OUT2) and the voltage of the first internal node N1 rise.

[0103] At time t15, the first control clock signal CK1 changes from high to low, and the voltage at the first internal node N1 rises to high, as in the above embodiment. This turns on the transistor M5, and the first output signal OUT1 changes from high to low. Furthermore, with the transistor M7 turning on, the voltage at the second internal node N2 also changes from high to low. As a result, the transistor M2 turns on. The low-level voltage at the second internal node N2 at this time is, to be precise, a voltage higher than the gate low voltage VGL (a constant voltage) by the threshold voltage of the transistor M6, but is still low enough to turn on the transistor M2.

[0104] As described above, in this modification as well, data is rewritten normally in the pixel circuits 15 included in the data update row. In the unit circuits 4 corresponding to the data maintenance row, the mode signal VM is maintained at a low level at least during the period t11 to t15, and therefore the first output signal OUT1 is maintained at a low level during the period t11 to t15. As a result, in this modification as well, data voltages are not written to the pixel circuits 15 included in the data maintenance row.

[0105] Incidentally, among the transistors M1 to M7 in the unit circuit 4 in this modification, only transistor M5 is N-type (N-channel type), while the other transistors M1 to M4 and M6 to M7 are P-type (P-channel type). Therefore, an oxide TFT such as an IGZO-TFT can be used for transistor M5, and LTPS-TFTs can be used for the other transistors M1 to M4 and M6 to M7. Generally, LTPS-TFTs have higher resistance to voltage stress than oxide TFTs. Therefore, this modification provides the same effects as the above embodiment, as well as the effect of higher resistance to voltage stress and improved reliability.

[0106] 6.2.3 Fifth Modification FIG. 22 is a circuit diagram showing the configuration of a unit circuit 4 in this modification. The unit circuit 4 in this modification includes a first control circuit 411, a second control circuit 421, a third control circuit 412, a first output circuit 423, and a second output circuit 422. The configurations of the first control circuit 411, the first output circuit 423, and the second output circuit 422 are the same as those in the above embodiment (see FIG. 8). The configuration of the second control circuit 421 is the same as that in the fourth modification (see FIG. 20). The configuration of the third control circuit 412 is the same as that in the third modification (see FIG. 18).

[0107] In this modification, in the unit circuit 4 corresponding to the data update row, the voltages of the first to fourth internal nodes N1 to N4 change as shown in FIG. 23 . That is, the first control circuit 411, the third control circuit 412, and the second output circuit 422 in this modification operate substantially similarly to the first control circuit 411, the third control circuit 412, and the second output circuit 422 in the third modification. As a result, the voltages of the first internal node N1, the third internal node N3, and the fourth internal node N4 change in the same manner as in the third modification (see FIG. 19 ). The second control circuit 421 in this modification operates in the same manner as the second control circuit 421 in the fourth modification. As a result, the voltage of the second internal node N2 changes in the same manner as in the fourth modification (see FIG. 21 ). Based on the voltages of the first to fourth internal nodes N1 to N4, the unit circuit 4 in this modification also outputs the first output signal OUT1 and the second output signal OUT2, similar to those in the above embodiment. Therefore, in this modification as well, data is rewritten normally in the pixel circuits 15 included in the data update row. In the unit circuits 4 corresponding to the data maintenance row, the mode signal VM is maintained at a low level at least during the period t11 to t15, and therefore the first output signal OUT1 is maintained at a low level during the period t11 to t15. As a result, in this modification as well, data voltages are not written to the pixel circuits 15 included in the data maintenance row.

[0108] As in the third modification, the unit circuit 4 in this modification includes a third control circuit 412. Therefore, the amplitude of the voltage at the first internal node N1 is reduced, thereby reducing the voltage stress applied to the transistors in the unit circuit 4 and improving reliability. Furthermore, the provision of the stabilization circuit 430 prevents problems such as display defects caused by the clock operation of the second control clock signal CK2.

[0109] The second control circuit 421 in this modification has the same configuration as the second control circuit 421 in the fourth modification. Therefore, by using an oxide TFT only for the transistor M5 in the unit circuit 4 and using LTPS-TFTs for the transistors other than the transistor M5, it is possible to increase the resistance to voltage stress and improve reliability.

[0110] 24 is a circuit diagram showing the configuration of a unit circuit 4 in this modification. As in the third modification (see FIG. 18 ), the unit circuit 4 in this modification includes a first control circuit 411, a second control circuit 421, a third control circuit 412, a first output circuit 423, and a second output circuit 422. However, the configurations of the first control circuit 411, the second control circuit 421, the third control circuit 412, and the second output circuit 422 are different from those in the third modification.

[0111] In this modification, the control terminal of the transistor M3 in the first control circuit 411 is connected to the input terminal 41 (i.e., the input terminal for the set signal S), the first conduction terminal is connected to the input terminal for the gate low voltage VGL, and the second conduction terminal is connected to the first internal node N1. As shown in FIG. 24 , the second control circuit 421 in this modification includes four transistors M11 to M14 and one resistor R1. The transistors M11 to M14 are P-type transistors. The control terminal of the transistor M11 is connected to the input terminal 42, the first conduction terminal is connected to one end of the resistor R1, and the second conduction terminal is connected to the input terminal for the gate low voltage VGL. The control terminal of the transistor M12 is connected to the input terminal 41, the first conduction terminal is connected to the input terminal for the gate high voltage VGH, and the second conduction terminal is connected to the second internal node N2. The control terminal of the transistor M13 is connected to the output terminal 49, the first conduction terminal is connected to the input terminal for the gate high voltage VGH, and the second conduction terminal is connected to the second internal node N2. The control terminal of the transistor M14 is connected to the input terminal 45 (the input terminal for the initialization signal INITB), the first conduction terminal is connected to the second internal node N2, and the second conduction terminal is connected to the input terminal for the gate low voltage VGL. The resistor R1 has one end connected to the first conduction terminal of the transistor M11 and the other end connected to the second internal node N2. The initialization signal INITB is a signal that goes low only immediately after power is turned on. By providing this initialization signal INITB to the control terminal of the transistor M14, the voltage of the second internal node N2 is reliably brought low immediately after power is turned on. Unlike the third modification, the third control circuit 412 in this modification does not include the transistor M8, and the second conduction terminal of the transistor M9 is connected to the first internal node N1. Unlike the third modification, the second output circuit 422 in this modification includes a capacitor C2, one end of which is connected to the second internal node N2 and the other end of which is connected to the first conduction terminal of the transistor M2.

[0112] The operation of the unit circuit 4 corresponding to the data update row (the operation in the period around the time when the set signal S becomes active) will be described with reference to FIG.

[0113] At time t11, the set signal S changes from high to low, turning on transistors M3 and M12. With transistor M3 turned on, the voltage at first internal node N1 drops to low, turning transistor M4 on, and turning transistor M5 off. At this time, the mode signal VM is maintained at high, turning on transistor M4 and turning transistor M5 off, causing the first output signal OUT1 to change from low to high. Also, at time t11, the first control clock signal CK1 changes from high to low, turning on transistor M11 in the second control circuit 421. This causes current to flow through the path indicated by the arrow labeled 69 in FIG. 25. By setting the resistance value of resistor R1 sufficiently high, the voltage at second internal node N2 rises from low to nearly high. As a result, transistors M2 and M9 are turned off. Furthermore, in the third control circuit 412, the transistor M10 is maintained in the on state. Therefore, the voltage of the third internal node N3 drops from high to low, and the transistor M1 is turned on. At time t12, the set signal S changes from low to high, and the transistors M3 and M12 are turned off.

[0114] At time t13, the voltage of the second output signal OUT2 drops sufficiently, as in the third modification. At this time, the voltage of the first internal node N1 does not change, as in the third modification. Furthermore, as the voltage of the second output signal OUT2 drops, the transistor M13 in the second control circuit 421 turns on. This maintains the voltage of the second internal node N2 at a high level. At time t14, the voltage of the second output terminal 49 (the voltage of the second output signal OUT2) and the voltage of the third internal node N3 rise, as in the third modification.

[0115] At time t15, while the set signal S is maintained at a high level, the first control clock signal CK1 changes from a high level to a low level. As a result, in the second control circuit 421, only the transistor M11 is turned on. As a result, the voltage of the second internal node N2 drops from a high level to a low level, and the transistors M2 and M9 are turned on. With the transistor M9 turned on, the voltage of the first internal node N1 rises to a high level, the transistor M4 is turned off, and the transistor M5 is turned on. As a result, the first output signal OUT1 changes from a high level to a low level. Furthermore, since the transistor M10 is turned on, the voltage of the third internal node N3 also rises to a high level. As a result, the transistor M1 is turned off.

[0116] As described above, in this modification as well, data is rewritten normally in the pixel circuits 15 included in the data update row. In the unit circuits 4 corresponding to the data maintenance row, the mode signal VM is maintained at a low level at least during the period t11 to t15, and therefore the first output signal OUT1 is maintained at a low level during the period t11 to t15. As a result, in this modification as well, data voltages are not written to the pixel circuits 15 included in the data maintenance row.

[0117] According to this modification, the number of connections between each unit circuit 4 and the clock wiring (wiring for the first and second control clock signals CK1 and CK2) is reduced compared to the third to fifth modifications. This reduces the clock load. Furthermore, since the set signal S, rather than the first control clock signal CK1, is applied to the control terminal of transistor M3, operational abnormalities caused by leakage current through transistor M3 are prevented. Furthermore, according to the configuration of the second control circuit 421 of this modification, the gate high voltage VGH is applied to the first internal node N1 and the third internal node N3 throughout the period during which the voltages of the first internal node N1 and the third internal node N3 should be maintained at a high level, thereby stabilizing the operation of the unit circuit 4. As a result, reliability is significantly improved.

[0118] <7. Others> In the above embodiment (including modified examples), an organic EL display device has been described as an example, but the present invention is not limited to this. The above disclosure can also be applied to an inorganic EL display device, a QLED display device, or any other display device that uses a display element driven by current.

[0119] 4...Unit circuit 10...Display device (organic EL display device) 11...Display section 15...Pixel circuit 30...Data side drive circuit 40...Scanning side drive circuit 401L...First shift register 401R...Second shift register NSL...First scanning signal line, first scanning signal NSR...Second scanning signal line, second scanning signal PS...Third scanning signal line, third scanning signal OL...Organic EL element T1...Initialization transistor T2...Threshold compensation transistor T3...Write control transistor T4...Drive transistor T5...First light-emitting control transistor T6...Second light-emitting control transistor T7...Reset transistor M1 to M10...Transistors (in unit circuit) N1 to N4...First to fourth internal nodes (in unit circuit)

Claims

1. A display device using a display element driven by current, comprising: a display section including a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of third scanning signal lines, a plurality of light-emitting control lines, an initialization power supply line that supplies an initialization voltage, and a plurality of pixel circuits that form a pixel matrix of a plurality of rows and a plurality of columns; a data-side drive circuit that applies a data voltage to the plurality of data signal lines; a light-emitting control circuit that selectively drives the plurality of light-emitting control lines; and a scan-side drive circuit that includes a plurality of shift registers and a scan-signal-line drive circuit that selectively drives the plurality of first scanning signal lines, the plurality of second scanning signal lines, and the plurality of third scanning signal lines, each of the plurality of pixel circuits corresponding to one of the plurality of data signal lines, one of the plurality of first scanning signal lines, one of the plurality of second scanning signal lines, one of the plurality of third scanning signal lines, and one of the plurality of light-emitting control lines; and a drive transistor having a control terminal, a first conduction terminal, and a second conduction terminal, and arranged in series with the display element; a storage capacitor having one end connected to the control terminal of the drive transistor; an initialization transistor as a switching element, having a control terminal connected to a corresponding first scanning signal line, a first conduction terminal connected to the initialization power supply line, and a second conduction terminal connected to the control terminal of the drive transistor; a threshold compensation transistor as a switching element, having a control terminal connected to a corresponding second scanning signal line, a first conduction terminal connected to the first conduction terminal of the drive transistor, and a second conduction terminal connected to the control terminal of the drive transistor; a write control transistor as a switching element, having a control terminal connected to a corresponding third scanning signal line, a first conduction terminal connected to the second conduction terminal of the drive transistor, and a second conduction terminal connected to a corresponding data signal line; and at least one emission control transistor as a switching element, having a control terminal connected to a corresponding emission control line, and arranged in series with the display element and the drive transistor, wherein the initialization transistor and the threshold compensation transistor are N-type transistors,the write control transistor is a P-type transistor; the plurality of first scanning signal lines and the plurality of second scanning signal lines are driven by different shift registers included in the scanning signal line drive circuit; and for each frame period, each row of the pixel matrix is set as either a data update row in which the data voltage is written to a pixel circuit or a data maintenance row in which the data voltage is not written to a pixel circuit, and the scanning signal line drive circuit drives the plurality of first scanning signal lines, the plurality of second scanning signal lines, and the plurality of third scanning signal lines so that, in each frame period, in pixel circuits included in rows set as the data update rows, after the initialization transistor is maintained in an on-state for a first predetermined period during a period in which the write control transistor and the threshold compensation transistor are maintained in an off-state, the threshold compensation transistor is maintained in an on-state for a second predetermined period and the write control transistor is maintained in an on-state for a third predetermined period that is a part of the second predetermined period, and so that in pixel circuits included in rows set as the data maintenance rows, the initialization transistor and the threshold compensation transistor are maintained in an off-state.

2. The display device according to claim 1, wherein the scanning signal line drive circuit drives the plurality of third scanning signal lines so that the write control transistor is maintained in an on state for the third predetermined period in all of the plurality of pixel circuits during each frame period, regardless of whether each of the plurality of pixel circuits is included in a row set as the data update row or a row set as the data maintenance row.

3. The display device according to claim 2, wherein the data side drive circuit applies the data voltage to the plurality of data signal lines during a period in which the write control transistor is maintained in an on state in the pixel circuits included in the row set as the data update row, and applies a bias voltage to the plurality of data signal lines to apply voltage stress to the drive transistor during a period in which the write control transistor is maintained in an on state in the pixel circuits included in the row set as the data maintenance row.

4. The display device according to claim 3, wherein the data side driving circuit includes a data signal line driving circuit having a plurality of output buffers corresponding one-to-one to the plurality of data signal lines, for applying the data voltage to the plurality of data signal lines, and the bias voltage is output from the plurality of output buffers.

5. The display device according to claim 4, characterized in that when k consecutive rows of the pixel matrix are set as the data maintenance rows, where k is an integer of 2 or greater, the data side driving circuit applies the bias voltage to the plurality of data signal lines during a period in which the write control transistor is maintained in an on state in the pixel circuit included in the first row of the k rows, and then sets the outputs of the plurality of output buffers to a high impedance state.

6. The display device according to claim 3, wherein the data side drive circuit includes: a data signal line drive circuit having a plurality of output buffers corresponding one-to-one to the plurality of data signal lines, for applying the data voltage to the plurality of data signal lines; and a bias voltage output circuit for outputting the bias voltage; a region between the data side drive circuit and the pixel matrix is provided with a plurality of connection control transistors corresponding one-to-one to the plurality of data signal lines, each of the plurality of connection control transistors having a control terminal to which a control signal is applied, a first conduction terminal connected to the bias voltage output circuit, and a second conduction terminal connected to the corresponding data signal line; and the application of the bias voltage to the plurality of data signal lines is performed by the data side drive circuit applying the control signal to the control terminals of the plurality of connection control transistors so that the plurality of connection control transistors are turned on.

7. The display device according to claim 6, wherein said data side driving circuit maintains said plurality of output buffers in a high impedance state while said plurality of connection control transistors are maintained in an on state.

8. The display device according to claim 1, wherein the data side driving circuit maintains the plurality of data signal lines in a high impedance state during a period in which the write control transistors are maintained in an on state in pixel circuits included in a row set as the data maintenance row.

9. A display device according to any one of claims 1 to 8, characterized in that the plurality of shift registers include a first shift register provided at one end side of the plurality of third scanning signal lines and a second shift register provided at the other end side of the plurality of third scanning signal lines, the first shift register driving the plurality of first scanning signal lines and the plurality of third scanning signal lines, and the second shift register driving the plurality of second scanning signal lines and the plurality of third scanning signal lines.

10. The display device according to claim 9, wherein the first shift register includes a plurality of first unit circuits each outputting a first scanning signal and a third scanning signal, and the second shift register includes a plurality of second unit circuits each outputting a second scanning signal and a third scanning signal, wherein a first unit circuit that outputs the third scanning signal to a third scanning signal line connected to a control terminal of the write control transistor included in the pixel circuit in the i-th row, where i and p are natural numbers, outputs the first scanning signal to a first scanning signal line connected to a control terminal of the initialization transistor included in the pixel circuit in the (i+p)-th row, and a second unit circuit that outputs the third scanning signal to a third scanning signal line connected to the control terminal of the write control transistor included in the pixel circuit in the i-th row, outputs the second scanning signal to a second scanning signal line connected to a control terminal of the threshold compensation transistor included in the pixel circuit in the i-th row.

11. The first shift register includes a plurality of first unit circuits that operate based on two-phase clock signals composed of a first clock signal and a second clock signal, and each output a first scanning signal and a third scanning signal; the second shift register includes a plurality of second unit circuits that operate based on the two-phase clock signals, and each output a second scanning signal and a third scanning signal; one of the first clock signal and the second clock signal is input as an output control clock signal to the first unit circuit and the second unit circuit that output the third scanning signal to a third scanning signal line connected to a control terminal of the write control transistor included in the pixel circuit in an odd row, and the other of the first clock signal and the second clock signal is input as the output control clock signal to the first unit circuit and the second unit circuit that output the third scanning signal to a third scanning signal line connected to the control terminal of the write control transistor included in the pixel circuit in an even row; a mode signal indicating whether or not to permit writing of the data voltage to the pixel circuit is given to the plurality of first unit circuits and the plurality of second unit circuits; the plurality of first unit circuits and the plurality of second unit circuits have the same internal configuration, and each of the plurality of first unit circuits and the plurality of second unit circuits includes: a first internal node; a second internal node; a first control circuit that sets the voltage of the first internal node to the first logic level of two logic levels, a first logic level and a second logic level, when receiving an active set signal; a second control circuit that maintains the logic level of the voltage of the second internal node at the first logic level throughout a period in which the logic level of the voltage of the first internal node is maintained at the second logic level; and a first output circuit that outputs a first output signal of a logic level obtained by inverting the logic level of the voltage of the first internal node when the mode signal indicates that writing of the data voltage to the pixel circuit is permitted, and outputs the first output signal of the first logic level when the mode signal indicates that writing of the data voltage to the pixel circuit is not permitted.a second output circuit that outputs a second output signal of the same logic level as the output control clock signal when the logic level of the voltage of the first internal node is the first logic level, and outputs a second output signal of a logic level obtained by inverting the logic level of the voltage of the second internal node when the logic level of the voltage of the first internal node is the second logic level, wherein the first output signal output from the first output circuit included in each of the plurality of first unit circuits is provided to a corresponding first scanning signal line as the first scanning signal, and the first output signal output from the first output circuit included in each of the plurality of second unit circuits is provided to a corresponding second scanning signal line as the second scanning signal.

12. The display device according to claim 11, wherein the mode signals include a first mode signal provided to a first unit circuit that outputs the third scanning signal to a third scanning signal line connected to the control terminal of the write control transistor included in pixel circuits on odd rows; a second mode signal provided to a first unit circuit that outputs the third scanning signal to a third scanning signal line connected to the control terminal of the write control transistor included in pixel circuits on even rows; a third mode signal provided to a second unit circuit that outputs the third scanning signal to a third scanning signal line connected to the control terminal of the write control transistor included in pixel circuits on odd rows; and a fourth mode signal provided to a second unit circuit that outputs the third scanning signal to a third scanning signal line connected to the control terminal of the write control transistor included in pixel circuits on even rows; and wherein the display device is configured so that the level of the first mode signal, the level of the second mode signal, the level of the third mode signal, and the level of the fourth mode signal can be changed at different timings.

13. A display device according to any one of claims 1 to 8, further comprising a first power supply line and a second power supply line, wherein the at least one light-emitting control transistor comprises: a first light-emitting control transistor having a control terminal connected to the corresponding light-emitting control line, a first conduction terminal connected to the second conduction terminal of the drive transistor, and a second conduction terminal connected to the second power supply line; and a second light-emitting control transistor having a control terminal connected to the corresponding light-emitting control line, a first conduction terminal connected to the first power supply line via the display element, and a second conduction terminal connected to the first conduction terminal of the drive transistor; and each of the plurality of pixel circuits comprises a reset transistor having a control terminal connected to the corresponding light-emitting control line, a first conduction terminal connected to the first power supply line via the display element, and a second conduction terminal connected to the initialization power supply line, wherein the first light-emitting control transistor and the second light-emitting control transistor are P-type transistors, and the reset transistor is an N-type transistor.

14. A method for driving a display device using a display element driven by current, the display device comprising: a display section including a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of third scanning signal lines, a plurality of light-emission control lines, an initialization power supply line for supplying an initialization voltage, and a plurality of pixel circuits constituting a pixel matrix of a plurality of rows and a plurality of columns; a data-side driving circuit for applying a data voltage to the plurality of data signal lines; a light-emission control circuit for selectively driving the plurality of light-emission control lines; and a scanning-side driving circuit including a plurality of shift registers and comprising a scanning signal line driving circuit for selectively driving each of the plurality of first scanning signal lines, the plurality of second scanning signal lines, and the plurality of third scanning signal lines, wherein each of the plurality of pixel circuits corresponds to one of the plurality of data signal lines, one of the plurality of first scanning signal lines, one of the plurality of second scanning signal lines, one of the plurality of third scanning signal lines, and one of the plurality of light-emission control lines, and each of the plurality of pixel circuits corresponds to the display element, a drive transistor having a control terminal, a first conduction terminal, and a second conduction terminal, and arranged in series with the display element; a storage capacitor having one end connected to the control terminal of the drive transistor; an initialization transistor as a switching element, having a control terminal connected to a corresponding first scanning signal line, a first conduction terminal connected to the initialization power supply line, and a second conduction terminal connected to the control terminal of the drive transistor; a threshold compensation transistor as a switching element, having a control terminal connected to a corresponding second scanning signal line, a first conduction terminal connected to the first conduction terminal of the drive transistor, and a second conduction terminal connected to the control terminal of the drive transistor; a write control transistor as a switching element, having a control terminal connected to a corresponding third scanning signal line, a first conduction terminal connected to the second conduction terminal of the drive transistor, and a second conduction terminal connected to a corresponding data signal line; and at least one emission control transistor as a switching element, having a control terminal connected to a corresponding emission control line, and arranged in series with the display element and the drive transistor, wherein the initialization transistor and the threshold compensation transistor are N-type transistors,the write control transistor is a P-type transistor, the plurality of first scanning signal lines and the plurality of second scanning signal lines are driven by different shift registers included in the scanning signal line drive circuit, and the driving method includes a write setting step of setting each row of the pixel matrix to either a data update row in which the data voltage is written to a pixel circuit or a data maintenance row in which the data voltage is not written to a pixel circuit, for each frame period; a scanning signal line driving step of driving the plurality of first scanning signal lines, the plurality of second scanning signal lines, and the plurality of third scanning signal lines so that, in each frame period, in pixel circuits included in a row set to the data update row in the write setting step, during a period in which the write control transistor and the threshold compensation transistor are maintained in an off state, the initialization transistor is maintained in an on state for a first predetermined period, and then the threshold compensation transistor is maintained in an on state for a second predetermined period and the write control transistor is maintained in an on state for a third predetermined period that is a part of the second predetermined period, and so that, in pixel circuits included in a row set to the data maintenance row in the write setting step, the initialization transistor and the threshold compensation transistor are maintained in an off state.

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