Communication data exchange method, communication apparatus, chip and communication system

Abstract

The present application provides a communication data exchange method, a communication apparatus, a chip and a communication system, applied to the technical field of chips, and used for solving the problem of routing deadlocks of a 2D-Mesh network. The communication data exchange method comprises dividing a memory in a network node into a plurality of input buffer areas. Each input buffer area comprises a plurality of first storage areas. Each input buffer area is used for storing a plurality of input buffer queues of one interface. Each first storage area is used for storing a plurality of input buffer queues of a same destination interface, and each input buffer queue corresponds to one routing type. Upon obtaining data packets received by interfaces, a processor in the network node can store the data packets into the corresponding input buffer queues in the memory, solving the influence of the problem of routing deadlocks by means of isolated storage, and improving the reliability of data transmission of the 2D-mesh network.

Description

Communication data exchange method, communication device, chip and communication system

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on January 30, 2024, with application number 202410139910.1 and application name “A communication data exchange method, communication device, chip and communication system”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of chip technology, and in particular to a communication data exchange method, a communication device, a chip, and a communication system. Background Art

[0003] In existing communication systems, data exchange between terminal devices often requires a data exchange network consisting of multiple network nodes. To ensure the orderly transmission of data packets in high-speed data transmission environments, each network node has a buffer to store data packets awaiting forwarding. In 2D-Mesh networks, data transmission occurs via edges between network nodes. When a node needs to transmit a data packet to a neighboring node, it can choose to transmit via an edge in the north, south, west, or east direction. However, data packets currently transmitted in 2D-Mesh networks are prone to routing deadlocks. Summary of the Invention

[0004] The present application provides a communication data exchange method, a communication device, a chip, and a communication system for solving the routing deadlock problem of a 2D-Mesh network.

[0005] In a first aspect, a communication data exchange method is provided, which is applied to a network node. The network node includes multiple interfaces, a memory, and a processor. The processor is coupled to the memory and the multiple interfaces, respectively. The communication data exchange method can be executed by the processor, and the execution process includes: obtaining a first data packet received by a first interface among the multiple interfaces; storing the first data packet in a corresponding input buffer queue in the memory based on the routing type and destination interface of the first data packet. The memory includes multiple input buffers, each corresponding to one of the multiple interfaces; each input buffer includes multiple first storage areas, each first storage area being used to store multiple input buffer queues for the same destination interface, and each input buffer queue corresponding to a routing type. The destination interface is any interface among the multiple interfaces other than the input interface of the data packet. Routing types include deterministic routing and adaptive routing. Deterministic routing uses a fixed network node to forward data packets with the same source and destination addresses; adaptive routing determines the next-hop network node based on the congestion status of each of the multiple interfaces. In 2D-Mesh networks, routing deadlock is primarily caused by adaptive routing, which accounts for a relatively small proportion. Through this approach, adaptive routing packets and deterministic routing packets can be stored in different input buffer queues, ensuring ample storage space for adaptive routing packets. This prevents the two packets from interfering with each other and potentially causing routing deadlock. Compared to existing methods that store adaptive routing packets and deterministic routing packets in the same input buffer queue, this approach can better prevent routing deadlock during packet transmission.

[0006] In one possible implementation, when executing the above method, the processor may further determine the routing type of the first data packet based on the source address and destination address of the first data packet and the location information of the network node, and determine the destination interface of the first data packet based on the destination address of the first data packet and the location information of the network node. In this manner, each data packet can be more accurately stored in the corresponding input buffer queue.

[0007] In one possible implementation, the input buffer queue of the deterministic routing includes a plurality of input buffer queues with different steering directions. The steering direction is the direction of the destination network node corresponding to the destination address of the data packet relative to the destination interface of the network node. When executing the above method, the processor can also determine the steering direction of the first data packet based on the destination address of the first data packet and the location information of the network node. Then, according to the steering direction, the first data packet is stored in the corresponding input buffer queue. In the above manner, the input buffer queues with different steering directions can be further isolated and stored to prevent the back pressure signal generated by the downstream network node of the above network node from affecting non-related data packets, thereby reducing the impact of network congestion and improving the transmission efficiency of data packets.

[0008] In one possible implementation, the first storage area is further used to store an input buffer queue for converting adaptive routing to deterministic routing; the first data packet also includes a conversion identifier for converting adaptive routing to deterministic routing. When executing the above method, the first data packet may also be stored in a corresponding input buffer queue based on the first data packet's source address, destination address, conversion identifier, and the location information of the network node. Through this method, if a data packet is converted from an adaptive routing forwarding mode to a deterministic routing forwarding mode, it can be stored in a separate input buffer queue, avoiding occupying space in other buffer queues and better preventing routing deadlock issues.

[0009] In a possible implementation, the above method further includes: obtaining a second data packet to be output from a second interface among multiple interfaces. The second data packet is a data packet whose destination interface is the second interface, obtained from the corresponding storage area in the input buffer of other interfaces except the second interface. Then, the second data packet is stored in the output buffer queue corresponding to the second interface in the memory according to the routing type of the second data packet. The memory includes multiple output buffers, each output buffer corresponds to one interface among the multiple interfaces. Each output buffer includes multiple second storage areas, each second storage area is used to store an output buffer queue of a routing type. Routing types include deterministic routing and adaptive routing. Based on this, different types of buffer queues in the output buffers of each interface do not affect each other, so that routing deadlock problems can be prevented by isolated storage.

[0010] In one possible implementation, the output buffer queue of the deterministic routing includes multiple output buffer queues with different steering directions. When the second data packet is a data packet of the deterministic routing, the second data packet can be stored in the output buffer queue corresponding to the deterministic routing of the second interface according to the routing type and steering direction of the second data packet. In this way, the data packets of the deterministic routing can be stored in different output buffer queues according to the steering direction, thereby avoiding the situation where the output buffer queue of a certain steering direction is congested and the transmission of data packets of other steering directions is affected, thereby improving the transmission efficiency of data packets.

[0011] In one possible implementation, the method further includes obtaining first configuration information, the first configuration information including an indication of a storage method for an input buffer queue. Then, configuring multiple input buffers in a memory based on the first configuration information. Through the above process, the configuration method for the input buffers can be stored in advance as configuration information. When the network node is powered on, the memory can be directly configured based on the configuration information, thereby improving operational efficiency.

[0012] In a possible implementation, the first configuration information further includes an indication of a storage mode of the output buffer queue. Based on this, the method further includes: configuring a plurality of the output buffers in a memory according to the first configuration information.

[0013] In a second aspect, a communication device is provided, which includes multiple interfaces, a memory and a processor. The processor is coupled to the memory and the multiple interfaces respectively. The memory includes multiple input buffers, each input buffer corresponds to one interface among the multiple interfaces, each input buffer includes multiple first storage areas, each first storage area is used to store multiple input buffer queues of the same destination interface, and each input buffer queue corresponds to a routing type. The above-mentioned destination interface is any interface among the multiple interfaces except the input interface of the data packet. Routing types include deterministic routing and adaptive routing. Deterministic routing is a routing that uses a fixed communication device to forward data packets with the same source address and destination address. Adaptive routing is a routing that determines the route of the next-hop communication device based on the congestion status of each interface among the multiple interfaces. Each of the above-mentioned input buffer queues is used to store data packets of the corresponding destination interface and the corresponding routing type.

[0014] In a possible implementation, the processor is configured to store the first data packet into a corresponding input buffer queue in a memory according to a routing type and a destination interface of the first data packet.

[0015] In one possible implementation, the processor is further configured to determine a routing type of the first data packet based on a source address and a destination address of the first data packet and the location information of the communication device, and to determine a destination interface of the first data packet based on the destination address of the first data packet and the current location information of the communication device.

[0016] In one possible implementation, the deterministic routing input buffer queue includes multiple input buffer queues with different redirection directions. A redirection direction is the direction of the communication device corresponding to the destination address of the data packet relative to the destination interface of the communication device. Based on this, the processor is further configured to determine the redirection direction of the first data packet based on the destination address of the first data packet and the location information of the communication device. Based on the redirection direction, the first data packet is stored in the corresponding input buffer queue.

[0017] In one possible implementation, each first storage area is further configured to store an input buffer queue for converting adaptive routing to deterministic routing. The first data packet also includes a conversion identifier for converting adaptive routing to deterministic routing. Based on this, the processor is further configured to store the first data packet in a corresponding input buffer queue based on the source address, destination address, conversion identifier, and location information of the communication device.

[0018] In one possible implementation, the processor is further configured to: obtain a second data packet to be output from a second interface among a plurality of interfaces. The second data packet is a data packet whose destination interface is the second interface, obtained from a corresponding storage area in an input buffer of an interface other than the second interface. The second data packet is stored in an output buffer queue corresponding to the second interface in the memory according to the routing type of the second data packet. The memory includes a plurality of output buffers; each output buffer corresponds to one of the plurality of interfaces. Each output buffer includes a plurality of second storage areas, and each second storage area is used to store an output buffer queue of a routing type. The routing types mentioned above include deterministic routing and adaptive routing.

[0019] In one possible implementation, the output buffer queue for the deterministic routing includes multiple output buffer queues for different redirection directions. When the second data packet is a data packet for the deterministic routing, the processor is specifically configured to store the second data packet in the output buffer queue corresponding to the deterministic routing of the second interface based on the routing type and redirection direction of the second data packet.

[0020] In a possible implementation, the processor is further configured to obtain first configuration information, the first configuration information including an indication of a storage mode of the input buffer queue, and then configure the plurality of input buffers in a memory according to the first configuration information.

[0021] In a possible implementation, the first configuration information further includes an indication of a storage mode of the output buffer queue. The processor is further configured to: configure the plurality of output buffers in the memory according to the first configuration information.

[0022] In a third aspect, a chip is provided, comprising a plurality of dies, wherein the plurality of dies form a 2D-Mesh network, and each of the dies is a communication device in any possible implementation of the second aspect.

[0023] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer program instructions, wherein the computer program instructions, when executed by a processor, implement the method in any possible implementation manner of the first aspect.

[0024] In a fifth aspect, a communication system is provided, which includes multiple switching devices, wherein the multiple switching devices form a 2D-Mesh network, and each switching device is a communication device in any possible implementation method of the second aspect above.

[0025] In a sixth aspect, a computer program product is provided, which, when executed by a processor, implements the method in any possible implementation manner of the first aspect above.

[0026] The technical effects brought about by the above-mentioned second to sixth aspects and possible implementation methods can be found in the description of the technical effects brought about by the above-mentioned first aspect and possible implementation methods, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG1 is a schematic diagram of the structure of a 2D-Mesh network provided in an embodiment of the present application;

[0028] FIG2 is a schematic diagram of the structure of a network on chip provided in an embodiment of the present application;

[0029] FIG3 is a schematic diagram of the structure of a communication system provided in an embodiment of the present application;

[0030] FIG4 is a schematic diagram of a deadlock routing method provided by an embodiment of the present application;

[0031] FIG5 is a schematic diagram of a deadlock-avoiding routing redirection method provided in an embodiment of the present application;

[0032] FIG6 is a flow chart of a communication data exchange method provided in an embodiment of the present application;

[0033] FIG7 is a schematic diagram of a storage method of an input buffer queue provided in an embodiment of the present application;

[0034] FIG8 is a flow chart of another communication data exchange method provided in an embodiment of the present application;

[0035] FIG9 is a schematic diagram of a storage method of an output buffer queue provided in an embodiment of the present application;

[0036] FIG10 is a schematic diagram of a buffer setting method of an interface provided in an embodiment of the present application;

[0037] FIG11 is a schematic diagram of a back pressure transmission relationship within a network node provided in an embodiment of the present application;

[0038] FIG12 is a schematic diagram of a back pressure transmission relationship between network nodes provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. In the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, where a, b and c can be single or multiple. In addition, in the embodiments of the present application, words such as "first" and "second" do not limit the quantity and order.

[0040] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0041] The present application is described in detail below with reference to the accompanying drawings and embodiments:

[0042] As shown in Figure 1, a 2D-Mesh network 100 is a common network structure with advantages such as simplicity, ease of implementation, low latency, high bandwidth, and good scalability. Generally, a 2D-Mesh network 100 can be viewed as a two-dimensional grid-like network structure, consisting of multiple communication devices 110. Each communication device 110 can serve as a network node (hereinafter collectively referred to as a network node), and has fixed location coordinates within the 2D-Mesh network 100. These location coordinates can be the horizontal and vertical coordinates of the communication device 110 serving as a network node within the 2D-Mesh network, typically expressed as (X, Y). Operators can set corresponding horizontal and vertical coordinates for each network node based on a defined two-dimensional coordinate system, thereby setting fixed location coordinates for each network node. For example, still as shown in Figure 1, the network node in the upper left corner of the 2D-Mesh network can be used as the origin (0, 0), with the direction of the network nodes to the right of this network node considered the X direction, and the direction of the network nodes below this network node considered the Y direction, to set corresponding location coordinates for each network node in the 2D-Mesh network. Of course, the above-mentioned method of setting the position coordinates is only an exemplary implementation provided for ease of understanding. In specific implementation, corresponding position coordinates can be set for each network node in the 2D-Mesh network according to actual needs.

[0043] Furthermore, in a 2D-Mesh network, connections between network nodes are achieved through edges. Each communication device 110 is directly connected to up to four adjacent network nodes in four directions (up, down, left, and right). Among them, the network node above a network node can be called the north neighbor of the network node, the network node below can be called the south neighbor of the network node, the network node to the left can be called the west neighbor of the network node, and the network node to the right can be called the east neighbor of the network node. In a 2D-Mesh network, data transmission is also carried out through the edges between network nodes. When a network node needs to transmit data to an adjacent network node, it can choose to transmit through the edges in the north, south, west, or east direction, which has advantages such as low latency and high bandwidth. Therefore, 2D-Mesh networks are widely used in different application scenarios. Among them, the product form of 2D-Mesh networks is also different in different application scenarios. For example, as shown in Figure 2, in a network-on-chip (NOC) scenario, a 2D-Mesh network is generally composed of multiple bare chips 210 (chiplets) with switching / routing functions set on a chip 200, and the bare chips 210 on the periphery of the chip 200 can be coupled with one or two execution units set on the chip 200, and each execution unit can exchange data through the 2D-Mesh network. Among them, each bare chip 210 can be regarded as an independent communication device to serve as a network node in the 2D-Mesh network. The above-mentioned chip 200 can be a switch chip, a router chip, a computer chip or other types of system on chip (SOC). As shown in Figure 3, in a device networking scenario, a 2D-Mesh network is generally composed of multiple switching devices 310, and each switching device 310 on the periphery of the 2D-Mesh network can be coupled with one or two terminal devices 320 to form a communication system 300. Each terminal device 320 can form a 2D-Mesh network through multiple switching devices 310 for data exchange. Each switching device is an independent communication device and can be used as a network node in a 2D-Mesh network. The switching device 310 can be a device with data exchange capabilities such as a switch or a router.

[0044] In current 2D-Mesh networks, packet routing primarily involves deterministic routing and adaptive routing. Deterministic routing uses fixed network nodes to forward packets with the same source and destination addresses. Adaptive routing determines the next-hop network node for a packet based on the congestion status of each network node's interfaces. Deterministic routing uses fewer hops than adaptive routing, resulting in higher transmission efficiency when the data volume is small. However, when the data volume is large, deterministic routing may not cause routing deadlocks. However, the buffer queues of the corresponding interfaces in network nodes using deterministic routing are prone to congestion, reducing packet transmission efficiency. Adaptive routing, on the other hand, allows packets to be transmitted to the destination node by selecting another network node when a node's interface is congested. Therefore, to improve packet transmission efficiency, 2D-Mesh networks often utilize both deterministic and adaptive routing to transmit packets. However, current network nodes typically use a single buffer queue to store both deterministic and adaptive routing packets, making adaptive routing prone to routing deadlocks. When routing deadlocks occur, packets using deterministic routing are also affected. For example, as shown in FIG4 , taking four network nodes as an example, each network node has an interface in the north, south, west or east direction (i.e., N interface, S interface, W interface and E interface) and a local interface LOC. Data packets P0, P1, P2, and P3 are stored in the buffer queues of network nodes R0, R1, R2, and R3, respectively. Among them, the destination of data packet P0 is R2, the destination of data packet P1 is R3, the destination of data packet P2 is R0, and the destination of data packet P3 is R1, so that the four network nodes form a routing loop. If the buffer queues of the four network nodes do not have extra space to store another data packet at this time, each network node will send a back pressure signal to its own previous hop network node to instruct the previous hop network node to stop transmitting the data packet. Based on this, on the basis of the above-mentioned four network nodes forming a routing loop, the above-mentioned four data packets are all affected by the back pressure signal, so that the four data packets cannot apply for the buffer queue of the next hop network node, forming a circular dependency, unable to move forward, forming a routing deadlock, and causing network paralysis.

[0045] In order to solve the above problem, as shown in Figure 5, when using a combination of adaptive routing and deterministic routing to transmit data packets, the formation of routing loops can be avoided by limiting the packet steering method of some network nodes in the 2D-Mesh network, thereby avoiding the formation of circular dependencies between data packets of multiple network nodes of adaptive routing, so as to solve the routing deadlock problem. In which, each dotted arrow in Figure 5 is a prohibited steering direction for the data packet, and each solid arrow is a steering direction for the data packet. In one example, as shown in part (a) of Figure 5, the network nodes in the 2D-Mesh network can use XY routing to transmit data packets, thereby solving the routing deadlock problem. In which, when using XY routing to transmit data packets, the data packet is first transmitted along the X coordinate direction, and then the data packet is transmitted along the Y coordinate direction. At the same time, the data packet transmitted in the Y coordinate direction is prohibited from steering to the X coordinate direction to avoid the formation of routing loops by multiple routing nodes. In another example, as shown in part (b) of Figure 5, network nodes in a 2D-Mesh network can select a west-first steering model to transmit data packets. That is, when transmitting data packets, each network node in the 2D-Mesh network can use the steering direction of W to N->N to E->E to S to transmit data packets, and prohibit the use of the steering direction of S to W to transmit data packets. Alternatively, the steering direction of W to S->S to E->E to N can be used to transmit data packets, and prohibit the use of the steering direction of N to W to transmit data packets. Where N represents north, S represents south, E represents east, and W represents west. The above four directions can be defined by the operator according to the actual situation of the 2D-Mesh network. In another example, as shown in part (c) of Figure 5, network nodes in a 2D-Mesh network can also select a negative-first steering model. That is, when transmitting data packets, each network node in the 2D-Mesh network can use the steering direction of W to S->S to E->E to N to transmit data packets, and prohibit the use of the steering method of N to W to transmit data packets. Alternatively, a steering direction of S to W->W to N->N to E can be used to transmit data packets, and a steering direction of E to S can be prohibited from being used to transmit data packets. In another example, as shown in part (d) of Figure 5 , network nodes in a 2D-Mesh network can also select a northbound subsequent steering model, that is, when each network node in the 2D-Mesh network transmits a data packet, a steering direction of E to S->S to W->W to N can be used to transmit data packets, and a steering direction of N to E can be prohibited from being used to transmit data packets. Alternatively, a steering direction of W to S->S to E->E to N can be used to transmit data packets, and a steering direction of N to W can be prohibited from being used to transmit data packets. In another example, as shown in part (e) of Figure 5 , network nodes in a 2D-Mesh network can also select an even-odd steering model.For example, in a 2D-Mesh network, when odd-numbered nodes transmit data packets, they can use the W to N->N to E->E to S steering direction to transmit data packets, and prohibit the use of the S to W steering direction. Alternatively, they can use the N to S->S to E->E to N steering direction to transmit data packets, and prohibit the use of the N to W steering direction to transmit data packets. When even-numbered nodes transmit data packets, they can use the S to W->W to N->N to E steering direction to transmit data packets, and prohibit the use of the E to S steering direction to transmit data packets. Alternatively, they can use the N to W->W to S->S to E steering direction to transmit data packets, and prohibit the use of the E to N steering direction to transmit data packets. Although the use of the above-mentioned various steering models can solve the routing deadlock problem, it limits the steering directions of data packets, resulting in uneven routing of network nodes and affecting multipath selection.

[0046] In another solution, you can also choose to set up a virtual channel to solve the routing deadlock problem. The method of setting up a virtual channel (VC) avoids deadlock by dividing the physical channel into virtual channels of different dimensions. When encountering a loop, deadlock is avoided by switching the virtual channel (or escape channel). For the existing virtual channel technical solutions, certain steering restrictions are still required in the 2D-Mesh network to achieve adaptive deadlock-free routing. For example, when setting up a virtual channel, you can also use the method of parts (b), (c) and (d) in Figure 5 to set the prohibited steering direction of the data packet. The embodiments of this application will not be described in detail here. Because a certain steering direction is restricted, the method of setting up a virtual channel also has the problem of uneven load between virtual channels, affecting the selection of multiple paths, and also increases the area and power consumption.

[0047] During the actual transmission of data packets in a 2D-Mesh network, data packets are primarily transmitted via deterministic routing. Data packets using adaptive routing account for a very small portion of the actual transmission process, but adaptive routing can easily cause routing deadlock. Therefore, to better address the aforementioned issues, embodiments of the present application provide a communication data exchange method that does not require limiting the direction in which data packets are redirected, thereby resolving the routing deadlock issue. This communication data exchange method can set an input buffer within a memory for each interface of a network node. Each input buffer includes multiple storage areas, each storage area being used to store multiple input buffer queues for the same destination interface, and each input buffer queue being used to store data packets of the same routing type. The aforementioned destination interface is any interface other than the interface through which the data packet is input. The aforementioned routing types include deterministic routing and adaptive routing, and the number of input buffer queues corresponding to different routing types may also differ. For example, data packets using adaptive routing can be stored using a single input buffer queue, data packets using deterministic routing can be stored using a single input buffer queue, or data packets using multiple input buffer queues corresponding to different redirection directions can be stored based on the data packet's redirection direction. By isolating the data packets, adaptive routing packets and deterministic routing packets can be stored in different input buffer queues, so that the adaptive routing packets can have sufficient storage space to store them, thereby avoiding mutual interference between the adaptive routing packets and the deterministic routing packets. Compared with the existing method of storing adaptive routing packets and deterministic routing packets in the same input buffer queue, the problem of routing deadlock during data packet transmission can be better avoided. The above method can be executed by a processor inside the network node. The above processor can be a central processing unit (CPU), a general-purpose processor, a network processor (NP), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or a system on chip (SoC), or any combination thereof. In specific implementation, the type of processor can be selected according to the actual application scenario, and the embodiments of the present application do not impose specific restrictions on this. In the memory, an input buffer can be configured for each interface of the network node, or an input buffer and an output buffer can be configured simultaneously. For example, taking the input buffer of the network node as an example, as shown in Figure 6, the specific execution process of the method is as follows.

[0048] S601: The processor obtains first configuration information, where the first configuration information includes an indication of a storage mode of an input buffer queue.

[0049] In one embodiment, an operator may write the first configuration information into a non-volatile memory in the form of computer program instructions. After the network node is powered on, the processor within the network node may read and execute the corresponding computer program instructions from the non-volatile memory to obtain the first configuration information. The instructions in the first configuration information may instruct the processor to configure multiple input buffers within the memory, each input buffer corresponding to one of the multiple interfaces. Each input buffer includes multiple first storage areas, each first storage area being used to store multiple input buffer queues for the same destination interface. Each input buffer queue is used to store packets of the same routing type. The destination interface is any interface other than the interface through which the packet is input. The routing types include deterministic routing and adaptive routing. Deterministic routing uses fixed network nodes to forward packets. Adaptive routing determines the next-hop network node for a packet based on the congestion status of each interface of the network node. In a specific implementation, deterministic routing may employ shortest path routing, i.e., Manhattan routing (MHD). Common algorithms include the XY routing algorithm and the YX routing algorithm, which are not specifically limited in the present embodiment. The adaptive routing described above can determine the congestion status of each interface of the network node based on the occupancy rate of the input buffer queue of each interface, and then use the network node connected to the interface with the lowest buffer space occupancy rate as the next-hop network node. Of course, the adaptive routing can also determine the next-hop network node based on the traffic flow, transmission delay, link status, etc. between network nodes, and the embodiments of the present application do not impose specific limitations on this.

[0050] S602: The processor configures a plurality of input buffers in the memory according to the first configuration information.

[0051] Each input buffer corresponds to one of the multiple interfaces, each input buffer includes multiple first storage areas, each first storage area is used to store multiple input buffer queues of the same destination interface, and each input buffer queue corresponds to a routing type.

[0052] In one embodiment, after the processor within the network node obtains the first configuration information, it may first divide the memory into multiple input buffers. Each input buffer corresponds to one of the multiple interfaces. Furthermore, each input buffer may be further divided into multiple first storage areas. Each first storage area is used to store multiple input buffer queues for the same destination interface, with each input buffer queue corresponding to a packet of a different routing type.

[0053] S603: The processor obtains a first data packet received by a first interface among the multiple interfaces.

[0054] In the process of transmitting the data packet, the first interface may be any one of the multiple interfaces of the network node.

[0055] S604: The processor stores the first data packet into a corresponding input buffer queue in the memory according to the routing type and destination interface of the first data packet.

[0056] In one embodiment, the processor can determine the routing type of the first data packet based on the source address, destination address and location information (i.e., location coordinates) of the first data packet. In one embodiment, the processor can determine the destination interface of the first data packet based on the destination address of the first data packet and the location information of the current network node, and then store the first data packet in the corresponding input buffer queue in the memory based on the determined routing type and destination interface. In one example, the processor in each network node can determine the routing type of the first data packet through a first lookup table. If the first data packet is a data packet of deterministic routing, the processor can store the first data packet in the input buffer queue corresponding to the deterministic routing. If the first data packet is not a data packet of deterministic routing, the processor can store the first data packet in the input buffer queue corresponding to the adaptive routing. The above-mentioned first lookup table may contain routing types corresponding to search keywords composed of different source addresses and destination addresses and the location information of the current network node. After the processor obtains the first data packet, it can search the first lookup table based on the keywords composed of the source address, destination address and location information of the current network node to determine the routing type of the first data packet. Of course, the processor of each network node can also execute a corresponding computer program in the network node to execute a routing algorithm to perform a calculation based on the source address, destination address, and location information of the current network node of the first data packet to determine whether the first data packet is a data packet with deterministic routing. Exemplarily, taking XY routing as an example, the processor can compare the location coordinates of the current network node with the location coordinates of the source address and the location coordinates of the destination address to determine whether the first data packet is a data packet with deterministic routing. For example, the location coordinates of the network node corresponding to the source address of the first data packet are (X1, Y1), the location coordinates of the current network node are (X2, Y2), and the location coordinates of the network node corresponding to the destination address of the first data packet are (X3, Y3). Among them, X3>X2>X1, Y3>Y2>Y1. Therefore, it can be determined that the data packet is not a data packet with deterministic routing and should be stored in the input buffer queue of the adaptive routing. Of course, the above is only an example given in the embodiment of the present application. The specific calculation method of the processor can be adaptively adjusted according to the type of routing algorithm, and the embodiment of the present application will not be described in detail here.

[0057] In one example, the processor within each network node can determine the destination interface of the first data packet using a second lookup table. The second lookup table can contain destination interfaces corresponding to search keywords composed of different destination addresses and the location information of the current network node. After receiving the first data packet, the processor can use the destination address of the first data packet and the location information of the current network node to form a search keyword to search the second lookup table for the corresponding destination interface. Of course, the destination interface of the first data packet can also be calculated based on the destination address of the first data packet and the location information of the current network node. For example, based on Figure 1, taking XY routing as an example, the processor can compare the location coordinates of the current network node with the location coordinates of the network node corresponding to the destination address to determine the destination interface. For example, the location coordinates of the network node corresponding to the destination address of the first data packet are (Xd, Yd), and the location coordinates of the current network node are (X1, Y1). If Xd is greater than X1, the first data packet should be transmitted in the direction of the X coordinate. If the X coordinate direction is the direction of the E interface of the network node, the destination interface of the first data packet is the E interface. Of course, the above calculation method is only an example given in the embodiment of the present application. When it is implemented specifically, the calculation method of the destination interface of each data packet can be adjusted according to the routing algorithm and coordinate system construction method actually used, and the embodiment of the present application will not be repeated here. Through the above method, the input buffer of each interface can isolate and store the input buffer queues of each destination interface, and the input buffer queues of each input buffer can be isolated and stored according to the routing type, thereby solving the routing deadlock problem. Exemplarily, as shown in Figure 7, taking the input buffer (ingress buffer, IB) corresponding to the N interface of the network node as an example, the input buffer stores input buffer queues with destination interfaces of S interface, W interface, E interface and local interface. Among them, the input buffer queue of each interface is divided into an input buffer queue of deterministic routing (i.e., MHD queue) and an input buffer queue of adaptive routing (i.e., AR queue) according to the routing type. Among them, the network node can send a back pressure signal to the upstream network node based on the MHD queue, and can also respond to the back pressure signal sent by the downstream network node. The AR queue does not respond to the back pressure signal generated by the downstream network node, nor does it generate a back pressure signal to the upstream network node.

[0058] In one embodiment, when a network node transmits a data packet using a deterministic routing method, the MHD queue can either send a back pressure signal to the upstream network node based on the cache status of the input buffer queue to instruct the upstream network node to stop transmitting the data packet, or it can respond to the back pressure signal sent by the downstream network node and stop transmitting the data packet. At this time, if the MHD queue of a destination interface in the input buffer corresponding to the interface of the input data packet simultaneously stores data packets with different steering directions, then when the destination interface receives the back pressure signal, the data packets with other steering directions in the MHD queue will stop transmitting, which has a great impact on the transmission efficiency of the data packet. Therefore, as shown in Figure 7, the MHD queue of each destination interface can also be divided into multiple input buffer queues with different steering directions, such as the straight queue I, left turn queue L and right turn queue R in the MHD queue in Figure 7. Among them, the above-mentioned steering direction is the direction of the network node corresponding to the destination address of the data packet relative to the destination interface of the current network node. The above-mentioned multiple input buffer queues with different steering directions can be stored through different sub-storage areas in the corresponding storage area. Through the above method, the input buffer queue of the deterministic routing can be divided into multiple input buffer queues with different steering directions, thereby preventing the back pressure signal of a certain destination interface from affecting the transmission of data packets of other destination interfaces, reducing the impact of network congestion, and improving the transmission efficiency of data packets. In particular, when the above method is executed, the steering direction of the first data packet can be determined based on the destination address of the first data packet and the location information of the current network node. Then, based on the determined steering direction, the first data packet is stored in the corresponding input buffer queue. In one example, the processor in the network node can determine the steering direction of the data packet through a third lookup table. In particular, the above third lookup table can include steering directions corresponding to search keywords composed of different destination addresses and the location information of the current network node. After the processor obtains the destination address of the first data packet, it can use the destination address of the first data packet and the location information of the current network node to form a search keyword to obtain the corresponding steering direction from the third lookup table. In another example, the processor can also directly calculate and determine the steering direction of the first data packet based on the destination address of the first data packet and the location information of the current network node.Among them, based on the coordinate system in FIG. 1, taking the data packet with the destination interface being the S interface in the input buffer of the N interface of a certain network node as an example, if the position coordinates of the current network node are (X0, Y0), and the position coordinates of the destination network node corresponding to the destination address of the data packet are (Xd, Yd), and the deterministic routing method is the XY routing, then the data packet can be stored in the input buffer queues with different turning directions in the following way: If Xd > X0, it means that this data packet turns left at the next-hop network node, so this data packet is stored in the left-turn queue L; if Xd < X0, it means that this data packet turns right at the next-hop network node, so this data packet is stored in the right-turn queue R; if Xd = X0, it means that this data packet goes straight at the next-hop network node, so this data packet is stored in the straight queue I. Among them, because the positions of the network nodes in the 2D-Mesh network are different, the MHD queues of each network node can be divided into input buffer queues with different turning directions according to the actual executable turning directions of the data packets. For example, in FIG. 1, the MHD queue with the destination interface being the S interface in the input buffer of the N interface of the network node with the position coordinates (0, 0) can only be divided into the straight queue I and the left-turn queue L. The MHD queue with the destination interface being the S interface in the input buffer of the N interface of the network node with the position coordinates (3, 0) can only be divided into the straight queue I and the right-turn queue R. The MHD queue with the destination interface being the S interface in the input buffer of the N interface of the network node with the position coordinates (1, 0) is divided into the straight queue I, the left-turn queue L, and the right-turn queue R.

[0059] Of course, the above method is only an example given in the embodiments of this application. The judgment conditions in actual implementation can be adaptively adjusted according to the actually adopted deterministic routing algorithm, and the embodiments of this application will not elaborate here.

[0060] In one embodiment, as still shown in FIG7 , each first storage area can also be used to store an input buffer queue for converting adaptive routing to deterministic routing (i.e., the AR_back queue in FIG7 ). On this basis, the first data packet can also include a conversion identifier for converting adaptive routing to deterministic routing. A conversion identifier bit can be set in the message header of the data packet, and the length of the conversion identifier bit is 1 bit. When the data packet is a data packet converted from adaptive routing to deterministic routing, the conversion identifier bit can be 1. When the data packet is not a data packet converted from adaptive routing to deterministic routing (i.e., the data packet is a data packet of deterministic routing or a data packet of adaptive routing), the conversion identifier bit can be 0. In one example, if a data packet is first transmitted using adaptive routing and is transmitted to the current network node, the current network node interacts with the next-hop network node that performs deterministic routing to determine that the input buffer queue of the next-hop network node has sufficient storage space to store the data packet, then the current network node can modify the conversion flag in the data packet from 0 to 1, and store the data packet in the input buffer queue of the corresponding destination interface (i.e., AR_back queue) based on the source address, destination address, conversion flag, and location information of the current network node, so as to transmit the data packet to the target network node using deterministic routing. Among them, the current network node can send a request message to the next-hop network node regularly or irregularly to obtain the storage space occupancy rate of the input buffer queue of the next-hop network node. When the storage space occupancy rate of the input buffer queue of the next-hop network node is lower than a set threshold, it is determined that the input buffer queue of the next-hop network node has sufficient storage space to store the data packet. In another example, when the traffic of the interface connected to the next-hop network node that performs deterministic routing exceeds a set threshold, the current network node can also change the conversion flag to 1. During specific implementation, the operator can choose the determination method to be used according to actual needs, and the embodiments of the present application do not impose specific restrictions on this. Through the above method, although the data packets of the AR_back queue and the MHD queue are subsequently transmitted in a deterministic routing manner, the two queues are isolated, which can avoid the AR_back queue from affecting the MHD queue. In addition, once a data packet enters the AR_back queue, it will not be allowed to enter the AR queue subsequently, and the data packet can only be subsequently transmitted through deterministic routing. Among them, the deterministic routing method can be determined based on the routing algorithm actually used, and the embodiments of the present application will not be described here. Furthermore, when the data packet contains a conversion flag bit, on the basis of the aforementioned routing type confirmation method, the processor also needs to identify the conversion flag bit to avoid the data packets in the AR_back queue from being stored in the MHD queue.

[0061] In one embodiment, still as shown in FIG7 , the AR_back queue may also include input buffer queues of multiple steering directions. The processor may determine the steering direction of the data packet at the next-hop network node based on the destination address of the data packet and the location information of the current network node, and then store the data packets of the same steering direction in the same input buffer queue. The above process may also refer to the data packet storage method of the input buffer queues of multiple steering directions in the MHD queue to store the data packets in the input buffer queues of various steering directions in the AR_back queue, and the embodiments of the present application will not be described in detail here. The AR_back queue may respond to the back pressure signal of the downstream network node, but does not generate a back pressure signal. In the above manner, the data packets of different steering directions in the AR_back queue may also be prevented from influencing each other, thereby preventing the transmission of data packets of other steering directions from being affected when data packets of a certain steering direction are congested, thereby improving the transmission efficiency of the data packets.

[0062] In one embodiment, if each interface of the network node also includes an output buffer, as shown in Figure 8, the above-mentioned first configuration information may also include an indication of the storage method of the output buffer queue. When the processor in the network node executes S602, it may also configure multiple output buffers in the memory according to the first configuration information. Each output buffer includes multiple second storage areas. Each output buffer can be used to store the output buffer queue of an interface, and each second storage area is used to store the output buffer queue of deterministic routing or the output buffer queue of adaptive routing. On this basis, the above-mentioned method may further include the following steps after S604:

[0063] S605: The processor obtains a second data packet to be output by a second interface among the multiple interfaces.

[0064] The processor in the network node can obtain a data packet with the second interface as the destination interface (i.e., the second data packet) from the corresponding storage area in the input buffer of the interface other than the second interface according to the first-in-first-out principle. The data packet can be a data packet of deterministic routing or a data packet of adaptive routing.

[0065] S606: The processor stores the second data packet into an output buffer queue corresponding to the second interface in the memory according to the routing type of the second data packet.

[0066] Among them, the memory also includes multiple output buffers. Each output buffer corresponds to one interface among the multiple interfaces. Each output buffer includes multiple second storage areas. Each second storage area is used to store the output buffer queue of deterministic routing or the output buffer queue of adaptive routing. Because the embodiment of the present application divides storage areas for data packets of different destination interfaces in the input buffer of each interface, and each storage area is divided into multiple input buffer queues according to the routing type, the processor can directly read the second data packet to be output from the memory according to the correspondence between the data packet and the input buffer queue, without having to reconfirm the routing type of the data packet based on the source address, destination address and location information of the current network node of the data packet, thereby improving the transmission efficiency of the data packet.

[0067] In one embodiment, as shown in Figure 9, the output buffer queue of the deterministic routing includes multiple output buffer queues with different redirection directions. The processor can store the data packets in the input buffer queue into the output buffer queue corresponding to the deterministic routing of the second interface based on the routing type and redirection direction of each data packet.

[0068] In the above manner, as shown in FIG10 , when each interface of the network node includes only one input buffer (as shown in FIG10 b ), the controller can use the first-in-first-out principle to output each data packet in the input buffer queue through the corresponding destination interface. When each interface of the network node includes both an input buffer and an output buffer (as shown in FIG10 a ), the data packets of each destination interface can be transferred from the input buffer to the output buffer of the corresponding destination interface and then output according to the first-in-first-out principle.

[0069] It is understandable that the processor may configure the aforementioned multiple input buffers and / or the aforementioned multiple output buffers in the memory according to the configuration information; the processor may also perform the configuration action by default without relying on the configuration information.

[0070] In one example, in order to better understand the back pressure transmission relationship between the input buffer and output buffer of the same network node, the embodiment of the present application takes a network node in a 2D-Mesh network as an example, and shows the back pressure relationship between the input buffer and the output buffer of each interface (including N interface, S interface, W interface, E interface and local interface) inside the network node. Among them, taking the output buffer (egress buffer, EB) of the E interface as an example, its back pressure transmission relationship with the input buffer (ingress buffer, IB) of the N interface, S interface, W interface and local interface is shown in Table 1 and Figure 11. It can be seen from Table 1 and Figure 11 that in the input buffer queue of each interface, the input buffer queues in each direction corresponding to the deterministic route with the destination interface being the E interface and the output buffer queues in each direction corresponding to the deterministic route in the output buffer queue of the E interface all have a back pressure transmission relationship. It can be seen from the above method that after the MHD queue is subdivided according to the steering direction, there is no need to limit the steering direction of the data packet. At the same time, if a certain output buffer queue of the E interface forms back pressure with the input buffer queue corresponding to other interfaces, it will not affect the output buffer queues of other directions of the E interface and the input buffer queues of other directions of the other interfaces, reducing the impact of network congestion and improving the transmission efficiency of data packets.

[0071] Table 1

[0072] Furthermore, taking network nodes 1 and 2 in a 2D-Mesh network as examples, the back pressure relationship between the output buffer EB of network node 1's E interface and the input buffer IB of network node 2's W interface is shown in Table 2 and Figure 12. As can be seen from Table 2 and Figure 12, after being transmitted to the IB of network node 2's W interface, packets in the AR queue in the EB corresponding to network node 1's E interface may continue to be stored in the AR queue, or they may be converted into deterministic routing packets and stored in the AR_back queue. Packets in the right-turn queue R for deterministic routing in the EB corresponding to network node 1's E interface may be stored in the straight queue I and left-turn queue L in the MHD queue with the destination interface S, or in the left-turn queue L in the MHD queue with the destination interface E, in network node 2. Therefore, a back pressure transfer relationship may exist between these packets and the input buffer queues for deterministic routing in the IB corresponding to network node 2's W interface, with the destination interfaces being the E and S interfaces. Similarly, there may be a back pressure transmission relationship between the straight queue I in the EB corresponding to the E interface of the network node 1 and the input buffer queue of the deterministic route with the destination interface being the E interface and the local interface in the IB corresponding to the W interface of the network node 2. There may be a back pressure transmission relationship between the left turn queue L in the EB corresponding to the E interface of the network node 1 and the input buffer queue of the deterministic route with the destination interface being the N interface and the E interface in the IB corresponding to the W interface of the network node 2. Among them, the above-mentioned various back pressure transmission relationships can be adjusted according to the connection relationship between the network nodes and the possible transmission direction of the data packet, and the embodiments of the present application will not be described in detail here. It can be seen from the above method that after the MHD queue is subdivided according to the steering direction, there is no need to restrict the steering direction of the data packet. In addition, even if multiple input buffer queues of the downstream network node form back pressure with a certain output buffer queue corresponding to the upstream node, it will not affect the output buffer queues of other steering directions of the upstream network node, and can also reduce the impact caused by the network congestion problem, thereby improving the transmission efficiency of the data packet.

[0073] Table 2

[0074] In one implementation, the embodiment of the present application further provides a network node, which may be a switching device such as a switch or a router.

[0075] The network node may execute the communication data exchange method in any possible implementation manner in Figures 7 to 10. The embodiments of the present application will not be described in detail here.

[0076] In one embodiment, the present application also provides a chip comprising multiple dies. The multiple dies form a 2D-Mesh network, and each die serves as a node in the aforementioned network. The chip may be a system-on-chip (SoC), and the 2D-Mesh network comprised of the multiple dies may be a network-on-chip (NOC) module on the SoC. The NOC module may be coupled to multiple execution units on the SoC.

[0077] In one embodiment, the present application also provides a computer-readable storage medium having computer program instructions stored therein. When the computer program instructions are executed by a processor, the above-mentioned communication data exchange method can be implemented. The computer-readable storage medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)), etc., and the present application does not impose specific limitations on this.

[0078] The memory involved in the embodiments of the present application may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that memory of the systems and methods described herein is intended to comprise, but not be limited to, these and any other suitable types of memory.

[0079] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0080] Those skilled in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0081] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0082] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, etc. can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of modules is only a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0083] Modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules, that is, they may be located on a single device or distributed across multiple devices. Some or all of these modules may be selected to achieve the objectives of this embodiment based on actual needs.

[0084] In addition, the functional modules in the various embodiments of the present application may be integrated into one device, or each module may exist physically separately, or two or more modules may be integrated into one device.

[0085] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing computer program instructions on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode to another website, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more media that can be integrated. The above is merely a specific implementation of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A communication data exchange method, characterized in that: The method is applied to a network node, the network node comprising multiple interfaces, a memory, and a processor; wherein the processor is coupled to the memory and the multiple interfaces respectively, and the method is executed based on the processor, the method comprising: Obtaining a first data packet received by a first interface among the multiple interfaces; The first data packet is stored in the corresponding input buffer queue in the memory according to the routing type and destination interface of the first data packet; wherein the memory includes multiple input buffers, each input buffer corresponds to one interface among the multiple interfaces, each input buffer includes multiple first storage areas, each first storage area is used to store multiple input buffer queues of the same destination interface, and each input buffer queue corresponds to a routing type, and the destination interface is any interface among the multiple interfaces except the input interface of the data packet; the routing types include deterministic routing and adaptive routing, the deterministic routing is a routing that uses a fixed network node to forward data packets with the same source address and destination address, and the adaptive routing is a routing that determines the next-hop network node according to the congestion status of each interface among the multiple interfaces.

2. The method according to claim 1, characterized in that The method further comprises: determining a routing type of the first data packet according to the source address, the destination address, and the location information of the network node of the first data packet; The destination interface of the first data packet is determined according to the destination address of the first data packet and the location information of the network node.

3. The method according to claim 1 or 2, characterized in that The input buffer queue of the deterministic routing includes a plurality of input buffer queues with different steering directions; The steering direction is the direction of the destination network node corresponding to the destination address of the data packet relative to the destination interface of the network node; The method further comprises: determining a direction of the first data packet according to a destination address of the first data packet and location information of the network node; According to the steering direction, the first data packet is stored in a corresponding input buffer queue.

4. The method according to any one of claims 1 to 3, characterized in that The first storage area is further used to store an input buffer queue for converting adaptive routing to deterministic routing; the first data packet also includes a conversion identifier for converting adaptive routing to deterministic routing; the method further includes: The first data packet is stored in a corresponding input buffer queue according to the source address, destination address, conversion identifier and location information of the current network node of the first data packet.

5. The method according to any one of claims 1 to 4, characterized in that The method further comprises: Obtain a second data packet to be output from a second interface among the multiple interfaces; the second data packet is a data packet whose destination interface is the second interface, obtained from a corresponding storage area in an input buffer of an interface other than the second interface; The second data packet is stored in the output buffer queue corresponding to the second interface in the memory according to the routing type of the second data packet; wherein the memory includes multiple output buffers, each of the output buffers corresponds to one of the multiple interfaces, each output buffer includes multiple second storage areas, and each of the second storage areas is used to store an output buffer queue of a routing type; the routing types include the deterministic routing and the adaptive routing.

6. The method according to claim 5, characterized in that The output buffer queue of the deterministic routing includes a plurality of output buffer queues with different steering directions; when the second data packet is a data packet of the deterministic routing, storing the second data packet in the corresponding output buffer queue in the memory according to the routing type of the second data packet specifically includes: The second data packet is stored in an output buffer queue corresponding to the deterministic route of the second interface according to the routing type and the steering direction of the second data packet.

7. The method according to any one of claims 1 to 6, characterized in that The method further comprises: Obtaining first configuration information; the first configuration information includes an indication of an input buffer queue storage mode; The plurality of input buffers are configured in the memory according to the first configuration information.

8. The method according to claim 6 or 7, characterized in that The first configuration information further includes an indication of an output buffer queue storage mode; and the method further includes: The plurality of output buffers are configured in the memory according to the first configuration information.

9. A communication device, characterized in that: The communication device includes multiple interfaces, a memory and a processor; wherein the processor is coupled to the memory and the multiple interfaces respectively; wherein the memory includes multiple input buffers, each input buffer corresponds to one interface among the multiple interfaces, each input buffer includes multiple first storage areas, each first storage area is used to store multiple input buffer queues of the same destination interface, and each input buffer queue corresponds to a routing type; the destination interface is any interface among the multiple interfaces except the input interface of the data packet; the routing types include deterministic routing and adaptive routing, the deterministic routing is a routing that uses a fixed communication device to forward data packets with the same source address and destination address; the adaptive routing is a routing that determines the next-hop communication device according to the congestion status of each interface among the multiple interfaces; Each input buffer queue is used to store data packets of a corresponding destination interface and a corresponding routing type.

10. The communication device according to claim 9, wherein: The processor is configured to store the first data packet into a corresponding input buffer queue in the memory according to a routing type and a destination interface of the first data packet. The communication device according to claim 10 , wherein: The processor is further configured to: determining a routing type of the first data packet according to a source address and a destination address of the first data packet and location information of the communication device; The destination interface of the first data packet is determined according to the destination address of the first data packet and the location information of the communication device.

12. The communication device according to any one of claims 9 to 11, characterized in that: The input buffer queue of the deterministic routing includes a plurality of input buffer queues with different steering directions; the steering direction is the direction of the communication device corresponding to the destination address of the data packet relative to the destination interface of the communication device; the processor is further configured to: determining a turning direction of the first data packet according to a destination address of the first data packet and location information of the communication device; According to the steering direction, the first data packet is stored in a corresponding input buffer queue.

13. The communication device according to any one of claims 9 to 12, characterized in that: Each of the first storage areas is further configured to store an input buffer queue for converting adaptive routing to deterministic routing; the first data packet also includes a conversion identifier for converting adaptive routing to deterministic routing; and the processor is further configured to: The first data packet is stored in a corresponding input buffer queue according to the source address, destination address, conversion identifier and location information of the current communication device of the first data packet.

14. The communication device according to any one of claims 9 to 13, characterized in that: The processor is further configured to: Obtain a second data packet to be output from a second interface among the multiple interfaces; the second data packet is a data packet whose destination interface is the second interface, obtained from a corresponding storage area in an input buffer of an interface other than the second interface; The second data packet is stored in the output buffer queue corresponding to the second interface in the memory according to the routing type of the second data packet; wherein the memory includes multiple output buffers; each of the output buffers corresponds to one of the multiple interfaces; each output buffer includes multiple second storage areas; each of the second storage areas is used to store an output buffer queue of a routing type; the routing types include the deterministic routing and the adaptive routing.

15. The communication device according to claim 14, wherein: The output buffer queue of the deterministic routing includes a plurality of output buffer queues with different steering directions; when the second data packet is a data packet of the deterministic routing, the processor is specifically configured to: The second data packet is stored in an output buffer queue corresponding to the deterministic route of the second interface according to the routing type and the steering direction of the second data packet.

16. The communication device according to any one of claims 9 to 14, characterized in that: The processor is further configured to: Obtaining first configuration information, the first configuration information including an indication of a storage mode of an input buffer queue; The plurality of input buffers are configured in the memory according to the first configuration information.

17. The communication device according to claim 16, wherein: The first configuration information further includes an indication of an output buffer queue storage mode; and the processor is further configured to: The plurality of output buffers are configured in the memory according to the first configuration information.

18. A chip, characterized in that: Comprising a plurality of bare chips; wherein the plurality of bare chips form a 2D-Mesh network, and each bare chip is a communication device according to any one of claims 9 to 17.

19. A computer-readable storage medium, characterized in that Computer program instructions are stored, and when the computer program instructions are executed by a processor, the method according to any one of claims 1 to 8 is implemented.

20. A communication system, characterized in that: It includes multiple switching devices, wherein the multiple switching devices form a 2D-Mesh network, and each of the switching devices is a communication device according to any one of claims 9 to 17.

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