Display panel and display device

Abstract

A display panel and a display device. The display panel comprises a display region, a binding region located on one side of the display region, and a first peripheral region located on the side of the binding region close to the display region. The display panel comprises a substrate, and a first conductive layer, a second conductive layer, a third conductive layer, and a cover plate which are sequentially arranged on the substrate, and an ink layer is arranged on the side of the cover plate close to the substrate. In the first peripheral region, the first conductive layer comprises a plurality of first signal lines, the second conductive layer comprises a plurality of second signal lines, and the plurality of first signal lines and the plurality of second signal lines are sequentially arranged and have the same extension direction. The orthographic projection of the ink layer on the substrate at least partially overlaps the first peripheral region. The orthographic projection of the third conductive layer on the substrate and the orthographic projection of the ink layer on the substrate cover the orthographic projections of the plurality of first signal lines and plurality of second signal lines on the substrate, and the orthographic projection of the third conductive layer on the substrate at least partially overlaps the orthographic projection of the ink layer on the substrate.

Description

Display panel and display device

[0001] This application claims priority to the Chinese patent application filed on March 4, 2024, with application number 202410245344.2 and invention name “Display Panel and Display Device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to display technology, and in particular to a display panel and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, and extremely fast response times. With the continuous advancement of display technology, display devices using OLEDs as light-emitting elements and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] However, there is a light leakage problem at the bottom frame of the display panel. Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] In a first aspect, an embodiment of the present disclosure provides a display panel, comprising a display area, a binding area located on one side of the display area, and a first peripheral area located on a side of the binding area close to the display area; the display panel comprises a substrate and a first conductive layer, a second conductive layer, a third conductive layer and a cover plate arranged in sequence on the substrate, and an ink layer is provided on a side of the cover plate close to the substrate; in the first peripheral area, the first conductive layer comprises a plurality of first signal lines, the second conductive layer comprises a plurality of second signal lines, and the plurality of first signal lines and the plurality of second signal lines are arranged in sequence and extend in the same direction; the orthographic projection of the ink layer on the substrate at least partially overlaps with the first peripheral area; the orthographic projection of the third conductive layer on the substrate and the orthographic projection of the ink layer on the substrate cover the orthographic projections of the plurality of first signal lines and the plurality of second signal lines on the substrate, and the orthographic projection of the third conductive layer on the substrate and the orthographic projection of the ink layer on the substrate at least partially overlap.

[0007] In an exemplary embodiment, in the first peripheral region and in a direction away from the display region, an overlapping dimension between the third conductive layer and the ink layer is a first overlapping dimension, and the first overlapping dimension is greater than or equal to 18 micrometers.

[0008] In an exemplary embodiment, the display panel further includes a second peripheral area located outside the display area and away from the binding area, and the first peripheral area is connected to the second peripheral area to surround the display area; the display panel further includes a first dam and a second dam, the first dam and the second dam respectively surround the display area, and the second dam is located on the side of the first dam away from the display area.

[0009] In an exemplary embodiment, the display panel further includes a fourth conductive layer, a first flat layer, a fifth conductive layer, a second flat layer, a third flat layer and a pixel definition layer, which are sequentially arranged on a side of the second conductive layer away from the substrate; the third conductive layer is located between the second flat layer and the third flat layer, and the pixel definition layer is located on a side of the third flat layer away from the substrate; the first dam includes a first dam base and a third dam base stacked together, and the third dam base is located on a side of the first dam base away from the substrate; the second dam includes a second dam base and a fourth dam base stacked together, and the fourth dam base is located on a side of the second dam base away from the substrate; the first dam base and the second dam base are located on the third flat layer; the third dam base and the fourth dam base are located on the pixel definition layer.

[0010] In an exemplary embodiment, the display panel further includes a second power line; and within the first peripheral region and the second peripheral region, the second power line extends to below a side of the second dam close to the substrate.

[0011] In an exemplary embodiment, the second power line is located in the fourth conductive layer; or, the second power line is located in the fourth conductive layer and the fifth conductive layer, and the second power lines in different conductive layers are connected through vias.

[0012] In an exemplary embodiment, the second power line includes a second conductive portion and a fourth conductive portion, the second conductive portion is located in the fourth conductive layer, and the fourth conductive portion is located in the fifth conductive layer; the second conductive portion, the fourth conductive portion and the second power line located in the third conductive layer are connected in sequence through vias, and the second power line located in the third conductive layer extends to the bottom of the second dam close to the side of the substrate.

[0013] In an exemplary embodiment, within the first peripheral region and in a direction away from the display area, an edge of the orthographic projection of the second conductive portion on the substrate is located within the range of the orthographic projection of the first flat layer on the substrate; and an edge of the orthographic projection of the fourth conductive portion on the substrate is located within the range of the orthographic projection of the second flat layer on the substrate.

[0014] In an exemplary embodiment, in the first peripheral region and in a direction away from the display region, an orthographic projection of the fourth conductive portion on the substrate covers an edge of an orthographic projection of the second conductive portion on the substrate.

[0015] In an exemplary embodiment, the third planar layer includes a third planar portion, and in the first peripheral region along a direction away from the display region, an orthographic projection of the third planar portion on the substrate covers an edge of an orthographic projection of the second planar layer on the substrate.

[0016] In an exemplary embodiment, a dimension between an edge of the third planar portion and an edge of the second planar layer in the first peripheral region in a direction away from the display region is a fifth overlap dimension, and the fifth overlap dimension is greater than or equal to 18 micrometers.

[0017] In an exemplary embodiment, a height of the third flat portion in a direction perpendicular to the substrate is greater than a height of the first dam in the direction perpendicular to the substrate.

[0018] In an exemplary embodiment, within the second peripheral region, the display panel further includes a connecting electrode, which is located on a side of the third flat layer away from the substrate, and is connected to the second power line. Within the second peripheral region, the connecting electrode extends below a side of the second dam close to the substrate.

[0019] In an exemplary embodiment, within the second peripheral area along a direction away from the display area, an edge of the orthographic projection of the fourth conductive layer on the substrate is located within the range of the orthographic projection of the first flat layer on the substrate; an edge of the orthographic projection of the fourth conductive layer on the substrate, an edge of the orthographic projection of the first flat layer on the substrate, an edge of the orthographic projection of the fifth conductive layer on the substrate, and an edge of the orthographic projection of the third conductive layer on the substrate are located within the range of the orthographic projection of the third dam base on the substrate.

[0020] In an exemplary embodiment, in the second peripheral region along a direction away from the display region, an orthographic projection of the third conductive layer on the substrate covers an edge of an orthographic projection of the fifth conductive layer on the substrate.

[0021] In an exemplary embodiment, within the second peripheral area, the first retaining dam further includes a fifth dam foundation, and the second retaining dam further includes a sixth dam foundation; the fifth dam foundation is located on a side of the third dam foundation away from the base, and the sixth dam foundation is located on a side of the fourth dam foundation away from the base.

[0022] In an exemplary embodiment, the display panel further includes a third dam, which surrounds the display area and is located on a side of the second dam away from the display area; the display panel further includes a second power line; within the first peripheral area and the second peripheral area, the second power line passes through the first dam and the second dam and extends to below a side of the third dam close to the substrate.

[0023] In an exemplary embodiment, the third retaining dam includes a seventh dam base, an eighth dam base, and a ninth dam base. The seventh dam base is located on the first flat layer, the eighth dam base is located on the second flat layer, and the ninth dam base is located on the third flat layer.

[0024] In an exemplary embodiment, a distance between the second dam and the third dam in a direction away from the display area is an eighth distance, the eighth distance being a minimum distance between opposing side surfaces of the second dam and the third dam, and the eighth distance is greater than or equal to 36 micrometers and less than or equal to 44 micrometers.

[0025] In a second aspect, an embodiment of the present disclosure provides a display device comprising the display panel as described above.

[0026] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0027] Summary of the Figures

[0028] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0029] FIG1 is a schematic diagram of the structure of a display panel in some technologies;

[0030] FIG2 is a partial cross-sectional schematic diagram of the display area in FIG1 ;

[0031] FIG3 is a cross-sectional view taken along line AA in FIG1 ;

[0032] FIG4 is a cross-sectional view taken along line AA in FIG1 in an exemplary embodiment;

[0033] FIG5 is a cross-sectional view taken along line AA in FIG1 in yet another exemplary embodiment;

[0034] FIG6 is a schematic diagram of a connection electrode damage in an exemplary embodiment;

[0035] FIG7 is a schematic diagram of a fifth overlap dimension in an exemplary embodiment;

[0036] FIG8 is a diagram showing the positional relationship between the first dam, the second dam, and the second power line boundary at the right frame in an exemplary embodiment;

[0037] FIG9 is a schematic diagram of the stacking of the first dam and the second dam at the right frame in an exemplary embodiment;

[0038] FIG10 is a cross-sectional view taken along line AA in FIG1 in yet another exemplary embodiment;

[0039] FIG11 is a diagram showing the positional relationship between the first dam, the second dam, the third dam, and the boundary of the second power line at the right frame in an exemplary embodiment;

[0040] FIG12 is a schematic diagram of stacking the first dam, the second dam, and the third dam at the right frame in an exemplary embodiment;

[0041] FIG13 is a schematic diagram of stacking the first dam, the second dam and the third dam at the right frame in yet another exemplary embodiment.

[0042] Details

[0043] The present disclosure describes a plurality of embodiments, but this description is exemplary rather than restrictive, and it will be apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present disclosure. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0044] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The disclosed embodiments, features, and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive solution defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any appropriate combination. Therefore, the embodiments are not subject to other limitations except for the limitations set forth in the appended claims and their equivalents. In addition, various modifications and changes may be made within the scope of protection of the appended claims.

[0045] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be understood by those skilled in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation on the claims. In addition, the claims to the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can readily understand that these orders can be changed and still remain within the spirit and scope of the disclosed embodiments.

[0046] In the drawings, the size of one or more components, thickness of layers, or regions may be exaggerated for clarity. In addition, the drawings schematically illustrate ideal examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0047] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. In this disclosure, "plurality" means two or more.

[0048] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0049] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0050] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0051] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0052] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0053] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0054] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0055] FIG1 is a schematic diagram of the structure of a display panel in some technologies. As shown in FIG1 , the display panel provided in this embodiment includes: a display area 100 and a non-display area located around the display area 100. The non-display area includes: a binding area 400 located on one side of the display area 100 along a second direction Y, a first peripheral area 200 located between the display area 100 and the binding area 400, and a second peripheral area 300 located outside the display area 100 and away from the binding area 400. The first peripheral area 200 and the second peripheral area 300 are connected and surround the display area 100. The display area 100 includes at least a plurality of regularly arranged pixel units. For example, the plurality of pixel units may be arranged in an array along a first direction X and a second direction Y, with the first direction X and the second direction Y intersecting. The plurality of pixel units are configured to display dynamic images or still images, and the display area 100 may be referred to as an active area (AA). In exemplary embodiments, the display panel may be deformable, such as being curled, bent, folded, or rolled up. The display panel includes an upper frame and a lower frame arranged relative to each other along the second direction Y, and a left frame and a right frame arranged relative to each other along the first direction X. The lower frame is the frame on the side where the binding area 400 is located, and the frame on the side opposite to the binding area 400 along the second direction Y can be called the upper frame. The right frame is located on the side of the left frame along the first direction X.

[0056] In an exemplary embodiment, the display area 100 may be in a quadrilateral, a circle, an ellipse, a polygon of other shapes, or an irregular shape, and the corners of the display area 100 may be rounded, which is not limited in the present disclosure.

[0057] In an exemplary embodiment, the first peripheral area 200 includes at least: a dam and a power line for transmitting voltage signals to a plurality of pixel units. The binding area 400 includes a circuit for connecting the signal lines of the plurality of pixel units to an external driving device. The second peripheral area 300 includes at least: a dam and a power line for transmitting voltage signals to a plurality of pixel units. The dams of the first peripheral area 200 and the second peripheral area 300 can form an annular structure surrounding the display area 100. The binding area 400 includes a plurality of bonding pads, which are configured to be bonded and connected to an external flexible printed circuit (FPC) or a chip on flex (COF).

[0058] As shown in FIG1 , the power lines may include a first power line 210 and a second power line 220. The first power line 210 may be connected to a high-voltage power line (VDD) of the display area 100 and configured to transmit a high-voltage signal to the multiple display units of the display area 100. The second power line 220 may be connected to a low-voltage power line (VSS) of the display area 100 to transmit a low-voltage signal to the multiple pixel units of the display area 100. The second power lines 220 may be distributed in the first peripheral area 200 and the second peripheral area 300. The second power lines 220 may surround the display area 100.

[0059] As shown in Figure 1 , the main portion of the first power line 210 in the first peripheral region 200 can extend along a first direction X. The first power line 210 also includes an extension, one end of which can be connected to the main portion, and the other end of which can be connected to a corresponding pad located in the bonding area 400 to receive a corresponding high-voltage signal. The second power line 220 in the first peripheral region 200 can be disposed on either side of the first power line 210 along the first direction X. The second power line 220 in the second peripheral region 300 can be disposed around the display area 100. One end of the second power line 220 in the first peripheral region 200 can be connected to the second power line 220 in the second peripheral region 300, and the other end of the second power line 220 in the first peripheral region 200 can be connected to a corresponding pad located in the bonding area 400 to receive a corresponding low-voltage signal. In an exemplary embodiment, the first direction X can be a direction extending parallel to the edge of the display area 100 on the side closest to the first peripheral region 200. That is, the first direction X is a direction extending parallel to the display area edge 110. In an exemplary embodiment, the display area 100 has an edge on the upper frame, lower frame, left frame and right frame respectively, and the display area edge 110 is the edge of the display area 100 on the lower frame side. In the embodiment of the present disclosure, "the direction away from the display area" or "the direction away from the edge of the display area" refers to the direction away from the display area range and perpendicular to the edge of the display area at the frame within the plane of the display area.

[0060] In an exemplary embodiment, the edge shapes of the display area at different frames vary with the shape of the display area, and may be, for example, straight lines, curves, broken lines, and the like, which is not limited in the present disclosure.

[0061] As shown in FIG1 , the dam may include a first dam 410 and a second dam 420. The second dam 420 may be located on a side of the first dam 410 away from the display area 100. Within the second peripheral area 300, the orthographic projection of the first dam 410 on the display panel may overlap with the orthographic projection of the second power line 220 on the base substrate. The orthographic projection of the second dam 420 on the display panel may overlap with the orthographic projection of the second power line 220 on the display panel, and the orthographic projection of the second dam 420 may surround the orthographic projection of the second power line 220 on the display panel. That is, within the second peripheral area 300, the second power line 220 may extend below the second dam 420. This is not limited in the present disclosure.

[0062] In an exemplary embodiment, the binding area 400 may include a fan-out area, a driver chip area, and a binding pin area, which are sequentially arranged in a direction away from the display area 100. The fan-out area is connected to the display area 100 and may include at least a plurality of data lead lines parallel to each other. For example, the first power line 210 may be connected to the high-voltage power line of the display area 100 by means of a fan-out trace, and the second power line 220 may also be connected to the low-voltage power line of the display area 100 by means of a fan-out trace. The driver chip area may include at least an integrated circuit (IC) configured to be connected to a plurality of data fan-out lines. The binding pin area may include at least a plurality of bonding pads configured to be bound and connected to an external flexible printed circuit (FPC).

[0063] In an exemplary embodiment, the binding area 400 may further include a bending area, which may be located between the fan-out area and the driving chip area, the bending area being connected to the fan-out area, and may include a composite insulating layer having a groove, configured to bend the binding area 400 to the back of the display area 100.

[0064] Figure 2 is a partial cross-sectional schematic diagram of the display area in Figure 1. Figure 2 illustrates the structure of a sub-pixel in the display area as an example. In this example, multiple transistors in the pixel driving circuit are of the same type. For example, the multiple transistors in the pixel driving circuit can all be low-temperature polysilicon thin-film transistors or oxide thin-film transistors.

[0065] In a direction perpendicular to the display panel, the display panel of the display area 100 may include: a circuit structure layer, a light-emitting structure layer, an encapsulation layer, a touch layer, a polarizer, and a cover plate, etc. As shown in FIG2 , the display panel of the display area 100 may include a substrate 10, and a buffer layer 501, a semiconductor layer, a first gate insulating layer 502, a first conductive layer 11, a first insulating layer 12, a second conductive layer 13, a second insulating layer 14, a fourth conductive layer 15, a first planar layer 16, a fifth conductive layer 17, a second planar layer 18, a third conductive layer 19, a third planar layer 20, an anode layer 503, a pixel definition layer 21, a cathode layer 504, a first inorganic layer 505, an organic layer 506, a second inorganic layer 507, and a touch layer 508. The polarizer 509 and the cover plate 24 may be sequentially attached to the side of the touch layer 508 away from the substrate 10. In an exemplary embodiment, the first conductive layer 11 may be referred to as a first gate layer, the second conductive layer 13 may be referred to as a second gate layer, the fourth conductive layer 15 may be referred to as a first source-drain electrode layer, the fifth conductive layer 17 may be referred to as a second source-drain electrode layer, and the third conductive layer 19 may be referred to as a third source-drain electrode layer.

[0066] In an exemplary embodiment, the circuit structure layer may include film layers between the buffer layer 501 and the third conductive layer 19. The buffer layer 501 can prevent harmful substances in the substrate 10 from invading the interior of the display panel and can also increase the adhesion of the film layers in the display panel to the substrate 10. The transistor T1 may include an active layer, a gate, a first electrode, and a second electrode. The active layer may be located in the semiconductor layer, the gate may be located in the first conductive layer 11, and the first electrode and the second electrode may be located in the fourth conductive layer 15. The capacitor may include a second electrode plate C2 and a first electrode plate C1. The orthographic projections of the second electrode plate C2 and the first electrode plate C1 on the substrate 10 may at least partially overlap, for example, they may coincide. The first electrode plate C1 may be located in the first conductive layer 11, and the second electrode plate C2 may be located in the second conductive layer 13. The transistor T1 may be connected to the anode layer 503 via the first and second conversion electrodes 175 and 195. The first conversion electrode 175 may be located in the fifth conductive layer 17, and the second conversion electrode 195 may be located in the third conductive layer 19.

[0067] In an exemplary embodiment, the light-emitting structure layer may include a pixel definition layer 21 and multiple light-emitting elements. For example, each light-emitting element may include a stacked anode layer 503, an organic light-emitting layer 600, and a cathode layer 504. The anode layer 503 may be disposed on the first planar layer 16 and electrically connected to the first electrode of the transistor T1 through a pixel via provided in the first planar layer 16. The pixel definition layer 21 is disposed on the anode layer 503 and the first planar layer 16. The pixel definition layer 21 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding anode layer 503. At least a portion of the organic light-emitting layer 600 may be disposed within a pixel opening and connected to the corresponding anode layer 503. The cathode layer 504 may be disposed on the organic light-emitting layer 600 and connected to the organic light-emitting layer 600. Driven by the anode layer 503 and the cathode layer 504, the organic light-emitting layer 600 may emit light of a corresponding color. In an exemplary embodiment, the spacer pillar (PS) 601 may be disposed on a side of the pixel definition layer 21 away from the substrate 10 , which is not limited in the present disclosure.

[0068] In an exemplary embodiment, the organic light-emitting layer 600 of the light-emitting element may include an emitting layer (EML), and one or more of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Driven by the voltage of the anode layer 503 and the cathode layer 504, the organic material's luminescence characteristics can be utilized to emit light according to desired grayscale.

[0069] In an exemplary embodiment, the light-emitting layers of the light-emitting elements emitting light of different colors may be different. For example, the red light-emitting element includes a red light-emitting layer, the green light-emitting element includes a green light-emitting layer, and the blue light-emitting element includes a blue light-emitting layer. In order to reduce the difficulty of the process and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In some examples, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer can be made by a one-time process (a one-time evaporation process or a one-time inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or by inkjet process.

[0070] In an exemplary embodiment, the encapsulation layer may include a stacked first inorganic layer 505, an organic layer 506, and a second inorganic layer 507. The first and second inorganic layers 505, 507 may be made of inorganic materials, and the second encapsulation layer 142 may be made of organic materials. The organic layer 506 may be disposed between the first and second inorganic layers 505, 507 to prevent external moisture from entering the light-emitting element. However, this embodiment is not limited to this. For example, the encapsulation layer may have a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0071] In an exemplary embodiment, the touch layer 508 may include multiple metal film layers. The present disclosure does not limit the structure of the touch layer 508 and the principle of realizing the touch function.

[0072] Figure 3 is a cross-sectional view taken along the AA axis of Figure 1 , omitting the film structure of the display panel. As shown in Figure 3 , perpendicular to the display panel, the display panel of the lower frame may include a substrate 10, and, sequentially disposed on substrate 10, a first conductive layer 11, a first insulating layer 12, a second conductive layer 13, a second insulating layer 14, a fourth conductive layer 15, a first planar layer 16, a fifth conductive layer 17, a second planar layer 18, a third conductive layer 19, a third planar layer 20, a pixel definition layer 21, an organic light-emitting layer 600, a cathode layer 504, an encapsulation layer, and a touch layer 508. The film layers on the side of the pixel definition layer 21 facing away from substrate 10 are omitted in Figure 3 and replaced with the reference numeral 22. The cover plate 24 corresponding to the lower frame is also provided with an ink layer 23. The ink layer 23 is located on the side of the cover plate 24 closest to the substrate 10. After the cover plate 24 is attached, the orthographic projection of the ink layer 23 on the substrate 10 at least partially covers the first peripheral area, thereby preventing light leakage from the lower frame of the display panel. The first conductive layer 11 may include a plurality of first signal lines 111, and the second conductive layer 13 may include a plurality of second signal lines 131. The first signal lines 111 and the second signal lines 131 may extend in the same direction and be arranged alternately. The signal types transmitted by the first signal lines 111 and the second signal lines 131 may be set as needed. The fourth conductive layer 15 may include a first power line 210 and a second power line 220. The first power line 210 is located on the side of the second power line 220 closer to the display area 100. The orthographic projection of the second flat layer 18 on the substrate 10 may cover the orthographic projection of the first flat layer 16 on the substrate 10. The third flat layer 20 may include a third flat portion 201 covering the third conductive layer 19, a first dam base 202, and a second dam base 203. The first dam base 212 is used to form the first dam 410, and the second dam base 213 is used to form the second dam 420. The pixel definition layer 21 may include a pixel definition portion 211 located on the side of the third flat portion 201 away from the substrate 10, a third dam base 212 located on the side of the first dam base 202 away from the substrate 10, and a fourth dam base 213 located on the side of the second dam base 203 away from the substrate 10. The first dam 410 is composed of the first dam base 202 and the third dam base 212, and the second dam 420 is composed of the second dam base 203 and the fourth dam base 213. The second power line 220 may extend directly below the second dam 420. In the embodiments of the present disclosure, "located below the dam" or "located directly below the dam" refers to the side of the dam closer to the substrate 10. If the dam includes different dam bases, "located below the dam" or "located directly below the dam" may refer to the side of any one of the dam bases closer to the substrate 10.

[0073] After research, the inventors of this application have discovered that the coating accuracy of the ink layer 23 is currently around 170 microns, with a maximum value of approximately 340 microns. In the case of a narrow bezel, for example, when the distance between the bottom bezel edge and the display area edge 110 is less than or equal to 626 microns, the ink layer 23 cannot completely cover the bottom bezel, and the side of the bottom bezel near the display area edge 110 will be exposed, forming a light leakage area as shown in area D in FIG3 . Because the first signal lines 111 and the second signal lines 131 extend in the same direction and are alternately arranged, the surfaces of the first insulating layer 12 and the second insulating layer 14 are uneven. The surface of the second power line 220, located on the side of the second insulating layer 14 away from the substrate 10, also exhibits an uneven topography. In FIG3 , natural light L, after entering the display panel from the side of the cover plate 24, is diffusely reflected from the surface of the second power line 220. Part of the reflected light will be emitted from the cover plate 24 in area D, causing the user to see light leakage from the bottom bezel of the display panel.

[0074] An embodiment of the present disclosure provides a display panel, comprising a display area, a binding area located on one side of the display area, and a first peripheral area located on a side of the binding area close to the display area; the display panel comprises a substrate and a first conductive layer, a second conductive layer, a third conductive layer and a cover plate arranged in sequence on the substrate, and an ink layer is provided on a side of the cover plate close to the substrate; in the first peripheral area, the first conductive layer comprises a plurality of first signal lines, and the second conductive layer comprises a plurality of second signal lines, and the plurality of first signal lines and the plurality of second signal lines are arranged in sequence and extend in the same direction; the orthographic projection of the ink layer on the substrate at least partially overlaps with the first peripheral area; the orthographic projection of the third conductive layer on the substrate and the orthographic projection of the ink layer on the substrate cover the orthographic projections of the plurality of first signal lines and the plurality of second signal lines on the substrate, and the orthographic projection of the third conductive layer on the substrate and the orthographic projection of the ink layer on the substrate at least partially overlap.

[0075] The display panel provided by the embodiment of the present disclosure solves the problem of light leakage from the lower frame of the display panel by setting the third conductive layer of the lower frame and the ink layer to overlap with each other in a direction perpendicular to the substrate. The third conductive layer can be used to block the lower frame area not covered by the ink, thereby solving the problem of light leakage from the lower frame of the display panel.

[0076] Figure 4 is a cross-sectional view taken along line AA in Figure 1 in an exemplary embodiment, omitting the remaining structure of the display panel. The difference between Figure 4 and Figure 3 is the size of the third conductive layer 19. The remaining details can be referred to the above description of Figure 3 and will not be repeated here.

[0077] As shown in FIG4 , at the lower frame, the orthographic projection of the third conductive layer 19 on the substrate 10 overlaps with the orthographic projection of the ink layer 23 on the substrate 10. In a direction away from the display area 100, the overlap between the third conductive layer 19 and the ink layer 23 is a first overlap dimension Z1. The first overlap dimension Z1 can be set to be greater than or equal to 18 microns. For example, the first overlap dimension Z1 can be set to be greater than or equal to 20 microns, although this disclosure is not limited thereto.

[0078] In an exemplary embodiment, the display panel may include a touch layer, and the orthographic projection of the metal film layer in the touch layer on the substrate 10 may overlap with the orthographic projection of the ink layer 23 on the substrate 10, and near the lower frame along the direction away from the display area 100, the distance between the edge of the touch layer and the edge 110 of the display area is greater than the distance between the edge of the third conductive layer 19 and the edge 110 of the display area, so that the touch layer can continue to block light at a position not covered by the third conductive layer 19. The present disclosure is not limited to this.

[0079] After research, the inventors of the present application discovered that in the display panel shown in Figures 3 and 4, in order to form the first dam 410 and the second dam 420, it is necessary to remove the first flat layer 16 near the first dam 410 and the second dam 420, so that the fourth conductive layer 15 is exposed. During the subsequent formation of the fifth conductive layer 17, the metal of the fourth conductive layer 15 is easily over-etched, and undercuts occur at the edge of the fourth conductive layer 15, causing cracks in the subsequently formed film layer. For example, when the fourth conductive layer 15 adopts a titanium / aluminum / titanium (Ti / Al / Ti) laminated structure, the aluminum metal layer of the fourth conductive layer 15 is over-etched during the formation of the fifth conductive layer 17. During reliability testing or during the use of the display panel, these cracks can easily cause cracks or breaks in the encapsulation layer. Moisture vapor in the atmosphere can enter the display panel through the cracks. The intruding moisture can easily cause the organic material in the light-emitting structure layer to oxidize and fail, forming a failed area that cannot emit light. As water vapor continuously invades the light-emitting device along the gap, the failure area gradually expands, causing poor display on the display panel and forming a growing dark spot (GDS). The GDS at the bottom frame of the display panel is called GDSX defect.

[0080] FIG5 is a cross-sectional view taken along line AA in FIG1 in another exemplary embodiment, omitting the remaining structure of the display panel. FIG5 differs from FIG4 in the structure of the first power line 210 and the second power line 220. The remaining structure can be referred to the description of FIG4 above and will not be repeated here.

[0081] As shown in FIG5 , at the bottom frame, the fourth conductive layer 15 includes a first conductive portion 151 and a second conductive portion 152 that are insulated from each other. The second conductive portion 152 is located on the side of the first conductive portion 151 away from the display area 100. The orthographic projections of the first conductive portion 151 and the second conductive portion 152 on the substrate 10 are located within the orthographic projection of the first planar layer 16 on the substrate 10. At the bottom frame, in a direction away from the display area 100, the dimension between the edge of the second conductive portion 152 and the edge of the first planar layer 16 is a second overlap dimension Z2, i.e., the dimension by which the first planar layer 16 covers the edge of the second conductive portion 152. In an exemplary embodiment, the second overlap dimension Z2 may be greater than or equal to 9 microns, for example, greater than or equal to 10 microns, although this disclosure is not limited thereto. By providing the first planar layer 16 to cover the edge of the second conductive portion 152, the edge of the second conductive portion 152 is prevented from being overetched when a metal film layer is subsequently formed above the fourth conductive layer 15. This helps maintain the edge morphology of the second conductive portion 152 and prevents cracks in the film layer of the display panel. The orthographic projection of the second conductive portion 152 on the substrate 10 does not overlap with the orthographic projection of the first dam 410 on the substrate 10.

[0082] As shown in FIG5 , the fifth conductive layer 17 includes a third conductive portion 171 and a fourth conductive portion 172 that are insulated from each other. The fourth conductive portion 172 is located on a side of the third conductive portion 171 away from the display area 100. The orthographic projections of the third conductive portion 171 and the fourth conductive portion 172 on the substrate 10 may be located within the orthographic projection of the second planar layer 18 on the substrate 10. In a direction away from the display area 100, the dimension between the edge of the fourth conductive portion 172 and the edge of the second planar layer 18 is a third overlap dimension Z3, i.e., the dimension by which the second planar layer 18 covers the edge of the fourth conductive portion 172. In an exemplary embodiment, the third overlap dimension Z3 may be greater than or equal to 4.5 microns. For example, the third overlap dimension Z3 may be greater than or equal to 5 microns. In some examples, the third overlap dimension Z3 may be greater than or equal to 10 microns, although this disclosure is not limited thereto. By setting the second flat layer 18 to cover the edge of the fourth conductive part 172, when the metal film layer is subsequently formed above the fifth conductive layer 17, the edge of the fourth conductive part 172 will not be over-etched, which helps to maintain the edge morphology of the fourth conductive part 172 and avoid cracks in the film layer of the display panel.

[0083] In an exemplary embodiment, the orthographic projection of the fourth conductive portion 172 on the substrate 10 may overlap the orthographic projection of the second conductive portion 152 on the substrate 10. In a direction away from the display area 100, the dimension between the edge of the fourth conductive portion 172 and the edge of the second conductive portion 152 is a fourth overlap dimension Z4, i.e., the dimension by which the fourth conductive portion 172 overlaps the edge of the second conductive portion 152. In an exemplary embodiment, the fourth overlap dimension Z4 may be greater than or equal to 4.5 microns. For example, the fourth overlap dimension Z4 may be greater than or equal to 5 microns. In some examples, the fourth overlap dimension Z4 may be greater than or equal to 30 microns, although this disclosure is not limited thereto. By providing the fourth conductive portion 172 to overlap the edge of the second conductive portion 152, the edge of the second conductive portion 152 is obscured by the fourth conductive portion 172 during formation, further preventing etching of the second conductive portion 152 and cracking of the display panel's film layer. The orthographic projection of the fourth conductive portion 172 on the substrate 10 does not overlap with the orthographic projection of the first dam 410 on the substrate 10.

[0084] In an exemplary embodiment, the orthographic projection of the third conductive portion 171 on the substrate 10 may overlap with the orthographic projection of the first conductive portion 151 on the substrate 10 . For example, the orthographic projection of the third conductive portion 171 on the substrate 10 may coincide with the orthographic projection of the first conductive portion 151 on the substrate 10 .

[0085] In an exemplary embodiment, the first power line 210 may include a first conductive portion 151 and a third conductive portion 171 , and the first conductive portion 151 and the third conductive portion 171 may be connected via a through hole (not shown).

[0086] As shown in FIG5 , the third conductive layer 19 can extend directly below the second dam 420 . The second power line 220 can include a second conductive portion 152 , a fourth conductive portion 172 , and a portion of the third conductive layer 19 . The second conductive portion 152 , the fourth conductive portion 172 , and a portion of the third conductive layer 19 can be sequentially connected via through-holes (not shown). In the direction away from the display area 100 at the lower frame, the overlap between the edge of the third flat portion 201 and the edge of the second flat layer 18 is a fifth overlap dimension Z5 , i.e., the dimension by which the third flat portion 201 overlaps the edge of the second flat layer 18 . In an exemplary embodiment, the fifth overlap dimension Z5 can be greater than or equal to 18 microns. For example, the fifth overlap dimension Z5 can be greater than or equal to 20 microns, although this disclosure is not limited thereto. By setting the fifth overlap dimension Z5 to be greater than or equal to 18 microns, the edge slope of the third flat portion 201 can be gentler. This prevents the organic material of the organic layer 506 from overflowing when the encapsulation layer is subsequently formed, thereby ensuring the success rate and effectiveness of the encapsulation.

[0087] In an exemplary embodiment, the display panel is provided with connecting electrodes at the top, left, and right borders. These connecting electrodes can be provided on the same layer as the anode layer 503 of the display panel. The connecting electrodes can be connected to the second power line 220, helping to reduce the voltage drop during the transmission of low-voltage signals. However, these connecting electrodes are easily damaged during the manufacturing process.

[0088] FIG6 is a schematic diagram of a connection electrode damage in an exemplary embodiment, illustrating a cross-sectional view of the display panel taken along the BB axis in FIG1 , and omitting the schematic diagram of the film structure of the display panel. The connection electrode at the upper and left frames can be similar to that at the right frame, and will not be described in detail here. As shown in FIG6 , the inventors of the present application have discovered that, due to the high height H of the first dam base 202 of the first dam 410 in the direction perpendicular to the substrate 10, after forming the anode layer film A1 and coating the photoresist P1, the photoresist P1 cannot cover the anode layer film A1 located above the first dam 410. Therefore, after exposure, the anode layer film A1 located above the first dam base 202 is damaged, causing the connection electrode to be disconnected near the first dam base 202, affecting the display uniformity of the display panel. Furthermore, after the pixel definition layer 21 is formed, the first dam base 202 is covered by the third dam base 212, and the damage to the connection electrode is concealed by the first dam 410, making it difficult to find the cause of the damage to the connection electrode. In FIG6 , reference numeral 31 indicates a film layer located between the substrate 10 and the fourth conductive layer 15 . This part of the structure can be designed as needed, and the present disclosure does not impose any limitation thereto.

[0089] To address the issue of connecting electrode damage, the height of the first dam base 202 can be set to be less than the height of the third flat portion 201 provided on the same layer, thereby reducing the height of the anode layer film A1 protruding above the first dam base 202, allowing the photoresist P1 to completely cover the anode layer film A1 located above the first dam 410. In an exemplary embodiment, the third flat layer 20 can be made to have different heights at different locations by using masks with different light transmittances. For example, a halftone mask can be used to form the first dam base 202, and a normal mask can be used to form the third flat portion 201. The height of the first dam base 202 obtained in this way is approximately half the height of the third flat portion 201. Other methods can also be used to achieve different heights at different locations of the third flat layer 20, and this disclosure is not limited to this. By reducing the height of the first dam 410, it helps to increase the flatness of the edges of the inkjet printed (IJP) organic material in the encapsulation layer, ensuring the success rate and encapsulation effect of the encapsulation.

[0090] Figure 7 is a schematic diagram of the fifth overlap dimension in an exemplary embodiment, omitting the remaining structure of the display panel. In an exemplary embodiment, the edge of the second flat portion 201 at the bottom frame can be formed using both a conventional mask and a halftone mask. The masks with different transmittances result in different slopes at the edge of the second flat portion 201. As shown in Figure 7, a conventional mask can be used on the side close to the display area 100 to form a first slope, while a halftone mask can be used on the side away from the display area 100 to form a second slope. The fifth overlap dimension Z5 in Figure 5 can be the distance between the edge of the second slope and the edge of the second flat layer 18 in the direction away from the display area 100. In an exemplary embodiment, the distance between the edge of the first slope and the edge of the second flat layer 18 can be a first dimension S1, and the distance between the edge of the first slope and the edge of the second slope can be a second dimension S2. The fifth overlap dimension Z5 can be the sum of the first dimension S1 and the second dimension S2. In an exemplary embodiment, the first size S1 may be greater than or equal to 9 microns, for example, the first size S1 may be greater than or equal to 10 microns, and the second size S2 may be greater than or equal to 9 microns, for example, the second size S2 may be greater than or equal to 10 microns, which is not limited in this disclosure.

[0091] FIG8 is a diagram showing the positional relationship between the first dam, the second dam, and the boundary of the second power line at the right frame in an exemplary embodiment, and omits the schematic diagram of the film structure of the display panel. The positional relationship between the first dam, the second dam, and the boundary of the second power line at the upper frame and the left frame of the display panel can be the same as that at the right frame, and will not be repeated here. As shown in FIG8 , the positive projection of the boundary T1 of the second power line 220 away from the side of the display area 100 on the substrate 10 can be located within the range of the positive projection of the second dam 420 on the substrate 10. The second power line 220 can be a single-layer structure or a stacked-layer structure. For example, the second power line 220 can be located in the fourth conductive layer 15, or the second power line 220 can be located in the fourth conductive layer 15 and the fifth conductive layer 17, or the second power line 220 can be located in the fourth conductive layer 15, the fifth conductive layer 17, and the third conductive layer 19. The present disclosure does not limit this.

[0092] Figure 9 is a schematic diagram of the stacking of the first and second dams at the right frame in an exemplary embodiment, omitting the film structure of the display panel. The stacking of the first and second dams at the top and left frames of the display panel can be the same as that at the right frame and will not be further described here. As shown in Figure 9, the second power line 220 can be located on the fourth conductive layer 15, the fifth conductive layer 17, and the third conductive layer 19. At the right frame, the fourth conductive layer 15, the fifth conductive layer 17, and the third conductive layer 19 are in contact with each other and extend directly below the second dam 420. The orthographic projection of the edge of the fourth conductive layer 15 on the substrate 10 is within the orthographic projection of the first planar layer 16 on the substrate 10, thereby protecting the edge of the fourth conductive layer 15. The dimension between the edge of the fourth conductive layer 15 and the edge of the first planar layer 16 in a direction away from the display area 100 is a sixth overlap dimension Z6. In an exemplary embodiment, the sixth overlap dimension Z6 can be greater than or equal to 4.5 microns. For example, the sixth overlap dimension Z6 can be greater than or equal to 5 microns, although this disclosure is not limited in this regard. The orthographic projection of the edge of the third conductive layer 19 on the substrate 10 overlaps the orthographic projection of the edge of the fifth conductive layer 17 on the substrate 10. The dimension between the edge of the third conductive layer 19 and the edge of the fifth conductive layer 17 in a direction away from the display area 100 is a seventh overlap dimension Z7. In an exemplary embodiment, the seventh overlap dimension Z7 may be greater than or equal to 4.5 microns. For example, the seventh overlap dimension Z7 may be greater than or equal to 5 microns, although this disclosure is not limited thereto. The first dam 202 may be formed using a halftone mask such that its height is less than that of the second dam 203. The orthographic projection of the third dam 203 on the substrate 10 may overlap the orthographic projections of the edges of the fourth conductive layer 15, the first planar layer 16, the fifth conductive layer 17, and the third conductive layer 19 on the substrate 10, thereby protecting these metal film layers. The connecting electrode 301 may be directly connected to the third conductive layer 19 to facilitate transmission of low-voltage signals. The orthographic projection of the connecting electrode 301 on the substrate 10 may overlap the orthographic projection of the first dam base 202 on the substrate 10, and the orthographic projection of the connecting electrode 301 on the substrate 10 may at least partially overlap with the orthographic projection of the second dam base 203 on the substrate 10. At the right frame, the first dam 410 may further include a fifth dam base 302 located on the side of the third dam base 212 away from the substrate 10. The orthographic projection of the fifth dam base 302 on the substrate 10 may be within the range of the orthographic projection of the third dam base 212 on the substrate 10. The second dam 420 may further include a sixth dam base 303 located on the side of the fourth dam base 213 away from the substrate 10. The orthographic projection of the sixth dam base 303 on the substrate 10 may be within the range of the orthographic projection of the fourth dam base 213 on the substrate 10. The fifth dam base 302 and the sixth dam base 303 may be provided on the same layer as the isolation column 601 of the display area 100.

[0093] Figure 10 is a cross-sectional view taken along line AA in Figure 1 of yet another exemplary embodiment, omitting the structure of the display panel. Figure 10 differs from Figure 5 in that a third dam 430 is added, and the second power line 220 extends directly below the third dam 430. The remaining structure can be found in the description of Figure 5 above and will not be repeated here.

[0094] As shown in FIG10 , the display panel may further include a third dam 430, which may be located on a side of the second dam 420 away from the display area 100 and disposed around the second dam 420. By extending the second power line 220 directly below the third dam 430, not only is the design of the second power line 220 not restricted by the position of the second dam 420, thereby increasing the flexibility of the display panel design, but the width of the second power line at the frame may also be increased, reducing the impedance of the second power line, thereby improving display quality, particularly when the display panel is displaying in highlight mode.

[0095] As shown in FIG10 , the third dam 430 may include a seventh dam base 162, an eighth dam base 182, and a ninth dam base 204. The orthographic projection of the eighth dam base 182 on the substrate 10 may overlap the orthographic projection of the seventh dam base 162 on the substrate 10, and the orthographic projection of the ninth dam base 204 on the substrate 10 may be within the orthographic projection of the eighth dam base 182 on the substrate 10. The seventh dam base 162 may be located on the first planar layer 16, and the orthographic projection of the first flat portion 161 of the first planar layer 16 on the substrate 10 may overlap the orthographic projections of the first conductive portion 151 and the second conductive portion 152 on the substrate 10. The eighth dam base 182 may be located on the second planar layer 18, and the orthographic projection of the second flat portion 181 of the second planar layer 18 on the substrate 10 may overlap the orthographic projections of the third conductive portion 171 and the fourth conductive portion 172 on the substrate 10. The ninth dam base 201 may be located on the third planar layer 20.

[0096] In an exemplary embodiment, third dam 430 may further include a tenth dam base 214 , whose orthographic projection on substrate 10 may be within the range of the orthographic projection of ninth dam base 201 on substrate 10 . Tenth dam base 214 may be located on pixel definition layer 21 .

[0097] As shown in FIG10 , the distance between the second dam 420 and the third dam 430 in a direction away from the display area 100 may be an eighth distance Z8. The eighth distance Z8 may be the minimum distance between the opposing side surfaces of the fourth dam base 213 and the eighth dam base 182. In an exemplary embodiment, the eighth distance Z8 may be greater than or equal to 36 microns and less than or equal to 44 microns. For example, the eighth distance Z8 may be approximately 40 microns. The distance between the eighth dam base 182 and the seventh dam base 162 in a direction away from the display area 100 may be a ninth distance Z9. The ninth distance Z9 may be greater than or equal to 18 microns and less than or equal to 22 microns. For example, the ninth distance Z9 may be approximately 20 microns. The distance between the eighth dam base 182 and the ninth dam base 204 in a direction away from the display area 100 may be a tenth distance Z10. The tenth distance Z10 may be greater than or equal to 9 microns and less than or equal to 11 microns. For example, the tenth distance Z10 may be approximately 10 microns. In a direction away from the display area 100, the distance between the ninth dam base 204 and the tenth dam base 214 may be an eleventh distance Z11. The eleventh distance Z11 may be greater than or equal to 9 microns and less than or equal to 11 microns. For example, the eleventh distance Z11 may be approximately 10 microns. The distance between the second dam 420 and the third dam 430, as well as the distance between the dam bases of the third dam 430 itself, may be set as needed to control the shape and inclination of the side of the third dam 430 adjacent to the second dam 420. This is not limited in this disclosure.

[0098] Figure 11 is a diagram showing the positional relationship between the first dam, the second dam, the third dam, and the boundary of the second power line at the right frame in an exemplary embodiment, and omits the schematic diagram of the film structure of the display panel. The positional relationship between the first dam, the second dam, the third dam, and the boundary of the second power line at the upper frame and the left frame of the display panel can be the same as that at the right frame, and will not be repeated here. As shown in Figure 11, the positive projection of the boundary T1 of the second power line 220 away from the side of the display area 100 on the substrate 10 can be located within the range of the positive projection of the third dam 430 on the substrate 10. The second power line 220 can be a single-layer structure or a stacked structure. For example, the second power line 220 can be located in the fourth conductive layer 15, or the second power line 220 can be located in the fourth conductive layer 15 and the fifth conductive layer 17, or the second power line 220 can be located in the fourth conductive layer 15, the fifth conductive layer 17, and the third conductive layer 19. The present disclosure does not limit this.

[0099] Figure 12 is a schematic diagram of the stacking of the first, second, and third dams at the right frame in an exemplary embodiment, omitting the display panel's film structure. The stacking of the first, second, and third dams at the top and left frames of the display panel is similar to that at the right frame and is not further described here. Figure 12 differs from Figure 9 in the addition of third dam 430. The remaining structure can be referred to in the description of Figure 9 above and is not further described here.

[0100] As shown in Figure 12, at the right frame, the fourth conductive layer 15, the fifth conductive layer 17, and the third conductive layer 19 are in contact with each other and extend directly below the third dam 430. The orthographic projection of the edge of the fourth conductive layer 15 on the substrate 10 is within the orthographic projection of the seventh dam base 162 on the substrate 10, thereby protecting the edge of the fourth conductive layer 15. The orthographic projection of the edge of the fifth conductive layer 17 on the substrate 10 is within the orthographic projection of the eighth dam base 182 on the substrate 10, thereby protecting the edge of the fifth conductive layer 17. The orthographic projection of the edge of the third conductive layer 19 on the substrate 10 is within the orthographic projection of the ninth dam base 204 on the substrate 10, thereby protecting the edge of the third conductive layer 19.

[0101] In an exemplary embodiment, the orthographic projection of the ninth dam base 204 on the substrate 10 may cover the orthographic projections of the seventh dam base 162 and the eighth dam base 182 on the substrate 10. At the right frame, the distance between the second dam 420 and the third dam 430 may be a twelfth distance Z12, which may be the minimum distance between the opposite side surfaces of the fourth dam base 213 and the ninth dam base 204. In an exemplary embodiment, the twelfth distance Z12 may be greater than or equal to 18 microns. For example, the twelfth distance Z12 may be greater than or equal to 20 microns, which is not limited in this disclosure. By setting the twelfth distance Z12 to be greater than or equal to 18 microns, it is ensured that the inorganic film layer between the second dam 420 and the third dam 430 will not penetrate the connection, thereby eliminating the path for water vapor intrusion, which helps to improve the display effect and service life of the display panel.

[0102] In an exemplary embodiment, the orthographic projection of the edge of the fifth conductive layer 17 on the substrate 10 covers the orthographic projection of the edge of the fourth conductive layer 15 on the substrate 10, and the orthographic projection of the edge of the third conductive layer 19 on the substrate 10 covers the orthographic projection of the edge of the fifth conductive layer 17 on the substrate 10. By arranging the upper conductive layer to cover the edge of the lower conductive layer, it is ensured that the lower conductive layer is not damaged during the formation of the upper conductive layer, which helps to prevent cracks in the display panel.

[0103] FIG13 is a schematic diagram of the stacking of the first dam, the second dam, and the third dam at the right frame in another exemplary embodiment, and omits the schematic diagram of the film structure of the display panel. The stacking of the first dam, the second dam, and the third dam at the upper frame and the left frame of the display panel can be the same as that at the right frame, and will not be repeated here. The difference between FIG13 and FIG12 is that, in the direction perpendicular to the substrate 10, the edge of the fifth conductive layer 17 located in the third dam 430 and the edge of the third conductive layer 19 are flush, and the rest of the structure can refer to the above description of FIG12, and will not be repeated here. By setting the edge of the fifth conductive layer 17 and the edge of the third conductive layer 19 to be flush, and both covering the edge of the fourth conductive layer 15, when the fifth conductive layer 17 and the third conductive layer 19 located above are formed, the fourth conductive layer 15 will not be damaged, which helps to avoid cracks in the display panel.

[0104] The present disclosure also provides a display device comprising the display panel described in any of the above embodiments. The display device can be any product or component with a display function, such as an OLED display, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, etc., but the present disclosure is not limited thereto.

[0105] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and variations in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of patent protection of the present invention shall remain subject to the scope defined by the appended claims.

Claims

1. A display panel, comprising a display area, a binding area located on one side of the display area, and a first peripheral area located on a side of the binding area close to the display area; the display panel comprises a substrate and a first conductive layer, a second conductive layer, a third conductive layer, and a cover plate sequentially disposed on the substrate, wherein an ink layer is disposed on a side of the cover plate close to the substrate; in the first peripheral area, the first conductive layer comprises a plurality of first signal lines, and the second conductive layer comprises a plurality of second signal lines, wherein the plurality of first signal lines and the plurality of second signal lines are arranged in sequence and extend in the same direction; an orthographic projection of the ink layer on the substrate at least partially overlaps with the first peripheral area; The orthographic projection of the third conductive layer on the substrate and the orthographic projection of the ink layer on the substrate cover the orthographic projections of the plurality of first signal lines and the plurality of second signal lines on the substrate, and the orthographic projection of the third conductive layer on the substrate and the orthographic projection of the ink layer on the substrate at least partially overlap.

2. The display panel according to claim 1, wherein In the first peripheral region, along a direction away from the display region, an overlapping dimension between the third conductive layer and the ink layer is a first overlapping dimension, and the first overlapping dimension is greater than or equal to 18 micrometers.

3. The display panel according to claim 1, wherein: The display panel further includes a second peripheral area located outside the display area and away from the binding area, and the first peripheral area is connected to the second peripheral area and surrounds the display area; The display panel further includes a first dam and a second dam, wherein the first dam and the second dam respectively surround the display area, and the second dam is located on a side of the first dam away from the display area.

4. The display panel according to claim 3, wherein: The display panel further includes a fourth conductive layer, a first flat layer, a fifth conductive layer, a second flat layer, a third flat layer, and a pixel definition layer, which are sequentially arranged on a side of the second conductive layer away from the substrate; the third conductive layer is located between the second flat layer and the third flat layer, and the pixel definition layer is located on a side of the third flat layer away from the substrate; The first dam includes a first dam base and a third dam base stacked together, and the third dam base is located on a side of the first dam base away from the substrate; the second dam includes a second dam base and a fourth dam base stacked together, and the fourth dam base is located on a side of the second dam base away from the substrate; the first dam base and the second dam base are located on the third flat layer; the third dam base and the fourth dam base are located on the pixel definition layer.

5. The display panel according to claim 4, wherein: The display panel further includes a second power line; in the first peripheral area and the second peripheral area, the second power line extends to below a side of the second dam close to the substrate. The display panel according to claim 5 , wherein: The second power line is located in the fourth conductive layer; or, the second power line is located in the fourth conductive layer and the fifth conductive layer, and the second power lines in different conductive layers are connected through vias.

7. The display panel according to claim 5, wherein: The second power line includes a second conductive part and a fourth conductive part, the second conductive part is located in the fourth conductive layer, and the fourth conductive part is located in the fifth conductive layer; the second conductive part, the fourth conductive part and the second power line located in the third conductive layer are connected in sequence through vias, and the second power line located in the third conductive layer extends to the bottom of the second dam close to the side of the substrate.

8. The display panel according to claim 7, wherein: In the first peripheral area, in a direction away from the display area, an edge of the orthographic projection of the second conductive portion on the substrate is located within the range of the orthographic projection of the first flat layer on the substrate; and an edge of the orthographic projection of the fourth conductive portion on the substrate is located within the range of the orthographic projection of the second flat layer on the substrate.

9. The display panel according to claim 8, wherein: In the first peripheral region and in a direction away from the display region, an orthographic projection of the fourth conductive portion on the substrate covers an edge of an orthographic projection of the second conductive portion on the substrate.

10. The display panel according to claim 8, wherein: The third flat layer includes a third flat portion. In the first peripheral region and in a direction away from the display region, an orthographic projection of the third flat portion on the substrate covers an edge of an orthographic projection of the second flat layer on the substrate.

11. The display panel according to claim 10, wherein: In the first peripheral region, a dimension between an edge of the third flat portion and an edge of the second flat layer in a direction away from the display region is a fifth overlapping dimension, and the fifth overlapping dimension is greater than or equal to 18 micrometers.

12. The display panel according to claim 10, wherein: A height of the third flat portion in a direction perpendicular to the substrate is greater than a height of the first dam in a direction perpendicular to the substrate.

13. The display panel according to claim 5, wherein: In the second peripheral area, the display panel further includes a connecting electrode, which is located on a side of the third flat layer away from the substrate, and is connected to the second power line. In the second peripheral area, the connecting electrode extends to below a side of the second dam close to the substrate.

14. The display panel according to claim 13, wherein: In the second peripheral region, in a direction away from the display region, an edge of an orthographic projection of the fourth conductive layer on the substrate is located within a range of an orthographic projection of the first planar layer on the substrate; The edge of the orthographic projection of the fourth conductive layer on the substrate, the edge of the orthographic projection of the first flat layer on the substrate, the edge of the orthographic projection of the fifth conductive layer on the substrate and the edge of the orthographic projection of the third conductive layer on the substrate are located within the range of the orthographic projection of the third dam base on the substrate.

15. The display panel according to claim 14, wherein: In the second peripheral region and in a direction away from the display region, the orthographic projection of the third conductive layer on the substrate covers an edge of the orthographic projection of the fifth conductive layer on the substrate.

16. The display panel according to claim 13, wherein: In the second peripheral area, the first retaining dam further includes a fifth dam foundation, and the second retaining dam further includes a sixth dam foundation; the fifth dam foundation is located on the side of the third dam foundation away from the base, and the sixth dam foundation is located on the side of the fourth dam foundation away from the base.

17. The display panel according to claim 4, wherein: The display panel also includes a third dam, which surrounds the display area and is located on a side of the second dam away from the display area; the display panel also includes a second power line; within the first peripheral area and the second peripheral area, the second power line passes through the first dam and the second dam and extends to below the side of the third dam close to the substrate.

18. The display panel according to claim 17, wherein: The third retaining dam includes a seventh dam foundation, an eighth dam foundation, and a ninth dam foundation. The seventh dam foundation is located on the first flat layer, the eighth dam foundation is located on the second flat layer, and the ninth dam foundation is located on the third flat layer.

19. The display panel according to claim 17, wherein: In a direction away from the display area, the distance between the second dam and the third dam is an eighth distance, which is the minimum distance between opposite side surfaces of the second dam and the third dam, and the eighth distance is greater than or equal to 36 micrometers and less than or equal to 44 micrometers.

20. A display device comprising the display panel according to any one of claims 1 to 19.

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