Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a driving structure layer and a light-emitting structure layer. The driving structure layer comprises a plurality of circuit units; a circuit unit comprises a pixel driving circuit, a power connection line, and a first power line; the pixel driving circuit at least comprises a power connection electrode; the power connection electrode is connected to the power connection line; and the first power line is connected to the power connection line or the power connection electrode through a power via hole. The light-emitting structure layer comprises a plurality of light-emitting units; at least one light-emitting unit comprises an anode and a pixel definition layer; the anode is connected to the pixel driving circuit of a corresponding circuit unit; a pixel opening exposing the anode is formed in the pixel definition layer; and the orthographic projection of at least one pixel opening on a substrate does not overlap the orthographic projection of the power via hole on the substrate. According to the present disclosure, by not forming any power via hole within the range of the pixel opening, color cast can be effectively improved, thereby improving the display quality.

Description

Display substrate and manufacturing method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on March 8, 2024, with application number 202410268975.6 and invention name “Display substrate, preparation method thereof, and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, including a driving structure layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving structure layer away from the substrate; on a plane parallel to the display substrate, the driving structure layer includes a plurality of circuit units, at least one circuit unit includes a pixel driving circuit, a power connection line extending along a first direction, and a first power line extending along a second direction, the first direction and the second direction intersect, the pixel driving circuit includes at least a power connection electrode, the power connection electrode is connected to the power connection line, and the first power line is connected to the power connection line or the power connection electrode through a power via; the light-emitting structure layer includes a plurality of light-emitting units, at least one light-emitting unit includes an anode and a pixel definition layer arranged on a side of the anode away from the substrate, the anode is connected to the pixel driving circuit of the corresponding circuit unit, the pixel definition layer is provided with a pixel opening exposing the anode, and the orthographic projection of at least one pixel opening on the substrate does not overlap with the orthographic projection of the power via on the substrate.

[0006] In an exemplary embodiment, the plurality of light-emitting units include at least a first light-emitting unit that emits a first color light, a second light-emitting unit that emits a second color light, and a third light-emitting unit that emits a third color light, the first light-emitting unit includes at least a first anode and a first pixel opening exposing the first anode, the second light-emitting unit includes at least a second anode and a second pixel opening exposing the second anode, and the third light-emitting unit includes at least a third anode and a third pixel opening exposing the third anode; the second anode is arranged on one side of the first anode in the second direction, and the third anode is arranged on one side of the first anode in the first direction; the orthographic projections of the first pixel opening and the second pixel opening on the substrate at least partially overlap with the orthographic projection of the first power line on the substrate, and the orthographic projection of the third pixel opening on the substrate does not overlap with the orthographic projection of the first power line on the substrate.

[0007] In an exemplary embodiment, orthographic projections of the first pixel opening and the second pixel opening on the substrate are located within a range of an orthographic projection of the first power line on the substrate.

[0008] In an exemplary embodiment, in at least one circuit unit and a circuit unit adjacent to the first direction, the first power lines in the two circuit units are connected to each other in an integrated structure.

[0009] In an exemplary embodiment, at least one circuit unit further includes a data signal line, and in at least one circuit unit and the circuit units adjacent to each other in the first direction, the data signal line in one circuit unit is arranged on a side of the first power line in the opposite direction of the first direction, and the data signal line in the other circuit unit is arranged on a side of the first power line in the first direction; the orthographic projections of the first pixel opening and the second pixel opening on the substrate do not overlap with the orthographic projections of the data signal line on the substrate, and the orthographic projection of the third pixel opening on the substrate at least partially overlaps with the orthographic projection of the data signal line on the substrate.

[0010] In an exemplary embodiment, the pixel driving circuit further includes a fourth transistor and a data connection electrode, the fourth transistor includes at least a fourth active layer, and the data signal line is connected to the data connection electrode through a data via; in at least one circuit unit and the circuit units adjacent in the first direction, the data connection electrode in one circuit unit is connected to the first area of ​​the fourth active layer through a via, and the data connection electrode in the other circuit unit is connected to the first area of ​​the fourth active layer through a data connection line.

[0011] In an exemplary embodiment, the pixel driving circuit further includes a shielding electrode and a second transistor with a dual-gate structure, the shielding electrode being connected to the first power line, the orthographic projection of the shielding electrode on the substrate at least partially overlapping with the orthographic projection of the second active layer between the two gate electrodes of the second transistor on the substrate, and the orthographic projection of the shielding electrode on the substrate at least partially overlapping with the orthographic projection of the data connection line on the substrate.

[0012] In an exemplary embodiment, the pixel driving circuit further includes a fourth node electrode and an anode connecting electrode, and the anode in at least one light-emitting unit is connected to the anode connecting electrode through an anode via; in at least one circuit unit and the circuit units adjacent in the first direction, the anode connecting electrode in one circuit unit is connected to the fourth node electrode through a via, and the anode connecting electrode in another circuit unit is connected to the fourth node electrode through an anode connecting line; the orthographic projections of the first pixel opening and the second pixel opening on the substrate do not overlap with the orthographic projection of the anode connecting line on the substrate, and the orthographic projection of the third pixel opening on the substrate at least partially overlaps with the orthographic projection of the anode connecting line on the substrate.

[0013] In an exemplary embodiment, the third pixel opening has an opening center line, which is a straight line extending along the second direction and passing through the geometric center of the third pixel opening; in at least one third pixel opening, the anode connection line has a first distance from the opening center line, and the data signal line has a second distance from the opening center line, and the ratio of the first distance to the second distance is 0.8 to 1.2.

[0014] In an exemplary embodiment, at least one circuit unit further includes at least one initial signal line extending along the first direction, and a second power line and an initial connection line extending along the second direction, the initial connection line being connected to the initial signal line, the orthographic projections of the first pixel opening and the second pixel opening on the substrate do not overlap with the orthographic projections of the second power line and the initial connection line on the substrate, and the orthographic projection of the third pixel opening on the substrate at least partially overlaps with the orthographic projections of the second power line and the initial connection line on the substrate.

[0015] In an exemplary embodiment, the third pixel opening has an opening center line, which is a straight line extending along the second direction and passing through the geometric center of the third pixel opening; in at least one third pixel opening, the second power line has a third distance from the opening center line, and the initial connection line has a fourth distance from the opening center line, and the ratio of the third distance to the fourth distance is 0.8 to 1.2.

[0016] In an exemplary embodiment, the pixel driving circuit further includes a storage capacitor, and at least one circuit unit further includes a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line, a first initial signal line, a second initial signal line, and a third initial signal line extending along the first direction and connected to the pixel driving circuit, the first scanning signal line being arranged on a side of the storage capacitor in the opposite direction of the second direction, the third scanning signal line being arranged on a side of the first scanning signal line away from the storage capacitor, the first initial signal line being arranged on a side of the third scanning signal line away from the storage capacitor, the light-emitting signal line being arranged on one side of the storage capacitor in the second direction, and the second scanning signal line being arranged on a side of the light-emitting signal line away from the storage capacitor. On one side of the storage capacitor, the second initial signal line is arranged on a side of the second scanning signal line away from the storage capacitor, and the third initial signal line is arranged on a side of the second initial signal line away from the storage capacitor; the orthographic projection of at least one first pixel opening on the substrate at least partially overlaps with the orthographic projection of the power connection line on the substrate, the orthographic projection of at least one second pixel opening on the substrate at least partially overlaps with the orthographic projections of the first initial signal line, the second initial signal line and the third initial signal line on the substrate, and the orthographic projection of at least one third pixel opening on the substrate at least partially overlaps with the orthographic projections of the second scanning signal line, the light-emitting signal line, the second initial signal line and the power connection line on the substrate.

[0017] In an exemplary embodiment, the orthographic projection of at least one first pixel opening on the substrate does not overlap with the orthographic projection of the first initial signal line on the substrate, the orthographic projection of at least one second pixel opening on the substrate does not overlap with the orthographic projections of the first scan signal line and the power connection line on the substrate, and the orthographic projection of at least one third pixel opening on the substrate does not overlap with the orthographic projections of the first scan signal line and the third scan signal line on the substrate.

[0018] In an exemplary embodiment, the plurality of light-emitting units include at least a first light-emitting unit emitting a first color light, a second light-emitting unit emitting a second color light, and a third light-emitting unit emitting a third color light, the first light-emitting unit including at least a first anode and a first pixel opening exposing the first anode, the second light-emitting unit including at least a second anode and a second pixel opening exposing the second anode, and the third light-emitting unit including at least a third anode and a third pixel opening exposing the third anode; the second anode is arranged on one side of the first anode in the second direction, and the third anode is arranged on one side of the first anode in the first direction; the pixel driving circuit further includes a data connection electrode, and at least one circuit unit further includes a data signal line, the data signal line being connected to the data connection electrode through a data via; the orthographic projections of the first pixel opening, the second pixel opening, and the third pixel opening on the substrate do not overlap with the orthographic projections of the data via on the substrate.

[0019] In an exemplary embodiment, the plurality of circuit units include at least a first circuit unit, a second circuit unit, and a third circuit unit sequentially arranged along the first direction, the first circuit unit including at least a first pixel driving circuit and a first data signal line connected to a data connection electrode in the first pixel driving circuit through a first data via, the second circuit unit including at least a second pixel driving circuit and a second data signal line connected to a data connection electrode in the second pixel driving circuit through a second data via, and the third circuit unit including at least a third pixel driving circuit and a third data signal line connected to a data connection electrode in the third pixel driving circuit through a third data via; the orthographic projections of the first pixel opening and the second pixel opening on the substrate at least partially overlap with the orthographic projections of the first data signal line on the substrate, and the orthographic projection of the third pixel opening on the substrate does not overlap with the orthographic projections of the first data signal line, the second data signal line, and the third data signal line on the substrate.

[0020] In an exemplary embodiment, in the first direction, the spacing between the first data signal line and the second data signal line is smaller than the spacing between the second data signal line and the third data signal line, and the spacing between the first data via and the second data via is smaller than the spacing between the second data via and the third data via.

[0021] In an exemplary embodiment, in the first direction, the second data via hole and the third data via hole are disposed on both sides of the third pixel opening, and in the second direction, the first data via hole is disposed between the first pixel opening and the second pixel opening.

[0022] In an exemplary embodiment, the pixel driving circuit includes at least a storage capacitor, and at least one circuit unit further includes a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line, a first initial signal line, a second initial signal line, and a third initial signal line extending along the first direction and connected to the pixel driving circuit, wherein the first scanning signal line is arranged on a side of the storage capacitor in the opposite direction of the second direction, the third scanning signal line is arranged on a side of the first scanning signal line away from the storage capacitor, the first initial signal line is arranged on a side of the third scanning signal line away from the storage capacitor, the light-emitting signal line is arranged on one side of the storage capacitor in the second direction, and the second scanning signal line is arranged on a side of the storage capacitor in the opposite direction of the second direction. The line is arranged on a side of the light-emitting signal line away from the storage capacitor, the second initial signal line is arranged on a side of the second scanning signal line away from the storage capacitor, and the third initial signal line is arranged on a side of the second initial signal line away from the storage capacitor; the orthographic projection of at least one first pixel opening on the substrate at least partially overlaps with the orthographic projection of the first initial signal line on the substrate, the orthographic projection of at least one second pixel opening on the substrate at least partially overlaps with the orthographic projections of the first scanning signal line and the power connection line on the substrate, and the orthographic projection of at least one third pixel opening on the substrate at least partially overlaps with the orthographic projections of the first scanning signal line and the third scanning signal line on the substrate.

[0023] In an exemplary embodiment, the orthographic projection of at least one first pixel opening on the substrate does not overlap with the orthographic projection of the power connection line on the substrate, the orthographic projection of at least one second pixel opening on the substrate does not overlap with the orthographic projections of the first initial signal line, the second initial signal line and the third initial signal line on the substrate, and the orthographic projection of at least one third pixel opening on the substrate does not overlap with the orthographic projections of the second scanning signal line, the light-emitting signal line, the power connection line and the second initial signal line on the substrate.

[0024] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0025] In another aspect, the present disclosure further provides a method for preparing a display substrate, comprising:

[0026] forming a driving structure layer on a substrate, the driving structure layer comprising a plurality of circuit units, at least one circuit unit comprising a pixel driving circuit, a power connection line extending along a first direction, and a first power line extending along a second direction, wherein the first direction and the second direction intersect, the pixel driving circuit comprising at least a power connection electrode, the power connection electrode being connected to the power connection line, and the first power line being connected to the power connection line or the power connection electrode through a power via;

[0027] A light-emitting structure layer is formed on the driving structure layer; the light-emitting structure layer includes a plurality of light-emitting units, at least one light-emitting unit includes an anode and a pixel definition layer arranged on a side of the anode away from the substrate, the anode is connected to a pixel driving circuit of a corresponding circuit unit, the pixel definition layer is provided with a pixel opening exposing the anode, and the orthographic projection of at least one pixel opening on the substrate does not overlap with the orthographic projection of the power via on the substrate.

[0028] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0030] FIG1 is a schematic structural diagram of a display device;

[0031] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0032] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0033] FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0034] FIG5 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0035] FIG6 is a schematic diagram of a display substrate after a shielding layer pattern is formed thereon according to the present disclosure;

[0036] 7A and 7B are schematic diagrams of a display substrate after a semiconductor layer pattern is formed according to the present disclosure;

[0037] 8A and 8B are schematic diagrams of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0038] 9A and 9B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0039] FIG10 is a schematic diagram of a display substrate after a fourth insulating layer pattern is formed according to the present disclosure;

[0040] 11A and 11B are schematic diagrams of a display substrate after a third conductive layer pattern is formed thereon according to the present disclosure;

[0041] FIG12 is a schematic diagram of a display substrate after forming a first flat layer pattern according to the present disclosure;

[0042] 13A and 13B are schematic diagrams of a display substrate after a fourth conductive layer pattern is formed thereon according to the present disclosure;

[0043] FIG14 is a schematic diagram of a display substrate after forming a second flat layer pattern according to the present disclosure;

[0044] 15A and 15B are schematic diagrams of a display substrate after forming an anode conductive layer pattern according to the present disclosure;

[0045] FIG16 is a schematic diagram of a display substrate according to the present disclosure after a pixel definition layer pattern is formed;

[0046] FIG17 is a schematic diagram showing the positional relationship between a third pixel opening and a signal line according to an embodiment of the present disclosure;

[0047] FIG18 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0048] FIG19 is a schematic diagram of another display substrate after forming a shielding layer pattern according to the present disclosure;

[0049] 20A and 20B are schematic diagrams of another display substrate after a semiconductor layer pattern is formed according to the present disclosure;

[0050] 21A and 21B are schematic diagrams of another display substrate after forming a first conductive layer pattern according to the present disclosure;

[0051] 22A and 22B are schematic diagrams of another display substrate after forming a second conductive layer pattern according to the present disclosure;

[0052] FIG23 is a schematic diagram of another display substrate after forming a fourth insulating layer pattern according to the present disclosure;

[0053] 24A and 24B are schematic diagrams of another display substrate after forming a third conductive layer pattern according to the present disclosure;

[0054] FIG25 is a schematic diagram of another display substrate after forming a first flat layer pattern according to the present disclosure;

[0055] 26A and 26B are schematic diagrams of another display substrate after forming a fourth conductive layer pattern according to the present disclosure;

[0056] FIG27 is a schematic diagram of another display substrate after forming a second planar layer pattern according to the present disclosure;

[0057] 28A and 28B are schematic diagrams of another display substrate after forming an anode conductive layer pattern according to the present disclosure;

[0058] FIG. 29 is a schematic diagram of another display substrate after forming a pixel definition layer pattern according to the present disclosure.

[0059] Explanation of Reference Numerals: 11—first active layer; 12—second active layer; 13—third active layer; 14—fourth active layer; 15—fifth active layer; 16—sixth active layer; 17—seventh active layer; 18—eighth active layer; 21—first gate electrode; 22—second gate electrode; 24—fourth gate electrode; 31—first scanning signal line; 32—second scanning signal line; 33—third scanning signal line; 34—light-emitting signal line; 35—shielding electrode; 41—first initial signal line; 42—second initial signal line; 43—third initial signal line; 44—power connection line; 45—auxiliary scanning signal line; 46—data connection line; 51—first connection electrode; 52—second connection electrode; 53—third connection electrode; 54—fourth connection electrode; 55—fifth connection electrode; 56—sixth connection electrode; 61—data signal line; 62—anode connection electrode; 63—anode connection line; 64—extension electrode; 71—first power line; 72—second power line; 73—initial connection line; 81—first electrode plate; 82—second electrode plate; 83—board-level connection bar; 84—opening; 90—shielding electrode; 91—first shielding connection bar; 92—second shielding connection bar; 93—third shielding connection bar; 94—first shielding block; 95—second shielding block; 101—substrate; 102—driving structure layer; 103—light-emitting structure layer; 104—encapsulation structure layer. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0061] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0062] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0063] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0064] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0065] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0066] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0067] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0068] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0069] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0070] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0071] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0072] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0073] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting unit is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0074] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a green subpixel (G) that emits green light, and the third subpixel P3 may be a blue subpixel (B) that emits blue light. In an exemplary embodiment, the subpixels may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three subpixels may be arranged horizontally, vertically, or in a triangular pattern, although this disclosure is not limited thereto.

[0075] In other exemplary embodiments, the pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in parallel horizontally, in parallel vertically, or in a square, etc., which is not limited in the present disclosure.

[0076] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of three sub-pixels. As shown in Figure 3, in a plane perpendicular to the display substrate, the display substrate may include a drive structure layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the drive structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in this disclosure.

[0077] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving structure layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include at least an anode, an organic light-emitting layer and a cathode, the anode being connected to the pixel driving circuit, the organic light-emitting layer being connected to the anode, and the cathode being connected to the organic light-emitting layer, and the organic light-emitting layer emitting light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material laminated structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0078] Figure 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in Figure 4, the pixel driving circuit may include eight transistors (first transistor T1 to eighth transistor T8) and one storage capacitor C. The pixel driving circuit is connected to nine signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, emission signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA, and first power line VDD).

[0079] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is respectively connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, the second node N2 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, and the fourth node N4 is respectively connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0080] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , and a second end of the storage capacitor C is connected to the first power line VDD.

[0081] In an exemplary embodiment, the first transistor T1 may be referred to as a first initialization transistor, a gate electrode of the first transistor T1 is connected to the third scan signal line S3 , a first electrode of the first transistor T1 is connected to the first initial signal line INIT1 , and a second electrode of the first transistor T1 is connected to the first node N1 .

[0082] In an exemplary embodiment, the second transistor T2 may be referred to as a compensation transistor, a gate electrode of the second transistor T2 is connected to the first scan signal line S1 , a first electrode of the second transistor T2 is connected to the first node N1 , and a second electrode of the second transistor T2 is connected to the third node N3 .

[0083] In an exemplary embodiment, the third transistor T3 may be referred to as a driving transistor, a gate electrode of the third transistor T3 is connected to the first node N1 , a first electrode of the third transistor T3 is connected to the second node N2 , and a second electrode of the third transistor T3 is connected to the third node N3 .

[0084] In an exemplary embodiment, the fourth transistor T4 may be referred to as a data writing transistor, a gate electrode of the fourth transistor T4 is connected to the first scan signal line S1 , a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2 .

[0085] In an exemplary embodiment, the fifth transistor T5 may be referred to as a first light emission control transistor, a gate electrode of the fifth transistor T5 is connected to the light emission signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.

[0086] In an exemplary embodiment, the sixth transistor T6 may be referred to as a second light emission control transistor, a gate electrode of the sixth transistor T6 is connected to the light emission signal line EM, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0087] In an exemplary embodiment, the seventh transistor T7 may be referred to as a second initialization transistor, a gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0088] In an exemplary embodiment, the eighth transistor T8 may be referred to as a third initialization transistor, a gate electrode of the eighth transistor T8 is connected to the second scan signal line S2, a first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and a second electrode of the eighth transistor T8 is connected to the second node N2.

[0089] In an exemplary embodiment, a first electrode of the light-emitting device EL is connected to the fourth node N4, and a second electrode of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0090] In an exemplary embodiment, the signal of the first power line VDD is a continuously provided high level signal, and the signal of the second power line VSS is a continuously provided low level signal.

[0091] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include P-type transistors and N-type transistors.

[0092] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be low-temperature polysilicon transistors, or oxide transistors, or both. The active layer of the low-temperature polysilicon transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and oxide transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0093] The inventors of the present application have discovered through research that the main reason for the color shift and other problems in existing display devices is due to poor anode flatness.

[0094] The exemplary embodiments of the present disclosure provide a display substrate. In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate; on a plane parallel to the display substrate, the driving structure layer includes a plurality of circuit units, at least one circuit unit includes a pixel driving circuit, a power connection line extending along a first direction, and a first power line extending along a second direction, the first direction and the second direction intersect, the pixel driving circuit includes at least a power connection electrode, the power connection electrode is connected to the power connection line, and the first power line is connected to the power connection line or the power connection electrode through a power via; the light-emitting structure layer includes a plurality of light-emitting units, at least one light-emitting unit includes an anode and a pixel definition layer disposed on a side of the anode away from the substrate, the anode is connected to the pixel driving circuit of the corresponding circuit unit, the pixel definition layer is provided with a pixel opening exposing the anode, and the orthographic projection of at least one pixel opening on the substrate does not overlap with the orthographic projection of the power via on the substrate.

[0095] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position and shape of the orthographic projection of the light-emitting unit on the substrate may correspond to the position and shape of the orthographic projection of the circuit unit on the substrate, or the position and shape of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position and shape of the orthographic projection of the circuit unit on the substrate.

[0096] In an exemplary embodiment, the plurality of light-emitting units include at least a first light-emitting unit that emits a first color light, a second light-emitting unit that emits a second color light, and a third light-emitting unit that emits a third color light, the first light-emitting unit includes at least a first anode and a first pixel opening exposing the first anode, the second light-emitting unit includes at least a second anode and a second pixel opening exposing the second anode, and the third light-emitting unit includes at least a third anode and a third pixel opening exposing the third anode; the second anode is arranged on one side of the first anode in the second direction, and the third anode is arranged on one side of the first anode in the first direction; the orthographic projections of the first pixel opening and the second pixel opening on the substrate at least partially overlap with the orthographic projection of the first power line on the substrate, and the orthographic projection of the third pixel opening on the substrate does not overlap with the orthographic projection of the first power line on the substrate.

[0097] In an exemplary embodiment, orthographic projections of the first pixel opening and the second pixel opening on the substrate are located within a range of an orthographic projection of the first power line on the substrate.

[0098] In an exemplary embodiment, at least one circuit unit further includes a data signal line, and in at least one circuit unit and the circuit units adjacent to each other in the first direction, the data signal line in one circuit unit is arranged on a side of the first power line in the opposite direction of the first direction, and the data signal line in the other circuit unit is arranged on a side of the first power line in the first direction; the orthographic projections of the first pixel opening and the second pixel opening on the substrate do not overlap with the orthographic projections of the data signal line on the substrate, and the orthographic projection of the third pixel opening on the substrate at least partially overlaps with the orthographic projection of the data signal line on the substrate.

[0099] In an exemplary embodiment, the plurality of light-emitting units include at least a first light-emitting unit emitting a first color light, a second light-emitting unit emitting a second color light, and a third light-emitting unit emitting a third color light, the first light-emitting unit including at least a first anode and a first pixel opening exposing the first anode, the second light-emitting unit including at least a second anode and a second pixel opening exposing the second anode, and the third light-emitting unit including at least a third anode and a third pixel opening exposing the third anode; the second anode is arranged on one side of the first anode in the second direction, and the third anode is arranged on one side of the first anode in the first direction; the pixel driving circuit further includes a data connection electrode, and at least one circuit unit further includes a data signal line, the data signal line being connected to the data connection electrode through a data via; the orthographic projections of the first pixel opening, the second pixel opening, and the third pixel opening on the substrate do not overlap with the orthographic projections of the data via on the substrate.

[0100] In an exemplary embodiment, the plurality of circuit units include at least a first circuit unit, a second circuit unit, and a third circuit unit sequentially arranged along the first direction, the first circuit unit including at least a first pixel driving circuit and a first data signal line connected to the first pixel driving circuit through a first data via, the second circuit unit including at least a second pixel driving circuit and a second data signal line connected to the second pixel driving circuit through a second data via, and the third circuit unit including at least a third pixel driving circuit and a third data signal line connected to the third pixel driving circuit through a third data via; the orthographic projections of the first pixel opening and the second pixel opening on the substrate at least partially overlap with the orthographic projections of the first data signal line on the substrate, and the orthographic projection of the third pixel opening on the substrate does not overlap with the orthographic projections of the first data signal line, the second data signal line, and the third data signal line on the substrate.

[0101] In an exemplary embodiment, a spacing between the first data signal line and the second data signal line is smaller than a spacing between the second data signal line and the third data signal line, and a spacing between the first data via and the second data via is smaller than a spacing between the second data via and the third data via.

[0102] Figure 5 is a schematic diagram of the planar structure of a display substrate according to an exemplary embodiment of the present disclosure. In this exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate may include a drive structure layer disposed on a base and a light-emitting structure layer disposed on a side of the drive structure layer away from the base. In a plane parallel to the display substrate, the drive structure layer includes multiple circuit units, and the light-emitting structure layer includes multiple light-emitting units.

[0103] In an exemplary embodiment, the plurality of circuit units may form a plurality of unit rows and a plurality of unit columns, wherein the plurality of circuit units in each unit row are sequentially arranged along a first direction X, and the plurality of circuit units in each unit column are sequentially arranged along a second direction Y, forming an array of circuit units arranged in an array, wherein the first direction X intersects the second direction Y.

[0104] In an exemplary embodiment, at least one circuit unit may include at least a pixel driving circuit, which may include at least a storage capacitor and a plurality of transistors. The pixel driving circuit is respectively connected to a first scan signal line 31, a second scan signal line 32, a third scan signal line 33, a light emission signal line 34, a first initial signal line 41, a second initial signal line 42, a third initial signal line 43, a data signal line 61, and a first power line 71. The first scan signal line 31, the second scan signal line 32, and the third scan signal line 33 are configured to respectively provide a first scan signal, a second scan signal, and a third scan signal to the pixel driving circuit. The light emission signal line 34 is configured to provide a light emission control signal to the pixel driving circuit. The first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 are configured to respectively provide a first initial signal, a second initial signal, and a third initial signal to the pixel driving circuit. The data signal line 61 is configured to provide a data signal to the pixel driving circuit. The first power line 71 is configured to provide a first power signal to the pixel driving circuit.

[0105] In an exemplary embodiment, the shapes of the first scan signal line 31, the second scan signal line 32, the third scan signal line 33, the light-emitting signal line 34, the first initial signal line 41, the second initial signal line 42 and the third initial signal line 43 can be straight lines or broken lines with the main parts extending along the first direction X, and the shapes of the data signal line 61 and the first power line 71 can be straight lines or broken lines with the main parts extending along the second direction Y.

[0106] In this disclosure, "A extends along direction B" means that A can include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B."

[0107] In an exemplary embodiment, in the second direction Y, the first scan signal line 31 may be located on a side of the storage capacitor opposite to the second direction Y, the third scan signal line 33 may be located on a side of the first scan signal line 31 away from the storage capacitor, and the first initial signal line 41 may be located on a side of the third scan signal line 33 away from the storage capacitor. The light-emitting signal line 34 may be located on a side of the storage capacitor in the second direction Y, the second scan signal line 32 may be located on a side of the light-emitting signal line 34 away from the storage capacitor, the second initial signal line 42 may be located on a side of the second scan signal line 32 away from the storage capacitor, and the third initial signal line 43 may be located on a side of the second initial signal line 42 away from the storage capacitor.

[0108] In an exemplary embodiment, at least one circuit unit may further include a power connection line 44. The power connection line 44 may be shaped as a straight line or a broken line, with the main portion extending along the first direction X. The power connection line 44 may be located between the first scanning signal line 31 and the light-emitting signal line 34, and the orthographic projection of the power connection line 44 on the substrate may at least partially overlap with the orthographic projection of the storage capacitor on the substrate. In an exemplary embodiment, the first power line 71 may be connected to the power connection line 44 via a power via K1, so that the first power line 71 and the power connection line 44 form a mesh-like interconnected structure on the display substrate for transmitting the first power signal. In an exemplary embodiment, the power connection line 44 is connected to the second plate of the storage capacitor in the pixel driving circuit. In an exemplary embodiment, the pixel driving circuit further includes a power connection electrode, which is connected to the power connection line 44.

[0109] In an exemplary embodiment, the first power line 71 may be provided in some circuit cells. For example, the first power line 71 may be provided in the circuit cells of the Nth cell column, the N+1th cell column, the N+3th cell column, and the N+4th cell column, while the first power line 71 is not provided in the circuit cells of the N+2th cell column and the N+5th cell column.

[0110] In an exemplary embodiment, in at least one circuit unit and adjacent circuit units in the first direction X, the first power lines 71 of the two circuit units are interconnected as a single unit. For example, the first power lines 71 of the Nth unit column and the first power lines 71 of the N+1th unit column can be interconnected as a single unit, so that the first power lines 71 of the two unit columns form a single, integrated structure. For another example, the first power lines 71 of the N+3th unit column and the first power lines 71 of the N+4th unit column can be interconnected as a single unit, so that the first power lines 71 of the two unit columns form a single, integrated structure.

[0111] In an exemplary embodiment, in at least one circuit cell and an adjacent circuit cell in the first direction X, the data signal line 61 in one circuit cell may be located on the side opposite to the first power line 71 in the circuit cell in the first direction X, while the data signal line 61 in the other circuit cell may be located on the side opposite to the first power line 71 in the circuit cell in the first direction X. For example, in the Nth cell column, the data signal line 61 may be located on the side opposite to the first power line 71 in the first direction X, while in the N+1th cell column, the data signal line 61 may be located on the side opposite to the first power line 71 in the first direction X. Because the first power lines 71 in the Nth cell column and the N+1th cell column are interconnected and integrated, the two data signal lines 61 in the two adjacent cell columns are located on either side of the integrated first power line 71. For another example, in the N+3th cell column, the data signal line 61 may be located on the side opposite to the first power line 71 in the first direction X, while in the N+4th cell column, the data signal line 61 may be located on the side opposite to the first power line 71 in the first direction X. Since the first power lines 71 in the (N+3)th unit column and the (N+4)th unit column are connected to each other in an integrated structure, the two data signal lines 61 in two adjacent unit columns are respectively located on both sides of the first power line 71 of the integrated structure.

[0112] In an exemplary embodiment, in at least one circuit unit and an adjacent circuit unit in the first direction X, the positions of the data signal lines 61 in the two circuit units may be symmetrical with respect to a column center line, and the column center line may be a straight line located between adjacent circuit units in the first direction X and extending along the second direction Y.

[0113] In an exemplary embodiment, at least one pixel driving circuit may include at least a fourth transistor and a data connection electrode, the fourth transistor may include at least a fourth active layer, the data signal line 61 is connected to the data connection electrode through the data via K2, and the data connection electrode is connected to the first region of the fourth active layer.

[0114] In an exemplary embodiment, in at least one circuit unit and an adjacent circuit unit in the first direction X, the data signal line 61 in one circuit unit is connected to the data connection electrode in the circuit unit through a data via K2, and the data connection electrode is connected to the first region of the fourth active layer in the circuit unit through the via. The data signal line 61 in another circuit unit is connected to the data connection electrode in the circuit unit through the data via K2, and the data connection electrode is connected to the first region of the fourth active layer in the circuit unit through the data connection line. The data connection electrode is connected to the first end of the data connection line, and the second end of the data connection line extends along the first direction X and is connected to the first region of the fourth active layer through the via. This results in the two data signal lines 61 in the two adjacent circuit units being located on either side of the first power line 71.

[0115] In an exemplary embodiment, at least one pixel driving circuit may further include a sixth transistor, a seventh transistor, a fourth node electrode and an anode connecting electrode, the sixth transistor may include at least a sixth active layer, the seventh transistor may include at least a seventh active layer, the anode in at least one light-emitting unit is connected to the anode connecting electrode through the anode via K3, the anode connecting electrode is connected to the fourth node electrode, and the fourth node electrode is connected to the second region of the sixth active layer and the second region of the seventh active layer through a via.

[0116] In an exemplary embodiment, in at least one circuit unit and an adjacent circuit unit in the first direction X, the anode connection electrode in one circuit unit is connected to the fourth node electrode in the same circuit unit via a via, and the fourth node electrode is connected to the second region of the sixth active layer and the second region of the seventh active layer via a via. The anode connection electrode in another circuit unit is connected to the fourth node electrode in the same circuit unit via an anode connection line 63, and the fourth node electrode is connected to the second region of the sixth active layer and the second region of the seventh active layer via a via. Anode connection line 63 can be in the shape of a straight line or a zigzag line extending along the second direction Y. The anode connection electrode is connected to the first end of anode connection line 63, and the second end of anode connection line 63, after extending along the second direction Y, is connected to the fourth node electrode via a via. In an exemplary embodiment, anode connection line 63 is configured to improve the flatness of the anode.

[0117] In an exemplary embodiment, at least one circuit unit may further include an initial connection line 73, the shape of which may be a straight line or a broken line extending along the second direction Y, and the initial connection line 73 is connected to the first initial signal line 41, the second initial signal line 42 and / or the third initial signal line 43, so that the initial connection line 73 and the initial signal line form a mesh-like interconnected structure for transmitting the initial signal on the display substrate.

[0118] In an exemplary embodiment, at least one circuit unit may further include a second power line 72. The shape of the second power line 72 may be a straight line or a broken line extending along the second direction Y. The second power line 72 is configured to provide a second power signal to the cathode in the light-emitting unit to realize the VSS in pixel structure.

[0119] In an exemplary embodiment, the plurality of light-emitting units may include a first light-emitting unit that emits a first color light, a second light-emitting unit that emits a second color light, and a third light-emitting unit that emits a third color light. The first light-emitting unit may include at least a first anode 90A and a first pixel opening 100A exposing the first anode 90A, the second light-emitting unit may include at least a second anode 90B and a second pixel opening 100B exposing the second anode 90B, the third light-emitting unit may include at least a third anode 90C and a third pixel opening 100C exposing the third anode 90C, the first anode 90A, the second anode 90B, and the third anode 90C may be set in the anode conductive layer, and the first pixel opening 100A, the second pixel opening 100B, and the third pixel opening 100C may be set in the pixel definition layer.

[0120] In an exemplary embodiment, the second anode 90B can be arranged on one side of the first anode 90A in the second direction Y, and the third anode 90C can be arranged on one side of the first anode 90A and the second anode 90B in the first direction X, that is, the second pixel opening 100B is arranged on one side of the first pixel opening 100A in the second direction Y, and the third pixel opening 100C is arranged on one side of the first pixel opening 100A and the second pixel opening 100B in the first direction X.

[0121] In an exemplary embodiment, the orthographic projection of any one or more of the first pixel opening 100A, the second pixel opening 100B, and the third pixel opening 100C on the substrate does not overlap with the orthographic projection of the power via K1 on the substrate.

[0122] In an exemplary embodiment, the orthographic projections of the first and second pixel openings 100A and 100B on the substrate at least partially overlap with the orthographic projection of the first power line 71 on the substrate, and the orthographic projection of the third pixel opening 100C on the substrate does not overlap with the orthographic projection of the first power line 71 on the substrate.

[0123] In an exemplary embodiment, the orthographic projections of the first and second pixel openings 100A and 100B on the substrate do not overlap with the orthographic projection of the second power line 72 on the substrate, and the orthographic projection of the third pixel opening 100C on the substrate at least partially overlaps with the orthographic projection of the second power line 72 on the substrate.

[0124] In an exemplary embodiment, the orthographic projections of the first and second pixel openings 100A and 100B on the substrate do not overlap with the orthographic projection of the data signal line 61 on the substrate, and the orthographic projection of the third pixel opening 100C on the substrate at least partially overlaps with the orthographic projection of the data signal line 61 on the substrate.

[0125] In an exemplary embodiment, the orthographic projections of the first and second pixel openings 100A and 100B on the substrate do not overlap with the orthographic projection of the initial connection line 63 on the substrate, and the orthographic projection of the third pixel opening 100C on the substrate at least partially overlaps with the orthographic projection of the initial connection line 63 on the substrate.

[0126] In an exemplary embodiment, the orthographic projections of the first pixel opening 100A and the second pixel opening 100B on the substrate are located within the range of the orthographic projection of the first power line 71 on the substrate.

[0127] In an exemplary embodiment, the third pixel opening 100C may have an opening center line, which is an imaginary line extending along the second direction Y and passing through the geometric center of the third pixel opening 100C. In at least one third pixel opening 100C, the data signal line 61 and the anode connection line 63 may be symmetrically arranged with respect to the opening center line, and the second power line 72 and the initial connection line 73 may be symmetrically arranged with respect to the opening center line.

[0128] In an exemplary embodiment, any one or more of the first pixel opening 100A, the second pixel opening 100B, and the third pixel opening 100C have their orthographic projections on the substrate not overlap with the orthographic projections of the data via K2 on the substrate, and their orthographic projections on the substrate do not overlap with the orthographic projections of the anode via K3 on the substrate.

[0129] In an exemplary embodiment, in the second direction Y, the first pixel opening 100A, the second pixel opening 100B, and the third pixel opening 100C may be disposed at a region of the corresponding circuit unit close to a next unit row.

[0130] In an exemplary embodiment, the orthographic projection of the first pixel opening 100A on the substrate at least partially overlaps with the orthographic projection of the power connection line 44 on the substrate, and does not overlap with the orthographic projection of the first initial signal line 41 on the substrate.

[0131] In an exemplary embodiment, the orthographic projection of the second pixel opening 100B on the substrate at least partially overlaps with the orthographic projections of the first initial signal line 41, the second initial signal line 42, and the second initial signal line 43 on the substrate, and the orthographic projection of the second pixel opening 100B on the substrate does not overlap with the orthographic projections of the first scanning signal line 31 and the power connection line 44 on the substrate.

[0132] In an exemplary embodiment, the orthographic projection of the third pixel opening 100C on the substrate at least partially overlaps with the orthographic projections of the second scanning signal line 32, the light emitting signal line 34, the second initial signal line 42 and the power connection line 44 on the substrate, and the orthographic projection of the third pixel opening 100C on the substrate does not overlap with the orthographic projections of the first scanning signal line 31 and the third scanning signal line 33 on the substrate.

[0133] In an exemplary embodiment, on a plane perpendicular to the display substrate, the driving structure layer may include at least: a shielding layer disposed on the substrate, a first insulating layer disposed on a side of the shielding layer away from the substrate, a semiconductor layer disposed on a side of the first insulating layer away from the substrate, a second insulating layer disposed on a side of the semiconductor layer away from the substrate, a first conductive layer disposed on a side of the second insulating layer away from the substrate, a third insulating layer disposed on a side of the first conductive layer away from the substrate, a second conductive layer disposed on a side of the third insulating layer away from the substrate, a fourth insulating layer disposed on a side of the second conductive layer away from the substrate, a third conductive layer disposed on a side of the fourth insulating layer away from the substrate, a first planar layer disposed on a side of the third conductive layer away from the substrate, a fourth conductive layer disposed on a side of the first planar layer away from the substrate, and a second planar layer disposed on a side of the fourth conductive layer away from the substrate. The light-emitting structure layer may include at least: an anode conductive layer disposed on a side of the second planar layer away from the substrate, a pixel definition layer disposed on a side of the anode conductive layer away from the substrate, an organic light-emitting layer disposed on a side of the pixel definition layer away from the substrate, and a cathode layer disposed on a side of the organic light-emitting layer away from the substrate.

[0134] In an exemplary embodiment, the blocking layer may include at least a blocking electrode, the semiconductor layer may include at least an active layer of multiple transistors and a first initial signal line, the first conductive layer may include at least a second scanning signal line, a light-emitting signal line and a first plate of a storage capacitor, the second conductive layer may include at least a shielding electrode and a second plate of a storage capacitor, the third conductive layer may include at least a first scanning signal line, a third scanning signal line, a second initial signal line, a third initial signal line, a power connection line and multiple connection electrodes, and the fourth conductive layer may include at least a data signal line, a first power line, a second power line and an initial connection line.

[0135] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes the deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes the coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0136] In an exemplary embodiment, taking 12 circuit units (the Mth unit row and the M+1th unit row, and the Nth to N+5th unit columns) as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0137] (11) Forming a blocking layer pattern. In an exemplary embodiment, forming the blocking layer pattern may include: depositing a blocking film on a substrate, patterning the blocking film through a patterning process, and forming a blocking layer pattern on the substrate, as shown in FIG6 . In an exemplary embodiment, the blocking layer may be referred to as a bottom metal (LS) layer.

[0138] In an exemplary embodiment, the shielding layer pattern of each circuit unit may include at least a shielding electrode 90 , a first shielding connection bar 91 , a second shielding connection bar 92 , a third shielding connection bar 93 , a first shielding block 94 , and a second shielding block 95 .

[0139] In an exemplary embodiment, the shielding electrode 90 may be rectangular in shape, with chamfers or grooves provided at the corners of the rectangle. The shielding electrode 90 may be provided in a central region of the circuit unit in the first direction X and the second direction Y.

[0140] In an exemplary embodiment, the shape of the first shielding connection strip 91 can be a straight line or a broken line with the main part extending along the first direction X. The first shielding connection strip 91 can be arranged on one side of the shielding electrode 90 in the first direction X or on the side opposite to the first direction X of the shielding electrode 90. The first end of the first shielding connection strip 91 is connected to the shielding electrode 90 of the current circuit unit, and the second end of the first shielding connection strip 91 is connected to the shielding electrode 90 of the adjacent circuit unit in the first direction X.

[0141] In an exemplary embodiment, in at least one cell row, the shielding electrodes 90 and the first shielding connection bars 91 may be connected to each other in an integrated structure.

[0142] In an exemplary embodiment, the shape of the second shielding connection strip 92 can be a straight line or a broken line with the main part extending along the second direction Y. The second shielding connection strip 92 can be arranged on one side of the shielding electrode 90 in the second direction Y. The first end of the second shielding connection strip 92 is connected to the shielding electrode 90 of the current circuit unit, and the second end of the second shielding connection strip 92 is connected to the second shielding block 95 of the adjacent circuit unit in the second direction Y.

[0143] In an exemplary embodiment, the shape of the third shielding connection strip 93 can be a straight line or a broken line with the main part extending along the second direction Y. The third shielding connection strip 93 can be arranged on the side opposite to the second direction Y of the shielding electrode 90. The first end of the third shielding connection strip 93 is connected to the shielding electrode 90, and the second end of the third shielding connection strip 93 is connected to the first shielding block 94.

[0144] In an exemplary embodiment, the shape of the first blocking block 94 can be block-shaped (such as a rectangle) and can be arranged on the side opposite to the second direction Y of the blocking electrode 90. The first end of the first blocking block 94 is connected to the third blocking connecting strip 93, and the second end of the first blocking block 94 is connected to the second blocking block 95.

[0145] In an exemplary embodiment, the shape of the second blocking block 95 can be block-shaped (such as rectangular) and can be arranged on the side of the second blocking block 95 away from the blocking electrode 90. The first end of the second blocking block 95 is connected to the first blocking block 94, and the second end of the second blocking block 95 is connected to the second blocking connecting strip 92 of the adjacent circuit unit in the opposite direction of the second direction Y.

[0146] In an exemplary embodiment, in at least one unit column, the second blocking block 95 , the first blocking block 94 , the third blocking connecting bar 93 , the blocking electrode 90 , and the second blocking connecting bar 92 are sequentially connected to form an interconnected integral structure.

[0147] In an exemplary embodiment, the blocking layers in multiple unit rows and multiple unit columns can be an integrated structure that is interconnected, which can ensure that the blocking layers in the display substrate have the same electric potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0148] In an exemplary embodiment, the position and shape of the shielding layer in a plurality of cell rows may be substantially the same, and the position and shape of the shielding layer in a plurality of cell columns may be substantially the same.

[0149] (12) Forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a first insulating layer covering the shielding layer, and a semiconductor layer pattern disposed on the first insulating layer, as shown in FIG7A and FIG7B , where FIG7B is a plan view schematic diagram of the semiconductor layer in FIG7A .

[0150] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit may include at least the first active layer 11 of the first transistor T1 to the eighth active layer 18 of the eighth transistor T8, and the first initial signal line 41, and the first active layer 11 to the seventh active layer 17 and the first initial signal line 41 are an integrated structure connected to each other, and the eighth active layer 18 may be provided separately.

[0151] In an exemplary embodiment, in the first direction X, the second active layer 12, the sixth active layer 16, and the seventh active layer 17 may be located on a side of the third active layer 13 opposite to the first direction X, and the fourth active layer 14 and the eighth active layer 18 may be located on a side of the third active layer 13 in the first direction X. In the second direction Y, the first active layer 11, the second active layer 12, the fourth active layer 14, and the first initial signal line 41 may be located on a side of the third active layer 13 opposite to the second direction Y, and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, and the eighth active layer 18 may be located on a side of the third active layer 13 in the second direction Y.

[0152] In an exemplary embodiment, the shape of the third active layer 13 may be an "Ω" shape, the shapes of the first active layer 11, the fourth active layer 14, the sixth active layer 16, the seventh active layer 17 and the eighth active layer 18 may be an "I" shape, the shapes of the second active layer 12 and the fifth active layer 15 may be an "L" shape, and the shape of the first initial signal line 41 may be a straight line or a broken line with the main portion extending along the first direction X.

[0153] In an exemplary embodiment, each of the first to eighth active layers 11 to 18 may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be interconnected, and the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be interconnected, and the first region 13-1 of the third active layer may serve as both the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer. The second region 12-1 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer may be interconnected, and the second region 12-1 of the second active layer may serve as both the second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer may be connected to each other, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer and the first initial signal line 41 may be connected to each other, and the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the second region 18-2 of the eighth active layer may be provided separately.

[0154] In an exemplary embodiment, the shape of the first initial signal line 41 can be a zigzag shape or a zigzag shape with the main portion extending along the first direction X, and can be located on the side of the first active layer 11 away from the third active layer 13, and the first initial signal line 41 is connected to the first region 11-1 of the first active layer of multiple circuit units in a unit row.

[0155] In an exemplary embodiment, the first initial signal line 41 and the first active layers of the plurality of circuit units in a unit row may be integrally connected. Since the first region of the first active layer and the first initial signal line 41 are integrally connected, this not only improves the reliable connection between the first initial signal line and the first electrode of the first transistor, but also reduces the number of vias and the space occupied by the pixel driver circuit, thereby facilitating high-resolution (PPI) display.

[0156] In an exemplary embodiment, in at least one circuit unit, a first initial connection block may be provided on the first initial signal line, and the first initial connection block is configured to be connected to the subsequently formed initial connection line, so that the first initial signal line extending along the first direction and the initial connection line extending along the second direction form a meshed interconnected structure for transmitting the first initial signal, which is not limited in the present disclosure.

[0157] In an exemplary embodiment, the orthographic projection of the third active layer 13 on the substrate at least partially overlaps with the orthographic projection of the shielding electrode 90 on the substrate. The shielding electrode 90 can serve as a shielding layer for the third transistor T3, shielding the channel region of the third transistor T3 to ensure the electrical performance of the third transistor T3.

[0158] In an exemplary embodiment, the orthographic projection of the channel region of the third active layer 13 on the substrate is located within the range of the orthographic projection of the shielding electrode 90 on the substrate.

[0159] In an exemplary embodiment, the orthographic projection of the second active layer 12 on the substrate at least partially overlaps with the orthographic projection of the first blocking block 94 on the substrate. The first blocking block 94 can serve as a blocking layer for the second transistor T2, blocking the channel region of the second transistor T2 and ensuring the electrical performance of the second transistor T2.

[0160] In an exemplary embodiment, the orthographic projection of the channel region of the second active layer 12 on the substrate is located within the range of the orthographic projection of the first blocking block 94 on the substrate.

[0161] In an exemplary embodiment, the orthographic projection of the first active layer 11 on the substrate at least partially overlaps with the orthographic projection of the second blocking block 95 on the substrate. The second blocking block 95 can serve as a blocking layer for the first transistor T1, blocking the channel region of the first transistor T1 and ensuring the electrical performance of the first transistor T1.

[0162] In an exemplary embodiment, the orthographic projection of the channel region of the first active layer 11 on the substrate is located within the range of the orthographic projection of the second blocking block 95 on the substrate.

[0163] In example embodiments, positions and shapes of semiconductor layers in a plurality of cell rows may be substantially the same, and positions and shapes of semiconductor layers in a plurality of cell columns may be substantially the same.

[0164] In an exemplary embodiment, the semiconductor layer may be made of polycrystalline silicon (p-Si), i.e., the third to seventh transistors are LTPS transistors. In an exemplary embodiment, patterning the semiconductor film through a patterning process may include: first forming an amorphous silicon (a-Si) film on a first insulating film, performing a dehydrogenation treatment on the amorphous silicon film, and then crystallizing the dehydrogenated amorphous silicon film to form a polycrystalline silicon film. Subsequently, patterning the polycrystalline silicon film to form a semiconductor layer pattern.

[0165] (13) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG8A and FIG8B , where FIG8B is a plan view schematic diagram of the first conductive layer in FIG8A . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0166] In an exemplary embodiment, the first conductive layer pattern of each circuit unit includes at least a first gate electrode 21 , a second gate electrode 22 , a fourth gate electrode 24 , a second scan signal line 32 , a light emitting signal line 34 and a first plate 81 of a storage capacitor.

[0167] In an exemplary embodiment, the first electrode plate 81 may be rectangular, with chamfered or grooved corners. The orthographic projection of the first electrode plate 81 on the substrate at least partially overlaps the orthographic projection of the third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 81 may serve as both a plate of the storage capacitor and a gate electrode of the third transistor T3.

[0168] In an exemplary embodiment, the orthographic projection of the channel region of the third active layer on the substrate is located within the range of the orthographic projection of the first electrode plate 81 on the substrate.

[0169] In an exemplary embodiment, an orthographic projection of the first electrode plate 81 on the substrate at least partially overlaps with an orthographic projection of the shielding electrode 90 on the substrate.

[0170] In an exemplary embodiment, the first gate electrode 21 may be C-shaped and may be located on the side of the first electrode 81 opposite to the second direction Y. The orthographic projection of the first gate electrode 21 on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate. The overlapping region of the first gate electrode 21 and the first active layer may serve as the gate electrode of the first transistor T1 of the dual-gate structure. In an exemplary embodiment, the first gate electrode 21 is configured to be connected to a third scan signal line to be formed subsequently.

[0171] In an exemplary embodiment, the second gate electrode 22 may be L-shaped and may be located between the first electrode plate 81 and the first gate electrode 21. The orthographic projection of the second gate electrode 22 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate. The overlapping region between the second gate electrode 22 and the second active layer may serve as the gate electrode of the second transistor T2 of the dual-gate structure. In an exemplary embodiment, the second gate electrode 22 is configured to be connected to a first scan signal line to be formed subsequently.

[0172] In an exemplary embodiment, the fourth gate electrode 24 may be in the shape of a strip extending along the first direction X and may be located between the first electrode plate 81 and the first gate electrode 21. The orthographic projection of the fourth gate electrode 24 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer on the substrate. The overlapping region of the fourth gate electrode 24 and the fourth active layer may serve as the gate electrode of the fourth transistor T4. In an exemplary embodiment, the second gate electrode 22 is configured to be connected to a first scan signal line formed subsequently.

[0173] In an exemplary embodiment, the fourth gate electrode 24 in the current circuit unit and the second gate electrode 22 in the adjacent circuit unit in the first direction X may be interconnected as an integral structure. For example, in a cell row, the fourth gate electrode 24 in the Nth cell column and the second gate electrode 22 in the N+1th cell column may be interconnected as an integral structure.

[0174] In an exemplary embodiment, the shape of the second scanning signal line 32 can be a straight line or a broken line with the main portion extending along the first direction X. The second scanning signal line 32 can be located on one side of the first electrode 81 in the second direction Y. The area where the second scanning signal line 32 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7, and the area where the second scanning signal line 32 overlaps with the eighth active layer can serve as the gate electrode of the eighth transistor T8.

[0175] In an exemplary embodiment, a second scan connection block 32-1 may be provided on the second scan signal line 32. The second scan connection block 32-1 may be in a block shape (e.g., a rectangle), a first end of the second scan connection block 32-1 is connected to a side of the second scan signal line 32 close to the first electrode plate 81, and a second end of the second scan connection block 32-1 extends toward the first electrode plate 81. The second scan connection block 32-1 is configured to be connected to a subsequently formed auxiliary scan signal line.

[0176] In an exemplary embodiment, the shape of the light-emitting signal line 34 can be a straight line or a broken line with the main part extending along the first direction X. The light-emitting signal line 34 can be located between the first electrode 81 and the second scanning signal line 32. The area where the light-emitting signal line 34 overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5, and the area where the light-emitting signal line 34 overlaps with the sixth active layer can serve as the gate electrode of the sixth transistor T6.

[0177] In example embodiments, positions and shapes of the first conductive layers in a plurality of cell rows may be substantially the same, and positions and shapes of the first conductive layers in a plurality of cell columns may be substantially the same.

[0178] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the eighth transistor T8, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first initial signal line 41 and the first and second areas of the first to eighth transistors T1 to T8 are all conductorized.

[0179] (14) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG9A and FIG9B , where FIG9B is a plan view schematic diagram of the second conductive layer in FIG9A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0180] In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least a second plate 82 of the storage capacitor and a shielding electrode 35 .

[0181] In an exemplary embodiment, the outline of the second plate 82 of the storage capacitor can be rectangular, and the corners of the rectangle can be provided with chamfers or grooves. The orthographic projection of the second plate 82 on the substrate at least partially overlaps with the orthographic projection of the first plate 81 on the substrate. The second plate 82 can serve as another plate of the storage capacitor, and the first plate 81 and the second plate 82 constitute the storage capacitor of the pixel driving circuit.

[0182] In an exemplary embodiment, the second electrode plate 82 may be provided with a plate-level connecting bar 83. The plate-level connecting bar 83 may be in the shape of a straight line or a broken line extending along the first direction X. The plate-level connecting bar 83 may be provided on one side of the second electrode plate 82 in the first direction X or on a side opposite to the first direction X. The first end of the plate-level connecting bar 83 is connected to the second electrode plate 82 in the circuit unit in question, and the second end of the plate-level connecting bar 83 is connected to the second electrode plate 82 in the adjacent circuit unit in the first direction X. Because the second electrode plate 82 in each circuit unit is connected to a subsequently formed first power line, by interconnecting the second electrode plates 82 of adjacent circuit units, the second electrode plates 82 and the plate-level connecting bar 83 can be reused as power signal lines. This ensures that multiple second electrode plates in a unit row have the same potential, which helps improve panel uniformity, prevents display defects on the display substrate, and ensures the display quality of the display substrate.

[0183] In an exemplary embodiment, the second electrode plates 82 and the plate-level connecting bars 83 in a plurality of circuit cells in one cell row may be an integral structure connected to each other.

[0184] In an exemplary embodiment, an opening 84 is provided on the second electrode plate 82. Opening 84 can be rectangular and located in the central region of the second electrode plate 82, forming an annular structure. Opening 84 exposes the third insulating layer covering the first electrode plate 81, and the orthographic projection of the first electrode plate 81 on the substrate includes the orthographic projection of opening 84 on the substrate. In an exemplary embodiment, opening 84 is configured to accommodate a ninth via hole to be formed later. The ninth via hole is located within opening 84 and exposes the first electrode plate 81, allowing a first connecting electrode to be formed later to connect to the first electrode plate 81.

[0185] In an exemplary embodiment, the shielding electrode 35 may be shaped like an inverted "U" and may be located on a side of the second electrode plate 82 proximal to the second transistor T2. The orthographic projection of the shielding electrode 35 on the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor T2 (the node between the two gate electrodes) on the substrate. In an exemplary embodiment, the shielding electrode 35 is configured to shield the first transistor T1 and the second transistor T2 from the effects of data voltage jumps, thereby preventing the data voltage jumps from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0186] In an exemplary embodiment, a shielding electrode 35 may be provided in each circuit unit. The inverted U-shaped shielding electrode 35 may include a first extension segment 35-1, a second extension segment 35-2, and a third extension segment 35-3, which are connected in sequence. The first end of the first extension segment 35-1 is connected to the second electrode plate 82. The second end of the first extension segment 35-1 extends away from the second electrode plate 82 along the second direction Y and then connects to the first end of the second extension segment 35-2. The orthographic projection of the first extension segment 35-1 on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate. The second end of the second extension segment 35-2 extends toward the second transistor T2 along the first direction X and then connects to the first end of the third extension segment 35-3. The second extension segment 35-2 is configured to overlap with a subsequently formed data connection line to prevent data voltage jumps from affecting the first transistor T1. The second end of the third extension segment 35-3 extends along the second direction Y toward the direction close to the second electrode 82, and the positive projection of the third extension segment 35-3 on the substrate at least partially overlaps with the positive projection of the semiconductor layer between the two gate electrodes of the second transistor T2 on the substrate. The third extension segment 35-3 is configured to shield the influence of the data voltage jump on the second transistor T2.

[0187] In an exemplary embodiment, in at least one circuit unit, the shielding electrode 35 and the second electrode plate 82 may be connected to each other as an integral structure. Since the second electrode plate 82 is connected to a first power line formed later, the shielding electrode 35 has the potential of the first power line.

[0188] In example embodiments, positions and shapes of the second conductive layers in a plurality of cell rows may be substantially the same, and positions and shapes of the second conductive layers in a plurality of cell columns may be substantially the same.

[0189] (15) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of vias are provided on the fourth insulating layer, as shown in FIG. 10 .

[0190] In an exemplary embodiment, the multiple vias of each circuit unit include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11 and a twelfth via V12.

[0191] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the second region of the first active layer (also the first region of the second active layer) on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the first via hole V1 are etched away to expose the surface of the second region of the first active layer (also the first region of the second active layer), and the first via hole V1 is configured to connect a subsequently formed first connecting electrode to the second region of the first active layer (also the first region of the second active layer) through the via hole.

[0192] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the first area of ​​the third active layer (also the second area of ​​the fourth active layer and the second area of ​​the fifth active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the first area of ​​the third active layer (also the second area of ​​the fourth active layer and the second area of ​​the fifth active layer), and the second via hole V2 is configured to connect a subsequently formed second connecting electrode to the first area of ​​the third active layer (also the second area of ​​the fourth active layer and the second area of ​​the fifth active layer) through the via hole.

[0193] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the third via hole V3 are etched away to expose the surface of the first area of ​​the fourth active layer, and the third via hole V3 is configured to connect a subsequently formed third connecting electrode to the first area of ​​the fourth active layer through the via hole.

[0194] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the fourth via hole V4 are etched away to expose the surface of the first region of the fifth active layer, and the fourth via hole V4 is configured to connect a subsequently formed fourth connecting electrode to the first region of the fifth active layer through the via hole.

[0195] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the fifth via hole V5 is configured to connect the subsequently formed fifth connecting electrode to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) through the via hole.

[0196] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via V6 are etched away to expose the surface of the first region of the seventh active layer, and the sixth via V6 is configured to connect a subsequently formed second initial signal line to the first region of the seventh active layer through the via.

[0197] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via V7 are etched away to expose the surface of the first region of the eighth active layer, and the seventh via V7 is configured to connect a subsequently formed third initial signal line to the first region of the eighth active layer through the via.

[0198] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second region of the eighth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighth via V8 are etched away to expose the surface of the second region of the eighth active layer, and the eighth via V8 is configured to connect a subsequently formed second connecting electrode to the second region of the eighth active layer through the via hole.

[0199] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the opening 84 on the substrate, the fourth insulating layer and the third insulating layer in the ninth via hole V9 are etched away to expose the surface of the first electrode 81, and the ninth via hole V9 is configured to connect the subsequently formed first connecting electrode to the first electrode 81 through the via hole.

[0200] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is within the range of the orthographic projection of the second electrode plate 82 on the substrate. The fourth insulating layer in the tenth via hole V10 is etched away, exposing the surface of the second electrode plate 82. The tenth via hole V10 is configured to allow a subsequently formed power connection line to be connected to the second electrode plate 82 through the via hole. In an exemplary embodiment, there may be multiple tenth via holes V10, and the multiple tenth via holes V10 may be arranged sequentially along the first direction X to improve connection reliability.

[0201] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first gate electrode 21 on the substrate, the fourth insulating layer and the third insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first gate electrode 21, and the eleventh via hole V11 is configured to connect a subsequently formed third scan signal line to the first gate electrode 21 through the via hole.

[0202] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the second gate electrode 22 (also the fourth gate electrode 24) on the substrate, the fourth insulating layer and the third insulating layer in the twelfth via hole V12 are etched away to expose the surface of the second gate electrode 22 (also the fourth gate electrode 24), and the twelfth via hole V12 is configured to connect the subsequently formed first scanning signal line to the second gate electrode 22 (also the fourth gate electrode 24) through the via hole.

[0203] In an exemplary embodiment, the fourth insulating layer of at least one circuit unit may further include a thirteenth via hole V13 .

[0204] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the second scan connection block 32-1 of the second scan signal line 32 on the substrate, the fourth insulating layer and the third insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the second scan connection block 32-1, and the thirteenth via hole V13 is configured to connect a subsequently formed auxiliary scan signal line to the second scan connection block 32-1 through the via hole.

[0205] In an exemplary embodiment, positions and shapes of the plurality of via holes in the plurality of cell rows may be substantially the same, and positions and shapes of the plurality of via holes in the plurality of cell columns may be substantially the same.

[0206] (16) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the fourth insulating layer, as shown in FIG11A and FIG11B , where FIG11B is a plan view schematic diagram of the third conductive layer in FIG11A . In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0207] In an exemplary embodiment, the third conductive layer of each circuit unit includes at least: a first scan signal line 31, a third scan signal line 33, a second initial signal line 42, a third initial signal line 43, a power connection line 44, an auxiliary scan signal line 45, a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54 and a fifth connection electrode 55.

[0208] In an exemplary embodiment, the shape of the first scanning signal line 31 can be a straight line or a broken line with the main part extending along the first direction X. The first scanning signal line 31 can be located on the side of the second electrode 82 in the opposite direction of the second direction Y. The first scanning signal line 31 is connected to the second gate electrode 22 (also the fourth gate electrode 24) in each circuit unit through the twelfth via V12 in each circuit unit, so that the first scanning signal line 31 writes the first scanning signal into the gate electrode of the second transistor T2 and the gate electrode of the fourth transistor T4 respectively.

[0209] In an exemplary embodiment, the shape of the third scan signal line 33 can be a straight line or a broken line with the main portion extending along the first direction X. The first scan signal line 33 can be located on the side of the first scan signal line 31 away from the second electrode 82. The third scan signal line 33 is connected to the first gate electrode 21 in each circuit unit through the eleventh via V11 in each circuit unit, so that the third scan signal line 33 writes the third scan signal into the gate electrode of the first transistor T1.

[0210] In an exemplary embodiment, the shape of the second initial signal line 42 can be a straight line or a broken line with the main portion extending along the first direction X. The second initial signal line 42 can be located on one side of the second electrode plate 82 in the second direction Y. The second initial signal line 42 is connected to the first area of ​​the seventh active layer in each circuit unit through the sixth via V6 in each circuit unit, so that the second initial signal line 42 writes the second initial signal into the first electrode of the seventh transistor T7.

[0211] In an exemplary embodiment, in at least one circuit unit, a second initial connection block may be provided on the second initial signal line, and the second initial connection block is configured to be connected to the subsequently formed initial connection line, so that the second initial signal line extending along the first direction and the initial connection line extending along the second direction form a meshed interconnected structure for transmitting the second initial signal, which is not limited in the present disclosure.

[0212] In an exemplary embodiment, the shape of the third initial signal line 43 can be a straight line or a broken line with the main portion extending along the first direction X. The third initial signal line 43 can be located on the side of the second initial signal line 42 away from the second electrode plate 82. The third initial signal line 43 is connected to the first area of ​​the eighth active layer in each circuit unit through the seventh via V7 in each circuit unit, so that the third initial signal line 43 writes the third initial signal into the first electrode of the eighth transistor T7.

[0213] In an exemplary embodiment, in at least one circuit unit, a third initial connection block may be provided on the third initial signal line, and the third initial connection block is configured to be connected to the subsequently formed initial connection line, so that the third initial signal line extending along the first direction and the initial connection line extending along the second direction form a meshed connection structure for transmitting the third initial signal, which is not limited in the present disclosure.

[0214] In an exemplary embodiment, the power connection line 44 may be in the shape of a straight line or a broken line, with the main portion extending along the first direction X. The power connection line 44 may be located between the first scanning signal line 31 and the light-emitting signal line 34. The orthographic projection of the power connection line 44 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 82 on the substrate. The power connection line 44 is connected to the second electrode plate 82 in each circuit unit through the tenth via V10 in each circuit unit. Since the power connection line 44 is configured to be connected to the first power line formed later, the first power line can write the first power signal to the second electrode plate 82 of the storage capacitor.

[0215] In an exemplary embodiment, the power connection line 44 in some circuit units may be provided with a power connection block 44-1. The power connection block 44-1 may be in a block shape (e.g., rectangular). A first end of the power connection block 44-1 is connected to a side of the power connection line 44 close to the first scan signal line 31, and a second end of the power connection block 44-1 extends toward the first scan signal line 31. In an exemplary embodiment, the power connection block 44-1 is configured to be connected to a first power line formed later.

[0216] In an exemplary embodiment, the power connection block 44 - 1 may be provided in a plurality of circuit cells of the N+1th cell column and the N+4th cell column.

[0217] In an exemplary embodiment, the power connection line 44 and the power connection block 44 - 1 may be an integral structure connected to each other.

[0218] In an exemplary embodiment, the auxiliary scan signal line 45 may be shaped as a straight line or a zigzag line, with its main portion extending along the first direction X. The orthographic projection of the auxiliary scan signal line 45 on the substrate at least partially overlaps with the orthographic projection of the second scan signal line 32 on the substrate. The auxiliary scan signal line 45 is connected to the second scan connection block 32-1 via a thirteenth via hole V13. Because the second scan connection block 32-1 is connected to the second scan signal line 32, the second scan signal line 32 and the auxiliary scan signal line 45 form a double-layer structure of scan signal lines, which effectively reduces the resistance of the scan signal lines and the voltage drop of the scan signals.

[0219] In an exemplary embodiment, the first connection electrode 51 may be in the shape of a strip extending along the second direction Y. A first end of the first connection electrode 51 is connected to the second region of the first active layer (also the first region of the second active layer) via a first via hole V1. A second end of the first connection electrode 51 extends along the second direction Y and is connected to the first electrode plate 81 via a ninth via hole V9. In an exemplary embodiment, because the first electrode plate 81 also serves as the gate electrode of the third transistor T3, the first connection electrode 51 causes the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 81 to have the same potential, thereby forming a first node N1 of the pixel driving circuit.

[0220] In an exemplary embodiment, the second connection electrode 52 may be in the shape of a strip extending along the second direction Y. A first end of the second connection electrode 52 is connected to the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer) via a second via hole V2. A second end of the second connection electrode 52 extends along the second direction Y and is connected to the second region of the eighth active layer via an eighth via hole V8. In an exemplary embodiment, the second connection electrode 52 causes the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8 to have the same potential, forming a second node N2 of the pixel driving circuit.

[0221] In an exemplary embodiment, the third connection electrode 53 in each circuit unit may be in a block shape (eg, rectangular) and configured to be connected to a subsequently formed data signal line. In an exemplary embodiment, the third connection electrode 53 may be referred to as a data connection electrode.

[0222] In an exemplary embodiment, the third connection electrode 53 of the circuit units in the N+1th unit column, the N+2th unit column, the N+4th unit column and the N+5th unit column can be arranged on one side of the first connection electrode 51 in the first direction X in the circuit unit, and the third connection electrode 53 is connected to the first region of the fourth active layer through the third via hole V3.

[0223] In an exemplary embodiment, positions and shapes of the third connection electrodes 53 in the (N+1)th, (N+2)th, (N+4)th, and (N+5)th cell columns may be substantially the same.

[0224] In an exemplary embodiment, the third connection electrode 53 of the circuit unit in the Nth unit column and the N+3th unit column can be arranged on the side opposite to the first direction X of the first connection electrode 51 in the circuit unit, and the third connection electrode 53 is connected to the first region of the fourth active layer through the data connection line 46.

[0225] In an exemplary embodiment, the third conductive layer of the circuit units in the Nth unit column and the N+3th unit column may further include a data connection line 46. The data connection line 46 may be in the shape of a strip extending along the first direction X. The first end of the data connection line 46 is connected to the third connection electrode 53. The second end of the data connection line 46 extends along the first direction X and is connected to the first area of ​​the fourth active layer through the third via hole V3.

[0226] In an exemplary embodiment, in at least one circuit unit, the third connection electrode 53 and the data connection line 46 may be an integral structure connected to each other.

[0227] In an exemplary embodiment, the orthographic projection of the data connection line 46 on the substrate at least partially overlaps the orthographic projection of the second extension 35-2 of the shielding electrode 35 on the substrate. Since the data connection line transmits a data signal, disposing a shielding electrode having the potential of the first power line below the data connection line can effectively prevent data voltage jumps from affecting the first transistor T1.

[0228] In an exemplary embodiment, positions and shapes of the third link electrodes 53 and the data link lines 46 in the Nth cell column and the (N+3)th cell column may be substantially the same.

[0229] In an exemplary embodiment, the fourth connection electrode 54 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the fourth connection electrode 54 is connected to the power connection line 44, and a second end of the fourth connection electrode 54 extends along the second direction Y and is connected to the first region of the fifth active layer through a fourth via V4. Because the power connection line 44 is configured to connect to a subsequently formed first power line, the first power line can write the first power signal to the first electrode of the fifth transistor T5. In an exemplary embodiment, the fourth connection electrode 54 can be referred to as a power connection electrode.

[0230] In an exemplary embodiment, in at least one unit row, the power connection line 44 and the plurality of fourth connection electrodes 54 may be connected to each other as an integrated structure, which can ensure that the first electrode of the fifth transistor T5 and the second electrode plate 82 of the storage capacitor of the plurality of circuit units in one unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0231] In an exemplary embodiment, the fifth connection electrode 55 may be in a block shape (e.g., a rectangular shape). The fifth connection electrode 55 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through a fifth via hole V5. The fifth connection electrode 55 is configured to be connected to a subsequently formed anode connection electrode. In an exemplary embodiment, the fifth connection electrode 55 may be referred to as a fourth node electrode.

[0232] In an exemplary embodiment, the shapes of the fifth connection electrodes 55 in the N+1th cell column, the N+2th cell column, the N+4th cell column, and the N+5th cell column may be substantially the same, the shapes of the fifth connection electrodes 55 in the Nth cell column and the N+3th cell column may be substantially the same, but the shapes of the fifth connection electrodes 55 in the Nth cell column and the N+1th cell column may be different.

[0233] (17) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the third conductive layer, wherein a plurality of vias are provided on the first planar layer, as shown in FIG. 12 .

[0234] In an exemplary embodiment, the plurality of via holes of each circuit unit includes at least a twenty-first via hole V21 and a twenty-second via hole V22 .

[0235] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the third connection electrode 53 on the substrate. The first planar layer in the twenty-first via hole V21 is removed, exposing the surface of the third connection electrode 53. The twenty-first via hole V21 is configured to connect a subsequently formed data signal line to the third connection electrode 53 through the via hole. In an exemplary embodiment, the twenty-first via hole V21 can be referred to as a data via hole.

[0236] In an exemplary embodiment, the positions of the data vias in some adjacent unit columns may be mirror-symmetrical with respect to a column centerline, where the column centerline may be a straight line located between adjacent unit columns and extending along the second direction Y. For example, the positions of the data vias in the Nth unit column and the positions of the data vias in the N+1th unit column may be mirror-symmetrical with respect to the column centerline. For another example, the positions of the data vias in the N+3th unit column and the positions of the data vias in the N+4th unit column may be mirror-symmetrical with respect to the column centerline.

[0237] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the fifth connecting electrode 55 on the substrate, the first flat layer in the twenty-second via hole V22 is removed, exposing the surface of the fifth connecting electrode 55, and the twenty-second via hole V22 is configured to connect the subsequently formed anode connecting electrode to the fifth connecting electrode 55 through the via hole.

[0238] In an exemplary embodiment, a twenty-third via V23 may also be provided on the first planar layer of some circuit units. The orthographic projection of the twenty-third via V23 on the substrate is located within the orthographic projection of the power connection block 44-1 of the power connection line 44 on the substrate. The first planar layer within the twenty-third via V23 is removed, exposing the surface of the power connection block 44-1. The twenty-third via V23 is configured to connect a subsequently formed first power line to the power connection block 44-1 through this via. In an exemplary embodiment, the twenty-third via V23 may be referred to as a power via.

[0239] In an exemplary embodiment, the twenty-third via hole V23 may be provided in a plurality of circuit cells of the N+1th cell column and the N+4th cell column.

[0240] (18) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process to form a fourth conductive layer disposed on the first flat layer, as shown in FIG13A and FIG13B , where FIG13B is a planar schematic diagram of the fourth conductive layer in FIG13A . In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0241] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least a data signal line 61 and an anode connection electrode 62 .

[0242] In an exemplary embodiment, the data signal line 61 may be in the shape of a straight line or a zigzag line extending along the second direction Y. The data signal line 61 is connected to the third connection electrode 53, which serves as the data connection electrode, through the twenty-first via hole V21. Since the third connection electrode 53 is connected to the first region of the fourth active layer, the data signal line 61 can write a data signal to the first electrode of the fourth transistor T4.

[0243] In an exemplary embodiment, the positions of the data signal lines 61 in different unit columns may be different. The data signal lines 61 in the Nth unit column and the N+3th unit column may be located on one side of the first connection electrode 51 (first power line 71) in the opposite direction of the first direction X, and the data signal lines 61 in the N+1th unit column, the N+2th unit column, the N+4th unit column, and the N+5th unit column may be located on one side of the first connection electrode 51 (first power line 71) in the first direction X.

[0244] In an exemplary embodiment, the data signal line 61 may include a main portion and a connecting portion. The main portion is a straight line extending along the second direction Y. The connecting portion is connected to the main portion. The connecting portion is connected to the third connecting electrode 53 via the twenty-first via V21. The position of the main portion of the data signal line 61 in some adjacent unit columns may be mirror-symmetrical with respect to the column center line A1. The column center line A1 may be a straight line extending along the second direction Y between adjacent unit columns. The column center line A11 is a virtual line. For example, the position of the main portion of the data signal line 61 in the Nth unit column and the position of the main portion of the data signal line 61 in the N+1th unit column may be mirror-symmetrical with respect to the column center line A1. For another example, the position of the main portion of the data signal line 61 in the N+3th unit column and the position of the main portion of the data signal line 61 in the N+4th unit column may be mirror-symmetrical with respect to the column center line A1.

[0245] In an exemplary embodiment, the anode connection electrode 62 in each circuit unit may be in a block shape (eg, a rectangular shape), and the anode connection electrode 62 is configured to be connected to an anode formed subsequently.

[0246] In an exemplary embodiment, the anode connection electrode 62 of the circuit units in the Nth unit column, the N+1th unit column, the N+3th unit column and the N+4th unit column can be arranged on one side of the second direction Y of the power connection line 44 in the circuit unit, and the anode connection electrode 62 is connected to the fifth connection electrode 55 through the twenty-second via V22.

[0247] In an exemplary embodiment, positions and shapes of the anode connection electrodes 62 in the Nth cell column, the N+1th cell column, the N+3th cell column, and the N+4th cell column may be substantially the same.

[0248] In an exemplary embodiment, the anode connecting electrode 62 of the circuit units in the N+2th unit column and the N+5th unit column can be arranged on the side opposite to the second direction Y of the power connection line 44 in the circuit unit, and the anode connecting electrode 62 is connected to the fifth connecting electrode 55 serving as the fourth node electrode through the anode connecting line 63.

[0249] In an exemplary embodiment, the fourth conductive layer of the circuit units in the N+2th unit column and the N+5th unit column may further include an anode connecting line 63, and the shape of the anode connecting line 63 may be a strip shape extending along the second direction Y. The first end of the anode connecting line 63 is connected to the anode connecting electrode 62, and the second end of the anode connecting line 63 extends along the first direction X and is connected to the fifth connecting electrode 55 through the twenty-second via hole V22.

[0250] In an exemplary embodiment, the anode connection line 63 may include a first connection sub-line 63-1 and a second connection sub-line 63-2. The first end of the first connection sub-line 63-1 is connected to the anode connection electrode 62. The second end of the first connection sub-line 63-1 extends along the second direction Y toward a direction close to the fifth connection electrode 55 and is then connected to the fifth connection electrode 55 through the twenty-second via hole V22. The first end of the second connection sub-line 63-2 is connected to the second end of the first connection sub-line 63-1, and the second end of the second connection sub-line 63-2 extends along the second direction Y toward a direction close to the anode connection electrode 62 in the next cell row.

[0251] In an exemplary embodiment, the anode connection line 63 is configured to change the position of the anode via hole so that the anode connection electrode 62 is connected to the fifth connection electrode 55 through the anode connection line 63 and to improve the flatness of the anode.

[0252] In an exemplary embodiment, positions and shapes of the anode connection electrodes 62 and the anode connection lines 63 in the (N+2)th cell column and the (N+5)th cell column may be substantially the same.

[0253] In an exemplary embodiment, in at least one circuit unit of the (N+2)th unit column and the (N+5)th unit column, the anode connection electrode 62 and the anode connection line 63 may be an integral structure connected to each other.

[0254] In an exemplary embodiment, the fourth conductive layer of a portion of the circuit unit may further include a first power line 71. The first power line 71 may be in a straight line shape or a zigzag line shape extending along the second direction Y.

[0255] In an exemplary embodiment, the first power line 71 may be provided in the circuit cells of the Nth, N+1th, N+3th, and N+4th cell columns, and the circuit cells of the N+2th and N+5th cell columns are not provided with the first power line 71. The first power line 71 may be provided with a groove 71-1. The groove 71-1 may be in a block shape (e.g., a rectangular shape). The groove 71-1 may be provided on a side of the first power line 71 opposite to the first direction X. The groove 71-1 is configured to accommodate the anode connection electrode 62 in the cell column.

[0256] In the exemplary embodiment, the first power lines 71 of the circuit cells in the (N+1)th and (N+4)th cell columns are connected to the power connection block 44-1 via the twenty-third via V23. Since the power connection block 44-1 is connected to the power connection line 44, the power connection line 44, whose main portion extends along the first direction X, is interconnected with the first power line 71, whose main portion extends along the second direction Y. This allows the first power lines 71 and the power connection lines 44 to form a mesh-like interconnected structure on the display substrate for transmitting the first power signal. This not only effectively reduces the resistance of the first power lines 71 and the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal across the display substrate, effectively improving display uniformity and enhancing display quality.

[0257] In an exemplary embodiment, the positions of the first power lines 71 in adjacent cell columns may be mirror-symmetrical with respect to the column centerline A1. For example, the positions of the first power lines 71 in the Nth cell column and the first power lines 71 in the N+1th cell column may be mirror-symmetrical with respect to the column centerline A1. For another example, the positions of the first power lines 71 in the N+3th cell column and the first power lines 71 in the N+4th cell column may be mirror-symmetrical with respect to the column centerline A1.

[0258] In an exemplary embodiment, the first power lines 71 of the Nth and N+1th cell columns may be interconnected as an integral structure, such that the first power lines 71 in the Nth and N+1th cell columns form a one-piece, full-surface structure. The first power lines 71 of the N+3th and N+4th cell columns may be interconnected as an integral structure, such that the first power lines 71 in the N+3th and N+4th cell columns form a one-piece, full-surface structure.

[0259] In an exemplary embodiment, in the Nth, N+1th, N+3th, and N+4th cell columns, the orthographic projection of the first power line 71 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 51 on the substrate. Because the first connection electrode 51 serves as the first node N1 in the pixel driving circuit, the constant voltage first power line 71 can effectively shield the first node N1 from the effects of other signals in the pixel driving circuit, preventing other signals (such as data voltage jumps) from affecting the potential of the first node N1 of the pixel driving circuit, thereby improving the display effect.

[0260] In an exemplary embodiment, an orthographic projection of the first power line 71 on the substrate may include an orthographic projection of the first connection electrode 41 on the substrate.

[0261] In an exemplary embodiment, the fourth conductive layer of a portion of the circuit units may further include a second power line 72 . The second power line 72 may be in a straight line shape or a zigzag line shape extending along the second direction Y.

[0262] In an exemplary embodiment, the second power line 72 can be arranged in the N+2th unit column and the N+5th unit column. On the one hand, it can ensure the symmetry of the signal line under the anode and improve the flatness and symmetry of the anode. On the other hand, it can realize the VSS in pixel structure, which can greatly reduce the width of the power lead in the border area and the border width, which is conducive to achieving full-screen display.

[0263] In an exemplary embodiment, in the (N+2)th and (N+5)th unit columns, the orthographic projection of the second power line 72 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 51 on the substrate. Because the first connection electrode 51 serves as the first node N1 in the pixel driving circuit, the constant voltage second power line 72 can effectively shield the first node N1 from the effects of other signals in the pixel driving circuit, preventing other signals (such as data voltage jumps) from affecting the potential of the first node N1 of the pixel driving circuit, thereby improving the display effect.

[0264] In an exemplary embodiment, the fourth conductive layer of a portion of the circuit units may further include an initial connection line 73 . The initial connection line 73 may be in a straight line shape or a zigzag line shape extending along the second direction Y.

[0265] In an exemplary embodiment, the initial connection line 73 may be disposed in the N+2th unit column and the N+5th unit column, and may be disposed on one side of the second power line 72 in the first direction X. The initial connection line 73 may ensure symmetry of the signal line below the anode, improving the flatness and symmetry of the anode, and may form a meshed connection structure for transmitting the initial signal.

[0266] In one embodiment, in at least one unit column, the initial connection line can be connected to the first initial connection block on the first initial signal line through a via, so that the first initial signal line whose main part extends along the first direction X and the initial connection line whose main part extends along the second direction Y form a mesh-like interconnected structure on the display substrate for transmitting the first initial signal, which can not only effectively reduce the resistance of the first initial signal line and reduce the voltage drop of the first initial signal, but also effectively improve the uniformity of the first initial signal, effectively improve the display uniformity, and improve the display quality and display quality.

[0267] In another embodiment, in at least one unit column, the initial connection line can be connected to the second initial connection block on the second initial signal line through a via, so that the second initial signal line whose main part extends along the first direction X and the initial connection line whose main part extends along the second direction Y form a mesh-like interconnected structure for transmitting the second initial signal on the display substrate, which can not only effectively reduce the resistance of the second initial signal line and reduce the voltage drop of the second initial signal, but also effectively improve the uniformity of the second initial signal, effectively improve the display uniformity, and improve the display quality and display quality.

[0268] In another embodiment, in at least one unit column, the initial connection line can be connected to the third initial connection block on the third initial signal line through a via, so that the third initial signal line whose main part extends along the first direction X and the initial connection line whose main part extends along the second direction Y form a mesh-like interconnected structure for transmitting the third initial signal on the display substrate, which can not only effectively reduce the resistance of the third initial signal line and reduce the voltage drop of the third initial signal, but also effectively improve the uniformity of the third initial signal, effectively improve the display uniformity, and improve the display quality and display quality.

[0269] In one possible embodiment, the initial connection line 73 in a unit column (such as the N+2th unit column) can be connected to the first initial signal line 41, the initial connection line 73 in another unit column (such as the N+5th unit column) can be connected to the second initial signal line 42, and the initial connection line 73 in another unit column (such as the N+8th unit column) can be connected to the third initial signal line 43, forming a first meshed connection structure for transmitting the first initial signal, a second meshed connection structure for transmitting the second initial signal, and a third meshed connection structure for transmitting the third initial signal on the display substrate.

[0270] In an exemplary embodiment, in at least one unit column, the positions of the second power line 72 and the initial connection line 73 can be interchanged, and the second power line 72 can be set on one side of the initial connection line 73 in the first direction X, which is not limited in the present disclosure.

[0271] (19) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a second planar layer covering the fourth conductive layer, wherein the second planar layer is provided with a plurality of vias, as shown in FIG. 14 .

[0272] In an exemplary embodiment, the plurality of vias of each circuit unit includes at least an anode via V30. The orthographic projection of the anode via V30 on the substrate is within the range of the orthographic projection of the anode connection electrode 62 on the substrate. The second planar layer within the anode via V30 is removed, exposing the surface of the anode connection electrode 62. The anode connection electrode is configured such that a subsequently formed anode is connected to the anode connection electrode 62 through the via.

[0273] At this point, the driving structure layer is prepared on the substrate. In a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units, each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line, a first initial signal line, a second initial signal line, a third initial signal line, a data signal line and a first power line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving structure layer may include at least a shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first flat layer, a fourth conductive layer and a second flat layer arranged in sequence on the substrate. The blocking layer may include at least a blocking electrode, the semiconductor layer may include at least a first initial signal line, an active layer of the first transistor to the eighth transistor, the first conductive layer may include at least a second scanning signal line, a light-emitting signal line and a first plate of the storage capacitor, the second conductive layer may include at least a shielding electrode and a second plate of the storage capacitor, the third conductive layer may include at least a first scanning signal line, a third scanning signal line, a second initial signal line, a third initial signal and a plurality of connecting electrodes, and the fourth conductive layer may include at least a data signal line and a first power line.

[0274] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).

[0275] In an exemplary embodiment, the shielding layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer. The first planarizing layer and the second planarizing layer can be made of organic materials, such as resin.

[0276] In an exemplary embodiment, after the driving structure layer is prepared, a light emitting structure layer is prepared on the driving structure layer. The preparation process of the light emitting structure layer may include the following operations.

[0277] (20) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the second flat layer, wherein the anode conductive layer includes at least a plurality of anode patterns, as shown in FIG15A and FIG15B , where FIG15B is a plan view schematic diagram of the anode conductive layer in FIG15A .

[0278] In an exemplary embodiment, the plurality of anodes may include at least a first anode 90A located in the first light emitting cell, a second anode 90B located in the second light emitting cell, and a third anode 90C located in the third light emitting cell.

[0279] In an exemplary embodiment, the first light emitting unit may be a red light emitting unit emitting red light, the second light emitting unit may be a green light emitting unit emitting green light, and the third light emitting unit may be a blue light emitting unit emitting blue light.

[0280] In an exemplary embodiment, the second anode 90B may be disposed on one side of the first anode 90A in the second direction Y, and the third anode 90C may be disposed on one side of the first direction X between the first anode 90A and the second anode 90B.

[0281] In an exemplary embodiment, the first anode 90A, the second anode 90B, and the third anode 90C may be connected to the anode connection electrode 62 of the corresponding circuit unit through the anode via V30 , respectively.

[0282] In an exemplary embodiment, at least one of the first anode 90A, the second anode 90B, and the third anode 90C may include an anode body portion and an anode connecting portion connected to each other, the anode connecting portion being connected to the anode body portion on one hand and to the anode connecting electrode 62 through the anode via V30 on the other hand.

[0283] In an exemplary embodiment, the first anode 90A may include a first anode main body and a first anode connecting portion connected to each other, the shape of the first anode main body may be rectangular, the corners of the rectangle may be provided with arc-shaped chamfers, the shape of the first anode connecting portion may be a strip shape extending in a direction away from the first anode main body, and the end of the first anode connecting portion away from the first anode main body is connected to the anode connecting electrode 62 through the anode via V30.

[0284] In an exemplary embodiment, the orthographic projection of the first anode body portion of the first anode 90A on the substrate at least partially overlaps with the orthographic projection of the first power line 71 on the substrate, and the orthographic projection of the first anode body portion of the first anode 90A on the substrate does not overlap with the orthographic projections of the data signal line 61, the anode connection line 63, the second power line 72 and the initial connection line 73 on the substrate.

[0285] In an exemplary embodiment, an orthographic projection of the first anode body portion of the first anode 90A on the substrate may be located within a range of an orthographic projection of the first power line 71 on the substrate.

[0286] In an exemplary embodiment, the second anode 90B may include a second anode main body and a second anode connecting portion connected to each other, the shape of the second anode main body may be rectangular, the corners of the rectangle may be provided with arc-shaped chamfers, the shape of the second anode connecting portion may be a strip shape extending in a direction away from the second anode main body, and the end of the second anode connecting portion away from the second anode main body is connected to the anode connecting electrode 62 through the anode via V30.

[0287] In an exemplary embodiment, the orthographic projection of the second anode body portion of the second anode 90B on the substrate at least partially overlaps with the orthographic projection of the first power line 71 on the substrate, and the orthographic projection of the second anode body portion of the second anode 90B on the substrate does not overlap with the orthographic projections of the data signal line 61, the anode connection line 63, the second power line 72 and the initial connection line 73 on the substrate.

[0288] In an exemplary embodiment, an orthographic projection of the second anode body portion of the second anode 90B on the substrate may be located within a range of an orthographic projection of the first power line 71 on the substrate.

[0289] In an exemplary embodiment, the third anode 90C may include a third anode main body and a third anode connecting portion that are connected to each other. The shape of the third anode main body may be rectangular, and the corners of the rectangle may be provided with arc-shaped chamfers. The shape of the third anode connecting portion may be a strip shape extending in a direction away from the third anode main body. The end of the third anode connecting portion away from the third anode main body is connected to the anode connecting electrode 62 through the anode via V30.

[0290] In an exemplary embodiment, the orthographic projection of the third anode body portion of the third anode 90C on the substrate at least partially overlaps with the orthographic projections of the data signal line 61, the anode connection line 63, the second power line 72 and the initial connection line 73 on the substrate, and the orthographic projection of the third anode body portion of the third anode 90C on the substrate does not overlap with the orthographic projection of the first power line 71 on the substrate.

[0291] In an exemplary embodiment, the orthographic projections of the first, second, and third anode body portions on the substrate do not overlap with the orthographic projections of the power via on the substrate and do not overlap with the orthographic projections of the anode via on the substrate.

[0292] In an exemplary embodiment, the anode conductive layer may have a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0293] In an exemplary embodiment, in the second direction Y, the first anode 90A, the second anode 90B, and the third anode 90C may be disposed at a region close to a next cell row of a corresponding circuit cell.

[0294] In an exemplary embodiment, the orthographic projection of the first anode 90A on the substrate at least partially overlaps with the orthographic projection of the power connection line 44 on the substrate, and does not overlap with the orthographic projection of the first initial signal line 41 on the substrate.

[0295] In an exemplary embodiment, the orthographic projection of the second anode 90B on the substrate at least partially overlaps with the orthographic projections of the first initial signal line 41, the second initial signal line 42, and the second initial signal line 43 on the substrate, and the orthographic projection of the second anode 90B on the substrate does not overlap with the orthographic projections of the first scanning signal line 31 and the power connection line 44 on the substrate.

[0296] In an exemplary embodiment, the orthographic projection of the third anode 90C on the substrate at least partially overlaps with the orthographic projections of the power connection line 44, the light emitting signal line 34, the second scanning signal line 32 and the second initial signal line 42 on the substrate, and the orthographic projection of the third anode 90C on the substrate does not overlap with the orthographic projection of the first scanning signal line 31 on the substrate.

[0297] (21) Forming a pixel definition layer pattern. In an exemplary embodiment, forming the pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition film using a patterning process to form a pixel definition layer pattern covering the anode conductive layer pattern, wherein a plurality of pixel openings are provided on the pixel definition layer, as shown in FIG16 .

[0298] In an exemplary embodiment, the plurality of pixel openings may include a first pixel opening 100A located in a red light-emitting cell, a second pixel opening 100B located in a green light-emitting cell, and a third pixel opening 100B located in a blue light-emitting cell. The orthographic projection of the first pixel opening 100A on the substrate is within the orthographic projection of the first anode 90A on the substrate. The pixel definition film within the first pixel opening 100A is removed, exposing the surface of the first anode 90A. The orthographic projection of the second pixel opening 100B on the substrate is within the orthographic projection of the second anode 90B on the substrate. The pixel definition film within the second pixel opening 100B is removed, exposing the surface of the second anode 90B. The orthographic projection of the third pixel opening 100C on the substrate is within the orthographic projection of the third anode 90C on the substrate. The pixel definition film within the third pixel opening 100C is removed, exposing the surface of the third anode 90C.

[0299] In an exemplary embodiment, the shape of the first pixel opening 100A can be rectangular, and the corners of the rectangle can be provided with arc-shaped chamfers, the orthographic projection of the first pixel opening 100A on the substrate at least partially overlaps with the orthographic projection of the first power line 71 on the substrate, and the orthographic projection of the first pixel opening 100A on the substrate does not overlap with the orthographic projections of the data signal line 61, the anode connection line 63, the second power line 72 and the initial connection line 73 on the substrate.

[0300] In an exemplary embodiment, the orthographic projection of the first pixel opening 100A on the substrate does not overlap with the orthographic projection of the power via on the substrate, that is, there is no power via within the range of the first pixel opening 100A.

[0301] In an exemplary embodiment, an orthographic projection of the first pixel opening 100A on the substrate may be located within a range of an orthographic projection of the first power line 71 on the substrate.

[0302] In an exemplary embodiment, the orthographic projection of the first pixel opening 100A on the substrate does not overlap with the orthographic projections of the data via and the anode via on the substrate, ie, there are no data vias and anode vias within the range of the first pixel opening 100A.

[0303] In an exemplary embodiment, the orthographic projection of the second pixel opening 100B on the substrate at least partially overlaps with the orthographic projection of the first power line 71 on the substrate, and the orthographic projection of the second pixel opening 100B on the substrate does not overlap with the orthographic projections of the data signal line 61, the anode connection line 63, the second power line 72 and the initial connection line 73 on the substrate.

[0304] In an exemplary embodiment, the orthographic projection of the second pixel opening 100B on the substrate does not overlap with the orthographic projection of the power via on the substrate, that is, there is no power via within the range of the second pixel opening 100B.

[0305] In an exemplary embodiment, an orthographic projection of the second pixel opening 100B on the substrate may be located within a range of an orthographic projection of the first power line 71 on the substrate.

[0306] In an exemplary embodiment, the orthographic projection of the second pixel opening 100B on the substrate does not overlap with the orthographic projections of the data via and the anode via on the substrate, ie, there is no data via and anode via within the range of the third pixel opening.

[0307] In an exemplary embodiment, the orthographic projection of the third pixel opening 100C on the substrate at least partially overlaps with the orthographic projections of the data signal line 61, the anode connection line 63, the second power line 72 and the initial connection line 73 on the substrate, and the orthographic projection of the third pixel opening 100C on the substrate does not overlap with the orthographic projection of the first power line 71 on the substrate.

[0308] In an exemplary embodiment, the orthographic projection of the third pixel opening 100C on the substrate does not overlap with the orthographic projection of the power via on the substrate, that is, there is no power via within the range of the third pixel opening 100C.

[0309] In an exemplary embodiment, the orthographic projection of the third pixel opening 100C on the substrate does not overlap with the orthographic projections of the data via and the anode via on the substrate, ie, there is no data via and anode via within the range of the third pixel opening 100C.

[0310] In an exemplary embodiment, the first pixel opening 100A and the second pixel opening 100B overlap with the first power line, but do not overlap with the second power line 72 and the initial connection line 73, and the third pixel opening 100C overlaps with the second power line 72 and the initial connection line 73, but does not overlap with the first power line, thereby effectively ensuring the flatness and symmetry of the anode within the pixel opening.

[0311] Figure 17 is a schematic diagram illustrating the positional relationship between the third pixel opening and the signal line in an embodiment of the present disclosure. As shown in Figure 17 , in an exemplary embodiment, the third pixel opening 100C may have an opening centerline B1. Opening centerline B1 may be a straight line extending along the second direction Y and passing through the geometric center of the third pixel opening. Opening centerline B1 is an imaginary line.

[0312] In an exemplary embodiment, in at least one third pixel opening 100C, in the first direction X, a first distance L1 is provided between the anode connection line 63 at least partially overlapping with the third pixel opening 100C and the opening center line B1, and a second distance L2 is provided between the data signal line 61 at least partially overlapping with the third pixel opening 100C and the opening center line B1, and a ratio of the first distance L1 to the second distance L2 may be approximately 0.8 to 1.2.

[0313] In an exemplary embodiment, a ratio of the first distance L1 to the second distance L2 may be approximately 0.9 to 1.1.

[0314] In an exemplary embodiment, the first distance L1 and the second distance L2 may be substantially the same, that is, the anode connection line 63 and the data signal line 61 may be substantially mirror-symmetrical with respect to the opening center line B1 .

[0315] In an exemplary embodiment, the first distance L1 and the second distance L2 are both dimensions in the first direction X. The first distance L1 may be the distance between the edge of the anode connection line 63 on the side closer to the opening center line B1 and the opening center line B1, or the first distance L1 may be the distance between the edge of the anode connection line 63 on the side farther from the opening center line B1 and the opening center line B1. The second distance L2 may be the distance between the edge of the data signal line 61 on the side closer to the opening center line B1 and the opening center line B1, or the second distance L2 may be the distance between the edge of the data signal line 61 on the side farther from the opening center line B1 and the opening center line B1.

[0316] In an exemplary embodiment, in at least one third pixel opening 100C, in the first direction X, a third distance L3 is provided between the second power line 72 at least partially overlapping with the third pixel opening 100C and the opening center line B1, and a fourth distance L4 is provided between the initial connection line 73 at least partially overlapping with the third pixel opening 100C and the opening center line B1, and a ratio of the third distance L3 to the fourth distance L4 may be approximately 0.8 to 1.2.

[0317] In an exemplary embodiment, a ratio of the third distance L3 to the fourth distance L4 may be approximately 0.9 to 1.1.

[0318] In an exemplary embodiment, the third distance L3 and the fourth distance L4 may be substantially the same, that is, the second power line 72 and the initial connection line 73 may be substantially mirror-symmetrical with respect to the opening center line B1.

[0319] In an exemplary embodiment, the third distance L3 and the fourth distance L4 are both dimensions in the first direction X. The third distance L3 may be the distance between the edge of the second power line 72 on the side closest to the opening centerline B1 and the opening centerline B1, or the third distance L3 may be the distance between the edge of the second power line 72 on the side away from the opening centerline B1 and the opening centerline B1. The fourth distance L4 may be the distance between the edge of the initial connection line 73 on the side closest to the opening centerline B1 and the opening centerline B1, or the fourth distance L4 may be the distance between the edge of the initial connection line 73 on the side away from the opening centerline B1 and the opening centerline B1.

[0320] In an exemplary embodiment, in the second direction Y, the anode connection line 63 at least partially overlapping the third pixel opening 100C has a first extension length, the second power supply line 72 at least partially overlapping the third pixel opening 100C has a second extension length, the initial connection line 73 at least partially overlapping the third pixel opening 100C has a third extension length, and the data signal line 61 at least partially overlapping the third pixel opening 100C has a fourth extension length, and the first extension length, the second extension length, the third extension length and the fourth extension length may be substantially the same.

[0321] The present disclosure sets a range where there are no power vias, data vias and anode vias within the pixel opening, and the orthographic projections of the first pixel opening and the third pixel opening on the substrate are located within the range of the orthographic projection of the first power line 71 on the substrate, that is, the first pixel opening and the second pixel opening are below the entire second source and drain metal layer, and the third pixel opening is set to overlap with the data signal line, the anode connection line, the second power line and the initial connection line, and the data signal line and the anode connection line are symmetrical relative to the third pixel opening, and the second power line 72 and the initial connection line 73 are symmetrical relative to the third pixel opening, so that the first anode, the second anode and the third anode not only have good flatness, which can effectively avoid defects such as off-screen watermarks (Mura) caused by poor anode flatness, but also have good symmetry, which can effectively improve color deviation and improve display quality.

[0322] In an exemplary embodiment, in the second direction Y, the first pixel opening 100A, the second pixel opening 100B, and the third pixel opening 100C may be disposed at a region of the corresponding circuit unit close to a next unit row.

[0323] In an exemplary embodiment, the orthographic projection of at least one first pixel opening 100A on the substrate at least partially overlaps with the orthographic projection of the power connection line 44 on the substrate, and the orthographic projection of at least one first pixel opening 100A on the substrate does not overlap with the orthographic projection of the first initial signal line 41 on the substrate.

[0324] In an exemplary embodiment, the orthographic projection of at least one first pixel opening 100A on the substrate also does not overlap with the orthographic projections of the first scan signal line 31, the second scan signal line 32, the third scan signal line 33, the light emitting signal line 34, the second initial signal line 42 and the third initial signal line 43 on the substrate.

[0325] In an exemplary embodiment, the orthographic projection of at least one second pixel opening 100B on the substrate at least partially overlaps with the orthographic projections of the first initial signal line 41, the second initial signal line 42, and the second initial signal line 43 on the substrate, and the orthographic projection of at least one second pixel opening 100B on the substrate does not overlap with the orthographic projections of the first scanning signal line 31 and the power connection line 44 on the substrate.

[0326] In an exemplary embodiment, the orthographic projection of at least one second pixel opening 100B on the substrate also at least partially overlaps with the orthographic projection of the third scan signal line 33 on the substrate, and the orthographic projection of at least one second pixel opening 100B on the substrate also does not overlap with the orthographic projections of the second scan signal line 32 and the light-emitting signal line 34 on the substrate.

[0327] In an exemplary embodiment, the orthographic projection of at least one third pixel opening 100C on the substrate at least partially overlaps with the orthographic projection of the second scanning signal line 32, the light emitting signal line 34, the second initial signal line 42 and the power connection line 44 on the substrate, and the orthographic projection of at least one third pixel opening 100C on the substrate does not overlap with the orthographic projection of the first scanning signal line 31 on the substrate.

[0328] In an exemplary embodiment, an orthographic projection of the at least one third pixel opening 100C on the substrate also at least partially overlaps with orthographic projections of the third scan signal line 33 , the first preliminary signal line 41 , and the third preliminary signal line 43 on the substrate.

[0329] In an exemplary embodiment, the subsequent preparation process may include: first forming an organic light-emitting layer by an evaporation or inkjet printing process, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer. The encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0330] The display substrate provided by the exemplary embodiment of the present disclosure adjusts the arrangement of the data signal line and the first power line so that there are no data vias and power vias within the range of the pixel opening. The anode exposed by the pixel opening has good flatness, which can effectively avoid defects such as off-screen watermarks (Mura) caused by poor anode flatness, effectively improve color deviation, and enhance display quality.

[0331] The exemplary embodiment of the present disclosure sets the orthographic projections of the first pixel opening and the second pixel opening on the substrate to be within the range of the orthographic projection of the first power line 71 on the substrate, that is, the entire second source-drain metal layer is below the first pixel opening and the second pixel opening, and sets the third pixel opening to overlap with the data signal line, the anode connection line, the second power line and the initial connection line, and the data signal line and the anode connection line are symmetrical relative to the third pixel opening, and the second power line 72 and the initial connection line 73 are symmetrical relative to the third pixel opening, so that the anode exposed by the pixel opening has good symmetry, which can effectively improve color deviation and enhance display quality.

[0332] The present disclosure provides a second power line in the second source-drain metal layer, which can, on the one hand, ensure the symmetry of the signal line below the anode and improve the flatness and symmetry of the anode; on the other hand, it can realize the VSS in pixel structure, which can greatly reduce the width of the power lead in the frame area, shorten the frame width, and facilitate the realization of full-screen display.

[0333] The present disclosure sets an initial connection line in the second source-drain metal layer, which can, on the one hand, ensure the symmetry of the signal line below the anode and improve the flatness and symmetry of the anode; on the other hand, it can enable the initial signal line and the initial connection line to form a mesh-like interconnected structure for transmitting the initial signal on the display substrate, which can not only effectively reduce the resistance of the initial signal line and reduce the voltage drop of the initial signal, but also effectively improve the uniformity of the initial signal, effectively improve the display uniformity, and improve the display quality and display quality.

[0334] The present disclosure provides a power connection line extending along a first direction and a first power line extending along a second direction, and the first power line is connected to the power connection line, so that the first power line and the power connection line form a mesh-like interconnected structure for transmitting a first power signal on a display substrate. This can not only effectively reduce the resistance of the first power signal line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal, effectively improve the display uniformity, and improve the display quality and display quality.

[0335] The embodiment of the present disclosure sets a first initial signal line in the semiconductor layer, which not only improves the reliable connection between the first initial signal line and the first electrode of the first transistor, but also reduces the number of vias and the space occupied by the pixel driving circuit, which is conducive to achieving high-resolution (PPI) display.

[0336] The embodiment of the present disclosure can shield the influence of data voltage jump on the first transistor T1 and the second transistor T2 by providing a shielding electrode, thereby preventing the data voltage jump from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0337] In the embodiment of the present disclosure, the first power line is provided to shield the first node N1 of the pixel driving circuit, thereby effectively preventing other signals from affecting the potential of the first node N1 of the pixel driving circuit and improving the display effect.

[0338] The preparation process disclosed in the present invention is well compatible with existing preparation processes, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0339] Figure 18 is a schematic diagram of the planar structure of another display substrate of an exemplary embodiment of the present disclosure. In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include a drive structure layer disposed on a base and a light-emitting structure layer disposed on a side of the drive structure layer away from the base. On a plane parallel to the display substrate, the drive structure layer includes a plurality of circuit units, and the light-emitting structure layer includes a plurality of light-emitting units. Figure 5 illustrates a structure in which the drive structure layer includes three circuit units and the light-emitting structure layer includes three light-emitting units. The structure of three circuit units (a first circuit unit Q1, a second circuit unit Q2, and a third circuit unit Q3) is illustrated.

[0340] In an exemplary embodiment, the structure of the pixel driving circuit in each circuit unit of this embodiment is substantially the same as the structure shown in FIG5 , the structures of the first scanning signal line 31, the second scanning signal line 32, the third scanning signal line 33, the light-emitting signal line 34, the first initial signal line 41, the second initial signal line 42 and the third initial signal line 43 are substantially the same as the structure shown in FIG5 , and the structures of the anode and the pixel opening in each light-emitting unit are substantially the same as the structure shown in FIG5 . The difference from the structure shown in FIG5 is the structure of the data signal line 61 and the first power line 71.

[0341] In an exemplary embodiment, the first power line 71 of this embodiment is provided in each circuit unit, that is, the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 are each provided with a first power line 71. At least one pixel driving circuit may further include a power connection electrode, and at least one circuit unit may further include a power connection line 44, the power connection electrode being connected to the power connection line 44. The first power line 71 may be connected to the power connection electrode in the circuit unit in which it is located through a power via K1, thereby achieving a connection between the first power line 71 and the power connection line 44.

[0342] In an exemplary embodiment, at least one circuit unit may further include an anode connection line 63 and an initial connection line 73. The structures of the anode connection line 63 and the initial connection line 73 are substantially the same as those shown in FIG5. In some possible embodiments, at least one circuit unit may further include a second power line, which is not limited in this disclosure.

[0343] In an exemplary embodiment, the positions of the data signal lines 61 in the first circuit unit Q1, the second circuit unit Q2 and the third circuit unit Q3 can be substantially the same, and the data signal lines 61 can all be arranged on one side of the first power line 71 in the first direction X, and the data signal lines 61 are connected to the data connection electrodes in the circuit units through the data vias K2.

[0344] In an exemplary embodiment, since the relative positions of the data signal line 61 and the first power line 71 in each circuit unit are substantially the same, this embodiment employs a compressed arrangement of the pixel driver circuits to avoid positioning the data via within the pixel opening, ensure anode flatness, and improve color shift. In some exemplary embodiments, compression can be achieved by adjusting the position of the pixel driver circuit in the first direction X, by adjusting the size of the pixel driver circuit in the first direction X, or by adjusting the structural layout of the pixel driver circuit.

[0345] In an exemplary embodiment, the present embodiment adjusts the spacing between adjacent pixel driving circuits in the first direction X by setting the positions of the pixel driving circuits in the first direction X, thereby adjusting the relative positions of the data vias and the pixel openings to prevent the data vias from being located within the pixel openings. For example, the pixel driving circuits in the second circuit unit Q2 can be positioned close to the pixel driving circuits in the first circuit unit Q1 and away from the pixel driving circuits in the third circuit unit Q3, so that the data vias in the second circuit unit Q2 and the third circuit unit Q3 avoid the third pixel opening 100C of the third light-emitting unit.

[0346] In an exemplary embodiment, the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be sequentially arranged along the first direction X. The first circuit unit Q1 may include at least a first pixel driving circuit and a first data signal line 61-1 connected to the first pixel driving circuit via a first data via K2-1. The second circuit unit Q2 may include at least a second pixel driving circuit and a second data signal line 61-2 connected to the second pixel driving circuit via a second data via K2-2. The third circuit unit Q3 may include at least a third pixel driving circuit and a third data signal line 61-3 connected to the third pixel driving circuit via a third data via K2-3. In an exemplary embodiment, the data signal line is connected to the pixel driving circuit via a data via, which means that the data signal line is connected to a data connection electrode in the pixel driving circuit via the data via, and the data connection electrode is connected to the first region of the fourth active layer via a via.

[0347] In an exemplary embodiment, the first data signal line 61-1 and the second data signal line 61-2 may have a first interval W1 therebetween, and the second data signal line 61-2 and the third data signal line 61-3 may have a second interval W2 therebetween, and the first interval W1 is smaller than the second interval W2.

[0348] In an exemplary embodiment, the first distance W1 may be the distance between an edge of the first data signal line 61-1 on a side close to the second data signal line 61-2 and an edge of the second data signal line 61-2 on a side close to the first data signal line 61-1, or the distance between an edge of the first data signal line 61-1 on a side away from the second data signal line 61-2 and an edge of the second data signal line 61-2 on a side away from the first data signal line 61-1. The second distance W2 may be the distance between an edge of the second data signal line 61-2 on a side close to the third data signal line 61-3 and an edge of the third data signal line 61-3 on a side close to the second data signal line 61-2, or the distance between an edge of the second data signal line 61-2 on a side away from the third data signal line 61-3 and an edge of the third data signal line 61-3 on a side away from the second data signal line 61-2.

[0349] In an exemplary embodiment, the first data via K2-1 and the second data via K2-2 may have a third interval W3 therebetween, and the second data via K2-2 and the third data via K2-3 may have a fourth interval W4 therebetween, and the third interval W3 is smaller than the fourth interval W4.

[0350] In an exemplary embodiment, the third distance W3 may be the distance between an edge of the first data via K2-1 on a side close to the second data via K2-2 and an edge of the second data via K2-2 on a side close to the first data via K2-1, or the distance between an edge of the first data via K2-1 on a side away from the second data via K2-2 and an edge of the second data via K2-2 on a side away from the first data via K2-1. The fourth distance W4 may be the distance between an edge of the second data via K2-2 on a side close to the third data via K2-3 and an edge of the third data via K2-3 on a side close to the second data via K2-2, or the distance between an edge of the second data via K2-2 on a side away from the third data via K2-3 and an edge of the third data via K2-3 on a side away from the second data via K2-2.

[0351] In an exemplary embodiment, the orthographic projection of any one or more of the first pixel opening 100A, the second pixel opening 100B, and the third pixel opening 100C on the substrate does not overlap with the orthographic projection of the data vias (including the first data via K2-1, the second data via K2-2, and the third data via K2-3) on the substrate.

[0352] In an exemplary embodiment, in the second direction Y, the first data via hole K2 - 1 may be located between the first pixel opening 100A and the second pixel opening 100B.

[0353] In an exemplary embodiment, a groove may be provided on a side of the second anode 90B close to the first anode 90A, and the groove is configured to avoid the first data via K2 - 1 .

[0354] In an exemplary embodiment, the orthographic projections of the first pixel opening 100A and the second pixel opening 100B on the substrate at least partially overlap with the orthographic projection of the first data signal line 61-1 on the substrate, and the orthographic projections of the first pixel opening 100A and the second pixel opening 100B on the substrate do not overlap with the orthographic projections of the second data signal line 61-2 and the third data signal line 61-3 on the substrate.

[0355] In an exemplary embodiment, in the first direction X, the second data via hole K2 - 2 and the third data via hole K2 - 3 may be located at both sides of the third pixel opening 100C.

[0356] In an exemplary embodiment, an orthographic projection of the third pixel opening 100C on the substrate does not overlap with orthographic projections of the first data signal line 61 - 1 , the second data signal line 61 - 2 , and the third data signal line 61 - 3 on the substrate.

[0357] In an exemplary embodiment, orthographic projections of any one or more of the first pixel opening 100A, the second pixel opening 100B, and the third pixel opening 100C on the substrate do not overlap with orthographic projections of the power via K1 and the anode via K3 on the substrate.

[0358] In this exemplary embodiment, unlike the structure of the previous embodiment in which the first power line 71 is connected to the power connection line 44 via the power via K1, the first power line 71 of this embodiment is connected to the power connection electrode via the power via K1. Because the power connection electrode is located to one side of the power connection line 44 in the second direction Y, the position of the power via K1 is lowered so that the pixel opening and the power via do not overlap. This embodiment adjusts the relative position of the power via and the pixel opening by adjusting the position of the power via, avoiding the power via being located within the pixel opening, ensuring the flatness of the anode, and improving color shift.

[0359] In an exemplary embodiment, the power via K1 may be located at one side of the second pixel opening 100B in the second direction Y, or the power via K1 may be located at one side of the third pixel opening 100C in the second direction Y.

[0360] In an exemplary embodiment, unlike the structure of the aforementioned embodiment in which the anode and pixel opening are arranged at a lower position of the circuit unit, the anode and pixel opening of this embodiment are arranged at an upper position of the circuit unit. By adjusting the positions of the anode and pixel opening, the relative positions of the data via and the power via and the pixel opening are adjusted, thereby avoiding the power via being located within the pixel opening, ensuring the flatness of the anode, and improving color deviation.

[0361] In an exemplary embodiment, in the second direction Y, the first pixel opening 100A, the second pixel opening 100B, and the third pixel opening 100C may be disposed in a region of the corresponding circuit unit close to a previous unit row.

[0362] In an exemplary embodiment, the orthographic projection of at least one first pixel opening 100A on the substrate at least partially overlaps with the orthographic projection of the first initial signal line 41 on the substrate, and the orthographic projection of the first pixel opening 100A on the substrate does not overlap with the orthographic projection of the power connection line 44 on the substrate.

[0363] In an exemplary embodiment, the orthographic projection of at least one second pixel opening 100B on the substrate at least partially overlaps with the orthographic projections of the first scan signal line 31 and the power connection line 44 on the substrate, and the orthographic projection of the second pixel opening 100B on the substrate does not overlap with the orthographic projections of the first initial signal line 41, the second initial signal line 42, and the second initial signal line 43 on the substrate.

[0364] In an exemplary embodiment, the orthographic projection of at least one third pixel opening 100C on the substrate at least partially overlaps with the orthographic projections of the first scanning signal line 31 and the third scanning signal line 33 on the substrate, and the orthographic projection of the third pixel opening 100C on the substrate does not overlap with the orthographic projections of the second scanning signal line 32, the light emitting signal line 34, the power connection line 44 and the second initial signal line 42 on the substrate.

[0365] In an exemplary embodiment, taking three circuit units as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0366] (31) Forming a blocking layer pattern. In an exemplary embodiment, forming a blocking layer pattern may include: depositing a blocking film on a substrate, patterning the blocking film through a patterning process, and forming a blocking layer pattern on the substrate, as shown in FIG. 19 .

[0367] In an exemplary embodiment, the shielding layer pattern of each circuit unit may include at least a shielding electrode 90, a first shielding connection bar 91, a second shielding connection bar 92, a third shielding connection bar 93, a first shielding block 94 and a second shielding block 95, and the above structure is basically the same as the previous embodiment.

[0368] In an exemplary embodiment, the shielding layer pattern in the second circuit unit Q2 is close to the shielding layer pattern in the first circuit unit Q1, but away from the shielding layer pattern in the third circuit unit Q3. That is, the distance between the shielding layer pattern in the first circuit unit Q1 and the shielding layer pattern in the second circuit unit Q2 is smaller than the distance between the shielding layer pattern in the second circuit unit Q2 and the shielding layer pattern in the third circuit unit Q3. For example, the shielding electrode 90 in the first circuit unit Q1 and the shielding electrode 90 in the second circuit unit Q2 have an eleventh distance W11, and the shielding electrode 90 in the second circuit unit Q2 and the shielding electrode 90 in the third circuit unit Q3 have a twelfth distance W12, and the eleventh distance W11 is smaller than the twelfth distance W12.

[0369] (32) Forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a first insulating layer covering the shielding layer, and a semiconductor layer pattern disposed on the first insulating layer, as shown in FIG20A and FIG20B , where FIG20B is a plan view schematic diagram of the semiconductor layer in FIG20A .

[0370] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit may include at least first to eighth active layers 11 to 18 and a first preliminary signal line 41 , and the above structure is substantially the same as that of the previous embodiment.

[0371] In an exemplary embodiment, a first initial connection block 41-1 may be provided on the first initial signal line, and the first initial connection block 41-1 is configured to be connected to the subsequently formed initial connection line, so that the first initial signal line extending along the first direction and the initial connection line extending along the second direction form a meshed connection structure for transmitting the first initial signal.

[0372] In an exemplary embodiment, the semiconductor layer pattern in the second circuit unit Q2 is close to the semiconductor layer pattern in the first circuit unit Q1 and away from the semiconductor layer pattern in the third circuit unit Q3. That is, the distance between the semiconductor layer pattern in the first circuit unit Q1 and the semiconductor layer pattern in the second circuit unit Q2 is smaller than the distance between the semiconductor layer pattern in the second circuit unit Q2 and the semiconductor layer pattern in the third circuit unit Q3. For example, a twenty-first distance W21 is defined between the first active layer 11 in the first circuit unit Q1 and the first active layer 11 in the second circuit unit Q2, and a twenty-second distance W22 is defined between the first active layer 11 in the second circuit unit Q2 and the first active layer 11 in the third circuit unit Q3. The twenty-first distance W21 is smaller than the twenty-second distance W22.

[0373] (33) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG. 21A and FIG. 21B , where FIG. 21B is a plan view schematic diagram of the first conductive layer in FIG. 21A .

[0374] In an exemplary embodiment, the first conductive layer pattern of each circuit unit includes at least: a first gate electrode 21, a second gate electrode 22, a fourth gate electrode 24, a second scanning signal line 32, a light-emitting signal line 34 and a first plate 81 of a storage capacitor, and the above structure is basically the same as the aforementioned embodiment.

[0375] In an exemplary embodiment, the first conductive layer pattern in the second circuit unit Q2 is close to the first conductive layer pattern in the first circuit unit Q1, but away from the first conductive layer pattern in the third circuit unit Q3. That is, the distance between the first conductive layer pattern in the first circuit unit Q1 and the first conductive layer pattern in the second circuit unit Q2 is smaller than the distance between the first conductive layer pattern in the second circuit unit Q2 and the first conductive layer pattern in the third circuit unit Q3. For example, the first electrode 81 in the first circuit unit Q1 and the first electrode 81 in the second circuit unit Q2 have a thirty-first distance W31, and the first electrode 81 in the second circuit unit Q2 and the first electrode 81 in the third circuit unit Q3 have a thirty-second distance W32, and the thirty-first distance W31 is smaller than the thirty-second distance W32.

[0376] (34) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG22A and FIG22B , where FIG22B is a plan view schematic diagram of the second conductive layer in FIG22A .

[0377] In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least: a second plate 82 of the storage capacitor and a shielding electrode 35 , and the above structure is substantially the same as that of the previous embodiment.

[0378] In an exemplary embodiment, the second conductive layer pattern in the second circuit unit Q2 is close to the second conductive layer pattern in the first circuit unit Q1, but away from the second conductive layer pattern in the third circuit unit Q3. That is, the distance between the second conductive layer pattern in the first circuit unit Q1 and the second conductive layer pattern in the second circuit unit Q2 is smaller than the distance between the second conductive layer pattern in the second circuit unit Q2 and the second conductive layer pattern in the third circuit unit Q3. For example, the second electrode plate 82 in the first circuit unit Q1 and the second electrode plate 82 in the second circuit unit Q2 have a forty-first distance W41, and the second electrode plate 82 in the second circuit unit Q2 and the second electrode plate 82 in the third circuit unit Q3 have a forty-second distance W42, and the forty-first distance W41 is smaller than the forty-second distance W42.

[0379] (35) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein the fourth insulating layer is provided with a plurality of via holes, as shown in FIG. 23 .

[0380] In an exemplary embodiment, the plurality of via holes of each circuit unit includes at least first to fourteenth via holes V1 to V14 , and the structures of the first to thirteenth via holes V1 to V13 are substantially the same as those of the previous embodiment.

[0381] In an exemplary embodiment, the fourth insulating layer of at least one circuit unit may further include a fourteenth via V14. The orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the first preliminary connection block 41-1 on the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fourteenth via V14 are etched away, exposing the surface of the first preliminary connection block 41-1. The fourteenth via V14 is configured to connect a subsequently formed sixth connection electrode to the first preliminary connection block 41-1 through the via.

[0382] (36) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the fourth insulating layer, as shown in FIG. 24A and FIG. 24B , where FIG. 24B is a plan view schematically illustrating the third conductive layer in FIG. 24A .

[0383] In an exemplary embodiment, the third conductive layer of each circuit unit includes at least: a first scanning signal line 31, a third scanning signal line 33, a second initial signal line 42, a third initial signal line 43, a power connection line 44, an auxiliary scanning signal line 45, a first connecting electrode 51, a second connecting electrode 52, a third connecting electrode 53, a fourth connecting electrode 54 and a fifth connecting electrode 55, and the above structure is basically the same as the aforementioned embodiment.

[0384] In an exemplary embodiment, the third conductive layer of at least one circuit unit may further include a sixth connection electrode 56. The sixth connection electrode 56 may be in a block shape (e.g., a rectangular shape) and connected to the first preliminary connection block 41-1 through the fourteenth via hole V14. In an exemplary embodiment, the sixth connection electrode 56 is configured to connect a subsequently formed preliminary connection line.

[0385] In an exemplary embodiment, the third conductive layer pattern in the second circuit unit Q2 is close to the third conductive layer pattern in the first circuit unit Q1, but away from the third conductive layer pattern in the third circuit unit Q3. That is, the distance between the third conductive layer pattern in the first circuit unit Q1 and the third conductive layer pattern in the second circuit unit Q2 is smaller than the distance between the third conductive layer pattern in the second circuit unit Q2 and the third conductive layer pattern in the third circuit unit Q3. For example, the third connecting electrode 53 in the first circuit unit Q1 and the third connecting electrode 53 in the second circuit unit Q2 have a fifty-first distance W51, and the third connecting electrode 53 in the second circuit unit Q2 and the third connecting electrode 53 in the third circuit unit Q3 have a fifty-second distance W52, and the fifty-first distance W51 is smaller than the fifty-second distance W52.

[0386] (37) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the third conductive layer, wherein a plurality of vias are provided on the first planar layer, as shown in FIG. 25 .

[0387] In an exemplary embodiment, the plurality of via holes of each circuit unit includes at least a twenty-first via hole V21 , a twenty-second via hole V22 , and a twenty-third via hole V23 . The structures of the twenty-first via hole V21 and the twenty-second via hole V22 are substantially the same as those in the previous embodiment.

[0388] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is within the range of the orthographic projection of the fourth connection electrode 54 on the substrate. The first planar layer within the twenty-third via hole V23 is removed, exposing the surface of the fourth connection electrode 54. The twenty-third via hole V23 is configured to connect a subsequently formed first power line to the fourth connection electrode 54 through the via hole. In an exemplary embodiment, the twenty-third via hole V23 can be referred to as a power via hole.

[0389] In an exemplary embodiment, the twenty-first via hole V21 may serve as a data via hole. Since the pixel driving circuit in the second circuit unit Q2 is close to the pixel driving circuit in the first circuit unit Q1 and away from the pixel driving circuit in the third circuit unit Q3, the twenty-first via hole V21 in the second circuit unit Q2 is close to the twenty-first via hole V21 in the first circuit unit Q1 and away from the twenty-first via hole V21 in the third circuit unit Q3.

[0390] In an exemplary embodiment, a third spacing W3 is provided between the twenty-first via hole V21 (first data via hole) in the first circuit unit Q1 and the twenty-first via hole V21 (second data via hole) in the second circuit unit Q2, and a fourth spacing W4 is provided between the twenty-first via hole V21 (second data via hole) in the second circuit unit Q2 and the twenty-first via hole V21 (third data via hole) in the third circuit unit Q3. The third spacing W3 is smaller than the fourth spacing W4, so that the twenty-first via holes V21 in the second circuit unit Q2 and the third circuit unit Q3 can avoid the pixel openings formed subsequently, thereby ensuring the flatness of the anode and improving color deviation.

[0391] In an exemplary embodiment, the third distance W3 may be: the distance between an edge of the twenty-first via V21 in the first circuit unit Q1 on a side close to the twenty-first via V21 in the second circuit unit Q2 and an edge of the twenty-first via V21 in the second circuit unit Q2 on a side close to the twenty-first via V21 in the first circuit unit Q1, or, may be the distance between an edge of the twenty-first via V21 in the first circuit unit Q1 on a side away from the twenty-first via V21 in the second circuit unit Q2 and an edge of the twenty-first via V21 in the second circuit unit Q2 on a side away from the twenty-first via V21 in the first circuit unit Q1. The fourth distance W4 can be: the distance between the edge of the twenty-first via V21 in the second circuit unit Q2 close to the twenty-first via V21 in the third circuit unit Q3 and the edge of the twenty-first via V21 in the third circuit unit Q3 close to the twenty-first via V21 in the second circuit unit Q2, or the distance between the edge of the twenty-first via V21 in the second circuit unit Q2 away from the twenty-first via V21 in the third circuit unit Q3 and the edge of the twenty-first via V21 in the third circuit unit Q3 away from the twenty-first via V21 in the second circuit unit Q2.

[0392] In an exemplary embodiment, the first planar layer of at least one circuit unit may further include a twenty-fourth via hole V24. The orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the sixth connection electrode 56 on the substrate. The first planar layer within the twenty-fourth via hole V24 is removed, exposing the surface of the sixth connection electrode 56. The twenty-fourth via hole V24 is configured to connect a subsequently formed initial connection line to the sixth connection electrode 56 through the via hole.

[0393] (38) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process to form a fourth conductive layer disposed on the first flat layer, as shown in FIG. 26A and FIG. 26B , where FIG. 26B is a planar schematic diagram of the fourth conductive layer in FIG. 26A .

[0394] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least a data signal line 61 , an anode connection electrode 62 , and a first power line 71 .

[0395] In an exemplary embodiment, the data signal line 61 may be in the shape of a straight line or a zigzag line extending along the second direction Y. The data signal line 61 is connected to the third connection electrode 53 through the twenty-first via hole V21. Since the third connection electrode 53 is connected to the first region of the fourth active layer, the data signal line 61 can write a data signal to the first electrode of the fourth transistor T4.

[0396] In an exemplary embodiment, positions of the data signal lines 61 in the first circuit unit Q1 , the second circuit unit Q2 , and the third circuit unit Q3 may be substantially the same, and the data signal lines 61 may all be located on one side of the first direction X of the first power line 71 .

[0397] In an exemplary embodiment, the fourth conductive layer pattern in the second circuit unit Q2 is close to the fourth conductive layer pattern in the first circuit unit Q1, but away from the fourth conductive layer pattern in the third circuit unit Q3. That is, the distance between the fourth conductive layer pattern in the first circuit unit Q1 and the fourth conductive layer pattern in the second circuit unit Q2 is smaller than the distance between the fourth conductive layer pattern in the second circuit unit Q2 and the fourth conductive layer pattern in the third circuit unit Q3. For example, a first spacing W1 is defined between the data signal line 61 in the first circuit unit Q1 and the data signal line 61 in the second circuit unit Q2, and a second spacing W2 is defined between the data signal line 61 in the second circuit unit Q2 and the data signal line 61 in the third circuit unit Q3, where the first spacing W1 is smaller than the second spacing W2.

[0398] In an exemplary embodiment, the first distance W1 may be the distance between an edge of the data signal line 61 in the first circuit unit Q1 that is close to the data signal line 61 in the second circuit unit Q2 and an edge of the data signal line 61 in the second circuit unit Q2 that is close to the data signal line 61 in the first circuit unit Q1, or the distance between an edge of the data signal line 61 in the first circuit unit Q1 that is away from the data signal line 61 in the second circuit unit Q2 and an edge of the data signal line 61 in the second circuit unit Q2 that is away from the data signal line 61 in the first circuit unit Q1. The second distance W2 may be the distance between an edge of the data signal line 61 in the second circuit unit Q2 that is close to the data signal line 61 in the third circuit unit Q3 and an edge of the data signal line 61 in the third circuit unit Q3 that is close to the data signal line 61 in the second circuit unit Q2, or the distance between an edge of the data signal line 61 in the second circuit unit Q2 that is away from the data signal line 61 in the third circuit unit Q3 and an edge of the data signal line 61 in the third circuit unit Q3 that is away from the data signal line 61 in the second circuit unit Q2.

[0399] In an exemplary embodiment, the anode connection electrode 62 may be in a block shape (eg, a rectangular shape), and the anode connection electrode 62 is configured to be connected to an anode to be formed subsequently.

[0400] In an exemplary embodiment, the anode connection electrode 62 of the circuit unit in the first circuit unit Q1 can be arranged on the side opposite to the second direction Y of the power connection line 44 in this circuit unit, and the anode connection electrode 62 is connected to the fifth connection electrode 55 through the anode connection line 63.

[0401] In an exemplary embodiment, the fourth conductive layer of the circuit unit in the first circuit unit Q1 may further include an anode connecting line 63, and the shape of the anode connecting line 63 may be a strip shape extending along the second direction Y. The first end of the anode connecting line 63 is connected to the anode connecting electrode 62, and the second end of the anode connecting line 63 extends along the second direction Y toward the direction close to the fifth connecting electrode 55, and is connected to the fifth connecting electrode 55 through the twenty-second via hole V22.

[0402] In an exemplary embodiment, in at least one circuit unit, the anode connection electrode 62 and the anode connection line 63 may be an integral structure connected to each other.

[0403] In an exemplary embodiment, the anode connection electrode 62 of the circuit unit in the second circuit unit Q2 and the third circuit unit Q3 can be set on one side of the power connection line 44 in the second direction Y in this circuit unit, and the anode connection electrode 62 is connected to the fifth connection electrode 55 through the twenty-second via hole V22.

[0404] In an exemplary embodiment, the fourth conductive layer in the second circuit unit Q2 and the third circuit unit Q3 may further include an extended electrode 64, and the shape of the extended electrode 64 may be a strip shape extending along the second direction Y, the first end of the extended electrode 64 is connected to the anode connecting electrode 62, and the second end of the extended electrode 64 extends in the opposite direction of the second direction Y, and the extended electrode 64 is configured to improve the flatness of the anode.

[0405] In an exemplary embodiment, in at least one circuit unit, the anode connection electrode 62 and the extension electrode 64 may be an integral structure connected to each other.

[0406] In an exemplary embodiment, the first power line 71 may be in the shape of a straight line or a zigzag line extending along the second direction Y. The first power line 71 may be provided in each circuit unit and connected to the fourth connection electrode 54 via the twenty-third via hole V23. Since the fourth connection electrode 54 is connected to the power connection line 44, the power connection line 44 extending in the main portion along the first direction X and the first power line 71 extending in the main portion along the second direction Y are interconnected. This allows the first power line 71 and the power connection line 44 to form a mesh-like interconnected structure on the display substrate for transmitting the first power signal. This effectively reduces the resistance of the first power line 71 and the voltage drop of the first power signal, and also effectively improves the uniformity of the first power signal across the display substrate, thereby enhancing display uniformity and improving display quality.

[0407] In an exemplary embodiment, unlike the structure of the aforementioned embodiment in which the first power line 71 is connected to the power connection line 44 through the twenty-third via hole V23, the first power line 71 of this embodiment is connected to the fourth connection electrode 54 serving as the power connection electrode through the twenty-third via hole V23. Since the fourth connection electrode 54 is located on one side of the second direction Y of the power connection line 44, the position of the twenty-third via hole V23 is lowered so that the pixel opening formed subsequently does not overlap with the twenty-third via hole V23.

[0408] In an exemplary embodiment, the orthographic projection of the first power line 71 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 51 on the substrate, so the constant voltage first power line 71 can effectively shield the influence of other signals in the pixel driving circuit on the first node N1.

[0409] In an exemplary embodiment, the fourth conductive layer of some circuit units may further include an initial connection line 73. The initial connection line 73 may be in the shape of a straight line or a zigzag line extending along the second direction Y. The initial connection line 73 may be disposed in the first circuit unit Q1 and may be connected to the sixth connection electrode 56 via the twenty-fourth via hole V24. Since the sixth connection electrode 56 is connected to the first initial connection block 41-1, and the first initial connection block 41-1 is connected to the first initial signal line 41, the first initial signal lines extending along the first direction X and the initial connection lines extending along the second direction Y form a mesh-like interconnected structure on the display substrate for transmitting the first initial signal. This effectively reduces the resistance of the first initial signal lines and the voltage drop of the first initial signal, and also effectively improves the uniformity of the first initial signal, thereby effectively improving display uniformity and enhancing display quality.

[0410] In some possible embodiments, the initial connection line can be connected to the second initial signal line through a via, so that the second initial signal line and the initial connection line form a mesh-like mesh connection structure for transmitting the second initial signal on the display substrate, or the initial connection line can be connected to the third initial signal line through a via, so that the third initial signal line and the initial connection line form a mesh-like mesh connection structure for transmitting the third initial signal on the display substrate, which is not limited in the present disclosure.

[0411] In some possible implementations, the fourth conductive layer of at least one circuit unit may further include a second power line to form a VSS in pixel structure, which is not limited in the present disclosure.

[0412] (39) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a second planar layer covering the fourth conductive layer, wherein a plurality of vias are provided on the second planar layer, as shown in FIG. 27 .

[0413] In an exemplary embodiment, the plurality of vias of each circuit unit includes at least an anode via V30. The orthographic projection of the anode via V30 on the substrate is within the range of the orthographic projection of the anode connection electrode 62 on the substrate. The second planar layer within the anode via V30 is removed, exposing the surface of the anode connection electrode 62. The anode connection electrode is configured such that a subsequently formed anode is connected to the anode connection electrode 62 through the via.

[0414] (40) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the second flat layer, wherein the anode conductive layer includes at least a plurality of anode patterns, as shown in FIG28A and FIG28B , FIG28B being a planar schematic diagram of the anode conductive layer in FIG28A .

[0415] In an exemplary embodiment, the plurality of anodes may include a first anode 90A located in a red light-emitting unit, a second anode 90B located in a green light-emitting unit, and a third anode 90C located in a blue light-emitting unit. The first anode 90A and the second anode 90B may be arranged sequentially along the second direction Y, and the third anode 90C may be arranged on one side of the first anode 90A and the second anode 90B in the first direction X.

[0416] In an exemplary embodiment, the first anode 90A, the second anode 90B, and the third anode 90C may be connected to the anode connection electrode 62 of the corresponding circuit unit through the anode via V30 , respectively.

[0417] In an exemplary embodiment, at least one of the first anode 90A, the second anode 90B, and the third anode 90C may include an anode body portion and an anode connecting portion connected to each other, the anode connecting portion being connected to the anode body portion on one hand and to the anode connecting electrode 62 through the anode via V30 on the other hand.

[0418] In an exemplary embodiment, the orthographic projection of the first anode body portion on the substrate does not overlap with the orthographic projection of the twenty-first via V21 serving as a data via and the twenty-third via V23 serving as a power via on the substrate, and the orthographic projection of the first anode body portion on the substrate does not overlap with the orthographic projection of the anode via V30 on the substrate.

[0419] In an exemplary embodiment, since the first anode 90A, the second anode 90B and the third anode 90C are moved upward as a whole, the orthographic projection of the first anode body on the substrate at least partially overlaps with the orthographic projection of the first initial signal line 41 on the substrate, and the orthographic projection of the first anode body on the substrate does not overlap with the orthographic projection of the power connection line 44 on the substrate.

[0420] In an exemplary embodiment, a groove 90-1 may be provided on the second anode body. The groove 90-1 may be block-shaped (e.g., rectangular) and may be located on an edge of the second anode body close to the first anode 90A. The groove 90-1 is configured to avoid the twenty-first via hole V21, so that the orthographic projection of the second anode body on the substrate does not overlap with the orthographic projection of the twenty-first via hole V21, which serves as a data via hole, on the substrate.

[0421] In an exemplary embodiment, since the first anode 90A, the second anode 90B and the third anode 90C are moved upward as a whole, and the twenty-first via V21 serving as the power via is moved downward, the orthographic projection of the second anode body portion on the substrate does not overlap with the orthographic projection of the twenty-third via V23 serving as the power via on the substrate.

[0422] In an exemplary embodiment, since the first anode 90A, the second anode 90B and the third anode 90C are moved upward as a whole, the orthographic projection of the second anode body on the substrate at least partially overlaps with the orthographic projection of the first scanning signal line 31 and the power connection line 44 on the substrate, and the orthographic projection of the second anode body on the substrate does not overlap with the orthographic projection of the first initial signal line 41, the second initial signal line 42 and the second initial signal line 43 on the substrate.

[0423] In an exemplary embodiment, due to pixel compression, the distance between the data via in the second circuit unit Q2 and the data via in the third circuit unit Q3 is increased, so that the twenty-first via V21 in the second circuit unit Q2 and the twenty-first via V21 in the third circuit unit Q3 are respectively located on both sides of the third anode main body in the first direction X, and the distance between the twenty-first via V21 in the second circuit unit Q2 and the twenty-first via V21 in the third circuit unit Q3 is greater than the width of the third anode main body in the first direction X, so that the orthographic projection of the third anode main body on the substrate does not overlap with the orthographic projection of the twenty-first via V21 serving as the data via on the substrate.

[0424] In an exemplary embodiment, since the first anode 90A, the second anode 90B and the third anode 90C are moved upward as a whole, and the twenty-first via V21 serving as the power via is moved downward, the orthographic projection of the third anode body on the substrate does not overlap with the orthographic projection of the twenty-third via V23 serving as the power via on the substrate.

[0425] In an exemplary embodiment, since the first anode 90A, the second anode 90B and the third anode 90C are moved upward as a whole, the orthographic projection of the third anode body on the substrate at least partially overlaps with the orthographic projections of the first scanning signal line 31 and the third scanning signal line 33 on the substrate, and the orthographic projection of the third anode body on the substrate does not overlap with the orthographic projections of the second scanning signal line 32, the light-emitting signal line 34, the power connection line 44 and the second initial signal line 42 on the substrate.

[0426] (41) Forming a pixel definition layer pattern. In an exemplary embodiment, forming the pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition film using a patterning process to form a pixel definition layer pattern covering the anode conductive layer pattern, wherein a plurality of pixel openings are provided on the pixel definition layer, as shown in FIG. 29 .

[0427] In an exemplary embodiment, the plurality of pixel openings may include a first pixel opening 100A, a second pixel opening 100B, and a third pixel opening 100C, and the structure is substantially the same as that of the previous embodiment.

[0428] In an exemplary embodiment, any one or more of the first pixel opening 100A, the second pixel opening 100B and the third pixel opening 100C have an orthographic projection on the substrate that does not overlap with an orthographic projection of the twenty-first via hole V21 serving as a data via hole on the substrate, have an orthographic projection on the substrate that does not overlap with an orthographic projection of the twenty-first via hole V21 serving as a power via hole on the substrate, and have an orthographic projection on the substrate that does not overlap with an orthographic projection of the anode via hole on the substrate.

[0429] In an exemplary embodiment, in the second direction Y, the first pixel opening 100A, the second pixel opening 100B, and the third pixel opening 100C may be disposed in a region of the corresponding circuit unit close to a previous unit row.

[0430] In an exemplary embodiment, the orthographic projection of at least one first pixel opening 100A on the substrate at least partially overlaps with the orthographic projection of the first initial signal line 41 on the substrate, and the orthographic projection of the first pixel opening 100A on the substrate does not overlap with the orthographic projection of the power connection line 44 on the substrate.

[0431] In an exemplary embodiment, the orthographic projection of at least one first pixel opening 100A on the substrate also at least partially overlaps with the orthographic projection of the third initial signal line 43 on the substrate, and the orthographic projection of at least one first pixel opening 100A on the substrate also does not overlap with the orthographic projections of the first scanning signal line 31, the second scanning signal line 32, the third scanning signal line 33, the light-emitting signal line 34 and the second initial signal line 42 on the substrate.

[0432] In an exemplary embodiment, the orthographic projection of at least one second pixel opening 100B on the substrate at least partially overlaps with the orthographic projections of the first scan signal line 31 and the power connection line 44 on the substrate, and the orthographic projection of the second pixel opening 100B on the substrate does not overlap with the orthographic projections of the first initial signal line 41, the second initial signal line 42, and the second initial signal line 43 on the substrate.

[0433] In an exemplary embodiment, the orthographic projection of the at least one second pixel opening 100B on the substrate also does not overlap with the orthographic projections of the second scan signal line 32 , the third scan signal line 33 , and the light emitting signal line 34 on the substrate.

[0434] In an exemplary embodiment, the orthographic projection of at least one third pixel opening 100C on the substrate at least partially overlaps with the orthographic projections of the first scanning signal line 31 and the third scanning signal line 33 on the substrate, and the orthographic projection of the third pixel opening 100C on the substrate does not overlap with the orthographic projections of the second scanning signal line 32, the light emitting signal line 34, the power connection line 44 and the second initial signal line 42 on the substrate.

[0435] In an exemplary embodiment, an orthographic projection of the at least one third pixel opening 100C on the substrate also at least partially overlaps with orthographic projections of the first preliminary signal line 41 and the third preliminary signal line 43 on the substrate.

[0436] In an exemplary embodiment, the subsequent preparation process may include forming an organic light emitting layer, a cathode, and an encapsulation structure layer, and the above structures are substantially the same as those in the previous embodiment.

[0437] The display substrate provided by the exemplary embodiment of the present disclosure has the technical effects of the aforementioned embodiments, and by adopting technical means such as pixel compression to adjust the spacing between data vias, moving the anode upward as a whole, and moving the power via downward, there are no data vias and power vias within the range of the pixel opening, and the anode exposed by the pixel opening has good flatness, which can effectively avoid defects such as off-screen watermarks caused by poor anode flatness, can effectively improve color deviation, and improve display quality.

[0438] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0439] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0440] The present disclosure also provides a method for preparing a display substrate to produce the display substrate provided in the above embodiment. In an exemplary embodiment, the preparation method may include:

[0441] forming a driving structure layer on a substrate, the driving structure layer comprising a plurality of circuit units, at least one circuit unit comprising a pixel driving circuit, a power connection line extending along a first direction, and a first power line extending along a second direction, wherein the first direction and the second direction intersect, the pixel driving circuit comprising at least a power connection electrode, the power connection electrode being connected to the power connection line, and the first power line being connected to the power connection line or the power connection electrode through a power via;

[0442] A light-emitting structure layer is formed on the driving structure layer; the light-emitting structure layer includes a plurality of light-emitting units, at least one light-emitting unit includes an anode and a pixel definition layer arranged on a side of the anode away from the substrate, the anode is connected to a pixel driving circuit of a corresponding circuit unit, the pixel definition layer is provided with a pixel opening exposing the anode, and the orthographic projection of at least one pixel opening on the substrate does not overlap with the orthographic projection of the power via on the substrate.

[0443] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0444] While the embodiments disclosed herein are as described above, it should be noted that the above embodiments are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a driving structure layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving structure layer away from the substrate; on a plane parallel to the display substrate, the driving structure layer comprises a plurality of circuit units, at least one circuit unit comprises a pixel driving circuit, a power connection line extending along a first direction, and a first power line extending along a second direction, the first direction and the second direction intersect, the pixel driving circuit comprises at least a power connection electrode, the power connection electrode is connected to the power connection line, and the first power line is connected to the power connection line or the power connection electrode through a power via; the light-emitting structure layer comprises a plurality of light-emitting units, at least one light-emitting unit comprises an anode and a pixel definition layer arranged on a side of the anode away from the substrate, the anode is connected to the pixel driving circuit of the corresponding circuit unit, the pixel definition layer is provided with a pixel opening exposing the anode, and the orthographic projection of at least one pixel opening on the substrate does not overlap with the orthographic projection of the power via on the substrate.

2. The display substrate according to claim 1, wherein The plurality of light-emitting units include at least a first light-emitting unit that emits a first color light, a second light-emitting unit that emits a second color light, and a third light-emitting unit that emits a third color light, wherein the first light-emitting unit includes at least a first anode and a first pixel opening exposing the first anode, the second light-emitting unit includes at least a second anode and a second pixel opening exposing the second anode, and the third light-emitting unit includes at least a third anode and a third pixel opening exposing the third anode; The second anode is arranged on one side of the first anode in the second direction, and the third anode is arranged on one side of the first anode in the first direction; the orthographic projections of the first pixel opening and the second pixel opening on the substrate at least partially overlap with the orthographic projection of the first power line on the substrate, and the orthographic projection of the third pixel opening on the substrate does not overlap with the orthographic projection of the first power line on the substrate.

3. The display substrate according to claim 2, wherein: The orthographic projections of the first pixel opening and the second pixel opening on the substrate are located within a range of the orthographic projection of the first power line on the substrate.

4. The display substrate according to claim 2, wherein: In at least one circuit unit and a circuit unit adjacent to the first direction, the first power lines in the two circuit units are an integrated structure connected to each other.

5. The display substrate according to claim 2, wherein: At least one circuit unit further includes a data signal line. In at least one circuit unit and the circuit units adjacent to each other in the first direction, the data signal line in one circuit unit is arranged on the side of the first power line in the opposite direction of the first direction, and the data signal line in the other circuit unit is arranged on the side of the first power line in the first direction; the orthographic projections of the first pixel opening and the second pixel opening on the substrate do not overlap with the orthographic projections of the data signal line on the substrate, and the orthographic projection of the third pixel opening on the substrate at least partially overlaps with the orthographic projection of the data signal line on the substrate. The display substrate according to claim 5 , wherein: The pixel driving circuit also includes a fourth transistor and a data connection electrode, the fourth transistor includes at least a fourth active layer, and the data signal line is connected to the data connection electrode through a data via; in at least one circuit unit and a circuit unit adjacent in the first direction, the data connection electrode in one circuit unit is connected to the first area of ​​the fourth active layer through a via, and the data connection electrode in the other circuit unit is connected to the first area of ​​the fourth active layer through a data connection line.

7. The display substrate according to claim 6, wherein: The pixel driving circuit also includes a shielding electrode and a second transistor with a dual-gate structure, the shielding electrode is connected to the first power line, the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor on the substrate, and the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the data connection line on the substrate.

8. The display substrate according to claim 5, wherein: The pixel driving circuit also includes a fourth node electrode and an anode connecting electrode, and the anode in at least one light-emitting unit is connected to the anode connecting electrode through an anode via; in at least one circuit unit and the circuit units adjacent in the first direction, the anode connecting electrode in one circuit unit is connected to the fourth node electrode through a via, and the anode connecting electrode in another circuit unit is connected to the fourth node electrode through an anode connecting line; the orthographic projections of the first pixel opening and the second pixel opening on the substrate do not overlap with the orthographic projection of the anode connecting line on the substrate, and the orthographic projection of the third pixel opening on the substrate at least partially overlaps with the orthographic projection of the anode connecting line on the substrate.

9. The display substrate according to claim 8, wherein: The third pixel opening has an opening center line, which is a straight line extending along the second direction and passing through the geometric center of the third pixel opening; in at least one third pixel opening, the anode connection line has a first distance from the opening center line, and the data signal line has a second distance from the opening center line, and the ratio of the first distance to the second distance is 0.8 to 1.

2.

10. The display substrate according to claim 2, wherein: At least one circuit unit also includes at least one initial signal line extending along the first direction, and a second power line and an initial connection line extending along the second direction, the initial connection line is connected to the initial signal line, the orthographic projections of the first pixel opening and the second pixel opening on the substrate do not overlap with the orthographic projections of the second power line and the initial connection line on the substrate, and the orthographic projection of the third pixel opening on the substrate at least partially overlaps with the orthographic projections of the second power line and the initial connection line on the substrate.

11. The display substrate according to claim 10, wherein: The third pixel opening has an opening center line, which is a straight line extending along the second direction and passing through the geometric center of the third pixel opening; in at least one third pixel opening, there is a third distance between the second power line and the opening center line, and there is a fourth distance between the initial connection line and the opening center line, and the ratio of the third distance to the fourth distance is 0.8 to 1.

2.

12. The display substrate according to claim 2, wherein: The pixel driving circuit also includes a storage capacitor, and at least one circuit unit also includes a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line, a first initial signal line, a second initial signal line and a third initial signal line extending along the first direction and connected to the pixel driving circuit, the first scanning signal line is arranged on a side of the storage capacitor in the opposite direction of the second direction, the third scanning signal line is arranged on a side of the first scanning signal line away from the storage capacitor, the first initial signal line is arranged on a side of the third scanning signal line away from the storage capacitor, the light-emitting signal line is arranged on one side of the storage capacitor in the second direction, and the second scanning signal line is arranged on the side of the light-emitting signal line away from the storage capacitor. on one side, the second initial signal line is arranged on a side of the second scanning signal line away from the storage capacitor, and the third initial signal line is arranged on a side of the second initial signal line away from the storage capacitor; the orthographic projection of at least one first pixel opening on the substrate at least partially overlaps with the orthographic projection of the power connection line on the substrate, the orthographic projection of at least one second pixel opening on the substrate at least partially overlaps with the orthographic projections of the first initial signal line, the second initial signal line and the third initial signal line on the substrate, and the orthographic projection of at least one third pixel opening on the substrate at least partially overlaps with the orthographic projections of the second scanning signal line, the light-emitting signal line, the second initial signal line and the power connection line on the substrate.

13. The display substrate according to claim 12, wherein: The orthographic projection of at least one first pixel opening on the substrate does not overlap with the orthographic projection of the first initial signal line on the substrate, the orthographic projection of at least one second pixel opening on the substrate does not overlap with the orthographic projections of the first scanning signal line and the power connection line on the substrate, and the orthographic projection of at least one third pixel opening on the substrate does not overlap with the orthographic projections of the first scanning signal line and the third scanning signal line on the substrate.

14. The display substrate according to claim 1, wherein The plurality of light-emitting units include at least a first light-emitting unit that emits a first color light, a second light-emitting unit that emits a second color light, and a third light-emitting unit that emits a third color light, wherein the first light-emitting unit includes at least a first anode and a first pixel opening exposing the first anode, the second light-emitting unit includes at least a second anode and a second pixel opening exposing the second anode, and the third light-emitting unit includes at least a third anode and a third pixel opening exposing the third anode; The second anode is arranged on one side of the first anode in the second direction, and the third anode is arranged on one side of the first anode in the first direction; the pixel driving circuit further includes a data connection electrode, and at least one circuit unit further includes a data signal line, and the data signal line is connected to the data connection electrode through a data via; The orthographic projections of the first pixel opening, the second pixel opening, and the third pixel opening on the substrate do not overlap with the orthographic projection of the data via on the substrate.

15. The display substrate according to claim 14, wherein: The multiple circuit units include at least a first circuit unit, a second circuit unit and a third circuit unit arranged in sequence along the first direction, the first circuit unit includes at least a first pixel driving circuit and a first data signal line connected to the data connection electrode in the first pixel driving circuit through a first data via, the second circuit unit includes at least a second pixel driving circuit and a second data signal line connected to the data connection electrode in the second pixel driving circuit through a second data via, and the third circuit unit includes at least a third pixel driving circuit and a third data signal line connected to the data connection electrode in the third pixel driving circuit through a third data via; the orthographic projections of the first pixel opening and the second pixel opening on the substrate at least partially overlap with the orthographic projections of the first data signal line on the substrate, and the orthographic projection of the third pixel opening on the substrate does not overlap with the orthographic projections of the first data signal line, the second data signal line and the third data signal line on the substrate.

16. The display substrate according to claim 15, wherein: In the first direction, the distance between the first data signal line and the second data signal line is smaller than the distance between the second data signal line and the third data signal line, and the distance between the first data via and the second data via is smaller than the distance between the second data via and the third data via.

17. The display substrate according to claim 15, wherein: In the first direction, the second data via hole and the third data via hole are disposed on both sides of the third pixel opening, and in the second direction, the first data via hole is disposed between the first pixel opening and the second pixel opening.

18. The display substrate according to claim 14, wherein: The pixel driving circuit includes at least a storage capacitor, and at least one circuit unit further includes a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line, a first initial signal line, a second initial signal line and a third initial signal line extending along the first direction and connected to the pixel driving circuit, the first scanning signal line is arranged on a side of the storage capacitor in the opposite direction of the second direction, the third scanning signal line is arranged on a side of the first scanning signal line away from the storage capacitor, the first initial signal line is arranged on a side of the third scanning signal line away from the storage capacitor, the light-emitting signal line is arranged on one side of the storage capacitor in the second direction, and the second scanning signal line is arranged on the The light-emitting signal line is arranged on a side away from the storage capacitor, the second initial signal line is arranged on a side away from the second scanning signal line, and the third initial signal line is arranged on a side away from the storage capacitor; the orthographic projection of at least one first pixel opening on the substrate at least partially overlaps with the orthographic projection of the first initial signal line on the substrate, the orthographic projection of at least one second pixel opening on the substrate at least partially overlaps with the orthographic projections of the first scanning signal line and the power connection line on the substrate, and the orthographic projection of at least one third pixel opening on the substrate at least partially overlaps with the orthographic projections of the first scanning signal line and the third scanning signal line on the substrate.

19. The display substrate according to claim 18, wherein: The orthographic projection of at least one first pixel opening on the substrate does not overlap with the orthographic projection of the power connection line on the substrate, the orthographic projection of at least one second pixel opening on the substrate does not overlap with the orthographic projections of the first initial signal line, the second initial signal line and the third initial signal line on the substrate, and the orthographic projection of at least one third pixel opening on the substrate does not overlap with the orthographic projections of the second scanning signal line, the light-emitting signal line, the power connection line and the second initial signal line on the substrate.

20. A display device comprising the display substrate according to any one of claims 1 to 19.

21. A method for preparing a display substrate, comprising: forming a driving structure layer on a substrate, the driving structure layer comprising a plurality of circuit units, at least one circuit unit comprising a pixel driving circuit, a power connection line extending along a first direction, and a first power line extending along a second direction, wherein the first direction and the second direction intersect, the pixel driving circuit comprising at least a power connection electrode, the power connection electrode being connected to the power connection line, and the first power line being connected to the power connection line or the power connection electrode through a power via; forming a light-emitting structure layer on the driving structure layer; The light-emitting structure layer includes a plurality of light-emitting units, at least one light-emitting unit includes an anode and a pixel definition layer arranged on a side of the anode away from the substrate, the anode is connected to a pixel driving circuit of a corresponding circuit unit, the pixel definition layer is provided with a pixel opening exposing the anode, and the orthographic projection of at least one pixel opening on the substrate does not overlap with the orthographic projection of the power via on the substrate.

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