Display apparatus and electronic device

Abstract

The purpose of the present invention is to provide a display device and an electronic apparatus that make it possible to suppress leakage power, for example.　Provided is a display device having a plurality of circuit blocks that operate at the time of display operation, the plurality of circuit blocks having a first circuit block for which a power supply is controlled to be off at the time of standby. The display device includes, for example, a switch provided between a power supply line of the power supply and the first circuit block, and a control unit for controlling the switch to be off when the standby state and the operation of the first circuit block are unnecessary.

Description

Display devices and electronic devices

[0001] The present technology relates to a display device and an electronic device.

[0002] Power consumption reduction technologies for display devices are known. For example, Patent Document 1 below discloses a technology for reducing the power consumption of a display IF circuit by configuring the register of the display IF circuit with nonvolatile memory and reducing the number of register accesses after restarting the power supply. Furthermore, Patent Document 2 discloses a technology for suppressing voltage application to pixels when the power supply is off by performing waveform adjustment processing of a gate waveform when the power supply is on and not performing the waveform adjustment processing when the power supply is off.

[0003] On the other hand, Patent Document 3 discloses a technology related to power gating of a microprocessor, which aims to reduce power consumption while suppressing malfunctions and increases in area by inserting a circuit between blocks that fixes the input of the circuit when power is cut off and maintaining the output even when power is stopped.

[0004] JP 2023-153768 A JP 2015-197484 A JP 2012-094171 A

[0005] Incidentally, the leakage current of individual transistors tends to increase with each successive generation of semiconductor processes. In addition, as semiconductor processes become more miniaturized and the amount of logic mounted increases, the leakage current also increases accordingly.

[0006] An object of the present technology is to provide, for example, a display device and an electronic device that can suppress leakage power.

[0007] The present technology relates to, for example, a display device having a plurality of circuit blocks that operate during a display operation, wherein the plurality of circuit blocks include a first circuit block that is controlled to be powered off during standby.

[0008] The present technology relates to, for example, an electronic device having a display device of the present technology.

[0009] FIG. 1 is a diagram showing a schematic configuration example of a display device to which the present technology can be applied. FIG. 2 is a diagram showing a configuration example of a main power supply path of a display device in a comparative example. FIG. 3 is a diagram showing a configuration example of a main power supply path of a display device according to a first embodiment. FIG. 4 is a diagram showing a configuration example of a switch circuit. FIG. 5 is a diagram showing another configuration example of a switch circuit. FIG. 6 is a diagram illustrating a layout of a switch circuit. FIG. 7 is a diagram showing a configuration example of a control circuit. FIG. 8 is a diagram showing another configuration example of a control circuit. FIG. 9 is a diagram showing a configuration example of a display device according to a second embodiment. FIG. 10 is a diagram illustrating a layout of a switch circuit in a third embodiment. FIG. 11 is a diagram showing a configuration example of a display device according to a fourth embodiment. FIG. 12 is a diagram showing a configuration example of a display device according to a fifth embodiment. FIG. 13A is a plan view of pixels, and FIG. 13B is a diagram showing a configuration example for discharging leakage current between pixels. FIG. 14 is a diagram showing a configuration example of a display device according to a sixth embodiment. FIG. 15 is a conceptual diagram illustrating a configuration example of a substrate to which the present technology can be applied. FIG. 16 is a diagram showing a configuration example of a display device according to a seventh embodiment. FIG. 17 is a diagram showing an example of a configuration of a pixel circuit. FIG. 18 is a diagram showing an example of a configuration of a pixel circuit. FIG. 19 is a diagram showing an example of a configuration of a pixel circuit. FIG. 20 is a diagram showing an example of a configuration of a pixel circuit. FIG. 21 is a diagram showing an example of a configuration of a pixel circuit. FIG. 22 is a diagram showing an example of a configuration of a pixel circuit. FIG. 23 is a diagram showing an example of a configuration of a pixel circuit. FIG. 24 is a diagram showing an example of a configuration of a pixel circuit. FIG. 25 is a diagram showing an example of a configuration of a pixel circuit. FIG. 26 is a perspective view showing an example of the appearance of a head-mounted display. FIG. 27 is a perspective view showing an example of the appearance of another head-mounted display. FIG. 28A is a front view showing an example of the appearance of a digital still camera. FIG. 28B is a rear view showing an example of the appearance of a digital still camera. FIG. 29 is a perspective view showing an example of the appearance of a television device. FIG. 30 is a perspective view showing an example of the appearance of a smartphone. FIG. 31A is a diagram showing an example of the interior of a vehicle from the rear to the front of the vehicle. FIG. 31B is a diagram showing an example of the interior of a vehicle from diagonally rear to diagonally front of the vehicle.

[0010] Hereinafter, embodiments of the present technology will be described with reference to the drawings. The description will be made in the following order. In this specification and the drawings, components having substantially the same function or configuration will be assigned the same reference numerals, and redundant description will be omitted as appropriate. Furthermore, the shapes, sizes, positional relationships, etc. of components shown in each drawing may be exaggerated depending on the content of the description, and hatching, reference numerals, etc. may be omitted. <1. Overview of the Present Technology> <2. First Embodiment> <3. Second Embodiment> <4. Third Embodiment> <5. Fourth Embodiment> <6. Fifth Embodiment> <7. Sixth Embodiment> <8. Seventh Embodiment> <9. Configuration Example of Pixel Circuit> <10. Modified Example> <11. Application Example>

[0011] <1. Overview of the Present Technology> First, an overview of a display device to which the present technology can be applied will be described. FIG. 1 is a diagram showing a schematic configuration example of a display device to which the present technology can be applied. The display device 1 shown in FIG. 1 is a device that displays images and the like using light-emitting elements. The light-emitting elements are, for example, LEDs (Light Emitting Diodes). LEDs include LEDs used in micro LED displays and OLEDs (Organic Light Emitting Diodes) used in organic EL (Electro-Luminescence) displays. Hereinafter, the display device 1 will be described as employing LEDs as light-emitting elements. The display device 1 is, for example, a display mounted in an electronic device. Specific examples of electronic devices to which the display device 1 can be applied will be described later.

[0012] The display device 1 has, as circuit blocks of its components, an input / output unit (IO) 2, a gamma processing unit 3, a power supply processing unit 4, an interface unit (IF) 5, a timing controller (TCON) 6, a pixel unit 7, a horizontal logic unit (HLOGIC) 8, a horizontal analog unit (HANALOG) 9, a vertical logic unit (VLOGIC) 10, and a vertical analog unit (VANALOG) 11. The display device 1 has these circuit blocks mounted on a substrate, for example. The substrate includes a semiconductor substrate such as silicon.

[0013] The input / output unit 2 inputs and outputs various data and is configured, for example, with an externally connectable FPC (Flexible Printed Circuits). The input / output unit 2 is connected to the gamma processing unit 3, the power supply processing unit 4, and the interface unit 5. The gamma processing unit 3 performs gamma correction processing. The gamma processing unit 3 is connected to the input / output unit 2 and the horizontal analog unit 9, and sets gamma correction based on a setting value for gamma correction input via the input / output unit 2, and gamma-corrects the pixel signal output from the horizontal analog unit 9 to the pixel unit 7.

[0014] The power supply processing unit 4 is a circuit that outputs power for driving the pixel unit 7 and is configured to include, for example, an LDO (Low Drop Out) regulator. The power supply processing unit 4 is connected to the input / output unit 2 and the pixel unit 7, and converts the supply power input via the input / output unit 2 into a power supply voltage for driving the pixel unit 7 and supplies it to the pixel unit 7. The interface unit 5 is connected to the input / output unit 2 and the timing controller 6. The interface unit 5 is an interface for inputting and outputting image data and the like to and from the outside via the input / output unit 2. For example, a high-speed interface standard such as MIPI (Mobile Industry Processor Interface) can be adopted as this interface.

[0015] The timing controller 6 controls the operation timing of each circuit block. The timing controller 6 is connected to the interface unit 5, horizontal logic unit 8, horizontal analog unit 9, vertical logic unit 10, and vertical analog unit 11. The timing controller 6 outputs image data input via the input / output unit 2 and interface unit 5 to the horizontal logic unit 8 based on a clock signal supplied from an oscillator unit (not shown in FIG. 1 ) or the like, and outputs signals as needed to the horizontal logic unit 8 and the horizontal analog unit 9. The timing controller 6 also outputs signals as needed to the vertical logic unit 10 and the vertical analog unit 11 based on the clock signal.

[0016] Although not shown here, the pixel unit 7 has a plurality of pixels (pixel circuits) arranged in a matrix of m rows and n columns (m and n are natural numbers). The pixel unit 7 is provided with pixels that represent the three primary colors of R (red), G (green), and B (blue), for example, to represent a color image. Note that the color representation of an image is not limited to this, and a configuration that represents a monochrome (black and white) image, for example, may also be used. Specific examples of the configuration and operation of the pixel will be described later.

[0017] The pixel section 7 also has signal lines extending in the column direction of the pixel array and control lines extending in the row direction of the pixel array. A signal line is provided for each pixel column, and a control line is provided for each pixel row. Each signal line is connected to an output terminal of the corresponding column of the horizontal analog section 9 and to a pixel group of the corresponding column. Each control line is connected to an output terminal of the corresponding row of the vertical analog section 11 and to a pixel group of the corresponding row.

[0018] The horizontal logic unit 8 and the horizontal analog unit 9 constitute a horizontal driver. The horizontal driver can be configured, for example, with a RAMPDAC circuit that uses a ramp waveform analog signal to generate pixel signals to be output to signal lines. The horizontal driver is not limited to this, and may be configured, for example, with a voltage follower circuit having a voltage follower circuit in the output section to the signal line. The horizontal logic unit 8 distributes the image data input from the timing controller 6 to each signal line. The horizontal analog unit 9 converts the distributed image data into gamma-corrected pixel signals and outputs them to the corresponding signal lines of the pixel unit 7.

[0019] The vertical logic unit 10 and the vertical analog unit 11 constitute a vertical driver. The vertical driver can be constituted, for example, by a shift register type circuit having a shift register circuit in the signal input section. However, the vertical driver is not limited to this, and may be constituted, for example, by an address decoder type circuit having an address decoder in the signal input section. The vertical logic unit 10 generates shift signals for each pixel row from signals input from the timing controller 6. The vertical analog unit 11 generates control signals for driving control lines based on the shift signals and outputs them to the pixel unit 7.

[0020] The present technology relates to power supply control of circuit blocks that constitute the display device 1, such as the timing controller 6, the horizontal logic unit 8, and the vertical logic unit 10, for example.

[0021] (Configuration example of a display device as a comparative example) Before describing the power supply control of the display device 1 according to the embodiment of the present technology, a comparative example will be described. Fig. 2 is a diagram showing a configuration example of main power supply paths of a display device 1A as a comparative example. Note that the display device 1A in Fig. 2 has the above-mentioned input / output unit 2, gamma processing unit 3, power supply processing unit 4, interface unit 5, timing controller 6, pixel unit 7, horizontal logic unit 8, horizontal analog unit 9, vertical logic unit 10, and vertical analog unit 11.

[0022] The display device 1A includes an oscillator 12. The oscillator 12 is configured by, for example, an oscillator, and generates the above-mentioned clock signal. The oscillator 12 is connected to the timing controller 6, and the clock signal generated by the oscillator 12 is output to the timing controller 6.

[0023] The timing controller 6 has a CLK+EN control unit 211, a timing generator 22, a signal processing unit 23, and a register 24. The circuit blocks of the CLK+EN control unit 211, the timing generator 22, the signal processing unit 23, and the register 24 are respectively connected to the gamma processing unit 3, the power supply processing unit 4, the interface unit 5, the horizontal logic unit 8, the horizontal analog unit 9, the vertical logic unit 10, and the vertical analog unit 11. The horizontal logic unit 8 is connected to the horizontal analog unit 9, and the vertical logic unit 10 is connected to the vertical analog unit 11.

[0024] The CLK+EN control unit 211 controls the clock signal and various enable signals used appropriately in each circuit block. The CLK+EN control unit 211 outputs the clock signal output by the oscillator unit 12 to a predetermined circuit block. The CLK+EN control unit 211 also generates various enable signals and outputs them to a predetermined circuit block. The timing generator 22 controls the operation timing of each circuit block. The timing generator 22 generates signals such as a start pulse and outputs them to a predetermined circuit block. The signal processing unit 23 performs signal processing on image data input via the interface unit 5 and outputs the processed image data to the horizontal logic unit 8. This signal processing includes, for example, resolution conversion processing and interpolation processing of color information for each pixel. The register 24 inputs and outputs data to and from the signal processing unit 23 via buffers 30 and 31 and stores information processed by the signal processing unit 23.

[0025] The display device 1A has power supply lines VDD1IF and VSSIF, power supply lines VDD1 and VSSD, power supply lines VDD2 and VSSA, and power supply lines VCCP and Vcath. The power supply lines VDD1IF and VSSIF are connected to the interface unit 5 and apply a predetermined power supply voltage to the interface unit 5. The power supply lines VDD1 and VSSD are connected to the interface unit 5, the oscillator unit 12, the CLK+EN control unit 211, the timing generator 22, the signal processing unit 23, the register 24, the horizontal logic unit 8, and the vertical logic unit 10 and apply a predetermined power supply voltage to each connecting block. The power supply lines VDD2 and VSSA are connected to the oscillator unit 12, the horizontal analog unit 9, the vertical analog unit 11, the gamma processing unit 3, and the power supply processing unit 4 and apply a predetermined power supply voltage to each connecting block. The power supply line VCCP and the power supply line Vcath are connected to the pixel section 7 and apply a predetermined power supply voltage to the pixel section 7 .

[0026] The display device 1A is capable of a standby operation in which display by the pixel unit 7 is paused. The standby state caused by this standby operation is a state in which the display device is on standby so that display by the pixel unit 7 can be immediately performed. In the display device 1A of the comparative example, a power supply voltage is constantly applied to each circuit block, and therefore, even during standby, a standby current due to leakage current is generated in each circuit block.

[0027] The arrows in Figure 2 represent the main standby current that occurs during standby. As the semiconductor process generation advances, this standby current becomes more pronounced. As semiconductor processes become more miniaturized, the amount of logic mounted can be expected to increase accordingly, but this increase in leakage current also increases standby power due to its causal relationship. Increased standby power has a significant impact on battery life, particularly in mobile products. Therefore, the following embodiments aim to suppress this leakage power.

[0028] 3 is a diagram showing an example of the configuration of main power supply paths of a display device 1 according to a first embodiment. The display device 1 shown in Fig. 3 has an input / output unit 2 (not shown in Fig. 3), a gamma processing unit 3, a power supply processing unit 4, an interface unit 5, a timing controller 6, a pixel unit 7, a horizontal logic unit 8, a horizontal analog unit 9, a vertical logic unit 10, a vertical analog unit 11, and an oscillator unit 12. The oscillator unit 12 is connected to the timing controller 6, and a clock signal generated by the oscillator unit 12 is output to the timing controller 6.

[0029] The timing controller 6 has a CLK+EN control unit 21, a timing generator 22, a signal processing unit 23, and a register 24. The circuit blocks of the CLK+EN control unit 21, the timing generator 22, the signal processing unit 23 (IN), and the register 24 are respectively connected to the interface unit 5, the horizontal analog unit 9, the vertical analog unit 11, the gamma processing unit 3, and the power supply processing unit 4. The signal processing unit 23 (OUT) is connected to the register 24 via a control circuit 50a, and the register 24 is connected to the signal processing unit 23 via a buffer 31.

[0030] The signal processing unit 23 (OUT) is connected to the horizontal logic unit 8 (IN) and the vertical logic unit 10 (IN), and is also connected to the horizontal analog unit 9 via a control circuit 50b. The horizontal logic unit 8 (OUT) is connected to the horizontal analog unit 9 via a control circuit 50c, and the vertical logic unit 10 (OUT) is connected to the vertical analog unit 11 via a control circuit 50d. The control circuits 50a to 50d will be described later.

[0031] The CLK+EN control unit 21 controls the clock signals and various enable signals used appropriately in each circuit block. The CLK+EN control unit 21 outputs the clock signal output by the oscillator 12 to a predetermined circuit block. The CLK+EN control unit 21 also generates various enable signals and outputs them to a predetermined circuit block. Note that the CLK+EN control unit 21 differs from the CLK+EN control unit 211 of the comparative example in that it generates and outputs the signals used for the power supply control described above.

[0032] The timing generator 22 controls the operation timing of each circuit block. The timing generator 22 generates signals such as a start pulse and outputs them to a predetermined circuit block. The signal processing unit 23 performs signal processing on image data input via the interface unit 5 and outputs the processed image data to the horizontal logic unit 8. The register 24 inputs and outputs signals to and from the signal processing unit 23 and stores information processed by the signal processing unit 23.

[0033] The display device 1 has power supply lines VDD1IF and VSSIF, power supply lines VDD1 and VSSD, power supply lines VDD2 and VSSA, and power supply lines VCCP and Vcath. The power supply lines VDD1IF and VSSIF are connected to the interface unit 5 and apply a predetermined power supply voltage (specifically, a power supply voltage for the interface) to the interface unit 5. The potential of the power supply line VDD1IF is higher than that of VSSIF.

[0034] The power supply line VDD1 and the power supply line VSSD are connected to the interface unit 5, the oscillator unit 12, the CLK+EN control unit 21, the timing generator 22, the signal processing unit 23, the register 24, the horizontal logic unit 8, and the vertical logic unit 10, and apply a predetermined power supply voltage (specifically, a power supply voltage for digital circuits) to each connection block. However, the power supply line VDD1 is connected to the signal processing unit 23 via a switch circuit 40a. When the switch circuit 40a is on (conductive state), the power supply voltage is applied to the signal processing unit 23, but when the switch circuit 40a is off (non-conductive state), the power supply voltage is not applied. Furthermore, the power supply line VDD1 is connected to the horizontal logic unit 8 via a switch circuit 40b. When the switch circuit 40b is on (conductive state), the power supply voltage is applied to the horizontal logic unit 8, but when the switch circuit 40b is off (non-conductive state), the power supply voltage is not applied. Furthermore, the power supply line VDD1 is connected to the vertical logic unit 10 via a switch circuit 40c, and when the switch circuit 40c is on (conductive state), a power supply voltage is applied to the vertical logic unit 10, and when the switch circuit 40c is off (non-conductive state), no power supply voltage is applied to the vertical logic unit 10. The potential of the power supply line VDD1 is higher than that of the power supply line VSSD.

[0035] The power supply lines VDD2 and VSSA are connected to the oscillator 12, horizontal analog unit 9, vertical analog unit 11, gamma processing unit 3, and power supply processing unit 4, and apply a predetermined power supply voltage (specifically, a power supply voltage for the analog circuits) to each connection block. The potential of the power supply line VDD2 is higher than that of the power supply line VSSA. The power supply lines VCCP and Vcath are connected to the pixel unit 7, and apply a predetermined power supply voltage (specifically, a power supply voltage for the pixel circuits) to the pixel unit 7. The potential of the power supply line VCCP is higher than that of the power supply line Vcath.

[0036] The display device 1 supports standby operation, and during standby, the gamma processing unit 3, power supply processing unit 4, pixel unit 7, horizontal logic unit 8, horizontal analog unit 9, vertical logic unit 10, vertical analog unit 11, and signal processing unit 23 of the timing controller 6 are circuit blocks that do not need to be operated. Among these, the signal processing unit 23, horizontal logic unit 8, and vertical logic unit 10 are circuit blocks in a logic area that have logic circuits, memories, etc., are large in circuit scale, and have a large amount of leakage current. Therefore, in this embodiment, the signal processing unit 23, horizontal logic unit 8, and vertical logic unit 10 are circuit blocks that are subject to power control (first circuit blocks), and power control is performed by the above-mentioned switch circuits 40a to 40c. Note that, as with the comparative example, all circuit blocks other than the signal processing unit 23, horizontal logic unit 8, and vertical logic unit 10 are always powered on (second circuit blocks).

[0037] (Configuration Example of Switch Circuit) FIG. 4 is a diagram showing a configuration example of the switch circuit 40a. Note that while the switch circuit 40a connected to the signal processing unit 23 will be described here, the configuration of the switch circuits 40b and 40c is similar. The switch circuit 40a has a plurality of switches 41(1) to 41(n) and buffers 42(1) to 42(n) that respectively constitute a plurality of delay circuits. The switches 41(1) to 41(n) are, for example, transistors. One end of each of the switches 41(1) to 41(n) is connected to the power supply line VDD1, and the other end is connected to the signal processing unit 23. The control terminals of the switches 41(1) to 41(n) are sequentially connected to the CLK+EN control unit 21 via the buffers 42(1) to 42(n), respectively.

[0038] The CLK+EN control unit 21 functions as a switch control unit that controls the switch circuit 40a. The CLK+EN control unit 21 generates an XNOSIG_STATE signal as an enable signal that controls each of the switches 41(1) to 41(n) and outputs the signal to the control terminals of each of the switches 41(1) to 41(n). When the device is not in standby mode, the CLK+EN control unit 21 controls each of the switches 41(1) to 41(n) by setting the XNOSIG_STATE signal to, for example, a high level, thereby turning on the switches. When the device is in standby mode, the CLK+EN control unit 21 controls each of the switches 41(1) to 41(n) by setting the XNOSIG_STATE signal to, for example, a low level, thereby turning off the switches 41(1) to 41(n). Whether the device is in standby mode can be determined, for example, by an external input signal (for example, a standby instruction signal) via the input / output unit 2 and the interface unit 5.

[0039] The CLK+EN control unit 21 not only controls the switch circuit 40a depending on whether the circuit block to be power-controlled is in a standby state, but also controls the switch circuit 40a depending on whether the circuit block to be power-controlled needs to be operated. When the circuit block to be power-controlled needs to be operated, the CLK+EN control unit 21 controls each switch 41(1) to 41(n) to be on by, for example, setting the XNOSIG_STATE signal to a high level. Furthermore, when the circuit block to be power-controlled does not need to be operated, the CLK+EN control unit 21 controls each switch 41(1) to 41(n) to be off by, for example, setting the XNOSIG_STATE signal to a low level. Whether or not operation is needed can be determined, for example, by an external input signal (e.g., a signal indicating various setting modes) via the input / output unit 2 and the interface unit 5. For example, by using a different XNOSIG_STATE signal for each of the switch circuits 40a to 40c, power on / off control can be performed for each circuit block.

[0040] Due to the buffer connection described above, the XNOSIG_STATE signal output from the CLK+EN control unit 21 is buffer-delayed by the buffers 42(1) to 42(n) and then sequentially output to the switches 41(1) to 41(n). Therefore, the switches 41(1) to 41(n) sequentially switch their conduction states (on / off states) in response to the XNOSIG_STATE signal. In this way, by using the buffer delay of the buffers 42(1) to 42(n) to control the switches 41(1) to 41(n) in a time-division manner, the switches 41(1) to 41(n) can be turned on in stages during startup, thereby suppressing peak currents. The order in which the switches are switched is not particularly limited, but smooth startup can be achieved, for example, by switching the switches sequentially from the upstream operating circuit. The numerical values ​​n (n is a natural number) of the switches 41(1) to 41(n) and buffers 42(1) to 42(n) and the delay amounts in the buffers 42(1) to 42(n) are appropriately designed in advance according to the circuit scale of the signal processing unit 23. Similarly, appropriately designed switch circuits 40b and 40c are also used.

[0041] (Another Configuration Example of the Switch Circuit) The switch circuits 40a to 40c are not limited to those using buffer delay. For example, the switch circuit 40a may have the configuration shown in FIG. 5. The same applies to the configurations of the switch circuits 40b and 40c. The switch circuit 40a shown in FIG. 5 has flip-flops 43(1) to 43(n) instead of the buffers 42(1) to 42(n) described above. That is, the switch circuit 40a has multiple switches 41(1) to 41(n) and flip-flops 43(1) to 43(n) constituting multiple delay circuits. One end of each of the switches 41(1) to 41(n) is connected to the power supply line VDD1, and the other end is connected to the signal processing unit 23. The control terminals of the switches 41(1) to 41(n) are sequentially connected to the CLK+EN control unit 21 via the flip-flops 43(1) to 43(n), respectively.

[0042] The CLK+EN control unit 21 generates an XNOSIG_STATE signal as an enable signal for controlling each switch 41(1) to 41(n) and outputs it to the control terminal of each switch 41(1) to 41(n). The CLK+EN control unit 21 is also connected to the clock input terminals of each flip-flop 43(1) to 43(n) and outputs a clock signal to each clock input terminal. As a result, the XNOSIG_STATE signal output from the CLK+EN control unit 21 is synchronized with the clock signal by the flip-flops 43(1) to 43(n) and output sequentially to the switches 41(1) to 41(n). Therefore, the switches 41(1) to 41(n) are sequentially switched between conductive states (on and off) in response to the XNOSIG_STATE signal. In this way, the switches 41(1) to 41(n) may be controlled in a time-division manner using the processing delay of the flip-flops 43(1) to 43(n). In this case, the delay can be managed by a clock signal, and the switches 41(1) to 41(n) can be turned on in stages when the signal processing unit 23 is started, thereby suppressing the peak current.

[0043] (Example of Switch Circuit Layout Structure) FIG. 6 is a diagram illustrating the layout of switch circuits 40a to 40c. As shown in FIG. 6, switch circuits 40a to 40c are provided between a power supply line VDD1 and a circuit block (referred to as a power cutoff circuit block in the figure) that is a power supply control target. This creates a virtual VDD between the power supply line VDD1 and each of the power supply control target circuit blocks. In this way, when switch circuits 40a to 40c are header-type switches capable of cutting off connection to the power supply line VDD1 on the power supply side (high-potential side) of the power supply path, they are compatible with a twin-well structure of a P-type semiconductor substrate (PSUB: P-Substrate) as shown in the figure. Therefore, in the case of these switch circuits 40a to 40c, for example, manufacturing efficiency can be improved by using a PSUB twin-well structure for the substrate and configuring switch circuits 40a to 40c with P-type transistors, as shown in the figure.

[0044] (Configuration Example of Control Circuit) Fig. 7 is a diagram showing a configuration example of the above-mentioned control circuit 50a. In Fig. 7, the power gating compatible logic 23a is a circuit of the signal processing unit 23 whose power supply is controlled by the switch circuit 40a, and the always-on logic 24a is a circuit of the register 24 to which power is always supplied. Note that although the control circuit 50a provided between the signal processing unit 23 and the register 24 will be described here, the control circuits 50b to 50d have the same configuration.

[0045] As shown in the figure, if there is a signal transmission path from the power gating compatible logic 23a to the always-on logic 24a, the power gating compatible logic 23a may output an undefined signal to the always-on logic 24a when the power is off, and the always-on logic 24a may be affected by this undefined signal. The control circuit 50a uses a logic gate to avoid this undefined output.

[0046] As shown in the figure, the control circuit 50a can be configured, for example, by providing an AND element 51 between the wiring connecting the power gating-enabled logic 23a (OUT) and the always-on logic 24a. Specifically, one input of the AND element 51 is connected to the XNOSIG_STATE signal output terminal of the CLK+EN control unit 21, and the other input is connected to the power gating-enabled logic 23a (OUT). The output of the AND element 51 is also connected to the always-on logic 24a. By providing the AND element 51 on the signal transmission path from the power gating-enabled logic 23a to the always-on logic 24a in this manner, the signal from the power gating-enabled logic 23a (OUT) is output to the always-on logic 24a when the switch circuit 40a is on, but is not output when the switch circuit 40a is off. This makes it possible to avoid undefined output propagation when the power is off.

[0047] (Other Configuration Examples of Control Circuits) The control circuits 50a to 50d are not limited to those using logic gates. For example, the control circuit 50a may have the configuration shown in FIG. 8. The control circuits 50b to 50d have a similar configuration. The control circuit 50a shown in FIG. 8 has a flip-flop 52 instead of the above-mentioned AND element 51, and further has a flip-flop 53 as an enabler for the flip-flop 52.

[0048] If there is a signal transmission path from the power gating-enabled logic 23a to the always-on logic 24a, the control circuit 50a provides, for example, a flip-flop 52 between the wiring connecting the power gating-enabled logic 23a (OUT) and the always-on logic 24a. Specifically, the input of the flip-flop 52 is connected to the power gating-enabled logic 23a (OUT), and the output is connected to the always-on logic 24a. The input of the flip-flop 53 is connected to the XNOSIG_STATE signal output terminal of the CLK+EN control unit 21, and the output is connected to the clock input terminal of the flip-flop 52. The clock input terminal of the flip-flop 53 is then connected to the clock signal output terminal of the CLK+EN control unit 21. This allows the signal from the power gating-enabled logic 23a (OUT) to be output to the always-on logic 24a when the switch circuit 40a is on, but not when it is off. This avoids undefined output propagation when the power is off. By using the flip-flop 52 as the control circuits 50a to 50d, it is possible to reduce the influence of coupling between other circuits such as the power supply / GND (low potential side power supply), other signals, etc. When the logic gates described above are used as the control circuits 50a to 50d, the circuit area can be made smaller than when the flip-flop 52 is used.

[0049] As described above, in this embodiment, the display device 1 has multiple circuit blocks that operate during display operation. These multiple circuit blocks include the signal processing unit 23, horizontal logic unit 8, and vertical logic unit 10, which are powered off during standby and when operation is not required. By powering off the signal processing unit 23, horizontal logic unit 8, and vertical logic unit 10 in this manner during standby and when operation is not required, leakage current does not occur in the signal processing unit 23, horizontal logic unit 8, and vertical logic unit 10 during standby and when operation is not required, as indicated by the dashed arrows in FIG. 3, thereby reducing leakage power. The inclusion of switch circuits 40a-40c in the internal power supply circuit of the display device 1 enables complete operation within the display device 1, enabling detailed power control of the circuit blocks. Furthermore, power control (power on / off) by an external power supply is not required, and peak current during startup can be reduced, resulting in faster startup.

[0050] 3. Second Embodiment In the above-described first embodiment, a configuration has been described in which leakage current is suppressed by cutting off the power supply voltage to logic with a large gate scale during standby. However, it is also possible to cut off the power supply voltage to analog blocks during standby or when operation is not required, to suppress leakage current, as needed.

[0051] 9 is a diagram showing an example of the configuration of a display device 1 according to a second embodiment of the present technology. As described above, the gamma processing unit 3, the power supply processing unit 4, the horizontal analog unit 9, and the vertical analog unit 11 are blocks that do not need to operate in standby mode. Therefore, in this embodiment, the following configuration is used to perform power control on the gamma processing unit 3, the power supply processing unit 4, the horizontal analog unit 9, and the vertical analog unit 11 as blocks subject to power control.

[0052] 9 , power supply line VDD2 and power supply line VSSA are connected to oscillator 12, horizontal analog unit 9, vertical analog unit 11, gamma processing unit 3, and power supply processing unit 4, and apply a predetermined power supply voltage (specifically, the power supply voltage for the analog circuits) to each connecting block. However, power supply line VDD2 is connected to horizontal analog unit 9 via switch circuit 40d, and the power supply voltage is applied to horizontal analog unit 9 when switch circuit 40d is on (conductive state), and the power supply voltage is not applied when switch circuit 40d is off (non-conductive state). Furthermore, power supply line VDD2 is connected to vertical analog unit 11 via switch circuit 40e, and the power supply voltage is applied to vertical analog unit 11 when switch circuit 40e is on (conductive state), and the power supply voltage is not applied when switch circuit 40e is off (non-conductive state). Furthermore, the power supply line VDD2 is connected to the gamma processing unit 3 via a switch circuit 40f, and when the switch circuit 40f is on (conductive state), a power supply voltage is applied to the gamma processing unit 3, and when the switch circuit 40f is off (non-conductive state), no power supply voltage is applied. Furthermore, the power supply line VDD2 is connected to the power supply processing unit 4 via a switch circuit 40g, and when the switch circuit 40g is on (conductive state), a power supply voltage is applied to the power supply processing unit 4, and when the switch circuit 40g is off (non-conductive state), no power supply voltage is applied. The switch circuits 40d to 40g are similar to the switch circuits 40a to 40c described above.

[0053] As a result, the display device 1 shown in FIG. 9 achieves the same effects as the first embodiment, and can also reduce leakage power by cutting off power in the analog blocks of the gamma processing unit 3, power supply processing unit 4, horizontal analog unit 9, and vertical analog unit 11 during standby or when operation is not required.

[0054] 4. Third Embodiment In the first embodiment described above, the switch circuits 40a to 40c are arranged on the power supply line VDD1 side, i.e., on the power supply side. However, the switch circuits 40a to 40c may be arranged on the power supply line VSSD side, i.e., on the GND side.

[0055] FIG. 10 is a diagram illustrating the layout of switch circuits 40a to 40c in this embodiment. As shown in FIG. 10, switch circuits 40a to 40c may be provided between a circuit block (represented as a power cutoff circuit block in the figure) subject to power control and a power line VSSD. That is, the power line VSSD may be connected to the signal processing unit 23 via switch circuit 40a, to the horizontal logic unit 8 via switch circuit 40b, and to the vertical logic unit 10 via switch circuit 40c. This creates a virtual VSS between the power line VSSD and each circuit block subject to power control. In this way, if switch circuits 40a to 40c are footer-type switches capable of cutting off connection to the power line VSSD on the ground side (low potential side) of the power path, they are compatible with a triple-well structure of a P-type semiconductor substrate (PSUB) as shown in the figure. Therefore, in the case of the switch circuits 40a to 40c, for example, as shown in the figure, the substrate can be made to have a triple-well structure of PSUB, and the switch circuits 40a to 40c can be configured with N-type transistors, thereby improving manufacturing efficiency. In this way, the switch circuits 40a to 40c can be used as either a header type or a footer type depending on the layout structure.

[0056] 5. Fourth Embodiment In the first embodiment described above, the switch circuits 40 a to 40 c that cut off the power supplied to each power control target block during standby are provided in the internal power supply path of the display device 1. However, this power cut-off may also be performed on the external power supply side of the display device 1.

[0057] Fig. 11 shows a configuration example of a display device 1 according to a fourth embodiment of the present technology. Note that Fig. 11 describes a power supply circuit for the power gating compatible logic 23a of the signal processing unit 23 and the always-on logic 24a of the register 24, but other circuit blocks have similar configurations.

[0058] The external power supply (external VDD1 power supply) 60 is an external power supply for the display device 1 connected to the input / output unit 2 (not shown in FIG. 11 ). The external power supply 60 supplies power to the always-on logic 24a of the register 24 via the input / output unit 2 through the always-on power line VDD1. The external power supply 60 is connected to the CLK+EN control unit 21 via the input / output unit 2, and the CLK+EN control unit 21 outputs an XNOSIG_STATE signal to the external power supply 60. This signal output can be performed, for example, by providing a control terminal for controlling the external power supply 60 in the input / output unit 2. The external power supply 60 supplies power to the power gating-compatible logic 23a of the signal processing unit 23 through the power supply control power line VDD1 in response to the XNOSIG_STATE signal. For example, when the XNOSIG_STATE signal is at a high level, power is supplied to the power gating compatible logic 23a (power on), and when it is at a low level, power to the power gating compatible logic 23a is cut off (power off).

[0059] In this way, the same effects as those of the first embodiment can be achieved even with a configuration in which power is controlled by the external power supply 60 of the display device 1. Furthermore, by performing substantial power control on the external power supply 60 side, the power control circuit on the display device 1 side can be simplified.

[0060] 6. Fifth Embodiment In the above-described fourth embodiment, power supply control is performed by an external power supply of the display device 1, but power supply control may also be performed by an internal power supply of the display device 1.

[0061] Fig. 12 shows a configuration example of a display device 1 according to a fifth embodiment of the present technology. Note that Fig. 12 describes a power supply circuit for the power gating compatible logic 23a of the signal processing unit 23 and the always-on logic 24a of the register 24, but other circuit blocks have similar configurations.

[0062] The internal power supply (internally generated VDD1 power supply) 70 is a chip internal power supply (power supply block) provided inside the display device 1. The internal power supply 70 supplies power to the always-on logic 24a of the register 24 via the always-on power supply line VDD1. The internal power supply 70 is connected to the CLK+EN control unit 21, which outputs an XNOSIG_STATE signal to the internal power supply 70. In response to this XNOSIG_STATE signal, the internal power supply 70 supplies power to the power gating compatible logic 23a of the signal processing unit 23 via the power supply control power line VDD1. For example, when the XNOSIG_STATE signal is at a high level, power is supplied to the power gating compatible logic 23a (power on), and when the XNOSIG_STATE signal is at a low level, power to the power gating compatible logic 23a is cut off (power off).

[0063] In this way, even with a configuration in which power is controlled by the internal power supply 70 of the display device 1, it is possible to achieve the same effects as in the first embodiment. Furthermore, by performing substantial power control by the internal power supply 70, it is possible to simplify the power control circuit of the display device 1. Furthermore, the control terminals that were required when power was controlled by the external power supply 60 are no longer necessary.

[0064] 7. Sixth Embodiment Fig. 13 is a diagram for explaining a configuration for dissipating leakage current between pixels. Fig. 13A shows a plan view of a pixel, and Fig. 13B shows an example of a configuration for dissipating leakage current between pixels. In Figs. 13A and 13B, "R" denotes a pixel from which red wavelength light is obtained, "G" denotes a pixel from which green wavelength light is obtained, and "B" denotes a pixel from which blue wavelength light is obtained. An insulating film 80 is provided between each pixel. The insulating film 80 is made of an insulator such as silicon oxide (SiOx).

[0065] 13B , by providing inter-pixel insulating film node wiring and applying a negative power supply (pixel isolation power supply) via the power supply line VISO to the insulating film 80, it is possible to allow leakage current between adjacent pixels to escape to the electrode side and prevent leakage current from flowing into the pixel. This technology can be applied not only to circuit blocks that drive circuits, but also to circuit blocks such as shields for ensuring characteristics.

[0066] FIG. 14 is a diagram illustrating a configuration example of a display device 1 according to a sixth embodiment of the present technology. The display device 1 of this embodiment includes a switch circuit 81 provided between an insulating film 80 between pixels in the pixel section 7 and a power line VSIO to form a virtual VISO. The switch circuit 81 can cut off power in response to an ISOEN signal serving as an enable signal. The switch circuit 81 corresponds to the switch circuits 40a to 40c in the first embodiment, and the ISOEN signal corresponds to the XNOSIG_STATE signal in the first embodiment. That is, in this embodiment, a circuit block that applies an insulation voltage to the insulating film 80 that insulates pixels is used as the first circuit block to control the power supply. The switch circuit 81 is controlled to be on when contrast needs to be increased (e.g., when light emission is not desired, such as in black display) in response to the ISOEN signal, and is controlled to be off during standby or when increased contrast is not required. This display device 1 can also reduce standby power consumption.

[0067] 8. Seventh Embodiment) In the first embodiment described above, it is assumed that the switch circuits 40a to 40c are formed on a silicon (Si) substrate, but the substrate on which the switch circuits 40a to 40c are formed is not limited to a silicon (Si) substrate.

[0068] Fig. 15 is a conceptual diagram illustrating an example of the configuration of a substrate to which the present technology can be applied. The substrate P shown in the lower part of Fig. 15 has a structure in which an oxide semiconductor is stacked on a silicon (Si) substrate. The silicon substrate includes, for example, amorphous silicon or polycrystalline silicon. The oxide semiconductor includes, for example, indium gallium zinc oxide (IGZO) and forms a TFT (Thin Film Transistor) layer.

[0069] Pixel transistors are formed in the pixel regions of the oxide semiconductor layer. The area other than the pixel regions of the oxide semiconductor layer is a dummy area in which dummy patterns are formed. High-voltage transistors are formed in the pixel regions of the silicon substrate, and low-voltage transistors are formed in the area other than the pixel regions as a logic area. The logic area is, for example, an area where logic blocks driven by a power supply voltage for digital circuits are arranged. The present technology can also be applied to, for example, a display device having a substrate P with such a structure.

[0070] FIG. 16 is a diagram illustrating a configuration example of a display device 1 according to a seventh embodiment of the present technology. The display device 1 illustrated in FIG. 16 includes the footer-type switch circuits 40a-40c (see FIG. 10) described in the third embodiment. In this display device 1, the switch circuits 40a-40c, which are power gating switches, are formed using oxide semiconductor transistors, specifically TFTs, in the dummy region of the substrate P described above, i.e., in the oxide semiconductor layer in the portion overlapping with the logic region. This achieves the same effects as the first embodiment described above, while also reducing leakage current due to the oxide semiconductor, contributing to process planarization and improved process characteristics. The switch circuits 40a-40c may also be formed in an empty region of the pixel region in the oxide semiconductor layer.

[0071] 9. Configuration Examples of Pixel Circuits Below, we will explain configuration examples of pixels (pixel circuits) included in the pixel section 7 of the display device 1. Note that the following configuration examples are merely illustrative and do not exclude other configurations.

[0072] (First Configuration Example) Figure 17 shows an example of the configuration of pixel PIX. Pixel PIX has a capacitor C01, transistors MN02 and MN03, and a light-emitting element EL. Transistors MN02 and MN03 are N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The gate of transistor MN02 is connected to a control line WSL, its drain is connected to a signal line SGL, and its source is connected to the gate of transistor MN03 and capacitor C01. One end of capacitor C01 is connected to the source of transistor MN02 and the gate of transistor MN03, and the other end is connected to the source of transistor MN03 and the anode of light-emitting element EL. The gate of transistor MN03 is connected to the source of transistor MN02 and one end of capacitor C01, its drain is connected to the power supply line VCCP, and its source is connected to the other end of capacitor C01 and the anode of light-emitting element EL. The anode of the light-emitting element EL is connected to the source of the transistor MN03 and the other end of the capacitor C01, and the cathode is connected to the power supply line Vcath. The voltage of the power supply line VCCP is appropriately switched between a first voltage and a second voltage lower than the first voltage.

[0073] With this configuration, in pixel PIX, when transistor MN02 is turned on, the voltage across capacitor C01 is set based on the pixel signal supplied from signal line SGL. During a period when the voltage of power supply line VCCP is at a first voltage, transistor MN03 passes a current corresponding to the voltage across capacitor C01 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN03. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. During a period when the voltage of power supply line VCCP is at a second voltage, light-emitting element EL is turned off.

[0074] (Second Configuration Example) Figure 18 shows another configuration example of pixel PIX. This pixel PIX has capacitors C11 and C12, transistors MP12 to MP15, and a light-emitting element EL. Transistors MP12 to MP15 are P-type MOSFETs. The gate of transistor MP12 is connected to a control line WSL, the source is connected to a signal line SGL, and the drain is connected to the gate of transistor MP14 and capacitor C12. One end of capacitor C11 is connected to a power supply line VCCP, and the other end is connected to capacitor C12, the drain of transistor MP13, and the source of transistor MP14. One end of capacitor C12 is connected to the other end of capacitor C11, the drain of transistor MP13, and the source of transistor MP14, and the other end is connected to the drain of transistor MP12 and the gate of transistor MP14. The gate of transistor MP13 is connected to the control line DSL, the source is connected to the power supply line VCCP, and the drain is connected to the source of transistor MP14, the other end of capacitor C11, and one end of capacitor C12. The gate of transistor MP14 is connected to the drain of transistor MP12 and the other end of capacitor C12, the source is connected to the drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12, and the drain is connected to the anode of the light-emitting element EL and the source of transistor MP15. The gate of transistor MP15 is connected to the control line AZSL, the source is connected to the drain of transistor MP14 and the anode of the light-emitting element EL, and the drain is connected to the power supply line VSS. The anode of the light-emitting element EL is connected to the drain of transistor MP14 and the source of transistor MP15, and the cathode is connected to the power supply line Vcath.

[0075] With this configuration, in pixel PIX, when transistor MP12 is turned on, the voltage across capacitor C12 is set based on the pixel signal supplied from signal line SGL. Transistor MP13 is turned on and off based on the signal on control line DSL. While transistor MP13 is on, transistor MP14 passes a current corresponding to the voltage across capacitor C12 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP14. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP15 is turned on and off based on the signal on control line AZSL. While transistor MP15 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0076] The transistors MP12 to MP15 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP12 and MP15 may be a transistor using an oxide semiconductor.

[0077] (Third Configuration Example) Figure 19 shows another configuration example of pixel PIX. This pixel PIX has a capacitor C21, transistors MN22 to MN25, and a light-emitting element EL. Transistors MN22 to MN25 are N-type MOSFETs. The gate of transistor MN22 is connected to a control line WSL, the drain is connected to a signal line SGL, and the source is connected to the gate of transistor MN24 and capacitor C21. One end of capacitor C21 is connected to the source of transistor MN22 and the gate of transistor MN24, and the other end is connected to the source of transistor MN24, the drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN23 is connected to a control line DSL, the drain is connected to a power supply line VCCP, and the source is connected to the drain of transistor MN24. The gate of transistor MN24 is connected to the source of transistor MN22 and one end of capacitor C21, the drain is connected to the source of transistor MN23, the source is connected to the other end of capacitor C21, the drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN25 is connected to control line AZSL, the drain is connected to the source of transistor MN24, the other end of capacitor C21, and the anode of light-emitting element EL, and the source is connected to power supply line VSS. The anode of light-emitting element EL is connected to the source of transistor MN24, the drain of transistor MN25, and the other end of capacitor C21, and the cathode is connected to power supply line Vcath.

[0078] With this configuration, in pixel PIX, when transistor MN22 is turned on, the voltage across capacitor C21 is set based on the pixel signal supplied from signal line SGL. Transistor MN23 is turned on and off based on the signal on control line DSL. While transistor MN23 is on, transistor MN24 passes a current corresponding to the voltage across capacitor C21 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MN24. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN25 is turned on and off based on the signal on control line AZSL. While transistor MN25 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0079] The transistors MN22 to MN25 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MN22 and MN25 may be a transistor using an oxide semiconductor.

[0080] (Fourth Configuration Example) Figure 20 shows another configuration example of pixel PIX. This pixel PIX has a capacitor C31, transistors MP32 to MP36, and a light-emitting element EL. Transistors MP32 to MP36 are P-type MOSFETs. The gate of transistor MP32 is connected to a control line WSL, its source is connected to a signal line SGL, and its drain is connected to the gate of transistor MP33, the drain of transistor MP34, and capacitor C31. One end of capacitor C31 is connected to a power supply line VCCP, and the other end is connected to the drain of transistor MP32, the gate of transistor MP33, and the drain of transistor MP34. The gate of transistor MP33 is connected to the drain of transistor MP32, the drain of transistor MP34, and the other end of capacitor C31, its source is connected to the power supply line VCCP, and its drain is connected to the sources of transistor MP34 and transistor MP35. The gate of transistor MP34 is connected to control line AZSL1, its source is connected to the drain of transistor MP33 and the source of transistor MP35, and its drain is connected to the drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31. The gate of transistor MP35 is connected to control line DSL, its source is connected to the drain of transistor MP33 and the source of transistor MP34, and its drain is connected to the source of transistor MP36 and the anode of light-emitting element EL. The gate of transistor MP36 is connected to control line AZSL2, its source is connected to the drain of transistor MP35 and the anode of light-emitting element EL, and its drain is connected to power supply line VSS. The anode of light-emitting element EL is connected to the drain of transistor MP35 and the source of transistor MP36, and its cathode is connected to power supply line Vcath.

[0081] With this configuration, in pixel PIX, when transistor MP32 is turned on, the voltage across capacitor C31 is set based on the pixel signal supplied from signal line SGL. Transistor MP35 is turned on and off based on the signal on control line DSL. While transistor MP35 is on, transistor MP33 passes a current corresponding to the voltage across capacitor C31 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP33. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP34 is turned on and off based on the signal on control line AZSL1. While transistor MP34 is on, the drain and gate of transistor MP33 are connected to each other. Transistor MP36 is turned on and off based on the signal on control line AZSL2. While transistor MP36 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0082] The transistors MP32 to MP36 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP32, MP34, and MP36 may be a transistor using an oxide semiconductor.

[0083] 21 shows another example of the configuration of pixel PIX. One end of capacitor C48 is connected to signal line SGL1, and the other end is connected to power supply line VSS. One end of capacitor C49 is connected to signal line SGL1, and the other end is connected to signal line SGL2. Transistor MP49 is a P-type MOSFET, and its gate is connected to control line WSL2, its source is connected to signal line SGL1, and its drain is connected to signal line SGL2.

[0084] The pixel PIX includes a capacitor C41, transistors MP42 to MP46, and a light-emitting element EL. Transistors MP42 to MP46 are P-type MOSFETs. The gate of transistor MP42 is connected to a control line WSL1, its source is connected to a signal line SGL2, and its drain is connected to the gate of transistor MP43 and capacitor C41. One end of capacitor C41 is connected to a power supply line VCCP, and the other end is connected to the drain of transistor MP42 and the gate of transistor MP43. The gate of transistor MP43 is connected to the drain of transistor MP42 and the other end of capacitor C41, its source is connected to the power supply line VCCP, and its drain is connected to the sources of transistors MP44 and MP45. The gate of transistor MP44 is connected to a control line AZSL1, its source is connected to the drain of transistor MP43 and the source of transistor MP45, and its drain is connected to signal line SGL2. The gate of transistor MP45 is connected to the control line DSL, the source is connected to the drain of transistor MP43 and the source of transistor MP44, and the drain is connected to the source of transistor MP46 and the anode of light-emitting element EL. The gate of transistor MP46 is connected to control line AZSL2, the source is connected to the drain of transistor MP45 and the anode of light-emitting element EL, and the drain is connected to power supply line VSS. The anode of light-emitting element EL is connected to the drain of transistor MP45 and the source of transistor MP46, and the cathode is connected to power supply line Vcath.

[0085] With this configuration, in pixel PIX, when transistor MP42 is turned on, the voltage across capacitor C41 is set based on the pixel signal supplied from signal line SGL1 via capacitor C49. Transistor MP45 is turned on and off based on the signal on control line DSL. While transistor MP45 is on, transistor MP43 passes a current corresponding to the voltage across capacitor C41 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP43. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP44 is turned on and off based on the signal on control line AZSL1. While transistor MP44 is on, the drain of transistor MP43 and signal line SGL2 are connected to each other. Transistor MP46 is turned on and off based on the signal on control line AZSL2. While transistor MP46 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0086] The transistors MP42 to MP46 and MP49 may be transistors using low temperature polysilicon (LTPS). At least one of the transistors MP42, MP46 and MP49 may be a transistor using an oxide semiconductor.

[0087] 22 shows another example of the configuration of the pixel PIX. A plurality of pixels PIX are arranged in a matrix in a display area 100, and the display area 100 is provided between a first control unit 91 and a second control unit 92.

[0088] The first control unit 91 includes transmission gates TG45 and TG46, transistors MP50 and MP51, and a capacitor C50. The transistors MP50 and MP51 are P-type MOSFETs. A pixel signal is supplied to the input terminal of the transmission gate TG45, and the output terminal of the transmission gate TG45 is connected to one end of a signal line 93a. The input terminal of the transmission gate TG46 is connected to a signal line 93b, and the output terminal of the transmission gate TG46 is connected to a power supply line Vorst. One end of the capacitor C50 is connected to the signal line 93a, and the other end is connected to a power supply line VSS1. The gate of the transistor MP50 is connected to a control line INIL, the source is connected to a power supply line Vini, and the drain is connected to a signal line 93b. The gate of the transistor MP51 is connected to a control line ELL, the source is connected to a power supply line Vel, and the drain is connected to a signal line 93b.

[0089] The second control unit 92 has a transmission gate TG72, a transistor MP73, and a capacitor C82. The transistor MP73 is a P-type MOSFET. The input terminal of the transmission gate TG72 is connected to the other end of the signal line 93a, and the output terminal is connected to the drain of the transistor MP73 and one end of the capacitor C82. The gate of the transistor MP73 is connected to the control line REFL, the source is connected to the power supply line Vref, and the drain is connected to the output terminal of the transmission gate TG72 and one end of the capacitor C82. One end of the capacitor C82 is connected to the output terminal of the transmission gate TG72 and the drain of the transistor MP73, and the other end is connected to one end of the signal line 93b.

[0090] The pixel PIX includes a capacitor C132, transistors MP121 to MP125, and a light-emitting element EL. Transistors MP121 to MP125 are P-type MOSFETs. The gate of transistor MP122 is connected to a control line WSL, its source is connected to a signal line 93b, and its drain is connected to the gate of transistor MP121 and capacitor C132. One end of capacitor C132 is connected to a power supply line Vel, and the other end is connected to the drain of transistor MP122 and the gate of transistor MP121. The gate of transistor MP121 is connected to the drain of transistor MP122 and the other end of capacitor C132, its source is connected to the power supply line Vel, and its drain is connected to the sources of transistors MP123 and MP124. The gate of transistor MP123 is connected to a control line AZSL, its source is connected to the drain of transistor MP121 and the source of transistor MP124, and its drain is connected to signal line 93b. The gate of transistor MP124 is connected to the control line DSL, the source is connected to the drain of transistor MP121 and the source of transistor MP123, and the drain is connected to the drain of transistor MP125 and the anode of the light-emitting element EL. The gate of transistor MP125 is connected to the control line AZSL, the source is connected to the power supply line Vorst, and the drain is connected to the drain of transistor MP124 and the anode of the light-emitting element EL. The anode of the light-emitting element EL is connected to the drains of transistor MP124 and transistor MP125, and the cathode is connected to the power supply line Vcath.

[0091] With this configuration, in pixel PIX, when transistor MP122 is turned on, the voltage across capacitor C132 is set based on the pixel signal supplied via transmission gate TG45, signal line 93a, transmission gate TG72, capacitor C82, and signal line 93b. Transistor MP124 is turned on and off based on the signal on control line DSL. While transistor MP124 is on, transistor MP121 passes a current corresponding to the voltage across capacitor C132 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP121. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistors MP123 and MP125 are turned on and off based on the signal on control line AZSL. While transistor MP123 is on, the drain of transistor MP121 and the source of transistor MP124 are connected to signal line 93b. During the period when transistor MP125 is in the ON state, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line Vorst. Furthermore, transistor MP50 is turned on and off based on the signal on control line INIL, transistor MP51 is turned on and off based on the signal on control line ELL, and transistor MP73 is turned on and off based on the signal on control line REFL. When transistor MP50 is in the ON state, signal line 93b is set to the voltage of power supply line Vini, and when transistor MP51 is in the ON state, signal line 93b is set to the voltage of power supply line Vel. When transistor MP73 is in the ON state, one end of capacitor C82 is initialized by being set to the voltage of power supply line Vref.

[0092] The transistors MP121 to MP125, MP50, and MP51 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP122 and MP125 may be a transistor using an oxide semiconductor.

[0093] (Seventh Configuration Example) Figure 23 shows another configuration example of pixel PIX. This pixel PIX has a capacitor C51, transistors MP52 to MP60, and a light-emitting element EL. Transistors MP52 to MP60 are P-type MOSFETs. The gate of transistor MP52 is connected to a control line WSL, its source is connected to a signal line SGL, and its drain is connected to the drain of transistor MP53 and the source of transistor MP54. The gate of transistor MP53 is connected to a control line DSL, its source is connected to a power supply line VCCP, and its drain is connected to the drain of transistor MP52 and the source of transistor MP54. The gate of transistor MP54 is connected to the source of transistor MP55, the drain of transistor MP57, and capacitor C51, its source is connected to the drains of transistors MP52 and MP53, and its drain is connected to the sources of transistors MP58 and MP59. One end of capacitor C51 is connected to the power supply line VCCP, and the other end is connected to the gate of transistor MP54, the source of transistor MP55, and the drain of transistor MP57. Capacitor C51 may include two capacitors connected in parallel. Transistor MP55 has a gate connected to control line AZSL1, a source connected to the gate of transistor MP54, the drain of transistor MP57, and the other end of capacitor C51, and a drain connected to the source of transistor MP56. Transistor MP56 has a gate connected to control line AZSL1, a source connected to the drain of transistor MP55, and a drain connected to power supply line VSS. Transistor MP57 has a gate connected to control line WSL, a drain connected to the gate of transistor MP54, the source of transistor MP55, and the other end of capacitor C51, and a source connected to the drain of transistor MP58. The gate of the transistor MP58 is connected to the control line WSL, the drain is connected to the source of the transistor MP57, and the source is connected to the drain of the transistor MP54 and the source of the transistor MP59.The gate of transistor MP59 is connected to the control line DSL, the source is connected to the drain of transistor MP54 and the source of transistor MP58, and the drain is connected to the source of transistor MP60 and the anode of light-emitting element EL. The gate of transistor MP60 is connected to control line AZSL2, the source is connected to the drain of transistor MP59 and the anode of light-emitting element EL, and the drain is connected to the power supply line VSS. The anode of light-emitting element EL is connected to the drain of transistor MP59 and the source of transistor MP60, and the cathode is connected to the power supply line Vcath.

[0094] With this configuration, in pixel PIX, transistors MP52, MP54, MP58, and MP57 are turned on, and the voltage across capacitor C51 is set based on the pixel signal supplied from signal line SGL. Transistors MP53 and MP59 are turned on and off based on the signal on control line DSL. While transistors MP53 and MP59 are on, transistor MP54 passes a current corresponding to the voltage across capacitor C51 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP54. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistors MP55 and MP56 are turned on and off based on the signal on control line AZSL1. While transistors MP55 and MP56 are on, the gate voltage of transistor MP54 is initialized by being set to the voltage of power supply line VSS. Transistor MP60 is turned on and off based on the signal on control line AZSL2. During the period in which the transistor MP60 is in the on state, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0095] The transistors MP52 to MP60 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP55 to MP58 and MP60 may be a transistor using an oxide semiconductor.

[0096] 24 shows another example of the configuration of the pixel PIX. The signal on the control line WSNL and the signal on the control line WSPL are mutually inverted signals.

[0097] The pixel PIX has capacitors C61 and C62, transistors MN63, MP64, and MN65 to MN67, and a light-emitting element EL. The transistors MN63, MN65 to MN67 are N-type MOSFETs, and the transistor MP64 is a P-type MOSFET. The gate of the transistor MN63 is connected to a control line WSNL, the drain is connected to a signal line SGL and the source of the transistor MP64, and the source is connected to the drain of the transistor MP64, the capacitors C61 and C62, and the gate of the transistor MN65. The gate of the transistor MP64 is connected to a control line WSPL, the source is connected to the signal line SGL and the drain of the transistor MN63, and the drain is connected to the source of the transistor MN63, the capacitors C61 and C62, and the gate of the transistor MN65. The capacitor C61 is configured using, for example, a metal oxide metal (MOM) capacitor, with one end connected to the source of transistor MN63, the drain of transistor MP64, capacitor C62, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C61 may be configured using, for example, a metal oxide metal (MOS) capacitor or a metal insulator metal (MIM) capacitor. The capacitor C62 is configured using, for example, a MOS capacitor, with one end connected to the source of transistor MN63, the drain of transistor MP64, one end of capacitor C61, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C62 may be configured using, for example, a MOM capacitor or a MIM capacitor. The other end of the capacitor C62 may be connected to the power supply line VSS3 (not shown). The gate of transistor MN65 is connected to the source of transistor MN63, the drain of transistor MP64, and one end of capacitors C61 and C62, the drain is connected to the power supply line VCCP, and the source is connected to the drains of transistors MN66 and MN67. The gate of transistor MN66 is connected to control line AZL, the drain is connected to the source of transistor MN65 and the drain of transistor MN67, and the source is connected to power supply line VSS1.The gate of transistor MN67 is connected to the control line DSL, the drain is connected to the source of transistor MN65 and the drain of transistor MN66, and the source is connected to the anode of light-emitting element EL. The anode of light-emitting element EL is connected to the source of transistor MN67, and the cathode is connected to the power supply line Vcath. Note that transistor MN67 and the control line DSL may be omitted, and the source of transistor MN65 may be connected to the drain of transistor MN66 and the anode of light-emitting element EL.

[0098] With this configuration, in pixel PIX, when at least one of transistors MN63 and MP64 is turned on, the voltage across capacitors C61 and C62 is set based on the pixel signal supplied from signal line SGL. Transistor MN67 is turned on and off based on the signal on control line DSL. While transistor MN67 is on, transistor MN65 passes a current corresponding to the voltage across capacitors C61 and C62 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP65. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN66 may be turned on and off based on the signal on control line AZL. Transistor MN66 may also function as a resistor element having a resistance value corresponding to the signal on control line AZL. In this case, transistors MN65 and MN66 form a so-called source follower circuit.

[0099] The transistors MN63, MP64, MN65 to MN67 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MN63, MP64, and MN66 may be a transistor using an oxide semiconductor.

[0100] (Ninth Configuration Example) Figure 25 shows another configuration example of pixel PIX. This pixel PIX has a capacitor C71, transistors MN72 to MN77, and a light-emitting element EL. Transistors MN72 to MN77 are N-type MOSFETs. The gate of transistor MN72 is connected to a control line WSL, the drain is connected to a signal line SGL, and the source is connected to the source of transistor MN74 and the drain of transistor MN75. One end of capacitor C71 is connected to the gate of transistor MN74 and the source of transistor MN76, and the other end is connected to the drain of transistor MN77, the source of transistor MN75, and the anode of light-emitting element EL. The gate of transistor MN73 is connected to control line DSL1, the drain is connected to a power supply line VCCP, and the source is connected to the drain of transistor MN74 and the drain of transistor MN76. The gate of transistor MN74 is connected to the source of transistor MN76 and one end of capacitor C71, the drain is connected to the source of transistor MN73 and the drain of transistor MN76, and the source is connected to the source of transistor MN72 and the drain of transistor MN75. The gate of transistor MN75 is connected to control line DSL2, the drain is connected to the source of transistor MN72 and the source of transistor MN74, and the source is connected to the other end of capacitor C71, the drain of transistor MN77, and the anode of light-emitting element EL. The gate of transistor MN76 is connected to control line AZSL, the drain is connected to the source of transistor MN73 and the drain of transistor MN74, and the source is connected to the gate of transistor MN74 and one end of capacitor C71. The gate of transistor MN77 is connected to control line AZSL, the drain is connected to the other end of capacitor C71, the source of transistor MN75, and the anode of light-emitting element EL, and the source is connected to power supply line VSS. The anode of the light emitting element EL is connected to the source of the transistor MN75, the drain of the transistor MN77 and the other end of the capacitor C71, and the cathode is connected to the power supply line Vcath.

[0101] With this configuration, in pixel PIX, transistors MN72, MN74, and MN76 are turned on, and the voltage across capacitor C71 is set based on the pixel signal supplied from signal line SGL. Transistor MN73 is turned on and off based on the signal on control line DSL1, and transistor MN75 is turned on and off based on the signal on control line DSL2. While transistors MN73 and MN75 are on, transistor MN74 passes a current corresponding to the voltage across capacitor C71 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN74. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN77 is turned on and off based on the signal on control line AZSL. While transistor MN77 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0102] The transistors MN72 to MN77 may be transistors using low temperature polysilicon (LTPS), and the transistor MN76 may be a transistor using an oxide semiconductor.

[0103] <10. Modifications> Although the embodiments of the present technology have been specifically described above, the content of the present technology is not limited to the above-described embodiments, and various modifications based on the technical concept of the present technology are possible. For example, the configurations, methods, processes, materials, shapes, and numerical values ​​of the above-described embodiments can be combined or substituted with each other as long as they do not deviate from the spirit of the present technology. Furthermore, one thing can be divided into two or more parts, and some parts can be omitted. Furthermore, as long as the present technology is applicable, the above-described configurations may be appropriately deleted, modified, or added with other configurations, or may be replaced with alternative configurations. Furthermore, the present technology may be an appropriate combination of the above-described embodiments.

[0104] For example, the circuit blocks to be powered on and the circuit blocks that are always powered on are merely illustrative and can be changed as appropriate depending on the circuit blocks that make up the display device 1. The constituent units of the circuit blocks can also be changed as appropriate. Furthermore, the XNOSIG_STATE signal and ISOEN signal described above are not limited to one type each, and multiple types may be used. This allows for fine-grained power control, such as power control for logic and analog circuits, for each circuit block, or for each display setting mode. Leakage power can be reduced by turning off the power not only during standby but also when various circuit blocks do not need to operate.

[0105] For example, the present technology can be applied to various displays. For example, the present technology can be applied to display panels such as SXRD (Silicon X-tal Reflective Display: registered trademark) used in projectors, etc., and phase modulation panels using SLM (Spatial Light Modulator) for hologram display. Furthermore, the present technology can be applied to panels such as LCOS (Liquid crystal on silicon, LCoS is a trademark) and HTPS (High Temperature Poly-Silicon). The above-mentioned XNOSIG_STATE signal and ISOEN signal may be acquired from the outside via the input / output unit 2.

[0106] 11. Application Examples Next, application examples of the display systems described in the above embodiments and modifications will be described.

[0107] 26 shows an example of the appearance of a head-mounted display 110. The head-mounted display 110 has, for example, ear hooks 112 for wearing on the user's head on both sides of a glasses-shaped display unit 111. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 110.

[0108] (Application Example 2) FIG. 27 shows an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a see-through head-mounted display having a main body 121, an arm 122, and a lens barrel 123. This head-mounted display 120 is attached to eyeglasses 128. The main body 121 has a control board and a display unit for controlling the operation of the head-mounted display 120. The display unit emits image light of a display image. The arm 122 connects the main body 121 to the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light supplied from the main body 121 via the arm 122 toward the user's eyes via lenses 129 of the eyeglasses 128. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 120.

[0109] The head-mounted display 120 is a so-called light guide plate type head-mounted display, but is not limited to this and may be, for example, a so-called birdbath type head-mounted display. The birdbath type head-mounted display includes, for example, a beam splitter and a partially transparent mirror. The beam splitter outputs light encoded with image information toward the mirror, and the mirror reflects the light toward the user's eyes. Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.

[0110] (Application Example 3) Figures 28A and 28B show an example of the appearance of a digital still camera 130, with Figure 28A showing a front view and Figure 28B showing a rear view. This digital still camera 130 is a single-lens reflex camera with interchangeable lenses and includes a camera body 131, a photographing lens unit 132, a grip 133, a monitor 134, and an electronic viewfinder 135. The photographing lens unit 132 is an interchangeable lens unit and is provided near the center of the front of the camera body 131. The grip 133 is provided on the left side of the front of the camera body 131, and is held by the photographer. The monitor 134 is provided to the left of the center of the back of the camera body 131. The electronic viewfinder 135 is provided above the monitor 134 on the back of the camera body 131. By looking through this electronic viewfinder 135, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 132 and determine the composition. The techniques according to the above-described embodiments and the like can be applied to the electronic viewfinder 135.

[0111] 29 shows an example of the appearance of a television device 140. The television device 140 has an image display screen unit 141 including a front panel 142 and a filter glass 143. The techniques according to the above-described embodiments and the like can be applied to this image display screen unit 141.

[0112] 30 shows an example of the appearance of a smartphone 150. The smartphone 150 has a display unit 151 that displays various information and an operation unit 152 that includes buttons and the like that accept operation inputs from a user. The techniques according to the above-described embodiments and the like can be applied to this display unit 151.

[0113] (Application Example 6) Figures 31A and 31B show an example configuration of a vehicle to which the technology of the present disclosure is applied, where Figure 31A shows an example of the interior of the vehicle as seen from the rear of vehicle 200, and Figure 31B shows an example of the interior of the vehicle as seen from the left rear of vehicle 200.

[0114] The vehicle in Figures 31A and 31B has a center display 201, a console display 202, a head-up display 203, a digital rearview mirror 204, a steering wheel display 205, and a rear entertainment display 206.

[0115] The center display 201 is disposed on the dashboard 261 in a position facing the driver's seat 262 and the passenger's seat 263. FIG. 31A illustrates an example of a horizontally elongated center display 201 extending from the driver's seat 262 to the passenger's seat 263, but the screen size and location of the center display 201 are not limited to this. The center display 201 can display information detected by various sensors. As a specific example, the center display 201 can display an image captured by an image sensor, a distance image to obstacles in front of or to the side of the vehicle measured by a ToF sensor, and the body temperature of an occupant detected by an infrared sensor. The center display 201 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information.

[0116] The safety-related information includes information based on sensor detection results, such as detection of drowsiness, distraction, child mischief, whether a seatbelt is fastened, and whether a passenger is abandoned. The operation-related information includes gesture information related to passenger operations detected by sensors. The gestures may include operations of various vehicle equipment, such as air conditioning, navigation, audiovisual (AV) equipment, and lighting. The life log includes life logs of all passengers. For example, the life log includes a record of each passenger's behavior. By acquiring and storing the life log, it is possible to determine the condition of the passengers at the time of an accident. The health-related information includes the passenger's body temperature detected using a temperature sensor and information on the passenger's health condition estimated based on the detected body temperature. Alternatively, the passenger's health condition information may be estimated based on the passenger's face captured by an image sensor. Furthermore, the passenger's health condition information may be estimated based on the passenger's responses obtained through an automated voice conversation with the passenger. The authentication / identification-related information includes information on a keyless entry function that uses a sensor to perform facial authentication, a function that automatically adjusts the seat height and position by facial recognition, etc. The entertainment-related information includes information on AV device operations by occupants detected by the sensor, and information on content to be displayed that is appropriate for the occupants detected and recognized by the sensor.

[0117] The console display 202 can be used to display, for example, life log information. The console display 202 is disposed near a shift lever 265 on a center console 264 between a driver's seat 262 and a passenger seat 263. The console display 202 can also display information detected by various sensors. The console display 202 may also display an image of the vehicle's surroundings captured by an image sensor, or an image showing the distance to an obstacle around the vehicle.

[0118] The head-up display 203 is virtually displayed behind a windshield 266 in front of the driver's seat 262. The head-up display 203 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. Since the head-up display 203 is often virtually disposed in front of the driver's seat 262, it is suitable for displaying information directly related to vehicle operation, such as the vehicle speed, the remaining fuel level, and the remaining battery level.

[0119] The digital rearview mirror 204 can not only display the rear of the vehicle, but also display the state of passengers in the rear seats, and can therefore be used to display life log information of passengers in the rear seats, for example.

[0120] The steering wheel display 205 is disposed near the center of the vehicle's steering wheel 267. The steering wheel display 205 can be used to display at least one of, for example, safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 205 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information related to the operation of AV equipment, air conditioning equipment, etc.

[0121] The rear entertainment display 206 is attached to the rear side of the driver's seat 262 and the passenger seat 263 and is intended for viewing by rear seat passengers. The rear entertainment display 206 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, since the rear entertainment display 206 is located in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 206. The rear entertainment display 206 may display, for example, information related to the operation of an AV device or an air conditioning system, or may display the results of measurement of the body temperature of the rear seat passengers using a temperature sensor.

[0122] The techniques according to the above-described embodiments can be applied to the center display 201, console display 202, head-up display 203, digital rearview mirror 204, steering wheel display 205, and rear entertainment display 206.

[0123] The present technology may also be configured as follows. (1) A display device including a plurality of circuit blocks that operate during display operation, wherein the plurality of circuit blocks includes a first circuit block whose power supply is controlled to be turned off during standby. (2) The display device according to (1), including: a switch provided between a power line of the power supply and the first circuit block; and a switch control unit that controls the switch to be off during standby and when operation of the first circuit block is not required. (3) The display device according to (2), including: a plurality of the switches; and a delay circuit that turns on the plurality of switches in a stepwise manner. (4) The display device according to (3), wherein the delay circuit is configured with a buffer. (5) The display device according to (3), wherein the delay circuit is configured with a flip-flop. (6) The display device according to any of (1) to (5), wherein the plurality of circuit blocks includes a second circuit block that operates during standby, and wherein a control circuit that controls an output signal of the first circuit block during standby is provided in a signal transmission path from the first circuit block to the second circuit block. (7) The display device according to (6), wherein the control circuit is configured with a logic gate. (8) The display device according to (6), wherein the control circuit is configured with a flip-flop. (9) The display device according to any one of (1), (6) to (9), further comprising a power supply path for supplying power from an external power supply to the first circuit block, wherein the external power supply turns off the power supply during the standby state and when the operation of the first circuit block is not required. (10) The display device according to any one of (1), (6) to (9), further comprising an internal power supply for supplying the power supply to the first circuit block, wherein the internal power supply turns off the power supply during the standby state and when the operation of the first circuit block is not required. (11) The display device according to any one of (1) to (10), further comprising a plurality of pixels each having a light-emitting element, wherein the first circuit block includes a logic unit that drives the pixels or a signal processing unit that performs signal processing on image data output to the logic unit.(12) The display device according to any one of (2) to (8) and (11), wherein the power supply line is a power supply line on a high potential side in a power supply path of the power supply. (13) The display device according to any one of (2) to (8) and (11), wherein the power supply line is a power supply line on a low potential side in a power supply path of the power supply. (14) The display device according to any one of (2) to (8) and (11) to (13), wherein the display device has a plurality of pixels each having a light-emitting element, and the first circuit block is a circuit block that applies an insulation voltage to an insulator that insulates the pixels from each other. (15) The display device according to any one of (2) to (8) and (11) to (14), wherein the switch is formed using an oxide semiconductor transistor. (16) An electronic device having the display device according to any one of (1) to (15).

[0124] 1 display device, 2 input / output unit, 3 gamma processing unit, 4 power supply processing unit, 5 interface unit, 6 timing controller, 7 pixel unit, 8 horizontal logic unit, 9 horizontal analog unit, 10 vertical logic unit, 11 vertical analog unit, 21 CLK+EN control unit, 22 timing generator, 23 signal processing unit, 24 register, 40a to 40g, 81 switch circuit, 50a to 50d control circuit, 60 external power supply, 70 internal power supply

Claims

1. A display device having a plurality of circuit blocks that operate during display operation, the plurality of circuit blocks including a first circuit block that is controlled to be powered off during standby.

2. The display device according to claim 1, further comprising: a switch provided between the power supply line of the power supply and the first circuit block; and a switch control unit that controls the switch to be turned off during standby and when operation of the first circuit block is not required.

3. The display device according to claim 2, comprising: a plurality of the switches; and a delay circuit that turns on the plurality of the switches in stages.

4. The display device according to claim 3, wherein the delay circuit is configured with a buffer.

5. The display device according to claim 3, wherein the delay circuit is configured with a flip-flop.

6. The display device according to claim 1, wherein the plurality of circuit blocks include a second circuit block that operates during the standby state, and a control circuit that controls the output signal of the first circuit block during the standby state is provided in a signal transmission path from the first circuit block to the second circuit block.

7. The display device according to claim 6, wherein the control circuit is composed of logic gates.

8. The display device according to claim 6, wherein the control circuit is composed of a flip-flop.

9. The display device according to claim 1, further comprising a power supply path for supplying the power from an external power supply to the first circuit block, wherein the external power supply turns off the power supply during the standby state and when the operation of the first circuit block is not required.

10. The display device according to claim 1, further comprising an internal power supply that supplies power to the first circuit block, the internal power supply turning off the power during standby and when the operation of the first circuit block is not required.

11. The display device according to claim 1, comprising a plurality of pixels each having a light-emitting element, wherein the first circuit block includes a logic section that drives the pixels, or a signal processing section that performs signal processing on image data output to the logic section.

12. The display device according to claim 2, wherein the power supply line is a power supply line on the high potential side of the power supply path of the power supply.

13. The display device according to claim 2, wherein the power supply line is a power supply line on the low potential side of the power supply path of the power supply.

14. The display device according to claim 2, comprising a plurality of pixels each having a light-emitting element, wherein the first circuit block is a circuit block that applies an insulating voltage to an insulator that insulates the pixels from one another.

15. The display device according to claim 2, wherein the switch is formed using an oxide semiconductor transistor.

16. An electronic device having the display device according to claim 1.

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